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From: <sv...@va...> - 2014-07-24 22:30:16
|
Author: philippe
Date: Thu Jul 24 22:30:08 2014
New Revision: 14190
Log:
Small follow up to lock address description: now that we describe
lock address, we can print something even if the lock observation
has no stacktrace.
Modified:
trunk/helgrind/hg_errors.c
Modified: trunk/helgrind/hg_errors.c
==============================================================================
--- trunk/helgrind/hg_errors.c (original)
+++ trunk/helgrind/hg_errors.c Thu Jul 24 22:30:08 2014
@@ -764,8 +764,6 @@
if (lk == Lock_INVALID)
return; /* Can't be announced -- we know nothing about it. */
tl_assert(lk->magic == LockP_MAGIC);
- if (!lk->appeared_at)
- return; /* There's nothing we can show */
if (VG_(clo_xml)) {
/* fixme: add announcement */
|
|
From: <sv...@va...> - 2014-07-24 21:15:04
|
Author: florian
Date: Thu Jul 24 21:14:52 2014
New Revision: 14189
Log:
Remove an unneeded function call.
Modified:
trunk/exp-bbv/bbv_main.c
Modified: trunk/exp-bbv/bbv_main.c
==============================================================================
--- trunk/exp-bbv/bbv_main.c (original)
+++ trunk/exp-bbv/bbv_main.c Thu Jul 24 21:14:52 2014
@@ -403,7 +403,6 @@
bbInfo->block_num=block_num;
block_num++;
/* get function name and entry point information */
- VG_(get_fnname)(origAddr,bbInfo->fn_name,FUNCTION_NAME_LENGTH);
bbInfo->is_entry=VG_(get_fnname_if_entry)(origAddr, bbInfo->fn_name,
FUNCTION_NAME_LENGTH);
/* insert structure into table */
|
|
From: <sv...@va...> - 2014-07-24 21:00:37
|
Author: philippe
Date: Thu Jul 24 21:00:24 2014
New Revision: 14188
Log:
Describe the lock address in a lock announcement message.
(note that some error messages are not announcing the lock,
which is not that nice).
At least the lock order violation message do not announce locks.
That should be improved/fixed
Modified:
trunk/NEWS
trunk/helgrind/hg_addrdescr.h
trunk/helgrind/hg_errors.c
trunk/helgrind/tests/annotate_rwlock.stderr.exp
trunk/helgrind/tests/locked_vs_unlocked1_fwd.stderr.exp
trunk/helgrind/tests/locked_vs_unlocked1_rev.stderr.exp
trunk/helgrind/tests/locked_vs_unlocked2.stderr.exp
trunk/helgrind/tests/locked_vs_unlocked3.stderr.exp
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Thu Jul 24 21:00:24 2014
@@ -18,16 +18,18 @@
the block size - 8. This is e.g. used by sqlite3MemMalloc.
* Helgrind:
- - Helgrind GDB server monitor command 'info locks' giving
- the list of locks, their location, and their status.
- Race condition error message with allocated blocks also show
the thread nr that allocated the racy block.
+ - The message indicating where a lock was first observed now also
+ describes the address/location of the lock.
- Helgrind now understands the Ada task termination rules
and creates a 'H-B relationship' between a terminated task and
its master. This avoids some false positive and avoids big
memory usage when a lot of Ada tasks are created and terminated.
The interceptions are only activated with gnatpro >= 7.3.0w-20140611
or gcc >= ????? (TBD: check when changes pushed to FSF gcc).
+ - Helgrind GDB server monitor command 'info locks' giving
+ the list of locks, their location, and their status.
* Callgrind:
- callgrind_control now supports the --vgdb-prefix argument,
Modified: trunk/helgrind/hg_addrdescr.h
==============================================================================
--- trunk/helgrind/hg_addrdescr.h (original)
+++ trunk/helgrind/hg_addrdescr.h Thu Jul 24 21:00:24 2014
@@ -39,12 +39,6 @@
VG_(clear_addrinfo). */
extern void HG_(describe_addr) ( Addr a, /*OUT*/AddrInfo* ai );
-/* Prints (using *print) the readable description of addr given in ai.
- "what" identifies the type pointed to by addr (e.g. a lock). */
-extern void HG_(pp_addrdescr) (Bool xml, const HChar* what, Addr addr,
- AddrInfo* ai,
- void(*print)(const HChar *format, ...));
-
/* Get a readable description of addr, then print it using HG_(pp_addrdescr)
using xml False and VG_(printf) to emit the characters.
Returns True if a description was found/printed, False otherwise. */
Modified: trunk/helgrind/hg_errors.c
==============================================================================
--- trunk/helgrind/hg_errors.c (original)
+++ trunk/helgrind/hg_errors.c Thu Jul 24 21:00:24 2014
@@ -770,9 +770,15 @@
if (VG_(clo_xml)) {
/* fixme: add announcement */
} else {
- VG_(umsg)( "Lock at %p was first observed\n",
- (void*)lk->guestaddr );
- VG_(pp_ExeContext)( lk->appeared_at );
+ if (lk->appeared_at) {
+ VG_(umsg)( "Lock at %p was first observed\n",
+ (void*)lk->guestaddr );
+ VG_(pp_ExeContext)( lk->appeared_at );
+ } else {
+ VG_(umsg)( "Lock at %p : no stacktrace for first observation\n",
+ (void*)lk->guestaddr );
+ }
+ HG_(get_and_pp_addrdescr) (lk->guestaddr);
VG_(umsg)("\n");
}
}
Modified: trunk/helgrind/tests/annotate_rwlock.stderr.exp
==============================================================================
--- trunk/helgrind/tests/annotate_rwlock.stderr.exp (original)
+++ trunk/helgrind/tests/annotate_rwlock.stderr.exp Thu Jul 24 21:00:24 2014
@@ -102,6 +102,7 @@
Lock at 0x........ was first observed
at 0x........: rwlock_init (annotate_rwlock.c:54)
by 0x........: main (annotate_rwlock.c:161)
+ Address 0x........ is 0 bytes inside data symbol "s_rwlock"
Possible data race during write of size 4 at 0x........ by thread #x
Locks held: 1, at address 0x........
Modified: trunk/helgrind/tests/locked_vs_unlocked1_fwd.stderr.exp
==============================================================================
--- trunk/helgrind/tests/locked_vs_unlocked1_fwd.stderr.exp (original)
+++ trunk/helgrind/tests/locked_vs_unlocked1_fwd.stderr.exp Thu Jul 24 21:00:24 2014
@@ -19,6 +19,7 @@
by 0x........: child_fn (locked_vs_unlocked1.c:18)
by 0x........: mythread_wrapper (hg_intercepts.c:...)
...
+ Address 0x........ is 0 bytes inside data symbol "mx"
Possible data race during write of size 4 at 0x........ by thread #x
Locks held: none
Modified: trunk/helgrind/tests/locked_vs_unlocked1_rev.stderr.exp
==============================================================================
--- trunk/helgrind/tests/locked_vs_unlocked1_rev.stderr.exp (original)
+++ trunk/helgrind/tests/locked_vs_unlocked1_rev.stderr.exp Thu Jul 24 21:00:24 2014
@@ -19,6 +19,7 @@
by 0x........: child_fn (locked_vs_unlocked1.c:18)
by 0x........: mythread_wrapper (hg_intercepts.c:...)
...
+ Address 0x........ is 0 bytes inside data symbol "mx"
Possible data race during write of size 4 at 0x........ by thread #x
Locks held: 1, at address 0x........
Modified: trunk/helgrind/tests/locked_vs_unlocked2.stderr.exp
==============================================================================
--- trunk/helgrind/tests/locked_vs_unlocked2.stderr.exp (original)
+++ trunk/helgrind/tests/locked_vs_unlocked2.stderr.exp Thu Jul 24 21:00:24 2014
@@ -17,14 +17,17 @@
Lock at 0x........ was first observed
at 0x........: pthread_mutex_init (hg_intercepts.c:...)
by 0x........: main (locked_vs_unlocked2.c:58)
+ Address 0x........ is 0 bytes inside data symbol "mx2a"
Lock at 0x........ was first observed
at 0x........: pthread_mutex_init (hg_intercepts.c:...)
by 0x........: main (locked_vs_unlocked2.c:59)
+ Address 0x........ is 0 bytes inside data symbol "mx2b"
Lock at 0x........ was first observed
at 0x........: pthread_mutex_init (hg_intercepts.c:...)
by 0x........: main (locked_vs_unlocked2.c:57)
+ Address 0x........ is 0 bytes inside data symbol "mx1b"
Possible data race during write of size 4 at 0x........ by thread #x
Locks held: 2, at addresses 0x........ 0x........
Modified: trunk/helgrind/tests/locked_vs_unlocked3.stderr.exp
==============================================================================
--- trunk/helgrind/tests/locked_vs_unlocked3.stderr.exp (original)
+++ trunk/helgrind/tests/locked_vs_unlocked3.stderr.exp Thu Jul 24 21:00:24 2014
@@ -17,6 +17,7 @@
Lock at 0x........ was first observed
at 0x........: pthread_mutex_init (hg_intercepts.c:...)
by 0x........: main (locked_vs_unlocked3.c:51)
+ Address 0x........ is 0 bytes inside data symbol "mx"
Possible data race during write of size 4 at 0x........ by thread #x
Locks held: none
|
|
From: <sv...@va...> - 2014-07-24 19:26:41
|
Author: florian
Date: Thu Jul 24 19:26:32 2014
New Revision: 14187
Log:
Update a comment so it won't need updating in the future.
No functional change.
Modified:
trunk/coregrind/m_demangle/demangle.c
Modified: trunk/coregrind/m_demangle/demangle.c
==============================================================================
--- trunk/coregrind/m_demangle/demangle.c (original)
+++ trunk/coregrind/m_demangle/demangle.c Thu Jul 24 19:26:32 2014
@@ -74,15 +74,12 @@
completely unmodified. We use vg_libciface.h as a way to
impedance-match the libiberty code into our own framework.
- The current code is from libiberty in the gcc tree, gcc svn
- r181975, dated 12 Dec 2011 (when the gcc trunk was in Stage 3
- leading up to a gcc-4.7 release). As of r141363, libiberty is LGPL
- 2.1, which AFAICT is compatible with "GPL 2 or later" and so is OK
- for inclusion in Valgrind.
-
- To update to a newer libiberty, it might be simplest to svn diff
- the gcc tree libibery against r181975 and then apply those diffs
- here. */
+ The libiberty code included here was taken from the GCC repository
+ and is released under the LGPL 2.1 license, which AFAICT is compatible
+ with "GPL 2 or later" and so is OK for inclusion in Valgrind.
+
+ To update to a newer libiberty, use the "update-demangler" script
+ which is included in the valgrind repository. */
/* This is the main, standard demangler entry point. */
|
|
From: Patrick J. L. <lop...@gm...> - 2014-07-24 16:10:58
|
I have opened the following bug report against Helgrind: https://bugs.kde.org/show_bug.cgi?id=337735 A typical use for pthread_once() is one-time initialization of shared data. I am working on an existing code base that uses this idiom widely, but Helgrind incorrectly reports it as a data race. I have attached a simple stand-alone test case to the bug report. It is modeled after the tc21_pthonce test in the Helgrind regression suite. I have also attached my attempt at a patch to fix the bug. The patch fixes my simple test case, but I am not sure what I am doing is valid, and I am fairly certain it is not an approach the Helgrind maintainers would approve. I am willing to do the work to make my patch commit-worthy if the Helgrind maintainers would (a) agree this is a real bug and (b) give me some guidance on the approach I should take. Thanks! - Pat |
|
From: <sv...@va...> - 2014-07-24 12:50:11
|
Author: florian
Date: Thu Jul 24 12:50:03 2014
New Revision: 14186
Log:
Change VG_(strncpy_safely) to use VG_(strncpy) to get the same padding
behaviour.
Modified:
trunk/coregrind/m_debuginfo/debuginfo.c
trunk/coregrind/m_libcbase.c
Modified: trunk/coregrind/m_debuginfo/debuginfo.c
==============================================================================
--- trunk/coregrind/m_debuginfo/debuginfo.c (original)
+++ trunk/coregrind/m_debuginfo/debuginfo.c Thu Jul 24 12:50:03 2014
@@ -1870,7 +1870,6 @@
&& di->text_avma <= a
&& a < di->text_avma + di->text_size) {
VG_(strncpy_safely)(buf, di->fsm.filename, nbuf);
- buf[nbuf-1] = 0;
return True;
}
}
Modified: trunk/coregrind/m_libcbase.c
==============================================================================
--- trunk/coregrind/m_libcbase.c (original)
+++ trunk/coregrind/m_libcbase.c Thu Jul 24 12:50:03 2014
@@ -304,14 +304,8 @@
{
libcbase_assert(ndest > 0);
- SizeT i = 0;
- while (True) {
- dest[i] = 0;
- if (src[i] == 0) return;
- if (i >= ndest-1) return;
- dest[i] = src[i];
- i++;
- }
+ VG_(strncpy)(dest, src, ndest);
+ dest[ndest - 1] = '\0';
}
HChar* VG_(strncpy) ( HChar* dest, const HChar* src, SizeT ndest )
|
Author: florian
Date: Thu Jul 24 12:46:28 2014
New Revision: 14185
Log:
Factor out VG_(exit_now) to contain the syscall incantation to terminate
the process. Make ML_(am_exit) and VG_(exit) use it, thereby avoiding
double maintenance.
Introduce libcbase_assert macro and use it in VG_(strncpy_safely) to
document the case that function cannot handle.
Add stub functions to memcheck/tests/unit_libcbase.c to satisfy new
dependencies.
Modified:
trunk/coregrind/m_aspacemgr/aspacemgr-common.c
trunk/coregrind/m_aspacemgr/priv_aspacemgr.h
trunk/coregrind/m_libcassert.c
trunk/coregrind/m_libcbase.c
trunk/coregrind/pub_core_libcassert.h
trunk/memcheck/tests/unit_libcbase.c
Modified: trunk/coregrind/m_aspacemgr/aspacemgr-common.c
==============================================================================
--- trunk/coregrind/m_aspacemgr/aspacemgr-common.c (original)
+++ trunk/coregrind/m_aspacemgr/aspacemgr-common.c Thu Jul 24 12:46:28 2014
@@ -54,14 +54,7 @@
__attribute__ ((noreturn))
void ML_(am_exit)( Int status )
{
-# if defined(VGO_linux)
- (void)VG_(do_syscall1)(__NR_exit_group, status);
-# endif
- (void)VG_(do_syscall1)(__NR_exit, status);
- /* Why are we still alive here? */
- /*NOTREACHED*/
- *(volatile Int *)0 = 'x';
- aspacem_assert(2+2 == 5);
+ VG_(exit_now) (status);
}
void ML_(am_barf) ( const HChar* what )
Modified: trunk/coregrind/m_aspacemgr/priv_aspacemgr.h
==============================================================================
--- trunk/coregrind/m_aspacemgr/priv_aspacemgr.h (original)
+++ trunk/coregrind/m_aspacemgr/priv_aspacemgr.h Thu Jul 24 12:46:28 2014
@@ -47,6 +47,8 @@
// VG_IS_PAGE_ALIGNED
// VG_PGROUNDDN, VG_PGROUNDUP
+#include "pub_core_libcassert.h" // VG_(exit_now)
+
#include "pub_core_syscall.h" // VG_(do_syscallN)
// VG_(mk_SysRes_Error)
// VG_(mk_SysRes_Success)
Modified: trunk/coregrind/m_libcassert.c
==============================================================================
--- trunk/coregrind/m_libcassert.c (original)
+++ trunk/coregrind/m_libcassert.c Thu Jul 24 12:46:28 2014
@@ -256,6 +256,15 @@
}
exit_called = True;
+ VG_(exit_now) (status);
+}
+
+/* Call the appropriate system call and nothing else. This function should
+ be called in places where the dependencies of VG_(exit) need to be
+ avoided. */
+__attribute__ ((__noreturn__))
+void VG_(exit_now)( Int status )
+{
#if defined(VGO_linux)
(void)VG_(do_syscall1)(__NR_exit_group, status );
#elif defined(VGO_darwin)
Modified: trunk/coregrind/m_libcbase.c
==============================================================================
--- trunk/coregrind/m_libcbase.c (original)
+++ trunk/coregrind/m_libcbase.c Thu Jul 24 12:46:28 2014
@@ -29,8 +29,34 @@
*/
#include "pub_core_basics.h"
+#include "pub_core_libcassert.h" // VG_(exit_now)
+#include "pub_core_debuglog.h" // VG_(debugLog)
#include "pub_core_libcbase.h"
+
+/* ---------------------------------------------------------------------
+ Assert machinery for use in this file. VG_(assert) cannot be called
+ here due to cyclic dependencies.
+ ------------------------------------------------------------------ */
+#define libcbase_assert(expr) \
+ ((void) ((expr) ? 0 : \
+ (ML_(libcbase_assert_fail)(#expr, \
+ __FILE__, __LINE__, \
+ __PRETTY_FUNCTION__))))
+
+static void ML_(libcbase_assert_fail)( const HChar *expr,
+ const HChar *file,
+ Int line,
+ const HChar *fn )
+{
+ VG_(debugLog)(0, "libcbase",
+ "Valgrind: FATAL: assertion failed:\n");
+ VG_(debugLog)(0, "libcbase", " %s\n", expr);
+ VG_(debugLog)(0, "libcbase", " at %s:%d (%s)\n", file, line, fn);
+ VG_(debugLog)(0, "libcbase", "Exiting now.\n");
+ VG_(exit_now)(1);
+}
+
/* ---------------------------------------------------------------------
HChar functions.
------------------------------------------------------------------ */
@@ -276,6 +302,8 @@
zero termination. */
void VG_(strncpy_safely) ( HChar* dest, const HChar* src, SizeT ndest )
{
+ libcbase_assert(ndest > 0);
+
SizeT i = 0;
while (True) {
dest[i] = 0;
Modified: trunk/coregrind/pub_core_libcassert.h
==============================================================================
--- trunk/coregrind/pub_core_libcassert.h (original)
+++ trunk/coregrind/pub_core_libcassert.h Thu Jul 24 12:46:28 2014
@@ -69,6 +69,10 @@
/* Exits with status as client exit code. */
extern void VG_(client_exit)( Int status );
+/* Lightweight exit without any dependencies. */
+__attribute__ ((__noreturn__))
+extern void VG_(exit_now)( Int status );
+
/* Called when some unhandleable client behaviour is detected.
Prints a msg and aborts. */
extern void VG_(unimplemented) ( const HChar* msg )
Modified: trunk/memcheck/tests/unit_libcbase.c
==============================================================================
--- trunk/memcheck/tests/unit_libcbase.c (original)
+++ trunk/memcheck/tests/unit_libcbase.c Thu Jul 24 12:46:28 2014
@@ -3,11 +3,30 @@
#include <assert.h>
#include <stdio.h>
#include <stdlib.h>
+#include <stddef.h>
#include "pub_tool_basics.h" /* UInt et al, needed for pub_tool_vki.h */
#include "pub_tool_vki.h"
#include "m_libcbase.c"
+/* Provide a stub to not have to pull in m_debuglog.c */
+void VG_(debugLog) ( Int level, const HChar* modulename,
+ const HChar* format, ... )
+{
+ va_list args;
+ va_start(args, format);
+ fprintf(stderr, "debuglog: %s: ", modulename);
+ vfprintf(stderr, format, args);
+ va_end(args);
+}
+
+/* Provide a stub to not have to pull in m_libcassert.c */
+void VG_(exit_now)( Int status )
+{
+ exit(status);
+}
+
+
#define CHECK(x) \
if (!x) { fprintf(stderr, "failure: %s:%d\n", __FILE__, __LINE__); }
|
|
From: <sv...@va...> - 2014-07-24 12:45:37
|
Author: sewardj
Date: Thu Jul 24 12:45:24 2014
New Revision: 14184
Log:
Track vex r2910 (infrastructural improvements in representation of
endianness in VEX).
In short: in m_machine.c, VG_(machine_get_hwcaps), get the endianness
of the host, and pass it through to all places (in VEX) where it is
required.
Modified:
trunk/coregrind/m_machine.c
trunk/coregrind/m_main.c
trunk/coregrind/m_translate.c
trunk/coregrind/m_transtab.c
trunk/coregrind/pub_core_transtab.h
Modified: trunk/coregrind/m_machine.c
==============================================================================
--- trunk/coregrind/m_machine.c (original)
+++ trunk/coregrind/m_machine.c Thu Jul 24 12:45:24 2014
@@ -774,6 +774,7 @@
have_mmxext = True;
va = VexArchX86;
+ vai.endness = VexEndnessLE;
if (have_sse2 && have_sse1 && have_mmxext) {
vai.hwcaps = VEX_HWCAPS_X86_MMXEXT;
vai.hwcaps |= VEX_HWCAPS_X86_SSE1;
@@ -891,14 +892,15 @@
have_avx2 = (ebx & (1<<5)) != 0; /* True => have AVX2 */
}
- va = VexArchAMD64;
- vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0)
- | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0)
- | (have_lzcnt ? VEX_HWCAPS_AMD64_LZCNT : 0)
- | (have_avx ? VEX_HWCAPS_AMD64_AVX : 0)
- | (have_bmi ? VEX_HWCAPS_AMD64_BMI : 0)
- | (have_avx2 ? VEX_HWCAPS_AMD64_AVX2 : 0)
- | (have_rdtscp ? VEX_HWCAPS_AMD64_RDTSCP : 0);
+ va = VexArchAMD64;
+ vai.endness = VexEndnessLE;
+ vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0)
+ | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0)
+ | (have_lzcnt ? VEX_HWCAPS_AMD64_LZCNT : 0)
+ | (have_avx ? VEX_HWCAPS_AMD64_AVX : 0)
+ | (have_bmi ? VEX_HWCAPS_AMD64_BMI : 0)
+ | (have_avx2 ? VEX_HWCAPS_AMD64_AVX2 : 0)
+ | (have_rdtscp ? VEX_HWCAPS_AMD64_RDTSCP : 0);
VG_(machine_get_cache_info)(&vai);
@@ -1047,6 +1049,7 @@
VG_(machine_ppc32_has_VMX) = have_V ? 1 : 0;
va = VexArchPPC32;
+ vai.endness = VexEndnessBE;
vai.hwcaps = 0;
if (have_F) vai.hwcaps |= VEX_HWCAPS_PPC32_F;
@@ -1185,6 +1188,9 @@
VG_(machine_ppc64_has_VMX) = have_V ? 1 : 0;
va = VexArchPPC64;
+ // CARLL fixme: when the time comes, copy .endness setting code
+ // from the VGA_mips32 case
+ vai.endness = VexEndnessBE;
vai.hwcaps = 0;
if (have_V) vai.hwcaps |= VEX_HWCAPS_PPC64_V;
@@ -1277,6 +1283,7 @@
r = VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);
vg_assert(r == 0);
va = VexArchS390X;
+ vai.endness = VexEndnessBE;
vai.hwcaps = model;
if (have_STFLE) vai.hwcaps |= VEX_HWCAPS_S390X_STFLE;
@@ -1438,6 +1445,7 @@
VG_(machine_arm_archlevel) = archlevel;
va = VexArchARM;
+ vai.endness = VexEndnessLE;
vai.hwcaps = VEX_ARM_ARCHLEVEL(archlevel);
if (have_VFP3) vai.hwcaps |= VEX_HWCAPS_ARM_VFP3;
@@ -1453,6 +1461,7 @@
#elif defined(VGA_arm64)
{
va = VexArchARM64;
+ vai.endness = VexEndnessLE;
/* So far there are no variants. */
vai.hwcaps = 0;
@@ -1486,6 +1495,14 @@
vai.hwcaps = model;
+# if defined(VKI_LITTLE_ENDIAN)
+ vai.endness = VexEndnessLE;
+# elif defined(VKI_BIG_ENDIAN)
+ vai.endness = VexEndnessBE;
+# else
+ vai.endness = VexEndness_INVALID;
+# endif
+
/* Same instruction set detection algorithm as for ppc32/arm... */
vki_sigset_t saved_set, tmp_set;
vki_sigaction_fromK_t saved_sigill_act;
@@ -1565,11 +1582,19 @@
{
va = VexArchMIPS64;
UInt model = VG_(get_machine_model)();
- if (model== -1)
+ if (model == -1)
return False;
vai.hwcaps = model;
+# if defined(VKI_LITTLE_ENDIAN)
+ vai.endness = VexEndnessLE;
+# elif defined(VKI_BIG_ENDIAN)
+ vai.endness = VexEndnessBE;
+# else
+ vai.endness = VexEndness_INVALID;
+# endif
+
VG_(machine_get_cache_info)(&vai);
return True;
Modified: trunk/coregrind/m_main.c
==============================================================================
--- trunk/coregrind/m_main.c (original)
+++ trunk/coregrind/m_main.c Thu Jul 24 12:45:24 2014
@@ -1377,9 +1377,10 @@
VG_(machine_get_VexArchInfo)( &vex_arch, &vex_archinfo );
VG_(message)(
Vg_DebugMsg,
- "Arch and hwcaps: %s, %s\n",
- LibVEX_ppVexArch ( vex_arch ),
- LibVEX_ppVexHwCaps ( vex_arch, vex_archinfo.hwcaps )
+ "Arch and hwcaps: %s, %s, %s\n",
+ LibVEX_ppVexArch ( vex_arch ),
+ LibVEX_ppVexEndness ( vex_archinfo.endness ),
+ LibVEX_ppVexHwCaps ( vex_arch, vex_archinfo.hwcaps )
);
VG_(message)(
Vg_DebugMsg,
Modified: trunk/coregrind/m_translate.c
==============================================================================
--- trunk/coregrind/m_translate.c (original)
+++ trunk/coregrind/m_translate.c Thu Jul 24 12:45:24 2014
@@ -1650,8 +1650,7 @@
tmpbuf_used,
tres.n_sc_extents > 0,
tres.offs_profInc,
- tres.n_guest_instrs,
- vex_arch );
+ tres.n_guest_instrs );
} else {
vg_assert(tres.offs_profInc == -1); /* -1 == unset */
VG_(add_to_unredir_transtab)( &vge,
Modified: trunk/coregrind/m_transtab.c
==============================================================================
--- trunk/coregrind/m_transtab.c (original)
+++ trunk/coregrind/m_transtab.c Thu Jul 24 12:45:24 2014
@@ -747,8 +747,11 @@
Bool to_fastEP )
{
/* Get the CPU info established at startup. */
- VexArch vex_arch = VexArch_INVALID;
- VG_(machine_get_VexArchInfo)( &vex_arch, NULL );
+ VexArch arch_host = VexArch_INVALID;
+ VexArchInfo archinfo_host;
+ VG_(bzero_inline)(&archinfo_host, sizeof(archinfo_host));
+ VG_(machine_get_VexArchInfo)( &arch_host, &archinfo_host );
+ VexEndness endness_host = archinfo_host.endness;
// host_code is where we're patching to. So it needs to
// take into account, whether we're jumping to the slow
@@ -757,7 +760,8 @@
// the slow (tcptr) entry point.
TTEntry* to_tte = index_tte(to_sNo, to_tteNo);
void* host_code = ((UChar*)to_tte->tcptr)
- + (to_fastEP ? LibVEX_evCheckSzB(vex_arch) : 0);
+ + (to_fastEP ? LibVEX_evCheckSzB(arch_host,
+ endness_host) : 0);
// stay sane -- the patch point (dst) is in this sector's code cache
vg_assert( (UChar*)host_code >= (UChar*)sectors[to_sNo].tc );
@@ -789,7 +793,7 @@
since it is host-dependent. */
VexInvalRange vir
= LibVEX_Chain(
- vex_arch,
+ arch_host, endness_host,
from__patch_addr,
VG_(fnptr_to_fnentry)(
to_fastEP ? &VG_(disp_cp_chain_me_to_fastEP)
@@ -833,7 +837,7 @@
addresses of the destination block (that is, the block that owns
this InEdge). */
__attribute__((noinline))
-static void unchain_one ( VexArch vex_arch,
+static void unchain_one ( VexArch arch_host, VexEndness endness_host,
InEdge* ie,
void* to_fastEPaddr, void* to_slowEPaddr )
{
@@ -858,7 +862,7 @@
// place_to_jump_to_EXPECTED really is the current dst, and
// asserts if it isn't.
VexInvalRange vir
- = LibVEX_UnChain( vex_arch, place_to_patch,
+ = LibVEX_UnChain( arch_host, endness_host, place_to_patch,
place_to_jump_to_EXPECTED, disp_cp_chain_me );
VG_(invalidate_icache)( (void*)vir.start, vir.len );
}
@@ -868,13 +872,14 @@
succs of its associated blocks accordingly. This includes undoing
any chained jumps to this block. */
static
-void unchain_in_preparation_for_deletion ( VexArch vex_arch,
+void unchain_in_preparation_for_deletion ( VexArch arch_host,
+ VexEndness endness_host,
UInt here_sNo, UInt here_tteNo )
{
if (DEBUG_TRANSTAB)
VG_(printf)("QQQ unchain_in_prep %u.%u...\n", here_sNo, here_tteNo);
UWord i, j, n, m;
- Int evCheckSzB = LibVEX_evCheckSzB(vex_arch);
+ Int evCheckSzB = LibVEX_evCheckSzB(arch_host, endness_host);
TTEntry* here_tte = index_tte(here_sNo, here_tteNo);
if (DEBUG_TRANSTAB)
VG_(printf)("... QQQ tt.entry 0x%llu tt.tcptr 0x%p\n",
@@ -888,7 +893,7 @@
// Undo the chaining.
UChar* here_slow_EP = (UChar*)here_tte->tcptr;
UChar* here_fast_EP = here_slow_EP + evCheckSzB;
- unchain_one(vex_arch, ie, here_fast_EP, here_slow_EP);
+ unchain_one(arch_host, endness_host, ie, here_fast_EP, here_slow_EP);
// Find the corresponding entry in the "from" node's out_edges,
// and remove it.
TTEntry* from_tte = index_tte(ie->from_sNo, ie->from_tteNo);
@@ -1427,8 +1432,11 @@
vg_assert(sec->tc_next != NULL);
n_dump_count += sec->tt_n_inuse;
- VexArch vex_arch = VexArch_INVALID;
- VG_(machine_get_VexArchInfo)( &vex_arch, NULL );
+ VexArch arch_host = VexArch_INVALID;
+ VexArchInfo archinfo_host;
+ VG_(bzero_inline)(&archinfo_host, sizeof(archinfo_host));
+ VG_(machine_get_VexArchInfo)( &arch_host, &archinfo_host );
+ VexEndness endness_host = archinfo_host.endness;
/* Visit each just-about-to-be-abandoned translation. */
if (DEBUG_TRANSTAB) VG_(printf)("QQQ unlink-entire-sector: %d START\n",
@@ -1444,7 +1452,8 @@
sec->tt[i].entry,
sec->tt[i].vge );
}
- unchain_in_preparation_for_deletion(vex_arch, sno, i);
+ unchain_in_preparation_for_deletion(arch_host,
+ endness_host, sno, i);
} else {
vg_assert(sec->tt[i].n_tte2ec == 0);
}
@@ -1508,8 +1517,7 @@
UInt code_len,
Bool is_self_checking,
Int offs_profInc,
- UInt n_guest_instrs,
- VexArch arch_host )
+ UInt n_guest_instrs )
{
Int tcAvailQ, reqdQ, y, i;
ULong *tcptr, *tcptr2;
@@ -1627,8 +1635,13 @@
/* Patch in the profile counter location, if necessary. */
if (offs_profInc != -1) {
vg_assert(offs_profInc >= 0 && offs_profInc < code_len);
+ VexArch arch_host = VexArch_INVALID;
+ VexArchInfo archinfo_host;
+ VG_(bzero_inline)(&archinfo_host, sizeof(archinfo_host));
+ VG_(machine_get_VexArchInfo)( &arch_host, &archinfo_host );
+ VexEndness endness_host = archinfo_host.endness;
VexInvalRange vir
- = LibVEX_PatchProfInc( arch_host,
+ = LibVEX_PatchProfInc( arch_host, endness_host,
dstP + offs_profInc,
§ors[y].tt[i].count );
VG_(invalidate_icache)( (void*)vir.start, vir.len );
@@ -1775,7 +1788,7 @@
/* Delete a tt entry, and update all the eclass data accordingly. */
static void delete_tte ( /*MOD*/Sector* sec, UInt secNo, Int tteno,
- VexArch vex_arch )
+ VexArch arch_host, VexEndness endness_host )
{
Int i, ec_num, ec_idx;
TTEntry* tte;
@@ -1789,7 +1802,7 @@
vg_assert(tte->n_tte2ec >= 1 && tte->n_tte2ec <= 3);
/* Unchain .. */
- unchain_in_preparation_for_deletion(vex_arch, secNo, tteno);
+ unchain_in_preparation_for_deletion(arch_host, endness_host, secNo, tteno);
/* Deal with the ec-to-tte links first. */
for (i = 0; i < tte->n_tte2ec; i++) {
@@ -1829,7 +1842,8 @@
Bool delete_translations_in_sector_eclass ( /*MOD*/Sector* sec, UInt secNo,
Addr64 guest_start, ULong range,
Int ec,
- VexArch vex_arch )
+ VexArch arch_host,
+ VexEndness endness_host )
{
Int i;
UShort tteno;
@@ -1853,7 +1867,7 @@
if (overlaps( guest_start, range, &tte->vge )) {
anyDeld = True;
- delete_tte( sec, secNo, (Int)tteno, vex_arch );
+ delete_tte( sec, secNo, (Int)tteno, arch_host, endness_host );
}
}
@@ -1868,7 +1882,8 @@
static
Bool delete_translations_in_sector ( /*MOD*/Sector* sec, UInt secNo,
Addr64 guest_start, ULong range,
- VexArch vex_arch )
+ VexArch arch_host,
+ VexEndness endness_host )
{
Int i;
Bool anyDeld = False;
@@ -1877,7 +1892,7 @@
if (sec->tt[i].status == InUse
&& overlaps( guest_start, range, &sec->tt[i].vge )) {
anyDeld = True;
- delete_tte( sec, secNo, i, vex_arch );
+ delete_tte( sec, secNo, i, arch_host, endness_host );
}
}
@@ -1907,8 +1922,11 @@
if (range == 0)
return;
- VexArch vex_arch = VexArch_INVALID;
- VG_(machine_get_VexArchInfo)( &vex_arch, NULL );
+ VexArch arch_host = VexArch_INVALID;
+ VexArchInfo archinfo_host;
+ VG_(bzero_inline)(&archinfo_host, sizeof(archinfo_host));
+ VG_(machine_get_VexArchInfo)( &arch_host, &archinfo_host );
+ VexEndness endness_host = archinfo_host.endness;
/* There are two different ways to do this.
@@ -1950,11 +1968,11 @@
continue;
anyDeleted |= delete_translations_in_sector_eclass(
sec, sno, guest_start, range, ec,
- vex_arch
+ arch_host, endness_host
);
anyDeleted |= delete_translations_in_sector_eclass(
sec, sno, guest_start, range, ECLASS_MISC,
- vex_arch
+ arch_host, endness_host
);
}
@@ -1970,7 +1988,9 @@
if (sec->tc == NULL)
continue;
anyDeleted |= delete_translations_in_sector(
- sec, sno, guest_start, range, vex_arch );
+ sec, sno, guest_start, range,
+ arch_host, endness_host
+ );
}
}
Modified: trunk/coregrind/pub_core_transtab.h
==============================================================================
--- trunk/coregrind/pub_core_transtab.h (original)
+++ trunk/coregrind/pub_core_transtab.h Thu Jul 24 12:45:24 2014
@@ -83,8 +83,7 @@
UInt code_len,
Bool is_self_checking,
Int offs_profInc,
- UInt n_guest_instrs,
- VexArch arch_host );
+ UInt n_guest_instrs );
extern
void VG_(tt_tc_do_chaining) ( void* from__patch_addr,
|
|
From: <sv...@va...> - 2014-07-24 12:42:16
|
Author: sewardj
Date: Thu Jul 24 12:42:03 2014
New Revision: 2910
Log:
Improve infrastructure for dealing with endianness in VEX. This patch
removes all decisions about endianness from VEX. Instead, it requires
that the LibVEX_* calls pass in information about the guest or host
endianness (depending on context) and in turn it passes that info
through to all the places that need it:
* the front ends (xx_toIR.c)
* the back ends (xx_isel.c)
* the patcher functions (Chain, UnChain, PatchProfInc)
Mostly it is boring and ugly plumbing. As far as types go, there is a
new type "VexEndness" that carries the endianness. This also makes it
possible to stop using Bools to indicate endianness. VexArchInfo has
a new field of type VexEndness. Apart from that, no other changes in
types.
Followups: MIPS front and back ends have not yet been fixed up to use
the passed-in endianness information. Currently they assume that the
endianness of both host and guest is the same as the endianness of the
target for which VEX is being compiled.
Modified:
trunk/priv/guest_amd64_defs.h
trunk/priv/guest_amd64_toIR.c
trunk/priv/guest_arm64_defs.h
trunk/priv/guest_arm64_toIR.c
trunk/priv/guest_arm_defs.h
trunk/priv/guest_arm_toIR.c
trunk/priv/guest_generic_bb_to_IR.c
trunk/priv/guest_generic_bb_to_IR.h
trunk/priv/guest_mips_defs.h
trunk/priv/guest_mips_toIR.c
trunk/priv/guest_ppc_defs.h
trunk/priv/guest_ppc_toIR.c
trunk/priv/guest_s390_defs.h
trunk/priv/guest_s390_toIR.c
trunk/priv/guest_x86_defs.h
trunk/priv/guest_x86_toIR.c
trunk/priv/host_amd64_defs.c
trunk/priv/host_amd64_defs.h
trunk/priv/host_amd64_isel.c
trunk/priv/host_arm64_defs.c
trunk/priv/host_arm64_defs.h
trunk/priv/host_arm64_isel.c
trunk/priv/host_arm_defs.c
trunk/priv/host_arm_defs.h
trunk/priv/host_arm_isel.c
trunk/priv/host_mips_defs.c
trunk/priv/host_mips_defs.h
trunk/priv/host_mips_isel.c
trunk/priv/host_ppc_defs.c
trunk/priv/host_ppc_defs.h
trunk/priv/host_ppc_isel.c
trunk/priv/host_s390_defs.c
trunk/priv/host_s390_defs.h
trunk/priv/host_s390_isel.c
trunk/priv/host_x86_defs.c
trunk/priv/host_x86_defs.h
trunk/priv/host_x86_isel.c
trunk/priv/main_main.c
trunk/pub/libvex.h
Modified: trunk/priv/guest_amd64_defs.h
==============================================================================
--- trunk/priv/guest_amd64_defs.h (original)
+++ trunk/priv/guest_amd64_defs.h Thu Jul 24 12:42:03 2014
@@ -60,7 +60,7 @@
VexArch guest_arch,
VexArchInfo* archinfo,
VexAbiInfo* abiinfo,
- Bool host_bigendian,
+ VexEndness host_endness,
Bool sigill_diag );
/* Used by the optimiser to specialise calls to helpers. */
Modified: trunk/priv/guest_amd64_toIR.c
==============================================================================
--- trunk/priv/guest_amd64_toIR.c (original)
+++ trunk/priv/guest_amd64_toIR.c Thu Jul 24 12:42:03 2014
@@ -185,7 +185,7 @@
that we don't have to pass them around endlessly. */
/* We need to know this to do sub-register accesses correctly. */
-static Bool host_is_bigendian;
+static VexEndness host_endness;
/* Pointer to the guest code area (points to start of BB, not to the
insn being processed). */
@@ -975,7 +975,7 @@
static IRExpr* getIRegCL ( void )
{
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
return IRExpr_Get( OFFB_RCX, Ity_I8 );
}
@@ -984,7 +984,7 @@
static void putIRegAH ( IRExpr* e )
{
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
stmt( IRStmt_Put( OFFB_RAX+1, e ) );
}
@@ -1006,7 +1006,7 @@
static IRExpr* getIRegRAX ( Int sz )
{
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
switch (sz) {
case 1: return IRExpr_Get( OFFB_RAX, Ity_I8 );
case 2: return IRExpr_Get( OFFB_RAX, Ity_I16 );
@@ -1019,7 +1019,7 @@
static void putIRegRAX ( Int sz, IRExpr* e )
{
IRType ty = typeOfIRExpr(irsb->tyenv, e);
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
switch (sz) {
case 8: vassert(ty == Ity_I64);
stmt( IRStmt_Put( OFFB_RAX, e ));
@@ -1054,7 +1054,7 @@
static IRExpr* getIRegRDX ( Int sz )
{
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
switch (sz) {
case 1: return IRExpr_Get( OFFB_RDX, Ity_I8 );
case 2: return IRExpr_Get( OFFB_RDX, Ity_I16 );
@@ -1066,7 +1066,7 @@
static void putIRegRDX ( Int sz, IRExpr* e )
{
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
vassert(typeOfIRExpr(irsb->tyenv, e) == szToITy(sz));
switch (sz) {
case 8: stmt( IRStmt_Put( OFFB_RDX, e ));
@@ -1108,7 +1108,7 @@
static IRExpr* getIReg32 ( UInt regno )
{
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
return unop(Iop_64to32,
IRExpr_Get( integerGuestReg64Offset(regno),
Ity_I64 ));
@@ -1132,7 +1132,7 @@
static IRExpr* getIReg16 ( UInt regno )
{
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
return IRExpr_Get( integerGuestReg64Offset(regno),
Ity_I16 );
}
@@ -1253,7 +1253,7 @@
static UInt offsetIRegG ( Int sz, Prefix pfx, UChar mod_reg_rm )
{
UInt reg;
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
vassert(IS_VALID_PFX(pfx));
vassert(sz == 8 || sz == 4 || sz == 2 || sz == 1);
reg = gregOfRexRM( pfx, mod_reg_rm );
@@ -1332,7 +1332,7 @@
static UInt offsetIRegE ( Int sz, Prefix pfx, UChar mod_reg_rm )
{
UInt reg;
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
vassert(IS_VALID_PFX(pfx));
vassert(sz == 8 || sz == 4 || sz == 2 || sz == 1);
reg = eregOfRexRM( pfx, mod_reg_rm );
@@ -1401,7 +1401,7 @@
static Int xmmGuestRegOffset ( UInt xmmreg )
{
/* Correct for little-endian host only. */
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
return ymmGuestRegOffset( xmmreg );
}
@@ -1411,7 +1411,7 @@
static Int xmmGuestRegLane16offset ( UInt xmmreg, Int laneno )
{
/* Correct for little-endian host only. */
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
vassert(laneno >= 0 && laneno < 8);
return xmmGuestRegOffset( xmmreg ) + 2 * laneno;
}
@@ -1419,7 +1419,7 @@
static Int xmmGuestRegLane32offset ( UInt xmmreg, Int laneno )
{
/* Correct for little-endian host only. */
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
vassert(laneno >= 0 && laneno < 4);
return xmmGuestRegOffset( xmmreg ) + 4 * laneno;
}
@@ -1427,7 +1427,7 @@
static Int xmmGuestRegLane64offset ( UInt xmmreg, Int laneno )
{
/* Correct for little-endian host only. */
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
vassert(laneno >= 0 && laneno < 2);
return xmmGuestRegOffset( xmmreg ) + 8 * laneno;
}
@@ -1435,7 +1435,7 @@
static Int ymmGuestRegLane128offset ( UInt ymmreg, Int laneno )
{
/* Correct for little-endian host only. */
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
vassert(laneno >= 0 && laneno < 2);
return ymmGuestRegOffset( ymmreg ) + 16 * laneno;
}
@@ -1443,7 +1443,7 @@
static Int ymmGuestRegLane64offset ( UInt ymmreg, Int laneno )
{
/* Correct for little-endian host only. */
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
vassert(laneno >= 0 && laneno < 4);
return ymmGuestRegOffset( ymmreg ) + 8 * laneno;
}
@@ -1451,7 +1451,7 @@
static Int ymmGuestRegLane32offset ( UInt ymmreg, Int laneno )
{
/* Correct for little-endian host only. */
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
vassert(laneno >= 0 && laneno < 8);
return ymmGuestRegOffset( ymmreg ) + 4 * laneno;
}
@@ -31745,7 +31745,7 @@
VexArch guest_arch,
VexArchInfo* archinfo,
VexAbiInfo* abiinfo,
- Bool host_bigendian_IN,
+ VexEndness host_endness_IN,
Bool sigill_diag_IN )
{
Int i, x1, x2;
@@ -31756,7 +31756,7 @@
vassert(guest_arch == VexArchAMD64);
guest_code = guest_code_IN;
irsb = irsb_IN;
- host_is_bigendian = host_bigendian_IN;
+ host_endness = host_endness_IN;
guest_RIP_curr_instr = guest_IP;
guest_RIP_bbstart = guest_IP - delta;
Modified: trunk/priv/guest_arm64_defs.h
==============================================================================
--- trunk/priv/guest_arm64_defs.h (original)
+++ trunk/priv/guest_arm64_defs.h Thu Jul 24 12:42:03 2014
@@ -50,7 +50,7 @@
VexArch guest_arch,
VexArchInfo* archinfo,
VexAbiInfo* abiinfo,
- Bool host_bigendian,
+ VexEndness host_endness,
Bool sigill_diag );
/* Used by the optimiser to specialise calls to helpers. */
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Thu Jul 24 12:42:03 2014
@@ -119,9 +119,10 @@
not change during translation of the instruction.
*/
-/* CONST: is the host bigendian? We need to know this in order to do
- sub-register accesses to the SIMD/FP registers correctly. */
-static Bool host_is_bigendian;
+/* CONST: what is the host's endianness? We need to know this in
+ order to do sub-register accesses to the SIMD/FP registers
+ correctly. */
+static VexEndness host_endness;
/* CONST: The guest address for the instruction currently being
translated. */
@@ -1227,7 +1228,7 @@
has the lowest offset. */
static Int offsetQRegLane ( UInt qregNo, IRType laneTy, UInt laneNo )
{
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
Int base = offsetQReg128(qregNo);
/* Since the host is little-endian, the least significant lane
will be at the lowest address. */
@@ -10355,7 +10356,7 @@
VexArch guest_arch,
VexArchInfo* archinfo,
VexAbiInfo* abiinfo,
- Bool host_bigendian_IN,
+ VexEndness host_endness_IN,
Bool sigill_diag_IN )
{
DisResult dres;
@@ -10365,7 +10366,7 @@
vassert(guest_arch == VexArchARM64);
irsb = irsb_IN;
- host_is_bigendian = host_bigendian_IN;
+ host_endness = host_endness_IN;
guest_PC_curr_instr = (Addr64)guest_IP;
/* Sanity checks */
Modified: trunk/priv/guest_arm_defs.h
==============================================================================
--- trunk/priv/guest_arm_defs.h (original)
+++ trunk/priv/guest_arm_defs.h Thu Jul 24 12:42:03 2014
@@ -52,7 +52,7 @@
VexArch guest_arch,
VexArchInfo* archinfo,
VexAbiInfo* abiinfo,
- Bool host_bigendian,
+ VexEndness host_endness,
Bool sigill_diag );
/* Used by the optimiser to specialise calls to helpers. */
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Thu Jul 24 12:42:03 2014
@@ -123,10 +123,10 @@
not change during translation of the instruction.
*/
-/* CONST: is the host bigendian? This has to do with float vs double
- register accesses on VFP, but it's complex and not properly thought
- out. */
-static Bool host_is_bigendian;
+/* CONST: what is the host's endianness? This has to do with float vs
+ double register accesses on VFP, but it's complex and not properly
+ thought out. */
+static VexEndness host_endness;
/* CONST: The guest address for the instruction currently being
translated. This is the real, "decoded" address (not subject
@@ -849,11 +849,11 @@
Int off;
vassert(fregNo < 32);
off = doubleGuestRegOffset(fregNo >> 1);
- if (host_is_bigendian) {
- vassert(0);
- } else {
+ if (host_endness == VexEndnessLE) {
if (fregNo & 1)
off += 4;
+ } else {
+ vassert(0);
}
return off;
}
@@ -21976,7 +21976,7 @@
VexArch guest_arch,
VexArchInfo* archinfo,
VexAbiInfo* abiinfo,
- Bool host_bigendian_IN,
+ VexEndness host_endness_IN,
Bool sigill_diag_IN )
{
DisResult dres;
@@ -21985,9 +21985,9 @@
/* Set globals (see top of this file) */
vassert(guest_arch == VexArchARM);
- irsb = irsb_IN;
- host_is_bigendian = host_bigendian_IN;
- __curr_is_Thumb = isThumb;
+ irsb = irsb_IN;
+ host_endness = host_endness_IN;
+ __curr_is_Thumb = isThumb;
if (isThumb) {
guest_R15_curr_instr_notENC = (Addr32)guest_IP_ENCODED - 1;
Modified: trunk/priv/guest_generic_bb_to_IR.c
==============================================================================
--- trunk/priv/guest_generic_bb_to_IR.c (original)
+++ trunk/priv/guest_generic_bb_to_IR.c Thu Jul 24 12:42:03 2014
@@ -186,7 +186,7 @@
/*IN*/ UChar* guest_code,
/*IN*/ Addr64 guest_IP_bbstart,
/*IN*/ Bool (*chase_into_ok)(void*,Addr64),
- /*IN*/ Bool host_bigendian,
+ /*IN*/ VexEndness host_endness,
/*IN*/ Bool sigill_diag,
/*IN*/ VexArch arch_guest,
/*IN*/ VexArchInfo* archinfo_guest,
@@ -362,7 +362,7 @@
arch_guest,
archinfo_guest,
abiinfo_both,
- host_bigendian,
+ host_endness,
sigill_diag );
/* stay sane ... */
Modified: trunk/priv/guest_generic_bb_to_IR.h
==============================================================================
--- trunk/priv/guest_generic_bb_to_IR.h (original)
+++ trunk/priv/guest_generic_bb_to_IR.h Thu Jul 24 12:42:03 2014
@@ -152,8 +152,8 @@
/* ABI info for both guest and host */
/*IN*/ VexAbiInfo* abiinfo,
- /* Is the host bigendian? */
- /*IN*/ Bool host_bigendian,
+ /* The endianness of the host */
+ /*IN*/ VexEndness host_endness,
/* Should diagnostics be printed for illegal instructions? */
/*IN*/ Bool sigill_diag
@@ -176,7 +176,7 @@
/*IN*/ UChar* guest_code,
/*IN*/ Addr64 guest_IP_bbstart,
/*IN*/ Bool (*chase_into_ok)(void*,Addr64),
- /*IN*/ Bool host_bigendian,
+ /*IN*/ VexEndness host_endness,
/*IN*/ Bool sigill_diag,
/*IN*/ VexArch arch_guest,
/*IN*/ VexArchInfo* archinfo_guest,
Modified: trunk/priv/guest_mips_defs.h
==============================================================================
--- trunk/priv/guest_mips_defs.h (original)
+++ trunk/priv/guest_mips_defs.h Thu Jul 24 12:42:03 2014
@@ -51,7 +51,7 @@
VexArch guest_arch,
VexArchInfo* archinfo,
VexAbiInfo* abiinfo,
- Bool host_bigendian,
+ VexEndness host_endness,
Bool sigill_diag );
/* Used by the optimiser to specialise calls to helpers. */
Modified: trunk/priv/guest_mips_toIR.c
==============================================================================
--- trunk/priv/guest_mips_toIR.c (original)
+++ trunk/priv/guest_mips_toIR.c Thu Jul 24 12:42:03 2014
@@ -49,10 +49,10 @@
that we don't have to pass them around endlessly. CONST means does
not change during translation of the instruction. */
-/* CONST: is the host bigendian? This has to do with float vs double
- register accesses on VFP, but it's complex and not properly thought
- out. */
-static Bool host_is_bigendian;
+/* CONST: what is the host's endianness? This has to do with float vs
+ double register accesses on VFP, but it's complex and not properly
+ thought out. */
+static VexEndness host_endness;
/* Pointer to the guest code area. */
static UChar *guest_code;
@@ -17202,7 +17202,7 @@
VexArch guest_arch,
VexArchInfo* archinfo,
VexAbiInfo* abiinfo,
- Bool host_bigendian_IN,
+ VexEndness host_endness_IN,
Bool sigill_diag_IN )
{
DisResult dres;
@@ -17217,7 +17217,7 @@
guest_code = guest_code_IN;
irsb = irsb_IN;
- host_is_bigendian = host_bigendian_IN;
+ host_endness = host_endness_IN;
#if defined(VGP_mips32_linux)
guest_PC_curr_instr = (Addr32)guest_IP;
#elif defined(VGP_mips64_linux)
Modified: trunk/priv/guest_ppc_defs.h
==============================================================================
--- trunk/priv/guest_ppc_defs.h (original)
+++ trunk/priv/guest_ppc_defs.h Thu Jul 24 12:42:03 2014
@@ -61,7 +61,7 @@
VexArch guest_arch,
VexArchInfo* archinfo,
VexAbiInfo* abiinfo,
- Bool host_bigendian,
+ VexEndness host_endness,
Bool sigill_diag );
/* Used by the optimiser to specialise calls to helpers. */
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Thu Jul 24 12:42:03 2014
@@ -154,7 +154,7 @@
given insn. */
/* We need to know this to do sub-register accesses correctly. */
-static Bool host_is_bigendian;
+static VexEndness host_endness;
/* Pointer to the guest code area. */
static UChar* guest_code;
@@ -1039,7 +1039,7 @@
// jrs: probably not necessary; only matters if we reference sub-parts
// of the ppc registers, but that isn't the case
// later: this might affect Altivec though?
- vassert(host_is_bigendian);
+ vassert(host_endness == VexEndnessBE);
switch (archreg) {
case 0: return offsetofPPCGuestState(guest_GPR0);
@@ -19941,7 +19941,7 @@
VexArch guest_arch,
VexArchInfo* archinfo,
VexAbiInfo* abiinfo,
- Bool host_bigendian_IN,
+ VexEndness host_endness_IN,
Bool sigill_diag_IN )
{
IRType ty;
@@ -19973,7 +19973,7 @@
/* Set globals (see top of this file) */
guest_code = guest_code_IN;
irsb = irsb_IN;
- host_is_bigendian = host_bigendian_IN;
+ host_endness = host_endness_IN;
guest_CIA_curr_instr = mkSzAddr(ty, guest_IP);
guest_CIA_bbstart = mkSzAddr(ty, guest_IP - delta);
Modified: trunk/priv/guest_s390_defs.h
==============================================================================
--- trunk/priv/guest_s390_defs.h (original)
+++ trunk/priv/guest_s390_defs.h Thu Jul 24 12:42:03 2014
@@ -50,7 +50,7 @@
VexArch guest_arch,
VexArchInfo* archinfo,
VexAbiInfo* abiinfo,
- Bool host_bigendian,
+ VexEndness host_endness,
Bool sigill_diag );
/* Used by the optimiser to specialise calls to helpers. */
Modified: trunk/priv/guest_s390_toIR.c
==============================================================================
--- trunk/priv/guest_s390_toIR.c (original)
+++ trunk/priv/guest_s390_toIR.c Thu Jul 24 12:42:03 2014
@@ -16565,13 +16565,13 @@
VexArch guest_arch,
VexArchInfo *archinfo,
VexAbiInfo *abiinfo,
- Bool host_bigendian,
+ VexEndness host_endness,
Bool sigill_diag_IN)
{
vassert(guest_arch == VexArchS390X);
/* The instruction decoder requires a big-endian machine. */
- vassert(host_bigendian == True);
+ vassert(host_endness == VexEndnessBE);
/* Set globals (see top of this file) */
guest_IA_curr_instr = guest_IP;
Modified: trunk/priv/guest_x86_defs.h
==============================================================================
--- trunk/priv/guest_x86_defs.h (original)
+++ trunk/priv/guest_x86_defs.h Thu Jul 24 12:42:03 2014
@@ -60,7 +60,7 @@
VexArch guest_arch,
VexArchInfo* archinfo,
VexAbiInfo* abiinfo,
- Bool host_bigendian,
+ VexEndness host_endness,
Bool sigill_diag );
/* Used by the optimiser to specialise calls to helpers. */
Modified: trunk/priv/guest_x86_toIR.c
==============================================================================
--- trunk/priv/guest_x86_toIR.c (original)
+++ trunk/priv/guest_x86_toIR.c Thu Jul 24 12:42:03 2014
@@ -195,7 +195,7 @@
given insn. */
/* We need to know this to do sub-register accesses correctly. */
-static Bool host_is_bigendian;
+static VexEndness host_endness;
/* Pointer to the guest code area (points to start of BB, not to the
insn being processed). */
@@ -452,7 +452,7 @@
vassert(archreg < 8);
/* Correct for little-endian host only. */
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
if (sz == 4 || sz == 2 || (sz == 1 && archreg < 4)) {
switch (archreg) {
@@ -515,7 +515,7 @@
static Int xmmGuestRegLane16offset ( UInt xmmreg, Int laneno )
{
/* Correct for little-endian host only. */
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
vassert(laneno >= 0 && laneno < 8);
return xmmGuestRegOffset( xmmreg ) + 2 * laneno;
}
@@ -523,7 +523,7 @@
static Int xmmGuestRegLane32offset ( UInt xmmreg, Int laneno )
{
/* Correct for little-endian host only. */
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
vassert(laneno >= 0 && laneno < 4);
return xmmGuestRegOffset( xmmreg ) + 4 * laneno;
}
@@ -531,7 +531,7 @@
static Int xmmGuestRegLane64offset ( UInt xmmreg, Int laneno )
{
/* Correct for little-endian host only. */
- vassert(!host_is_bigendian);
+ vassert(host_endness == VexEndnessLE);
vassert(laneno >= 0 && laneno < 2);
return xmmGuestRegOffset( xmmreg ) + 8 * laneno;
}
@@ -15421,7 +15421,7 @@
VexArch guest_arch,
VexArchInfo* archinfo,
VexAbiInfo* abiinfo,
- Bool host_bigendian_IN,
+ VexEndness host_endness_IN,
Bool sigill_diag_IN )
{
Int i, x1, x2;
@@ -15432,7 +15432,7 @@
vassert(guest_arch == VexArchX86);
guest_code = guest_code_IN;
irsb = irsb_IN;
- host_is_bigendian = host_bigendian_IN;
+ host_endness = host_endness_IN;
guest_EIP_curr_instr = (Addr32)guest_IP;
guest_EIP_bbstart = (Addr32)toUInt(guest_IP - delta);
Modified: trunk/priv/host_amd64_defs.c
==============================================================================
--- trunk/priv/host_amd64_defs.c (original)
+++ trunk/priv/host_amd64_defs.c Thu Jul 24 12:42:03 2014
@@ -2265,7 +2265,7 @@
Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc,
UChar* buf, Int nbuf, AMD64Instr* i,
- Bool mode64,
+ Bool mode64, VexEndness endness_host,
void* disp_cp_chain_me_to_slowEP,
void* disp_cp_chain_me_to_fastEP,
void* disp_cp_xindir,
@@ -3499,7 +3499,7 @@
p = doAMode_M(p, fake(4), i->Ain.EvCheck.amFailAddr);
vassert(p - p0 == 8); /* also ensures that 0x03 offset above is ok */
/* And crosscheck .. */
- vassert(evCheckSzB_AMD64() == 8);
+ vassert(evCheckSzB_AMD64(endness_host) == 8);
goto done;
}
@@ -3542,7 +3542,7 @@
/* How big is an event check? See case for Ain_EvCheck in
emit_AMD64Instr just above. That crosschecks what this returns, so
we can tell if we're inconsistent. */
-Int evCheckSzB_AMD64 ( void )
+Int evCheckSzB_AMD64 ( VexEndness endness_host )
{
return 8;
}
@@ -3550,10 +3550,13 @@
/* NB: what goes on here has to be very closely coordinated with the
emitInstr case for XDirect, above. */
-VexInvalRange chainXDirect_AMD64 ( void* place_to_chain,
+VexInvalRange chainXDirect_AMD64 ( VexEndness endness_host,
+ void* place_to_chain,
void* disp_cp_chain_me_EXPECTED,
void* place_to_jump_to )
{
+ vassert(endness_host == VexEndnessLE);
+
/* What we're expecting to see is:
movabsq $disp_cp_chain_me_EXPECTED, %r11
call *%r11
@@ -3636,10 +3639,13 @@
/* NB: what goes on here has to be very closely coordinated with the
emitInstr case for XDirect, above. */
-VexInvalRange unchainXDirect_AMD64 ( void* place_to_unchain,
+VexInvalRange unchainXDirect_AMD64 ( VexEndness endness_host,
+ void* place_to_unchain,
void* place_to_jump_to_EXPECTED,
void* disp_cp_chain_me )
{
+ vassert(endness_host == VexEndnessLE);
+
/* What we're expecting to see is either:
(general case)
movabsq $place_to_jump_to_EXPECTED, %r11
@@ -3700,9 +3706,11 @@
/* Patch the counter address into a profile inc point, as previously
created by the Ain_ProfInc case for emit_AMD64Instr. */
-VexInvalRange patchProfInc_AMD64 ( void* place_to_patch,
+VexInvalRange patchProfInc_AMD64 ( VexEndness endness_host,
+ void* place_to_patch,
ULong* location_of_counter )
{
+ vassert(endness_host == VexEndnessLE);
vassert(sizeof(ULong*) == 8);
UChar* p = (UChar*)place_to_patch;
vassert(p[0] == 0x49);
Modified: trunk/priv/host_amd64_defs.h
==============================================================================
--- trunk/priv/host_amd64_defs.h (original)
+++ trunk/priv/host_amd64_defs.h Thu Jul 24 12:42:03 2014
@@ -754,8 +754,10 @@
extern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr*, Bool );
extern Bool isMove_AMD64Instr ( AMD64Instr*, HReg*, HReg* );
extern Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc,
- UChar* buf, Int nbuf, AMD64Instr* i,
+ UChar* buf, Int nbuf,
+ AMD64Instr* i,
Bool mode64,
+ VexEndness endness_host,
void* disp_cp_chain_me_to_slowEP,
void* disp_cp_chain_me_to_fastEP,
void* disp_cp_xindir,
@@ -782,19 +784,22 @@
and so assumes that they are both <= 128, and so can use the short
offset encoding. This is all checked with assertions, so in the
worst case we will merely assert at startup. */
-extern Int evCheckSzB_AMD64 ( void );
+extern Int evCheckSzB_AMD64 ( VexEndness endness_host );
/* Perform a chaining and unchaining of an XDirect jump. */
-extern VexInvalRange chainXDirect_AMD64 ( void* place_to_chain,
+extern VexInvalRange chainXDirect_AMD64 ( VexEndness endness_host,
+ void* place_to_chain,
void* disp_cp_chain_me_EXPECTED,
void* place_to_jump_to );
-extern VexInvalRange unchainXDirect_AMD64 ( void* place_to_unchain,
+extern VexInvalRange unchainXDirect_AMD64 ( VexEndness endness_host,
+ void* place_to_unchain,
void* place_to_jump_to_EXPECTED,
void* disp_cp_chain_me );
/* Patch the counter location into an existing ProfInc point. */
-extern VexInvalRange patchProfInc_AMD64 ( void* place_to_patch,
+extern VexInvalRange patchProfInc_AMD64 ( VexEndness endness_host,
+ void* place_to_patch,
ULong* location_of_counter );
Modified: trunk/priv/host_amd64_isel.c
==============================================================================
--- trunk/priv/host_amd64_isel.c (original)
+++ trunk/priv/host_amd64_isel.c Thu Jul 24 12:42:03 2014
@@ -4877,6 +4877,9 @@
| VEX_HWCAPS_AMD64_BMI
| VEX_HWCAPS_AMD64_AVX2)));
+ /* Check that the host's endianness is as expected. */
+ vassert(archinfo_host->endness == VexEndnessLE);
+
/* Make up an initial environment to use. */
env = LibVEX_Alloc(sizeof(ISelEnv));
env->vreg_ctr = 0;
Modified: trunk/priv/host_arm64_defs.c
==============================================================================
--- trunk/priv/host_arm64_defs.c (original)
+++ trunk/priv/host_arm64_defs.c Thu Jul 24 12:42:03 2014
@@ -4104,7 +4104,7 @@
Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc,
UChar* buf, Int nbuf, ARM64Instr* i,
- Bool mode64,
+ Bool mode64, VexEndness endness_host,
void* disp_cp_chain_me_to_slowEP,
void* disp_cp_chain_me_to_fastEP,
void* disp_cp_xindir,
@@ -6866,7 +6866,7 @@
/* nofail: */
/* Crosscheck */
- vassert(evCheckSzB_ARM64() == (UChar*)p - (UChar*)p0);
+ vassert(evCheckSzB_ARM64(endness_host) == (UChar*)p - (UChar*)p0);
goto done;
}
@@ -6917,7 +6917,7 @@
/* How big is an event check? See case for ARM64in_EvCheck in
emit_ARM64Instr just above. That crosschecks what this returns, so
we can tell if we're inconsistent. */
-Int evCheckSzB_ARM64 ( void )
+Int evCheckSzB_ARM64 ( VexEndness endness_host )
{
return 24;
}
@@ -6925,10 +6925,13 @@
/* NB: what goes on here has to be very closely coordinated with the
emitInstr case for XDirect, above. */
-VexInvalRange chainXDirect_ARM64 ( void* place_to_chain,
+VexInvalRange chainXDirect_ARM64 ( VexEndness endness_host,
+ void* place_to_chain,
void* disp_cp_chain_me_EXPECTED,
void* place_to_jump_to )
{
+ vassert(endness_host == VexEndnessLE);
+
/* What we're expecting to see is:
movw x9, disp_cp_chain_me_to_EXPECTED[15:0]
movk x9, disp_cp_chain_me_to_EXPECTED[31:15], lsl 16
@@ -6968,10 +6971,13 @@
/* NB: what goes on here has to be very closely coordinated with the
emitInstr case for XDirect, above. */
-VexInvalRange unchainXDirect_ARM64 ( void* place_to_unchain,
+VexInvalRange unchainXDirect_ARM64 ( VexEndness endness_host,
+ void* place_to_unchain,
void* place_to_jump_to_EXPECTED,
void* disp_cp_chain_me )
{
+ vassert(endness_host == VexEndnessLE);
+
/* What we're expecting to see is:
movw x9, place_to_jump_to_EXPECTED[15:0]
movk x9, place_to_jump_to_EXPECTED[31:15], lsl 16
@@ -7009,7 +7015,8 @@
//ZZ /* Patch the counter address into a profile inc point, as previously
//ZZ created by the ARMin_ProfInc case for emit_ARMInstr. */
-//ZZ VexInvalRange patchProfInc_ARM ( void* place_to_patch,
+//ZZ VexInvalRange patchProfInc_ARM ( VexEndness endness_host,
+//ZZ void* place_to_patch,
//ZZ ULong* location_of_counter )
//ZZ {
//ZZ vassert(sizeof(ULong*) == 4);
Modified: trunk/priv/host_arm64_defs.h
==============================================================================
--- trunk/priv/host_arm64_defs.h (original)
+++ trunk/priv/host_arm64_defs.h Thu Jul 24 12:42:03 2014
@@ -843,6 +843,7 @@
extern Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc,
UChar* buf, Int nbuf, ARM64Instr* i,
Bool mode64,
+ VexEndness endness_host,
void* disp_cp_chain_me_to_slowEP,
void* disp_cp_chain_me_to_fastEP,
void* disp_cp_xindir,
@@ -867,19 +868,22 @@
/* How big is an event check? This is kind of a kludge because it
depends on the offsets of host_EvC_FAILADDR and
host_EvC_COUNTER. */
-extern Int evCheckSzB_ARM64 ( void );
+extern Int evCheckSzB_ARM64 ( VexEndness endness_host );
/* Perform a chaining and unchaining of an XDirect jump. */
-extern VexInvalRange chainXDirect_ARM64 ( void* place_to_chain,
+extern VexInvalRange chainXDirect_ARM64 ( VexEndness endness_host,
+ void* place_to_chain,
void* disp_cp_chain_me_EXPECTED,
void* place_to_jump_to );
-extern VexInvalRange unchainXDirect_ARM64 ( void* place_to_unchain,
+extern VexInvalRange unchainXDirect_ARM64 ( VexEndness endness_host,
+ void* place_to_unchain,
void* place_to_jump_to_EXPECTED,
void* disp_cp_chain_me );
//ZZ /* Patch the counter location into an existing ProfInc point. */
-//ZZ extern VexInvalRange patchProfInc_ARM ( void* place_to_patch,
+//ZZ extern VexInvalRange patchProfInc_ARM ( VexEndness endness_host,
+//ZZ void* place_to_patch,
//ZZ ULong* location_of_counter );
Modified: trunk/priv/host_arm64_isel.c
==============================================================================
--- trunk/priv/host_arm64_isel.c (original)
+++ trunk/priv/host_arm64_isel.c Thu Jul 24 12:42:03 2014
@@ -7106,6 +7106,9 @@
/* sanity ... */
vassert(arch_host == VexArchARM64);
+ /* Check that the host's endianness is as expected. */
+ vassert(archinfo_host->endness == VexEndnessLE);
+
/* guard against unexpected space regressions */
vassert(sizeof(ARM64Instr) <= 32);
Modified: trunk/priv/host_arm_defs.c
==============================================================================
--- trunk/priv/host_arm_defs.c (original)
+++ trunk/priv/host_arm_defs.c Thu Jul 24 12:42:03 2014
@@ -2971,7 +2971,7 @@
Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc,
UChar* buf, Int nbuf, ARMInstr* i,
- Bool mode64,
+ Bool mode64, VexEndness endness_host,
void* disp_cp_chain_me_to_slowEP,
void* disp_cp_chain_me_to_fastEP,
void* disp_cp_xindir,
@@ -4644,7 +4644,7 @@
/* nofail: */
/* Crosscheck */
- vassert(evCheckSzB_ARM() == (UChar*)p - (UChar*)p0);
+ vassert(evCheckSzB_ARM(endness_host) == (UChar*)p - (UChar*)p0);
goto done;
}
@@ -4695,7 +4695,7 @@
/* How big is an event check? See case for ARMin_EvCheck in
emit_ARMInstr just above. That crosschecks what this returns, so
we can tell if we're inconsistent. */
-Int evCheckSzB_ARM ( void )
+Int evCheckSzB_ARM ( VexEndness endness_host )
{
return 24;
}
@@ -4703,10 +4703,13 @@
/* NB: what goes on here has to be very closely coordinated with the
emitInstr case for XDirect, above. */
-VexInvalRange chainXDirect_ARM ( void* place_to_chain,
+VexInvalRange chainXDirect_ARM ( VexEndness endness_host,
+ void* place_to_chain,
void* disp_cp_chain_me_EXPECTED,
void* place_to_jump_to )
{
+ vassert(endness_host == VexEndnessLE);
+
/* What we're expecting to see is:
movw r12, lo16(disp_cp_chain_me_to_EXPECTED)
movt r12, hi16(disp_cp_chain_me_to_EXPECTED)
@@ -4783,10 +4786,13 @@
/* NB: what goes on here has to be very closely coordinated with the
emitInstr case for XDirect, above. */
-VexInvalRange unchainXDirect_ARM ( void* place_to_unchain,
+VexInvalRange unchainXDirect_ARM ( VexEndness endness_host,
+ void* place_to_unchain,
void* place_to_jump_to_EXPECTED,
void* disp_cp_chain_me )
{
+ vassert(endness_host == VexEndnessLE);
+
/* What we're expecting to see is:
(general case)
movw r12, lo16(place_to_jump_to_EXPECTED)
@@ -4844,9 +4850,11 @@
/* Patch the counter address into a profile inc point, as previously
created by the ARMin_ProfInc case for emit_ARMInstr. */
-VexInvalRange patchProfInc_ARM ( void* place_to_patch,
+VexInvalRange patchProfInc_ARM ( VexEndness endness_host,
+ void* place_to_patch,
ULong* location_of_counter )
{
+ vassert(endness_host == VexEndnessLE);
vassert(sizeof(ULong*) == 4);
UInt* p = (UInt*)place_to_patch;
vassert(0 == (3 & (HWord)p));
Modified: trunk/priv/host_arm_defs.h
==============================================================================
--- trunk/priv/host_arm_defs.h (original)
+++ trunk/priv/host_arm_defs.h Thu Jul 24 12:42:03 2014
@@ -1027,6 +1027,7 @@
extern Int emit_ARMInstr ( /*MB_MOD*/Bool* is_profInc,
UChar* buf, Int nbuf, ARMInstr* i,
Bool mode64,
+ VexEndness endness_host,
void* disp_cp_chain_me_to_slowEP,
void* disp_cp_chain_me_to_fastEP,
void* disp_cp_xindir,
@@ -1051,19 +1052,22 @@
/* How big is an event check? This is kind of a kludge because it
depends on the offsets of host_EvC_FAILADDR and
host_EvC_COUNTER. */
-extern Int evCheckSzB_ARM ( void );
+extern Int evCheckSzB_ARM ( VexEndness endness_host );
/* Perform a chaining and unchaining of an XDirect jump. */
-extern VexInvalRange chainXDirect_ARM ( void* place_to_chain,
+extern VexInvalRange chainXDirect_ARM ( VexEndness endness_host,
+ void* place_to_chain,
void* disp_cp_chain_me_EXPECTED,
void* place_to_jump_to );
-extern VexInvalRange unchainXDirect_ARM ( void* place_to_unchain,
+extern VexInvalRange unchainXDirect_ARM ( VexEndness endness_host,
+ void* place_to_unchain,
void* place_to_jump_to_EXPECTED,
void* disp_cp_chain_me );
/* Patch the counter location into an existing ProfInc point. */
-extern VexInvalRange patchProfInc_ARM ( void* place_to_patch,
+extern VexInvalRange patchProfInc_ARM ( VexEndness endness_host,
+ void* place_to_patch,
ULong* location_of_counter );
Modified: trunk/priv/host_arm_isel.c
==============================================================================
--- trunk/priv/host_arm_isel.c (original)
+++ trunk/priv/host_arm_isel.c Thu Jul 24 12:42:03 2014
@@ -6331,6 +6331,9 @@
/* sanity ... */
vassert(arch_host == VexArchARM);
+ /* Check that the host's endianness is as expected. */
+ vassert(archinfo_host->endness == VexEndnessLE);
+
/* guard against unexpected space regressions */
vassert(sizeof(ARMInstr) <= 28);
Modified: trunk/priv/host_mips_defs.c
==============================================================================
--- trunk/priv/host_mips_defs.c (original)
+++ trunk/priv/host_mips_defs.c Thu Jul 24 12:42:03 2014
@@ -2920,6 +2920,7 @@
Int emit_MIPSInstr ( /*MB_MOD*/Bool* is_profInc,
UChar* buf, Int nbuf, MIPSInstr* i,
Bool mode64,
+ VexEndness endness_host,
void* disp_cp_chain_me_to_slowEP,
void* disp_cp_chain_me_to_fastEP,
void* disp_cp_xindir,
@@ -4229,7 +4230,7 @@
/* nofail: */
/* Crosscheck */
- vassert(evCheckSzB_MIPS() == (UChar*)p - (UChar*)p0);
+ vassert(evCheckSzB_MIPS(endness_host) == (UChar*)p - (UChar*)p0);
goto done;
}
@@ -4315,7 +4316,7 @@
/* How big is an event check? See case for Min_EvCheck in
emit_MIPSInstr just above. That crosschecks what this returns, so
we can tell if we're inconsistent. */
-Int evCheckSzB_MIPS ( void )
+Int evCheckSzB_MIPS ( VexEndness endness_host )
{
UInt kInstrSize = 4;
return 7*kInstrSize;
@@ -4323,11 +4324,13 @@
/* NB: what goes on here has to be very closely coordinated with the
emitInstr case for XDirect, above. */
-VexInvalRange chainXDirect_MIPS ( void* place_to_chain,
+VexInvalRange chainXDirect_MIPS ( VexEndness endness_host,
+ void* place_to_chain,
void* disp_cp_chain_me_EXPECTED,
void* place_to_jump_to,
Bool mode64 )
{
+ vassert(endness_host == VexEndnessLE || endness_host == VexEndnessBE);
/* What we're expecting to see is:
move r9, disp_cp_chain_me_to_EXPECTED
jalr r9
@@ -4369,11 +4372,13 @@
/* NB: what goes on here has to be very closely coordinated with the
emitInstr case for XDirect, above. */
-VexInvalRange unchainXDirect_MIPS ( void* place_to_unchain,
+VexInvalRange unchainXDirect_MIPS ( VexEndness endness_host,
+ void* place_to_unchain,
void* place_to_jump_to_EXPECTED,
void* disp_cp_chain_me,
Bool mode64 )
{
+ vassert(endness_host == VexEndnessLE || endness_host == VexEndnessBE);
/* What we're expecting to see is:
move r9, place_to_jump_to_EXPECTED
jalr r9
@@ -4413,13 +4418,16 @@
/* Patch the counter address into a profile inc point, as previously
created by the Min_ProfInc case for emit_MIPSInstr. */
-VexInvalRange patchProfInc_MIPS ( void* place_to_patch,
+VexInvalRange patchProfInc_MIPS ( VexEndness endness_host,
+ void* place_to_patch,
ULong* location_of_counter, Bool mode64 )
{
- if (mode64)
+ vassert(endness_host == VexEndnessLE || endness_host == VexEndnessBE);
+ if (mode64) {
vassert(sizeof(ULong*) == 8);
- else
+ } else {
vassert(sizeof(ULong*) == 4);
+ }
UChar* p = (UChar*)place_to_patch;
vassert(0 == (3 & (HWord)p));
vassert(isLoadImm_EXACTLY2or6((UChar *)p, /*r*/9,
Modified: trunk/priv/host_mips_defs.h
==============================================================================
--- trunk/priv/host_mips_defs.h (original)
+++ trunk/priv/host_mips_defs.h Thu Jul 24 12:42:03 2014
@@ -715,6 +715,7 @@
extern Int emit_MIPSInstr (/*MB_MOD*/Bool* is_profInc,
UChar* buf, Int nbuf, MIPSInstr* i,
Bool mode64,
+ VexEndness endness_host,
void* disp_cp_chain_me_to_slowEP,
void* disp_cp_chain_me_to_fastEP,
void* disp_cp_xindir,
@@ -741,25 +742,28 @@
and so assumes that they are both <= 128, and so can use the short
offset encoding. This is all checked with assertions, so in the
worst case we will merely assert at startup. */
-extern Int evCheckSzB_MIPS ( void );
+extern Int evCheckSzB_MIPS ( VexEndness endness_host );
/* Perform a chaining and unchaining of an XDirect jump. */
-extern VexInvalRange chainXDirect_MIPS ( void* place_to_chain,
+extern VexInvalRange chainXDirect_MIPS ( VexEndness endness_host,
+ void* place_to_chain,
void* disp_cp_chain_me_EXPECTED,
void* place_to_jump_to,
Bool mode64 );
-extern VexInvalRange unchainXDirect_MIPS ( void* place_to_unchain,
+extern VexInvalRange unchainXDirect_MIPS ( VexEndness endness_host,
+ void* place_to_unchain,
void* place_to_jump_to_EXPECTED,
void* disp_cp_chain_me,
Bool mode64 );
/* Patch the counter location into an existing ProfInc point. */
-extern VexInvalRange patchProfInc_MIPS ( void* place_to_patch,
+extern VexInvalRange patchProfInc_MIPS ( VexEndness endness_host,
+ void* place_to_patch,
ULong* location_of_counter,
Bool mode64 );
-#endif /* ndef __LIBVEX_HOST_MIPS_HDEFS_H */
+#endif /* ndef __VEX_HOST_MIPS_DEFS_H */
/*---------------------------------------------------------------*/
/*--- end host-mips_defs.h ---*/
Modified: trunk/priv/host_mips_isel.c
==============================================================================
--- trunk/priv/host_mips_isel.c (original)
+++ trunk/priv/host_mips_isel.c Thu Jul 24 12:42:03 2014
@@ -4173,6 +4173,10 @@
|| VEX_PRID_COMP_BROADCOM == hwcaps_host
|| VEX_PRID_COMP_NETLOGIC);
+ /* Check that the host's endianness is as expected. */
+ vassert(archinfo_host->endness == VexEndnessLE
+ || archinfo_host->endness == VexEndnessBE);
+
mode64 = arch_host != VexArchMIPS32;
#if (__mips_fpr==64)
fp_mode64 = ((VEX_MIPS_REV(hwcaps_host) == VEX_PRID_CPU_32FPR)
Modified: trunk/priv/host_ppc_defs.c
==============================================================================
--- trunk/priv/host_ppc_defs.c (original)
+++ trunk/priv/host_ppc_defs.c Thu Jul 24 12:42:03 2014
@@ -3720,7 +3720,7 @@
*/
Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,
UChar* buf, Int nbuf, PPCInstr* i,
- Bool mode64,
+ Bool mode64, VexEndness endness_host,
void* disp_cp_chain_me_to_slowEP,
void* disp_cp_chain_me_to_fastEP,
void* disp_cp_xindir,
@@ -5707,7 +5707,7 @@
/* nofail: */
/* Crosscheck */
- vassert(evCheckSzB_PPC() == (UChar*)p - (UChar*)p0);
+ vassert(evCheckSzB_PPC(endness_host) == (UChar*)p - (UChar*)p0);
goto done;
}
@@ -5772,7 +5772,7 @@
/* How big is an event check? See case for Pin_EvCheck in
emit_PPCInstr just above. That crosschecks what this returns, so
we can tell if we're inconsistent. */
-Int evCheckSzB_PPC ( void )
+Int evCheckSzB_PPC ( VexEndness endness_host )
{
return 28;
}
@@ -5780,11 +5780,18 @@
/* NB: what goes on here has to be very closely coordinated with the
emitInstr case for XDirect, above. */
-VexInvalRange chainXDirect_PPC ( void* place_to_chain,
+VexInvalRange chainXDirect_PPC ( VexEndness endness_host,
+ void* place_to_chain,
void* disp_cp_chain_me_EXPECTED,
void* place_to_jump_to,
Bool mode64 )
{
+ if (mode64) {
+ vassert(endness_host == VexEndnessBE); /* later: or LE */
+ } else {
+ vassert(endness_host == VexEndnessBE);
+ }
+
/* What we're expecting to see is:
imm32/64-fixed r30, disp_cp_chain_me_to_EXPECTED
mtctr r30
@@ -5825,11 +5832,18 @@
/* NB: what goes on here has to be very closely coordinated with the
emitInstr case for XDirect, above. */
-VexInvalRange unchainXDirect_PPC ( void* place_to_unchain,
+VexInvalRange unchainXDirect_PPC ( VexEndness endness_host,
+ void* place_to_unchain,
void* place_to_jump_to_EXPECTED,
void* disp_cp_chain_me,
Bool mode64 )
{
+ if (mode64) {
+ vassert(endness_host == VexEndnessBE); /* later: or LE */
+ } else {
+ vassert(endness_host == VexEndnessBE);
+ }
+
/* What we're expecting to see is:
imm32/64-fixed r30, place_to_jump_to_EXPECTED
mtctr r30
@@ -5870,10 +5884,17 @@
/* Patch the counter address into a profile inc point, as previously
created by the Pin_ProfInc case for emit_PPCInstr. */
-VexInvalRange patchProfInc_PPC ( void* place_to_patch,
+VexInvalRange patchProfInc_PPC ( VexEndness endness_host,
+ void* place_to_patch,
ULong* location_of_counter,
Bool mode64 )
{
+ if (mode64) {
+ vassert(endness_host == VexEndnessBE); /* later: or LE */
+ } else {
+ vassert(endness_host == VexEndnessBE);
+ }
+
UChar* p = (UChar*)place_to_patch;
vassert(0 == (3 & (HWord)p));
Modified: trunk/priv/host_ppc_defs.h
==============================================================================
--- trunk/priv/host_ppc_defs.h (original)
+++ trunk/priv/host_ppc_defs.h Thu Jul 24 12:42:03 2014
@@ -1138,6 +1138,7 @@
extern Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc,
UChar* buf, Int nbuf, PPCInstr* i,
Bool mode64,
+ VexEndness endness_host,
void* disp_cp_chain_me_to_slowEP,
void* disp_cp_chain_me_to_fastEP,
void* disp_cp_xindir,
@@ -1162,21 +1163,24 @@
/* How big is an event check? This is kind of a kludge because it
depends on the offsets of host_EvC_FAILADDR and
host_EvC_COUNTER. */
-extern Int evCheckSzB_PPC ( void );
+extern Int evCheckSzB_PPC ( VexEndness endness_host );
/* Perform a chaining and unchaining of an XDirect jump. */
-extern VexInvalRange chainXDirect_PPC ( void* place_to_chain,
+extern VexInvalRange chainXDirect_PPC ( VexEndness endness_host,
+ void* place_to_chain,
void* disp_cp_chain_me_EXPECTED,
void* place_to_jump_to,
Bool mode64 );
-extern VexInvalRange unchainXDirect_PPC ( void* place_to_unchain,
+extern VexInvalRange unchainXDirect_PPC ( VexEndness endness_host,
+ void* place_to_unchain,
void* place_to_jump_to_EXPECTED,
void* disp_cp_chain_me,
Bool mode64 );
/* Patch the counter location into an existing ProfInc point. */
-extern VexInvalRange patchProfInc_PPC ( void* place_to_patch,
+extern VexInvalRange patchProfInc_PPC ( VexEndness endness_host,
+ void* place_to_patch,
ULong* location_of_counter,
Bool mode64 );
Modified: trunk/priv/host_ppc_isel.c
==============================================================================
--- trunk/priv/host_ppc_isel.c (original)
+++ trunk/priv/host_ppc_isel.c Thu Jul 24 12:42:03 2014
@@ -5920,6 +5920,9 @@
vassert((hwcaps_host & mask64) == 0);
}
+ /* Check that the host's endianness is as expected. */
+ vassert(archinfo_host->endness == VexEndnessBE);
+
/* Make up an initial environment to use. */
env = LibVEX_Alloc(sizeof(ISelEnv));
env->vreg_ctr = 0;
Modified: trunk/priv/host_s390_defs.c
==============================================================================
--- trunk/priv/host_s390_defs.c (original)
+++ trunk/priv/host_s390_defs.c Thu Jul 24 12:42:03 2014
@@ -9831,7 +9831,8 @@
The dispatch counter is a 32-bit value. */
static UChar *
-s390_insn_evcheck_emit(UChar *buf, const s390_insn *insn)
+s390_insn_evcheck_emit(UChar *buf, const s390_insn *insn,
+ VexEndness endness_host)
{
s390_amode *amode;
UInt b, d;
@@ -9867,7 +9868,7 @@
/* Make sure the size of the generated code is identical to the size
returned by evCheckSzB_S390 */
- vassert(evCheckSzB_S390() == code_end - code_begin);
+ vassert(evCheckSzB_S390(endness_host) == code_end - code_begin);
return buf;
}
@@ -9896,7 +9897,8 @@
Int
emit_S390Instr(Bool *is_profinc, UChar *buf, Int nbuf, s390_insn *insn,
- Bool mode64, void *disp_cp_chain_me_to_slowEP,
+ Bool mode64, VexEndness endness_host,
+ void *disp_cp_chain_me_to_slowEP,
void *disp_cp_chain_me_to_fastEP, void *disp_cp_xindir,
void *disp_cp_xassisted)
{
@@ -10057,7 +10059,7 @@
break;
case S390_INSN_EVCHECK:
- end = s390_insn_evcheck_emit(buf, insn);
+ end = s390_insn_evcheck_emit(buf, insn, endness_host);
break;
case S390_INSN_XDIRECT:
@@ -10087,7 +10089,7 @@
/* Return the number of bytes emitted for an S390_INSN_EVCHECK.
See s390_insn_evcheck_emit */
Int
-evCheckSzB_S390(void)
+evCheckSzB_S390(VexEndness endness_host)
{
return s390_host_has_gie ? 18 : 24;
}
@@ -10096,7 +10098,8 @@
/* Patch the counter address into CODE_TO_PATCH as previously
generated by s390_insn_profinc_emit. */
VexInvalRange
-patchProfInc_S390(void *code_to_patch, ULong *location_of_counter)
+patchProfInc_S390(VexEndness endness_host,
+ void *code_to_patch, ULong *location_of_counter)
{
vassert(sizeof(ULong *) == 8);
@@ -10114,10 +10117,13 @@
/* NB: what goes on here has to be very closely coordinated with the
s390_insn_xdirect_emit code above. */
VexInvalRange
-chainXDirect_S390(void *place_to_chain,
+chainXDirect_S390(VexEndness endness_host,
+ void *place_to_chain,
void *disp_cp_chain_me_EXPECTED,
void *place_to_jump_to)
{
+ vassert(endness_host == VexEndnessBE);
+
/* What we're expecting to see @ PLACE_TO_CHAIN is:
load tchain_scratch, #disp_cp_chain_me_EXPECTED
@@ -10199,10 +10205,13 @@
/* NB: what goes on here has to be very closely coordinated with the
s390_insn_xdirect_emit code above. */
VexInvalRange
-unchainXDirect_S390(void *place_to_unchain,
+unchainXDirect_S390(VexEndness endness_host,
+ void *place_to_unchain,
void *place_to_jump_to_EXPECTED,
void *disp_cp_chain_me)
{
+ vassert(endness_host == VexEndnessBE);
+
/* What we're expecting to see @ PLACE_TO_UNCHAIN:
load tchain_scratch, #place_to_jump_to_EXPECTED
Modified: trunk/priv/host_s390_defs.h
==============================================================================
--- trunk/priv/host_s390_defs.h (original)
+++ trunk/priv/host_s390_defs.h Thu Jul 24 12:42:03 2014
@@ -736,7 +736,7 @@
void mapRegs_S390Instr ( HRegRemap *, s390_insn *, Bool );
Bool isMove_S390Instr ( s390_insn *, HReg *, HReg * );
Int emit_S390Instr ( Bool *, UChar *, Int, s390_insn *, Bool,
- void *, void *, void *, void *);
+ VexEndness, void *, void *, void *, void *);
void getAllocableRegs_S390( Int *, HReg **, Bool );
void genSpill_S390 ( HInstr **, HInstr **, HReg , Int , Bool );
void genReload_S390 ( HInstr **, HInstr **, HReg , Int , Bool );
@@ -745,19 +745,22 @@
Int, Int, Bool, Bool, Addr64);
/* Return the number of bytes of code needed for an event check */
-Int evCheckSzB_S390(void);
+Int evCheckSzB_S390(VexEndness endness_host);
/* Perform a chaining and unchaining of an XDirect jump. */
-VexInvalRange chainXDirect_S390(void *place_to_chain,
+VexInvalRange chainXDirect_S390(VexEndness endness_host,
+ void *place_to_chain,
void *disp_cp_chain_me_EXPECTED,
void *place_to_jump_to);
-VexInvalRange unchainXDirect_S390(void *place_to_unchain,
+VexInvalRange unchainXDirect_S390(VexEndness endness_host,
+ void *place_to_unchain,
void *place_to_jump_to_EXPECTED,
void *disp_cp_chain_me);
/* Patch the counter location into an existing ProfInc point. */
-VexInvalRange patchProfInc_S390(void *code_to_patch,
+VexInvalRange patchProfInc_S390(VexEndness endness_host,
+ void *code_to_patch,
ULong *location_of_counter);
/* KLUDGE: See detailled comment in host_s390_defs.c. */
Modified: trunk/priv/host_s390_isel.c
==============================================================================
--- trunk/priv/host_s390_isel.c (original)
+++ trunk/priv/host_s390_isel.c Thu Jul 24 12:42:03 2014
@@ -4094,6 +4094,9 @@
/* Do some sanity checks */
vassert((VEX_HWCAPS_S390X(hwcaps_host) & ~(VEX_HWCAPS_S390X_ALL)) == 0);
+ /* Check that the host's endianness is as expected. */
+ vassert(archinfo_host->endness == VexEndnessBE);
+
/* Make up an initial environment to use. */
env = LibVEX_Alloc(sizeof(ISelEnv));
env->vreg_ctr = 0;
Modified: trunk/priv/host_x86_defs.c
==============================================================================
--- trunk/priv/host_x86_defs.c (original)
+++ trunk/priv/host_x86_defs.c Thu Jul 24 12:42:03 2014
@@ -2102,7 +2102,7 @@
Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc,
UChar* buf, Int nbuf, X86Instr* i,
- Bool mode64,
+ Bool mode64, VexEndness endness_host,
void* disp_cp_chain_me_to_slowEP,
void* disp_cp_chain_me_to_fastEP,
void* disp_cp_xindir,
@@ -3291,7 +3291,7 @@
p = doAMode_M(p, fake(4), i->Xin.EvCheck.amFailAddr);
vassert(p - p0 == 8); /* also ensures that 0x03 offset above is ok */
/* And crosscheck .. */
- vassert(evCheckSzB_X86() == 8);
+ vassert(evCheckSzB_X86(endness_host) == 8);
goto done;
}
@@ -3336,7 +3336,7 @@
/* How big is an event check? See case for Xin_EvCheck in
emit_X86Instr just above. That crosschecks what this returns, so
we can tell if we're inconsistent. */
-Int evCheckS...
[truncated message content] |
|
From: Christian B. <bor...@de...> - 2014-07-24 04:08:54
|
valgrind revision: 14183 VEX revision: 2909 C compiler: gcc (SUSE Linux) 4.3.4 [gcc-4_3-branch revision 152973] GDB: GNU gdb (GDB) SUSE (7.5.1-0.7.29) Assembler: GNU assembler (GNU Binutils; SUSE Linux Enterprise 11) 2.23.1 C library: GNU C Library stable release version 2.11.3 (20110527) uname -mrs: Linux 3.0.101-0.31-default s390x Vendor version: Welcome to SUSE Linux Enterprise Server 11 SP3 (s390x) - Kernel %r (%t). Nightly build on sless390 ( SUSE Linux Enterprise Server 11 SP3 gcc 4.3.4 on z196 (s390x) ) Started at 2014-07-24 03:45:01 CEST Ended at 2014-07-24 06:08:40 CEST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 657 tests, 3 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/origin5-bz2 (stderr) helgrind/tests/pth_cond_destroy_busy (stderr) helgrind/tests/tc20_verifywrap (stderr) --tools=none,memcheck,callgrind,helgrind,cachegrind,drd,massif --reps=3 --vg=../valgrind-new --vg=../valgrind-old -- Running tests in perf ---------------------------------------------- -- bigcode1 -- bigcode1 valgrind-new:0.23s no: 4.7s (20.5x, -----) me: 6.2s (27.0x, -----) ca:26.4s (114.8x, -----) he: 5.8s (25.0x, -----) ca: 9.1s (39.7x, -----) dr: 4.8s (21.0x, -----) ma: 4.9s (21.5x, -----) bigcode1 valgrind-old:0.23s no: 4.7s (20.4x, 0.4%) me: 6.2s (26.8x, 0.6%) ca:26.4s (114.8x, 0.0%) he: 5.8s (25.0x, 0.2%) ca: 9.1s (39.7x, -0.1%) dr: 4.8s (21.0x, 0.2%) ma: 4.9s (21.3x, 0.8%) -- bigcode2 -- bigcode2 valgrind-new:0.24s no: 7.7s (31.9x, -----) me:13.2s (54.9x, -----) ca:39.5s (164.5x, -----) he:10.8s (45.1x, -----) ca:14.2s (59.3x, -----) dr: 9.0s (37.4x, -----) ma: 8.3s (34.5x, -----) bigcode2 valgrind-old:0.24s no: 7.7s (32.0x, -0.1%) me:13.1s (54.6x, 0.6%) ca:39.5s (164.6x, -0.0%) he:10.7s (44.5x, 1.2%) ca:14.3s (59.5x, -0.4%) dr: 9.0s (37.5x, -0.3%) ma: 8.3s (34.5x, 0.0%) -- bz2 -- bz2 valgrind-new:0.69s no: 5.9s ( 8.6x, -----) me:12.7s (18.4x, -----) ca:30.6s (44.4x, -----) he:19.5s (28.3x, -----) ca:34.3s (49.8x, -----) dr:29.0s (42.1x, -----) ma: 5.2s ( 7.6x, -----) bz2 valgrind-old:0.69s no: 5.9s ( 8.6x, 0.2%) me:12.7s (18.4x, 0.1%) ca:30.6s (44.4x, -0.1%) he:19.6s (28.4x, -0.2%) ca:34.3s (49.7x, 0.0%) dr:28.8s (41.8x, 0.8%) ma: 5.2s ( 7.6x, -0.6%) -- fbench -- fbench valgrind-new:0.41s no: 1.6s ( 3.9x, -----) me: 4.2s (10.3x, -----) ca: 9.4s (23.0x, -----) he: 6.4s (15.6x, -----) ca: 7.2s (17.7x, -----) dr: 5.5s (13.5x, -----) ma: 1.6s ( 4.0x, -----) fbench valgrind-old:0.41s no: 1.6s ( 3.9x, 0.6%) me: 4.3s (10.4x, -0.7%) ca: 9.4s (22.9x, 0.4%) he: 6.3s (15.4x, 0.8%) ca: 7.2s (17.6x, 0.1%) dr: 5.6s (13.6x, -0.5%) ma: 1.6s ( 4.0x, 0.6%) -- ffbench -- ffbench valgrind-new:0.21s no: 1.1s ( 5.2x, -----) me: 3.0s (14.1x, -----) ca: 3.0s (14.3x, -----) he:42.9s (204.3x, -----) ca: 9.6s (45.9x, -----) dr: 6.9s (32.8x, -----) ma: 1.0s ( 4.6x, -----) ffbench valgrind-old:0.21s no: 1.1s ( 5.3x, -0.9%) me: 3.0s (14.1x, 0.0%) ca: 3.0s (14.3x, -0.3%) he:42.9s (204.5x, -0.1%) ca: 9.6s (45.8x, 0.2%) dr: 6.9s (32.9x, -0.1%) ma: 1.0s ( 4.6x, 1.0%) -- heap -- heap valgrind-new:0.23s no: 2.1s ( 9.3x, -----) me: 8.8s (38.1x, -----) ca:13.2s (57.2x, -----) he:12.8s (55.8x, -----) ca:11.4s (49.5x, -----) dr: 7.8s (33.7x, -----) ma: 7.8s (34.1x, -----) heap valgrind-old:0.23s no: 2.2s ( 9.5x, -1.4%) me: 9.0s (39.1x, -2.6%) ca:13.2s (57.2x, -0.1%) he:12.8s (55.7x, 0.3%) ca:11.4s (49.4x, 0.1%) dr: 7.7s (33.4x, 0.8%) ma: 7.8s (33.9x, 0.5%) -- heap_pdb4 -- heap_pdb4 valgrind-new:0.22s no: 2.4s (11.0x, -----) me:12.8s (58.4x, -----) ca:14.2s (64.7x, -----) he:14.0s (63.5x, -----) ca:12.3s (56.1x, -----) dr: 8.7s (39.4x, -----) ma: 8.0s (36.5x, -----) heap_pdb4 valgrind-old:0.22s no: 2.4s (10.8x, 1.7%) me:13.0s (59.1x, -1.2%) ca:14.2s (64.8x, -0.1%) he:14.0s (63.8x, -0.4%) ca:12.4s (56.3x, -0.3%) dr: 8.6s (39.1x, 0.7%) ma: 8.0s (36.3x, 0.7%) -- many-loss-records -- many-loss-records valgrind-new:0.02s no: 0.5s (26.0x, -----) me: 2.1s (105.0x, -----) ca: 1.9s (97.0x, -----) he: 2.1s (107.0x, -----) ca: 1.9s (96.0x, -----) dr: 1.8s (88.0x, -----) ma: 1.6s (82.0x, -----) many-loss-records valgrind-old:0.02s no: 0.5s (25.5x, 1.9%) me: 2.1s (106.5x, -1.4%) ca: 1.9s (97.0x, 0.0%) he: 2.1s (107.5x, -0.5%) ca: 1.9s (96.0x, 0.0%) dr: 1.8s (87.5x, 0.6%) ma: 1.6s (82.5x, -0.6%) -- many-xpts -- many-xpts valgrind-new:0.06s no: 0.7s (11.2x, -----) me: 3.2s (52.8x, -----) ca:366.7s (6111.2x, -----) he: 6.6s (109.8x, -----) ca: 2.8s (46.8x, -----) dr: 2.5s (42.0x, -----) ma: 2.6s (42.8x, -----) many-xpts valgrind-old:0.06s no: 0.7s (11.0x, 1.5%) me: 3.2s (54.0x, -2.2%) ca:371.7s (6195.7x, -1.4%) he: 6.6s (110.0x, -0.2%) ca: 2.8s (46.8x, 0.0%) dr: 2.5s (42.0x, 0.0%) ma: 2.5s (42.5x, 0.8%) -- sarp -- sarp valgrind-new:0.03s no: 0.6s (20.3x, -----) me: 3.5s (115.3x, -----) ca: 3.1s (104.7x, -----) he:17.5s (582.7x, -----) ca: 2.0s (68.0x, -----) dr: 1.3s (44.7x, -----) ma: 0.5s (16.0x, -----) sarp valgrind-old:0.03s no: 0.6s (20.0x, 1.6%) me: 3.6s (120.7x, -4.6%) ca: 3.2s (105.7x, -1.0%) he:17.7s (589.0x, -1.1%) ca: 2.0s (68.0x, 0.0%) dr: 1.3s (44.7x, 0.0%) ma: 0.5s (16.0x, 0.0%) -- tinycc -- tinycc valgrind-new:0.22s no: 3.2s (14.4x, -----) me:14.5s (66.0x, -----) ca:29.9s (136.0x, -----) he:27.7s (126.0x, -----) ca:21.2s (96.5x, -----) dr:20.6s (93.7x, -----) ma: 4.1s (18.6x, -----) tinycc valgrind-old:0.22s no: 3.2s (14.5x, -0.6%) me:14.6s (66.5x, -0.8%) ca:29.9s (136.0x, 0.0%) he:27.8s (126.5x, -0.4%) ca:21.3s (96.7x, -0.2%) dr:20.6s (93.8x, -0.1%) ma: 4.1s (18.7x, -0.7%) -- Finished tests in perf ---------------------------------------------- == 11 programs, 154 timings ================= real 110m53.964s user 110m7.146s sys 0m39.661s |
|
From: Tom H. <to...@co...> - 2014-07-24 03:27:53
|
valgrind revision: 14183 VEX revision: 2909 C compiler: gcc (GCC) 4.3.0 20080428 (Red Hat 4.3.0-8) GDB: Assembler: GNU assembler version 2.18.50.0.6-2 20080403 C library: GNU C Library stable release version 2.8 uname -mrs: Linux 3.15.3-200.fc20.x86_64 x86_64 Vendor version: Fedora release 9 (Sulphur) Nightly build on bristol ( x86_64, Fedora 9 ) Started at 2014-07-24 03:51:49 BST Ended at 2014-07-24 04:27:35 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 660 tests, 2 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/amd64/insn-pcmpistri (stderr) memcheck/tests/err_disable4 (stderr) none/tests/amd64/sse4-64 (stdout) |
|
From: Tom H. <to...@co...> - 2014-07-24 02:47:21
|
valgrind revision: 14183 VEX revision: 2909 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) GDB: GNU gdb (GDB) Fedora (7.3.1-48.fc15) Assembler: GNU assembler version 2.21.51.0.6-6.fc15 20110118 C library: GNU C Library stable release version 2.14.1 uname -mrs: Linux 3.15.3-200.fc20.x86_64 x86_64 Vendor version: Fedora release 15 (Lovelock) Nightly build on bristol ( x86_64, Fedora 15 ) Started at 2014-07-24 03:12:48 BST Ended at 2014-07-24 03:47:09 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 692 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) |
|
From: Tom H. <to...@co...> - 2014-07-24 02:38:09
|
valgrind revision: 14183 VEX revision: 2909 C compiler: gcc (GCC) 4.6.3 20120306 (Red Hat 4.6.3-2) GDB: GNU gdb (GDB) Fedora (7.3.50.20110722-16.fc16) Assembler: GNU assembler version 2.21.53.0.1-6.fc16 20110716 C library: GNU C Library development release version 2.14.90 uname -mrs: Linux 3.15.3-200.fc20.x86_64 x86_64 Vendor version: Fedora release 16 (Verne) Nightly build on bristol ( x86_64, Fedora 16 ) Started at 2014-07-24 03:02:06 BST Ended at 2014-07-24 03:37:51 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 692 tests, 1 stderr failure, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) |
|
From: Tom H. <to...@co...> - 2014-07-24 02:28:03
|
valgrind revision: 14183 VEX revision: 2909 C compiler: gcc (GCC) 4.7.2 20120921 (Red Hat 4.7.2-2) GDB: GNU gdb (GDB) Fedora (7.4.50.20120120-54.fc17) Assembler: GNU assembler version 2.22.52.0.1-10.fc17 20120131 C library: GNU C Library stable release version 2.15 uname -mrs: Linux 3.15.3-200.fc20.x86_64 x86_64 Vendor version: Fedora release 17 (Beefy Miracle) Nightly build on bristol ( x86_64, Fedora 17 (Beefy Miracle) ) Started at 2014-07-24 02:51:09 BST Ended at 2014-07-24 03:27:44 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 692 tests, 5 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == gdbserver_tests/mcinfcallRU (stderr) gdbserver_tests/mcinfcallWSRU (stderr) gdbserver_tests/mcmain_pic (stderr) memcheck/tests/err_disable4 (stderr) exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) |
|
From: Rich C. <rc...@wi...> - 2014-07-24 02:21:36
|
valgrind revision: 14183
VEX revision: 2909
C compiler: gcc (SUSE Linux) 4.8.1 20130909 [gcc-4_8-branch revision 202388]
GDB: GNU gdb (GDB; openSUSE Factory) 7.6.50.20130731-cvs
Assembler: GNU assembler (GNU Binutils; openSUSE Factory) 2.23.2
C library: GNU C Library (GNU libc) stable release version 2.18 (git )
uname -mrs: Linux 3.11.4-3-desktop x86_64
Vendor version: Welcome to openSUSE 13.1 "Bottle" Beta 1 - Kernel %r (%t).
Nightly build on rodan ( Linux 3.11.4-3-desktop x86_64 )
Started at 2014-07-23 19:22:01 CDT
Ended at 2014-07-23 21:21:23 CDT
Results unchanged from 24 hours ago
Checking out valgrind source tree ... done
Configuring valgrind ... done
Building valgrind ... done
Running regression tests ... failed
Regression test results follow
== 607 tests, 5 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures ==
memcheck/tests/err_disable3 (stderr)
memcheck/tests/err_disable4 (stderr)
memcheck/tests/threadname (stderr)
memcheck/tests/threadname_xml (stderr)
exp-sgcheck/tests/hackedbz2 (stderr)
=================================================
./valgrind-new/exp-sgcheck/tests/hackedbz2.stderr.diff-glibc28-amd64
=================================================
--- hackedbz2.stderr.exp-glibc28-amd64 2014-07-23 20:21:50.067559971 -0500
+++ hackedbz2.stderr.out 2014-07-23 21:20:09.828692412 -0500
@@ -1,7 +1,6 @@
Invalid read of size 1
- at 0x........: vex_strlen (hackedbz2.c:1006)
- by 0x........: add_to_myprintf_buf (hackedbz2.c:1284)
+ at 0x........: add_to_myprintf_buf (hackedbz2.c:1006)
by 0x........: vex_printf (hackedbz2.c:1155)
by 0x........: BZ2_compressBlock (hackedbz2.c:4039)
by 0x........: handle_compress (hackedbz2.c:4761)
=================================================
./valgrind-new/memcheck/tests/err_disable3.stderr.diff
=================================================
--- err_disable3.stderr.exp 2014-07-23 20:21:58.664654773 -0500
+++ err_disable3.stderr.out 2014-07-23 20:40:51.534054470 -0500
@@ -10,8 +10,6 @@
Thread 2:
Invalid read of size 1
at 0x........: err (err_disable3.c:25)
- by 0x........: child_fn (err_disable3.c:31)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable3.c:42)
=================================================
./valgrind-new/memcheck/tests/err_disable4.stderr.diff
=================================================
--- err_disable4.stderr.exp 2014-07-23 20:21:59.337662195 -0500
+++ err_disable4.stderr.out 2014-07-23 20:40:56.013103091 -0500
@@ -1501,8 +1501,6 @@
Thread x:
Invalid read of size 1
at 0x........: err (err_disable4.c:41)
- by 0x........: child_fn_2 (err_disable4.c:55)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable4.c:68)
=================================================
./valgrind-new/memcheck/tests/threadname.stderr.diff
=================================================
--- threadname.stderr.exp 2014-07-23 20:22:00.241672163 -0500
+++ threadname.stderr.out 2014-07-23 20:47:08.097145649 -0500
@@ -9,36 +9,12 @@
Thread 2:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_0 (threadname.c:53)
- ...
Address 0x........ is 0 bytes after a block of size 2 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: bad_things (threadname.c:15)
by 0x........: child_fn_0 (threadname.c:53)
...
-Thread 3 try1:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
- Address 0x........ is 0 bytes after a block of size 3 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
-
-Thread 4 012345678901234:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
- Address 0x........ is 0 bytes after a block of size 4 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
-
Thread 1:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
=================================================
./valgrind-new/memcheck/tests/threadname_xml.stderr.diff
=================================================
--- threadname_xml.stderr.exp 2014-07-23 20:22:00.232672064 -0500
+++ threadname_xml.stderr.out 2014-07-23 20:47:10.167168158 -0500
@@ -94,14 +94,6 @@
<file>threadname.c</file>
<line>...</line>
</frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_0</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
</stack>
<auxwhat>Address 0x........ is 0 bytes after a block of size 2 alloc'd</auxwhat>
<stack>
@@ -135,112 +127,6 @@
<error>
<unique>0x........</unique>
<tid>...</tid>
- <threadname>try1</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 3 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>malloc</fn>
- <dir>...</dir>
- <file>vg_replace_malloc.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
-</error>
-
-<error>
- <unique>0x........</unique>
- <tid>...</tid>
- <threadname>012345678901234</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_2</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 4 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
<truncated beyond 100 lines>
=================================================
./valgrind-old/exp-sgcheck/tests/hackedbz2.stderr.diff-glibc28-amd64
=================================================
--- hackedbz2.stderr.exp-glibc28-amd64 2014-07-23 19:22:31.838094534 -0500
+++ hackedbz2.stderr.out 2014-07-23 20:20:34.076721990 -0500
@@ -1,7 +1,6 @@
Invalid read of size 1
- at 0x........: vex_strlen (hackedbz2.c:1006)
- by 0x........: add_to_myprintf_buf (hackedbz2.c:1284)
+ at 0x........: add_to_myprintf_buf (hackedbz2.c:1006)
by 0x........: vex_printf (hackedbz2.c:1155)
by 0x........: BZ2_compressBlock (hackedbz2.c:4039)
by 0x........: handle_compress (hackedbz2.c:4761)
=================================================
./valgrind-old/memcheck/tests/err_disable3.stderr.diff
=================================================
--- err_disable3.stderr.exp 2014-07-23 19:22:33.512113173 -0500
+++ err_disable3.stderr.out 2014-07-23 19:41:26.343714922 -0500
@@ -10,8 +10,6 @@
Thread 2:
Invalid read of size 1
at 0x........: err (err_disable3.c:25)
- by 0x........: child_fn (err_disable3.c:31)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable3.c:42)
=================================================
./valgrind-old/memcheck/tests/err_disable4.stderr.diff
=================================================
--- err_disable4.stderr.exp 2014-07-23 19:22:35.141131312 -0500
+++ err_disable4.stderr.out 2014-07-23 19:41:30.819764671 -0500
@@ -1501,8 +1501,6 @@
Thread x:
Invalid read of size 1
at 0x........: err (err_disable4.c:41)
- by 0x........: child_fn_2 (err_disable4.c:55)
- ...
Address 0x........ is 5 bytes inside a block of size 10 free'd
at 0x........: free (vg_replace_malloc.c:...)
by 0x........: main (err_disable4.c:68)
=================================================
./valgrind-old/memcheck/tests/threadname.stderr.diff
=================================================
--- threadname.stderr.exp 2014-07-23 19:22:32.705104187 -0500
+++ threadname.stderr.out 2014-07-23 19:47:42.246892433 -0500
@@ -9,36 +9,12 @@
Thread 2:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_0 (threadname.c:53)
- ...
Address 0x........ is 0 bytes after a block of size 2 alloc'd
at 0x........: malloc (vg_replace_malloc.c:...)
by 0x........: bad_things (threadname.c:15)
by 0x........: child_fn_0 (threadname.c:53)
...
-Thread 3 try1:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
- Address 0x........ is 0 bytes after a block of size 3 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_1 (threadname.c:38)
- ...
-
-Thread 4 012345678901234:
-Invalid write of size 1
- at 0x........: bad_things (threadname.c:16)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
- Address 0x........ is 0 bytes after a block of size 4 alloc'd
- at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: bad_things (threadname.c:15)
- by 0x........: child_fn_2 (threadname.c:26)
- ...
-
Thread 1:
Invalid write of size 1
at 0x........: bad_things (threadname.c:16)
=================================================
./valgrind-old/memcheck/tests/threadname_xml.stderr.diff
=================================================
--- threadname_xml.stderr.exp 2014-07-23 19:22:32.797105212 -0500
+++ threadname_xml.stderr.out 2014-07-23 19:47:44.317915471 -0500
@@ -94,14 +94,6 @@
<file>threadname.c</file>
<line>...</line>
</frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_0</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
</stack>
<auxwhat>Address 0x........ is 0 bytes after a block of size 2 alloc'd</auxwhat>
<stack>
@@ -135,112 +127,6 @@
<error>
<unique>0x........</unique>
<tid>...</tid>
- <threadname>try1</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 3 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>malloc</fn>
- <dir>...</dir>
- <file>vg_replace_malloc.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_1</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
-</error>
-
-<error>
- <unique>0x........</unique>
- <tid>...</tid>
- <threadname>012345678901234</threadname>
- <kind>InvalidWrite</kind>
- <what>Invalid write of size 1</what>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>bad_things</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
- <fn>child_fn_2</fn>
- <dir>...</dir>
- <file>threadname.c</file>
- <line>...</line>
- </frame>
- </stack>
- <auxwhat>Address 0x........ is 0 bytes after a block of size 4 alloc'd</auxwhat>
- <stack>
- <frame>
- <ip>0x........</ip>
- <obj>...</obj>
<truncated beyond 100 lines>
|
|
From: Tom H. <to...@co...> - 2014-07-24 02:18:25
|
valgrind revision: 14183 VEX revision: 2909 C compiler: gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8) GDB: GNU gdb (GDB) Fedora 7.5.1-42.fc18 Assembler: GNU assembler version 2.23.51.0.1-10.fc18 20120806 C library: GNU C Library stable release version 2.16 uname -mrs: Linux 3.15.3-200.fc20.x86_64 x86_64 Vendor version: Fedora release 18 (Spherical Cow) Nightly build on bristol ( x86_64, Fedora 18 (Spherical Cow) ) Started at 2014-07-24 02:41:13 BST Ended at 2014-07-24 03:18:08 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 692 tests, 2 stderr failures, 1 stdout failure, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) exp-sgcheck/tests/preen_invars (stdout) exp-sgcheck/tests/preen_invars (stderr) |
|
From: Tom H. <to...@co...> - 2014-07-24 02:09:36
|
valgrind revision: 14183 VEX revision: 2909 C compiler: gcc (GCC) 4.8.3 20140624 (Red Hat 4.8.3-1) GDB: GNU gdb (GDB) Fedora 7.6.1-46.fc19 Assembler: GNU assembler version 2.23.52.0.1-9.fc19 20130226 C library: GNU C Library (GNU libc) stable release version 2.17 uname -mrs: Linux 3.15.3-200.fc20.x86_64 x86_64 Vendor version: Fedora release 19 (Schrödingerâs Cat) Nightly build on bristol ( x86_64, Fedora 19 (Schrödingerâs Cat) ) Started at 2014-07-24 02:31:28 BST Ended at 2014-07-24 03:09:22 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 692 tests, 2 stderr failures, 0 stdout failures, 0 stderrB failures, 0 stdoutB failures, 0 post failures == memcheck/tests/err_disable4 (stderr) exp-sgcheck/tests/hackedbz2 (stderr) |