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From: <sv...@va...> - 2014-07-21 19:55:26
|
Author: philippe
Date: Mon Jul 21 19:55:11 2014
New Revision: 14179
Log:
Add a new heuristic 'length64' to detect interior pointers
pointing at offset 64bit of a block, when the first 8 bytes contains
the block size - 8. This is e.g. used by sqlite3MemMalloc.
Patch by Matthias Schwarzott (with small modif)
Modified:
trunk/NEWS
trunk/gdbserver_tests/mchelp.stdoutB.exp
trunk/memcheck/docs/mc-manual.xml
trunk/memcheck/mc_include.h
trunk/memcheck/mc_leakcheck.c
trunk/memcheck/mc_main.c
trunk/memcheck/tests/leak_cpp_interior.cpp
trunk/memcheck/tests/leak_cpp_interior.stderr.exp
trunk/memcheck/tests/leak_cpp_interior.stderr.exp-64bit
trunk/memcheck/tests/leak_cpp_interior.vgtest
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Mon Jul 21 19:55:11 2014
@@ -13,6 +13,9 @@
- new client requests
VALGRIND_DISABLE_ADDR_ERROR_REPORTING_IN_RANGE and
VALGRIND_ENABLE_ADDR_ERROR_REPORTING_IN_RANGE
+ - new leak check heuristic 'length64' to detect interior pointers
+ pointing at offset 64bit of a block, when the first 8 bytes contains
+ the block size - 8. This is e.g. used by sqlite3MemMalloc.
* Helgrind:
- Helgrind GDB server monitor command 'info locks' giving
@@ -184,6 +187,7 @@
336957 Add a section about the Solaris/illumos port on the webpage
337094 ifunc wrapper is broken on ppc64
337285 fcntl commands F_OFD_SETLK, F_OFD_SETLKW, and F_OFD_GETLK not supported
+337528 leak check heuristic for block prefixed by length as 64bit number
n-i-bz Fix KVM_CREATE_IRQCHIP ioctl handling
n-i-bz s390x: Fix memory corruption for multithreaded applications
n-i-bz vex arm->IR: allow PC as basereg in some LDRD cases
Modified: trunk/gdbserver_tests/mchelp.stdoutB.exp
==============================================================================
--- trunk/gdbserver_tests/mchelp.stdoutB.exp (original)
+++ trunk/gdbserver_tests/mchelp.stdoutB.exp Mon Jul 21 19:55:11 2014
@@ -31,7 +31,8 @@
[unlimited*|limited <max_loss_records_output>]
* = defaults
where kind is one of definite indirect possible reachable all none
- where heur is one of stdstring newarray multipleinheritance all none*
+ where heur is one of stdstring length64 newarray
+ multipleinheritance all none*
Examples: leak_check
leak_check summary any
leak_check full kinds indirect,possible
@@ -90,7 +91,8 @@
[unlimited*|limited <max_loss_records_output>]
* = defaults
where kind is one of definite indirect possible reachable all none
- where heur is one of stdstring newarray multipleinheritance all none*
+ where heur is one of stdstring length64 newarray
+ multipleinheritance all none*
Examples: leak_check
leak_check summary any
leak_check full kinds indirect,possible
Modified: trunk/memcheck/docs/mc-manual.xml
==============================================================================
--- trunk/memcheck/docs/mc-manual.xml (original)
+++ trunk/memcheck/docs/mc-manual.xml Mon Jul 21 19:55:11 2014
@@ -462,6 +462,21 @@
</listitem>
<listitem>
+ <para>It might be a pointer to the inner char array of a C++
+ <computeroutput>std::string</computeroutput>. For example, some
+ compilers add 3 words at the beginning of the std::string to
+ store the length, the capacity and a reference count before the
+ memory containing the array of characters. They return a pointer
+ just after these 3 words, pointing at the char array.</para>
+ </listitem>
+
+ <listitem>
+ <para>Some code might allocate a block of memory, and use the first 8
+ bytes to store (block size - 8) as a 64bit number.
+ <computeroutput>sqlite3MemMalloc</computeroutput> does this.</para>
+ </listitem>
+
+ <listitem>
<para>It might be a pointer to an array of C++ objects (which possess
destructors) allocated with <computeroutput>new[]</computeroutput>. In
this case, some compilers store a "magic cookie" containing the array
@@ -472,15 +487,6 @@
</listitem>
<listitem>
- <para>It might be a pointer to the inner char array of a C++
- <computeroutput>std::string</computeroutput>. For example, some
- compilers add 3 words at the beginning of the std::string to
- store the length, the capacity and a reference count before the
- memory containing the array of characters. They return a pointer
- just after these 3 words, pointing at the char array.</para>
- </listitem>
-
- <listitem>
<para>It might be a pointer to an inner part of a C++ object using
multiple inheritance. </para>
</listitem>
@@ -488,9 +494,10 @@
<para>You can optionally activate heuristics to use during the leak
search to detect the interior pointers corresponding to
-the <computeroutput>newarray</computeroutput>,
-<computeroutput>stdstring</computeroutput> and
-<computeroutput>multipleinheritance</computeroutput> cases. If the
+the <computeroutput>stdstring</computeroutput>,
+<computeroutput>length64</computeroutput>,
+<computeroutput>newarray</computeroutput>
+and <computeroutput>multipleinheritance</computeroutput> cases. If the
heuristic detects that an interior pointer corresponds to such a case,
the block will be considered as reachable by the interior
pointer. In other words, the interior pointer will be treated
@@ -599,8 +606,8 @@
<para>If heuristics have been used to consider some blocks as
reachable, the leak summary details the heuristically reachable subset
-of 'still reachable:' per heuristic. In the below example, of the 79
-bytes still reachable, 71 bytes (56+7+8) have been considered
+of 'still reachable:' per heuristic. In the below example, of the 95
+bytes still reachable, 87 bytes (56+7+8+16) have been considered
heuristically reachable.
</para>
@@ -609,9 +616,10 @@
definitely lost: 4 bytes in 1 blocks
indirectly lost: 0 bytes in 0 blocks
possibly lost: 0 bytes in 0 blocks
- still reachable: 79 bytes in 5 blocks
+ still reachable: 95 bytes in 6 blocks
of which reachable via heuristic:
stdstring : 56 bytes in 2 blocks
+ length64 : 16 bytes in 1 blocks
newarray : 7 bytes in 1 blocks
multipleinheritance: 8 bytes in 1 blocks
suppressed: 0 bytes in 0 blocks
@@ -810,13 +818,13 @@
<itemizedlist>
<listitem><para>a comma separated list of one or more of
- <option>stdstring newarray multipleinheritance</option>.</para>
+ <option>stdstring length64 newarray multipleinheritance</option>.</para>
</listitem>
<listitem><para><option>all</option> to activate the complete set of
heuristics.
It is equivalent to
- <option>--leak-check-heuristics=stdstring,newarray,multipleinheritance</option>.</para>
+ <option>--leak-check-heuristics=stdstring,length64,newarray,multipleinheritance</option>.</para>
</listitem>
<listitem><para><option>none</option> for the empty set.</para>
Modified: trunk/memcheck/mc_include.h
==============================================================================
--- trunk/memcheck/mc_include.h (original)
+++ trunk/memcheck/mc_include.h Mon Jul 21 19:55:11 2014
@@ -513,18 +513,23 @@
LchStdString =1,
// Consider interior pointer pointing at the array of char in a
// std::string as reachable.
- LchNewArray =2,
+ LchLength64 =2,
+ // Consider interior pointer pointing at offset 64bit of a block as
+ // reachable, when the first 8 bytes contains the block size - 8.
+ // Such length+interior pointers are used by e.g. sqlite3MemMalloc.
+ // On 64bit platforms LchNewArray will also match these blocks.
+ LchNewArray =3,
// Consider interior pointer pointing at second word of a new[] array as
// reachable. Such interior pointers are used for arrays whose elements
// have a destructor.
- LchMultipleInheritance =3,
+ LchMultipleInheritance =4,
// Conside interior pointer pointing just after what looks a vtable
// as reachable.
}
LeakCheckHeuristic;
// Nr of heuristics, including the LchNone heuristic.
-#define N_LEAK_CHECK_HEURISTICS 4
+#define N_LEAK_CHECK_HEURISTICS 5
// Build mask to check or set Heuristic h membership
#define H2S(h) (1 << (h))
@@ -532,7 +537,8 @@
#define HiS(h,s) ((s) & R2S(h))
// A set with all Heuristics:
#define HallS \
- (H2S(LchStdString) | H2S(LchNewArray) | H2S(LchMultipleInheritance))
+ (H2S(LchStdString) | H2S(LchLength64) | H2S(LchNewArray) | \
+ H2S(LchMultipleInheritance))
/* Heuristics set to use for the leak search.
Default : no heuristic. */
Modified: trunk/memcheck/mc_leakcheck.c
==============================================================================
--- trunk/memcheck/mc_leakcheck.c (original)
+++ trunk/memcheck/mc_leakcheck.c Mon Jul 21 19:55:11 2014
@@ -594,6 +594,7 @@
switch(h) {
case LchNone: return "none";
case LchStdString: return "stdstring";
+ case LchLength64: return "length64";
case LchNewArray: return "newarray";
case LchMultipleInheritance: return "multipleinheritance";
default: return "???invalid heuristic???";
@@ -672,6 +673,16 @@
return False;
}
+// true if a is properly aligned and points to 64bits of valid memory
+static Bool is_valid_aligned_ULong ( Addr a )
+{
+ if (sizeof(Word) == 8)
+ return MC_(is_valid_aligned_word)(a);
+
+ return MC_(is_valid_aligned_word)(a)
+ && MC_(is_valid_aligned_word)(a + 4);
+}
+
// If ch is heuristically reachable via an heuristic member of heur_set,
// returns this heuristic.
// If ch cannot be considered reachable using one of these heuristics,
@@ -712,6 +723,23 @@
}
}
+ if (HiS(LchLength64, heur_set)) {
+ // Detects inner pointers that point at 64bit offset (8 bytes) into a
+ // block following the length of the remaining as 64bit number
+ // (=total block size - 8).
+ // This is used e.g. by sqlite for tracking the total size of allocated
+ // memory.
+ // Note that on 64bit platforms, a block matching LchLength64 will
+ // also be matched by LchNewArray.
+ if ( ptr == ch->data + sizeof(ULong)
+ && is_valid_aligned_ULong(ch->data)) {
+ const ULong size = *((ULong*)ch->data);
+ if (size > 0 && (ch->szB - sizeof(ULong)) == size) {
+ return LchLength64;
+ }
+ }
+ }
+
if (HiS(LchNewArray, heur_set)) {
// Detects inner pointers at second word of new[] array, following
// a plausible nr of elements.
@@ -1058,7 +1086,7 @@
MC_(pp_describe_addr) (ptr);
if (lc_is_a_chunk_ptr(addr, &ch_no, &ch, &ex) ) {
Int h;
- for (h = LchStdString; h <= LchMultipleInheritance; h++) {
+ for (h = LchStdString; h < N_LEAK_CHECK_HEURISTICS; h++) {
if (heuristic_reachedness(addr, ch, ex, H2S(h)) == h) {
VG_(umsg)("block at %#lx considered reachable "
"by ptr %#lx using %s heuristic\n",
Modified: trunk/memcheck/mc_main.c
==============================================================================
--- trunk/memcheck/mc_main.c (original)
+++ trunk/memcheck/mc_main.c Mon Jul 21 19:55:11 2014
@@ -5197,8 +5197,9 @@
static Bool MC_(parse_leak_heuristics) ( const HChar *str0, UInt *lhs )
{
- return VG_(parse_enum_set) ("-,stdstring,newarray,multipleinheritance",
- str0, lhs);
+ return
+ VG_(parse_enum_set) ("-,stdstring,length64,newarray,multipleinheritance",
+ str0, lhs);
}
@@ -5370,7 +5371,8 @@
" where kind is one of definite indirect possible reachable all none\n"
" --leak-check-heuristics=heur1,heur2,... which heuristics to use for\n"
" improving leak search false positive [none]\n"
-" where heur is one of stdstring newarray multipleinheritance all none\n"
+" where heur is one of stdstring length64 newarray\n"
+" multipleinheritance all none\n"
" --show-reachable=yes same as --show-leak-kinds=all\n"
" --show-reachable=no --show-possibly-lost=yes\n"
" same as --show-leak-kinds=definite,possible\n"
@@ -5508,7 +5510,8 @@
" [unlimited*|limited <max_loss_records_output>]\n"
" * = defaults\n"
" where kind is one of definite indirect possible reachable all none\n"
-" where heur is one of stdstring newarray multipleinheritance all none*\n"
+" where heur is one of stdstring length64 newarray\n"
+" multipleinheritance all none*\n"
" Examples: leak_check\n"
" leak_check summary any\n"
" leak_check full kinds indirect,possible\n"
Modified: trunk/memcheck/tests/leak_cpp_interior.cpp
==============================================================================
--- trunk/memcheck/tests/leak_cpp_interior.cpp (original)
+++ trunk/memcheck/tests/leak_cpp_interior.cpp Mon Jul 21 19:55:11 2014
@@ -1,5 +1,7 @@
#include <stdio.h>
#include <unistd.h>
+#include <stdint.h>
+#include <stdlib.h>
#include <string>
#include <sstream>
#include "../memcheck.h"
@@ -7,6 +9,8 @@
class MyClass
{
+ char m1;
+ int m2;
public:
~MyClass()
{ fprintf(stderr, "destruct MyClass\n");
@@ -65,6 +69,23 @@
}
};
+void* wrap64_malloc(int size)
+{
+ uint64_t *p = (uint64_t*)malloc(size + 8);
+ *p = size;
+ ++p;
+ return p;
+}
+
+void wrap64_free(void *p)
+{
+ uint64_t *p2 = (uint64_t*)p;
+ if (p2 == NULL)
+ return;
+ --p2;
+ free(p2);
+}
+
std::string str;
std::string str2;
MyClass *ptr;
@@ -73,6 +94,7 @@
Ae *ptrACe;
B *ptrBC;
A *ptrAC;
+void* ptr64;
char who_points_at_cmd[100];
@@ -81,6 +103,7 @@
str = "Valgrind"; // interior ptr.
str2 = str;
ptr = new MyClass[3]; // interior ptr.
+ ptr64 = wrap64_malloc(23);
// prepare the who_points_at cmd we will run.
// Do it here to avoid having ptr or its exterior ptr kept in a register.
@@ -112,9 +135,19 @@
(void) VALGRIND_MONITOR_COMMAND("leak_check summary heuristics multipleinheritance");
fprintf(stderr, "leak_check summary any heuristics newarray\n");
(void) VALGRIND_MONITOR_COMMAND("leak_check summary heuristics newarray");
+ fprintf(stderr, "leak_check summary heuristics length64\n");
+ (void) VALGRIND_MONITOR_COMMAND("leak_check summary heuristics length64");
fprintf(stderr, "leak_check summary heuristics stdstring\n");
(void) VALGRIND_MONITOR_COMMAND("leak_check summary heuristics stdstring");
+ // check all and none
+ fprintf(stderr, "leak_check summary heuristics multipleinheritance,newarray,stdstring,length64\n");
+ (void) VALGRIND_MONITOR_COMMAND("leak_check summary heuristics multipleinheritance,newarray,stdstring,length64");
+ fprintf(stderr, "leak_check summary heuristics all\n");
+ (void) VALGRIND_MONITOR_COMMAND("leak_check summary heuristics all");
+ fprintf(stderr, "leak_check summary heuristics none\n");
+ (void) VALGRIND_MONITOR_COMMAND("leak_check summary heuristics none");
+
// Test the who_points_at when the block is pointed to with an interior ptr.
(void) VALGRIND_MONITOR_COMMAND(who_points_at_cmd);
@@ -124,6 +157,7 @@
delete ptrACe;
delete ptrBC;
delete ptrAC;
+ wrap64_free(ptr64);
fprintf(stderr, "Finished!\n");
return 0;
}
Modified: trunk/memcheck/tests/leak_cpp_interior.stderr.exp
==============================================================================
--- trunk/memcheck/tests/leak_cpp_interior.stderr.exp (original)
+++ trunk/memcheck/tests/leak_cpp_interior.stderr.exp Mon Jul 21 19:55:11 2014
@@ -2,17 +2,18 @@
valgrind output will go to log
VALGRIND_DO_LEAK_CHECK
4 bytes in 1 blocks are definitely lost in loss record ... of ...
- by 0x........: doit() (leak_cpp_interior.cpp:89)
- by 0x........: main (leak_cpp_interior.cpp:104)
+ by 0x........: doit() (leak_cpp_interior.cpp:112)
+ by 0x........: main (leak_cpp_interior.cpp:127)
LEAK SUMMARY:
definitely lost: 4 bytes in 1 blocks
indirectly lost: 0 bytes in 0 blocks
possibly lost: 0 bytes in 0 blocks
- still reachable: 111 bytes in 7 blocks
+ still reachable: 163 bytes in 8 blocks
of which reachable via heuristic:
stdstring : 56 bytes in 2 blocks
- newarray : 7 bytes in 1 blocks
+ length64 : 31 bytes in 1 blocks
+ newarray : 28 bytes in 1 blocks
multipleinheritance: 24 bytes in 2 blocks
suppressed: 0 bytes in 0 blocks
Reachable blocks (those to which a pointer was found) are not shown.
@@ -22,11 +23,12 @@
LEAK SUMMARY:
definitely lost: 4 (+0) bytes in 1 (+0) blocks
indirectly lost: 0 (+0) bytes in 0 (+0) blocks
- possibly lost: 63 (+63) bytes in 3 (+3) blocks
- still reachable: 48 (-63) bytes in 4 (-3) blocks
+ possibly lost: 115 (+115) bytes in 4 (+4) blocks
+ still reachable: 48 (-115) bytes in 4 (-4) blocks
of which reachable via heuristic:
stdstring : 0 (-56) bytes in 0 (-2) blocks
- newarray : 0 (-7) bytes in 0 (-1) blocks
+ length64 : 0 (-31) bytes in 0 (-1) blocks
+ newarray : 0 (-28) bytes in 0 (-1) blocks
multipleinheritance: 24 (+0) bytes in 2 (+0) blocks
suppressed: 0 (+0) bytes in 0 (+0) blocks
To see details of leaked memory, give 'full' arg to leak_check
@@ -35,23 +37,77 @@
LEAK SUMMARY:
definitely lost: 4 (+0) bytes in 1 (+0) blocks
indirectly lost: 0 (+0) bytes in 0 (+0) blocks
- possibly lost: 80 (+17) bytes in 4 (+1) blocks
- still reachable: 31 (-17) bytes in 3 (-1) blocks
+ possibly lost: 111 (-4) bytes in 5 (+1) blocks
+ still reachable: 52 (+4) bytes in 3 (-1) blocks
of which reachable via heuristic:
- newarray : 7 (+7) bytes in 1 (+1) blocks
+ newarray : 28 (+28) bytes in 1 (+1) blocks
multipleinheritance: 0 (-24) bytes in 0 (-2) blocks
suppressed: 0 (+0) bytes in 0 (+0) blocks
To see details of leaked memory, give 'full' arg to leak_check
+leak_check summary heuristics length64
+LEAK SUMMARY:
+ definitely lost: 4 (+0) bytes in 1 (+0) blocks
+ indirectly lost: 0 (+0) bytes in 0 (+0) blocks
+ possibly lost: 108 (-3) bytes in 5 (+0) blocks
+ still reachable: 55 (+3) bytes in 3 (+0) blocks
+ of which reachable via heuristic:
+ length64 : 31 (+31) bytes in 1 (+1) blocks
+ newarray : 0 (-28) bytes in 0 (-1) blocks
+ suppressed: 0 (+0) bytes in 0 (+0) blocks
+To see details of leaked memory, give 'full' arg to leak_check
+
leak_check summary heuristics stdstring
LEAK SUMMARY:
definitely lost: 4 (+0) bytes in 1 (+0) blocks
indirectly lost: 0 (+0) bytes in 0 (+0) blocks
- possibly lost: 31 (-49) bytes in 3 (-1) blocks
- still reachable: 80 (+49) bytes in 4 (+1) blocks
+ possibly lost: 83 (-25) bytes in 4 (-1) blocks
+ still reachable: 80 (+25) bytes in 4 (+1) blocks
of which reachable via heuristic:
stdstring : 56 (+56) bytes in 2 (+2) blocks
- newarray : 0 (-7) bytes in 0 (-1) blocks
+ length64 : 0 (-31) bytes in 0 (-1) blocks
+ suppressed: 0 (+0) bytes in 0 (+0) blocks
+To see details of leaked memory, give 'full' arg to leak_check
+
+leak_check summary heuristics multipleinheritance,newarray,stdstring,length64
+LEAK SUMMARY:
+ definitely lost: 4 (+0) bytes in 1 (+0) blocks
+ indirectly lost: 0 (+0) bytes in 0 (+0) blocks
+ possibly lost: 0 (-83) bytes in 0 (-4) blocks
+ still reachable: 163 (+83) bytes in 8 (+4) blocks
+ of which reachable via heuristic:
+ stdstring : 56 (+0) bytes in 2 (+0) blocks
+ length64 : 31 (+31) bytes in 1 (+1) blocks
+ newarray : 28 (+28) bytes in 1 (+1) blocks
+ multipleinheritance: 24 (+24) bytes in 2 (+2) blocks
+ suppressed: 0 (+0) bytes in 0 (+0) blocks
+To see details of leaked memory, give 'full' arg to leak_check
+
+leak_check summary heuristics all
+LEAK SUMMARY:
+ definitely lost: 4 (+0) bytes in 1 (+0) blocks
+ indirectly lost: 0 (+0) bytes in 0 (+0) blocks
+ possibly lost: 0 (+0) bytes in 0 (+0) blocks
+ still reachable: 163 (+0) bytes in 8 (+0) blocks
+ of which reachable via heuristic:
+ stdstring : 56 (+0) bytes in 2 (+0) blocks
+ length64 : 31 (+0) bytes in 1 (+0) blocks
+ newarray : 28 (+0) bytes in 1 (+0) blocks
+ multipleinheritance: 24 (+0) bytes in 2 (+0) blocks
+ suppressed: 0 (+0) bytes in 0 (+0) blocks
+To see details of leaked memory, give 'full' arg to leak_check
+
+leak_check summary heuristics none
+LEAK SUMMARY:
+ definitely lost: 4 (+0) bytes in 1 (+0) blocks
+ indirectly lost: 0 (+0) bytes in 0 (+0) blocks
+ possibly lost: 139 (+139) bytes in 6 (+6) blocks
+ still reachable: 24 (-139) bytes in 2 (-6) blocks
+ of which reachable via heuristic:
+ stdstring : 0 (-56) bytes in 0 (-2) blocks
+ length64 : 0 (-31) bytes in 0 (-1) blocks
+ newarray : 0 (-28) bytes in 0 (-1) blocks
+ multipleinheritance: 0 (-24) bytes in 0 (-2) blocks
suppressed: 0 (+0) bytes in 0 (+0) blocks
To see details of leaked memory, give 'full' arg to leak_check
@@ -78,7 +134,7 @@
HEAP SUMMARY:
in use at exit: 0 bytes in 0 blocks
- total heap usage: 8 allocs, 8 frees, 115 bytes allocated
+ total heap usage: 9 allocs, 9 frees, 167 bytes allocated
All heap blocks were freed -- no leaks are possible
Modified: trunk/memcheck/tests/leak_cpp_interior.stderr.exp-64bit
==============================================================================
--- trunk/memcheck/tests/leak_cpp_interior.stderr.exp-64bit (original)
+++ trunk/memcheck/tests/leak_cpp_interior.stderr.exp-64bit Mon Jul 21 19:55:11 2014
@@ -2,17 +2,18 @@
valgrind output will go to log
VALGRIND_DO_LEAK_CHECK
8 bytes in 1 blocks are definitely lost in loss record ... of ...
- by 0x........: doit() (leak_cpp_interior.cpp:89)
- by 0x........: main (leak_cpp_interior.cpp:104)
+ by 0x........: doit() (leak_cpp_interior.cpp:112)
+ by 0x........: main (leak_cpp_interior.cpp:127)
LEAK SUMMARY:
definitely lost: 8 bytes in 1 blocks
indirectly lost: 0 bytes in 0 blocks
possibly lost: 0 bytes in 0 blocks
- still reachable: 187 bytes in 7 blocks
+ still reachable: 239 bytes in 8 blocks
of which reachable via heuristic:
stdstring : 80 bytes in 2 blocks
- newarray : 11 bytes in 1 blocks
+ length64 : 31 bytes in 1 blocks
+ newarray : 32 bytes in 1 blocks
multipleinheritance: 48 bytes in 2 blocks
suppressed: 0 bytes in 0 blocks
Reachable blocks (those to which a pointer was found) are not shown.
@@ -22,11 +23,12 @@
LEAK SUMMARY:
definitely lost: 8 (+0) bytes in 1 (+0) blocks
indirectly lost: 0 (+0) bytes in 0 (+0) blocks
- possibly lost: 91 (+91) bytes in 3 (+3) blocks
- still reachable: 96 (-91) bytes in 4 (-3) blocks
+ possibly lost: 143 (+143) bytes in 4 (+4) blocks
+ still reachable: 96 (-143) bytes in 4 (-4) blocks
of which reachable via heuristic:
stdstring : 0 (-80) bytes in 0 (-2) blocks
- newarray : 0 (-11) bytes in 0 (-1) blocks
+ length64 : 0 (-31) bytes in 0 (-1) blocks
+ newarray : 0 (-32) bytes in 0 (-1) blocks
multipleinheritance: 48 (+0) bytes in 2 (+0) blocks
suppressed: 0 (+0) bytes in 0 (+0) blocks
To see details of leaked memory, give 'full' arg to leak_check
@@ -35,23 +37,77 @@
LEAK SUMMARY:
definitely lost: 8 (+0) bytes in 1 (+0) blocks
indirectly lost: 0 (+0) bytes in 0 (+0) blocks
- possibly lost: 128 (+37) bytes in 4 (+1) blocks
- still reachable: 59 (-37) bytes in 3 (-1) blocks
+ possibly lost: 128 (-15) bytes in 4 (+0) blocks
+ still reachable: 111 (+15) bytes in 4 (+0) blocks
of which reachable via heuristic:
- newarray : 11 (+11) bytes in 1 (+1) blocks
+ newarray : 63 (+63) bytes in 2 (+2) blocks
multipleinheritance: 0 (-48) bytes in 0 (-2) blocks
suppressed: 0 (+0) bytes in 0 (+0) blocks
To see details of leaked memory, give 'full' arg to leak_check
+leak_check summary heuristics length64
+LEAK SUMMARY:
+ definitely lost: 8 (+0) bytes in 1 (+0) blocks
+ indirectly lost: 0 (+0) bytes in 0 (+0) blocks
+ possibly lost: 160 (+32) bytes in 5 (+1) blocks
+ still reachable: 79 (-32) bytes in 3 (-1) blocks
+ of which reachable via heuristic:
+ length64 : 31 (+31) bytes in 1 (+1) blocks
+ newarray : 0 (-63) bytes in 0 (-2) blocks
+ suppressed: 0 (+0) bytes in 0 (+0) blocks
+To see details of leaked memory, give 'full' arg to leak_check
+
leak_check summary heuristics stdstring
LEAK SUMMARY:
definitely lost: 8 (+0) bytes in 1 (+0) blocks
indirectly lost: 0 (+0) bytes in 0 (+0) blocks
- possibly lost: 59 (-69) bytes in 3 (-1) blocks
- still reachable: 128 (+69) bytes in 4 (+1) blocks
+ possibly lost: 111 (-49) bytes in 4 (-1) blocks
+ still reachable: 128 (+49) bytes in 4 (+1) blocks
of which reachable via heuristic:
stdstring : 80 (+80) bytes in 2 (+2) blocks
- newarray : 0 (-11) bytes in 0 (-1) blocks
+ length64 : 0 (-31) bytes in 0 (-1) blocks
+ suppressed: 0 (+0) bytes in 0 (+0) blocks
+To see details of leaked memory, give 'full' arg to leak_check
+
+leak_check summary heuristics multipleinheritance,newarray,stdstring,length64
+LEAK SUMMARY:
+ definitely lost: 8 (+0) bytes in 1 (+0) blocks
+ indirectly lost: 0 (+0) bytes in 0 (+0) blocks
+ possibly lost: 0 (-111) bytes in 0 (-4) blocks
+ still reachable: 239 (+111) bytes in 8 (+4) blocks
+ of which reachable via heuristic:
+ stdstring : 80 (+0) bytes in 2 (+0) blocks
+ length64 : 31 (+31) bytes in 1 (+1) blocks
+ newarray : 32 (+32) bytes in 1 (+1) blocks
+ multipleinheritance: 48 (+48) bytes in 2 (+2) blocks
+ suppressed: 0 (+0) bytes in 0 (+0) blocks
+To see details of leaked memory, give 'full' arg to leak_check
+
+leak_check summary heuristics all
+LEAK SUMMARY:
+ definitely lost: 8 (+0) bytes in 1 (+0) blocks
+ indirectly lost: 0 (+0) bytes in 0 (+0) blocks
+ possibly lost: 0 (+0) bytes in 0 (+0) blocks
+ still reachable: 239 (+0) bytes in 8 (+0) blocks
+ of which reachable via heuristic:
+ stdstring : 80 (+0) bytes in 2 (+0) blocks
+ length64 : 31 (+0) bytes in 1 (+0) blocks
+ newarray : 32 (+0) bytes in 1 (+0) blocks
+ multipleinheritance: 48 (+0) bytes in 2 (+0) blocks
+ suppressed: 0 (+0) bytes in 0 (+0) blocks
+To see details of leaked memory, give 'full' arg to leak_check
+
+leak_check summary heuristics none
+LEAK SUMMARY:
+ definitely lost: 8 (+0) bytes in 1 (+0) blocks
+ indirectly lost: 0 (+0) bytes in 0 (+0) blocks
+ possibly lost: 191 (+191) bytes in 6 (+6) blocks
+ still reachable: 48 (-191) bytes in 2 (-6) blocks
+ of which reachable via heuristic:
+ stdstring : 0 (-80) bytes in 0 (-2) blocks
+ length64 : 0 (-31) bytes in 0 (-1) blocks
+ newarray : 0 (-32) bytes in 0 (-1) blocks
+ multipleinheritance: 0 (-48) bytes in 0 (-2) blocks
suppressed: 0 (+0) bytes in 0 (+0) blocks
To see details of leaked memory, give 'full' arg to leak_check
@@ -78,7 +134,7 @@
HEAP SUMMARY:
in use at exit: 0 bytes in 0 blocks
- total heap usage: 8 allocs, 8 frees, 195 bytes allocated
+ total heap usage: 9 allocs, 9 frees, 247 bytes allocated
All heap blocks were freed -- no leaks are possible
Modified: trunk/memcheck/tests/leak_cpp_interior.vgtest
==============================================================================
--- trunk/memcheck/tests/leak_cpp_interior.vgtest (original)
+++ trunk/memcheck/tests/leak_cpp_interior.vgtest Mon Jul 21 19:55:11 2014
@@ -1,2 +1,2 @@
prog: leak_cpp_interior
-vgopts: --leak-check=summary --leak-check-heuristics=multipleinheritance,stdstring,newarray
+vgopts: --leak-check=summary --leak-check-heuristics=multipleinheritance,stdstring,newarray,length64
|
|
From: <sv...@va...> - 2014-07-21 09:22:07
|
Author: sewardj
Date: Mon Jul 21 09:21:57 2014
New Revision: 14178
Log:
Track vex r2907, which amongst other things, renamed Iop_QDMulLong* to
Iop_QDMull*.
Modified:
trunk/memcheck/mc_translate.c
trunk/memcheck/tests/vbit-test/irops.c
trunk/memcheck/tests/vbit-test/util.c
Modified: trunk/memcheck/mc_translate.c
==============================================================================
--- trunk/memcheck/mc_translate.c (original)
+++ trunk/memcheck/mc_translate.c Mon Jul 21 09:21:57 2014
@@ -3361,13 +3361,13 @@
case Iop_Mull32Sx2:
case Iop_Mull32Ux2:
- case Iop_QDMulLong32Sx2:
+ case Iop_QDMull32Sx2:
return vectorWidenI64(mce, Iop_Widen32Sto64x2,
mkUifU64(mce, vatom1, vatom2));
case Iop_Mull16Sx4:
case Iop_Mull16Ux4:
- case Iop_QDMulLong16Sx4:
+ case Iop_QDMull16Sx4:
return vectorWidenI64(mce, Iop_Widen16Sto32x4,
mkUifU64(mce, vatom1, vatom2));
Modified: trunk/memcheck/tests/vbit-test/irops.c
==============================================================================
--- trunk/memcheck/tests/vbit-test/irops.c (original)
+++ trunk/memcheck/tests/vbit-test/irops.c Mon Jul 21 09:21:57 2014
@@ -702,8 +702,8 @@
{ DEFOP(Iop_QDMulHi32Sx4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_QRDMulHi16Sx8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_QRDMulHi32Sx4, UNDEF_UNKNOWN), },
- { DEFOP(Iop_QDMulLong16Sx4, UNDEF_UNKNOWN), },
- { DEFOP(Iop_QDMulLong32Sx2, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_QDMull16Sx4, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_QDMull32Sx2, UNDEF_UNKNOWN), },
{ DEFOP(Iop_PolynomialMul8x16, UNDEF_UNKNOWN), },
{ DEFOP(Iop_PolynomialMull8x8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_PwAdd8x16, UNDEF_UNKNOWN), },
Modified: trunk/memcheck/tests/vbit-test/util.c
==============================================================================
--- trunk/memcheck/tests/vbit-test/util.c (original)
+++ trunk/memcheck/tests/vbit-test/util.c Mon Jul 21 09:21:57 2014
@@ -779,7 +779,7 @@
case Iop_ExtractV128:
TERNARY(Ity_V128, Ity_V128, Ity_I8, Ity_V128);
- case Iop_QDMulLong16Sx4: case Iop_QDMulLong32Sx2:
+ case Iop_QDMull16Sx4: case Iop_QDMull32Sx2:
BINARY(Ity_I64, Ity_I64, Ity_V128);
/* s390 specific */
|
|
From: <sv...@va...> - 2014-07-21 09:21:00
|
Author: sewardj
Date: Mon Jul 21 09:20:53 2014
New Revision: 14177
Log:
Enable tests for: sqneg, {u,s}q{add,sub} (scalar),
{sqdmlal,sqdmlsl,sqdmull} (vector x element).
Modified:
trunk/none/tests/arm64/fp_and_simd.c
Modified: trunk/none/tests/arm64/fp_and_simd.c
==============================================================================
--- trunk/none/tests/arm64/fp_and_simd.c (original)
+++ trunk/none/tests/arm64/fp_and_simd.c Mon Jul 21 09:20:53 2014
@@ -4275,10 +4275,10 @@
if (1) test_sqabs_s_s(TyS);
if (1) test_sqabs_h_h(TyH);
if (1) test_sqabs_b_b(TyB);
- if (0) test_sqneg_d_d(TyD);
- if (0) test_sqneg_s_s(TyS);
- if (0) test_sqneg_h_h(TyH);
- if (0) test_sqneg_b_b(TyB);
+ if (1) test_sqneg_d_d(TyD);
+ if (1) test_sqneg_s_s(TyS);
+ if (1) test_sqneg_h_h(TyH);
+ if (1) test_sqneg_b_b(TyB);
// sqabs 2d,4s,2s,8h,4h,16b,8b
// sqneg 2d,4s,2s,8h,4h,16b,8b
@@ -4289,34 +4289,34 @@
if (1) test_sqabs_4h_4h(TyH);
if (1) test_sqabs_16b_16b(TyB);
if (1) test_sqabs_8b_8b(TyB);
- if (0) test_sqneg_2d_2d(TyD);
- if (0) test_sqneg_4s_4s(TyS);
- if (0) test_sqneg_2s_2s(TyS);
- if (0) test_sqneg_8h_8h(TyH);
- if (0) test_sqneg_4h_4h(TyH);
- if (0) test_sqneg_16b_16b(TyB);
- if (0) test_sqneg_8b_8b(TyB);
+ if (1) test_sqneg_2d_2d(TyD);
+ if (1) test_sqneg_4s_4s(TyS);
+ if (1) test_sqneg_2s_2s(TyS);
+ if (1) test_sqneg_8h_8h(TyH);
+ if (1) test_sqneg_4h_4h(TyH);
+ if (1) test_sqneg_16b_16b(TyB);
+ if (1) test_sqneg_8b_8b(TyB);
// sqadd d,s,h,b
// uqadd d,s,h,b
// sqsub d,s,h,b
// uqsub d,s,h,b
- if (0) test_sqadd_d_d_d(TyD);
- if (0) test_sqadd_s_s_s(TyS);
- if (0) test_sqadd_h_h_h(TyH);
- if (0) test_sqadd_b_b_b(TyB);
- if (0) test_uqadd_d_d_d(TyD);
- if (0) test_uqadd_s_s_s(TyS);
- if (0) test_uqadd_h_h_h(TyH);
- if (0) test_uqadd_b_b_b(TyB);
- if (0) test_sqsub_d_d_d(TyD);
- if (0) test_sqsub_s_s_s(TyS);
- if (0) test_sqsub_h_h_h(TyH);
- if (0) test_sqsub_b_b_b(TyB);
- if (0) test_uqsub_d_d_d(TyD);
- if (0) test_uqsub_s_s_s(TyS);
- if (0) test_uqsub_h_h_h(TyH);
- if (0) test_uqsub_b_b_b(TyB);
+ if (1) test_sqadd_d_d_d(TyD);
+ if (1) test_sqadd_s_s_s(TyS);
+ if (1) test_sqadd_h_h_h(TyH);
+ if (1) test_sqadd_b_b_b(TyB);
+ if (1) test_uqadd_d_d_d(TyD);
+ if (1) test_uqadd_s_s_s(TyS);
+ if (1) test_uqadd_h_h_h(TyH);
+ if (1) test_uqadd_b_b_b(TyB);
+ if (1) test_sqsub_d_d_d(TyD);
+ if (1) test_sqsub_s_s_s(TyS);
+ if (1) test_sqsub_h_h_h(TyH);
+ if (1) test_sqsub_b_b_b(TyB);
+ if (1) test_uqsub_d_d_d(TyD);
+ if (1) test_uqsub_s_s_s(TyS);
+ if (1) test_uqsub_h_h_h(TyH);
+ if (1) test_uqsub_b_b_b(TyB);
// sqadd 2d,4s,2s,8h,4h,16b,8b
// uqadd 2d,4s,2s,8h,4h,16b,8b
@@ -4370,30 +4370,30 @@
// sqdmlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
// sqdmlsl{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
// sqdmull{2} 2d_2s/4s_s[], 4s_4h/2h_h[]
- if (0) test_sqdmlal_2d_2s_s0(TyS);
- if (0) test_sqdmlal_2d_2s_s3(TyS);
- if (0) test_sqdmlal2_2d_4s_s1(TyS);
- if (0) test_sqdmlal2_2d_4s_s2(TyS);
- if (0) test_sqdmlal_4s_4h_h0(TyH);
- if (0) test_sqdmlal_4s_4h_h7(TyH);
- if (0) test_sqdmlal2_4s_8h_h1(TyH);
- if (0) test_sqdmlal2_4s_8h_h4(TyH);
- if (0) test_sqdmlsl_2d_2s_s0(TyS);
- if (0) test_sqdmlsl_2d_2s_s3(TyS);
- if (0) test_sqdmlsl2_2d_4s_s1(TyS);
- if (0) test_sqdmlsl2_2d_4s_s2(TyS);
- if (0) test_sqdmlsl_4s_4h_h0(TyH);
- if (0) test_sqdmlsl_4s_4h_h7(TyH);
- if (0) test_sqdmlsl2_4s_8h_h1(TyH);
- if (0) test_sqdmlsl2_4s_8h_h4(TyH);
- if (0) test_sqdmull_2d_2s_s0(TyS);
- if (0) test_sqdmull_2d_2s_s3(TyS);
- if (0) test_sqdmull2_2d_4s_s1(TyS);
- if (0) test_sqdmull2_2d_4s_s2(TyS);
- if (0) test_sqdmull_4s_4h_h0(TyH);
- if (0) test_sqdmull_4s_4h_h7(TyH);
- if (0) test_sqdmull2_4s_8h_h1(TyH);
- if (0) test_sqdmull2_4s_8h_h4(TyH);
+ if (1) test_sqdmlal_2d_2s_s0(TyS);
+ if (1) test_sqdmlal_2d_2s_s3(TyS);
+ if (1) test_sqdmlal2_2d_4s_s1(TyS);
+ if (1) test_sqdmlal2_2d_4s_s2(TyS);
+ if (1) test_sqdmlal_4s_4h_h0(TyH);
+ if (1) test_sqdmlal_4s_4h_h7(TyH);
+ if (1) test_sqdmlal2_4s_8h_h1(TyH);
+ if (1) test_sqdmlal2_4s_8h_h4(TyH);
+ if (1) test_sqdmlsl_2d_2s_s0(TyS);
+ if (1) test_sqdmlsl_2d_2s_s3(TyS);
+ if (1) test_sqdmlsl2_2d_4s_s1(TyS);
+ if (1) test_sqdmlsl2_2d_4s_s2(TyS);
+ if (1) test_sqdmlsl_4s_4h_h0(TyH);
+ if (1) test_sqdmlsl_4s_4h_h7(TyH);
+ if (1) test_sqdmlsl2_4s_8h_h1(TyH);
+ if (1) test_sqdmlsl2_4s_8h_h4(TyH);
+ if (1) test_sqdmull_2d_2s_s0(TyS);
+ if (1) test_sqdmull_2d_2s_s3(TyS);
+ if (1) test_sqdmull2_2d_4s_s1(TyS);
+ if (1) test_sqdmull2_2d_4s_s2(TyS);
+ if (1) test_sqdmull_4s_4h_h0(TyH);
+ if (1) test_sqdmull_4s_4h_h7(TyH);
+ if (1) test_sqdmull2_4s_8h_h1(TyH);
+ if (1) test_sqdmull2_4s_8h_h4(TyH);
// sqdmlal d_s_s, s_h_h
// sqdmlsl d_s_s, s_h_h
|
Author: sewardj
Date: Mon Jul 21 09:19:50 2014
New Revision: 2907
Log:
arm64: implement: sqneg, {u,s}q{add,sub} (scalar),
{sqdmlal,sqdmlsl,sqdmull} (vector x element)
As part of this, rename Iop_QDMulLong* to Iop_QDMull* so as to be
consistent with their non-saturating equivalents.
Modified:
trunk/priv/guest_arm64_toIR.c
trunk/priv/guest_arm_toIR.c
trunk/priv/host_arm64_defs.c
trunk/priv/host_arm64_defs.h
trunk/priv/host_arm64_isel.c
trunk/priv/host_arm_isel.c
trunk/priv/ir_defs.c
trunk/pub/libvex_ir.h
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Mon Jul 21 09:19:50 2014
@@ -384,6 +384,27 @@
/* Initialise V128 temporaries en masse. */
static
+void newTempsV128_2(IRTemp* t1, IRTemp* t2)
+{
+ vassert(t1 && *t1 == IRTemp_INVALID);
+ vassert(t2 && *t2 == IRTemp_INVALID);
+ *t1 = newTempV128();
+ *t2 = newTempV128();
+}
+
+/* Initialise V128 temporaries en masse. */
+static
+void newTempsV128_3(IRTemp* t1, IRTemp* t2, IRTemp* t3)
+{
+ vassert(t1 && *t1 == IRTemp_INVALID);
+ vassert(t2 && *t2 == IRTemp_INVALID);
+ vassert(t3 && *t3 == IRTemp_INVALID);
+ *t1 = newTempV128();
+ *t2 = newTempV128();
+ *t3 = newTempV128();
+}
+
+static
void newTempsV128_7(IRTemp* t1, IRTemp* t2, IRTemp* t3,
IRTemp* t4, IRTemp* t5, IRTemp* t6, IRTemp* t7)
{
@@ -710,6 +731,13 @@
return ops[sizeNarrow];
}
+static IROp mkVecQDMULLS ( UInt sizeNarrow ) {
+ const IROp ops[4]
+ = { Iop_INVALID, Iop_QDMull16Sx4, Iop_QDMull32Sx2, Iop_INVALID };
+ vassert(sizeNarrow < 3);
+ return ops[sizeNarrow];
+}
+
static IROp mkVecCMPEQ ( UInt size ) {
const IROp ops[4]
= { Iop_CmpEQ8x16, Iop_CmpEQ16x8, Iop_CmpEQ32x4, Iop_CmpEQ64x2 };
@@ -6223,15 +6251,117 @@
}
-static IRTemp math_ZERO_ALL_EXCEPT_LOWEST_LANE ( IRTemp src, UInt size )
+/* Compute vector SQNEG at lane size |size| for |srcE|, returning
+ the q result in |*qneg| and the normal result in |*nneg|. */
+static
+void math_SQNEG ( /*OUT*/IRTemp* qneg, /*OUT*/IRTemp* nneg,
+ IRExpr* srcE, UInt size )
+{
+ IRTemp src = IRTemp_INVALID;
+ newTempsV128_3(&src, nneg, qneg);
+ assign(src, srcE);
+ assign(*nneg, binop(mkVecSUB(size), mkV128(0x0000), mkexpr(src)));
+ assign(*qneg, binop(mkVecQSUBS(size), mkV128(0x0000), mkexpr(src)));
+}
+
+
+static IRTemp math_ZERO_ALL_EXCEPT_LOWEST_LANE ( IRExpr* srcE, UInt size )
{
vassert(size < 4);
IRTemp t = newTempV128();
- assign(t, unop(mkVecZEROHIxxOFV128(size), mkexpr(src)));
+ assign(t, unop(mkVecZEROHIxxOFV128(size), srcE));
return t;
}
+/* Generate IR to compute vector widening MULL from either the lower
+ (is2==False) or upper (is2==True) halves of vecN and vecM. The
+ widening multiplies are unsigned when isU==True and signed when
+ isU==False. |size| is the narrow lane size indication. Optionally,
+ the product may be added to or subtracted from vecD, at the wide lane
+ size. This happens when |mas| is 'a' (add) or 's' (sub). When |mas|
+ is 'm' (only multiply) then the accumulate part does not happen, and
+ |vecD| is expected to == IRTemp_INVALID.
+
+ Only size==0 (h_b_b), size==1 (s_h_h) and size==2 (d_s_s) variants
+ are allowed. The result is returned in a new IRTemp, which is
+ returned in *res. */
+static
+void math_MULL_ACC ( /*OUT*/IRTemp* res,
+ Bool is2, Bool isU, UInt size, HChar mas,
+ IRTemp vecN, IRTemp vecM, IRTemp vecD )
+{
+ vassert(res && *res == IRTemp_INVALID);
+ vassert(size <= 2);
+ vassert(mas == 'm' || mas == 'a' || mas == 's');
+ if (mas == 'm') vassert(vecD == IRTemp_INVALID);
+ IROp mulOp = isU ? mkVecMULLU(size) : mkVecMULLS(size);
+ IROp accOp = (mas == 'a') ? mkVecADD(size+1)
+ : (mas == 's' ? mkVecSUB(size+1)
+ : Iop_INVALID);
+ IRTemp mul = math_BINARY_WIDENING_V128(is2, mulOp,
+ mkexpr(vecN), mkexpr(vecM));
+ *res = newTempV128();
+ assign(*res, mas == 'm' ? mkexpr(mul)
+ : binop(accOp, mkexpr(vecD), mkexpr(mul)));
+}
+
+
+/* Same as math_MULL_ACC, except the multiply is signed widening,
+ the multiplied value is then doubled, before being added to or
+ subtracted from the accumulated value. And everything is
+ saturated. In all cases, saturation residuals are returned
+ via (sat1q, sat1n), and in the accumulate cases,
+ via (sat2q, sat2n) too. All results are returned in new temporaries.
+ In the no-accumulate case, *sat2q and *sat2n are never instantiated,
+ so the caller can tell this has happened. */
+static
+void math_SQDMULL_ACC ( /*OUT*/IRTemp* res,
+ /*OUT*/IRTemp* sat1q, /*OUT*/IRTemp* sat1n,
+ /*OUT*/IRTemp* sat2q, /*OUT*/IRTemp* sat2n,
+ Bool is2, UInt size, HChar mas,
+ IRTemp vecN, IRTemp vecM, IRTemp vecD )
+{
+ vassert(size <= 2);
+ vassert(mas == 'm' || mas == 'a' || mas == 's');
+ /* Compute
+ sat1q = vecN.D[is2] *sq vecM.d[is2] *q 2
+ sat1n = vecN.D[is2] *s vecM.d[is2] * 2
+ IOW take either the low or high halves of vecN and vecM, signed widen,
+ multiply, double that, and signedly saturate. Also compute the same
+ but without saturation.
+ */
+ vassert(sat2q && *sat2q == IRTemp_INVALID);
+ vassert(sat2n && *sat2n == IRTemp_INVALID);
+ newTempsV128_3(sat1q, sat1n, res);
+ IRTemp tq = math_BINARY_WIDENING_V128(is2, mkVecQDMULLS(size),
+ mkexpr(vecN), mkexpr(vecM));
+ IRTemp tn = math_BINARY_WIDENING_V128(is2, mkVecMULLS(size),
+ mkexpr(vecN), mkexpr(vecM));
+ assign(*sat1q, mkexpr(tq));
+ assign(*sat1n, binop(mkVecADD(size+1), mkexpr(tn), mkexpr(tn)));
+
+ /* If there is no accumulation, the final result is sat1q,
+ and there's no assignment to sat2q or sat2n. */
+ if (mas == 'm') {
+ assign(*res, mkexpr(*sat1q));
+ return;
+ }
+
+ /* Compute
+ sat2q = vecD +sq/-sq sat1q
+ sat2n = vecD +/- sat1n
+ result = sat2q
+ */
+ newTempsV128_2(sat2q, sat2n);
+ assign(*sat2q, binop(mas == 'a' ? mkVecQADDS(size+1) : mkVecQSUBS(size+1),
+ mkexpr(vecD), mkexpr(*sat1q)));
+ assign(*sat2n, binop(mas == 'a' ? mkVecADD(size+1) : mkVecSUB(size+1),
+ mkexpr(vecD), mkexpr(*sat1n)));
+ assign(*res, mkexpr(*sat2q));
+}
+
+
/* QCFLAG tracks the SIMD sticky saturation status. Update the status
thusly: if |qres| and |nres| hold the same value, leave QCFLAG
unchanged. Otherwise, set it (implicitly) to 1. */
@@ -7151,6 +7281,7 @@
{
/* 31 29 28 23 21 20 15 10 9 4
01 U 11110 size 1 m opcode 1 n d
+ Decode fields: u,size,opcode
*/
# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
if (INSN(31,30) != BITS2(0,1)
@@ -7167,6 +7298,42 @@
UInt dd = INSN(4,0);
vassert(size < 4);
+ if (opcode == BITS5(0,0,0,0,1) || opcode == BITS5(0,0,1,0,1)) {
+ /* -------- 0,xx,00001 SQADD std4_std4_std4 -------- */
+ /* -------- 1,xx,00001 UQADD std4_std4_std4 -------- */
+ /* -------- 0,xx,00101 SQSUB std4_std4_std4 -------- */
+ /* -------- 1,xx,00101 UQSUB std4_std4_std4 -------- */
+ Bool isADD = opcode == BITS5(0,0,0,0,1);
+ Bool isU = bitU == 1;
+ IROp qop = Iop_INVALID;
+ IROp nop = Iop_INVALID;
+ if (isADD) {
+ qop = isU ? mkVecQADDU(size) : mkVecQADDS(size);
+ nop = mkVecADD(size);
+ } else {
+ qop = isU ? mkVecQSUBU(size) : mkVecQSUBS(size);
+ nop = mkVecSUB(size);
+ }
+ IRTemp argL = newTempV128();
+ IRTemp argR = newTempV128();
+ IRTemp qres = newTempV128();
+ IRTemp nres = newTempV128();
+ assign(argL, getQReg128(nn));
+ assign(argR, getQReg128(mm));
+ assign(qres, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(
+ binop(qop, mkexpr(argL), mkexpr(argR)), size)));
+ assign(nres, mkexpr(math_ZERO_ALL_EXCEPT_LOWEST_LANE(
+ binop(nop, mkexpr(argL), mkexpr(argR)), size)));
+ putQReg128(dd, mkexpr(qres));
+ updateQCFLAGwithDifference(qres, nres);
+ const HChar* nm = isADD ? (isU ? "uqadd" : "sqadd")
+ : (isU ? "uqsub" : "sqsub");
+ const HChar arr = "bhsd"[size];
+ DIP("%s %s.%c, %s.%c, %s.%c\n", nm,
+ nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
+ return True;
+ }
+
if (size == X11 && opcode == BITS5(0,0,1,1,0)) {
/* -------- 0,11,00110 CMGT d_d_d -------- */ // >s
/* -------- 1,11,00110 CMHI d_d_d -------- */ // >u
@@ -7277,16 +7444,19 @@
UInt dd = INSN(4,0);
vassert(size < 4);
- if (bitU == 0 && opcode == BITS5(0,0,1,1,1)) {
+ if (opcode == BITS5(0,0,1,1,1)) {
/* -------- 0,xx,00111 SQABS std4_std4 -------- */
- IRTemp qabs = IRTemp_INVALID, nabs = IRTemp_INVALID;
- math_SQABS(&qabs, &nabs, getQReg128(nn), size);
- IRTemp qres = math_ZERO_ALL_EXCEPT_LOWEST_LANE(qabs, size);
- IRTemp nres = math_ZERO_ALL_EXCEPT_LOWEST_LANE(nabs, size);
+ /* -------- 1,xx,00111 SQNEG std4_std4 -------- */
+ Bool isNEG = bitU == 1;
+ IRTemp qresFW = IRTemp_INVALID, nresFW = IRTemp_INVALID;
+ (isNEG ? math_SQNEG : math_SQABS)( &qresFW, &nresFW,
+ getQReg128(nn), size );
+ IRTemp qres = math_ZERO_ALL_EXCEPT_LOWEST_LANE(mkexpr(qresFW), size);
+ IRTemp nres = math_ZERO_ALL_EXCEPT_LOWEST_LANE(mkexpr(nresFW), size);
putQReg128(dd, mkexpr(qres));
updateQCFLAGwithDifference(qres, nres);
const HChar arr = "bhsd"[size];
- DIP("%s %c%u, %c%u\n", "sqabs", arr, dd, arr, nn);
+ DIP("%s %c%u, %c%u\n", isNEG ? "sqneg" : "sqabs", arr, dd, arr, nn);
return True;
}
@@ -7776,15 +7946,16 @@
vassert(ks >= 0 && ks <= 2);
if (size == X11) return False;
vassert(size <= 2);
- Bool isU = bitU == 1;
- IROp mulOp = isU ? mkVecMULLU(size) : mkVecMULLS(size);
- IROp accOp = (ks == 1) ? mkVecADD(size+1)
- : (ks == 2 ? mkVecSUB(size+1) : Iop_INVALID);
- IRTemp mul = math_BINARY_WIDENING_V128(is2, mulOp,
- getQReg128(nn), getQReg128(mm));
- IRTemp res = newTempV128();
- assign(res, ks == 0 ? mkexpr(mul)
- : binop(accOp, getQReg128(dd), mkexpr(mul)));
+ Bool isU = bitU == 1;
+ IRTemp vecN = newTempV128();
+ IRTemp vecM = newTempV128();
+ IRTemp vecD = newTempV128();
+ assign(vecN, getQReg128(nn));
+ assign(vecM, getQReg128(mm));
+ assign(vecD, getQReg128(dd));
+ IRTemp res = IRTemp_INVALID;
+ math_MULL_ACC(&res, is2, isU, size, "mas"[ks],
+ vecN, vecM, ks == 0 ? IRTemp_INVALID : vecD);
putQReg128(dd, mkexpr(res));
const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size);
const HChar* arrWide = nameArr_Q_SZ(1, size+1);
@@ -8493,18 +8664,21 @@
return True;
}
- if (bitU == 0 && opcode == BITS5(0,0,1,1,1)) {
+ if (opcode == BITS5(0,0,1,1,1)) {
/* -------- 0,xx,00111 SQABS std7_std7 -------- */
+ /* -------- 1,xx,00111 SQNEG std7_std7 -------- */
if (bitQ == 0 && size == X11) return False; // implied 1d case
- IRTemp qabs = IRTemp_INVALID, nabs = IRTemp_INVALID;
- math_SQABS(&qabs, &nabs, getQReg128(nn), size);
+ Bool isNEG = bitU == 1;
+ IRTemp qresFW = IRTemp_INVALID, nresFW = IRTemp_INVALID;
+ (isNEG ? math_SQNEG : math_SQABS)( &qresFW, &nresFW,
+ getQReg128(nn), size );
IRTemp qres = newTempV128(), nres = newTempV128();
- assign(qres, math_MAYBE_ZERO_HI64(bitQ, qabs));
- assign(nres, math_MAYBE_ZERO_HI64(bitQ, nabs));
+ assign(qres, math_MAYBE_ZERO_HI64(bitQ, qresFW));
+ assign(nres, math_MAYBE_ZERO_HI64(bitQ, nresFW));
putQReg128(dd, mkexpr(qres));
updateQCFLAGwithDifference(qres, nres);
const HChar* arr = nameArr_Q_SZ(bitQ, size);
- DIP("%s %s.%s, %s.%s\n", "sqabs",
+ DIP("%s %s.%s, %s.%s\n", isNEG ? "sqneg" : "sqabs",
nameQReg128(dd), arr, nameQReg128(nn), arr);
return True;
}
@@ -8840,19 +9014,14 @@
vassert(0);
}
vassert(mm < 32 && ix < 16);
- IROp mulOp = isU ? mkVecMULLU(size) : mkVecMULLS(size);
- IROp accOp = (ks == 1) ? mkVecADD(size+1)
- : (ks == 2 ? mkVecSUB(size+1) : Iop_INVALID);
+ IRTemp vecN = newTempV128();
IRTemp vecM = math_DUP_VEC_ELEM(getQReg128(mm), size, ix);
IRTemp vecD = newTempV128();
- IRTemp vecN = newTempV128();
- assign(vecD, getQReg128(dd));
assign(vecN, getQReg128(nn));
- IRTemp mul = math_BINARY_WIDENING_V128(is2, mulOp,
- mkexpr(vecN), mkexpr(vecM));
- IRTemp res = newTempV128();
- assign(res, ks == 0 ? mkexpr(mul)
- : binop(accOp, getQReg128(dd), mkexpr(mul)));
+ assign(vecD, getQReg128(dd));
+ IRTemp res = IRTemp_INVALID;
+ math_MULL_ACC(&res, is2, isU, size, "mas"[ks],
+ vecN, vecM, ks == 0 ? IRTemp_INVALID : vecD);
putQReg128(dd, mkexpr(res));
const HChar* nm = ks == 0 ? "mull" : (ks == 1 ? "mlal" : "mlsl");
const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size);
@@ -8865,6 +9034,64 @@
return True;
}
+ if (bitU == 0
+ && (opcode == BITS4(1,0,1,1)
+ || opcode == BITS4(0,0,1,1) || opcode == BITS4(0,1,1,1))) {
+ /* -------- 0,xx,1011 SQDMULL s/h variants only -------- */ // 0 (ks)
+ /* -------- 0,xx,0011 SQDMLAL s/h variants only -------- */ // 1
+ /* -------- 0,xx,0111 SQDMLSL s/h variants only -------- */ // 2
+ /* Widens, and size refers to the narrowed lanes. */
+ UInt ks = 3;
+ switch (opcode) {
+ case BITS4(1,0,1,1): ks = 0; break;
+ case BITS4(0,0,1,1): ks = 1; break;
+ case BITS4(0,1,1,1): ks = 2; break;
+ default: vassert(0);
+ }
+ vassert(ks >= 0 && ks <= 2);
+ Bool is2 = bitQ == 1;
+ UInt mm = 32; // invalid
+ UInt ix = 16; // invalid
+ switch (size) {
+ case X00:
+ return False; // h_b_b[] case is not allowed
+ case X01:
+ mm = mmLO4; ix = (bitH << 2) | (bitL << 1) | (bitM << 0); break;
+ case X10:
+ mm = (bitM << 4) | mmLO4; ix = (bitH << 1) | (bitL << 0); break;
+ case X11:
+ return False; // q_d_d[] case is not allowed
+ default:
+ vassert(0);
+ }
+ vassert(mm < 32 && ix < 16);
+ IRTemp vecN, vecD, res, sat1q, sat1n, sat2q, sat2n;
+ vecN = vecD = res = sat1q = sat1n = sat2q = sat2n = IRTemp_INVALID;
+ newTempsV128_2(&vecN, &vecD);
+ assign(vecN, getQReg128(nn));
+ IRTemp vecM = math_DUP_VEC_ELEM(getQReg128(mm), size, ix);
+ assign(vecD, getQReg128(dd));
+ math_SQDMULL_ACC(&res, &sat1q, &sat1n, &sat2q, &sat2n,
+ is2, size, "mas"[ks],
+ vecN, vecM, ks == 0 ? IRTemp_INVALID : vecD);
+ putQReg128(dd, mkexpr(res));
+ vassert(sat1q != IRTemp_INVALID && sat1n != IRTemp_INVALID);
+ updateQCFLAGwithDifference(sat1q, sat1n);
+ if (sat2q != IRTemp_INVALID || sat2n != IRTemp_INVALID) {
+ updateQCFLAGwithDifference(sat2q, sat2n);
+ }
+ const HChar* nm = ks == 0 ? "sqmull"
+ : (ks == 1 ? "sqdmlal" : "sqdmlsl");
+ const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size);
+ const HChar* arrWide = nameArr_Q_SZ(1, size+1);
+ HChar ch = size == X01 ? 'h' : 's';
+ DIP("%s%s %s.%s, %s.%s, %s.%c[%u]\n",
+ nm, is2 ? "2" : "",
+ nameQReg128(dd), arrWide,
+ nameQReg128(nn), arrNarrow, nameQReg128(dd), ch, ix);
+ return True;
+ }
+
return False;
# undef INSN
}
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Mon Jul 21 09:19:50 2014
@@ -5132,7 +5132,7 @@
case 0: case 3:
return False;
case 1:
- op = Iop_QDMulLong16Sx4;
+ op = Iop_QDMull16Sx4;
cmp = Iop_CmpEQ16x4;
add = P ? Iop_QSub32Sx4 : Iop_QAdd32Sx4;
op2 = P ? Iop_Sub32x4 : Iop_Add32x4;
@@ -5141,7 +5141,7 @@
imm = (imm << 32) | imm;
break;
case 2:
- op = Iop_QDMulLong32Sx2;
+ op = Iop_QDMull32Sx2;
cmp = Iop_CmpEQ32x2;
add = P ? Iop_QSub64Sx2 : Iop_QAdd64Sx2;
op2 = P ? Iop_Sub64x2 : Iop_Add64x2;
@@ -5206,14 +5206,14 @@
case 3:
return False;
case 1:
- op = Iop_QDMulLong16Sx4;
+ op = Iop_QDMull16Sx4;
op2 = Iop_CmpEQ16x4;
imm = 1LL << 15;
imm = (imm << 16) | imm;
imm = (imm << 32) | imm;
break;
case 2:
- op = Iop_QDMulLong32Sx2;
+ op = Iop_QDMull32Sx2;
op2 = Iop_CmpEQ32x2;
imm = 1LL << 31;
imm = (imm << 32) | imm;
@@ -5454,7 +5454,7 @@
case 3:
return False;
case 1:
- op = Iop_QDMulLong16Sx4;
+ op = Iop_QDMull16Sx4;
cmp = Iop_CmpEQ16x4;
add = P ? Iop_QSub32Sx4 : Iop_QAdd32Sx4;
op2 = P ? Iop_Sub32x4 : Iop_Add32x4;
@@ -5463,7 +5463,7 @@
imm = (imm << 32) | imm;
break;
case 2:
- op = Iop_QDMulLong32Sx2;
+ op = Iop_QDMull32Sx2;
cmp = Iop_CmpEQ32x2;
add = P ? Iop_QSub64Sx2 : Iop_QAdd64Sx2;
op2 = P ? Iop_Sub64x2 : Iop_Add64x2;
@@ -5667,14 +5667,14 @@
case 3:
return False;
case 1:
- op = Iop_QDMulLong16Sx4;
+ op = Iop_QDMull16Sx4;
op2 = Iop_CmpEQ16x4;
imm = 1LL << 15;
imm = (imm << 16) | imm;
imm = (imm << 32) | imm;
break;
case 2:
- op = Iop_QDMulLong32Sx2;
+ op = Iop_QDMull32Sx2;
op2 = Iop_CmpEQ32x2;
imm = 1LL << 31;
imm = (imm << 32) | imm;
Modified: trunk/priv/host_arm64_defs.c
==============================================================================
--- trunk/priv/host_arm64_defs.c (original)
+++ trunk/priv/host_arm64_defs.c Mon Jul 21 09:19:50 2014
@@ -854,97 +854,99 @@
static void showARM64VecBinOp(/*OUT*/const HChar** nm,
/*OUT*/const HChar** ar, ARM64VecBinOp op ) {
switch (op) {
- case ARM64vecb_ADD64x2: *nm = "add "; *ar = "2d"; return;
- case ARM64vecb_ADD32x4: *nm = "add "; *ar = "4s"; return;
- case ARM64vecb_ADD16x8: *nm = "add "; *ar = "8h"; return;
- case ARM64vecb_ADD8x16: *nm = "add "; *ar = "16b"; return;
- case ARM64vecb_SUB64x2: *nm = "sub "; *ar = "2d"; return;
- case ARM64vecb_SUB32x4: *nm = "sub "; *ar = "4s"; return;
- case ARM64vecb_SUB16x8: *nm = "sub "; *ar = "8h"; return;
- case ARM64vecb_SUB8x16: *nm = "sub "; *ar = "16b"; return;
- case ARM64vecb_MUL32x4: *nm = "mul "; *ar = "4s"; return;
- case ARM64vecb_MUL16x8: *nm = "mul "; *ar = "8h"; return;
- case ARM64vecb_MUL8x16: *nm = "mul "; *ar = "16b"; return;
- case ARM64vecb_FADD64x2: *nm = "fadd "; *ar = "2d"; return;
- case ARM64vecb_FSUB64x2: *nm = "fsub "; *ar = "2d"; return;
- case ARM64vecb_FMUL64x2: *nm = "fmul "; *ar = "2d"; return;
- case ARM64vecb_FDIV64x2: *nm = "fdiv "; *ar = "2d"; return;
- case ARM64vecb_FADD32x4: *nm = "fadd "; *ar = "4s"; return;
- case ARM64vecb_FSUB32x4: *nm = "fsub "; *ar = "4s"; return;
- case ARM64vecb_FMUL32x4: *nm = "fmul "; *ar = "4s"; return;
- case ARM64vecb_FDIV32x4: *nm = "fdiv "; *ar = "4s"; return;
- case ARM64vecb_UMAX32x4: *nm = "umax "; *ar = "4s"; return;
- case ARM64vecb_UMAX16x8: *nm = "umax "; *ar = "8h"; return;
- case ARM64vecb_UMAX8x16: *nm = "umax "; *ar = "16b"; return;
- case ARM64vecb_UMIN32x4: *nm = "umin "; *ar = "4s"; return;
- case ARM64vecb_UMIN16x8: *nm = "umin "; *ar = "8h"; return;
- case ARM64vecb_UMIN8x16: *nm = "umin "; *ar = "16b"; return;
- case ARM64vecb_SMAX32x4: *nm = "smax "; *ar = "4s"; return;
- case ARM64vecb_SMAX16x8: *nm = "smax "; *ar = "8h"; return;
- case ARM64vecb_SMAX8x16: *nm = "smax "; *ar = "16b"; return;
- case ARM64vecb_SMIN32x4: *nm = "smin "; *ar = "4s"; return;
- case ARM64vecb_SMIN16x8: *nm = "smin "; *ar = "8h"; return;
- case ARM64vecb_SMIN8x16: *nm = "smin "; *ar = "16b"; return;
- case ARM64vecb_AND: *nm = "and "; *ar = "16b"; return;
- case ARM64vecb_ORR: *nm = "orr "; *ar = "16b"; return;
- case ARM64vecb_XOR: *nm = "eor "; *ar = "16b"; return;
- case ARM64vecb_CMEQ64x2: *nm = "cmeq "; *ar = "2d"; return;
- case ARM64vecb_CMEQ32x4: *nm = "cmeq "; *ar = "4s"; return;
- case ARM64vecb_CMEQ16x8: *nm = "cmeq "; *ar = "8h"; return;
- case ARM64vecb_CMEQ8x16: *nm = "cmeq "; *ar = "16b"; return;
- case ARM64vecb_CMHI64x2: *nm = "cmhi "; *ar = "2d"; return;
- case ARM64vecb_CMHI32x4: *nm = "cmhi "; *ar = "4s"; return;
- case ARM64vecb_CMHI16x8: *nm = "cmhi "; *ar = "8h"; return;
- case ARM64vecb_CMHI8x16: *nm = "cmhi "; *ar = "16b"; return;
- case ARM64vecb_CMGT64x2: *nm = "cmgt "; *ar = "2d"; return;
- case ARM64vecb_CMGT32x4: *nm = "cmgt "; *ar = "4s"; return;
- case ARM64vecb_CMGT16x8: *nm = "cmgt "; *ar = "8h"; return;
- case ARM64vecb_CMGT8x16: *nm = "cmgt "; *ar = "16b"; return;
- case ARM64vecb_FCMEQ64x2: *nm = "fcmeq"; *ar = "2d"; return;
- case ARM64vecb_FCMEQ32x4: *nm = "fcmeq"; *ar = "4s"; return;
- case ARM64vecb_FCMGE64x2: *nm = "fcmge"; *ar = "2d"; return;
- case ARM64vecb_FCMGE32x4: *nm = "fcmge"; *ar = "4s"; return;
- case ARM64vecb_FCMGT64x2: *nm = "fcmgt"; *ar = "2d"; return;
- case ARM64vecb_FCMGT32x4: *nm = "fcmgt"; *ar = "4s"; return;
- case ARM64vecb_TBL1: *nm = "tbl "; *ar = "16b"; return;
- case ARM64vecb_UZP164x2: *nm = "uzp1 "; *ar = "2d"; return;
- case ARM64vecb_UZP132x4: *nm = "uzp1 "; *ar = "4s"; return;
- case ARM64vecb_UZP116x8: *nm = "uzp1 "; *ar = "8h"; return;
- case ARM64vecb_UZP18x16: *nm = "uzp1 "; *ar = "16b"; return;
- case ARM64vecb_UZP264x2: *nm = "uzp2 "; *ar = "2d"; return;
- case ARM64vecb_UZP232x4: *nm = "uzp2 "; *ar = "4s"; return;
- case ARM64vecb_UZP216x8: *nm = "uzp2 "; *ar = "8h"; return;
- case ARM64vecb_UZP28x16: *nm = "uzp2 "; *ar = "16b"; return;
- case ARM64vecb_ZIP132x4: *nm = "zip1 "; *ar = "4s"; return;
- case ARM64vecb_ZIP116x8: *nm = "zip1 "; *ar = "8h"; return;
- case ARM64vecb_ZIP18x16: *nm = "zip1 "; *ar = "16b"; return;
- case ARM64vecb_ZIP232x4: *nm = "zip2 "; *ar = "4s"; return;
- case ARM64vecb_ZIP216x8: *nm = "zip2 "; *ar = "8h"; return;
- case ARM64vecb_ZIP28x16: *nm = "zip2 "; *ar = "16b"; return;
- case ARM64vecb_PMUL8x16: *nm = "pmul "; *ar = "16b"; return;
- case ARM64vecb_PMULL8x8: *nm = "pmull"; *ar = "8hbb"; return;
- case ARM64vecb_UMULL2DSS: *nm = "umull"; *ar = "2dss"; return;
- case ARM64vecb_UMULL4SHH: *nm = "umull"; *ar = "4shh"; return;
- case ARM64vecb_UMULL8HBB: *nm = "umull"; *ar = "8hbb"; return;
- case ARM64vecb_SMULL2DSS: *nm = "smull"; *ar = "2dss"; return;
- case ARM64vecb_SMULL4SHH: *nm = "smull"; *ar = "4shh"; return;
- case ARM64vecb_SMULL8HBB: *nm = "smull"; *ar = "8hbb"; return;
- case ARM64vecb_SQADD64x2: *nm = "sqadd"; *ar = "2d"; return;
- case ARM64vecb_SQADD32x4: *nm = "sqadd"; *ar = "4s"; return;
- case ARM64vecb_SQADD16x8: *nm = "sqadd"; *ar = "8h"; return;
- case ARM64vecb_SQADD8x16: *nm = "sqadd"; *ar = "16b"; return;
- case ARM64vecb_UQADD64x2: *nm = "uqadd"; *ar = "2d"; return;
- case ARM64vecb_UQADD32x4: *nm = "uqadd"; *ar = "4s"; return;
- case ARM64vecb_UQADD16x8: *nm = "uqadd"; *ar = "8h"; return;
- case ARM64vecb_UQADD8x16: *nm = "uqadd"; *ar = "16b"; return;
- case ARM64vecb_SQSUB64x2: *nm = "sqsub"; *ar = "2d"; return;
- case ARM64vecb_SQSUB32x4: *nm = "sqsub"; *ar = "4s"; return;
- case ARM64vecb_SQSUB16x8: *nm = "sqsub"; *ar = "8h"; return;
- case ARM64vecb_SQSUB8x16: *nm = "sqsub"; *ar = "16b"; return;
- case ARM64vecb_UQSUB64x2: *nm = "uqsub"; *ar = "2d"; return;
- case ARM64vecb_UQSUB32x4: *nm = "uqsub"; *ar = "4s"; return;
- case ARM64vecb_UQSUB16x8: *nm = "uqsub"; *ar = "8h"; return;
- case ARM64vecb_UQSUB8x16: *nm = "uqsub"; *ar = "16b"; return;
+ case ARM64vecb_ADD64x2: *nm = "add "; *ar = "2d"; return;
+ case ARM64vecb_ADD32x4: *nm = "add "; *ar = "4s"; return;
+ case ARM64vecb_ADD16x8: *nm = "add "; *ar = "8h"; return;
+ case ARM64vecb_ADD8x16: *nm = "add "; *ar = "16b"; return;
+ case ARM64vecb_SUB64x2: *nm = "sub "; *ar = "2d"; return;
+ case ARM64vecb_SUB32x4: *nm = "sub "; *ar = "4s"; return;
+ case ARM64vecb_SUB16x8: *nm = "sub "; *ar = "8h"; return;
+ case ARM64vecb_SUB8x16: *nm = "sub "; *ar = "16b"; return;
+ case ARM64vecb_MUL32x4: *nm = "mul "; *ar = "4s"; return;
+ case ARM64vecb_MUL16x8: *nm = "mul "; *ar = "8h"; return;
+ case ARM64vecb_MUL8x16: *nm = "mul "; *ar = "16b"; return;
+ case ARM64vecb_FADD64x2: *nm = "fadd "; *ar = "2d"; return;
+ case ARM64vecb_FSUB64x2: *nm = "fsub "; *ar = "2d"; return;
+ case ARM64vecb_FMUL64x2: *nm = "fmul "; *ar = "2d"; return;
+ case ARM64vecb_FDIV64x2: *nm = "fdiv "; *ar = "2d"; return;
+ case ARM64vecb_FADD32x4: *nm = "fadd "; *ar = "4s"; return;
+ case ARM64vecb_FSUB32x4: *nm = "fsub "; *ar = "4s"; return;
+ case ARM64vecb_FMUL32x4: *nm = "fmul "; *ar = "4s"; return;
+ case ARM64vecb_FDIV32x4: *nm = "fdiv "; *ar = "4s"; return;
+ case ARM64vecb_UMAX32x4: *nm = "umax "; *ar = "4s"; return;
+ case ARM64vecb_UMAX16x8: *nm = "umax "; *ar = "8h"; return;
+ case ARM64vecb_UMAX8x16: *nm = "umax "; *ar = "16b"; return;
+ case ARM64vecb_UMIN32x4: *nm = "umin "; *ar = "4s"; return;
+ case ARM64vecb_UMIN16x8: *nm = "umin "; *ar = "8h"; return;
+ case ARM64vecb_UMIN8x16: *nm = "umin "; *ar = "16b"; return;
+ case ARM64vecb_SMAX32x4: *nm = "smax "; *ar = "4s"; return;
+ case ARM64vecb_SMAX16x8: *nm = "smax "; *ar = "8h"; return;
+ case ARM64vecb_SMAX8x16: *nm = "smax "; *ar = "16b"; return;
+ case ARM64vecb_SMIN32x4: *nm = "smin "; *ar = "4s"; return;
+ case ARM64vecb_SMIN16x8: *nm = "smin "; *ar = "8h"; return;
+ case ARM64vecb_SMIN8x16: *nm = "smin "; *ar = "16b"; return;
+ case ARM64vecb_AND: *nm = "and "; *ar = "16b"; return;
+ case ARM64vecb_ORR: *nm = "orr "; *ar = "16b"; return;
+ case ARM64vecb_XOR: *nm = "eor "; *ar = "16b"; return;
+ case ARM64vecb_CMEQ64x2: *nm = "cmeq "; *ar = "2d"; return;
+ case ARM64vecb_CMEQ32x4: *nm = "cmeq "; *ar = "4s"; return;
+ case ARM64vecb_CMEQ16x8: *nm = "cmeq "; *ar = "8h"; return;
+ case ARM64vecb_CMEQ8x16: *nm = "cmeq "; *ar = "16b"; return;
+ case ARM64vecb_CMHI64x2: *nm = "cmhi "; *ar = "2d"; return;
+ case ARM64vecb_CMHI32x4: *nm = "cmhi "; *ar = "4s"; return;
+ case ARM64vecb_CMHI16x8: *nm = "cmhi "; *ar = "8h"; return;
+ case ARM64vecb_CMHI8x16: *nm = "cmhi "; *ar = "16b"; return;
+ case ARM64vecb_CMGT64x2: *nm = "cmgt "; *ar = "2d"; return;
+ case ARM64vecb_CMGT32x4: *nm = "cmgt "; *ar = "4s"; return;
+ case ARM64vecb_CMGT16x8: *nm = "cmgt "; *ar = "8h"; return;
+ case ARM64vecb_CMGT8x16: *nm = "cmgt "; *ar = "16b"; return;
+ case ARM64vecb_FCMEQ64x2: *nm = "fcmeq"; *ar = "2d"; return;
+ case ARM64vecb_FCMEQ32x4: *nm = "fcmeq"; *ar = "4s"; return;
+ case ARM64vecb_FCMGE64x2: *nm = "fcmge"; *ar = "2d"; return;
+ case ARM64vecb_FCMGE32x4: *nm = "fcmge"; *ar = "4s"; return;
+ case ARM64vecb_FCMGT64x2: *nm = "fcmgt"; *ar = "2d"; return;
+ case ARM64vecb_FCMGT32x4: *nm = "fcmgt"; *ar = "4s"; return;
+ case ARM64vecb_TBL1: *nm = "tbl "; *ar = "16b"; return;
+ case ARM64vecb_UZP164x2: *nm = "uzp1 "; *ar = "2d"; return;
+ case ARM64vecb_UZP132x4: *nm = "uzp1 "; *ar = "4s"; return;
+ case ARM64vecb_UZP116x8: *nm = "uzp1 "; *ar = "8h"; return;
+ case ARM64vecb_UZP18x16: *nm = "uzp1 "; *ar = "16b"; return;
+ case ARM64vecb_UZP264x2: *nm = "uzp2 "; *ar = "2d"; return;
+ case ARM64vecb_UZP232x4: *nm = "uzp2 "; *ar = "4s"; return;
+ case ARM64vecb_UZP216x8: *nm = "uzp2 "; *ar = "8h"; return;
+ case ARM64vecb_UZP28x16: *nm = "uzp2 "; *ar = "16b"; return;
+ case ARM64vecb_ZIP132x4: *nm = "zip1 "; *ar = "4s"; return;
+ case ARM64vecb_ZIP116x8: *nm = "zip1 "; *ar = "8h"; return;
+ case ARM64vecb_ZIP18x16: *nm = "zip1 "; *ar = "16b"; return;
+ case ARM64vecb_ZIP232x4: *nm = "zip2 "; *ar = "4s"; return;
+ case ARM64vecb_ZIP216x8: *nm = "zip2 "; *ar = "8h"; return;
+ case ARM64vecb_ZIP28x16: *nm = "zip2 "; *ar = "16b"; return;
+ case ARM64vecb_PMUL8x16: *nm = "pmul "; *ar = "16b"; return;
+ case ARM64vecb_PMULL8x8: *nm = "pmull"; *ar = "8hbb"; return;
+ case ARM64vecb_UMULL2DSS: *nm = "umull"; *ar = "2dss"; return;
+ case ARM64vecb_UMULL4SHH: *nm = "umull"; *ar = "4shh"; return;
+ case ARM64vecb_UMULL8HBB: *nm = "umull"; *ar = "8hbb"; return;
+ case ARM64vecb_SMULL2DSS: *nm = "smull"; *ar = "2dss"; return;
+ case ARM64vecb_SMULL4SHH: *nm = "smull"; *ar = "4shh"; return;
+ case ARM64vecb_SMULL8HBB: *nm = "smull"; *ar = "8hbb"; return;
+ case ARM64vecb_SQADD64x2: *nm = "sqadd"; *ar = "2d"; return;
+ case ARM64vecb_SQADD32x4: *nm = "sqadd"; *ar = "4s"; return;
+ case ARM64vecb_SQADD16x8: *nm = "sqadd"; *ar = "8h"; return;
+ case ARM64vecb_SQADD8x16: *nm = "sqadd"; *ar = "16b"; return;
+ case ARM64vecb_UQADD64x2: *nm = "uqadd"; *ar = "2d"; return;
+ case ARM64vecb_UQADD32x4: *nm = "uqadd"; *ar = "4s"; return;
+ case ARM64vecb_UQADD16x8: *nm = "uqadd"; *ar = "8h"; return;
+ case ARM64vecb_UQADD8x16: *nm = "uqadd"; *ar = "16b"; return;
+ case ARM64vecb_SQSUB64x2: *nm = "sqsub"; *ar = "2d"; return;
+ case ARM64vecb_SQSUB32x4: *nm = "sqsub"; *ar = "4s"; return;
+ case ARM64vecb_SQSUB16x8: *nm = "sqsub"; *ar = "8h"; return;
+ case ARM64vecb_SQSUB8x16: *nm = "sqsub"; *ar = "16b"; return;
+ case ARM64vecb_UQSUB64x2: *nm = "uqsub"; *ar = "2d"; return;
+ case ARM64vecb_UQSUB32x4: *nm = "uqsub"; *ar = "4s"; return;
+ case ARM64vecb_UQSUB16x8: *nm = "uqsub"; *ar = "8h"; return;
+ case ARM64vecb_UQSUB8x16: *nm = "uqsub"; *ar = "16b"; return;
+ case ARM64vecb_SQDMULL2DSS: *nm = "sqdmull"; *ar = "2dss"; return;
+ case ARM64vecb_SQDMULL4SHH: *nm = "sqdmull"; *ar = "4shh"; return;
default: vpanic("showARM64VecBinOp");
}
}
@@ -3507,6 +3509,7 @@
#define X101110 BITS8(0,0, 1,0,1,1,1,0)
#define X110000 BITS8(0,0, 1,1,0,0,0,0)
#define X110001 BITS8(0,0, 1,1,0,0,0,1)
+#define X110100 BITS8(0,0, 1,1,0,1,0,0)
#define X110101 BITS8(0,0, 1,1,0,1,0,1)
#define X110111 BITS8(0,0, 1,1,0,1,1,1)
#define X111000 BITS8(0,0, 1,1,1,0,0,0)
@@ -5189,6 +5192,9 @@
011 01110 10 1 m 001011 n d UQSUB Vd.4s, Vn.4s, Vm.4s
011 01110 01 1 m 001011 n d UQSUB Vd.8h, Vn.8h, Vm.8h
011 01110 00 1 m 001011 n d UQSUB Vd.16b, Vn.16b, Vm.16b
+
+ 000 01110 10 1 m 110100 n d SQDMULL Vd.2d, Vn.2s, Vm.2s
+ 000 01110 01 1 m 110100 n d SQDMULL Vd.4s, Vn.4h, Vm.4h
*/
UInt vD = qregNo(i->ARM64in.VBinV.dst);
UInt vN = qregNo(i->ARM64in.VBinV.argL);
@@ -5492,6 +5498,13 @@
*p++ = X_3_8_5_6_5_5(X011, X01110001, vM, X001011, vN, vD);
break;
+ case ARM64vecb_SQDMULL2DSS:
+ *p++ = X_3_8_5_6_5_5(X000, X01110101, vM, X110100, vN, vD);
+ break;
+ case ARM64vecb_SQDMULL4SHH:
+ *p++ = X_3_8_5_6_5_5(X000, X01110011, vM, X110100, vN, vD);
+ break;
+
default:
goto bad;
}
Modified: trunk/priv/host_arm64_defs.h
==============================================================================
--- trunk/priv/host_arm64_defs.h (original)
+++ trunk/priv/host_arm64_defs.h Mon Jul 21 09:19:50 2014
@@ -350,14 +350,17 @@
ARM64vecb_UMULL4SHH, ARM64vecb_UMULL8HBB,
ARM64vecb_SMULL2DSS,
ARM64vecb_SMULL4SHH, ARM64vecb_SMULL8HBB,
- ARM64vecb_SQADD64x2, ARM64vecb_SQADD32x4,
- ARM64vecb_SQADD16x8, ARM64vecb_SQADD8x16,
- ARM64vecb_UQADD64x2, ARM64vecb_UQADD32x4,
- ARM64vecb_UQADD16x8, ARM64vecb_UQADD8x16,
- ARM64vecb_SQSUB64x2, ARM64vecb_SQSUB32x4,
- ARM64vecb_SQSUB16x8, ARM64vecb_SQSUB8x16,
- ARM64vecb_UQSUB64x2, ARM64vecb_UQSUB32x4,
- ARM64vecb_UQSUB16x8, ARM64vecb_UQSUB8x16,
+ ARM64vecb_SQADD64x2, ARM64vecb_SQADD32x4,
+ ARM64vecb_SQADD16x8, ARM64vecb_SQADD8x16,
+ ARM64vecb_UQADD64x2, ARM64vecb_UQADD32x4,
+ ARM64vecb_UQADD16x8, ARM64vecb_UQADD8x16,
+ ARM64vecb_SQSUB64x2, ARM64vecb_SQSUB32x4,
+ ARM64vecb_SQSUB16x8, ARM64vecb_SQSUB8x16,
+ ARM64vecb_UQSUB64x2, ARM64vecb_UQSUB32x4,
+ ARM64vecb_UQSUB16x8, ARM64vecb_UQSUB8x16,
+ ARM64vecb_SQDMULL2DSS,
+ ARM64vecb_SQDMULL4SHH,
+
ARM64vecb_INVALID
}
ARM64VecBinOp;
Modified: trunk/priv/host_arm64_isel.c
==============================================================================
--- trunk/priv/host_arm64_isel.c (original)
+++ trunk/priv/host_arm64_isel.c Mon Jul 21 09:19:50 2014
@@ -5658,6 +5658,8 @@
case Iop_Mull32Sx2:
case Iop_Mull16Sx4:
case Iop_Mull8Sx8:
+ case Iop_QDMull32Sx2:
+ case Iop_QDMull16Sx4:
{
HReg iSrcL = iselIntExpr_R(env, e->Iex.Binop.arg1);
HReg iSrcR = iselIntExpr_R(env, e->Iex.Binop.arg2);
@@ -5666,13 +5668,15 @@
HReg dst = newVRegV(env);
ARM64VecBinOp op = ARM64vecb_INVALID;
switch (e->Iex.Binop.op) {
- case Iop_PolynomialMull8x8: op = ARM64vecb_PMULL8x8; break;
- case Iop_Mull32Ux2: op = ARM64vecb_UMULL2DSS; break;
- case Iop_Mull16Ux4: op = ARM64vecb_UMULL4SHH; break;
- case Iop_Mull8Ux8: op = ARM64vecb_UMULL8HBB; break;
- case Iop_Mull32Sx2: op = ARM64vecb_SMULL2DSS; break;
- case Iop_Mull16Sx4: op = ARM64vecb_SMULL4SHH; break;
- case Iop_Mull8Sx8: op = ARM64vecb_SMULL8HBB; break;
+ case Iop_PolynomialMull8x8: op = ARM64vecb_PMULL8x8; break;
+ case Iop_Mull32Ux2: op = ARM64vecb_UMULL2DSS; break;
+ case Iop_Mull16Ux4: op = ARM64vecb_UMULL4SHH; break;
+ case Iop_Mull8Ux8: op = ARM64vecb_UMULL8HBB; break;
+ case Iop_Mull32Sx2: op = ARM64vecb_SMULL2DSS; break;
+ case Iop_Mull16Sx4: op = ARM64vecb_SMULL4SHH; break;
+ case Iop_Mull8Sx8: op = ARM64vecb_SMULL8HBB; break;
+ case Iop_QDMull32Sx2: op = ARM64vecb_SQDMULL2DSS; break;
+ case Iop_QDMull16Sx4: op = ARM64vecb_SQDMULL4SHH; break;
default: vassert(0);
}
addInstr(env, ARM64Instr_VQfromXX(vSrcL, iSrcL, iSrcL));
Modified: trunk/priv/host_arm_isel.c
==============================================================================
--- trunk/priv/host_arm_isel.c (original)
+++ trunk/priv/host_arm_isel.c Mon Jul 21 09:19:50 2014
@@ -5118,15 +5118,15 @@
return res;
}
- case Iop_QDMulLong16Sx4:
- case Iop_QDMulLong32Sx2: {
+ case Iop_QDMull16Sx4:
+ case Iop_QDMull32Sx2: {
HReg res = newVRegV(env);
HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
UInt size = 0;
switch(e->Iex.Binop.op) {
- case Iop_QDMulLong16Sx4: size = 1; break;
- case Iop_QDMulLong32Sx2: size = 2; break;
+ case Iop_QDMull16Sx4: size = 1; break;
+ case Iop_QDMull32Sx2: size = 2; break;
default: vassert(0);
}
addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULL,
Modified: trunk/priv/ir_defs.c
==============================================================================
--- trunk/priv/ir_defs.c (original)
+++ trunk/priv/ir_defs.c Mon Jul 21 09:19:50 2014
@@ -470,8 +470,8 @@
case Iop_QDMulHi32Sx2: vex_printf("QDMulHi32Sx2"); return;
case Iop_QRDMulHi16Sx4: vex_printf("QRDMulHi16Sx4"); return;
case Iop_QRDMulHi32Sx2: vex_printf("QRDMulHi32Sx2"); return;
- case Iop_QDMulLong16Sx4: vex_printf("QDMulLong16Sx4"); return;
- case Iop_QDMulLong32Sx2: vex_printf("QDMulLong32Sx2"); return;
+ case Iop_QDMull16Sx4: vex_printf("QDMull16Sx4"); return;
+ case Iop_QDMull32Sx2: vex_printf("QDMull32Sx2"); return;
case Iop_Avg8Ux8: vex_printf("Avg8Ux8"); return;
case Iop_Avg16Ux4: vex_printf("Avg16Ux4"); return;
case Iop_Max8Sx8: vex_printf("Max8Sx8"); return;
@@ -2979,7 +2979,7 @@
case Iop_BCDAdd:
case Iop_BCDSub:
TERNARY(Ity_V128,Ity_V128, Ity_I8, Ity_V128);
- case Iop_QDMulLong16Sx4: case Iop_QDMulLong32Sx2:
+ case Iop_QDMull16Sx4: case Iop_QDMull32Sx2:
BINARY(Ity_I64, Ity_I64, Ity_V128);
/* s390 specific */
Modified: trunk/pub/libvex_ir.h
==============================================================================
--- trunk/pub/libvex_ir.h (original)
+++ trunk/pub/libvex_ir.h Mon Jul 21 09:19:50 2014
@@ -1411,20 +1411,24 @@
/* (widening signed/unsigned of even lanes, with lowest lane=zero) */
Iop_MullEven8Ux16, Iop_MullEven16Ux8, Iop_MullEven32Ux4,
Iop_MullEven8Sx16, Iop_MullEven16Sx8, Iop_MullEven32Sx4,
- /* FIXME: document these */
+
+ /* Widening multiplies, all of the form (I64, I64) -> V128 */
Iop_Mull8Ux8, Iop_Mull8Sx8,
Iop_Mull16Ux4, Iop_Mull16Sx4,
Iop_Mull32Ux2, Iop_Mull32Sx2,
+
+ /* Signed doubling saturating widening multiplies, (I64, I64) -> V128 */
+ Iop_QDMull16Sx4, Iop_QDMull32Sx2,
+
/* Vector Saturating Doubling Multiply Returning High Half and
Vector Saturating Rounding Doubling Multiply Returning High Half */
- /* These IROp's multiply corresponding elements in two vectors, double
+ /* These IROps multiply corresponding elements in two vectors, double
the results, and place the most significant half of the final results
in the destination vector. The results are truncated or rounded. If
any of the results overflow, they are saturated. */
Iop_QDMulHi16Sx8, Iop_QDMulHi32Sx4,
Iop_QRDMulHi16Sx8, Iop_QRDMulHi32Sx4,
- /* Doubling saturating multiplication (long) (I64, I64) -> V128 */
- Iop_QDMulLong16Sx4, Iop_QDMulLong32Sx2,
+
/* Polynomial multiplication treats its arguments as
coefficients of polynomials over {0, 1}. */
Iop_PolynomialMul8x16, /* (V128, V128) -> V128 */
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From: <sv...@va...> - 2014-07-21 07:56:02
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Author: sewardj
Date: Mon Jul 21 07:55:45 2014
New Revision: 2906
Log:
Initialise a couple of scalars that gcc -Og thinks might be
uninitialised, presumably because at -Og it doesn't do enough
block straightening-outening or whatever to see that they are
always assigned before use.
Modified:
trunk/priv/guest_arm_toIR.c
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Mon Jul 21 07:55:45 2014
@@ -3657,8 +3657,8 @@
case 4:
if (B == 0) {
/* VSHL */
- IROp op, sub_op;
- IRTemp tmp;
+ IROp op = Iop_INVALID, sub_op = Iop_INVALID;
+ IRTemp tmp = IRTemp_INVALID;
if (U) {
switch (size) {
case 0: op = Q ? Iop_Shl8x16 : Iop_Shl8x8; break;
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