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From: Julian S. <js...@ac...> - 2010-04-16 20:32:54
|
On Thursday 15 April 2010, Sebastien Cote wrote:
> Hi,
>
> It seems the instructions were already handled in VEX but not with the REX
> prefix. I tried changing the code to work around it like the following:
>
> /* 66 0F FC = PADDB */
> - if (have66noF2noF3(pfx) && sz == 2
> + if ((have66noF2noF3(pfx) || haveREX(pfx))
> + && (sz == 2 || /* ignore redundant REX.W */ sz == 8)
> && insn[0] == 0x0F && insn[1] == 0xFC) {
> delta = dis_SSEint_E_to_G( vbi, pfx, delta+2,
> "paddb", Iop_Add8x16, False );
>
>
> I may have broken something with this change but it got rid of the previous
> unhandled instructions. However, now I get an unhandled instruction on:
That's nearly right. In fact the "haveREX(pfx)" is redundant, so in fact
the only change is from
sz == 2
to
(sz == 2 || /* ignore redundant REX.W */ sz == 8)
> 66 48 0f d7 c0 pmovmskb %xmm0,%rax
>
> Now I really don't know how to work around this because the handling of the
> pmovmskb instruction is much more complex than the previous ones.
I'm surprised it failed there. It looks to me like the handler for pmovmskb
(xmm version), around line 11860 of guest_am64_toIR.c, can handle the
redundant rex prefix (0x48).
J
|
|
From: <sv...@va...> - 2010-04-16 20:14:14
|
Author: de
Date: 2010-04-16 21:14:06 +0100 (Fri, 16 Apr 2010)
New Revision: 1976
Log:
Added new SSE4.1 instruction:
PMAXUD
Modified:
trunk/priv/guest_amd64_toIR.c
Modified: trunk/priv/guest_amd64_toIR.c
===================================================================
--- trunk/priv/guest_amd64_toIR.c 2010-04-16 14:12:09 UTC (rev 1975)
+++ trunk/priv/guest_amd64_toIR.c 2010-04-16 20:14:06 UTC (rev 1976)
@@ -14304,6 +14304,54 @@
}
+ /* 66 0F 38 3F /r = PMAXUD xmm1, xmm2/m128
+ Maximum of Packed Unsigned Doubleword Integers (XMM) */
+ if ( have66noF2noF3( pfx )
+ && sz == 2
+ && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x3F ) {
+
+ IRTemp reg_vec = newTemp(Ity_V128);
+ IRTemp rom_vec = newTemp(Ity_V128);
+ IRTemp mask_vec = newTemp(Ity_V128);
+ IRTemp and_vec = newTemp(Ity_V128);
+ IRTemp not_vec = newTemp(Ity_V128);
+
+ modrm = insn[3];
+ assign( reg_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) );
+
+ if ( epartIsReg( modrm ) ) {
+ assign( rom_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
+ delta += 3+1;
+ DIP( "pmaxud %s,%s\n",
+ nameXMMReg( eregOfRexRM(pfx, modrm) ),
+ nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
+ assign( rom_vec, loadLE( Ity_V128, mkexpr(addr) ) );
+ delta += 3+alen;
+ DIP( "pmaxud %s,%s\n", dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ }
+
+ /* the foll. simulates Iop_CmpGT32Ux4 (not implemented)
+ c.f. Hacker's Delight, S2-11, p.23 */
+ assign( mask_vec,
+ binop( Iop_XorV128,
+ binop( Iop_XorV128,
+ binop( Iop_CmpGT32Sx4, mkexpr(reg_vec), mkexpr(rom_vec) ),
+ binop( Iop_SarN32x4, mkexpr(reg_vec), mkU8(31) ) ),
+ binop( Iop_SarN32x4, mkexpr(rom_vec), mkU8(31) ) ) );
+
+ assign( and_vec, binop( Iop_AndV128, mkexpr(reg_vec), mkexpr(mask_vec) ) );
+ assign( not_vec, binop( Iop_AndV128, mkexpr(rom_vec),
+ unop( Iop_NotV128, mkexpr(mask_vec) ) ) );
+
+ putXMMReg( gregOfRexRM(pfx, modrm),
+ binop( Iop_OrV128, mkexpr(not_vec), mkexpr(and_vec) ) );
+
+ goto decode_success;
+ }
+
+
/* 66 0f 38 20 /r = PMOVSXBW xmm1, xmm2/m64
Packed Move with Sign Extend from Byte to Word (XMM) */
if ( have66noF2noF3( pfx )
|
|
From: <sv...@va...> - 2010-04-16 14:12:18
|
Author: de
Date: 2010-04-16 15:12:09 +0100 (Fri, 16 Apr 2010)
New Revision: 1975
Log:
Added new SSE4.1 instruction:
PINSRQ
Modified:
trunk/priv/guest_amd64_toIR.c
Modified: trunk/priv/guest_amd64_toIR.c
===================================================================
--- trunk/priv/guest_amd64_toIR.c 2010-04-15 14:42:41 UTC (rev 1974)
+++ trunk/priv/guest_amd64_toIR.c 2010-04-16 14:12:09 UTC (rev 1975)
@@ -14200,6 +14200,53 @@
}
+ /* 66 REX.W 0F 3A 22 /r ib = PINSRQ xmm1, r/m64, imm8
+ Extract Quadword int from gen.reg/mem64 and insert into xmm1 */
+ if ( have66noF2noF3( pfx )
+ && sz == 8 /* REX.W is present */
+ && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x22 ) {
+
+ Int imm8_0;
+ IRTemp src_elems = newTemp(Ity_I64);
+ IRTemp src_vec = newTemp(Ity_V128);
+
+ modrm = insn[3];
+
+ if ( epartIsReg( modrm ) ) {
+ imm8_0 = (Int)(insn[3+1] & 1);
+ assign( src_elems, getIReg64( eregOfRexRM(pfx,modrm) ) );
+ delta += 3+1+1;
+ DIP( "pinsrq $%d, %s,%s\n", imm8_0,
+ nameIReg64( eregOfRexRM(pfx, modrm) ),
+ nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ } else {
+ addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 );
+ imm8_0 = (Int)(insn[3+alen] & 1);
+ assign( src_elems, loadLE( Ity_I64, mkexpr(addr) ) );
+ delta += 3+alen+1;
+ DIP( "pinsrq $%d, %s,%s\n",
+ imm8_0, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+ }
+
+ UShort mask = 0;
+ if ( imm8_0 == 0 ) {
+ mask = 0xFF00;
+ assign( src_vec, binop( Iop_64HLtoV128, mkU64(0), mkexpr(src_elems) ) );
+ } else {
+ mask = 0x00FF;
+ assign( src_vec, binop( Iop_64HLtoV128, mkexpr(src_elems), mkU64(0) ) );
+ }
+
+ putXMMReg( gregOfRexRM(pfx, modrm),
+ binop( Iop_OrV128, mkexpr(src_vec),
+ binop( Iop_AndV128,
+ getXMMReg( gregOfRexRM(pfx, modrm) ),
+ mkV128(mask) ) ) );
+
+ goto decode_success;
+ }
+
+
/* 66 0F 38 3D /r = PMAXSD xmm1, xmm2/m128
Maximum of Packed Signed Double Word Integers (XMM)
--
|