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From: Tom H. <th...@cy...> - 2007-05-08 02:23:31
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2007-05-08 03:00:06 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 294 tests, 6 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) none/tests/fdleak_fcntl (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |
|
From: Tom H. <th...@cy...> - 2007-05-08 02:17:33
|
Nightly build on lloyd ( x86_64, Fedora Core 3 ) started at 2007-05-08 03:05:03 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 292 tests, 6 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |
|
From: <js...@ac...> - 2007-05-08 00:00:55
|
Nightly build on g5 ( SuSE 10.1, ppc970 ) started at 2007-05-08 02:00:01 CEST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 226 tests, 6 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/deep_templates (stdout) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 226 tests, 6 stderr failures, 3 stdout failures, 0 posttest failures == memcheck/tests/deep_templates (stdout) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/res_search (stdout) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Tue May 8 02:08:57 2007 --- new.short Tue May 8 02:16:58 2007 *************** *** 8,10 **** ! == 226 tests, 6 stderr failures, 3 stdout failures, 0 posttest failures == memcheck/tests/deep_templates (stdout) --- 8,10 ---- ! == 226 tests, 6 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/deep_templates (stdout) *************** *** 17,19 **** none/tests/mremap2 (stdout) - none/tests/res_search (stdout) --- 17,18 ---- |
|
From: <sv...@va...> - 2007-05-07 18:36:53
|
Author: sewardj
Date: 2007-05-07 19:36:48 +0100 (Mon, 07 May 2007)
New Revision: 1768
Log:
Cosmetic (non-functional) changes associated with r1767.
Modified:
branches/CGTUNE/priv/main/vex_main.c
Modified: branches/CGTUNE/priv/main/vex_main.c
===================================================================
--- branches/CGTUNE/priv/main/vex_main.c 2007-05-07 02:33:30 UTC (rev 1767)
+++ branches/CGTUNE/priv/main/vex_main.c 2007-05-07 18:36:48 UTC (rev 1768)
@@ -186,18 +186,18 @@
from the target instruction set. */
HReg* available_real_regs;
Int n_available_real_regs;
- Bool (*isMove) ( HInstr*, HReg*, HReg* );
- void (*getRegUsage) ( HRegUsage*, HInstr*, Bool );
- void (*mapRegs) ( HRegRemap*, HInstr*, Bool );
- HInstr* (*genSpill) ( HReg, Int, Bool );
- HInstr* (*genReload) ( HReg, Int, Bool );
- HInstr* (*directReload)( HInstr*, HReg, Short );
- void (*ppInstr) ( HInstr*, Bool );
- void (*ppReg) ( HReg );
- HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*,
- VexAbiInfo* );
- Int (*emit) ( UChar*, Int, HInstr*, Bool, void* );
- IRExpr* (*specHelper) ( HChar*, IRExpr** );
+ Bool (*isMove) ( HInstr*, HReg*, HReg* );
+ void (*getRegUsage) ( HRegUsage*, HInstr*, Bool );
+ void (*mapRegs) ( HRegRemap*, HInstr*, Bool );
+ HInstr* (*genSpill) ( HReg, Int, Bool );
+ HInstr* (*genReload) ( HReg, Int, Bool );
+ HInstr* (*directReload) ( HInstr*, HReg, Short );
+ void (*ppInstr) ( HInstr*, Bool );
+ void (*ppReg) ( HReg );
+ HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*,
+ VexAbiInfo* );
+ Int (*emit) ( UChar*, Int, HInstr*, Bool, void* );
+ IRExpr* (*specHelper) ( HChar*, IRExpr** );
Bool (*preciseMemExnsFn) ( Int, Int );
DisOneInstrFn disInstrFn;
@@ -248,19 +248,19 @@
switch (vta->arch_host) {
case VexArchX86:
- mode64 = False;
+ mode64 = False;
getAllocableRegs_X86 ( &n_available_real_regs,
&available_real_regs );
- isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr;
- getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_X86Instr;
- mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_X86Instr;
- genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_X86;
- genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_X86;
+ isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr;
+ getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_X86Instr;
+ mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_X86Instr;
+ genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_X86;
+ genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_X86;
directReload = (HInstr*(*)(HInstr*,HReg,Short)) directReload_X86;
- ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr;
- ppReg = (void(*)(HReg)) ppHRegX86;
- iselSB = iselSB_X86;
- emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_X86Instr;
+ ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr;
+ ppReg = (void(*)(HReg)) ppHRegX86;
+ iselSB = iselSB_X86;
+ emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_X86Instr;
host_is_bigendian = False;
host_word_type = Ity_I32;
vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_host.hwcaps));
|
|
From: <js...@ac...> - 2007-05-07 13:41:05
|
Nightly build on minnie ( SuSE 10.0, ppc32 ) started at 2007-05-07 09:00:02 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 219 tests, 10 stderr failures, 6 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-fp (stderr) none/tests/ppc32/round (stdout) none/tests/ppc32/round (stderr) none/tests/ppc32/test_fx (stdout) none/tests/ppc32/test_fx (stderr) none/tests/ppc32/test_gx (stdout) |
|
From: <sv...@va...> - 2007-05-07 02:33:32
|
Author: sewardj
Date: 2007-05-07 03:33:30 +0100 (Mon, 07 May 2007)
New Revision: 1767
Log:
Add a second spill-code-avoidance optimisation, which could be called
'directReload' for lack of a better name.
If an instruction reads exactly one vreg which is currently in a spill
slot, and this is last use of that vreg, see if the instruction can be
converted into one that reads directly from the spill slot. This is
clearly only possible for x86 and amd64 targets, since ppc is a
load-store architecture. So, for example,
orl %vreg, %dst
where %vreg is in a spill slot, and this is its last use, would
previously be converted to
movl $spill-offset(%ebp), %tmp
orl %tmp, %dst
whereas now it becomes
orl $spill-offset(%ebp), %dst
This not only avoids an instruction, it eliminates the need for a
reload temporary (%tmp in this example) and so potentially further
reduces spilling.
Implementation is in two parts: an architecture independent part, in
reg_alloc2.c, which finds candidate instructions, and a host dependent
function (directReload_ARCH) for each arch supporting the
optimisation. The directReload_ function does the instruction form
conversion, when possible. Currently only x86 hosts are supported.
As a side effect, change the form of the X86_Test32 instruction from
reg-only to reg/mem so it can participate in such transformations.
This gives a code size reduction of 0.6% for perf/bz2 on x86 memcheck,
but tends to be more effective for long blocks of x86 FP code.
Modified:
branches/CGTUNE/priv/host-generic/h_generic_regs.h
branches/CGTUNE/priv/host-generic/reg_alloc2.c
branches/CGTUNE/priv/host-x86/hdefs.c
branches/CGTUNE/priv/host-x86/hdefs.h
branches/CGTUNE/priv/host-x86/isel.c
branches/CGTUNE/priv/main/vex_main.c
Modified: branches/CGTUNE/priv/host-generic/h_generic_regs.h
===================================================================
--- branches/CGTUNE/priv/host-generic/h_generic_regs.h 2007-05-06 17:44:16 UTC (rev 1766)
+++ branches/CGTUNE/priv/host-generic/h_generic_regs.h 2007-05-07 02:33:30 UTC (rev 1767)
@@ -266,9 +266,10 @@
void (*mapRegs) (HRegRemap*, HInstr*, Bool),
/* Return an insn to spill/restore a real reg to a spill slot
- offset. */
+ offset. And optionally a function to do direct reloads. */
HInstr* (*genSpill) ( HReg, Int, Bool ),
HInstr* (*genReload) ( HReg, Int, Bool ),
+ HInstr* (*directReload) ( HInstr*, HReg, Short ),
Int guest_sizeB,
/* For debug printing only. */
Modified: branches/CGTUNE/priv/host-generic/reg_alloc2.c
===================================================================
--- branches/CGTUNE/priv/host-generic/reg_alloc2.c 2007-05-06 17:44:16 UTC (rev 1766)
+++ branches/CGTUNE/priv/host-generic/reg_alloc2.c 2007-05-07 02:33:30 UTC (rev 1767)
@@ -323,10 +323,14 @@
/* Apply a reg-reg mapping to an insn. */
void (*mapRegs) ( HRegRemap*, HInstr*, Bool ),
- /* Return an insn to spill/restore a real reg to a spill slot
- byte offset. */
+ /* Return an insn to spill/restore a real reg to a spill slot byte
+ offset. Also (optionally) a 'directReload' function, which
+ attempts to replace a given instruction by one which reads
+ directly from a specified spill slot. May be NULL, in which
+ case the optimisation is not attempted. */
HInstr* (*genSpill) ( HReg, Int, Bool ),
HInstr* (*genReload) ( HReg, Int, Bool ),
+ HInstr* (*directReload) ( HInstr*, HReg, Short ),
Int guest_sizeB,
/* For debug printing only. */
@@ -1162,6 +1166,76 @@
initHRegRemap(&remap);
+ /* ------------ BEGIN directReload optimisation ----------- */
+
+ /* If the instruction reads exactly one vreg which is currently
+ in a spill slot, and this is last use of that vreg, see if we
+ can convert the instruction into one reads directly from the
+ spill slot. This is clearly only possible for x86 and amd64
+ targets, since ppc is a load-store architecture. If
+ successful, replace instrs_in->arr[ii] with this new
+ instruction, and recompute its reg usage, so that the change
+ is invisible to the standard-case handling that follows. */
+
+ if (directReload && reg_usage.n_used <= 2) {
+ Bool debug_direct_reload = True && False;
+ HReg cand = INVALID_HREG;
+ Bool nreads = 0;
+ Short spilloff = 0;
+
+ for (j = 0; j < reg_usage.n_used; j++) {
+
+ vreg = reg_usage.hreg[j];
+
+ if (!hregIsVirtual(vreg))
+ continue;
+
+ if (reg_usage.mode[j] == HRmRead) {
+ nreads++;
+ m = hregNumber(vreg);
+ vassert(IS_VALID_VREGNO(m));
+ k = vreg_state[m];
+ if (!IS_VALID_RREGNO(k)) {
+ /* ok, it is spilled. Now, is this its last use? */
+ vassert(vreg_lrs[m].dead_before >= ii+1);
+ if (vreg_lrs[m].dead_before == ii+1
+ && cand == INVALID_HREG) {
+ spilloff = vreg_lrs[m].spill_offset;
+ cand = vreg;
+ }
+ }
+ }
+ }
+
+ if (nreads == 1 && cand != INVALID_HREG) {
+ HInstr* reloaded;
+ if (reg_usage.n_used == 2)
+ vassert(reg_usage.hreg[0] != reg_usage.hreg[1]);
+
+ reloaded = directReload ( instrs_in->arr[ii], cand, spilloff );
+ if (debug_direct_reload && !reloaded) {
+ vex_printf("[%3d] ", spilloff); ppHReg(cand); vex_printf(" ");
+ ppInstr(instrs_in->arr[ii], mode64);
+ }
+ if (reloaded) {
+ /* Update info about the insn, so it looks as if it had
+ been in this form all along. */
+ instrs_in->arr[ii] = reloaded;
+ (*getRegUsage)( ®_usage, instrs_in->arr[ii], mode64 );
+ if (debug_direct_reload && !reloaded) {
+ vex_printf(" --> ");
+ ppInstr(reloaded, mode64);
+ }
+ }
+
+ if (debug_direct_reload && !reloaded)
+ vex_printf("\n");
+ }
+
+ }
+
+ /* ------------ END directReload optimisation ------------ */
+
/* for each reg mentioned in the insn ... */
for (j = 0; j < reg_usage.n_used; j++) {
Modified: branches/CGTUNE/priv/host-x86/hdefs.c
===================================================================
--- branches/CGTUNE/priv/host-x86/hdefs.c 2007-05-06 17:44:16 UTC (rev 1766)
+++ branches/CGTUNE/priv/host-x86/hdefs.c 2007-05-07 02:33:30 UTC (rev 1767)
@@ -598,7 +598,7 @@
i->Xin.Sh32.dst = dst;
return i;
}
-X86Instr* X86Instr_Test32 ( UInt imm32, HReg dst ) {
+X86Instr* X86Instr_Test32 ( UInt imm32, X86RM* dst ) {
X86Instr* i = LibVEX_Alloc(sizeof(X86Instr));
i->tag = Xin_Test32;
i->Xin.Test32.imm32 = imm32;
@@ -908,7 +908,7 @@
return;
case Xin_Test32:
vex_printf("testl $%d,", (Int)i->Xin.Test32.imm32);
- ppHRegX86(i->Xin.Test32.dst);
+ ppX86RM(i->Xin.Test32.dst);
return;
case Xin_Unary32:
vex_printf("%sl ", showX86UnaryOp(i->Xin.Unary32.op));
@@ -1173,7 +1173,7 @@
addHRegUse(u, HRmRead, hregX86_ECX());
return;
case Xin_Test32:
- addHRegUse(u, HRmRead, i->Xin.Test32.dst);
+ addRegUsage_X86RM(u, i->Xin.Test32.dst, HRmRead);
return;
case Xin_Unary32:
addHRegUse(u, HRmModify, i->Xin.Unary32.dst);
@@ -1402,7 +1402,7 @@
mapReg(m, &i->Xin.Sh32.dst);
return;
case Xin_Test32:
- mapReg(m, &i->Xin.Test32.dst);
+ mapRegs_X86RM(m, i->Xin.Test32.dst);
return;
case Xin_Unary32:
mapReg(m, &i->Xin.Unary32.dst);
@@ -1610,7 +1610,83 @@
}
}
+/* The given instruction reads the specified vreg exactly once, and
+ that vreg is currently located at the given spill offset. If
+ possible, return a variant of the instruction which instead
+ references the spill slot directly. */
+X86Instr* directReload_X86( X86Instr* i, HReg vreg, Short spill_off )
+{
+ vassert(spill_off >= 0 && spill_off < 10000); /* let's say */
+
+ /* Deal with form: src=RMI_Reg, dst=Reg where src == vreg
+ Convert to: src=RMI_Mem, dst=Reg
+ */
+ if (i->tag == Xin_Alu32R
+ && (i->Xin.Alu32R.op == Xalu_MOV || i->Xin.Alu32R.op == Xalu_OR
+ || i->Xin.Alu32R.op == Xalu_XOR)
+ && i->Xin.Alu32R.src->tag == Xrmi_Reg
+ && i->Xin.Alu32R.src->Xrmi.Reg.reg == vreg) {
+ vassert(i->Xin.Alu32R.dst != vreg);
+ return X86Instr_Alu32R(
+ i->Xin.Alu32R.op,
+ X86RMI_Mem( X86AMode_IR( spill_off, hregX86_EBP())),
+ i->Xin.Alu32R.dst
+ );
+ }
+
+ /* Deal with form: src=RMI_Imm, dst=Reg where dst == vreg
+ Convert to: src=RI_Imm, dst=Mem
+ */
+ if (i->tag == Xin_Alu32R
+ && (i->Xin.Alu32R.op == Xalu_CMP)
+ && i->Xin.Alu32R.src->tag == Xrmi_Imm
+ && i->Xin.Alu32R.dst == vreg) {
+ return X86Instr_Alu32M(
+ i->Xin.Alu32R.op,
+ X86RI_Imm( i->Xin.Alu32R.src->Xrmi.Imm.imm32 ),
+ X86AMode_IR( spill_off, hregX86_EBP())
+ );
+ }
+
+ /* Deal with form: Push(RMI_Reg)
+ Convert to: Push(RMI_Mem)
+ */
+ if (i->tag == Xin_Push
+ && i->Xin.Push.src->tag == Xrmi_Reg
+ && i->Xin.Push.src->Xrmi.Reg.reg == vreg) {
+ return X86Instr_Push(
+ X86RMI_Mem( X86AMode_IR( spill_off, hregX86_EBP()))
+ );
+ }
+
+ /* Deal with form: CMov32(src=RM_Reg, dst) where vreg == src
+ Convert to CMov32(RM_Mem, dst) */
+ if (i->tag == Xin_CMov32
+ && i->Xin.CMov32.src->tag == Xrm_Reg
+ && i->Xin.CMov32.src->Xrm.Reg.reg == vreg) {
+ vassert(i->Xin.CMov32.dst != vreg);
+ return X86Instr_CMov32(
+ i->Xin.CMov32.cond,
+ X86RM_Mem( X86AMode_IR( spill_off, hregX86_EBP() )),
+ i->Xin.CMov32.dst
+ );
+ }
+
+ /* Deal with form: Test32(imm,RM_Reg vreg) -> Test32(imm,amode) */
+ if (i->tag == Xin_Test32
+ && i->Xin.Test32.dst->tag == Xrm_Reg
+ && i->Xin.Test32.dst->Xrm.Reg.reg == vreg) {
+ return X86Instr_Test32(
+ i->Xin.Test32.imm32,
+ X86RM_Mem( X86AMode_IR( spill_off, hregX86_EBP() ) )
+ );
+ }
+
+ return NULL;
+}
+
+
/* --------- The x86 assembler (bleh.) --------- */
static UChar iregNo ( HReg r )
@@ -2010,6 +2086,7 @@
switch (i->Xin.Alu32M.op) {
case Xalu_ADD: opc = 0x01; subopc_imm = 0; break;
case Xalu_SUB: opc = 0x29; subopc_imm = 5; break;
+ case Xalu_CMP: opc = 0x39; subopc_imm = 7; break;
default: goto bad;
}
switch (i->Xin.Alu32M.src->tag) {
@@ -2054,11 +2131,19 @@
goto done;
case Xin_Test32:
- /* testl $imm32, %reg */
- *p++ = 0xF7;
- p = doAMode_R(p, fake(0), i->Xin.Test32.dst);
- p = emit32(p, i->Xin.Test32.imm32);
- goto done;
+ if (i->Xin.Test32.dst->tag == Xrm_Reg) {
+ /* testl $imm32, %reg */
+ *p++ = 0xF7;
+ p = doAMode_R(p, fake(0), i->Xin.Test32.dst->Xrm.Reg.reg);
+ p = emit32(p, i->Xin.Test32.imm32);
+ goto done;
+ } else {
+ /* testl $imm32, amode */
+ *p++ = 0xF7;
+ p = doAMode_M(p, fake(0), i->Xin.Test32.dst->Xrm.Mem.am);
+ p = emit32(p, i->Xin.Test32.imm32);
+ goto done;
+ }
case Xin_Unary32:
if (i->Xin.Unary32.op == Xun_NOT) {
Modified: branches/CGTUNE/priv/host-x86/hdefs.h
===================================================================
--- branches/CGTUNE/priv/host-x86/hdefs.h 2007-05-06 17:44:16 UTC (rev 1766)
+++ branches/CGTUNE/priv/host-x86/hdefs.h 2007-05-07 02:33:30 UTC (rev 1767)
@@ -351,7 +351,7 @@
Xin_Alu32R, /* 32-bit mov/arith/logical, dst=REG */
Xin_Alu32M, /* 32-bit mov/arith/logical, dst=MEM */
Xin_Sh32, /* 32-bit shift/rotate, dst=REG */
- Xin_Test32, /* 32-bit test of REG against imm32 (AND, set
+ Xin_Test32, /* 32-bit test of REG or MEM against imm32 (AND, set
flags, discard result) */
Xin_Unary32, /* 32-bit not and neg */
Xin_Lea32, /* 32-bit compute EA into a reg */
@@ -413,8 +413,8 @@
HReg dst;
} Sh32;
struct {
- UInt imm32;
- HReg dst; /* not written, only read */
+ UInt imm32;
+ X86RM* dst; /* not written, only read */
} Test32;
/* Not and Neg */
struct {
@@ -624,7 +624,7 @@
extern X86Instr* X86Instr_Lea32 ( X86AMode* am, HReg dst );
extern X86Instr* X86Instr_Sh32 ( X86ShiftOp, UInt, HReg );
-extern X86Instr* X86Instr_Test32 ( UInt imm32, HReg dst );
+extern X86Instr* X86Instr_Test32 ( UInt imm32, X86RM* dst );
extern X86Instr* X86Instr_MulL ( Bool syned, X86RM* );
extern X86Instr* X86Instr_Div ( Bool syned, X86RM* );
extern X86Instr* X86Instr_Sh3232 ( X86ShiftOp, UInt amt, HReg src, HReg dst );
@@ -672,6 +672,8 @@
Bool, void* dispatch );
extern X86Instr* genSpill_X86 ( HReg rreg, Int offset, Bool );
extern X86Instr* genReload_X86 ( HReg rreg, Int offset, Bool );
+extern X86Instr* directReload_X86 ( X86Instr* i,
+ HReg vreg, Short spill_off );
extern void getAllocableRegs_X86 ( Int*, HReg** );
extern HInstrArray* iselSB_X86 ( IRSB*, VexArch,
VexArchInfo*,
Modified: branches/CGTUNE/priv/host-x86/isel.c
===================================================================
--- branches/CGTUNE/priv/host-x86/isel.c 2007-05-06 17:44:16 UTC (rev 1766)
+++ branches/CGTUNE/priv/host-x86/isel.c 2007-05-07 02:33:30 UTC (rev 1767)
@@ -113,6 +113,12 @@
return IRExpr_Binder(binder);
}
+static Bool isZeroU8 ( IRExpr* e )
+{
+ return e->tag == Iex_Const
+ && e->Iex.Const.con->tag == Ico_U8
+ && e->Iex.Const.con->Ico.U8 == 0;
+}
/*---------------------------------------------------------*/
@@ -1248,12 +1254,12 @@
case Iex_Mux0X: {
if ((ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8)
&& typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) == Ity_I8) {
- HReg r8;
- HReg rX = iselIntExpr_R(env, e->Iex.Mux0X.exprX);
- X86RM* r0 = iselIntExpr_RM(env, e->Iex.Mux0X.expr0);
- HReg dst = newVRegI(env);
+ X86RM* r8;
+ HReg rX = iselIntExpr_R(env, e->Iex.Mux0X.exprX);
+ X86RM* r0 = iselIntExpr_RM(env, e->Iex.Mux0X.expr0);
+ HReg dst = newVRegI(env);
addInstr(env, mk_iMOVsd_RR(rX,dst));
- r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
+ r8 = iselIntExpr_RM(env, e->Iex.Mux0X.cond);
addInstr(env, X86Instr_Test32(0xFF, r8));
addInstr(env, X86Instr_CMov32(Xcc_Z,r0,dst));
return dst;
@@ -1552,7 +1558,7 @@
if (e->tag == Iex_RdTmp) {
HReg r32 = lookupIRTemp(env, e->Iex.RdTmp.tmp);
/* Test32 doesn't modify r32; so this is OK. */
- addInstr(env, X86Instr_Test32(1,r32));
+ addInstr(env, X86Instr_Test32(1,X86RM_Reg(r32)));
return Xcc_NZ;
}
@@ -1597,8 +1603,8 @@
unop(Iop_32to1,bind(0))
);
if (matchIRExpr(&mi,p_32to1,e)) {
- HReg r = iselIntExpr_R(env, mi.bindee[0]);
- addInstr(env, X86Instr_Test32(1,r));
+ X86RM* rm = iselIntExpr_RM(env, mi.bindee[0]);
+ addInstr(env, X86Instr_Test32(1,rm));
return Xcc_NZ;
}
@@ -1607,8 +1613,8 @@
/* CmpNEZ8(x) */
if (e->tag == Iex_Unop
&& e->Iex.Unop.op == Iop_CmpNEZ8) {
- HReg r = iselIntExpr_R(env, e->Iex.Unop.arg);
- addInstr(env, X86Instr_Test32(0xFF,r));
+ X86RM* rm = iselIntExpr_RM(env, e->Iex.Unop.arg);
+ addInstr(env, X86Instr_Test32(0xFF,rm));
return Xcc_NZ;
}
@@ -1617,8 +1623,8 @@
/* CmpNEZ16(x) */
if (e->tag == Iex_Unop
&& e->Iex.Unop.op == Iop_CmpNEZ16) {
- HReg r = iselIntExpr_R(env, e->Iex.Unop.arg);
- addInstr(env, X86Instr_Test32(0xFFFF,r));
+ X86RM* rm = iselIntExpr_RM(env, e->Iex.Unop.arg);
+ addInstr(env, X86Instr_Test32(0xFFFF,rm));
return Xcc_NZ;
}
@@ -1721,16 +1727,26 @@
if (e->tag == Iex_Binop
&& (e->Iex.Binop.op == Iop_CmpEQ8
|| e->Iex.Binop.op == Iop_CmpNE8)) {
- HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1);
- X86RMI* rmi2 = iselIntExpr_RMI(env, e->Iex.Binop.arg2);
- HReg r = newVRegI(env);
- addInstr(env, mk_iMOVsd_RR(r1,r));
- addInstr(env, X86Instr_Alu32R(Xalu_XOR,rmi2,r));
- addInstr(env, X86Instr_Test32(0xFF,r));
- switch (e->Iex.Binop.op) {
- case Iop_CmpEQ8: return Xcc_Z;
- case Iop_CmpNE8: return Xcc_NZ;
- default: vpanic("iselCondCode(x86): CmpXX8");
+ if (isZeroU8(e->Iex.Binop.arg2)) {
+ HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1);
+ addInstr(env, X86Instr_Test32(0xFF,X86RM_Reg(r1)));
+ switch (e->Iex.Binop.op) {
+ case Iop_CmpEQ8: return Xcc_Z;
+ case Iop_CmpNE8: return Xcc_NZ;
+ default: vpanic("iselCondCode(x86): CmpXX8(expr,0:I8)");
+ }
+ } else {
+ HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1);
+ X86RMI* rmi2 = iselIntExpr_RMI(env, e->Iex.Binop.arg2);
+ HReg r = newVRegI(env);
+ addInstr(env, mk_iMOVsd_RR(r1,r));
+ addInstr(env, X86Instr_Alu32R(Xalu_XOR,rmi2,r));
+ addInstr(env, X86Instr_Test32(0xFF,X86RM_Reg(r)));
+ switch (e->Iex.Binop.op) {
+ case Iop_CmpEQ8: return Xcc_Z;
+ case Iop_CmpNE8: return Xcc_NZ;
+ default: vpanic("iselCondCode(x86): CmpXX8(expr,expr)");
+ }
}
}
@@ -1743,7 +1759,7 @@
HReg r = newVRegI(env);
addInstr(env, mk_iMOVsd_RR(r1,r));
addInstr(env, X86Instr_Alu32R(Xalu_XOR,rmi2,r));
- addInstr(env, X86Instr_Test32(0xFFFF,r));
+ addInstr(env, X86Instr_Test32(0xFFFF,X86RM_Reg(r)));
switch (e->Iex.Binop.op) {
case Iop_CmpEQ16: return Xcc_Z;
case Iop_CmpNE16: return Xcc_NZ;
@@ -1901,15 +1917,16 @@
/* 64-bit Mux0X */
if (e->tag == Iex_Mux0X) {
- HReg e0Lo, e0Hi, eXLo, eXHi, r8;
- HReg tLo = newVRegI(env);
- HReg tHi = newVRegI(env);
+ X86RM* rm8;
+ HReg e0Lo, e0Hi, eXLo, eXHi;
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
iselInt64Expr(&e0Hi, &e0Lo, env, e->Iex.Mux0X.expr0);
iselInt64Expr(&eXHi, &eXLo, env, e->Iex.Mux0X.exprX);
addInstr(env, mk_iMOVsd_RR(eXHi, tHi));
addInstr(env, mk_iMOVsd_RR(eXLo, tLo));
- r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
- addInstr(env, X86Instr_Test32(0xFF, r8));
+ rm8 = iselIntExpr_RM(env, e->Iex.Mux0X.cond);
+ addInstr(env, X86Instr_Test32(0xFF, rm8));
/* This assumes the first cmov32 doesn't trash the condition
codes, so they are still available for the second cmov32 */
addInstr(env, X86Instr_CMov32(Xcc_Z,X86RM_Reg(e0Hi),tHi));
@@ -2047,7 +2064,7 @@
and those regs are legitimately modifiable. */
addInstr(env, X86Instr_Sh3232(Xsh_SHL, 0/*%cl*/, tLo, tHi));
addInstr(env, X86Instr_Sh32(Xsh_SHL, 0/*%cl*/, tLo));
- addInstr(env, X86Instr_Test32(32, hregX86_ECX()));
+ addInstr(env, X86Instr_Test32(32, X86RM_Reg(hregX86_ECX())));
addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(tLo), tHi));
addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(0), tTemp));
addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(tTemp), tLo));
@@ -2089,7 +2106,7 @@
and those regs are legitimately modifiable. */
addInstr(env, X86Instr_Sh3232(Xsh_SHR, 0/*%cl*/, tHi, tLo));
addInstr(env, X86Instr_Sh32(Xsh_SHR, 0/*%cl*/, tHi));
- addInstr(env, X86Instr_Test32(32, hregX86_ECX()));
+ addInstr(env, X86Instr_Test32(32, X86RM_Reg(hregX86_ECX())));
addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(tHi), tLo));
addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(0), tTemp));
addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(tTemp), tHi));
@@ -2812,12 +2829,12 @@
if (e->tag == Iex_Mux0X) {
if (ty == Ity_F64
&& typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) == Ity_I8) {
- HReg r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
- HReg rX = iselDblExpr(env, e->Iex.Mux0X.exprX);
- HReg r0 = iselDblExpr(env, e->Iex.Mux0X.expr0);
- HReg dst = newVRegF(env);
+ X86RM* rm8 = iselIntExpr_RM(env, e->Iex.Mux0X.cond);
+ HReg rX = iselDblExpr(env, e->Iex.Mux0X.exprX);
+ HReg r0 = iselDblExpr(env, e->Iex.Mux0X.expr0);
+ HReg dst = newVRegF(env);
addInstr(env, X86Instr_FpUnary(Xfp_MOV,rX,dst));
- addInstr(env, X86Instr_Test32(0xFF, r8));
+ addInstr(env, X86Instr_Test32(0xFF, rm8));
addInstr(env, X86Instr_FpCMov(Xcc_Z,r0,dst));
return dst;
}
@@ -3333,12 +3350,12 @@
} /* if (e->tag == Iex_Binop) */
if (e->tag == Iex_Mux0X) {
- HReg r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
- HReg rX = iselVecExpr(env, e->Iex.Mux0X.exprX);
- HReg r0 = iselVecExpr(env, e->Iex.Mux0X.expr0);
- HReg dst = newVRegV(env);
+ X86RM* rm8 = iselIntExpr_RM(env, e->Iex.Mux0X.cond);
+ HReg rX = iselVecExpr(env, e->Iex.Mux0X.exprX);
+ HReg r0 = iselVecExpr(env, e->Iex.Mux0X.expr0);
+ HReg dst = newVRegV(env);
addInstr(env, mk_vMOVsd_RR(rX,dst));
- addInstr(env, X86Instr_Test32(0xFF, r8));
+ addInstr(env, X86Instr_Test32(0xFF, rm8));
addInstr(env, X86Instr_SseCMov(Xcc_Z,r0,dst));
return dst;
}
Modified: branches/CGTUNE/priv/main/vex_main.c
===================================================================
--- branches/CGTUNE/priv/main/vex_main.c 2007-05-06 17:44:16 UTC (rev 1766)
+++ branches/CGTUNE/priv/main/vex_main.c 2007-05-07 02:33:30 UTC (rev 1767)
@@ -191,6 +191,7 @@
void (*mapRegs) ( HRegRemap*, HInstr*, Bool );
HInstr* (*genSpill) ( HReg, Int, Bool );
HInstr* (*genReload) ( HReg, Int, Bool );
+ HInstr* (*directReload)( HInstr*, HReg, Short );
void (*ppInstr) ( HInstr*, Bool );
void (*ppReg) ( HReg );
HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*,
@@ -221,6 +222,7 @@
mapRegs = NULL;
genSpill = NULL;
genReload = NULL;
+ directReload = NULL;
ppInstr = NULL;
ppReg = NULL;
iselSB = NULL;
@@ -254,6 +256,7 @@
mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_X86Instr;
genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_X86;
genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_X86;
+ directReload = (HInstr*(*)(HInstr*,HReg,Short)) directReload_X86;
ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr;
ppReg = (void(*)(HReg)) ppHRegX86;
iselSB = iselSB_X86;
@@ -581,7 +584,8 @@
rcode = doRegisterAllocation ( vcode, available_real_regs,
n_available_real_regs,
isMove, getRegUsage, mapRegs,
- genSpill, genReload, guest_sizeB,
+ genSpill, genReload, directReload,
+ guest_sizeB,
ppInstr, ppReg, mode64 );
vexAllocSanityCheck();
|
|
From: Tom H. <th...@cy...> - 2007-05-07 02:24:17
|
Nightly build on dellow ( x86_64, Fedora Core 6 ) started at 2007-05-07 03:10:05 BST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 292 tests, 4 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 292 tests, 4 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/pth_detached (stdout) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Mon May 7 03:16:53 2007 --- new.short Mon May 7 03:24:10 2007 *************** *** 8,10 **** ! == 292 tests, 4 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/pointer-trace (stderr) --- 8,10 ---- ! == 292 tests, 4 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) *************** *** 14,16 **** none/tests/mremap2 (stdout) - none/tests/pth_detached (stdout) --- 14,15 ---- |
|
From: Tom H. <th...@cy...> - 2007-05-07 02:24:15
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2007-05-07 03:00:04 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 294 tests, 6 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) none/tests/fdleak_fcntl (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |
|
From: Tom H. <th...@cy...> - 2007-05-07 02:17:59
|
Nightly build on lloyd ( x86_64, Fedora Core 3 ) started at 2007-05-07 03:05:05 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 292 tests, 6 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |
|
From: <sv...@va...> - 2007-05-06 17:44:22
|
Author: sewardj
Date: 2007-05-06 18:44:16 +0100 (Sun, 06 May 2007)
New Revision: 1766
Log:
Followup to r1765: fix some comments, and rearrange fields in struct
RRegState so as to fit it into 16 bytes.
Modified:
branches/CGTUNE/priv/host-generic/reg_alloc2.c
Modified: branches/CGTUNE/priv/host-generic/reg_alloc2.c
===================================================================
--- branches/CGTUNE/priv/host-generic/reg_alloc2.c 2007-05-06 15:21:57 UTC (rev 1765)
+++ branches/CGTUNE/priv/host-generic/reg_alloc2.c 2007-05-06 17:44:16 UTC (rev 1766)
@@ -56,9 +56,6 @@
/* TODO 27 Oct 04:
- (Critical): Need a way to statically establish the vreg classes,
- else we can't allocate spill slots properly.
-
Better consistency checking from what isMove tells us.
We can possibly do V-V coalescing even when the src is spilled,
@@ -66,10 +63,6 @@
Note that state[].hreg is the same as the available real regs.
- Check whether rreg preferencing has any beneficial effect.
-
- Remove preferencing fields in VRegInfo, if not used.
-
Generally rationalise data structures. */
@@ -109,20 +102,14 @@
updated as the allocator processes instructions. */
typedef
struct {
- /* FIELDS WHICH DO NOT CHANGE */
+ /* ------ FIELDS WHICH DO NOT CHANGE ------ */
/* Which rreg is this for? */
HReg rreg;
/* Is this involved in any HLRs? (only an optimisation hint) */
Bool has_hlrs;
- /* FIELDS WHICH DO CHANGE */
- /* What's it's current disposition? */
- enum { Free, /* available for use */
- Unavail, /* in a real-reg live range */
- Bound /* in use (holding value of some vreg) */
- }
- disp;
- /* If RRegBound, what vreg is it bound to? */
- HReg vreg;
+ /* ------ FIELDS WHICH DO CHANGE ------ */
+ /* 6 May 07: rearranged fields below so the whole struct fits
+ into 16 bytes on both x86 and amd64. */
/* Used when .disp == Bound and we are looking for vregs to
spill. */
Bool is_spill_cand;
@@ -131,6 +118,14 @@
vreg. Is safely left at False, and becomes True after a
spill store or reload for this rreg. */
Bool eq_spill_slot;
+ /* What's it's current disposition? */
+ enum { Free, /* available for use */
+ Unavail, /* in a real-reg live range */
+ Bound /* in use (holding value of some vreg) */
+ }
+ disp;
+ /* If .disp == Bound, what vreg is it bound to? */
+ HReg vreg;
}
RRegState;
@@ -1043,9 +1038,9 @@
vreg_state[hregNumber(vregD)] = toShort(m);
vreg_state[hregNumber(vregS)] = INVALID_RREG_NO;
- /* FIXME check this. This rreg has become associated with a different
- vreg and hence with a different spill slot. Play safe. */
- rreg_state[m].eq_spill_slot = False;
+ /* This rreg has become associated with a different vreg and
+ hence with a different spill slot. Play safe. */
+ rreg_state[m].eq_spill_slot = False;
/* Move on to the next insn. We skip the post-insn stuff for
fixed registers, since this move should not interact with
@@ -1242,7 +1237,7 @@
rreg_state[k].eq_spill_slot = True;
} else {
rreg_state[k].eq_spill_slot = False;
- }
+ }
continue;
}
|
|
From: <sv...@va...> - 2007-05-06 15:22:01
|
Author: sewardj
Date: 2007-05-06 16:21:57 +0100 (Sun, 06 May 2007)
New Revision: 1765
Log:
During register allocation, keep track of which (real) registers have
the same value as their associated spill slot. Then, if a register
needs to be freed up for some reason, and that register has the same
value as its spill slot, there is no need to produce a spill store.
This substantially reduces the number of spill store instructions
created. Overall gives a 1.9% generated code size reduction for
perf/bz2 running on x86.
Modified:
branches/CGTUNE/priv/host-generic/reg_alloc2.c
Modified: branches/CGTUNE/priv/host-generic/reg_alloc2.c
===================================================================
--- branches/CGTUNE/priv/host-generic/reg_alloc2.c 2007-05-06 13:16:29 UTC (rev 1764)
+++ branches/CGTUNE/priv/host-generic/reg_alloc2.c 2007-05-06 15:21:57 UTC (rev 1765)
@@ -126,6 +126,11 @@
/* Used when .disp == Bound and we are looking for vregs to
spill. */
Bool is_spill_cand;
+ /* Optimisation: used when .disp == Bound. Indicates when the
+ rreg has the same value as the spill slot for the associated
+ vreg. Is safely left at False, and becomes True after a
+ spill store or reload for this rreg. */
+ Bool eq_spill_slot;
}
RRegState;
@@ -339,6 +344,8 @@
{
# define N_SPILL64S (LibVEX_N_SPILL_BYTES / 8)
+ const Bool eq_spill_opt = True;
+
/* Iterators and temporaries. */
Int ii, j, k, m, spillee, k_suboptimal;
HReg rreg, vreg, vregS, vregD;
@@ -462,6 +469,7 @@
rreg_state[j].disp = Free;
rreg_state[j].vreg = INVALID_HREG;
rreg_state[j].is_spill_cand = False;
+ rreg_state[j].eq_spill_slot = False;
}
for (j = 0; j < n_vregs; j++)
@@ -783,7 +791,7 @@
two spill slots.
Do a rank-based allocation of vregs to spill slot numbers. We
- put as few values as possible in spill slows, but nevertheless
+ put as few values as possible in spill slots, but nevertheless
need to have a spill slot available for all vregs, just in case.
*/
/* max_ss_no = -1; */
@@ -956,8 +964,10 @@
/* Sanity check 3: all vreg-rreg bindings must bind registers
of the same class. */
for (j = 0; j < n_rregs; j++) {
- if (rreg_state[j].disp != Bound)
+ if (rreg_state[j].disp != Bound) {
+ vassert(rreg_state[j].eq_spill_slot == False);
continue;
+ }
vassert(hregClass(rreg_state[j].rreg)
== hregClass(rreg_state[j].vreg));
vassert( hregIsVirtual(rreg_state[j].vreg));
@@ -1033,6 +1043,10 @@
vreg_state[hregNumber(vregD)] = toShort(m);
vreg_state[hregNumber(vregS)] = INVALID_RREG_NO;
+ /* FIXME check this. This rreg has become associated with a different
+ vreg and hence with a different spill slot. Play safe. */
+ rreg_state[m].eq_spill_slot = False;
+
/* Move on to the next insn. We skip the post-insn stuff for
fixed registers, since this move should not interact with
them in any way. */
@@ -1052,6 +1066,7 @@
vassert(IS_VALID_VREGNO(vreg));
if (vreg_lrs[vreg].dead_before <= ii) {
rreg_state[j].disp = Free;
+ rreg_state[j].eq_spill_slot = False;
m = hregNumber(rreg_state[j].vreg);
vassert(IS_VALID_VREGNO(m));
vreg_state[m] = INVALID_RREG_NO;
@@ -1115,13 +1130,17 @@
vreg_state[m] = INVALID_RREG_NO;
if (vreg_lrs[m].dead_before > ii) {
vassert(vreg_lrs[m].reg_class != HRcINVALID);
- EMIT_INSTR( (*genSpill)( rreg_state[k].rreg,
- vreg_lrs[m].spill_offset,
- mode64 ) );
+ if ((!eq_spill_opt) || !rreg_state[k].eq_spill_slot) {
+ EMIT_INSTR( (*genSpill)( rreg_state[k].rreg,
+ vreg_lrs[m].spill_offset,
+ mode64 ) );
+ }
+ rreg_state[k].eq_spill_slot = True;
}
}
rreg_state[k].disp = Unavail;
rreg_state[k].vreg = INVALID_HREG;
+ rreg_state[k].eq_spill_slot = False;
/* check for further rregs entering HLRs at this point */
rreg_lrs_la_next++;
@@ -1170,6 +1189,10 @@
if (IS_VALID_RREGNO(k)) {
vassert(rreg_state[k].disp == Bound);
addToHRegRemap(&remap, vreg, rreg_state[k].rreg);
+ /* If this rreg is written or modified, mark it as different
+ from any spill slot value. */
+ if (reg_usage.mode[j] != HRmRead)
+ rreg_state[k].eq_spill_slot = False;
continue;
} else {
vassert(k == INVALID_RREG_NO);
@@ -1205,13 +1228,22 @@
vassert(IS_VALID_VREGNO(m));
vreg_state[m] = toShort(k);
addToHRegRemap(&remap, vreg, rreg_state[k].rreg);
- /* Generate a reload if needed. */
+ /* Generate a reload if needed. This only creates needed
+ reloads because the live range builder for vregs will
+ guarantee that the first event for a vreg is a write.
+ Hence, if this reference is not a write, it cannot be
+ the first reference for this vreg, and so a reload is
+ indeed needed. */
if (reg_usage.mode[j] != HRmWrite) {
vassert(vreg_lrs[m].reg_class != HRcINVALID);
EMIT_INSTR( (*genReload)( rreg_state[k].rreg,
vreg_lrs[m].spill_offset,
mode64 ) );
- }
+ rreg_state[k].eq_spill_slot = True;
+ } else {
+ rreg_state[k].eq_spill_slot = False;
+ }
+
continue;
}
@@ -1272,15 +1304,19 @@
live vreg. */
vassert(vreg_lrs[m].dead_before > ii);
vassert(vreg_lrs[m].reg_class != HRcINVALID);
- EMIT_INSTR( (*genSpill)( rreg_state[spillee].rreg,
- vreg_lrs[m].spill_offset,
- mode64 ) );
+ if ((!eq_spill_opt) || !rreg_state[spillee].eq_spill_slot) {
+ EMIT_INSTR( (*genSpill)( rreg_state[spillee].rreg,
+ vreg_lrs[m].spill_offset,
+ mode64 ) );
+ }
/* Update the rreg_state to reflect the new assignment for this
rreg. */
rreg_state[spillee].vreg = vreg;
vreg_state[m] = INVALID_RREG_NO;
+ rreg_state[spillee].eq_spill_slot = False; /* be safe */
+
m = hregNumber(vreg);
vassert(IS_VALID_VREGNO(m));
vreg_state[m] = toShort(spillee);
@@ -1292,6 +1328,7 @@
EMIT_INSTR( (*genReload)( rreg_state[spillee].rreg,
vreg_lrs[m].spill_offset,
mode64 ) );
+ rreg_state[spillee].eq_spill_slot = True;
}
/* So after much twisting and turning, we have vreg mapped to
@@ -1344,6 +1381,7 @@
vassert(rreg_state[k].disp == Unavail);
rreg_state[k].disp = Free;
rreg_state[k].vreg = INVALID_HREG;
+ rreg_state[k].eq_spill_slot = False;
/* check for further rregs leaving HLRs at this point */
rreg_lrs_db_next++;
|
|
From: <js...@ac...> - 2007-05-06 13:33:09
|
Nightly build on minnie ( SuSE 10.0, ppc32 ) started at 2007-05-06 09:00:01 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 219 tests, 10 stderr failures, 6 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-fp (stderr) none/tests/ppc32/round (stdout) none/tests/ppc32/round (stderr) none/tests/ppc32/test_fx (stdout) none/tests/ppc32/test_fx (stderr) none/tests/ppc32/test_gx (stdout) |
|
From: <sv...@va...> - 2007-05-06 13:22:23
|
Author: sewardj Date: 2007-05-06 14:22:23 +0100 (Sun, 06 May 2007) New Revision: 6732 Log: Swizzle external: svn propset svn:externals "VEX svn://svn.valgrind.org/vex/branches/CGTUNE" . Modified: branches/CGTUNE/ Property changes on: branches/CGTUNE ___________________________________________________________________ Name: svn:externals - VEX svn://svn.valgrind.org/vex/trunk + VEX svn://svn.valgrind.org/vex/branches/CGTUNE |
|
From: <sv...@va...> - 2007-05-06 13:19:52
|
Author: sewardj Date: 2007-05-06 14:19:50 +0100 (Sun, 06 May 2007) New Revision: 6731 Log: Make a copy of trunk r6730, for the purposes of various kinds of code generator tuning experiments. Added: branches/CGTUNE/ Copied: branches/CGTUNE (from rev 6730, trunk) |
|
From: <sv...@va...> - 2007-05-06 13:16:32
|
Author: sewardj Date: 2007-05-06 14:16:29 +0100 (Sun, 06 May 2007) New Revision: 1764 Log: Make a copy of trunk r1763, for the purposes of various kinds of code generator tuning experiments. Added: branches/CGTUNE/ Copied: branches/CGTUNE (from rev 1763, trunk) |
|
From: <sv...@va...> - 2007-05-06 11:28:23
|
Author: sewardj
Date: 2007-05-06 12:28:18 +0100 (Sun, 06 May 2007)
New Revision: 6730
Log:
Update.
Modified:
trunk/docs/internals/3_2_BUGSTATUS.txt
Modified: trunk/docs/internals/3_2_BUGSTATUS.txt
===================================================================
--- trunk/docs/internals/3_2_BUGSTATUS.txt 2007-05-05 16:46:21 UTC (rev 6729)
+++ trunk/docs/internals/3_2_BUGSTATUS.txt 2007-05-06 11:28:18 UTC (rev 6730)
@@ -32,8 +32,9 @@
and makes a valid MPI program crash.
vx1735 vx1750 32 141790 Missing amd64 x87 insns (FCOM, FCOMPP)
+vx1761 vx1762 32 n-i-bz Missing amd64 x87 insns (FCOMP)
-r6608 pending 32 n-i-bz intercept for __memmove_chk
+r6608 r6723 32 n-i-bz intercept for __memmove_chk
r6593 r6711 32 139363 callgrind: fix --collect-systime=yes
with "no instrumentation" mode
@@ -47,7 +48,7 @@
r6631 pending 142186 add I2C ioctl support
-Ashley logfile qualifiers in coredumps patch
+XXX Ashley logfile qualifiers in coredumps patch
r6612 r6718 32 142228 RedHat8: complaint of elf_dynamic_do_rela
r6646 r6718 32 142229 RedHat8: unexpected "write(buf) points
@@ -66,8 +67,7 @@
vx1740 vx1754 32 n-i-bz handle REX.W fsqrt
-Make configure check try for -fno-stack-protector (users, 26 Feb)
-#144112
+r6721 r6724 32 144112 undefined reference to __stack_chk_fail
possible false errors on amd64 cmpq/jae, cmpq/jbe
@@ -100,9 +100,18 @@
vx1749 vx1758 32 143907 sahf/lahf on amd64
-XXX copy spill area size, aspacem #segs and #segnames from trunk
+r6728 r6279 32 n-i-bz ppc-linux startup stack overflow fix
+XXX increase #segs and #segnames from 5000/1000 ?
+
+vx1759,r6722
+ vx1760,r6725 n-i-bz gcc-4.2 build fixes
+
+XXX 143924: --db-attach=yes and --trace-children=yes
+
+
+
//// maybe do not fix in 3.2 branch
64 bit DWARF in unwind (r6610) (definitely merge (??))
@@ -114,12 +123,10 @@
r6706 pending no n-i-bz memcheck: wrap getenv/setenv/putenv
-143924: --db-attach=yes and --trace-children=yes
+3.2.4 criteria: FC7 runs, SuSE 10.3a? runs, gcc-4.2 works OK
-3.2.4 criteria: FC7 runs, SuSE 10.3a? runs
-
------- Bugs reported and fixed in 3.2.3 ------
TRUNK 32BRANCH PRI BUG# WHAT
|
|
From: Tom H. <th...@cy...> - 2007-05-06 02:23:54
|
Nightly build on dellow ( x86_64, Fedora Core 6 ) started at 2007-05-06 03:10:04 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 292 tests, 4 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/pth_detached (stdout) |
|
From: Tom H. <th...@cy...> - 2007-05-06 02:17:25
|
Nightly build on lloyd ( x86_64, Fedora Core 3 ) started at 2007-05-06 03:05:04 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 292 tests, 6 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |
|
From: Tom H. <th...@cy...> - 2007-05-06 02:10:57
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2007-05-06 03:00:03 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 294 tests, 6 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) none/tests/fdleak_fcntl (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |
|
From: <js...@ac...> - 2007-05-06 00:16:50
|
Nightly build on g5 ( SuSE 10.1, ppc970 ) started at 2007-05-06 02:00:01 CEST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 226 tests, 6 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/deep_templates (stdout) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |
|
From: <sv...@va...> - 2007-05-05 16:46:22
|
Author: sewardj
Date: 2007-05-05 17:46:21 +0100 (Sat, 05 May 2007)
New Revision: 6729
Log:
Merge r6728 (Fix stack overflow which lead to totally mysterious .bss
corruption)
Modified:
branches/VALGRIND_3_2_BRANCH/coregrind/m_ume.c
Modified: branches/VALGRIND_3_2_BRANCH/coregrind/m_ume.c
===================================================================
--- branches/VALGRIND_3_2_BRANCH/coregrind/m_ume.c 2007-05-05 11:40:35 UTC (rev 6728)
+++ branches/VALGRIND_3_2_BRANCH/coregrind/m_ume.c 2007-05-05 16:46:21 UTC (rev 6729)
@@ -553,8 +553,8 @@
/* returns: 0 = success, non-0 is failure */
static Int load_script(Int fd, const HChar* name, ExeInfo* info)
{
- Char hdr[VKI_MAX_PAGE_SIZE];
- Int len = VKI_PAGE_SIZE;
+ Char hdr[4096];
+ Int len = 4096;
Int eol;
Char* interp;
Char* end;
@@ -628,8 +628,8 @@
{
Int fd, ret;
SysRes res;
- Char buf[VKI_MAX_PAGE_SIZE];
- SizeT bufsz = VKI_PAGE_SIZE, fsz;
+ Char buf[4096];
+ SizeT bufsz = 4096, fsz;
// Check it's readable
res = VG_(open)(exe_name, VKI_O_RDONLY, 0);
|
|
From: <js...@ac...> - 2007-05-05 13:55:38
|
Nightly build on minnie ( SuSE 10.0, ppc32 ) started at 2007-05-05 09:00:01 BST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 219 tests, 10 stderr failures, 7 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-fp (stderr) none/tests/ppc32/round (stdout) none/tests/ppc32/round (stderr) none/tests/ppc32/test_fx (stdout) none/tests/ppc32/test_fx (stderr) none/tests/ppc32/test_gx (stdout) none/tests/tls (stdout) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 219 tests, 10 stderr failures, 6 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-fp (stderr) none/tests/ppc32/round (stdout) none/tests/ppc32/round (stderr) none/tests/ppc32/test_fx (stdout) none/tests/ppc32/test_fx (stderr) none/tests/ppc32/test_gx (stdout) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Sat May 5 09:16:50 2007 --- new.short Sat May 5 09:50:47 2007 *************** *** 8,10 **** ! == 219 tests, 10 stderr failures, 6 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) --- 8,10 ---- ! == 219 tests, 10 stderr failures, 7 stdout failures, 0 posttest failures == memcheck/tests/leak-tree (stderr) *************** *** 25,26 **** --- 25,27 ---- none/tests/ppc32/test_gx (stdout) + none/tests/tls (stdout) |
|
From: <sv...@va...> - 2007-05-05 12:26:24
|
Author: sewardj
Date: 2007-05-05 13:26:23 +0100 (Sat, 05 May 2007)
New Revision: 1763
Log:
Oops. Fix longstanding bug which will have caused an unnecessary 4M
of bss space to be allocated.
Modified:
trunk/priv/main/vex_util.c
Modified: trunk/priv/main/vex_util.c
===================================================================
--- trunk/priv/main/vex_util.c 2007-05-04 10:48:12 UTC (rev 1762)
+++ trunk/priv/main/vex_util.c 2007-05-05 12:26:23 UTC (rev 1763)
@@ -71,12 +71,12 @@
static ULong temporary_bytes_allocd_TOT = 0;
-#define N_PERMANENT_BYTES 1000
+#define N_PERMANENT_BYTES 10000
-static HChar permanent[N_TEMPORARY_BYTES] __attribute__((aligned(8)));
+static HChar permanent[N_PERMANENT_BYTES] __attribute__((aligned(8)));
static HChar* permanent_first = &permanent[0];
static HChar* permanent_curr = &permanent[0];
-static HChar* permanent_last = &permanent[N_TEMPORARY_BYTES-1];
+static HChar* permanent_last = &permanent[N_PERMANENT_BYTES-1];
static VexAllocMode mode = VexAllocModeTEMP;
@@ -85,7 +85,7 @@
vassert(temporary_first == &temporary[0]);
vassert(temporary_last == &temporary[N_TEMPORARY_BYTES-1]);
vassert(permanent_first == &permanent[0]);
- vassert(permanent_last == &permanent[N_TEMPORARY_BYTES-1]);
+ vassert(permanent_last == &permanent[N_PERMANENT_BYTES-1]);
vassert(temporary_first <= temporary_curr);
vassert(temporary_curr <= temporary_last);
vassert(permanent_first <= permanent_curr);
@@ -178,7 +178,7 @@
private_LibVEX_alloc_first,
private_LibVEX_alloc_curr,
private_LibVEX_alloc_last,
- (Long)(private_LibVEX_alloc_last - private_LibVEX_alloc_first));
+ (Long)(private_LibVEX_alloc_last + 1 - private_LibVEX_alloc_first));
vpanic("VEX temporary storage exhausted.\n"
"Increase N_{TEMPORARY,PERMANENT}_BYTES and recompile.");
}
@@ -202,6 +202,8 @@
{
vex_printf("vex storage: T total %lld bytes allocated\n",
(Long)temporary_bytes_allocd_TOT );
+ vex_printf("vex storage: P total %lld bytes allocated\n",
+ (Long)(permanent_curr - permanent_first) );
}
|
|
From: <sv...@va...> - 2007-05-05 11:40:39
|
Author: sewardj
Date: 2007-05-05 12:40:35 +0100 (Sat, 05 May 2007)
New Revision: 6728
Log:
Fix stack overflow which lead to totally mysterious .bss corruption
and hence to segfaulting in vex on ppc32/64-linux in obscure
circumstances. VKI_MAX_PAGE_SIZE is 64k in recent Valgrinds.
Modified:
trunk/coregrind/m_ume.c
Modified: trunk/coregrind/m_ume.c
===================================================================
--- trunk/coregrind/m_ume.c 2007-05-03 21:25:37 UTC (rev 6727)
+++ trunk/coregrind/m_ume.c 2007-05-05 11:40:35 UTC (rev 6728)
@@ -565,8 +565,8 @@
/* returns: 0 = success, non-0 is failure */
static Int load_script(Int fd, const HChar* name, ExeInfo* info)
{
- Char hdr[VKI_MAX_PAGE_SIZE];
- Int len = VKI_PAGE_SIZE;
+ Char hdr[4096];
+ Int len = 4096;
Int eol;
Char* interp;
Char* end;
@@ -640,8 +640,8 @@
{
Int fd, ret;
SysRes res;
- Char buf[VKI_MAX_PAGE_SIZE];
- SizeT bufsz = VKI_PAGE_SIZE, fsz;
+ Char buf[4096];
+ SizeT bufsz = 4096, fsz;
// Check it's readable
res = VG_(open)(exe_name, VKI_O_RDONLY, 0);
|
|
From: Tom H. <th...@cy...> - 2007-05-05 02:24:19
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Nightly build on dellow ( x86_64, Fedora Core 6 ) started at 2007-05-05 03:10:05 BST Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 292 tests, 4 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 292 tests, 4 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/pointer-trace (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/xml1 (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) none/tests/pth_detached (stdout) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Sat May 5 03:16:53 2007 --- new.short Sat May 5 03:24:13 2007 *************** *** 8,10 **** ! == 292 tests, 4 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/pointer-trace (stderr) --- 8,10 ---- ! == 292 tests, 4 stderr failures, 1 stdout failure, 0 posttest failures == memcheck/tests/pointer-trace (stderr) *************** *** 14,16 **** none/tests/mremap2 (stdout) - none/tests/pth_detached (stdout) --- 14,15 ---- |