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From: <sv...@va...> - 2006-12-26 02:54:48
|
Author: sewardj
Date: 2006-12-26 02:54:46 +0000 (Tue, 26 Dec 2006)
New Revision: 6421
Log:
Merge r6084 (fix for #134727: valgrind exits with "Value too large
for defined data type")
Modified:
branches/VALGRIND_3_2_BRANCH/coregrind/m_libcfile.c
Modified: branches/VALGRIND_3_2_BRANCH/coregrind/m_libcfile.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VALGRIND_3_2_BRANCH/coregrind/m_libcfile.c 2006-12-25 23:32:=
41 UTC (rev 6420)
+++ branches/VALGRIND_3_2_BRANCH/coregrind/m_libcfile.c 2006-12-26 02:54:=
46 UTC (rev 6421)
@@ -234,10 +234,14 @@
/* returns: 0 =3D success, non-0 is failure */
Int VG_(check_executable)(HChar* f)
{
+#ifdef __NR_stat64
+ struct vki_stat64 st;
+ SysRes res =3D VG_(do_syscall2)(__NR_stat64, (UWord)f, (UWord)&st);
+#else
struct vki_stat st;
- SysRes res;
+ SysRes res =3D VG_(do_syscall2)(__NR_stat, (UWord)f, (UWord)&st);
+#endif
=20
- res =3D VG_(stat)(f, &st);
if (res.isError) {
return res.val;
}
|
|
From: <sv...@va...> - 2006-12-26 02:37:40
|
Author: sewardj
Date: 2006-12-26 02:37:38 +0000 (Tue, 26 Dec 2006)
New Revision: 1701
Log:
Merge r1686 (speed up register allocator by using a less braindead
algorithm for maintenance of real register live ranges)
Modified:
branches/VEX_3_2_BRANCH/priv/host-generic/reg_alloc2.c
Modified: branches/VEX_3_2_BRANCH/priv/host-generic/reg_alloc2.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-generic/reg_alloc2.c 2006-12-26 02:=
34:31 UTC (rev 1700)
+++ branches/VEX_3_2_BRANCH/priv/host-generic/reg_alloc2.c 2006-12-26 02:=
37:38 UTC (rev 1701)
@@ -129,6 +129,7 @@
}
RRegState;
=20
+
/* The allocator also maintains a redundant array of indexes
(vreg_state) from vreg numbers back to entries in rreg_state. It
is redundant because iff vreg_state[i] =3D=3D j then
@@ -152,7 +153,6 @@
#define IS_VALID_RREGNO(_zz) ((_zz) >=3D 0 && (_zz) < n_rregs)
=20
=20
-
/* Does this instruction mention a particular reg? */
static Bool instrMentionsReg (=20
void (*getRegUsage) (HRegUsage*, HInstr*, Bool),
@@ -215,7 +215,6 @@
}
=20
=20
-
/* Double the size of the real-reg live-range array, if needed. */
static void ensureRRLRspace ( RRegLR** info, Int* size, Int used )
{
@@ -233,6 +232,62 @@
}
=20
=20
+/* Sort an array of RRegLR entries by either the .live_after or
+ .dead_before fields. This is performance-critical. */
+static void sortRRLRarray ( RRegLR* arr,=20
+ Int size, Bool by_live_after )
+{
+ Int incs[14] =3D { 1, 4, 13, 40, 121, 364, 1093, 3280,
+ 9841, 29524, 88573, 265720,
+ 797161, 2391484 };
+ Int lo =3D 0;
+ Int hi =3D size-1;
+ Int i, j, h, bigN, hp;
+ RRegLR v;
+
+ vassert(size >=3D 0);
+ if (size =3D=3D 0)
+ return;
+
+ bigN =3D hi - lo + 1; if (bigN < 2) return;
+ hp =3D 0; while (hp < 14 && incs[hp] < bigN) hp++; hp--;
+
+ if (by_live_after) {
+
+ for ( ; hp >=3D 0; hp--) {
+ h =3D incs[hp];
+ for (i =3D lo + h; i <=3D hi; i++) {
+ v =3D arr[i];
+ j =3D i;
+ while (arr[j-h].live_after > v.live_after) {
+ arr[j] =3D arr[j-h];
+ j =3D j - h;
+ if (j <=3D (lo + h - 1)) break;
+ }
+ arr[j] =3D v;
+ }
+ }
+
+ } else {
+
+ for ( ; hp >=3D 0; hp--) {
+ h =3D incs[hp];
+ for (i =3D lo + h; i <=3D hi; i++) {
+ v =3D arr[i];
+ j =3D i;
+ while (arr[j-h].dead_before > v.dead_before) {
+ arr[j] =3D arr[j-h];
+ j =3D j - h;
+ if (j <=3D (lo + h - 1)) break;
+ }
+ arr[j] =3D v;
+ }
+ }
+
+ }
+}
+
+
/* A target-independent register allocator. Requires various
functions which it uses to deal abstractly with instructions and
registers, since it cannot have any target-specific knowledge.
@@ -294,9 +349,18 @@
Int n_vregs;
VRegLR* vreg_lrs; /* [0 .. n_vregs-1] */
=20
- RRegLR* rreg_lrs;
+ /* We keep two copies of the real-reg live range info, one sorted
+ by .live_after and the other by .dead_before. First the
+ unsorted info is created in the _la variant is copied into the
+ _db variant. Once that's done both of them are sorted.=20
+ We also need two integer cursors which record the next
+ location in the two arrays to consider. */
+ RRegLR* rreg_lrs_la;
+ RRegLR* rreg_lrs_db;
Int rreg_lrs_size;
Int rreg_lrs_used;
+ Int rreg_lrs_la_next;
+ Int rreg_lrs_db_next;
=20
/* Used when constructing vreg_lrs (for allocating stack
slots). */
@@ -437,7 +501,8 @@
=20
rreg_lrs_used =3D 0;
rreg_lrs_size =3D 4;
- rreg_lrs =3D LibVEX_Alloc(rreg_lrs_size * sizeof(RRegLR));
+ rreg_lrs_la =3D LibVEX_Alloc(rreg_lrs_size * sizeof(RRegLR));
+ rreg_lrs_db =3D NULL; /* we'll create this later */
=20
/* We'll need to track live range start/end points seperately for
each rreg. Sigh. */
@@ -593,12 +658,12 @@
if (flush) {
vassert(flush_la !=3D INVALID_INSTRNO);
vassert(flush_db !=3D INVALID_INSTRNO);
- ensureRRLRspace(&rreg_lrs, &rreg_lrs_size, rreg_lrs_used);
+ ensureRRLRspace(&rreg_lrs_la, &rreg_lrs_size, rreg_lrs_used)=
;
if (0)=20
vex_printf("FLUSH 1 (%d,%d)\n", flush_la, flush_db);
- rreg_lrs[rreg_lrs_used].rreg =3D rreg;
- rreg_lrs[rreg_lrs_used].live_after =3D toShort(flush_la);
- rreg_lrs[rreg_lrs_used].dead_before =3D toShort(flush_db);
+ rreg_lrs_la[rreg_lrs_used].rreg =3D rreg;
+ rreg_lrs_la[rreg_lrs_used].live_after =3D toShort(flush_la)=
;
+ rreg_lrs_la[rreg_lrs_used].dead_before =3D toShort(flush_db)=
;
rreg_lrs_used++;
}
=20
@@ -629,13 +694,13 @@
if (rreg_live_after[j] =3D=3D INVALID_INSTRNO)
continue;
=20
- ensureRRLRspace(&rreg_lrs, &rreg_lrs_size, rreg_lrs_used);
+ ensureRRLRspace(&rreg_lrs_la, &rreg_lrs_size, rreg_lrs_used);
if (0)
vex_printf("FLUSH 2 (%d,%d)\n",=20
rreg_live_after[j], rreg_dead_before[j]);
- rreg_lrs[rreg_lrs_used].rreg =3D available_real_regs[j];
- rreg_lrs[rreg_lrs_used].live_after =3D toShort(rreg_live_after[j]=
);
- rreg_lrs[rreg_lrs_used].dead_before =3D toShort(rreg_dead_before[j=
]);
+ rreg_lrs_la[rreg_lrs_used].rreg =3D available_real_regs[j];
+ rreg_lrs_la[rreg_lrs_used].live_after =3D toShort(rreg_live_after=
[j]);
+ rreg_lrs_la[rreg_lrs_used].dead_before =3D toShort(rreg_dead_befor=
e[j]);
rreg_lrs_used++;
}
=20
@@ -648,7 +713,7 @@
this mechanism -- it is only an optimisation. */
=20
for (j =3D 0; j < rreg_lrs_used; j++) {
- rreg =3D rreg_lrs[j].rreg;
+ rreg =3D rreg_lrs_la[j].rreg;
vassert(!hregIsVirtual(rreg));
/* rreg is involved in a HLR. Record this info in the array, if
there is space. */
@@ -667,6 +732,24 @@
}
}
=20
+ /* Finally, copy the _la variant into the _db variant and
+ sort both by their respective fields. */
+ rreg_lrs_db =3D LibVEX_Alloc(rreg_lrs_used * sizeof(RRegLR));
+ for (j =3D 0; j < rreg_lrs_used; j++)
+ rreg_lrs_db[j] =3D rreg_lrs_la[j];
+
+ sortRRLRarray( rreg_lrs_la, rreg_lrs_used, True /* by .live_after*/ =
);
+ sortRRLRarray( rreg_lrs_db, rreg_lrs_used, False/* by .dead_before*/ =
);
+
+ /* And set up the cursors. */
+ rreg_lrs_la_next =3D 0;
+ rreg_lrs_db_next =3D 0;
+
+ for (j =3D 1; j < rreg_lrs_used; j++) {
+ vassert(rreg_lrs_la[j-1].live_after <=3D rreg_lrs_la[j].live_afte=
r);
+ vassert(rreg_lrs_db[j-1].dead_before <=3D rreg_lrs_db[j].dead_befo=
re);
+ }
+
/* ------ end of FINALISE RREG LIVE RANGES ------ */
=20
# if DEBUG_REGALLOC
@@ -677,11 +760,20 @@
# endif
=20
# if DEBUG_REGALLOC
+ vex_printf("RRegLRs by LA:\n");
for (j =3D 0; j < rreg_lrs_used; j++) {
- (*ppReg)(rreg_lrs[j].rreg);
+ vex_printf(" ");
+ (*ppReg)(rreg_lrs_la[j].rreg);
vex_printf(" la =3D %d, db =3D %d\n",
- rreg_lrs[j].live_after, rreg_lrs[j].dead_before );
+ rreg_lrs_la[j].live_after, rreg_lrs_la[j].dead_before )=
;
}
+ vex_printf("RRegLRs by DB:\n");
+ for (j =3D 0; j < rreg_lrs_used; j++) {
+ vex_printf(" ");
+ (*ppReg)(rreg_lrs_db[j].rreg);
+ vex_printf(" la =3D %d, db =3D %d\n",
+ rreg_lrs_db[j].live_after, rreg_lrs_db[j].dead_before )=
;
+ }
# endif
=20
/* --------- Stage 3: allocate spill slots. --------- */
@@ -815,8 +907,8 @@
this insn must be marked as unavailable in the running
state. */
for (j =3D 0; j < rreg_lrs_used; j++) {
- if (rreg_lrs[j].live_after < ii=20
- && ii < rreg_lrs[j].dead_before) {
+ if (rreg_lrs_la[j].live_after < ii=20
+ && ii < rreg_lrs_la[j].dead_before) {
/* ii is the middle of a hard live range for some real
reg. Check it's marked as such in the running
state. */
@@ -831,7 +923,7 @@
=20
/* find the state entry for this rreg */
for (k =3D 0; k < n_rregs; k++)
- if (rreg_state[k].rreg =3D=3D rreg_lrs[j].rreg)
+ if (rreg_state[k].rreg =3D=3D rreg_lrs_la[j].rreg)
break;
=20
/* and assert that this rreg is marked as unavailable */
@@ -850,9 +942,9 @@
if (rreg_state[j].disp !=3D Unavail)
continue;
for (k =3D 0; k < rreg_lrs_used; k++)=20
- if (rreg_lrs[k].rreg =3D=3D rreg_state[j].rreg
- && rreg_lrs[k].live_after < ii=20
- && ii < rreg_lrs[k].dead_before)=20
+ if (rreg_lrs_la[k].rreg =3D=3D rreg_state[j].rreg
+ && rreg_lrs_la[k].live_after < ii=20
+ && ii < rreg_lrs_la[k].dead_before)=20
break;
/* If this vassertion fails, we couldn't find a
corresponding HLR. */
@@ -980,49 +1072,60 @@
Note we could do better:
* Could move it into some other free rreg, if one is available=20
=20
- Simplest way to do this is to iterate over the collection
- of rreg live ranges.
+ Do this efficiently, by incrementally stepping along an array
+ of rreg HLRs that are known to be sorted by start point
+ (their .live_after field).
*/
- for (j =3D 0; j < rreg_lrs_used; j++) {
- if (rreg_lrs[j].live_after =3D=3D ii) {
- /* rreg_lrs[j].rreg needs to be freed up. Find=20
- the associated rreg_state entry. */
- /* Note, re rreg_lrs[j].live_after =3D=3D ii. Real register
- live ranges are guaranteed to be well-formed in that
- they start with a write to the register -- Stage 2
- rejects any code not satisfying this. So the correct
- question to ask is whether rreg_lrs[j].live_after =3D=3D
- ii, that is, whether the reg becomes live after this
- insn -- rather than before it. */
-# if DEBUG_REGALLOC
- vex_printf("need to free up rreg: ");
- (*ppReg)(rreg_lrs[j].rreg);
- vex_printf("\n\n");
-# endif
- for (k =3D 0; k < n_rregs; k++)
- if (rreg_state[k].rreg =3D=3D rreg_lrs[j].rreg)
- break;
- /* If this fails, we don't have an entry for this rreg.
- Which we should. */
- vassert(IS_VALID_RREGNO(k));
- m =3D hregNumber(rreg_state[k].vreg);
- if (rreg_state[k].disp =3D=3D Bound) {
- /* Yes, there is an associated vreg. Spill it if it's
- still live. */
- vassert(IS_VALID_VREGNO(m));
- vreg_state[m] =3D INVALID_RREG_NO;
- if (vreg_lrs[m].dead_before > ii) {
- vassert(vreg_lrs[m].reg_class !=3D HRcINVALID);
- EMIT_INSTR( (*genSpill)( rreg_state[k].rreg,
- vreg_lrs[m].spill_offset,
- mode64 ) );
- }
+ while (True) {
+ vassert(rreg_lrs_la_next >=3D 0);
+ vassert(rreg_lrs_la_next <=3D rreg_lrs_used);
+ if (rreg_lrs_la_next =3D=3D rreg_lrs_used)
+ break; /* no more real reg live ranges to consider */
+ if (ii < rreg_lrs_la[rreg_lrs_la_next].live_after)
+ break; /* next live range does not yet start */
+ vassert(ii =3D=3D rreg_lrs_la[rreg_lrs_la_next].live_after);
+ /* rreg_lrs_la[rreg_lrs_la_next].rreg needs to be freed up.
+ Find the associated rreg_state entry. */
+ /* Note, re ii =3D=3D rreg_lrs_la[rreg_lrs_la_next].live_after.
+ Real register live ranges are guaranteed to be well-formed
+ in that they start with a write to the register -- Stage 2
+ rejects any code not satisfying this. So the correct
+ question to ask is whether
+ rreg_lrs_la[rreg_lrs_la_next].live_after =3D=3D ii, that is,
+ whether the reg becomes live after this insn -- rather
+ than before it. */
+# if DEBUG_REGALLOC
+ vex_printf("need to free up rreg: ");
+ (*ppReg)(rreg_lrs_la[rreg_lrs_la_next].rreg);
+ vex_printf("\n\n");
+# endif
+ for (k =3D 0; k < n_rregs; k++)
+ if (rreg_state[k].rreg =3D=3D rreg_lrs_la[rreg_lrs_la_next].=
rreg)
+ break;
+ /* If this fails, we don't have an entry for this rreg.
+ Which we should. */
+ vassert(IS_VALID_RREGNO(k));
+ m =3D hregNumber(rreg_state[k].vreg);
+ if (rreg_state[k].disp =3D=3D Bound) {
+ /* Yes, there is an associated vreg. Spill it if it's
+ still live. */
+ vassert(IS_VALID_VREGNO(m));
+ vreg_state[m] =3D INVALID_RREG_NO;
+ if (vreg_lrs[m].dead_before > ii) {
+ vassert(vreg_lrs[m].reg_class !=3D HRcINVALID);
+ EMIT_INSTR( (*genSpill)( rreg_state[k].rreg,
+ vreg_lrs[m].spill_offset,
+ mode64 ) );
}
- rreg_state[k].disp =3D Unavail;
- rreg_state[k].vreg =3D INVALID_HREG;
}
+ rreg_state[k].disp =3D Unavail;
+ rreg_state[k].vreg =3D INVALID_HREG;
+
+ /* check for further rregs entering HLRs at this point */
+ rreg_lrs_la_next++;
}
=20
+
# if DEBUG_REGALLOC
vex_printf("After pre-insn actions for fixed regs:\n");
PRINT_STATE;
@@ -1220,20 +1323,28 @@
=20
/* Now we need to check for rregs exiting fixed live ranges
after this instruction, and if so mark them as free. */
- for (j =3D 0; j < rreg_lrs_used; j++) {
- if (rreg_lrs[j].dead_before =3D=3D ii+1) {
- /* rreg_lrs[j].rreg is exiting a hard live range. Mark
- it as such in the main rreg_state array. */
- for (k =3D 0; k < n_rregs; k++)
- if (rreg_state[k].rreg =3D=3D rreg_lrs[j].rreg)
- break;
- /* If this vassertion fails, we don't have an entry for
- this rreg. Which we should. */
- vassert(k < n_rregs);
- vassert(rreg_state[k].disp =3D=3D Unavail);
- rreg_state[k].disp =3D Free;
- rreg_state[k].vreg =3D INVALID_HREG;
- }
+ while (True) {
+ vassert(rreg_lrs_db_next >=3D 0);
+ vassert(rreg_lrs_db_next <=3D rreg_lrs_used);
+ if (rreg_lrs_db_next =3D=3D rreg_lrs_used)
+ break; /* no more real reg live ranges to consider */
+ if (ii+1 < rreg_lrs_db[rreg_lrs_db_next].dead_before)
+ break; /* next live range does not yet start */
+ vassert(ii+1 =3D=3D rreg_lrs_db[rreg_lrs_db_next].dead_before);
+ /* rreg_lrs_db[[rreg_lrs_db_next].rreg is exiting a hard live
+ range. Mark it as such in the main rreg_state array. */
+ for (k =3D 0; k < n_rregs; k++)
+ if (rreg_state[k].rreg =3D=3D rreg_lrs_db[rreg_lrs_db_next].=
rreg)
+ break;
+ /* If this vassertion fails, we don't have an entry for
+ this rreg. Which we should. */
+ vassert(k < n_rregs);
+ vassert(rreg_state[k].disp =3D=3D Unavail);
+ rreg_state[k].disp =3D Free;
+ rreg_state[k].vreg =3D INVALID_HREG;
+
+ /* check for further rregs leaving HLRs at this point */
+ rreg_lrs_db_next++;
}
=20
# if DEBUG_REGALLOC
@@ -1254,6 +1365,9 @@
for (j =3D 0; j < n_rregs; j++)
vassert(rreg_state[j].rreg =3D=3D available_real_regs[j]);
=20
+ vassert(rreg_lrs_la_next =3D=3D rreg_lrs_used);
+ vassert(rreg_lrs_db_next =3D=3D rreg_lrs_used);
+
return instrs_out;
=20
# undef INVALID_INSTRNO
|
|
From: <sv...@va...> - 2006-12-26 02:34:32
|
Author: sewardj
Date: 2006-12-26 02:34:31 +0000 (Tue, 26 Dec 2006)
New Revision: 1700
Log:
Merge r1669 (ppc64 be imm64 improvements)
Modified:
branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.c
Modified: branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.c 2006-12-26 02:31:01 UTC=
(rev 1699)
+++ branches/VEX_3_2_BRANCH/priv/host-ppc/hdefs.c 2006-12-26 02:34:31 UTC=
(rev 1700)
@@ -1123,67 +1123,13 @@
=20
/* Pretty Print instructions */
static void ppLoadImm ( HReg dst, ULong imm, Bool mode64 ) {
-#if 1
vex_printf("li_word ");
ppHRegPPC(dst);
if (!mode64) {
- vassert(imm =3D=3D (ULong)(Long)(Int)(UInt)imm);
vex_printf(",0x%08x", (UInt)imm);
} else {
vex_printf(",0x%016llx", imm);
}
-#else
- if (imm >=3D 0xFFFFFFFFFFFF8000ULL || imm < 0x8000) {
- // sign-extendable from 16 bits
- vex_printf("li ");
- ppHRegPPC(dst);
- vex_printf(",0x%x", (UInt)imm);
- } else {
- if (imm >=3D 0xFFFFFFFF80000000ULL || imm < 0x80000000ULL) {
- // sign-extendable from 32 bits
- vex_printf("lis ");
- ppHRegPPC(dst);
- vex_printf(",0x%x ; ", (UInt)(imm >> 16));
- vex_printf("ori ");
- ppHRegPPC(dst);
- vex_printf(",");
- ppHRegPPC(dst);
- vex_printf(",0x%x", (UInt)(imm & 0xFFFF));
- } else {
- // full 64bit immediate load: 5 (five!) insns.
- vassert(mode64);
-
- // load high word
- vex_printf("lis ");
- ppHRegPPC(dst);
- vex_printf(",0x%x ; ", (UInt)(imm >> 48) & 0xFFFF);
- vex_printf("ori ");
- ppHRegPPC(dst);
- vex_printf(",");
- ppHRegPPC(dst);
- vex_printf(",0x%x ; ", (UInt)(imm >> 32) & 0xFFFF);
- =20
- // shift r_dst low word to high word =3D> rldicr
- vex_printf("rldicr ");
- ppHRegPPC(dst);
- vex_printf(",");
- ppHRegPPC(dst);
- vex_printf(",32,31 ; ");
-
- // load low word
- vex_printf("oris ");
- ppHRegPPC(dst);
- vex_printf(",");
- ppHRegPPC(dst);
- vex_printf(",0x%x ; ", (UInt)(imm >> 16) & 0xFFFF);
- vex_printf("ori ");
- ppHRegPPC(dst);
- vex_printf(",");
- ppHRegPPC(dst);
- vex_printf(",0x%x", (UInt)(imm >> 0) & 0xFFFF);
- }
- }
-#endif
}
=20
static void ppMovReg ( HReg dst, HReg src ) {
@@ -2496,19 +2442,26 @@
vassert(mode64);
=20
// load high word
+
// lis r_dst, (imm>>48) & 0xFFFF
p =3D mkFormD(p, 15, r_dst, 0, (imm>>48) & 0xFFFF);
+
// ori r_dst, r_dst, (imm>>32) & 0xFFFF
- p =3D mkFormD(p, 24, r_dst, r_dst, (imm>>32) & 0xFFFF);
+ if ((imm>>32) & 0xFFFF)
+ p =3D mkFormD(p, 24, r_dst, r_dst, (imm>>32) & 0xFFFF);
=20
// shift r_dst low word to high word =3D> rldicr
p =3D mkFormMD(p, 30, r_dst, r_dst, 32, 31, 1);
=20
// load low word
+
// oris r_dst, r_dst, (imm>>16) & 0xFFFF
- p =3D mkFormD(p, 25, r_dst, r_dst, (imm>>16) & 0xFFFF);
+ if ((imm>>16) & 0xFFFF)
+ p =3D mkFormD(p, 25, r_dst, r_dst, (imm>>16) & 0xFFFF);
+
// ori r_dst, r_dst, (imm) & 0xFFFF
- p =3D mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF);
+ if (imm & 0xFFFF)
+ p =3D mkFormD(p, 24, r_dst, r_dst, imm & 0xFFFF);
}
}
return p;
|
|
From: <sv...@va...> - 2006-12-26 02:31:04
|
Author: sewardj
Date: 2006-12-26 02:31:01 +0000 (Tue, 26 Dec 2006)
New Revision: 1699
Log:
Merge r1670/1 (ppc64 fe rld/rlw improvements)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c 2006-12-26 02:25:46 UTC=
(rev 1698)
+++ branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c 2006-12-26 02:31:01 UTC=
(rev 1699)
@@ -3288,6 +3288,7 @@
vassert(sh_imm < 32);
=20
if (mode64) {
+ IRTemp rTmp =3D newTemp(Ity_I64);
mask64 =3D MASK64(31-MaskEnd, 31-MaskBeg);
DIP("rlwinm%s r%u,r%u,%d,%d,%d\n", flag_rC ? ".":"",
rA_addr, rS_addr, sh_imm, MaskBeg, MaskEnd);
@@ -3295,8 +3296,10 @@
// rA =3D ((tmp32 || tmp32) & mask64)
r =3D ROTL( unop(Iop_64to32, mkexpr(rS) ), mkU8(sh_imm) );
r =3D unop(Iop_32Uto64, r);
- assign( rot, binop(Iop_Or64, r,
- binop(Iop_Shl64, r, mkU8(32))) );
+ assign( rTmp, r );
+ r =3D NULL;
+ assign( rot, binop(Iop_Or64, mkexpr(rTmp),
+ binop(Iop_Shl64, mkexpr(rTmp), mkU8(32))) );
assign( rA, binop(Iop_And64, mkexpr(rot), mkU64(mask64)) );
}
else {
@@ -3311,7 +3314,7 @@
/* Special-case the ,32-n,n,31 form as that is just n-bit
unsigned shift right, PPC32 p501 */
DIP("srwi%s r%u,r%u,%d\n", flag_rC ? ".":"",
- rA_addr, rS_addr, sh_imm);
+ rA_addr, rS_addr, MaskBeg);
assign( rA, binop(Iop_Shr32, mkexpr(rS), mkU8(MaskBeg)) );
}
else {
@@ -3356,7 +3359,6 @@
break;
}
=20
-
/* 64bit Integer Rotates */
case 0x1E: {
msk_imm =3D ((msk_imm & 1) << 5) | (msk_imm >> 1);
@@ -3402,24 +3404,38 @@
*/
=20
case 0x0: // rldicl (Rotl DWord Imm, Clear Left, PPC64 p558)
- DIP("rldicl%s r%u,r%u,%u,%u\n", flag_rC ? ".":"",
- rA_addr, rS_addr, sh_imm, msk_imm);
- r =3D ROTL(mkexpr(rS), mkU8(sh_imm));
- mask64 =3D MASK64(0, 63-msk_imm);
- assign( rA, binop(Iop_And64, r, mkU64(mask64)) );
+ if (mode64
+ && sh_imm + msk_imm =3D=3D 64 && msk_imm >=3D 1 && msk_imm =
<=3D 63) {
+ /* special-case the ,64-n,n form as that is just
+ unsigned shift-right by n */
+ DIP("srdi%s r%u,r%u,%u\n",
+ flag_rC ? ".":"", rA_addr, rS_addr, msk_imm);
+ assign( rA, binop(Iop_Shr64, mkexpr(rS), mkU8(msk_imm)) );
+ } else {
+ DIP("rldicl%s r%u,r%u,%u,%u\n", flag_rC ? ".":"",
+ rA_addr, rS_addr, sh_imm, msk_imm);
+ r =3D ROTL(mkexpr(rS), mkU8(sh_imm));
+ mask64 =3D MASK64(0, 63-msk_imm);
+ assign( rA, binop(Iop_And64, r, mkU64(mask64)) );
+ }
break;
- /* later: deal with special case:
- (msk_imm + sh_imm =3D=3D 63) =3D> SHR(63 - sh_imm) */
=20
case 0x1: // rldicr (Rotl DWord Imm, Clear Right, PPC64 p559)
- DIP("rldicr%s r%u,r%u,%u,%u\n", flag_rC ? ".":"",
- rA_addr, rS_addr, sh_imm, msk_imm);
- r =3D ROTL(mkexpr(rS), mkU8(sh_imm));
- mask64 =3D MASK64(63-msk_imm, 63);
- assign( rA, binop(Iop_And64, r, mkU64(mask64)) );
+ if (mode64=20
+ && sh_imm + msk_imm =3D=3D 63 && sh_imm >=3D 1 && sh_imm <=3D=
63) {
+ /* special-case the ,n,63-n form as that is just
+ shift-left by n */
+ DIP("sldi%s r%u,r%u,%u\n",
+ flag_rC ? ".":"", rA_addr, rS_addr, sh_imm);
+ assign( rA, binop(Iop_Shl64, mkexpr(rS), mkU8(sh_imm)) );
+ } else {
+ DIP("rldicr%s r%u,r%u,%u,%u\n", flag_rC ? ".":"",
+ rA_addr, rS_addr, sh_imm, msk_imm);
+ r =3D ROTL(mkexpr(rS), mkU8(sh_imm));
+ mask64 =3D MASK64(63-msk_imm, 63);
+ assign( rA, binop(Iop_And64, r, mkU64(mask64)) );
+ }
break;
- /* later: deal with special case:
- (msk_imm =3D=3D sh_imm) =3D> SHL(sh_imm) */
=20
case 0x3: { // rldimi (Rotl DWord Imm, Mask Insert, PPC64 p560)
IRTemp rA_orig =3D newTemp(ty);
|
|
From: <sv...@va...> - 2006-12-26 02:25:49
|
Author: sewardj
Date: 2006-12-26 02:25:46 +0000 (Tue, 26 Dec 2006)
New Revision: 1698
Log:
Merge r1678 (jcxz (x86))
Modified:
branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2006-12-26 02:24:12 UTC=
(rev 1697)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2006-12-26 02:25:46 UTC=
(rev 1698)
@@ -10834,6 +10834,28 @@
=20
after_sse_decoders:
=20
+ /* ---------------------------------------------------- */
+ /* --- deal with misc 0x67 pfxs (addr size override) -- */
+ /* ---------------------------------------------------- */
+
+ /* 67 E3 =3D JCXZ (for JECXZ see below) */
+ if (insn[0] =3D=3D 0x67 && insn[1] =3D=3D 0xE3 && sz =3D=3D 4) {
+ delta +=3D 2;
+ d32 =3D (((Addr32)guest_EIP_bbstart)+delta+1) + getSDisp8(delta);
+ delta ++;
+ stmt( IRStmt_Exit(
+ binop(Iop_CmpEQ16, getIReg(2,R_ECX), mkU16(0)),
+ Ijk_Boring,
+ IRConst_U32(d32)
+ ));
+ DIP("jcxz 0x%x\n", d32);
+ goto decode_success;
+ }
+
+ /* ---------------------------------------------------- */
+ /* --- start of the baseline insn decoder -- */
+ /* ---------------------------------------------------- */
+
/* Get the primary opcode. */
opc =3D getIByte(delta); delta++;
=20
@@ -11164,21 +11186,16 @@
DIP("j%s-8 0x%x\n", name_X86Condcode(opc - 0x70), d32);
break;
=20
- case 0xE3: /* JECXZ or perhaps JCXZ, depending on OSO ? Intel
- manual says it depends on address size override. */
+ case 0xE3: /* JECXZ (for JCXZ see above) */
if (sz !=3D 4) goto decode_failure;
d32 =3D (((Addr32)guest_EIP_bbstart)+delta+1) + getSDisp8(delta);
- delta++;
- ty =3D szToITy(sz);
+ delta ++;
stmt( IRStmt_Exit(
- binop(mkSizedOp(ty,Iop_CmpEQ8),
- getIReg(sz,R_ECX),
- mkU(ty,0)),
+ binop(Iop_CmpEQ32, getIReg(4,R_ECX), mkU32(0)),
Ijk_Boring,
- IRConst_U32(d32))=20
- );
-
- DIP("j%sz 0x%x\n", nameIReg(sz, R_ECX), d32);
+ IRConst_U32(d32)
+ ));
+ DIP("jecxz 0x%x\n", d32);
break;
=20
case 0xE0: /* LOOPNE disp8: decrement count, jump if count !=3D 0 && =
ZF=3D=3D0 */
|
|
From: <sv...@va...> - 2006-12-26 02:24:14
|
Author: sewardj
Date: 2006-12-26 02:24:12 +0000 (Tue, 26 Dec 2006)
New Revision: 1697
Log:
Merge r1675 (x86 COPY-CondP rule)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c 2006-12-26 02:22:38=
UTC (rev 1696)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c 2006-12-26 02:24:12=
UTC (rev 1697)
@@ -1161,6 +1161,23 @@
);
}
=20
+ if (isU32(cc_op, X86G_CC_OP_COPY) && isU32(cond, X86CondP)) {
+ /* COPY, then P --> extract P from dep1, and test (P =3D=3D 1).=
*/
+ return
+ unop(
+ Iop_1Uto32,
+ binop(
+ Iop_CmpNE32,
+ binop(
+ Iop_And32,
+ binop(Iop_Shr32, cc_dep1, mkU8(X86G_CC_SHIFT_P)),
+ mkU32(1)
+ ),
+ mkU32(0)
+ )
+ );
+ }
+
return NULL;
}
=20
|
|
From: <sv...@va...> - 2006-12-26 02:22:40
|
Author: sewardj
Date: 2006-12-26 02:22:38 +0000 (Tue, 26 Dec 2006)
New Revision: 1696
Log:
Duh; fix compile breakage caused by r1694.
Modified:
branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2006-12-26 02:08:21 U=
TC (rev 1695)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2006-12-26 02:22:38 U=
TC (rev 1696)
@@ -12170,7 +12170,7 @@
if (have66orF2orF3(pfx)) goto decode_failure;
d64 =3D getUDisp16(delta);=20
delta +=3D 2;
- dis_ret(vmi, d64);
+ dis_ret(d64);
dres.whatNext =3D Dis_StopHere;
DIP("ret %lld\n", d64);
break;
|
|
From: <sv...@va...> - 2006-12-26 02:08:23
|
Author: sewardj
Date: 2006-12-26 02:08:21 +0000 (Tue, 26 Dec 2006)
New Revision: 1695
Log:
Merge r1679 (x86 Grp5(R) case 6)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2006-12-26 02:06:09 UTC=
(rev 1694)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2006-12-26 02:08:21 UTC=
(rev 1695)
@@ -2815,6 +2815,13 @@
jmp_treg(Ijk_Boring,t1);
dres->whatNext =3D Dis_StopHere;
break;
+ case 6: /* PUSH Ev */
+ vassert(sz =3D=3D 4 || sz =3D=3D 2);
+ t2 =3D newTemp(Ity_I32);
+ assign( t2, binop(Iop_Sub32,getIReg(4,R_ESP),mkU32(sz)) );
+ putIReg(4, R_ESP, mkexpr(t2) );
+ storeLE( mkexpr(t2), mkexpr(t1) );
+ break;
default:=20
vex_printf(
"unhandled Grp5(R) case %d\n", (Int)gregOfRM(modrm));
|
|
From: <sv...@va...> - 2006-12-26 02:06:10
|
Author: sewardj
Date: 2006-12-26 02:06:09 +0000 (Tue, 26 Dec 2006)
New Revision: 1694
Log:
Merge r1676 (amd64 ret imm16)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2006-12-26 02:04:04 U=
TC (rev 1693)
+++ branches/VEX_3_2_BRANCH/priv/guest-amd64/toIR.c 2006-12-26 02:06:09 U=
TC (rev 1694)
@@ -514,13 +514,13 @@
return v;
}
=20
-//.. static UInt getUDisp16 ( Long delta )
-//.. {
-//.. UInt v =3D guest_code[delta+1]; v <<=3D 8;
-//.. v |=3D guest_code[delta+0];
-//.. return v & 0xFFFF;
-//.. }
-//..=20
+static UInt getUDisp16 ( Long delta )
+{
+ UInt v =3D guest_code[delta+1]; v <<=3D 8;
+ v |=3D guest_code[delta+0];
+ return v & 0xFFFF;
+}
+
//.. static UInt getUDisp ( Int size, Long delta )
//.. {
//.. switch (size) {
@@ -733,6 +733,12 @@
return toBool( ! haveNo66noF2noF3(pfx) );
}
=20
+/* Return True iff pfx has 66 or F2 set */
+static Bool have66orF2 ( Prefix pfx )
+{
+ return toBool((pfx & (PFX_66|PFX_F2)) > 0);
+}
+
/* Clear all the segment-override bits in a prefix. */
static Prefix clearSegBits ( Prefix p )
{
@@ -12160,15 +12166,17 @@
=20
/* ------------------------ Control flow --------------- */
=20
-//.. case 0xC2: /* RET imm16 */
-//.. d32 =3D getUDisp16(delta);=20
-//.. delta +=3D 2;
-//.. dis_ret(d32);
-//.. whatNext =3D Dis_StopHere;
-//.. DIP("ret %d\n", d32);
-//.. break;
+ case 0xC2: /* RET imm16 */
+ if (have66orF2orF3(pfx)) goto decode_failure;
+ d64 =3D getUDisp16(delta);=20
+ delta +=3D 2;
+ dis_ret(vmi, d64);
+ dres.whatNext =3D Dis_StopHere;
+ DIP("ret %lld\n", d64);
+ break;
+
case 0xC3: /* RET */
- if (haveF2(pfx)) goto decode_failure;
+ if (have66orF2(pfx)) goto decode_failure;
/* F3 is acceptable on AMD. */
dis_ret(0);
dres.whatNext =3D Dis_StopHere;
|
|
From: <sv...@va...> - 2006-12-26 02:04:09
|
Author: sewardj
Date: 2006-12-26 02:04:04 +0000 (Tue, 26 Dec 2006)
New Revision: 1693
Log:
Merge r1673/4 (x86 repne movsw)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2006-12-26 02:01:37 UTC=
(rev 1692)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2006-12-26 02:04:04 UTC=
(rev 1693)
@@ -11919,17 +11919,22 @@
/* According to the Intel manual, "repne movs" should never occur,=
but
* in practice it has happened, so allow for it here... */
case 0xA4: sz =3D 1; /* REPNE MOVS<sz> */
- goto decode_failure;
-//-- case 0xA5:=20
- // dis_REP_op ( CondNZ, dis_MOVS, sz, eip_orig,
- // guest_eip_bbstart+delta, "repne =
movs" );
- // break;
+ case 0xA5:=20
+ dis_REP_op ( X86CondNZ, dis_MOVS, sz, eip_orig,
+ guest_EIP_bbstart+delta, "repne movs" )=
;
+ break;
//--=20
//-- case 0xA6: sz =3D 1; /* REPNE CMPS<sz> */
//-- case 0xA7:
//-- dis_REP_op ( cb, CondNZ, dis_CMPS, sz, eip_orig, eip, "rep=
ne cmps" );
//-- break;
//--=20
+ case 0xAA: sz =3D 1; /* REPNE STOS<sz> */
+ case 0xAB:
+ dis_REP_op ( X86CondNZ, dis_STOS, sz, eip_orig,=20
+ guest_EIP_bbstart+delta, "repne stos" )=
;
+ break;
+
case 0xAE: sz =3D 1; /* REPNE SCAS<sz> */
case 0xAF:
dis_REP_op ( X86CondNZ, dis_SCAS, sz, eip_orig,
|
|
From: <sv...@va...> - 2006-12-26 02:01:39
|
Author: sewardj
Date: 2006-12-26 02:01:37 +0000 (Tue, 26 Dec 2006)
New Revision: 1692
Log:
Merge r1672 (x86 xlat)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2006-12-26 01:58:54 UTC=
(rev 1691)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/toIR.c 2006-12-26 02:01:37 UTC=
(rev 1692)
@@ -12041,23 +12041,23 @@
codegen_xchg_eAX_Reg ( sz, opc - 0x90 );
break;
=20
-//-- /* ------------------------ XLAT ----------------------- */
-//--=20
-//-- case 0xD7: /* XLAT */
-//-- t1 =3D newTemp(cb); t2 =3D newTemp(cb);
-//-- uInstr2(cb, GET, sz, ArchReg, R_EBX, TempReg, t1); /* get eBX=
*/
-//-- handleSegOverride( cb, sorb, t1 ); /* make t1 D=
S:eBX */
-//-- uInstr2(cb, GET, 1, ArchReg, R_AL, TempReg, t2); /* get AL */
-//-- /* Widen %AL to 32 bits, so it's all defined when we add it. =
*/
-//-- uInstr1(cb, WIDEN, 4, TempReg, t2);
-//-- uWiden(cb, 1, False);
-//-- uInstr2(cb, ADD, sz, TempReg, t2, TempReg, t1); /* add AL to=
eBX */
-//-- uInstr2(cb, LOAD, 1, TempReg, t1, TempReg, t2); /* get byte =
at t1 into t2 */
-//-- uInstr2(cb, PUT, 1, TempReg, t2, ArchReg, R_AL); /* put byte =
into AL */
-//--=20
-//-- DIP("xlat%c [ebx]\n", nameISize(sz));
-//-- break;
+ /* ------------------------ XLAT ----------------------- */
=20
+ case 0xD7: /* XLAT */
+ if (sz !=3D 4) goto decode_failure; /* sz =3D=3D 2 is also allowed=
(0x66) */
+ putIReg(=20
+ 1,=20
+ R_EAX/*AL*/,
+ loadLE(Ity_I8,=20
+ handleSegOverride(=20
+ sorb,=20
+ binop(Iop_Add32,=20
+ getIReg(4, R_EBX),=20
+ unop(Iop_8Uto32, getIReg(1, R_EAX/*AL*/))))));
+
+ DIP("xlat%c [ebx]\n", nameISize(sz));
+ break;
+
/* ------------------------ IN / OUT ----------------------- */
=20
case 0xE4: /* IN imm8, AL */
|
|
From: <sv...@va...> - 2006-12-26 01:58:55
|
Author: sewardj
Date: 2006-12-26 01:58:54 +0000 (Tue, 26 Dec 2006)
New Revision: 1691
Log:
Merge r1667 (ppc32/64: support mcrfs)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c 2006-12-26 01:56:49 UTC=
(rev 1690)
+++ branches/VEX_3_2_BRANCH/priv/guest-ppc/toIR.c 2006-12-26 01:58:54 UTC=
(rev 1691)
@@ -6497,23 +6497,27 @@
break;
}
=20
-//zz case 0x040: { // mcrfs (Move to Condition Register from FPSCR, P=
PC32 p465)
-//zz UChar crfD =3D toUChar( IFIELD( theInstr, 23, 3 ) );
-//zz UChar b21to22 =3D toUChar( IFIELD( theInstr, 21, 2 ) );
-//zz UChar crfS =3D toUChar( IFIELD( theInstr, 18, 3 ) );
-//zz UChar b11to17 =3D toUChar( IFIELD( theInstr, 11, 7 ) );
-//zz=20
-//zz IRTemp tmp =3D newTemp(Ity_I32);
-//zz=20
-//zz if (b21to22 !=3D 0 || b11to17 !=3D 0 || flag_rC !=3D 0) {
-//zz vex_printf("dis_fp_scr(ppc)(instr,mcrfs)\n");
-//zz return False;
-//zz }
-//zz DIP("mcrfs crf%d,crf%d\n", crfD, crfS);
-//zz assign( tmp, getGST_field( PPC_GST_FPSCR, crfS ) );
-//zz putGST_field( PPC_GST_CR, mkexpr(tmp), crfD );
-//zz break;
-//zz }
+ case 0x040: { // mcrfs (Move to Condition Register from FPSCR, PPC32 =
p465)
+ UChar crfD =3D toUChar( IFIELD( theInstr, 23, 3 ) );
+ UChar b21to22 =3D toUChar( IFIELD( theInstr, 21, 2 ) );
+ UChar crfS =3D toUChar( IFIELD( theInstr, 18, 3 ) );
+ UChar b11to17 =3D toUChar( IFIELD( theInstr, 11, 7 ) );
+ IRTemp tmp =3D newTemp(Ity_I32);
+ IRExpr* fpscr_all;
+ if (b21to22 !=3D 0 || b11to17 !=3D 0 || flag_rC !=3D 0) {
+ vex_printf("dis_fp_scr(ppc)(instr,mcrfs)\n");
+ return False;
+ }
+ DIP("mcrfs crf%d,crf%d\n", crfD, crfS);
+ vassert(crfD < 8);
+ vassert(crfS < 8);
+ fpscr_all =3D getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN );
+ assign( tmp, binop(Iop_And32,
+ binop(Iop_Shr32,fpscr_all,mkU8(4 * (7-crfS))),
+ mkU32(0xF)) );
+ putGST_field( PPC_GST_CR, mkexpr(tmp), crfD );
+ break;
+ }
=20
case 0x046: { // mtfsb0 (Move to FPSCR Bit 0, PPC32 p478)
// Bit crbD of the FPSCR is cleared.
@@ -6545,8 +6549,9 @@
}
=20
case 0x247: { // mffs (Move from FPSCR, PPC32 p468)
- UChar frD_addr =3D ifieldRegDS(theInstr);
- UInt b11to20 =3D IFIELD(theInstr, 11, 10);
+ UChar frD_addr =3D ifieldRegDS(theInstr);
+ UInt b11to20 =3D IFIELD(theInstr, 11, 10);
+ IRExpr* fpscr_all =3D getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN =
);
=20
if (b11to20 !=3D 0) {
vex_printf("dis_fp_scr(ppc)(instr,mffs)\n");
@@ -6555,8 +6560,7 @@
DIP("mffs%s fr%u\n", flag_rC ? ".":"", frD_addr);
putFReg( frD_addr,
unop( Iop_ReinterpI64asF64,
- unop( Iop_32Uto64,=20
- getGST_masked( PPC_GST_FPSCR, MASK_FPSCR_RN ) )));
+ unop( Iop_32Uto64, fpscr_all )));
break;
}
=20
@@ -9004,7 +9008,7 @@
=20
/* Floating Point Status/Control Register Instructions */ =20
case 0x026: // mtfsb1
- /* case 0x040: // mcrfs */
+ case 0x040: // mcrfs
case 0x046: // mtfsb0
case 0x086: // mtfsfi
case 0x247: // mffs
|
|
From: <sv...@va...> - 2006-12-26 01:56:51
|
Author: sewardj
Date: 2006-12-26 01:56:49 +0000 (Tue, 26 Dec 2006)
New Revision: 1690
Log:
Merge r1660 (%eflags rule for SUBL-CondNLE)
Modified:
branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c
Modified: branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c 2006-12-24 02:20:24=
UTC (rev 1689)
+++ branches/VEX_3_2_BRANCH/priv/guest-x86/ghelpers.c 2006-12-26 01:56:49=
UTC (rev 1690)
@@ -853,6 +853,16 @@
binop(Iop_CmpLE32S, cc_dep1, cc_dep2));
}
=20
+ if (isU32(cc_op, X86G_CC_OP_SUBL) && isU32(cond, X86CondNLE)) {
+ /* long sub/cmp, then LE (signed not less than or equal)
+ --> test dst >s src=20
+ --> test !(dst <=3Ds src) */
+ return binop(Iop_Xor32,
+ unop(Iop_1Uto32,
+ binop(Iop_CmpLE32S, cc_dep1, cc_dep2)),
+ mkU32(1));
+ }
+
if (isU32(cc_op, X86G_CC_OP_SUBL) && isU32(cond, X86CondBE)) {
/* long sub/cmp, then BE (unsigned less than or equal)
--> test dst <=3Du src */
|
|
From: <js...@ac...> - 2006-12-26 01:16:07
|
Nightly build on g5 ( SuSE 10.1, ppc970 ) started at 2006-12-26 02:00:01 CET Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 221 tests, 6 stderr failures, 2 stdout failures, 0 posttest failures == memcheck/tests/deep_templates (stdout) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) none/tests/mremap2 (stdout) |