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From: <sv...@va...> - 2006-01-03 18:41:04
|
Author: sewardj
Date: 2006-01-03 18:41:00 +0000 (Tue, 03 Jan 2006)
New Revision: 1530
Log:
Fix magic-sequence spotting in 64-bit mode.
Modified:
trunk/priv/guest-ppc/toIR.c
Modified: trunk/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/toIR.c 2006-01-03 18:40:18 UTC (rev 1529)
+++ trunk/priv/guest-ppc/toIR.c 2006-01-03 18:41:00 UTC (rev 1530)
@@ -8361,11 +8361,39 @@
=20
/* Spot the client-request magic sequence. */
// Essentially a v. unlikely sequence of noops that we can catch
- {
+ if (mode64) {
+ /* Spot the magic sequence, 64-bit mode */
UChar* code =3D (UChar*)(&guest_code[delta]);
=20
/* Spot this: =20
0x7C03D808 tw 0,3,27 =3D> trap word if (0) =3D> no=
p
+ 0x7800E802 rotldi 0,0,61 =3D> ro =3D rotl(r0,61)
+ 0x78001800 rotldi 0,0,3 =3D> ro =3D rotl(r0,3)
+ 0x78006800 rotldi 0,0,13 =3D> ro =3D rotl(r0,13)
+ 0x78009802 rotldi 0,0,51 =3D> ro =3D rotl(r0,51)
+ 0x60000000 nop
+ */
+ if (getUIntBigendianly(code+ 0) =3D=3D 0x7C03D808 &&
+ getUIntBigendianly(code+ 4) =3D=3D 0x7800E802 &&
+ getUIntBigendianly(code+ 8) =3D=3D 0x78001800 &&
+ getUIntBigendianly(code+12) =3D=3D 0x78006800 &&
+ getUIntBigendianly(code+16) =3D=3D 0x78009802 &&
+ getUIntBigendianly(code+20) =3D=3D 0x60000000) {
+ DIP("%%r3 =3D client_request ( %%r31 )\n");
+ dres.len =3D 24;
+ delta +=3D 24;
+
+ irbb->next =3D mkSzImm( ty, guest_CIA_bbstart + delta );
+ irbb->jumpkind =3D Ijk_ClientReq;
+ dres.whatNext =3D Dis_StopHere;
+ goto decode_success;
+ }
+ } else {
+ /* Spot the magic sequence, 32-bit mode */
+ UChar* code =3D (UChar*)(&guest_code[delta]);
+
+ /* Spot this: =20
+ 0x7C03D808 tw 0,3,27 =3D> trap word if (0) =3D> no=
p
0x5400E800 rlwinm 0,0,29,0,0 =3D> r0 =3D rotl(r0,29)
0x54001800 rlwinm 0,0, 3,0,0 =3D> r0 =3D rotl(r0, 3)
0x54006800 rlwinm 0,0,13,0,0 =3D> r0 =3D rotl(r0,13)
|
|
From: <sv...@va...> - 2006-01-03 18:40:22
|
Author: sewardj
Date: 2006-01-03 18:40:18 +0000 (Tue, 03 Jan 2006)
New Revision: 1529
Log:
Add missing function.
Modified:
trunk/priv/guest-ppc/ghelpers.c
Modified: trunk/priv/guest-ppc/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/ghelpers.c 2006-01-02 15:15:45 UTC (rev 1528)
+++ trunk/priv/guest-ppc/ghelpers.c 2006-01-03 18:40:18 UTC (rev 1529)
@@ -306,6 +306,16 @@
vex_state->guest_XER_CA =3D toUChar((xer_native >> 29) & 0x1);
}
=20
+/* VISIBLE TO LIBVEX CLIENT */
+/* Note: %XER is 32 bits even for ppc64 */
+void LibVEX_GuestPPC64_put_XER ( UInt xer_native,
+ /*OUT*/VexGuestPPC64State* vex_state )
+{
+ vex_state->guest_XER_BC =3D toUChar(xer_native & 0xFF);
+ vex_state->guest_XER_SO =3D toUChar((xer_native >> 31) & 0x1);
+ vex_state->guest_XER_OV =3D toUChar((xer_native >> 30) & 0x1);
+ vex_state->guest_XER_CA =3D toUChar((xer_native >> 29) & 0x1);
+}
=20
/* VISIBLE TO LIBVEX CLIENT */
void LibVEX_GuestPPC32_initialise ( /*OUT*/VexGuestPPC32State* vex_state=
)
|
|
From: <sv...@va...> - 2006-01-03 18:08:48
|
Author: dirk
Date: 2006-01-03 18:08:38 +0000 (Tue, 03 Jan 2006)
New Revision: 5492
Log:
update suppression for Xorg 6.9.0
Modified:
branches/VALGRIND_3_1_BRANCH/xfree-4.supp
Modified: branches/VALGRIND_3_1_BRANCH/xfree-4.supp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/VALGRIND_3_1_BRANCH/xfree-4.supp 2006-01-03 18:04:32 UTC (re=
v 5491)
+++ branches/VALGRIND_3_1_BRANCH/xfree-4.supp 2006-01-03 18:08:38 UTC (re=
v 5492)
@@ -183,5 +183,16 @@
fun:_XSend
}
=20
+{
+ Xorg 6.9.0 writev uninit padding
+ Memcheck:Param
+ writev(vector[...])
+ fun:do_writev
+ fun:writev
+ obj:/usr/X11R6/lib*/libX11.so.6.2
+ fun:_X11TransWritev
+ fun:_XSend
+}
+
##----------------------------------------------------------------------=
##
=20
|
|
From: <sv...@va...> - 2006-01-03 18:04:42
|
Author: dirk
Date: 2006-01-03 18:04:32 +0000 (Tue, 03 Jan 2006)
New Revision: 5491
Log:
update suppression for newer versions of Xorg
Modified:
trunk/xfree-4.supp
Modified: trunk/xfree-4.supp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/xfree-4.supp 2006-01-03 14:28:02 UTC (rev 5490)
+++ trunk/xfree-4.supp 2006-01-03 18:04:32 UTC (rev 5491)
@@ -183,5 +183,16 @@
fun:_XSend
}
=20
+{
+ Xorg 6.9.0 writev uninit padding
+ Memcheck:Param
+ writev(vector[...])
+ fun:do_writev
+ fun:writev
+ obj:/usr/X11R6/lib*/libX11.so.6.2
+ fun:_X11TransWritev
+ fun:_XSend
+}
+
##----------------------------------------------------------------------=
##
=20
|
|
From: <sv...@va...> - 2006-01-03 14:28:08
|
Author: cerion
Date: 2006-01-03 14:28:02 +0000 (Tue, 03 Jan 2006)
New Revision: 5490
Log:
Tidy up some ppc64 assembly & comments a little.
Modified:
trunk/coregrind/m_syswrap/syswrap-ppc64-linux.c
Modified: trunk/coregrind/m_syswrap/syswrap-ppc64-linux.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syswrap-ppc64-linux.c 2006-01-03 14:20:36 U=
TC (rev 5489)
+++ trunk/coregrind/m_syswrap/syswrap-ppc64-linux.c 2006-01-03 14:28:02 U=
TC (rev 5490)
@@ -140,7 +140,7 @@
pid_t* parent_tid in r8
void* ??? in r9
=20
- Note: r3 contains fn ptr, not fn entry ptr -- needs toc deref
+ Note: r3 contains fn desc ptr, not fn ptr -- p_fn =3D p_fn_desc[=
0]
System call requires:
=20
int $__NR_clone in r0 (sc number)
@@ -185,7 +185,8 @@
=20
// setup child stack
" rldicr 4,4, 0,59\n" // trim sp to multiple of 16 bytes
-" li 0,0\n" // (r4 &=3D ~0xF)
+ // (r4 &=3D ~0xF)
+" li 0,0\n"
" stdu 0,-32(4)\n" // make initial stack frame
" mr 29,4\n" // preserve sp
=20
@@ -202,13 +203,10 @@
" sc\n" // clone()
=20
" mfcr 4\n" // CR now in low half r4
-" sldi 4,4,16\n"
-" sldi 4,4,16\n" // CR now in hi half r4
+" sldi 4,4,32\n" // CR now in hi half r4
=20
-" sldi 3,3,16\n"
-" sldi 3,3,16\n"
-" srdi 3,3,16\n"
-" srdi 3,3,16\n" // zero out hi half r3
+" sldi 3,3,32\n"
+" srdi 3,3,32\n" // zero out hi half r3
=20
" or 3,3,4\n" // r3 =3D CR : syscall-retval
" cmpwi 3,0\n" // child if retval =3D=3D 0 (note, =
cmpw)
@@ -220,7 +218,7 @@
That does leave a small window for a signal to be delivered
on the wrong stack, unfortunately. */
" mr 1,29\n"
-" ld 30, 0(30)\n" // convert fn ptr to fn entry
+" ld 30, 0(30)\n" // convert fn desc ptr to fn ptr
" mtctr 30\n" // ctr reg =3D fn
" mr 3,31\n" // r3 =3D arg
" bctrl\n" // call fn()
|
|
From: <sv...@va...> - 2006-01-03 14:20:41
|
Author: cerion Date: 2006-01-03 14:20:36 +0000 (Tue, 03 Jan 2006) New Revision: 5489 Log: couple more svn:ignore's Modified: trunk/perf/ Property changes on: trunk/perf ___________________________________________________________________ Name: svn:ignore - .deps Makefile Makefile.in fbench vg_perf ffbench bz2 sarp bigcode + .deps Makefile Makefile.in fbench vg_perf ffbench bz2 sarp bigcode tinycc heap |
|
From: <sv...@va...> - 2006-01-03 14:08:37
|
Author: cerion Date: 2006-01-03 14:08:26 +0000 (Tue, 03 Jan 2006) New Revision: 5488 Log: Add ppc64 int,fp,vmx regtest: jm-insns (test code is a symlink to ppc32/jm-insns.c) Added: trunk/none/tests/ppc64/filter_stderr trunk/none/tests/ppc64/jm-fp.stderr.exp trunk/none/tests/ppc64/jm-fp.stdout.exp trunk/none/tests/ppc64/jm-fp.vgtest trunk/none/tests/ppc64/jm-insns.c trunk/none/tests/ppc64/jm-int.stderr.exp trunk/none/tests/ppc64/jm-int.stdout.exp trunk/none/tests/ppc64/jm-int.vgtest trunk/none/tests/ppc64/jm-vmx.stderr.exp trunk/none/tests/ppc64/jm-vmx.stdout.exp trunk/none/tests/ppc64/jm-vmx.vgtest Modified: trunk/none/tests/ppc64/Makefile.am [... diff too large to include ...] |
|
From: <sv...@va...> - 2006-01-03 12:55:51
|
Author: cerion
Date: 2006-01-03 12:55:40 +0000 (Tue, 03 Jan 2006)
New Revision: 5487
Log:
Update ppc32 jm-insns regtest to test ppc64 insns, if built with -m64.
Modified:
trunk/none/tests/ppc32/jm-insns.c
Modified: trunk/none/tests/ppc32/jm-insns.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/jm-insns.c 2006-01-03 11:47:38 UTC (rev 5486)
+++ trunk/none/tests/ppc32/jm-insns.c 2006-01-03 12:55:40 UTC (rev 5487)
@@ -1,7 +1,10 @@
=20
/* HOW TO COMPILE:
=20
-gcc -Winline -Wall -O -mregnames -DHAS_ALTIVEC -maltivec=20
+* 32bit build:
+ gcc -Winline -Wall -g -O -mregnames -DHAS_ALTIVEC -maltivec
+* 64bit build:
+ gcc -Winline -Wall -g -O -mregnames -DHAS_ALTIVEC -maltivec -m64
=20
This program is useful, but the register usage conventions in
it are a complete dog. In particular, _patch_op_imm has to
@@ -167,7 +170,11 @@
=20
/* Something of the same size as void*, so can be safely be coerced
to/from a pointer type. Also same size as the host's gp registers. */
+#ifndef __powerpc64__
typedef uint32_t HWord_t;
+#else
+typedef uint64_t HWord_t;
+#endif // #ifndef __powerpc64__
=20
=20
register double f14 __asm__ ("f14");
@@ -197,6 +204,7 @@
=20
=20
=20
+#ifndef __powerpc64__
#define ASSEMBLY_FUNC(__fname, __insn) \
asm(".section \".text\"\n" \
"\t.align 2\n" \
@@ -206,6 +214,23 @@
"\tblr\n" \
"\t.previous\n" \
)
+#else
+#define ASSEMBLY_FUNC(__fname, __insn) \
+asm(".section \".text\"\n" \
+ "\t.align 2\n" \
+ "\t.global "__fname"\n" \
+ "\t.section \".opd\",\"aw\"\n" \
+ "\t.align 3\n" \
+ ""__fname":\n" \
+ "\t.quad ."__fname",.TOC.@tocbase,0\n" \
+ "\t.previous\n" \
+ "\t.type ."__fname",@function\n" \
+ "\t.global ."__fname"\n" \
+ "."__fname":\n" \
+ "\t"__insn"\n" \
+ "\tblr\n" \
+ )
+#endif // #ifndef __powerpc64__
=20
=20
=20
@@ -432,6 +457,33 @@
__asm__ __volatile__ ("subfco 17, 14, 15");
}
=20
+#ifdef __powerpc64__
+static void test_mulld (void)
+{
+ __asm__ __volatile__ ("mulld 17, 14, 15");
+}
+
+static void test_mulhd (void)
+{
+ __asm__ __volatile__ ("mulhd 17, 14, 15");
+}
+
+static void test_mulhdu (void)
+{
+ __asm__ __volatile__ ("mulhdu 17, 14, 15");
+}
+
+static void test_divd (void)
+{
+ __asm__ __volatile__ ("divd 17, 14, 15");
+}
+
+static void test_divdu (void)
+{
+ __asm__ __volatile__ ("divdu 17, 14, 15");
+}
+#endif // #ifdef __powerpc64__
+
static test_t tests_ia_ops_two[] =3D {
{ &test_add , " add", },
{ &test_addo , " addo", },
@@ -449,6 +501,13 @@
{ &test_subfo , " subfo", },
{ &test_subfc , " subfc", },
{ &test_subfco , " subfco", },
+#ifdef __powerpc64__
+ { &test_mulhd , " mulhd", },
+ { &test_mulhdu , " mulhdu", },
+ { &test_mulld , " mulld", },
+ { &test_divd , " divd", },
+ { &test_divdu , " divdu", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
=20
@@ -532,6 +591,33 @@
__asm__ __volatile__ ("subfco. 17, 14, 15");
}
=20
+#ifdef __powerpc64__
+static void test_mulhd_ (void)
+{
+ __asm__ __volatile__ ("mulhd. 17, 14, 15");
+}
+
+static void test_mulhdu_ (void)
+{
+ __asm__ __volatile__ ("mulhdu. 17, 14, 15");
+}
+
+static void test_mulld_ (void)
+{
+ __asm__ __volatile__ ("mulld. 17, 14, 15");
+}
+
+static void test_divd_ (void)
+{
+ __asm__ __volatile__ ("divd. 17, 14, 15");
+}
+
+static void test_divdu_ (void)
+{
+ __asm__ __volatile__ ("divdu. 17, 14, 15");
+}
+#endif // #ifdef __powerpc64__
+
static test_t tests_iar_ops_two[] =3D {
{ &test_add_ , " add.", },
{ &test_addo_ , " addo.", },
@@ -549,6 +635,13 @@
{ &test_subfo_ , " subfo.", },
{ &test_subfc_ , " subfc.", },
{ &test_subfco_ , " subfco.", },
+#ifdef __powerpc64__
+ { &test_mulhd_ , " mulhd.", },
+ { &test_mulhdu_ , " mulhdu.", },
+ { &test_mulld_ , " mulld.", },
+ { &test_divd_ , " divd.", },
+ { &test_divdu_ , " divdu.", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
=20
@@ -663,6 +756,23 @@
__asm__ __volatile__ ("srw 17, 14, 15");
}
=20
+#ifdef __powerpc64__
+static void test_sld (void)
+{
+ __asm__ __volatile__ ("sld 17, 14, 15");
+}
+
+static void test_srad (void)
+{
+ __asm__ __volatile__ ("srad 17, 14, 15");
+}
+
+static void test_srd (void)
+{
+ __asm__ __volatile__ ("srd 17, 14, 15");
+}
+#endif // #ifdef __powerpc64__
+
static test_t tests_il_ops_two[] =3D {
{ &test_and , " and", },
{ &test_andc , " andc", },
@@ -675,6 +785,11 @@
{ &test_slw , " slw", },
{ &test_sraw , " sraw", },
{ &test_srw , " srw", },
+#ifdef __powerpc64__
+ { &test_sld , " sld", },
+ { &test_srad , " srad", },
+ { &test_srd , " srd", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
=20
@@ -733,6 +848,23 @@
__asm__ __volatile__ ("srw. 17, 14, 15");
}
=20
+#ifdef __powerpc64__
+static void test_sld_ (void)
+{
+ __asm__ __volatile__ ("sld. 17, 14, 15");
+}
+
+static void test_srad_ (void)
+{
+ __asm__ __volatile__ ("srad. 17, 14, 15");
+}
+
+static void test_srd_ (void)
+{
+ __asm__ __volatile__ ("srd. 17, 14, 15");
+}
+#endif // #ifdef __powerpc64__
+
static test_t tests_ilr_ops_two[] =3D {
{ &test_and_ , " and.", },
{ &test_andc_ , " andc.", },
@@ -745,6 +877,11 @@
{ &test_slw_ , " slw.", },
{ &test_sraw_ , " sraw.", },
{ &test_srw_ , " srw.", },
+#ifdef __powerpc64__
+ { &test_sld_ , " sld.", },
+ { &test_srad_ , " srad.", },
+ { &test_srd_ , " srd.", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
=20
@@ -758,9 +895,25 @@
__asm__ __volatile__ ("cmplw 2, 14, 15");
}
=20
+#ifdef __powerpc64__
+static void test_cmpd (void)
+{
+ __asm__ __volatile__ ("cmpd 2, 14, 15");
+}
+
+static void test_cmpld (void)
+{
+ __asm__ __volatile__ ("cmpld 2, 14, 15");
+}
+#endif // #ifdef __powerpc64__
+
static test_t tests_icr_ops_two[] =3D {
{ &test_cmpw , " cmpw", },
{ &test_cmplw , " cmplw", },
+#ifdef __powerpc64__
+ { &test_cmpd , " cmpd", },
+ { &test_cmpld , " cmpld", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
=20
@@ -770,9 +923,21 @@
extern void test_cmplwi (void);
ASSEMBLY_FUNC("test_cmplwi", "cmplwi 2, 14, 0");
=20
+#ifdef __powerpc64__
+extern void test_cmpdi (void);
+ASSEMBLY_FUNC("test_cmpdi", "cmpdi 2, 14, 0");
+
+extern void test_cmpldi (void);
+ASSEMBLY_FUNC("test_cmpldi", "cmpldi 2, 14, 0");
+#endif // #ifdef __powerpc64__
+
static test_t tests_icr_ops_two_i16[] =3D {
{ &test_cmpwi , " cmpwi", },
{ &test_cmplwi , " cmplwi", },
+#ifdef __powerpc64__
+ { &test_cmpdi , " cmpdi", },
+ { &test_cmpldi , " cmpldi", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
=20
@@ -1021,12 +1186,28 @@
__asm__ __volatile__ ("nego 17, 14");
}
=20
+#ifdef __powerpc64__
+static void test_cntlzd (void)
+{
+ __asm__ __volatile__ ("cntlzd 17, 14");
+}
+
+static void test_extsw (void)
+{
+ __asm__ __volatile__ ("extsw 17, 14");
+}
+#endif // #ifdef __powerpc64__
+
static test_t tests_il_ops_one[] =3D {
{ &test_cntlzw , " cntlzw", },
{ &test_extsb , " extsb", },
{ &test_extsh , " extsh", },
{ &test_neg , " neg", },
{ &test_nego , " nego", },
+#ifdef __powerpc64__
+ { &test_cntlzd , " cntlzd", },
+ { &test_extsw , " extsw", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
=20
@@ -1055,12 +1236,28 @@
__asm__ __volatile__ ("nego. 17, 14");
}
=20
+#ifdef __powerpc64__
+static void test_cntlzd_ (void)
+{
+ __asm__ __volatile__ ("cntlzd. 17, 14");
+}
+
+static void test_extsw_ (void)
+{
+ __asm__ __volatile__ ("extsw. 17, 14");
+}
+#endif // #ifdef __powerpc64__
+
static test_t tests_ilr_ops_one[] =3D {
{ &test_cntlzw_ , " cntlzw.", },
{ &test_extsb_ , " extsb.", },
{ &test_extsh_ , " extsh.", },
{ &test_neg_ , " neg.", },
{ &test_nego_ , " nego.", },
+#ifdef __powerpc64__
+ { &test_cntlzd_ , " cntlzd.", },
+ { &test_extsw_ , " extsw.", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
=20
@@ -1091,6 +1288,29 @@
__asm__ __volatile__ ("mtspr 1, 14");
}
=20
+#ifdef __powerpc64__
+extern void test_rldcl (void);
+ASSEMBLY_FUNC("test_rldcl", "rldcl 17, 14, 15, 0");
+
+extern void test_rldcr (void);
+ASSEMBLY_FUNC("test_rldcr", "rldcr 17, 14, 15, 0");
+
+extern void test_rldic (void);
+ASSEMBLY_FUNC("test_rldic", "rldic 17, 14, 0, 0");
+
+extern void test_rldicl (void);
+ASSEMBLY_FUNC("test_rldicl", "rldicl 17, 14, 0, 0");
+
+extern void test_rldicr (void);
+ASSEMBLY_FUNC("test_rldicr", "rldicr 17, 14, 0, 0");
+
+extern void test_rldimi (void);
+ASSEMBLY_FUNC("test_rldimi", "rldimi 17, 14, 0, 0");
+
+extern void test_sradi (void);
+ASSEMBLY_FUNC("test_sradi", "sradi 17, 14, 0");
+#endif // #ifdef __powerpc64__
+
static test_t tests_il_ops_spe[] =3D {
{ &test_rlwimi , " rlwimi", },
{ &test_rlwinm , " rlwinm", },
@@ -1099,6 +1319,15 @@
{ &test_mfcr , " mfcr", },
{ &test_mfspr , " mfspr", },
{ &test_mtspr , " mtspr", },
+#ifdef __powerpc64__
+ { &test_rldcl , " rldcl", },
+ { &test_rldcr , " rldcr", },
+ { &test_rldic , " rldic", },
+ { &test_rldicl , " rldicl", },
+ { &test_rldicr , " rldicr", },
+ { &test_rldimi , " rldimi", },
+ { &test_sradi , " sradi", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
=20
@@ -1123,6 +1352,29 @@
extern void test_mtcrf (void);
ASSEMBLY_FUNC("test_mtcrf", "mtcrf 0, 14");
=20
+#ifdef __powerpc64__
+extern void test_rldcl_ (void);
+ASSEMBLY_FUNC("test_rldcl_", "rldcl. 17, 14, 15, 0");
+
+extern void test_rldcr_ (void);
+ASSEMBLY_FUNC("test_rldcr_", "rldcr. 17, 14, 15, 0");
+
+extern void test_rldic_ (void);
+ASSEMBLY_FUNC("test_rldic_", "rldic. 17, 14, 0, 0");
+
+extern void test_rldicl_ (void);
+ASSEMBLY_FUNC("test_rldicl_", "rldicl. 17, 14, 0, 0");
+
+extern void test_rldicr_ (void);
+ASSEMBLY_FUNC("test_rldicr_", "rldicr. 17, 14, 0, 0");
+
+extern void test_rldimi_ (void);
+ASSEMBLY_FUNC("test_rldimi_", "rldimi. 17, 14, 0, 0");
+
+extern void test_sradi_ (void);
+ASSEMBLY_FUNC("test_sradi_", "sradi. 17, 14, 0");
+#endif // #ifdef __powerpc64__
+
static test_t tests_ilr_ops_spe[] =3D {
{ &test_rlwimi_ , " rlwimi.", },
{ &test_rlwinm_ , " rlwinm.", },
@@ -1131,6 +1383,15 @@
{ &test_mcrf , " mcrf", },
{ &test_mcrxr , " mcrxr", },
{ &test_mtcrf , " mtcrf", },
+#ifdef __powerpc64__
+ { &test_rldcl_ , " rldcl.", },
+ { &test_rldcr_ , " rldcr.", },
+ { &test_rldic_ , " rldic.", },
+ { &test_rldicl_ , " rldicl.", },
+ { &test_rldicr_ , " rldicr.", },
+ { &test_rldimi_ , " rldimi.", },
+ { &test_sradi_ , " sradi.", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
=20
@@ -1158,6 +1419,17 @@
extern void test_lwzu (void);
ASSEMBLY_FUNC("test_lwzu", "lwzu 17,0(14)");
=20
+#ifdef __powerpc64__
+extern void test_ld (void);
+ASSEMBLY_FUNC("test_ld", "ld 17,0(14)");
+
+extern void test_ldu (void);
+ASSEMBLY_FUNC("test_ldu", "ldu 17,0(14)");
+
+extern void test_lwa (void);
+ASSEMBLY_FUNC("test_lwa", "lwa 17,0(14)");
+#endif // #ifdef __powerpc64__
+
static test_t tests_ild_ops_two_i16[] =3D {
{ &test_lbz , " lbz", },
{ &test_lbzu , " lbzu", },
@@ -1167,6 +1439,11 @@
{ &test_lhzu , " lhzu", },
{ &test_lwz , " lwz", },
{ &test_lwzu , " lwzu", },
+#ifdef __powerpc64__
+ { &test_ld , " ld", },
+ { &test_ldu , " ldu", },
+ { &test_lwa , " lwa", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
=20
@@ -1210,6 +1487,28 @@
__asm__ __volatile__ ("lwzux 17,14,15");
}
=20
+#ifdef __powerpc64__
+static void test_ldx (void)
+{
+ __asm__ __volatile__ ("ldx 17,14,15");
+}
+
+static void test_ldux (void)
+{
+ __asm__ __volatile__ ("ldux 17,14,15");
+}
+
+static void test_lwax (void)
+{
+ __asm__ __volatile__ ("lwax 17,14,15");
+}
+
+static void test_lwaux (void)
+{
+ __asm__ __volatile__ ("lwaux 17,14,15");
+}
+#endif // #ifdef __powerpc64__
+
static test_t tests_ild_ops_two[] =3D {
{ &test_lbzx , " lbzx", },
{ &test_lbzux , " lbzux", },
@@ -1219,6 +1518,12 @@
{ &test_lhzux , " lhzux", },
{ &test_lwzx , " lwzx", },
{ &test_lwzux , " lwzux", },
+#ifdef __powerpc64__
+ { &test_ldx , " ldx", },
+ { &test_ldux , " ldux", },
+ { &test_lwax , " lwax", },
+ { &test_lwaux , " lwaux", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
=20
@@ -1240,6 +1545,14 @@
extern void test_stwu (void);
ASSEMBLY_FUNC("test_stwu", "stwu 14,0(15)");
=20
+#ifdef __powerpc64__
+extern void test_std (void);
+ASSEMBLY_FUNC("test_std", "std 14,0(15)");
+
+extern void test_stdu (void);
+ASSEMBLY_FUNC("test_stdu", "stdu 14,0(15)");
+#endif // #ifdef __powerpc64__
+
static test_t tests_ist_ops_three_i16[] =3D {
{ &test_stb , " stb", },
{ &test_stbu , " stbu", },
@@ -1247,6 +1560,10 @@
{ &test_sthu , " sthu", },
{ &test_stw , " stw", },
{ &test_stwu , " stwu", },
+#ifdef __powerpc64__
+ { &test_std , " std", },
+ { &test_stdu , " stdu", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
=20
@@ -1280,6 +1597,18 @@
__asm__ __volatile__ ("stwux 14,15,16");
}
=20
+#ifdef __powerpc64__
+static void test_stdx (void)
+{
+ __asm__ __volatile__ ("stdx 14,15,16");
+}
+
+static void test_stdux (void)
+{
+ __asm__ __volatile__ ("stdux 14,15,16");
+}
+#endif // #ifdef __powerpc64__
+
static test_t tests_ist_ops_three[] =3D {
{ &test_stbx , " stbx", },
{ &test_stbux , " stbux", },
@@ -1287,6 +1616,10 @@
{ &test_sthux , " sthux", },
{ &test_stwx , " stwx", },
{ &test_stwux , " stwux", },
+#ifdef __powerpc64__
+ { &test_stdx , " stdx", },
+ { &test_stdux , " stdux", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
=20
@@ -1590,6 +1923,23 @@
__asm__ __volatile__ ("fsqrt 17, 14");
}
=20
+#ifdef __powerpc64__
+static void test_fcfid (void)
+{
+ __asm__ __volatile__ ("fcfid 17, 14");
+}
+
+static void test_fctid (void)
+{
+ __asm__ __volatile__ ("fctid 17, 14");
+}
+
+static void test_fctidz (void)
+{
+ __asm__ __volatile__ ("fctidz 17, 14");
+}
+#endif // #ifdef __powerpc64__
+
static test_t tests_fa_ops_one[] =3D {
// { &test_fres , " fres", }, // TODO: Not yet=
supported
// { &test_frsqrte , " frsqrte", }, // TODO: Not yet=
supported
@@ -1601,6 +1951,11 @@
{ &test_fabs , " fabs", },
{ &test_fnabs , " fnabs", },
{ &test_fsqrt , " fsqrt", },
+#ifdef __powerpc64__
+ { &test_fcfid , " fcfid", },
+ { &test_fctid , " fctid", },
+ { &test_fctidz , " fctidz", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
#endif /* !defined (NO_FLOAT) */
@@ -1654,6 +2009,23 @@
__asm__ __volatile__ ("fnabs. 17, 14");
}
=20
+#ifdef __powerpc64__
+static void test_fcfid_ (void)
+{
+ __asm__ __volatile__ ("fcfid. 17, 14");
+}
+
+static void test_fctid_ (void)
+{
+ __asm__ __volatile__ ("fctid. 17, 14");
+}
+
+static void test_fctidz_ (void)
+{
+ __asm__ __volatile__ ("fctidz. 17, 14");
+}
+#endif // #ifdef __powerpc64__
+
static test_t tests_far_ops_one[] =3D {
// { &test_fres_ , " fres.", }, // TODO: Not yet=
supported
// { &test_frsqrte_ , " frsqrte.", }, // TODO: Not ye=
t supported
@@ -1664,6 +2036,11 @@
{ &test_fneg_ , " fneg.", },
{ &test_fabs_ , " fabs.", },
{ &test_fnabs_ , " fnabs.", },
+#ifdef __powerpc64__
+ { &test_fcfid_ , " fcfid.", },
+ { &test_fctid_ , " fctid.", },
+ { &test_fctidz_ , " fctidz.", },
+#endif // #ifdef __powerpc64__
{ NULL, NULL, },
};
#endif /* !defined (NO_FLOAT) */
@@ -3734,7 +4111,11 @@
=20
tmp =3D ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
*(uint64_t *)farg =3D tmp;
+#ifndef __powerpc64__
AB_DPRINTF("%d %03x %013llx =3D> %016llx %0e\n",
+#else
+ AB_DPRINTF("%d %03x %013lx =3D> %016lx %0e\n",
+#endif
s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
}
=20
@@ -3873,6 +4254,7 @@
uint64_t tmp;
int i=3D0;
=20
+#ifndef __powerpc64__
if (arg_list_size =3D=3D 1) { // Large
iargs =3D malloc(400 * sizeof(HWord_t));
for (tmp=3D0; ; tmp =3D tmp + 1 + (tmp >> 1)) {
@@ -3896,6 +4278,31 @@
break;
}
}
+#else
+ if (arg_list_size =3D=3D 1) { // Large
+ iargs =3D malloc(800 * sizeof(HWord_t));
+ for (tmp=3D0; ; tmp =3D 2*tmp + 1 + (tmp >> 2)) {
+ if ((long)tmp < 0 )
+ tmp =3D 0xFFFFFFFFFFFFFFFFULL;
+ iargs[i++] =3D tmp;
+ AB_DPRINTF("val %016lx\n", tmp);
+ if (tmp =3D=3D 0xFFFFFFFFFFFFFFFFULL)
+ break;
+ }
+ } else { // Default
+ iargs =3D malloc(20 * sizeof(HWord_t));
+ // for (tmp=3D0; ; tmp =3D 9999*tmp + 999999) { // gives 6
+ for (tmp =3D 0; ; tmp =3D 123456789*tmp + 123456789999) { // give=
s 3
+ if ((long)tmp < 0 )
+ tmp =3D 0xFFFFFFFFFFFFFFFFULL;
+ iargs[i++] =3D tmp;
+ AB_DPRINTF("val %016lx\n", tmp);
+ if (tmp =3D=3D 0xFFFFFFFFFFFFFFFFULL)
+ break;
+ }
+ }
+#endif // #ifndef __powerpc64__
+
AB_DPRINTF("Registered %d iargs values\n", i);
nb_iargs =3D i;
}
@@ -4146,7 +4553,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %08x, %08x, %08x =3D> %08x (%08x %08x)\n",
+#else
+ printf("%s %016lx, %016lx, %016lx =3D> %016lx (%08x %08x)\n"=
,
+#endif
name, iargs[i], iargs[j], iargs[k], res, flags, xer);
}
if (verbose) printf("\n");
@@ -4201,7 +4612,12 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %08x, %08x =3D> %08x (%08x %08x)\n",
+#else
+ if (zap_hi32) res &=3D 0xFFFFFFFFULL;
+ printf("%s %016lx, %016lx =3D> %016lx (%08x %08x)\n",
+#endif
name, iargs[i], iargs[j], res, flags, xer);
}
if (verbose) printf("\n");
@@ -4248,7 +4664,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %08x =3D> %08x (%08x %08x)\n",
+#else
+ printf("%s %016lx =3D> %016lx (%08x %08x)\n",
+#endif
name, iargs[i], res, flags, xer);
}
if ((test_flags & PPC_XER_CA) && xer_orig =3D=3D 0x00000000) {
@@ -4300,10 +4720,17 @@
void init_function( test_func_t *p_func, uint32_t func_buf[] )
{
uint32_t *p;
+#ifndef __powerpc64__
p =3D (uint32_t *)*p_func;
func_buf[0] =3D p[0];
func_buf[1] =3D p[1];
*p_func =3D (void *)func_buf;
+#else
+ p =3D (uint32_t *)((uint64_t *)*p_func)[0];
+ func_buf[0] =3D p[0];
+ func_buf[1] =3D p[1];
+ ((uint64_t *)*p_func)[0] =3D (uint64_t)&func_buf[0];
+#endif // #ifndef __powerpc64__
}
=20
=20
@@ -4347,7 +4774,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %08x, %08x =3D> %08x (%08x %08x)\n",
+#else
+ printf("%s %016lx, %08x =3D> %016lx (%08x %08x)\n",
+#endif
name, iargs[i], ii16[j], res, flags, xer);
}
if (verbose) printf("\n");
@@ -4367,6 +4798,15 @@
* mftb_cb
* mtcrf_cb
* mtspr_cb
+
+ __powerpc64__ only:
+ * rldcl rA,rS,SH,MB
+ * rldcr rA,rS,SH,ME
+ * rldic rA,rS,SH,MB
+ * rldicl rA,rS,SH,MB
+ * rldicr rA,rS,SH,ME
+ * rldimi rA,rS,SH,MB
+ * sradi rA,rS,SH
*/
=20
static void rlwi_cb (const char* name, test_func_t func,
@@ -4416,7 +4856,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %08x, %2d, %2d, %2d =3D> %08x (%08x %08x)\n",
+#else
+ printf("%s %016lx, %2d, %2d, %2d =3D> %016lx (%08x %08x)\=
n",
+#endif
name, iargs[i], j, k, l, res, flags, xer);
}
if (verbose) printf("\n");
@@ -4470,7 +4914,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %08x, %08x, %2d, %2d =3D> %08x (%08x %08x)\n",
+#else
+ printf("%s %016lx, %016lx, %2d, %2d =3D> %016lx (%08x %08=
x)\n",
+#endif
name, iargs[i], iargs[j], k, l, res, flags, xer);
}
if (verbose) printf("\n");
@@ -4520,7 +4968,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %08x, %2d =3D> %08x (%08x %08x)\n",
+#else
+ printf("%s %016lx, %2d =3D> %016lx (%08x %08x)\n",
+#endif
name, iargs[i], j, res, flags, xer);
}
if (verbose) printf("\n");
@@ -4568,7 +5020,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %d, %d (%08x) =3D> (%08x %08x)\n",
+#else
+ printf("%s %d, %d (%016lx) =3D> (%08x %08x)\n",
+#endif
name, j, k, iargs[i], flags, xer);
}
if (verbose) printf("\n");
@@ -4663,7 +5119,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s (%08x) =3D> %08x (%08x %08x)\n",
+#else
+ printf("%s (%016lx) =3D> %016lx (%08x %08x)\n",
+#endif
name, iargs[i], res, flags, xer);
}
}
@@ -4687,7 +5147,11 @@
);
res &=3D 0xE000007F; /* rest of the bits are undefined */
=20
+#ifndef __powerpc64__
printf("%s 1 (%08x) -> mtxer -> mfxer =3D> %08x\n",
+#else
+ printf("%s 1 (%08x) -> mtxer -> mfxer =3D> %016lx\n",
+#endif
name, j, res);
}
=20
@@ -4700,7 +5164,11 @@
: /*out*/"=3Dr"(res) : /*in*/"r"(j) : /*trashed*/"lr"=20
);
=20
+#ifndef __powerpc64__
printf("%s 8 (%08x) -> mtlr -> mflr =3D> %08x\n",
+#else
+ printf("%s 8 (%08x) -> mtlr -> mflr =3D> %016lx\n",
+#endif
name, j, res);
}
=20
@@ -4713,7 +5181,11 @@
: /*out*/"=3Dr"(res) : /*in*/"r"(j) : /*trashed*/"ctr"=20
);
=20
+#ifndef __powerpc64__
printf("%s 9 (%08x) -> mtctr -> mfctr =3D> %08x\n",
+#else
+ printf("%s 9 (%08x) -> mtctr -> mfctr =3D> %016lx\n",
+#endif
name, j, res);
}
=20
@@ -4963,7 +5435,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %3d, %08x =3D> (%08x %08x)\n",
+#else
+ printf("%s %3d, %016lx =3D> (%08x %08x)\n",
+#endif
name, j, iargs[i], flags, xer);
}
if (verbose) printf("\n");
@@ -5022,7 +5498,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %d, %08x =3D> (%08x %08x, %08x, %08x)\n",
+#else
+ printf("%s %d, %016lx =3D> (%08x %08x, %016lx, %016lx)\n",
+#endif
name, j, iargs[k], flags, xer, lr, ctr);
}
if (verbose) printf("\n");
@@ -5062,7 +5542,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %d, %08x =3D> (%08x %08x, %08x, %08x)\n",
+#else
+ printf("%s %d, %016lx =3D> (%08x %08x, %016lx, %016lx)\n",
+#endif
name, j, iargs[k], flags, xer, lr, ctr);
}
if (verbose) printf("\n");
@@ -5102,14 +5586,171 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %d, %08x =3D> (%08x %08x, %08x, %08x)\n",
+#else
+ printf("%s %d, %016lx =3D> (%08x %08x, %016lx, %016lx)\n",
+#endif
name, j, iargs[k], flags, xer, lr, ctr);
}
#endif
}
=20
+#ifdef __powerpc64__
+static void rldc_cb (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ uint32_t func_buf[2];
+ volatile HWord_t res;
+ volatile uint32_t flags, xer, tmpcr, tmpxer;
+ int i, j, k, arg_step;
+ =20
+ arg_step =3D (arg_list_size =3D=3D 0) ? 7 : 3;
+ =20
+ for (i=3D0; i<nb_iargs; i++) {
+ for (j=3D0; j<nb_iargs; j++) {
+ for (k=3D0; k<64; k+=3Darg_step) {
+ /* Patch up the instruction */
+ init_function( &func, func_buf );
+ patch_op_imm(&func_buf[0], (((k & 0x1F)<<1) | ((k>>5)&1)), 5=
, 6);
+ =20
+ r14 =3D iargs[i];
+ r15 =3D iargs[j];
=20
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr 18");
+ tmpcr =3D r18;
+ __asm__ __volatile__ ("mfxer 18");
+ tmpxer =3D r18;
=20
+ /* Set up flags for test */
+ r18 =3D 0;
+ __asm__ __volatile__ ("mtcr 18");
+ __asm__ __volatile__ ("mtxer 18");
+ (*func)();
+ __asm__ __volatile__ ("mfcr 18");
+ flags =3D r18;
+ __asm__ __volatile__ ("mfxer 18");
+ xer =3D r18;
+ res =3D r17;
+
+ /* Restore flags */
+ r18 =3D tmpcr;
+ __asm__ __volatile__ ("mtcr 18");
+ r18 =3D tmpxer;
+ __asm__ __volatile__ ("mtxer 18");
+
+ printf("%s %016lx, %016lx, %2d =3D> %016lx (%08x %08x)\n",
+ name, iargs[i], iargs[j], k, res, flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+ }
+}
+
+static void rldi_cb (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ uint32_t func_buf[2];
+ volatile HWord_t res;
+ volatile uint32_t flags, xer, tmpcr, tmpxer;
+ int i, j, k, arg_step;
+ =20
+ arg_step =3D (arg_list_size =3D=3D 0) ? 7 : 3;
+ =20
+ for (i=3D0; i<nb_iargs; i++) {
+ for (j=3D0; j<64; j+=3Darg_step) { // SH
+ for (k=3D0; k<64; k+=3Darg_step) { // MB|ME
+ /* Patch up the instruction */
+ init_function( &func, func_buf );
+ _patch_op_imm(&func_buf[0], (j & 0x1F), 11, 5);
+ _patch_op_imm(&func_buf[0], ((j>>5)&1), 1, 1);
+ patch_op_imm(&func_buf[0], (((k & 0x1F)<<1) | ((k>>5)&1)), 5=
, 6);
+ =20
+ r14 =3D iargs[i];
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr 18");
+ tmpcr =3D r18;
+ __asm__ __volatile__ ("mfxer 18");
+ tmpxer =3D r18;
+
+ /* Set up flags for test */
+ r18 =3D 0;
+ __asm__ __volatile__ ("mtcr 18");
+ __asm__ __volatile__ ("mtxer 18");
+ (*func)();
+ __asm__ __volatile__ ("mfcr 18");
+ flags =3D r18;
+ __asm__ __volatile__ ("mfxer 18");
+ xer =3D r18;
+ res =3D r17;
+
+ /* Restore flags */
+ r18 =3D tmpcr;
+ __asm__ __volatile__ ("mtcr 18");
+ r18 =3D tmpxer;
+ __asm__ __volatile__ ("mtxer 18");
+
+ printf("%s %016lx, %2d, %2d =3D> %016lx (%08x %08x)\n",
+ name, iargs[i], j, k, res, flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+ }
+}
+
+static void sradi_cb (const char* name, test_func_t func,
+ unused uint32_t test_flags)
+{
+ uint32_t func_buf[2];
+ volatile HWord_t res;
+ volatile uint32_t flags, xer, tmpcr, tmpxer;
+ int i, j, arg_step;
+ =20
+ arg_step =3D (arg_list_size =3D=3D 0) ? 7 : 3;
+ =20
+ for (i=3D0; i<nb_iargs; i++) {
+ for (j=3D0; j<64; j+=3Darg_step) { // SH
+ /* Patch up the instruction */
+ init_function( &func, func_buf );
+ _patch_op_imm(&func_buf[0], (j & 0x1F), 11, 5);
+ patch_op_imm(&func_buf[0], ((j>>5)&1), 1, 1);
+ =20
+ r14 =3D iargs[i];
+
+ /* Save flags */
+ __asm__ __volatile__ ("mfcr 18");
+ tmpcr =3D r18;
+ __asm__ __volatile__ ("mfxer 18");
+ tmpxer =3D r18;
+
+ /* Set up flags for test */
+ r18 =3D 0;
+ __asm__ __volatile__ ("mtcr 18");
+ __asm__ __volatile__ ("mtxer 18");
+ (*func)();
+ __asm__ __volatile__ ("mfcr 18");
+ flags =3D r18;
+ __asm__ __volatile__ ("mfxer 18");
+ xer =3D r18;
+ res =3D r17;
+
+ /* Restore flags */
+ r18 =3D tmpcr;
+ __asm__ __volatile__ ("mtcr 18");
+ r18 =3D tmpxer;
+ __asm__ __volatile__ ("mtxer 18");
+
+ printf("%s %016lx, %2d =3D> %016lx (%08x %08x)\n",
+ name, iargs[i], j, res, flags, xer);
+ }
+ if (verbose) printf("\n");
+ }
+}
+#endif // #ifdef __powerpc64__
+
+
typedef struct special_t special_t;
=20
struct special_t {
@@ -5209,7 +5850,65 @@
"mtspr", /* One register + 1 10 bits immediate arguments */
&mtspr_cb,
},
+#ifdef __powerpc64__
{
+ "rldcl", /* Two registers + 1 6 bit immediate argument */
+ &rldc_cb,
+ },
+ {
+ "rldcl.", /* Two registers + 1 6 bit immediate argument */
+ &rldc_cb,
+ },
+ {
+ "rldcr", /* Two registers + 1 6 bit immediate argument */
+ &rldc_cb,
+ },
+ {
+ "rldcr.", /* Two registers + 1 6 bit immediate argument */
+ &rldc_cb,
+ },
+ {
+ "rldic", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "rldic.", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "rldicl", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "rldicl.", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "rldicr", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "rldicr.", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "rldimi", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "rldimi.", /* One register + 2 6 bit immediate arguments */
+ &rldi_cb,
+ },
+ {
+ "sradi", /* One register + 1 6 bit immediate argument */
+ &sradi_cb,
+ },
+ {
+ "sradi.", /* One register + 1 6 bit immediate argument */
+ &sradi_cb,
+ },
+#endif // #ifdef __powerpc64__
+ {
NULL,
NULL,
},
@@ -5229,8 +5928,12 @@
uint32_t func_buf[2];
volatile HWord_t res, base;
volatile uint32_t flags, xer, tmpcr, tmpxer;
- int i, offs;
+ int i, offs, is_lwa=3D0;
=20
+#ifdef __powerpc64__
+ is_lwa =3D strstr(name, "lwa") !=3D NULL;
+#endif
+
// +ve d
base =3D (HWord_t)&iargs[0];
for (i=3D0; i<nb_iargs; i++) {
@@ -5238,7 +5941,10 @@
=20
/* Patch up the instruction */
init_function( &func, func_buf );
- patch_op_imm16(&func_buf[0], offs);
+ if (is_lwa)
+ patch_op_imm(&func_buf[0], offs>>2, 2, 14);
+ else
+ patch_op_imm16(&func_buf[0], offs);
=20
r14 =3D base;
=20
@@ -5265,7 +5971,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %2d, (%08x) =3D> %08x, %2d (%08x %08x)\n",
+#else
+ printf("%s %3d, (%016lx) =3D> %016lx, %3ld (%08x %08x)\n",
+#endif
name, offs, iargs[i], res, r14-base, flags, xer);
}
if (verbose) printf("\n");
@@ -5304,7 +6014,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %2d, (%08x) =3D> %08x, %2d (%08x %08x)\n",
+#else
+ printf("%s %3d, (%016lx) =3D> %016lx, %3ld (%08x %08x)\n",
+#endif
name, offs, iargs[nb_iargs-1+i], res, r14-base, flags, xer)=
;
}
}
@@ -5347,7 +6061,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %d (%08x) =3D> %08x, %d (%08x %08x)\n",
+#else
+ printf("%s %3d, (%016lx) =3D> %016lx, %2ld (%08x %08x)\n",
+#endif
name, offs, iargs[i], res, r14-base, flags, xer);
}
}
@@ -5401,7 +6119,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %08x, %2d =3D> %08x, %2d (%08x %08x)\n",
+#else
+ printf("%s %016lx, %3d =3D> %016lx, %3ld (%08x %08x)\n",
+#endif
name, iargs[i], offs, iargs_priv[i], r15-base, flags, xer);
}
if (verbose) printf("\n");
@@ -5443,7 +6165,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %08x, %2d =3D> %08x, %2d (%08x %08x)\n",
+#else
+ printf("%s %016lx, %3d =3D> %016lx, %3ld (%08x %08x)\n",
+#endif
name, iargs[nb_iargs-1+i], offs, iargs_priv[nb_iargs-1+i],
r15-base, flags, xer);
}
@@ -5493,7 +6219,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %08x, %d =3D> %08x, %d (%08x %08x)\n",
+#else
+ printf("%s %016lx, %3d =3D> %016lx, %2ld (%08x %08x)\n",
+#endif
name, iargs[i], offs, iargs_priv[i], r15-base, flags, xer);
}
free(iargs_priv);
@@ -5568,7 +6298,11 @@
as vex's accuracy isn't perfect */
ur &=3D 0xFFFFFFFFFFFFFF00ULL;
=20
+#ifndef __powerpc64__
printf("%s %016llx, %016llx, %016llx =3D> %016llx",
+#else
+ printf("%s %016lx, %016lx, %016lx =3D> %016lx",
+#endif
name, u0, u1, u2, ur);
#if defined TEST_FLOAT_FLAGS
printf(" (%08x)", flags);
@@ -5619,7 +6353,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %016llx, %016llx =3D> %016llx",
+#else
+ printf("%s %016lx, %016lx =3D> %016lx",
+#endif
name, u0, u1, ur);
#if defined TEST_FLOAT_FLAGS
printf(" (%08x)", flags);
@@ -5673,7 +6411,11 @@
if (zap_hi_32bits)
ur &=3D 0xFFFFFFFFULL;
=20
+#ifndef __powerpc64__
printf("%s %016llx =3D> %016llx",
+#else
+ printf("%s %016lx =3D> %016lx",
+#endif
name, u0, ur);
#if defined TEST_FLOAT_FLAGS
printf(" (%08x)", flags);
@@ -5793,7 +6535,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %016llx, %4d =3D> %016llx, %4d",
+#else
+ printf("%s %016lx, %4d =3D> %016lx, %4ld",
+#endif
name, double_to_bits(src), offs,
double_to_bits(res), r14-base);
#if defined TEST_FLOAT_FLAGS
@@ -5850,7 +6596,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %016llx, %4d =3D> %016llx, %4d",
+#else
+ printf("%s %016lx, %4ld =3D> %016lx, %4ld",
+#endif
name, double_to_bits(src), r15/*offs*/,
double_to_bits(res), r14-base);
#if defined TEST_FLOAT_FLAGS
@@ -5931,7 +6681,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %016llx, %4d =3D> %016llx, %4d",
+#else
+ printf("%s %016lx, %4d =3D> %016lx, %4ld",
+#endif
name, double_to_bits(src), offs,
double_to_bits(*p_dst), r15-base);
#if defined TEST_FLOAT_FLAGS
@@ -6008,7 +6762,11 @@
r18 =3D tmpxer;
__asm__ __volatile__ ("mtxer 18");
=20
+#ifndef __powerpc64__
printf("%s %016llx, %4d =3D> %016llx, %4d",
+#else
+ printf("%s %016lx, %4ld =3D> %016lx, %4ld",
+#endif
name, double_to_bits(src), r16/*offs*/,
double_to_bits(*p_dst), r15-base);
#if defined TEST_FLOAT_FLAGS
@@ -6019,12 +6777,20 @@
=20
#if 0
// print double precision result
+#ifndef __powerpc64__
printf("%s %016llx (%014e), %4d =3D> %016llx (%014e), %08x (%08x %=
08x)\n",
+#else
+ printf("%s %016lx (%014e), %4d =3D> %016lx (%014e), %08x (%08x %08=
x)\n",
+#endif
name, double_to_bits(src), src, offs,
double_to_bits(*p_dst), *p_dst, r15, flags, xer);
=20
// print single precision result
+#ifndef __powerpc64__
printf("%s %016llx (%014e), %4d =3D> %08x (%f), %08x (%08x %08x)\n=
",
+#else
+ printf("%s %016lx (%014e), %4d =3D> %08x (%f), %08x (%08x %08x)\n"=
,
+#endif
name, double_to_bits(src), src, offs,
(uint32_t)(double_to_bits(*p_dst) >> 32),
bits_to_float( (uint32_t)(double_to_bits(*p_dst) >> 32) ),
|
|
From: <sv...@va...> - 2006-01-03 11:47:49
|
Author: cerion Date: 2006-01-03 11:47:38 +0000 (Tue, 03 Jan 2006) New Revision: 5486 Log: regtest none::ppc32 - More cleanup - Fixed rlwimi test - init r_dst to zero. - Fixed load/store tests - print change in updated base reg, not actual = value. Modified: trunk/none/tests/ppc32/jm-fp.stdout.exp trunk/none/tests/ppc32/jm-insns.c trunk/none/tests/ppc32/jm-int.stdout.exp [... diff too large to include ...] |
|
From: <sv...@va...> - 2006-01-03 04:10:22
|
Author: sewardj
Date: 2006-01-03 04:10:13 +0000 (Tue, 03 Jan 2006)
New Revision: 5485
Log:
Signal-related syscall support.
Modified:
trunk/coregrind/m_syswrap/syswrap-ppc64-linux.c
Modified: trunk/coregrind/m_syswrap/syswrap-ppc64-linux.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syswrap-ppc64-linux.c 2006-01-03 04:09:27 U=
TC (rev 5484)
+++ trunk/coregrind/m_syswrap/syswrap-ppc64-linux.c 2006-01-03 04:10:13 U=
TC (rev 5485)
@@ -422,7 +422,7 @@
//zz DECL_TEMPLATE(ppc64_linux, sys_ipc);
DECL_TEMPLATE(ppc64_linux, sys_clone);
//zz DECL_TEMPLATE(ppc64_linux, sys_sigreturn);
-//zz DECL_TEMPLATE(ppc64_linux, sys_rt_sigreturn);
+DECL_TEMPLATE(ppc64_linux, sys_rt_sigreturn);
//zz DECL_TEMPLATE(ppc64_linux, sys_sigaction);
=20
PRE(sys_socketcall)
@@ -1051,42 +1051,42 @@
//zz /* Check to see if some any signals arose as a result of this. *=
/
//zz *flags |=3D SfPollAfter;
//zz }
-//zz=20
-//zz PRE(sys_rt_sigreturn)
-//zz {
-//zz ThreadState* tst;
-//zz PRINT("rt_sigreturn ( )");
-//zz=20
-//zz vg_assert(VG_(is_valid_tid)(tid));
-//zz vg_assert(tid >=3D 1 && tid < VG_N_THREADS);
-//zz vg_assert(VG_(is_running_thread)(tid));
-//zz=20
-//zz ///* Adjust esp to point to start of frame; skip back up over ha=
ndler
-//zz // ret addr */
-//zz tst =3D VG_(get_ThreadState)(tid);
-//zz //tst->arch.vex.guest_ESP -=3D sizeof(Addr);
-//zz // Should we do something equivalent on ppc64? Who knows.
-//zz=20
-//zz ///* This is only so that the EIP is (might be) useful to report=
if
-//zz // something goes wrong in the sigreturn */
-//zz //ML_(fixup_guest_state_to_restart_syscall)(&tst->arch);
-//zz // Should we do something equivalent on ppc64? Who knows.
-//zz=20
-//zz VG_(sigframe_destroy)(tid, True);
-//zz=20
-//zz /* See comments above in PRE(sys_sigreturn) about this. */
-//zz SET_STATUS_from_SysRes_NO_SANITY_CHECK(
-//zz VG_(mk_SysRes_ppc64_linux)(=20
-//zz tst->arch.vex.guest_GPR3,
-//zz /* get CR0.SO */
-//zz (LibVEX_GuestPPC32_get_CR( &tst->arch.vex ) >> 28) & 1
-//zz )
-//zz );
-//zz=20
-//zz /* Check to see if some any signals arose as a result of this. *=
/
-//zz *flags |=3D SfPollAfter;
-//zz }
-//zz=20
+
+PRE(sys_rt_sigreturn)
+{
+ ThreadState* tst;
+ PRINT("rt_sigreturn ( )");
+
+ vg_assert(VG_(is_valid_tid)(tid));
+ vg_assert(tid >=3D 1 && tid < VG_N_THREADS);
+ vg_assert(VG_(is_running_thread)(tid));
+
+ ///* Adjust esp to point to start of frame; skip back up over handler
+ // ret addr */
+ tst =3D VG_(get_ThreadState)(tid);
+ //tst->arch.vex.guest_ESP -=3D sizeof(Addr);
+ // Should we do something equivalent on ppc64? Who knows.
+
+ ///* This is only so that the EIP is (might be) useful to report if
+ // something goes wrong in the sigreturn */
+ //ML_(fixup_guest_state_to_restart_syscall)(&tst->arch);
+ // Should we do something equivalent on ppc64? Who knows.
+
+ VG_(sigframe_destroy)(tid, True);
+
+ /* See comments above in PRE(sys_sigreturn) about this. */
+ SET_STATUS_from_SysRes_NO_SANITY_CHECK(
+ VG_(mk_SysRes_ppc64_linux)(=20
+ tst->arch.vex.guest_GPR3,
+ /* get CR0.SO */
+ (LibVEX_GuestPPC64_get_CR( &tst->arch.vex ) >> 28) & 1
+ )
+ );
+
+ /* Check to see if some any signals arose as a result of this. */
+ *flags |=3D SfPollAfter;
+}
+
//zz /* Convert from non-RT to RT sigset_t's */
//zz static=20
//zz void convert_sigset_to_rt(const vki_old_sigset_t *oldset, vki_sigse=
t_t *set)
@@ -1188,7 +1188,7 @@
=20
GENX_(__NR_unlink, sys_unlink), // 10
GENX_(__NR_execve, sys_execve), // 11
-// _____(__NR_chdir, sys_chdir), // 12
+ GENX_(__NR_chdir, sys_chdir), // 12
// _____(__NR_time, sys_time), // 13
// _____(__NR_mknod, sys_mknod), // 14
=20
@@ -1380,7 +1380,7 @@
=20
// _____(__NR_getresgid, sys_getresgid), // 170
// _____(__NR_prctl, sys_prctl), // 171
-// _____(__NR_rt_sigreturn, sys_rt_sigreturn), // 172
+ PLAX_(__NR_rt_sigreturn, sys_rt_sigreturn), // 172
LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 173
LINXY(__NR_rt_sigprocmask, sys_rt_sigprocmask), // 174
=20
@@ -1400,7 +1400,7 @@
// _____(__NR_sendfile, sys_sendfile), // 186
// _____(__NR_getpmsg, sys_getpmsg), // 187
// _____(__NR_putpmsg, sys_putpmsg), // 188
-// _____(__NR_vfork, sys_vfork), // 189
+ GENX_(__NR_vfork, sys_fork), // 189 treat a=
s fork
=20
GENXY(__NR_ugetrlimit, sys_getrlimit), // 190
// _____(__NR_readahead, sys_readahead), // 191
|
|
From: <sv...@va...> - 2006-01-03 04:09:36
|
Author: sewardj
Date: 2006-01-03 04:09:27 +0000 (Tue, 03 Jan 2006)
New Revision: 5484
Log:
casting paranoia (harmless)
Modified:
trunk/coregrind/m_syswrap/syswrap-generic.c
Modified: trunk/coregrind/m_syswrap/syswrap-generic.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syswrap-generic.c 2006-01-03 04:08:32 UTC (=
rev 5483)
+++ trunk/coregrind/m_syswrap/syswrap-generic.c 2006-01-03 04:09:27 UTC (=
rev 5484)
@@ -80,7 +80,7 @@
if (!ret && syscallname !=3D NULL) {
VG_(message)(Vg_UserMsg, "Warning: client syscall %s tried "
"to modify addresses %p-%p",
- syscallname, start, start+size-1);
+ syscallname, (void*)start, (void*)(start+=
size-1));
if (VG_(clo_verbosity) > 1) {
VG_(get_and_pp_StackTrace)(tid, VG_(clo_backtrace_size));
}
|
|
From: <sv...@va...> - 2006-01-03 04:08:37
|
Author: sewardj
Date: 2006-01-03 04:08:32 +0000 (Tue, 03 Jan 2006)
New Revision: 5483
Log:
First cut at signal frame build/removal for ppc64-linux. Ghastly
stuff, but it does at least appear to do simple signal stuff
correctly.
Modified:
trunk/coregrind/m_sigframe/sigframe-ppc64-linux.c
Modified: trunk/coregrind/m_sigframe/sigframe-ppc64-linux.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_sigframe/sigframe-ppc64-linux.c 2006-01-02 20:47:26=
UTC (rev 5482)
+++ trunk/coregrind/m_sigframe/sigframe-ppc64-linux.c 2006-01-03 04:08:32=
UTC (rev 5483)
@@ -78,148 +78,95 @@
// A structure in which to save the application's registers
// during the execution of signal handlers.
=20
-// Linux has 2 signal frame structures: one for normal signal
-// deliveries, and one for SA_SIGINFO deliveries (also known as RT
-// signals).
-//
+// On ppc64-linux, rt_sigframe is used for all signals.
+
// In theory, so long as we get the arguments to the handler function
// right, it doesn't matter what the exact layout of the rest of the
// frame is. Unfortunately, things like gcc's exception unwinding
// make assumptions about the locations of various parts of the frame,
// so we need to duplicate it exactly.
=20
+/* Many of these byzantine details derived from
+ linux-2.6.13/arch/ppc64/kernel/signal.c */
+
+#define TRAMP_SIZE 6 /* who knows why - it only needs to be 2. */
+
/* Structure containing bits of information that we want to save
on signal delivery. */
-//zz struct vg_sig_private {
-//zz UInt magicPI;
-//zz UInt sigNo_private;
-//zz VexGuestPPC32State shadow;
-//zz };
-//zz=20
-//zz /* Structure put on stack for signal handlers with SA_SIGINFO clear=
. */
-//zz struct nonrt_sigframe {
-//zz UInt gap1[16];
-//zz struct vki_sigcontext sigcontext;
-//zz struct vki_mcontext mcontext;
-//zz struct vg_sig_private priv;
-//zz unsigned char abigap[224];
-//zz };
-//zz=20
-//zz /* Structure put on stack for signal handlers with SA_SIGINFO set. =
*/
-//zz struct rt_sigframe {
-//zz UInt gap1[20];
-//zz vki_siginfo_t siginfo;
-//zz struct vki_ucontext ucontext;
-//zz struct vg_sig_private priv;
-//zz unsigned char abigap[224];
-//zz };
+struct vg_sig_private {
+ UInt magicPI;
+ UInt sigNo_private;
+ VexGuestPPC64State shadow;
+};
=20
+/* Structure put on stack for all signal handlers. */
+struct rt_sigframe {
+ struct vki_ucontext uc;
+ ULong _unused[2];
+ UInt tramp[TRAMP_SIZE];
+ struct vki_siginfo* pinfo;
+ void* puc;
+ vki_siginfo_t info;
+ struct vg_sig_private priv;
+ UChar abigap[288];
+};
+
#define SET_SIGNAL_LR(zztst, zzval) \
do { tst->arch.vex.guest_LR =3D (zzval); \
VG_TRACK( post_reg_write, Vg_CoreSignal, tst->tid, \
- offsetof(VexGuestPPC32State,guest_LR), \
+ offsetof(VexGuestPPC64State,guest_LR), \
sizeof(UWord) ); \
} while (0)
=20
#define SET_SIGNAL_GPR(zztst, zzn, zzval) \
do { tst->arch.vex.guest_GPR##zzn =3D (zzval); \
VG_TRACK( post_reg_write, Vg_CoreSignal, tst->tid, \
- offsetof(VexGuestPPC32State,guest_GPR##zzn), \
+ offsetof(VexGuestPPC64State,guest_GPR##zzn), \
sizeof(UWord) ); \
} while (0)
=20
=20
-static=20
-void stack_mcontext ( struct vki_mcontext *mc,=20
- ThreadState* tst,=20
- Int ret,
- UInt fault_addr )
-{
-// VG_TRACK( pre_mem_write, Vg_CoreSignal, tst->tid, "signal frame mco=
ntext",
-// (Addr)mc, sizeof(struct vki_pt_regs) );
-//
-//# define DO(gpr) mc->mc_gregs[VKI_PT_R0+gpr] =3D tst->arch.vex.guest=
_GPR##gpr
-// DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
-// DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
-// DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23);
-// DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
-//# undef DO
-//
-// mc->mc_gregs[VKI_PT_NIP] =3D tst->arch.vex.guest_CIA;
-// mc->mc_gregs[VKI_PT_MSR] =3D 0xf032; /* pretty arbitrary */
-// mc->mc_gregs[VKI_PT_ORIG_R3] =3D tst->arch.vex.guest_GPR3;
-// mc->mc_gregs[VKI_PT_CTR] =3D tst->arch.vex.guest_CTR;
-// mc->mc_gregs[VKI_PT_LNK] =3D tst->arch.vex.guest_LR;
-// mc->mc_gregs[VKI_PT_XER] =3D LibVEX_GuestPPC32_get_XER(&tst->ar=
ch.vex);
-// mc->mc_gregs[VKI_PT_CCR] =3D LibVEX_GuestPPC32_get_CR(&tst->arc=
h.vex);
-// mc->mc_gregs[VKI_PT_MQ] =3D 0;
-// mc->mc_gregs[VKI_PT_TRAP] =3D 0;
-// mc->mc_gregs[VKI_PT_DAR] =3D fault_addr;
-// mc->mc_gregs[VKI_PT_DSISR] =3D 0;
-// mc->mc_gregs[VKI_PT_RESULT] =3D 0;
-// VG_TRACK( post_mem_write, Vg_CoreSignal, tst->tid,=20
-// (Addr)mc, sizeof(struct vki_pt_regs) );
-//
-// /* XXX should do FP and vector regs */
-//
-// /* set up signal return trampoline */
-// VG_TRACK(pre_mem_write, Vg_CoreSignal, tst->tid, "signal frame mcon=
text",
-// (Addr)&mc->mc_pad, sizeof(mc->mc_pad));
-// mc->mc_pad[0] =3D 0x38000000U + ret; /* li 0,ret */
-// mc->mc_pad[1] =3D 0x44000002U; /* sc */
-// VG_TRACK( post_mem_write, Vg_CoreSignal, tst->tid,=20
-// (Addr)&mc->mc_pad, sizeof(mc->mc_pad) );
-// /* invalidate any translation of this area */
-// VG_(discard_translations)( (Addr64)(Addr)&mc->mc_pad,=20
-// sizeof(mc->mc_pad), "stack_mcontext" ); =
=20
-//
-// /* set the signal handler to return to the trampoline */
-// SET_SIGNAL_LR(tst, (Addr) &mc->mc_pad[0]);
-}
-
-
/* Extend the stack segment downwards if needed so as to ensure the
new signal frames are mapped to something. Return a Bool
indicating whether or not the operation was successful.
*/
static Bool extend ( ThreadState *tst, Addr addr, SizeT size )
{
- I_die_here;
-// ThreadId tid =3D tst->tid;
-// NSegment *stackseg =3D NULL;
-//
-// if (VG_(extend_stack)(addr, tst->client_stack_szB)) {
-// stackseg =3D VG_(am_find_nsegment)(addr);
-// if (0 && stackseg)
-// VG_(printf)("frame=3D%p seg=3D%p-%p\n",
-// addr, stackseg->start, stackseg->end);
-// }
-//
-// if (stackseg =3D=3D NULL || !stackseg->hasR || !stackseg->hasW) {
-// VG_(message)(
-// Vg_UserMsg,
-// "Can't extend stack to %p during signal delivery for thread %=
d:",
-// addr, tid);
-// if (stackseg =3D=3D NULL)
-// VG_(message)(Vg_UserMsg, " no stack segment");
-// else
-// VG_(message)(Vg_UserMsg, " too small or bad protection modes=
");
-//
-// /* set SIGSEGV to default handler */
-// VG_(set_default_handler)(VKI_SIGSEGV);
-// VG_(synth_fault_mapping)(tid, addr);
-//
-// /* The whole process should be about to die, since the default
-// action of SIGSEGV to kill the whole process. */
-// return False;
-// }
-//
-// /* For tracking memory events, indicate the entire frame has been
-// allocated. */
-// VG_TRACK( new_mem_stack_signal, addr - VG_STACK_REDZONE_SZB,
-// size + VG_STACK_REDZONE_SZB );
-//
-// return True;
+ ThreadId tid =3D tst->tid;
+ NSegment *stackseg =3D NULL;
+
+ if (VG_(extend_stack)(addr, tst->client_stack_szB)) {
+ stackseg =3D VG_(am_find_nsegment)(addr);
+ if (0 && stackseg)
+ VG_(printf)("frame=3D%p seg=3D%p-%p\n",
+ addr, stackseg->start, stackseg->end);
+ }
+
+ if (stackseg =3D=3D NULL || !stackseg->hasR || !stackseg->hasW) {
+ VG_(message)(
+ Vg_UserMsg,
+ "Can't extend stack to %p during signal delivery for thread %d:=
",
+ addr, tid);
+ if (stackseg =3D=3D NULL)
+ VG_(message)(Vg_UserMsg, " no stack segment");
+ else
+ VG_(message)(Vg_UserMsg, " too small or bad protection modes")=
;
+
+ /* set SIGSEGV to default handler */
+ VG_(set_default_handler)(VKI_SIGSEGV);
+ VG_(synth_fault_mapping)(tid, addr);
+
+ /* The whole process should be about to die, since the default
+ action of SIGSEGV to kill the whole process. */
+ return False;
+ }
+
+ /* For tracking memory events, indicate the entire frame has been
+ allocated. */
+ VG_TRACK( new_mem_stack_signal, addr - VG_STACK_REDZONE_SZB,
+ size + VG_STACK_REDZONE_SZB );
+
+ return True;
}
=20
=20
@@ -232,107 +179,123 @@
const vki_sigset_t *mask,
void *restorer )
{
- I_die_here;
-// struct vg_sig_private *priv;
-// Addr sp;
-// ThreadState *tst;
-// Int sigNo =3D siginfo->si_signo;
-// Addr faultaddr;
-//
-// /* Stack must be 16-byte aligned */
-// sp_top_of_frame &=3D ~0xf;
-//
-// if (flags & VKI_SA_SIGINFO) {
-// sp =3D sp_top_of_frame - sizeof(struct rt_sigframe);
-// } else {
-// sp =3D sp_top_of_frame - sizeof(struct nonrt_sigframe);
-// }
-//
-// tst =3D VG_(get_ThreadState)(tid);
-//
-// if (!extend(tst, sp, sp_top_of_frame - sp))
-// return;
-//
-// vg_assert(VG_IS_16_ALIGNED(sp));
-//
-// /* Set up the stack chain pointer */
-// VG_TRACK( pre_mem_write, Vg_CoreSignal, tid, "signal handler frame"=
,
-// sp, sizeof(UWord) );
-// *(Addr *)sp =3D tst->arch.vex.guest_GPR1;
-// VG_TRACK( post_mem_write, Vg_CoreSignal, tid,=20
-// sp, sizeof(UWord) );
-//
-// faultaddr =3D (Addr)siginfo->_sifields._sigfault._addr;
-// if (sigNo =3D=3D VKI_SIGILL && siginfo->si_code > 0)
-// faultaddr =3D tst->arch.vex.guest_CIA;
-//
-// if (flags & VKI_SA_SIGINFO) {
-// struct rt_sigframe *frame =3D (struct rt_sigframe *) sp;
-// struct vki_ucontext *ucp =3D &frame->ucontext;
-//
-// VG_TRACK( pre_mem_write, Vg_CoreSignal, tid, "signal frame sigin=
fo",
-// (Addr)&frame->siginfo, sizeof(frame->siginfo) );
-// VG_(memcpy)(&frame->siginfo, siginfo, sizeof(*siginfo));
-// VG_TRACK( post_mem_write, Vg_CoreSignal, tid,=20
-// (Addr)&frame->siginfo, sizeof(frame->siginfo) );
-//
-// VG_TRACK( pre_mem_write, Vg_CoreSignal, tid, "signal frame ucont=
ext",
-// (Addr)ucp, offsetof(struct vki_ucontext, uc_pad) );
-// ucp->uc_flags =3D 0;
-// ucp->uc_link =3D 0;
-// ucp->uc_stack =3D tst->altstack;
-// VG_TRACK( post_mem_write, Vg_CoreSignal, tid, (Addr)ucp,
-// offsetof(struct vki_ucontext, uc_pad) );
-//
-// VG_TRACK( pre_mem_write, Vg_CoreSignal, tid, "signal frame ucont=
ext",
-// (Addr)&ucp->uc_regs,
-// sizeof(ucp->uc_regs) + sizeof(ucp->uc_sigmask) );
-// ucp->uc_regs =3D &ucp->uc_mcontext;
-// ucp->uc_sigmask =3D tst->sig_mask;
-// VG_TRACK( post_mem_write, Vg_CoreSignal, tid,=20
-// (Addr)&ucp->uc_regs,
-// sizeof(ucp->uc_regs) + sizeof(ucp->uc_sigmask) );
-//
-// stack_mcontext(&ucp->uc_mcontext, tst, __NR_rt_sigreturn, faulta=
ddr);
-// priv =3D &frame->priv;
-//
-// SET_SIGNAL_GPR(tid, 4, (Addr) &frame->siginfo);
-// SET_SIGNAL_GPR(tid, 5, (Addr) ucp);
-// /* the kernel sets this, though it doesn't seem to be in the ABI=
*/
-// SET_SIGNAL_GPR(tid, 6, (Addr) &frame->siginfo);
-//
-// } else {
-// /* non-RT signal delivery */
-// struct nonrt_sigframe *frame =3D (struct nonrt_sigframe *) sp;
-// struct vki_sigcontext *scp =3D &frame->sigcontext;
-//
-// VG_TRACK( pre_mem_write, Vg_CoreSignal, tid, "signal frame sigco=
ntext",
-// (Addr)&scp->_unused[3], sizeof(*scp) - 3 * sizeof(UInt=
) );
-// scp->signal =3D sigNo;
-// scp->handler =3D (Addr) handler;
-// scp->oldmask =3D tst->sig_mask.sig[0];
-// scp->_unused[3] =3D tst->sig_mask.sig[1];
-// VG_TRACK( post_mem_write, Vg_CoreSignal, tid,
-// (Addr)&scp->_unused[3], sizeof(*scp) - 3 * sizeof(UInt=
) );
-//
-// stack_mcontext(&frame->mcontext, tst, __NR_sigreturn, faultaddr)=
;
-// priv =3D &frame->priv;
-//
-// SET_SIGNAL_GPR(tid, 4, (Addr) scp);
-// }
-//
-// priv->magicPI =3D 0x31415927;
-// priv->sigNo_private =3D sigNo;
-// priv->shadow =3D tst->arch.vex_shadow;
-//
-// SET_SIGNAL_GPR(tid, 1, sp);
-// SET_SIGNAL_GPR(tid, 3, sigNo);
-// tst->arch.vex.guest_CIA =3D (Addr) handler;
-//
-// if (0)
-// VG_(printf)("pushed signal frame; %R1 now =3D %p, "
-// "next %%CIA =3D %p, status=3D%d\n",=20
-// sp, tst->arch.vex.guest_CIA, tst->status);
+ struct vg_sig_private* priv;
+ Addr sp;
+ ThreadState* tst;
+ Int sigNo =3D siginfo->si_signo;
+ Addr faultaddr;
+ struct rt_sigframe* frame;
+
+ /* Stack must be 16-byte aligned */
+ vg_assert(VG_IS_16_ALIGNED(sizeof(struct rt_sigframe)));
+
+ sp_top_of_frame &=3D ~0xf;
+ sp =3D sp_top_of_frame - sizeof(struct rt_sigframe);
+
+ tst =3D VG_(get_ThreadState)(tid);
+ if (!extend(tst, sp, sp_top_of_frame - sp))
+ return;
+
+ vg_assert(VG_IS_16_ALIGNED(sp));
+
+ frame =3D (struct rt_sigframe *) sp;
+
+ /* clear it (conservatively) */
+ VG_(memset)(frame, 0, sizeof(*frame));
+
+ /////////
+ frame->pinfo =3D &frame->info;
+ frame->puc =3D &frame->uc;
+
+ frame->uc.uc_flags =3D 0;
+ frame->uc.uc_link =3D 0;
+ /////////
+
+ /* Set up the stack chain pointer */
+ VG_TRACK( pre_mem_write, Vg_CoreSignal, tid, "signal handler frame",
+ sp, sizeof(UWord) );
+ *(Addr *)sp =3D tst->arch.vex.guest_GPR1;
+ VG_TRACK( post_mem_write, Vg_CoreSignal, tid,=20
+ sp, sizeof(UWord) );
+
+ faultaddr =3D (Addr)siginfo->_sifields._sigfault._addr;
+ if (sigNo =3D=3D VKI_SIGILL && siginfo->si_code > 0)
+ faultaddr =3D tst->arch.vex.guest_CIA;
+
+ VG_(memcpy)(&frame->info, siginfo, sizeof(*siginfo));
+ VG_TRACK( post_mem_write, Vg_CoreSignal, tid,
+ (Addr)&frame->info, sizeof(frame->info) );
+
+ frame->uc.uc_flags =3D 0;
+ frame->uc.uc_link =3D 0;
+ frame->uc.uc_stack =3D tst->altstack;
+ frame->uc.uc_sigmask =3D tst->sig_mask;
+ VG_TRACK( post_mem_write, Vg_CoreSignal, tid,
+ (Addr)(&frame->uc), sizeof(frame->uc) );
+
+# define DO(gpr) frame->uc.uc_mcontext.gp_regs[VKI_PT_R0+gpr] \
+ =3D tst->arch.vex.guest_GPR##gpr=20
+ DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
+ DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
+ DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23);
+ DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
+# undef DO
+
+ frame->uc.uc_mcontext.gp_regs[VKI_PT_NIP] =3D tst->arch.vex.guest=
_CIA;
+ frame->uc.uc_mcontext.gp_regs[VKI_PT_MSR] =3D 0xf032; /* pretty=
arbitrary */
+ frame->uc.uc_mcontext.gp_regs[VKI_PT_ORIG_R3] =3D tst->arch.vex.guest=
_GPR3;
+ frame->uc.uc_mcontext.gp_regs[VKI_PT_CTR] =3D tst->arch.vex.guest=
_CTR;
+ frame->uc.uc_mcontext.gp_regs[VKI_PT_LNK] =3D tst->arch.vex.guest=
_LR;
+ frame->uc.uc_mcontext.gp_regs[VKI_PT_XER] =3D LibVEX_GuestPPC64_g=
et_XER(
+ &tst->arch.vex);
+ frame->uc.uc_mcontext.gp_regs[VKI_PT_CCR] =3D LibVEX_GuestPPC64_g=
et_CR(
+ &tst->arch.vex);
+ //mc->mc_gregs[VKI_PT_MQ] =3D 0;
+ //mc->mc_gregs[VKI_PT_TRAP] =3D 0;
+ //mc->mc_gregs[VKI_PT_DAR] =3D fault_addr;
+ //mc->mc_gregs[VKI_PT_DSISR] =3D 0;
+ //mc->mc_gregs[VKI_PT_RESULT] =3D 0;
+
+ /* XXX should do FP and vector regs */
+
+ /* set up signal return trampoline */
+ frame->tramp[0] =3D 0x38000000U + __NR_rt_sigreturn; /* li 0,__NR_rt_=
sigreturn */
+ frame->tramp[1] =3D 0x44000002U; /* sc */
+ VG_TRACK(post_mem_write, Vg_CoreSignal, tst->tid,
+ (Addr)&frame->tramp, sizeof(frame->tramp));
+
+ /* invalidate any translation of this area */
+ VG_(discard_translations)( (Addr64)&frame->tramp[0],=20
+ sizeof(frame->tramp), "stack_mcontext" ); =
=20
+
+ /* set the signal handler to return to the trampoline */
+ SET_SIGNAL_LR(tst, (Addr) &frame->tramp[0]);
+
+ /* Stack pointer for the handler .. (note, back chain set
+ earlier) */
+ SET_SIGNAL_GPR(tid, 1, sp);
+
+ /* Args for the handler .. */
+ SET_SIGNAL_GPR(tid, 3, sigNo);
+ SET_SIGNAL_GPR(tid, 4, (Addr) &frame->info);
+ SET_SIGNAL_GPR(tid, 5, (Addr) &frame->uc);
+ /* the kernel sets this, though it doesn't seem to be in the ABI */
+ SET_SIGNAL_GPR(tid, 6, (Addr) &frame->info);
+
+ /* Handler is in fact a standard ppc64-linux function descriptor,=20
+ so extract the function entry point and also the toc ptr to use. *=
/
+ SET_SIGNAL_GPR(tid, 2, (Addr) ((ULong*)handler)[1]);
+ tst->arch.vex.guest_CIA =3D (Addr) ((ULong*)handler)[0];
+
+ priv =3D &frame->priv;
+ priv->magicPI =3D 0x31415927;
+ priv->sigNo_private =3D sigNo;
+ priv->shadow =3D tst->arch.vex_shadow;
+
+ if (0)
+ VG_(printf)("pushed signal frame; %R1 now =3D %p, "
+ "next %%CIA =3D %p, status=3D%d\n",=20
+ sp, tst->arch.vex.guest_CIA, tst->status);
}
=20
=20
@@ -343,77 +306,65 @@
/* EXPORTED */
void VG_(sigframe_destroy)( ThreadId tid, Bool isRT )
{
- I_die_here;
-// ThreadState *tst;
-// struct vg_sig_private *priv;
-// Addr sp;
-// UInt frame_size;
-// struct vki_mcontext *mc;
-// Int sigNo;
-// Bool has_siginfo =3D isRT;
-//
-// vg_assert(VG_(is_valid_tid)(tid));
-// tst =3D VG_(get_ThreadState)(tid);
-//
-// /* Check that the stack frame looks valid */
-// sp =3D tst->arch.vex.guest_GPR1;
-// vg_assert(VG_IS_16_ALIGNED(sp));
-// /* JRS 17 Nov 05: This code used to check that *sp -- which should
-// have been set by the stwu at the start of the handler -- points
-// to just above the frame (ie, the previous frame). However, that
-// isn't valid when delivering signals on alt stacks. So I removed
-// it. The frame is still sanity-checked using the priv->magicPI
-// field. */
-//
-// if (has_siginfo) {
-// struct rt_sigframe *frame =3D (struct rt_sigframe *)sp;
-// frame_size =3D sizeof(*frame);
-// mc =3D &frame->ucontext.uc_mcontext;
-// priv =3D &frame->priv;
-// vg_assert(priv->magicPI =3D=3D 0x31415927);
-// tst->sig_mask =3D frame->ucontext.uc_sigmask;
-// } else {
-// struct nonrt_sigframe *frame =3D (struct nonrt_sigframe *)sp;
-// frame_size =3D sizeof(*frame);
-// mc =3D &frame->mcontext;
-// priv =3D &frame->priv;
-// vg_assert(priv->magicPI =3D=3D 0x31415927);
-// tst->sig_mask.sig[0] =3D frame->sigcontext.oldmask;
-// tst->sig_mask.sig[1] =3D frame->sigcontext._unused[3];
-// }
-// tst->tmp_sig_mask =3D tst->sig_mask;
-//
-// sigNo =3D priv->sigNo_private;
-//
-//# define DO(gpr) tst->arch.vex.guest_GPR##gpr =3D mc->mc_gregs[VKI_P=
T_R0+gpr]
-// DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
-// DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
-// DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23);
-// DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
-//# undef DO
-//
-// tst->arch.vex.guest_CIA =3D mc->mc_gregs[VKI_PT_NIP];
-//
-// // Umm ... ? (jrs 2005 July 8)
-// // tst->arch.m_orig_gpr3 =3D mc->mc_gregs[VKI_PT_ORIG_R3];
-//
-// LibVEX_GuestPPC32_put_CR( mc->mc_gregs[VKI_PT_CCR], &tst->arch.vex =
);
-//
-// tst->arch.vex.guest_LR =3D mc->mc_gregs[VKI_PT_LNK];
-// tst->arch.vex.guest_CTR =3D mc->mc_gregs[VKI_PT_CTR];
-// LibVEX_GuestPPC32_put_XER( mc->mc_gregs[VKI_PT_XER], &tst->arch.vex=
);
-//
-// tst->arch.vex_shadow =3D priv->shadow;
-//
-// VG_TRACK(die_mem_stack_signal, sp, frame_size);
-//
-// if (VG_(clo_trace_signals))
-// VG_(message)(Vg_DebugMsg,
-// "vg_pop_signal_frame (thread %d): isRT=3D%d valid m=
agic; EIP=3D%p",
-// tid, has_siginfo, tst->arch.vex.guest_CIA);
-//
-// /* tell the tools */
-// VG_TRACK( post_deliver_signal, tid, sigNo );
+ ThreadState *tst;
+ struct vg_sig_private *priv;
+ Addr sp;
+ UInt frame_size;
+ struct rt_sigframe *frame;
+ Int sigNo;
+ Bool has_siginfo =3D isRT;
+
+ vg_assert(VG_(is_valid_tid)(tid));
+ tst =3D VG_(get_ThreadState)(tid);
+
+ /* Check that the stack frame looks valid */
+ sp =3D tst->arch.vex.guest_GPR1;
+ vg_assert(VG_IS_16_ALIGNED(sp));
+ /* JRS 17 Nov 05: This code used to check that *sp -- which should
+ have been set by the stwu at the start of the handler -- points
+ to just above the frame (ie, the previous frame). However, that
+ isn't valid when delivering signals on alt stacks. So I removed
+ it. The frame is still sanity-checked using the priv->magicPI
+ field. */
+
+ frame =3D (struct rt_sigframe *)sp;
+ frame_size =3D sizeof(*frame);
+ priv =3D &frame->priv;
+ vg_assert(priv->magicPI =3D=3D 0x31415927);
+ tst->sig_mask =3D frame->uc.uc_sigmask;
+ tst->tmp_sig_mask =3D tst->sig_mask;
+
+ sigNo =3D priv->sigNo_private;
+
+# define DO(gpr) tst->arch.vex.guest_GPR##gpr \
+ =3D frame->uc.uc_mcontext.gp_regs[VKI_PT_R0+gpr]
+ DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
+ DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
+ DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23);
+ DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
+# undef DO
+
+ tst->arch.vex.guest_CIA =3D frame->uc.uc_mcontext.gp_regs[VKI_PT_NIP]=
;
+
+ LibVEX_GuestPPC64_put_CR( frame->uc.uc_mcontext.gp_regs[VKI_PT_CCR],=20
+ &tst->arch.vex );
+
+ tst->arch.vex.guest_LR =3D frame->uc.uc_mcontext.gp_regs[VKI_PT_LNK]=
;
+ tst->arch.vex.guest_CTR =3D frame->uc.uc_mcontext.gp_regs[VKI_PT_CTR]=
;
+ LibVEX_GuestPPC64_put_XER( frame->uc.uc_mcontext.gp_regs[VKI_PT_XER],=
=20
+ &tst->arch.vex );
+
+ tst->arch.vex_shadow =3D priv->shadow;
+
+ VG_TRACK(die_mem_stack_signal, sp, frame_size);
+
+ if (VG_(clo_trace_signals))
+ VG_(message)(Vg_DebugMsg,
+ "vg_pop_signal_frame (thread %d): isRT=3D%d valid mag=
ic; EIP=3D%p",
+ tid, has_siginfo, tst->arch.vex.guest_CIA);
+
+ /* tell the tools */
+ VG_TRACK( post_deliver_signal, tid, sigNo );
}
=20
/*--------------------------------------------------------------------*/
|
|
From: <js...@ac...> - 2006-01-03 04:04:32
|
Nightly build on phoenix ( SuSE 10.0 ) started at 2006-01-03 03:30:01 GMT Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 209 tests, 5 stderr failures, 1 stdout failure ================= memcheck/tests/leak-tree (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) none/tests/mremap2 (stdout) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: <js...@ac...> - 2006-01-03 03:56:56
|
Nightly build on g5 ( YDL 4.0, ppc970 ) started at 2006-01-03 04:40:00 CET Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 176 tests, 15 stderr failures, 1 stdout failure ================= memcheck/tests/badjump (stderr) memcheck/tests/badjump2 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/mempool (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/supp1 (stderr) memcheck/tests/supp_unknown (stderr) memcheck/tests/toobig-allocs (stderr) memcheck/tests/xml1 (stderr) massif/tests/toobig-allocs (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/mremap (stderr) |
|
From: Tom H. <to...@co...> - 2006-01-03 03:42:58
|
Nightly build on dunsmere ( athlon, Fedora Core 4 ) started at 2006-01-03 03:30:05 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 211 tests, 7 stderr failures, 2 stdout failures ================= memcheck/tests/leak-tree (stderr) memcheck/tests/mempool (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/sse1_memory (stdout) none/tests/mremap2 (stdout) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) |