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From: Julian S. <js...@ac...> - 2006-01-25 21:40:17
|
> I used this tool to evaluate the amount of data
> transfer between different functions if they were
> executed on , say, different processors. I was
> wondering if there has been a talk about such a tool
> and if it would be useful to other people. Of course,
> the code is not release quality yet but I can work on
This sounds similar to a tool discussed a couple of years
back; it came to be referred to Bandsaw. The idea is
essentially the same, except that we thought it would be valuable
for knowing the amount of data transferred even within the
same process. I think Jeremy made a partial prototype
implementation at one stage, but it went no further.
So I'd be interested to see some example results from your
tool. Can you send some? I'd be interested to see if a
tool along these lines can be made to work well, since if
it could, it would be useful.
J
----------
Some comments from long ago:
[...]
All these things gave me an idea. I can't easily show you where
you made redundant copies, but I can easily enough show you how
data flows from place to place in your program through memory.
Consider this:
int a[];
register int sum;
line A: for (i = 0; i < 10*1000*1000; i++)
a[i] = ... whatever ...
(in some other place in the code)
line B: for (i = 0; i < 10*1000*1000; i++)
sum += a[i];
Whenever data is written to memory, the tool writes into shadow memory
the program location doing the write. When data is read, the tool
knows the location doing the read, and by inspecting shadow memory it
knows who put that data there. It can therefore increment a counter
tracking the volume of data transferred across this (source, destination)
pair. For the above fragment, assuming it was executed once, it
would say
40 MB transferred from (file.c line A) to (file.c line B)
Imagine now doing this across a whole program, and having a GUI
tool like kcachegrind to show the results. The tool shows each line
of code and graphically illustrates (possibly using width of arrows
or something) the locations to which this line sent data, or received
data, and the quantity of data transferred.
In short, the tool considers memory as a channel for transferring
data between different parts of your program, and shows exactly
how you are using that (large but finite) bandwidth.
|
|
From: <sv...@va...> - 2006-01-25 21:30:09
|
Author: sewardj
Date: 2006-01-25 21:29:48 +0000 (Wed, 25 Jan 2006)
New Revision: 1550
Log:
Change the way the ppc backend does ppc32/64 float-integer
conversions. fctiw/fctid/fcfid/stfiwx are now represented explicitly
and are generated by the instruction selector. This removes the need
for hdefs.c to know anything about scratch areas on the stack and
scratch FP registers.
Modified:
trunk/priv/host-ppc/hdefs.c
trunk/priv/host-ppc/hdefs.h
trunk/priv/host-ppc/isel.c
Modified: trunk/priv/host-ppc/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/hdefs.c 2006-01-25 03:26:27 UTC (rev 1549)
+++ trunk/priv/host-ppc/hdefs.c 2006-01-25 21:29:48 UTC (rev 1550)
@@ -910,34 +910,32 @@
vassert(sz =3D=3D 4 || sz =3D=3D 8);
return i;
}
-PPCInstr* PPCInstr_FpF64toF32 ( HReg dst, HReg src ) {
- PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
- i->tag =3D Pin_FpF64toF32;
- i->Pin.FpF64toF32.dst =3D dst;
- i->Pin.FpF64toF32.src =3D src;
+PPCInstr* PPCInstr_FpSTFIW ( HReg addr, HReg data )
+{
+ PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag =3D Pin_FpSTFIW;
+ i->Pin.FpSTFIW.addr =3D addr;
+ i->Pin.FpSTFIW.data =3D data;
return i;
}
-PPCInstr* PPCInstr_FpF64toI32 ( HReg dst, HReg src ) {
- PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
- i->tag =3D Pin_FpF64toI32;
- i->Pin.FpF64toI32.dst =3D dst;
- i->Pin.FpF64toI32.src =3D src;
+PPCInstr* PPCInstr_FpRSP ( HReg dst, HReg src ) {
+ PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag =3D Pin_FpRSP;
+ i->Pin.FpRSP.dst =3D dst;
+ i->Pin.FpRSP.src =3D src;
return i;
}
-PPCInstr* PPCInstr_FpF64toI64 ( HReg dst, HReg src ) {
- PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
- i->tag =3D Pin_FpF64toI64;
- i->Pin.FpF64toI64.dst =3D dst;
- i->Pin.FpF64toI64.src =3D src;
+PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32,=20
+ HReg dst, HReg src ) {
+ PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
+ i->tag =3D Pin_FpCftI;
+ i->Pin.FpCftI.fromI =3D fromI;
+ i->Pin.FpCftI.int32 =3D int32;
+ i->Pin.FpCftI.dst =3D dst;
+ i->Pin.FpCftI.src =3D src;
+ vassert(!(int32 && fromI)); /* no such insn ("fcfiw"). */
return i;
}
-PPCInstr* PPCInstr_FpI64toF64 ( HReg dst, HReg src ) {
- PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
- i->tag =3D Pin_FpI64toF64;
- i->Pin.FpI64toF64.dst =3D dst;
- i->Pin.FpI64toF64.src =3D src;
- return i;
-}
PPCInstr* PPCInstr_FpCMov ( PPCCondCode cond, HReg dst, HReg src ) {
PPCInstr* i =3D LibVEX_Alloc(sizeof(PPCInstr));
i->tag =3D Pin_FpCMov;
@@ -1417,37 +1415,35 @@
}
return;
}
- case Pin_FpF64toF32:
+ case Pin_FpSTFIW:
+ vex_printf("stfiwz ");
+ ppHRegPPC(i->Pin.FpSTFIW.data);
+ vex_printf(",0(");
+ ppHRegPPC(i->Pin.FpSTFIW.addr);
+ vex_printf(")");
+ return;
+ case Pin_FpRSP:
vex_printf("frsp ");
- ppHRegPPC(i->Pin.FpF64toF32.dst);
+ ppHRegPPC(i->Pin.FpRSP.dst);
vex_printf(",");
- ppHRegPPC(i->Pin.FpF64toF32.src);
+ ppHRegPPC(i->Pin.FpRSP.src);
return;
- case Pin_FpF64toI32:
- vex_printf("fctiw %%fr7,");
- ppHRegPPC(i->Pin.FpF64toI32.src);
- vex_printf("; stfiwx %%fr7,%%r0,%%r1");
- vex_printf("; lwzx ");
- ppHRegPPC(i->Pin.FpF64toI32.dst);
- vex_printf(",%%r0,%%r1");
+ case Pin_FpCftI: {
+ HChar* str =3D "fc???";
+ if (i->Pin.FpCftI.fromI =3D=3D False && i->Pin.FpCftI.int32 =3D=3D=
False)
+ str =3D "fctid";
+ else
+ if (i->Pin.FpCftI.fromI =3D=3D False && i->Pin.FpCftI.int32 =3D=3D=
True)
+ str =3D "fctiw";
+ else
+ if (i->Pin.FpCftI.fromI =3D=3D True && i->Pin.FpCftI.int32 =3D=3D =
False)
+ str =3D "fcfid";
+ vex_printf("%s ", str);
+ ppHRegPPC(i->Pin.FpCftI.dst);
+ vex_printf(",");
+ ppHRegPPC(i->Pin.FpCftI.src);
return;
- case Pin_FpF64toI64:
- vex_printf("fctid %%fr7,");
- ppHRegPPC(i->Pin.FpF64toI64.src);
- vex_printf("; stfdx %%fr7,%%r0,%%r1");
- vex_printf("; ldx ");
- ppHRegPPC(i->Pin.FpF64toI64.dst);
- vex_printf(",%%r0,%%r1");
- return;
- case Pin_FpI64toF64:
- vex_printf("stdx ");
- ppHRegPPC(i->Pin.FpI64toF64.src);
- vex_printf(",%%r0,%%r1");
- vex_printf("; lfdx %%fr7,%%r0,%%r1");
- vex_printf("; fcfid ");
- ppHRegPPC(i->Pin.FpI64toF64.dst);
- vex_printf(",%%r7");
- return;
+ }
case Pin_FpCMov:
vex_printf("fpcmov (%s) ", showPPCCondCode(i->Pin.FpCMov.cond));
ppHRegPPC(i->Pin.FpCMov.dst);
@@ -1778,25 +1774,18 @@
i->Pin.FpLdSt.reg);
addRegUsage_PPCAMode(u, i->Pin.FpLdSt.addr);
return;
- case Pin_FpF64toF32:
- addHRegUse(u, HRmWrite, i->Pin.FpF64toF32.dst);
- addHRegUse(u, HRmRead, i->Pin.FpF64toF32.src);
+ case Pin_FpSTFIW:
+ addHRegUse(u, HRmRead, i->Pin.FpSTFIW.addr);
+ addHRegUse(u, HRmRead, i->Pin.FpSTFIW.data);
return;
- case Pin_FpF64toI32:
- addHRegUse(u, HRmWrite, i->Pin.FpF64toI32.dst);
- addHRegUse(u, HRmWrite, hregPPC_FPR7());
- addHRegUse(u, HRmRead, i->Pin.FpF64toI32.src);
+ case Pin_FpRSP:
+ addHRegUse(u, HRmWrite, i->Pin.FpRSP.dst);
+ addHRegUse(u, HRmRead, i->Pin.FpRSP.src);
return;
- case Pin_FpF64toI64:
- addHRegUse(u, HRmWrite, i->Pin.FpF64toI64.dst);
- addHRegUse(u, HRmWrite, hregPPC_FPR7());
- addHRegUse(u, HRmRead, i->Pin.FpF64toI64.src);
+ case Pin_FpCftI:
+ addHRegUse(u, HRmWrite, i->Pin.FpCftI.dst);
+ addHRegUse(u, HRmRead, i->Pin.FpCftI.src);
return;
- case Pin_FpI64toF64:
- addHRegUse(u, HRmWrite, i->Pin.FpI64toF64.dst);
- addHRegUse(u, HRmWrite, hregPPC_FPR7());
- addHRegUse(u, HRmRead, i->Pin.FpI64toF64.src);
- return;
case Pin_FpCMov:
addHRegUse(u, HRmModify, i->Pin.FpCMov.dst);
addHRegUse(u, HRmRead, i->Pin.FpCMov.src);
@@ -1983,22 +1972,18 @@
mapReg(m, &i->Pin.FpLdSt.reg);
mapRegs_PPCAMode(m, i->Pin.FpLdSt.addr);
return;
- case Pin_FpF64toF32:
- mapReg(m, &i->Pin.FpF64toF32.dst);
- mapReg(m, &i->Pin.FpF64toF32.src);
+ case Pin_FpSTFIW:
+ mapReg(m, &i->Pin.FpSTFIW.addr);
+ mapReg(m, &i->Pin.FpSTFIW.data);
return;
- case Pin_FpF64toI32:
- mapReg(m, &i->Pin.FpF64toI32.dst);
- mapReg(m, &i->Pin.FpF64toI32.src);
+ case Pin_FpRSP:
+ mapReg(m, &i->Pin.FpRSP.dst);
+ mapReg(m, &i->Pin.FpRSP.src);
return;
- case Pin_FpF64toI64:
- mapReg(m, &i->Pin.FpF64toI64.dst);
- mapReg(m, &i->Pin.FpF64toI64.src);
+ case Pin_FpCftI:
+ mapReg(m, &i->Pin.FpCftI.dst);
+ mapReg(m, &i->Pin.FpCftI.src);
return;
- case Pin_FpI64toF64:
- mapReg(m, &i->Pin.FpI64toF64.dst);
- mapReg(m, &i->Pin.FpI64toF64.src);
- return;
case Pin_FpCMov:
mapReg(m, &i->Pin.FpCMov.dst);
mapReg(m, &i->Pin.FpCMov.src);
@@ -3205,73 +3190,93 @@
goto done;
}
=20
- case Pin_FpF64toF32: {
- UInt fr_dst =3D fregNo(i->Pin.FpF64toF32.dst);
- UInt fr_src =3D fregNo(i->Pin.FpF64toF32.src);
- // frsp, PPC32 p423
- p =3D mkFormX(p, 63, fr_dst, 0, fr_src, 12, 0);
+ case Pin_FpSTFIW: {
+ UInt ir_addr =3D iregNo(i->Pin.FpSTFIW.addr, mode64);
+ UInt fr_data =3D fregNo(i->Pin.FpSTFIW.data);
+ // stfiwx (store fp64[lo32] as int32), PPC32 p517
+ // Use rA=3D=3D0, so that EA =3D=3D rB =3D=3D ir_addr
+ p =3D mkFormX(p, 31, fr_data, 0/*rA=3D0*/, ir_addr, 983, 0);
goto done;
}
=20
- case Pin_FpF64toI32: {
- UInt r_dst =3D iregNo(i->Pin.FpF64toI32.dst, mode64);
- UInt fr_src =3D fregNo(i->Pin.FpF64toI32.src);
- UChar fr_tmp =3D 7; // Temp freg
- PPCAMode* am_addr;
-
- // fctiw (conv f64 to i32), PPC32 p404
- p =3D mkFormX(p, 63, fr_tmp, 0, fr_src, 14, 0);
-
- // No RI form of stfiwx, so need PPCAMode_RR:
- am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
- hregPPC_GPR0(mode64) );
-
- // stfiwx (store fp64[lo32] as int32), PPC32 p517
- p =3D doAMode_RR(p, 31, 983, fr_tmp, am_addr, mode64);
-
- // lwzx (load int32), PPC32 p463
- p =3D doAMode_RR(p, 31, 23, r_dst, am_addr, mode64);
+ case Pin_FpRSP: {
+ UInt fr_dst =3D fregNo(i->Pin.FpRSP.dst);
+ UInt fr_src =3D fregNo(i->Pin.FpRSP.src);
+ // frsp, PPC32 p423
+ p =3D mkFormX(p, 63, fr_dst, 0, fr_src, 12, 0);
goto done;
}
=20
- case Pin_FpF64toI64: {
- UInt r_dst =3D iregNo(i->Pin.FpF64toI64.dst, mode64);
- UInt fr_src =3D fregNo(i->Pin.FpF64toI64.src);
- UChar fr_tmp =3D 7; // Temp freg
- PPCAMode* am_addr;
-
- // fctid (conv f64 to i64), PPC64 p437
- p =3D mkFormX(p, 63, fr_tmp, 0, fr_src, 814, 0);
-
- am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
- hregPPC_GPR0(mode64) );
-
- // stfdx (store fp64), PPC64 p589
- p =3D doAMode_RR(p, 31, 727, fr_tmp, am_addr, mode64);
-
- // ldx (load int64), PPC64 p476
- p =3D doAMode_RR(p, 31, 21, r_dst, am_addr, mode64);
- goto done;
+ case Pin_FpCftI: {
+ UInt fr_dst =3D fregNo(i->Pin.FpCftI.dst);
+ UInt fr_src =3D fregNo(i->Pin.FpCftI.src);
+ if (i->Pin.FpCftI.fromI =3D=3D False && i->Pin.FpCftI.int32 =3D=3D=
True) {
+ // fctiw (conv f64 to i32), PPC32 p404
+ p =3D mkFormX(p, 63, fr_dst, 0, fr_src, 14, 0);
+ goto done;
+ }
+ goto bad;
}
=20
- case Pin_FpI64toF64: {
- UInt r_src =3D iregNo(i->Pin.FpI64toF64.src, mode64);
- UInt fr_dst =3D fregNo(i->Pin.FpI64toF64.dst);
- UChar fr_tmp =3D 7; // Temp freg
- PPCAMode* am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
- hregPPC_GPR0(mode64) );
+// case Pin_FpF64toI32: {
+// UInt r_dst =3D iregNo(i->Pin.FpF64toI32.dst, mode64);
+// UInt fr_src =3D fregNo(i->Pin.FpF64toI32.src);
+// UChar fr_tmp =3D 7; // Temp freg
+// PPCAMode* am_addr;
+//
+// // fctiw (conv f64 to i32), PPC32 p404
+// p =3D mkFormX(p, 63, fr_tmp, 0, fr_src, 14, 0);
+//
+// // No RI form of stfiwx, so need PPCAMode_RR:
+// am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
+// hregPPC_GPR0(mode64) );
+//
+// // stfiwx (store fp64[lo32] as int32), PPC32 p517
+// p =3D doAMode_RR(p, 31, 983, fr_tmp, am_addr, mode64);
+//
+// // lwzx (load int32), PPC32 p463
+// p =3D doAMode_RR(p, 31, 23, r_dst, am_addr, mode64);
+// goto done;
+// }
+//
+// case Pin_FpF64toI64: {
+// UInt r_dst =3D iregNo(i->Pin.FpF64toI64.dst, mode64);
+// UInt fr_src =3D fregNo(i->Pin.FpF64toI64.src);
+// UChar fr_tmp =3D 7; // Temp freg
+// PPCAMode* am_addr;
+//
+// // fctid (conv f64 to i64), PPC64 p437
+// p =3D mkFormX(p, 63, fr_tmp, 0, fr_src, 814, 0);
+//
+// am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
+// hregPPC_GPR0(mode64) );
+//
+// // stfdx (store fp64), PPC64 p589
+// p =3D doAMode_RR(p, 31, 727, fr_tmp, am_addr, mode64);
+//
+// // ldx (load int64), PPC64 p476
+// p =3D doAMode_RR(p, 31, 21, r_dst, am_addr, mode64);
+// goto done;
+// }
+//
+// case Pin_FpI64toF64: {
+// UInt r_src =3D iregNo(i->Pin.FpI64toF64.src, mode64);
+// UInt fr_dst =3D fregNo(i->Pin.FpI64toF64.dst);
+// UChar fr_tmp =3D 7; // Temp freg
+// PPCAMode* am_addr =3D PPCAMode_RR( StackFramePtr(mode64),
+// hregPPC_GPR0(mode64) );
+//
+// // stdx r_src,r0,r1
+// p =3D doAMode_RR(p, 31, 149, r_src, am_addr, mode64);
+//
+// // lfdx fr7,r0,r1
+// p =3D doAMode_RR(p, 31, 599, fr_tmp, am_addr, mode64);
+//
+// // fcfid (conv i64 to f64), PPC64 p434
+// p =3D mkFormX(p, 63, fr_dst, 0, fr_tmp, 846, 0);
+// goto done;
+// }
=20
- // stdx r_src,r0,r1
- p =3D doAMode_RR(p, 31, 149, r_src, am_addr, mode64);
-
- // lfdx fr7,r0,r1
- p =3D doAMode_RR(p, 31, 599, fr_tmp, am_addr, mode64);
-
- // fcfid (conv i64 to f64), PPC64 p434
- p =3D mkFormX(p, 63, fr_dst, 0, fr_tmp, 846, 0);
- goto done;
- }
-
case Pin_FpCMov: {
UInt fr_dst =3D fregNo(i->Pin.FpCMov.dst);
UInt fr_src =3D fregNo(i->Pin.FpCMov.src);
Modified: trunk/priv/host-ppc/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/hdefs.h 2006-01-25 03:26:27 UTC (rev 1549)
+++ trunk/priv/host-ppc/hdefs.h 2006-01-25 21:29:48 UTC (rev 1550)
@@ -207,8 +207,8 @@
=20
typedef
enum {
- Pam_IR, /* Immediate (signed 16-bit) + Reg */
- Pam_RR /* Reg1 + Reg2 */
+ Pam_IR=3D1, /* Immediate (signed 16-bit) + Reg */
+ Pam_RR=3D2 /* Reg1 + Reg2 */
}
PPCAModeTag;
=20
@@ -240,8 +240,8 @@
/* ("RH" =3D=3D "Register or Halfword immediate") */
typedef=20
enum {
- Prh_Imm=3D1,
- Prh_Reg=3D2
+ Prh_Imm=3D3,
+ Prh_Reg=3D4
}
PPCRHTag;
=20
@@ -271,8 +271,8 @@
=20
typedef
enum {
- Pri_Imm=3D3,
- Pri_Reg=3D4
+ Pri_Imm=3D5,
+ Pri_Reg=3D6
}=20
PPCRITag;
=20
@@ -297,8 +297,8 @@
/* ("VI" =3D=3D "Vector Register or Immediate") */
typedef
enum {
- Pvi_Imm=3D5,
- Pvi_Reg=3D6
+ Pvi_Imm=3D7,
+ Pvi_Reg=3D8
}=20
PPCVI5sTag;
=20
@@ -459,16 +459,15 @@
Pin_FpUnary, /* FP unary op */
Pin_FpBinary, /* FP binary op */
Pin_FpLdSt, /* FP load/store */
- Pin_FpF64toF32, /* FP round IEEE754 double to IEEE754 single */
- Pin_FpF64toI32, /* FP round IEEE754 double to 32-bit integer */
- Pin_FpF64toI64, /* FP round IEEE754 double to 64-bit integer */
- Pin_FpI64toF64, /* FP round IEEE754 64-bit integer to double */
+ Pin_FpSTFIW, /* stfiwx */
+ Pin_FpRSP, /* FP round IEEE754 double to IEEE754 single */
+ Pin_FpCftI, /* fcfid/fctid/fctiw */
Pin_FpCMov, /* FP floating point conditional move */
Pin_FpLdFPSCR, /* mtfsf */
Pin_FpCmp, /* FP compare, generating value into int reg */
+
Pin_RdWrLR, /* Read/Write Link Register */
=20
-// Pin_AvConst, /* Generate restricted AV literal */
Pin_AvLdSt, /* AV load/store (kludging for AMode_IR) */
Pin_AvUnary, /* AV unary general reg=3D>reg */
=20
@@ -636,32 +635,25 @@
HReg reg;
PPCAMode* addr;
} FpLdSt;
- /* By observing the current FPU rounding mode, round src->dst,
- re-interpreting dst to an IEEE754 32-bit (float) type. */
struct {
- HReg src;
- HReg dst;
- } FpF64toF32;
- /* By observing the current FPU rounding mode, round src->dst,
- re-interpreting dst to an 32-bit integer type. */
+ HReg addr; /* int reg */
+ HReg data; /* float reg */
+ } FpSTFIW;
+ /* Round 64-bit FP value to 32-bit FP value in an FP reg. */
struct {
HReg src;
HReg dst;
- } FpF64toI32;
- /* Ditto to 64-bit integer type. */
+ } FpRSP;
+ /* fcfid/fctid/fctiw. Note there's no fcfiw so fromI=3D=3DTrue
+ && int32=3D=3DTrue is not allowed. */
struct {
+ Bool fromI; /* False=3D=3DF->I, True=3D=3DI->F */
+ Bool int32; /* True=3D=3D I is 32, False=3D=3DI is 64 */
HReg src;
HReg dst;
- } FpF64toI64;
- /* By observing the current FPU rounding mode, reinterpret src
- from a 64bit integer to double type, and round into dst. */
+ } FpCftI;
+ /* FP mov src to dst on the given condition. */
struct {
- HReg src;
- HReg dst;
- } FpI64toF64;
- /* Mov src to dst on the given condition, which may not
- be the bogus Xcc_ALWAYS. */
- struct {
PPCCondCode cond;
HReg dst;
HReg src;
@@ -793,10 +785,10 @@
extern PPCInstr* PPCInstr_FpUnary ( PPCFpOp op, HReg dst, HReg src );
extern PPCInstr* PPCInstr_FpBinary ( PPCFpOp op, HReg dst, HReg srcL, =
HReg srcR );
extern PPCInstr* PPCInstr_FpLdSt ( Bool isLoad, UChar sz, HReg, PPCA=
Mode* );
-extern PPCInstr* PPCInstr_FpF64toF32 ( HReg dst, HReg src );
-extern PPCInstr* PPCInstr_FpF64toI32 ( HReg dst, HReg src );
-extern PPCInstr* PPCInstr_FpF64toI64 ( HReg dst, HReg src );
-extern PPCInstr* PPCInstr_FpI64toF64 ( HReg dst, HReg src );
+extern PPCInstr* PPCInstr_FpSTFIW ( HReg addr, HReg data );
+extern PPCInstr* PPCInstr_FpRSP ( HReg dst, HReg src );
+extern PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32,=20
+ HReg dst, HReg src );
extern PPCInstr* PPCInstr_FpCMov ( PPCCondCode, HReg dst, HReg src )=
;
extern PPCInstr* PPCInstr_FpLdFPSCR ( HReg src );
extern PPCInstr* PPCInstr_FpCmp ( HReg dst, HReg srcL, HReg srcR );
Modified: trunk/priv/host-ppc/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/isel.c 2006-01-25 03:26:27 UTC (rev 1549)
+++ trunk/priv/host-ppc/isel.c 2006-01-25 21:29:48 UTC (rev 1550)
@@ -1299,18 +1299,27 @@
}
=20
if (e->Iex.Binop.op =3D=3D Iop_F64toI32) {
- HReg fr_src =3D iselDblExpr(env, e->Iex.Binop.arg2);
- HReg r_dst =3D newVRegI(env); =20
+ /* This works in both mode64 and mode32. */
+ HReg r1 =3D StackFramePtr(env->mode64);
+ PPCAMode* zero_r1 =3D PPCAMode_IR( 0, r1 );
+ HReg fsrc =3D iselDblExpr(env, e->Iex.Binop.arg2);
+ HReg ftmp =3D newVRegF(env);
+ HReg idst =3D newVRegI(env);
+ vassert(!env->mode64); // wait for 64-bit test case
/* Set host rounding mode */
set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
=20
sub_from_sp( env, 16 );
- addInstr(env, PPCInstr_FpF64toI32(r_dst, fr_src));
+ addInstr(env, PPCInstr_FpCftI(False/*F->I*/, True/*int32*/,=20
+ ftmp, fsrc));
+ addInstr(env, PPCInstr_FpSTFIW(r1, ftmp));
+ addInstr(env, PPCInstr_Load(4, True/*signed*/,=20
+ idst, zero_r1, mode64));
add_to_sp( env, 16 );
=20
/* Restore default FPU rounding. */
set_FPU_rounding_default( env );
- return r_dst;
+ return idst;
}
=20
if (e->Iex.Binop.op =3D=3D Iop_F64toI64) {
@@ -1320,7 +1329,8 @@
set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
=20
sub_from_sp( env, 16 );
- addInstr(env, PPCInstr_FpF64toI64(r_dst, fr_src));
+vassert(0);
+// addInstr(env, PPCInstr_FpF64toI64(r_dst, fr_src));
add_to_sp( env, 16 );
=20
/* Restore default FPU rounding. */
@@ -2638,7 +2648,7 @@
HReg r_dst =3D newVRegF(env);
HReg r_src =3D iselDblExpr(env, e->Iex.Binop.arg2);
set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
- addInstr(env, PPCInstr_FpF64toF32(r_dst, r_src));
+ addInstr(env, PPCInstr_FpRSP(r_dst, r_src));
set_FPU_rounding_default( env );
return r_dst;
}
@@ -2780,7 +2790,8 @@
set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
=20
sub_from_sp( env, 16 );
- addInstr(env, PPCInstr_FpI64toF64(fr_dst, r_src));
+vassert(0);
+// addInstr(env, PPCInstr_FpI64toF64(fr_dst, r_src));
add_to_sp( env, 16 );
=20
/* Restore default FPU rounding. */
|
|
From: Josef W. <Jos...@gm...> - 2006-01-25 18:40:17
|
Hi Divya, On Wednesday 25 January 2006 15:48, divya arora wrote: > Hi, > I am a Ph. D. student and as part of my research, I > augmented callgrind to do data structure level > profiling i.e. the tool outputs the data structures > accesses by each user function in the running > program. Wow. What is the slowdown of your approach? Do you read debug info to get names of global/local vars? > It outputs the > following information about these accesses > - whether the data structure is global/stack > variable/heap variable > - size > - for stack variable: function in whose stack the > variable is located + > offset from stack start > - for heap variable: address + function that performed > the allocation I suppose that relation to some stack backtrace instead of only the function could be important (similar to data from massif). > I used this tool to evaluate the amount of data > transfer between different functions if they were > executed on , say, different processors. I was > wondering if there has been a talk about such a tool > and if it would be useful to other people. At least it is very interesting for cache simulation e.g. to locate data structure which generated most of L2 misses. > Of course, > the code is not release quality yet but I can work on > it. I would be very interested in it. I started something like this in src/data.c, but work stalled b/c I wanted variable names to be printed, and to group counts for same types of variables to not produce huge amounts of data. Does your tool actually work with large apps, e.g. Konqueror? Josef > Thanx, > Divya |
|
From: divya a. <div...@ya...> - 2006-01-25 14:48:59
|
Hi, I am a Ph. D. student and as part of my research, I augmented callgrind to do data structure level profiling i.e. the tool outputs the data structures accesses by each user function in the running program. It outputs the following information about these accesses - whether the data structure is global/stack variable/heap variable - size - for stack variable: function in whose stack the variable is located + offset from stack start - for heap variable: address + function that performed the allocation I used this tool to evaluate the amount of data transfer between different functions if they were executed on , say, different processors. I was wondering if there has been a talk about such a tool and if it would be useful to other people. Of course, the code is not release quality yet but I can work on it. Thanx, Divya __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com |
|
From: <js...@ac...> - 2006-01-25 10:28:43
|
Nightly build on minnie ( SuSE 10.0, ppc32 ) started at 2006-01-25 05:00:01 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 188 tests, 10 stderr failures, 2 stdout failures ================= memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/mempool (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigaltstack (stderr) memcheck/tests/stack_changes (stdout) memcheck/tests/stack_changes (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/mremap (stderr) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-fp (stderr) |
|
From: <js...@ac...> - 2006-01-25 04:00:55
|
Nightly build on phoenix ( SuSE 10.0 ) started at 2006-01-25 03:30:01 GMT Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 221 tests, 7 stderr failures, 0 stdout failures ================= memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: <js...@ac...> - 2006-01-25 03:56:49
|
Nightly build on g5 ( YDL 4.0, ppc970 ) started at 2006-01-25 04:40:00 CET Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 191 tests, 6 stderr failures, 1 stdout failure ================= memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_fcntl (stderr) none/tests/mremap (stderr) |
|
From: Tom H. <to...@co...> - 2006-01-25 03:44:19
|
Nightly build on dunsmere ( athlon, Fedora Core 4 ) started at 2006-01-25 03:30:04 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 223 tests, 8 stderr failures, 1 stdout failure ================= memcheck/tests/leak-tree (stderr) memcheck/tests/mempool (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2006-01-25 03:30:39
|
Nightly build on alvis ( i686, Red Hat 7.3 ) started at 2006-01-25 03:15:03 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 222 tests, 21 stderr failures, 2 stdout failures ================= memcheck/tests/addressable (stderr) memcheck/tests/badjump (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/erringfds (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/match-overrun (stderr) memcheck/tests/mempool (stderr) memcheck/tests/partial_load_dflt (stderr) memcheck/tests/partial_load_ok (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigkill (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) memcheck/tests/xml1 (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: <sv...@va...> - 2006-01-25 03:26:33
|
Author: sewardj
Date: 2006-01-25 03:26:27 +0000 (Wed, 25 Jan 2006)
New Revision: 1549
Log:
C89 fixes.
Modified:
trunk/priv/guest-ppc/toIR.c
trunk/priv/host-ppc/isel.c
trunk/priv/ir/irdefs.c
trunk/priv/ir/iropt.c
Modified: trunk/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/toIR.c 2006-01-25 03:01:09 UTC (rev 1548)
+++ trunk/priv/guest-ppc/toIR.c 2006-01-25 03:26:27 UTC (rev 1549)
@@ -365,11 +365,12 @@
*/
static UInt MASK32( UInt begin, UInt end )
{
+ UInt m1, m2, mask;
vassert(begin < 32);
vassert(end < 32);
- UInt m1 =3D ((UInt)(-1)) << begin;
- UInt m2 =3D ((UInt)(-1)) << end << 1;
- UInt mask =3D m1 ^ m2;
+ m1 =3D ((UInt)(-1)) << begin;
+ m2 =3D ((UInt)(-1)) << end << 1;
+ mask =3D m1 ^ m2;
if (begin > end) mask =3D ~mask; // wrap mask
return mask;
}
@@ -377,11 +378,12 @@
/* ditto for 64bit mask */
static ULong MASK64( UInt begin, UInt end )
{
+ ULong m1, m2, mask;
vassert(begin < 64);
vassert(end < 64);
- ULong m1 =3D ((ULong)(-1)) << begin;
- ULong m2 =3D ((ULong)(-1)) << end << 1;
- ULong mask =3D m1 ^ m2;
+ m1 =3D ((ULong)(-1)) << begin;
+ m2 =3D ((ULong)(-1)) << end << 1;
+ mask =3D m1 ^ m2;
if (begin > end) mask =3D ~mask; // wrap mask
return mask;
}
@@ -848,8 +850,8 @@
/* Signed/Unsigned IR widens I8/I16/I32 -> I32/I64 */
static IRExpr* mkSzWiden8 ( IRType ty, IRExpr* src, Bool sined )
{
+ IROp op;
vassert(ty =3D=3D Ity_I32 || ty =3D=3D Ity_I64);
- IROp op;
if (sined) op =3D (ty=3D=3DIty_I32) ? Iop_8Sto32 : Iop_8Sto64;
else op =3D (ty=3D=3DIty_I32) ? Iop_8Uto32 : Iop_8Uto64;
return unop(op, src);
@@ -857,8 +859,8 @@
=20
static IRExpr* mkSzWiden16 ( IRType ty, IRExpr* src, Bool sined )
{
+ IROp op;
vassert(ty =3D=3D Ity_I32 || ty =3D=3D Ity_I64);
- IROp op;
if (sined) op =3D (ty=3D=3DIty_I32) ? Iop_16Sto32 : Iop_16Sto64;
else op =3D (ty=3D=3DIty_I32) ? Iop_16Uto32 : Iop_16Uto64;
return unop(op, src);
@@ -1436,29 +1438,33 @@
=20
static void putXER_SO ( IRExpr* e )
{
+ IRExpr* so;
vassert(typeOfIRExpr(irbb->tyenv, e) =3D=3D Ity_I8);
- IRExpr* so =3D binop(Iop_And8, e, mkU8(1));
+ so =3D binop(Iop_And8, e, mkU8(1));
stmt( IRStmt_Put( OFFB_XER_SO, so ) );
}
=20
static void putXER_OV ( IRExpr* e )
{
+ IRExpr* ov;
vassert(typeOfIRExpr(irbb->tyenv, e) =3D=3D Ity_I8);
- IRExpr* ov =3D binop(Iop_And8, e, mkU8(1));
+ ov =3D binop(Iop_And8, e, mkU8(1));
stmt( IRStmt_Put( OFFB_XER_OV, ov ) );
}
=20
static void putXER_CA ( IRExpr* e )
{
+ IRExpr* ca;
vassert(typeOfIRExpr(irbb->tyenv, e) =3D=3D Ity_I8);
- IRExpr* ca =3D binop(Iop_And8, e, mkU8(1));
+ ca =3D binop(Iop_And8, e, mkU8(1));
stmt( IRStmt_Put( OFFB_XER_CA, ca ) );
}
=20
static void putXER_BC ( IRExpr* e )
{
+ IRExpr* bc;
vassert(typeOfIRExpr(irbb->tyenv, e) =3D=3D Ity_I8);
- IRExpr* bc =3D binop(Iop_And8, e, mkU8(0x7F));
+ bc =3D binop(Iop_And8, e, mkU8(0x7F));
stmt( IRStmt_Put( OFFB_XER_BC, bc ) );
}
=20
Modified: trunk/priv/host-ppc/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/isel.c 2006-01-25 03:01:09 UTC (rev 1548)
+++ trunk/priv/host-ppc/isel.c 2006-01-25 03:26:27 UTC (rev 1549)
@@ -1517,13 +1517,14 @@
break;
case Iop_Clz32:
case Iop_Clz64: {
+ HReg r_src, r_dst;
PPCUnaryOp op_clz =3D (op_unop =3D=3D Iop_Clz32) ? Pun_CLZ32 :
Pun_CLZ64;
if (op_unop =3D=3D Iop_Clz64 && !mode64)
goto irreducible;
/* Count leading zeroes. */
- HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
+ r_dst =3D newVRegI(env);
+ r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
addInstr(env, PPCInstr_Unary(op_clz,r_dst,r_src));
return r_dst;
}
Modified: trunk/priv/ir/irdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/irdefs.c 2006-01-25 03:01:09 UTC (rev 1548)
+++ trunk/priv/ir/irdefs.c 2006-01-25 03:26:27 UTC (rev 1549)
@@ -75,8 +75,8 @@
=20
void ppIRConst ( IRConst* con )
{
+ union { ULong i64; Double f64; } u;
vassert(sizeof(ULong) =3D=3D sizeof(Double));
- union { ULong i64; Double f64; } u;
switch (con->tag) {
case Ico_U1: vex_printf( "%d:I1", con->Ico.U1 ? 1 : 0); b=
reak;
case Ico_U8: vex_printf( "0x%x:I8", (UInt)(con->Ico.U8)); b=
reak;
Modified: trunk/priv/ir/iropt.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/iropt.c 2006-01-25 03:01:09 UTC (rev 1548)
+++ trunk/priv/ir/iropt.c 2006-01-25 03:26:27 UTC (rev 1549)
@@ -3621,6 +3621,7 @@
=20
/* Consider current stmt. */
if (st->tag =3D=3D Ist_Tmp && uses[st->Ist.Tmp.tmp] <=3D 1) {
+ IRExpr *e, *e2;
=20
/* optional extra: dump dead bindings as we find them.
Removes the need for a prior dead-code removal pass. */
@@ -3632,8 +3633,8 @@
=20
/* ok, we have 't =3D E', occ(t)=3D=3D1. Do the abovementioned
actions. */
- IRExpr* e =3D st->Ist.Tmp.data;
- IRExpr* e2 =3D atbSubst_Expr(env, e);
+ e =3D st->Ist.Tmp.data;
+ e2 =3D atbSubst_Expr(env, e);
addToEnvFront(env, st->Ist.Tmp.tmp, e2);
setHints_Expr(&env[0].doesLoad, &env[0].doesGet, e2);
/* don't advance j, as we are deleting this stmt and instead
|
|
From: Tom H. <th...@cy...> - 2006-01-25 03:23:55
|
Nightly build on dellow ( x86_64, Fedora Core 4 ) started at 2006-01-25 03:10:09 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 242 tests, 6 stderr failures, 1 stdout failure ================= memcheck/tests/pointer-trace (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) none/tests/amd64/faultstatus (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2006-01-25 03:19:41
|
Nightly build on aston ( x86_64, Fedora Core 3 ) started at 2006-01-25 03:05:09 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 242 tests, 6 stderr failures, 1 stdout failure ================= memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) none/tests/amd64/faultstatus (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2006-01-25 03:14:24
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2006-01-25 03:00:02 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 242 tests, 7 stderr failures, 1 stdout failure ================= memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) none/tests/amd64/faultstatus (stderr) none/tests/fdleak_fcntl (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: <sv...@va...> - 2006-01-25 03:01:49
|
Author: sewardj
Date: 2006-01-25 03:01:09 +0000 (Wed, 25 Jan 2006)
New Revision: 1548
Log:
Tidy up the ppc instruction selector a bit. This is almost all cosmetic:
- clarify which functions are to be used both in 64-bit and 32-bit mode,
and which are for one or other modes only. Rename accordingly.
- iselWordExpr_AMode: was not generating nice amodes in 64-bit mode.
Fixed.
Modified:
trunk/priv/host-ppc/isel.c
Modified: trunk/priv/host-ppc/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/isel.c 2006-01-24 19:39:02 UTC (rev 1547)
+++ trunk/priv/host-ppc/isel.c 2006-01-25 03:01:09 UTC (rev 1548)
@@ -220,8 +220,8 @@
return env->vregmap[tmp];
}
=20
-static void lookupIRTemp64 ( HReg* vrHI, HReg* vrLO,
- ISelEnv* env, IRTemp tmp )
+static void lookupIRTempPair ( HReg* vrHI, HReg* vrLO,
+ ISelEnv* env, IRTemp tmp )
{
vassert(!env->mode64);
vassert(tmp >=3D 0);
@@ -231,17 +231,6 @@
*vrHI =3D env->vregmapHI[tmp];
}
=20
-static void lookupIRTemp128 ( HReg* vrHI, HReg* vrLO,
- ISelEnv* env, IRTemp tmp )
-{
- vassert(env->mode64);
- vassert(tmp >=3D 0);
- vassert(tmp < env->n_vregmap);
- vassert(env->vregmapHI[tmp] !=3D INVALID_HREG);
- *vrLO =3D env->vregmap[tmp];
- *vrHI =3D env->vregmapHI[tmp];
-}
-
static void addInstr ( ISelEnv* env, PPCInstr* instr )
{
addHInstr(env->code, instr);
@@ -283,48 +272,60 @@
For each XXX, iselXXX calls its iselXXX_wrk counterpart, then
checks that all returned registers are virtual. You should not
call the _wrk version directly.
+
+ 'Word' refers to the size of the native machine word, that is,
+ 32-bit int in 32-bit mode and 64-bit int in 64-bit mode. '2Word'
+ therefore refers to a double-width (64/128-bit) quantity in two
+ integer registers.
*/
-/* Compute an I8/I16/I32 into a GPR. */
-static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e );
-static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e );
+/* 32-bit mode: compute an I8/I16/I32 into a GPR.
+ 64-bit mode: compute an I8/I16/I32/I64 into a GPR. */
+static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e );
+static HReg iselWordExpr_R ( ISelEnv* env, IRExpr* e );
=20
-/* Compute an I8/I16/I32 into a RH (reg-or-halfword-immediate). It's
- important to specify whether the immediate is to be regarded as
- signed or not. If yes, this will never return -32768 as an
+/* 32-bit mode: Compute an I8/I16/I32 into a RH
+ (reg-or-halfword-immediate).
+ 64-bit mode: Compute an I8/I16/I32/I64 into a RH
+ (reg-or-halfword-immediate).
+ It's important to specify whether the immediate is to be regarded
+ as signed or not. If yes, this will never return -32768 as an
immediate; this guaranteed that all signed immediates that are
- return can have their sign inverted if need be. */
-static PPCRH* iselIntExpr_RH_wrk ( ISelEnv* env,=20
- Bool syned, IRExpr* e );
-static PPCRH* iselIntExpr_RH ( ISelEnv* env,=20
- Bool syned, IRExpr* e );
+ return can have their sign inverted if need be.=20
+*/
+static PPCRH* iselWordExpr_RH_wrk ( ISelEnv* env,=20
+ Bool syned, IRExpr* e );
+static PPCRH* iselWordExpr_RH ( ISelEnv* env,=20
+ Bool syned, IRExpr* e );
=20
-/* Compute an I32 into a RI (reg or 32-bit immediate). */
-static PPCRI* iselIntExpr_RI_wrk ( ISelEnv* env, IRExpr* e );
-static PPCRI* iselIntExpr_RI ( ISelEnv* env, IRExpr* e );
+/* 32-bit mode: compute an I32 into a RI (reg or 32-bit immediate).
+ 64-bit mode: compute an I64 into a RI (reg or 64-bit immediate). */
+static PPCRI* iselWordExpr_RI_wrk ( ISelEnv* env, IRExpr* e );
+static PPCRI* iselWordExpr_RI ( ISelEnv* env, IRExpr* e );
=20
-/* Compute an I8 into a reg-or-5-bit-unsigned-immediate, the latter
- being an immediate in the range 1 .. 31 inclusive. Used for doing
- shift amounts. */
-static PPCRH* iselIntExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e );
-static PPCRH* iselIntExpr_RH5u ( ISelEnv* env, IRExpr* e );
+/* In 32 bit mode ONLY, compute an I8 into a
+ reg-or-5-bit-unsigned-immediate, the latter being an immediate in
+ the range 1 .. 31 inclusive. Used for doing shift amounts. */
+static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e );
+static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, IRExpr* e );
=20
-/* Compute an I8 into a reg-or-6-bit-unsigned-immediate, the latter
- being an immediate in the range 1 .. 63 inclusive. Used for doing
- shift amounts. */
-static PPCRH* iselIntExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e );
-static PPCRH* iselIntExpr_RH6u ( ISelEnv* env, IRExpr* e );
+/* In 64-bit mode ONLY, compute an I8 into a Compute an I8 into a
+ reg-or-6-bit-unsigned-immediate, the latter being an immediate in
+ the range 1 .. 63 inclusive. Used for doing shift amounts. */
+static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e );
+static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, IRExpr* e );
=20
-/* Compute an I32 into an AMode. */
-static PPCAMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e );
-static PPCAMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e );
+/* 32-bit mode: compute an I32 into an AMode.
+ 64-bit mode: compute an I64 into an AMode. */
+static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e );
+static PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e );
=20
-/* Compute an I64 into a GPR pair. */
+/* 32-bit mode ONLY: compute an I64 into a GPR pair. */
static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,=20
ISelEnv* env, IRExpr* e );
static void iselInt64Expr ( HReg* rHi, HReg* rLo,=20
ISelEnv* env, IRExpr* e );
=20
-/* Compute an I128 into a GPR64 pair. */
+/* 64-bit mode ONLY: compute an I128 into a GPR64 pair. */
static void iselInt128Expr_wrk ( HReg* rHi, HReg* rLo,=20
ISelEnv* env, IRExpr* e );
static void iselInt128Expr ( HReg* rHi, HReg* rLo,=20
@@ -619,7 +620,7 @@
argiregs |=3D (1 << (argreg+3));
addInstr(env,
mk_iMOVds_RR( argregs[argreg],
- iselIntExpr_R(env, args[i]) ));
+ iselWordExpr_R(env, args[i]) ));
} else { // Ity_I64
HReg rHi, rLo;
if (argreg%2 =3D=3D 1) // ppc32 abi spec for passing LONG=
_LONG
@@ -634,7 +635,7 @@
} else { // mode64
argiregs |=3D (1 << (argreg+3));
addInstr(env, mk_iMOVds_RR( argregs[argreg],
- iselIntExpr_R(env, args[i]) ));
+ iselWordExpr_R(env, args[i]) ));
}
argreg++;
}
@@ -662,7 +663,7 @@
typeOfIRExpr(env->type_env, args[i]) =3D=3D Ity_I64);
if (!mode64) {
if (typeOfIRExpr(env->type_env, args[i]) =3D=3D Ity_I32) {=20
- tmpregs[argreg] =3D iselIntExpr_R(env, args[i]);
+ tmpregs[argreg] =3D iselWordExpr_R(env, args[i]);
} else { // Ity_I64
HReg rHi, rLo;
if (argreg%2 =3D=3D 1) // ppc32 abi spec for passing LONG=
_LONG
@@ -673,7 +674,7 @@
tmpregs[argreg] =3D rLo;
}
} else { // mode64
- tmpregs[argreg] =3D iselIntExpr_R(env, args[i]);
+ tmpregs[argreg] =3D iselWordExpr_R(env, args[i]);
}
argreg++;
}
@@ -751,7 +752,7 @@
addi %tmp, %tmp, base
... Baseblockptr + %tmp ...
*/
- roff =3D iselIntExpr_R(env, off);
+ roff =3D iselWordExpr_R(env, off);
rtmp =3D newVRegI(env);
addInstr(env, PPCInstr_Alu(
Palu_ADD,=20
@@ -847,7 +848,7 @@
*/
=20
// Resolve rounding mode and convert to PPC representation
- r_src =3D roundModeIRtoPPC( env, iselIntExpr_R(env, mode) );
+ r_src =3D roundModeIRtoPPC( env, iselWordExpr_R(env, mode) );
// gpr -> fpr
if (env->mode64) {
fr_src =3D mk_LoadR64toFPR( env, r_src ); // 1*I64 -> F64
@@ -871,7 +872,7 @@
{
HReg r_src;
HReg dst =3D newVRegV(env);
- PPCRI* ri =3D iselIntExpr_RI(env, e);
+ PPCRI* ri =3D iselWordExpr_RI(env, e);
IRType ty =3D typeOfIRExpr(env->type_env,e);
UInt sz =3D (ty =3D=3D Ity_I8) ? 8 : (ty =3D=3D Ity_I16) ? 16 : 32=
;
vassert(ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 || ty =3D=3D Ity_I32);
@@ -991,9 +992,9 @@
if necessary.
*/
=20
-static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e )
+static HReg iselWordExpr_R ( ISelEnv* env, IRExpr* e )
{
- HReg r =3D iselIntExpr_R_wrk(env, e);
+ HReg r =3D iselWordExpr_R_wrk(env, e);
/* sanity checks ... */
# if 0
vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
@@ -1005,7 +1006,7 @@
}
=20
/* DO NOT CALL THIS DIRECTLY ! */
-static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
+static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e )
{
Bool mode64 =3D env->mode64;
MatchInfo mi;
@@ -1024,7 +1025,7 @@
/* --------- LOAD --------- */
case Iex_Load: {
HReg r_dst =3D newVRegI(env);
- PPCAMode* am_addr =3D iselIntExpr_AMode( env, e->Iex.Load.addr );
+ PPCAMode* am_addr =3D iselWordExpr_AMode( env, e->Iex.Load.addr );
if (e->Iex.Load.end !=3D Iend_BE)
goto irreducible;
addInstr(env, PPCInstr_Load( toUChar(sizeofIRType(ty)),=20
@@ -1057,20 +1058,20 @@
values are on the second operand. */
if (aluOp !=3D Palu_INVALID) {
HReg r_dst =3D newVRegI(env);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
PPCRH* ri_srcR =3D NULL;
/* get right arg into an RH, in the appropriate way */
switch (aluOp) {
case Palu_ADD: case Palu_SUB:
- ri_srcR =3D iselIntExpr_RH(env, True/*signed*/,=20
- e->Iex.Binop.arg2);
+ ri_srcR =3D iselWordExpr_RH(env, True/*signed*/,=20
+ e->Iex.Binop.arg2);
break;
case Palu_AND: case Palu_OR: case Palu_XOR:
- ri_srcR =3D iselIntExpr_RH(env, False/*signed*/,
- e->Iex.Binop.arg2);
+ ri_srcR =3D iselWordExpr_RH(env, False/*signed*/,
+ e->Iex.Binop.arg2);
break;
default:
- vpanic("iselIntExpr_R_wrk-aluOp-arg2");
+ vpanic("iselWordExpr_R_wrk-aluOp-arg2");
}
addInstr(env, PPCInstr_Alu(aluOp, r_dst, r_srcL, ri_srcR));
return r_dst;
@@ -1090,15 +1091,15 @@
/* we assume any literal values are on the second operand. */
if (shftOp !=3D Pshft_INVALID) {
HReg r_dst =3D newVRegI(env);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
PPCRH* ri_srcR =3D NULL;
/* get right arg into an RH, in the appropriate way */
switch (shftOp) {
case Pshft_SHL: case Pshft_SHR: case Pshft_SAR:
if (!mode64)
- ri_srcR =3D iselIntExpr_RH5u(env, e->Iex.Binop.arg2);
+ ri_srcR =3D iselWordExpr_RH5u(env, e->Iex.Binop.arg2);
else
- ri_srcR =3D iselIntExpr_RH6u(env, e->Iex.Binop.arg2);
+ ri_srcR =3D iselWordExpr_RH6u(env, e->Iex.Binop.arg2);
break;
default:
vpanic("iselIntExpr_R_wrk-shftOp-arg2");
@@ -1137,8 +1138,8 @@
e->Iex.Binop.op =3D=3D Iop_DivU32) {
Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_DivS32);
HReg r_dst =3D newVRegI(env);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, PPCInstr_Div(syned, True/*32bit div*/,
r_dst, r_srcL, r_srcR));
return r_dst;
@@ -1147,8 +1148,8 @@
e->Iex.Binop.op =3D=3D Iop_DivU64) {
Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_DivS64);
HReg r_dst =3D newVRegI(env);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
vassert(mode64);
addInstr(env, PPCInstr_Div(syned, False/*64bit div*/,
r_dst, r_srcL, r_srcR));
@@ -1156,29 +1157,28 @@
}
=20
/* No? Anyone for a mul? */
- if (e->Iex.Binop.op =3D=3D Iop_Mul16 ||
- e->Iex.Binop.op =3D=3D Iop_Mul32 ||
- e->Iex.Binop.op =3D=3D Iop_Mul64) {
+ if (e->Iex.Binop.op =3D=3D Iop_Mul32
+ || e->Iex.Binop.op =3D=3D Iop_Mul64) {
Bool syned =3D False;
Bool sz32 =3D (e->Iex.Binop.op !=3D Iop_Mul64);
HReg r_dst =3D newVRegI(env);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, PPCInstr_MulL(syned, False/*lo32*/, sz32,
r_dst, r_srcL, r_srcR));
return r_dst;
} =20
=20
/* 32 x 32 -> 64 multiply */
- if (e->Iex.Binop.op =3D=3D Iop_MullU32 ||
- e->Iex.Binop.op =3D=3D Iop_MullS32) {
+ if (mode64
+ && (e->Iex.Binop.op =3D=3D Iop_MullU32
+ || e->Iex.Binop.op =3D=3D Iop_MullS32)) {
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
HReg r_dst =3D newVRegI(env);
Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_MullS32);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
- vassert(mode64);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, PPCInstr_MulL(False/*signedness irrelevant*/,=20
False/*lo32*/, True/*32bit mul*/,
tLo, r_srcL, r_srcR));
@@ -1193,12 +1193,12 @@
}
=20
/* El-mutanto 3-way compare? */
- if (e->Iex.Binop.op =3D=3D Iop_CmpORD32S ||
- e->Iex.Binop.op =3D=3D Iop_CmpORD32U) {
+ if (e->Iex.Binop.op =3D=3D Iop_CmpORD32S
+ || e->Iex.Binop.op =3D=3D Iop_CmpORD32U) {
Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_CmpORD32S);
HReg dst =3D newVRegI(env);
- HReg srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- PPCRH* srcR =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2);
+ HReg srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ PPCRH* srcR =3D iselWordExpr_RH(env, syned, e->Iex.Binop.arg2)=
;
addInstr(env, PPCInstr_Cmp(syned, True/*32bit cmp*/,
7/*cr*/, srcL, srcR));
addInstr(env, PPCInstr_MfCR(dst));
@@ -1207,12 +1207,12 @@
return dst;
}
=20
- if (e->Iex.Binop.op =3D=3D Iop_CmpORD64S ||
- e->Iex.Binop.op =3D=3D Iop_CmpORD64U) {
+ if (e->Iex.Binop.op =3D=3D Iop_CmpORD64S
+ || e->Iex.Binop.op =3D=3D Iop_CmpORD64U) {
Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_CmpORD64S);
HReg dst =3D newVRegI(env);
- HReg srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- PPCRH* srcR =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2);
+ HReg srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ PPCRH* srcR =3D iselWordExpr_RH(env, syned, e->Iex.Binop.arg2)=
;
vassert(mode64);
addInstr(env, PPCInstr_Cmp(syned, False/*64bit cmp*/,
7/*cr*/, srcL, srcR));
@@ -1223,8 +1223,8 @@
}
=20
if (e->Iex.Binop.op =3D=3D Iop_32HLto64) {
- HReg r_Hi =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_Lo =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_Hi =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_Lo =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
HReg r_dst =3D newVRegI(env);
HReg msk =3D newVRegI(env);
vassert(mode64);
@@ -1341,7 +1341,7 @@
if (matchIRExpr(&mi,p_32to1_then_1Uto8,e)) {
IRExpr* expr32 =3D mi.bindee[0];
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, expr32);
+ HReg r_src =3D iselWordExpr_R(env, expr32);
addInstr(env, PPCInstr_Alu(Palu_AND, r_dst,
r_src, PPCRH_Imm(False,1)));
return r_dst;
@@ -1355,7 +1355,7 @@
IRExpr_Load(Iend_BE,Ity_I16,bind(0))) );
if (matchIRExpr(&mi,p_LDbe16_then_16Uto32,e)) {
HReg r_dst =3D newVRegI(env);
- PPCAMode* amode =3D iselIntExpr_AMode( env, mi.bindee[0] );
+ PPCAMode* amode =3D iselWordExpr_AMode( env, mi.bindee[0] );
addInstr(env, PPCInstr_Load(2,False,r_dst,amode, mode64));
return r_dst;
}
@@ -1368,7 +1368,7 @@
case Iop_16Uto32:
case Iop_16Uto64: {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
UShort mask =3D toUShort(op_unop=3D=3DIop_16Uto64 ? 0xFFFF :
op_unop=3D=3DIop_16Uto32 ? 0xFFFF : 0xF=
F);
addInstr(env, PPCInstr_Alu(Palu_AND,r_dst,r_src,
@@ -1377,7 +1377,7 @@
}
case Iop_32Uto64: {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
vassert(mode64);
addInstr(env,
PPCInstr_Shft(Pshft_SHL, False/*64bit shift*/,
@@ -1391,7 +1391,7 @@
case Iop_8Sto32:
case Iop_16Sto32: {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
UShort amt =3D toUShort(op_unop=3D=3DIop_16Sto32 ? 16 : 24);
addInstr(env,
PPCInstr_Shft(Pshft_SHL, True/*32bit shift*/,
@@ -1405,7 +1405,7 @@
case Iop_16Sto64:
case Iop_32Sto64: {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
UShort amt =3D toUShort(op_unop=3D=3DIop_8Sto64 ? 56 :
op_unop=3D=3DIop_16Sto64 ? 48 : 32);
vassert(mode64);
@@ -1422,7 +1422,7 @@
case Iop_Not32:
case Iop_Not64: {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
addInstr(env, PPCInstr_Unary(Pun_NOT,r_dst,r_src));
return r_dst;
}
@@ -1433,7 +1433,7 @@
return rHi; /* and abandon rLo .. poor wee thing :-) */
} else {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
addInstr(env,
PPCInstr_Shft(Pshft_SHR, False/*64bit shift*/,
r_dst, r_src, PPCRH_Imm(False,32)));
@@ -1447,36 +1447,39 @@
return rLo; /* similar stupid comment to the above ... */
} else {
/* This is a no-op. */
- return iselIntExpr_R(env, e->Iex.Unop.arg);
+ return iselWordExpr_R(env, e->Iex.Unop.arg);
}
}
case Iop_64to16: {
if (mode64) { /* This is a no-op. */
- return iselIntExpr_R(env, e->Iex.Unop.arg);
+ return iselWordExpr_R(env, e->Iex.Unop.arg);
}
+ break; /* evidently not used in 32-bit mode */
}
case Iop_16HIto8:
case Iop_32HIto16: {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
UShort shift =3D toUShort(op_unop =3D=3D Iop_16HIto8 ? 8 : 16);
addInstr(env,
PPCInstr_Shft(Pshft_SHR, True/*32bit shift*/,
r_dst, r_src, PPCRH_Imm(False,shift)));
return r_dst;
}
- case Iop_128HIto64: {
- HReg rHi, rLo;
- vassert(mode64);
- iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
- return rHi; /* and abandon rLo .. poor wee thing :-) */
- }
- case Iop_128to64: {
- vassert(mode64);
- HReg rHi, rLo;
- iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
- return rLo; /* similar stupid comment to the above ... */
- }
+ case Iop_128HIto64:=20
+ if (mode64) {
+ HReg rHi, rLo;
+ iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
+ return rHi; /* and abandon rLo .. poor wee thing :-) */
+ }
+ break;
+ case Iop_128to64:
+ if (mode64) {
+ HReg rHi, rLo;
+ iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
+ return rLo; /* similar stupid comment to the above ... */
+ }
+ break;
case Iop_1Uto32:
case Iop_1Uto8: {
HReg r_dst =3D newVRegI(env);
@@ -1499,24 +1502,28 @@
r_dst, r_dst, PPCRH_Imm(False,31)));
return r_dst;
}
- case Iop_1Sto64: {
- /* could do better than this, but for now ... */
- HReg r_dst =3D newVRegI(env);
- PPCCondCode cond =3D iselCondCode(env, e->Iex.Unop.arg);
- addInstr(env, PPCInstr_Set(cond,r_dst));
- addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64bit shift*/,
- r_dst, r_dst, PPCRH_Imm(False,63)))=
;
- addInstr(env, PPCInstr_Shft(Pshft_SAR, False/*64bit shift*/,
- r_dst, r_dst, PPCRH_Imm(False,63)))=
;
- return r_dst;
- }
+ case Iop_1Sto64:=20
+ if (mode64) {
+ /* could do better than this, but for now ... */
+ HReg r_dst =3D newVRegI(env);
+ PPCCondCode cond =3D iselCondCode(env, e->Iex.Unop.arg);
+ addInstr(env, PPCInstr_Set(cond,r_dst));
+ addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64bit shift*/,
+ r_dst, r_dst, PPCRH_Imm(False,63=
)));
+ addInstr(env, PPCInstr_Shft(Pshft_SAR, False/*64bit shift*/,
+ r_dst, r_dst, PPCRH_Imm(False,63=
)));
+ return r_dst;
+ }
+ break;
case Iop_Clz32:
case Iop_Clz64: {
PPCUnaryOp op_clz =3D (op_unop =3D=3D Iop_Clz32) ? Pun_CLZ32 :
Pun_CLZ64;
+ if (op_unop =3D=3D Iop_Clz64 && !mode64)
+ goto irreducible;
/* Count leading zeroes. */
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
addInstr(env, PPCInstr_Unary(op_clz,r_dst,r_src));
return r_dst;
}
@@ -1525,7 +1532,9 @@
case Iop_Neg32:
case Iop_Neg64: {
HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
+ if (op_unop =3D=3D Iop_Neg64 && !mode64)
+ goto irreducible;
addInstr(env, PPCInstr_Unary(Pun_NEG,r_dst,r_src));
return r_dst;
}
@@ -1553,61 +1562,65 @@
}
=20
case Iop_V128to64:
- case Iop_V128HIto64: {
- HReg r_aligned16;
- HReg dst =3D newVRegI(env);
- HReg vec =3D iselVecExpr(env, e->Iex.Unop.arg);
- PPCAMode *am_off0, *am_off8;
- vassert(mode64);
- sub_from_sp( env, 32 ); // Move SP down 32 bytes
+ case Iop_V128HIto64:=20
+ if (mode64) {
+ HReg r_aligned16;
+ HReg dst =3D newVRegI(env);
+ HReg vec =3D iselVecExpr(env, e->Iex.Unop.arg);
+ PPCAMode *am_off0, *am_off8;
+ sub_from_sp( env, 32 ); // Move SP down 32 bytes
=20
- // get a quadword aligned address within our stack space
- r_aligned16 =3D get_sp_aligned16( env );
- am_off0 =3D PPCAMode_IR( 0, r_aligned16 );
- am_off8 =3D PPCAMode_IR( 8 ,r_aligned16 );
+ // get a quadword aligned address within our stack space
+ r_aligned16 =3D get_sp_aligned16( env );
+ am_off0 =3D PPCAMode_IR( 0, r_aligned16 );
+ am_off8 =3D PPCAMode_IR( 8 ,r_aligned16 );
=20
- // store vec, load low word (+8) or high (+0) to dst
- addInstr(env,
- PPCInstr_AvLdSt( False/*store*/, 16, vec, am_off0 ));
- addInstr(env,
- PPCInstr_Load( 8, False, dst,=20
- op_unop =3D=3D Iop_V128HIto64 ? am_o=
ff0 : am_off8,=20
- mode64 ));
+ // store vec, load low word (+8) or high (+0) to dst
+ addInstr(env,
+ PPCInstr_AvLdSt( False/*store*/, 16, vec, am_off0 )=
);
+ addInstr(env,
+ PPCInstr_Load(=20
+ 8, False, dst,=20
+ op_unop =3D=3D Iop_V128HIto64 ? am_off0 : am_off=
8,=20
+ mode64 ));
=20
- add_to_sp( env, 32 ); // Reset SP
- return dst;
- }
-
+ add_to_sp( env, 32 ); // Reset SP
+ return dst;
+ }
+ break;
case Iop_16to8:
case Iop_32to8:
case Iop_32to16:
case Iop_64to8:
/* These are no-ops. */
- return iselIntExpr_R(env, e->Iex.Unop.arg);
+ if (op_unop =3D=3D Iop_Neg64 && !mode64)
+ goto irreducible;
+ return iselWordExpr_R(env, e->Iex.Unop.arg);
=20
/* ReinterpF64asI64(e) */
/* Given an IEEE754 double, produce an I64 with the same bit
pattern. */
- case Iop_ReinterpF64asI64: {
- PPCAMode *am_addr;
- HReg fr_src =3D iselDblExpr(env, e->Iex.Unop.arg);
- HReg r_dst =3D newVRegI(env);
- vassert(mode64);
+ case Iop_ReinterpF64asI64:=20
+ if (mode64) {
+ PPCAMode *am_addr;
+ HReg fr_src =3D iselDblExpr(env, e->Iex.Unop.arg);
+ HReg r_dst =3D newVRegI(env);
=20
- sub_from_sp( env, 16 ); // Move SP down 16 bytes
- am_addr =3D PPCAMode_IR( 0, StackFramePtr(mode64) );
+ sub_from_sp( env, 16 ); // Move SP down 16 bytes
+ am_addr =3D PPCAMode_IR( 0, StackFramePtr(mode64) );
=20
- // store as F64
- addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8,
- fr_src, am_addr ));
- // load as Ity_I64
- addInstr(env, PPCInstr_Load( 8, False,
- r_dst, am_addr, mode64 ));
+ // store as F64
+ addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8,
+ fr_src, am_addr ));
+ // load as Ity_I64
+ addInstr(env, PPCInstr_Load( 8, False,
+ r_dst, am_addr, mode64 ));
=20
- add_to_sp( env, 16 ); // Reset SP
- return r_dst;
- }
- =20
+ add_to_sp( env, 16 ); // Reset SP
+ return r_dst;
+ }
+ break;
+
default:=20
break;
}
@@ -1666,12 +1679,12 @@
HReg r_dst =3D newVRegI(env);
IRConst* con =3D e->Iex.Const.con;
switch (con->tag) {
- case Ico_U64: vassert(mode64);
- l =3D (Long) con->Ico.U64; break;
- case Ico_U32: l =3D (Long)(Int) con->Ico.U32; break;
- case Ico_U16: l =3D (Long)(Int)(Short)con->Ico.U16; break;
- case Ico_U8: l =3D (Long)(Int)(Char )con->Ico.U8; break;
- default: vpanic("iselIntExpr_R.const(ppc)");
+ case Ico_U64: if (!mode64) goto irreducible;
+ l =3D (Long) con->Ico.U64; break;
+ case Ico_U32: l =3D (Long)(Int) con->Ico.U32; break;
+ case Ico_U16: l =3D (Long)(Int)(Short)con->Ico.U16; break;
+ case Ico_U8: l =3D (Long)(Int)(Char )con->Ico.U8; break;
+ default: vpanic("iselIntExpr_R.const(ppc)");
}
addInstr(env, PPCInstr_LI(r_dst, (ULong)l, mode64));
return r_dst;
@@ -1683,9 +1696,9 @@
ty =3D=3D Ity_I32 || ((ty =3D=3D Ity_I64) && mode64)) &&
typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) =3D=3D Ity_I8) {
PPCCondCode cc =3D mk_PPCCondCode( Pct_TRUE, Pcf_7EQ );
- HReg r_cond =3D iselIntExpr_R(env, e->Iex.Mux0X.cond);
- HReg rX =3D iselIntExpr_R(env, e->Iex.Mux0X.exprX);
- PPCRI* r0 =3D iselIntExpr_RI(env, e->Iex.Mux0X.expr0);
+ HReg r_cond =3D iselWordExpr_R(env, e->Iex.Mux0X.cond);
+ HReg rX =3D iselWordExpr_R(env, e->Iex.Mux0X.exprX);
+ PPCRI* r0 =3D iselWordExpr_RI(env, e->Iex.Mux0X.expr0);
HReg r_dst =3D newVRegI(env);
HReg r_tmp =3D newVRegI(env);
addInstr(env, mk_iMOVds_RR(r_dst,rX));
@@ -1719,10 +1732,10 @@
=20
/* Return an AMode which computes the value of the specified
expression, possibly also adding insns to the code list as a
- result. The expression may only be a 32-bit one.
+ result. The expression may only be a word-size one.
*/
=20
-static Bool fits16bits ( UInt u )=20
+static Bool uInt_fits_in_16_bits ( UInt u )=20
{
/* Is u the same as the sign-extend of its lower 16 bits? */
Int i =3D u & 0xFFFF;
@@ -1731,14 +1744,25 @@
return toBool(u =3D=3D (UInt)i);
}
=20
+static Bool uLong_fits_in_16_bits ( ULong u )=20
+{
+ /* Is u the same as the sign-extend of its lower 16 bits? */
+ Long i =3D u & 0xFFFFULL;
+ i <<=3D 48;
+ i >>=3D 48;
+ return toBool(u =3D=3D (ULong)i);
+}
+
static Bool sane_AMode ( ISelEnv* env, PPCAMode* am )
{
Bool mode64 =3D env->mode64;
switch (am->tag) {
case Pam_IR:
+ /* Using uInt_fits_in_16_bits in 64-bit mode seems a bit bogus,
+ somehow, but I think it's OK. */
return toBool( hregClass(am->Pam.IR.base) =3D=3D HRcGPR(mode64) &&=
=20
hregIsVirtual(am->Pam.IR.base) &&=20
- fits16bits(am->Pam.IR.index) );
+ uInt_fits_in_16_bits(am->Pam.IR.index) );
case Pam_RR:
return toBool( hregClass(am->Pam.RR.base) =3D=3D HRcGPR(mode64) &&=
=20
hregIsVirtual(am->Pam.RR.base) &&
@@ -1749,57 +1773,84 @@
}
}
=20
-static PPCAMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e )
+static PPCAMode* iselWordExpr_AMode ( ISelEnv* env, IRExpr* e )
{
- PPCAMode* am =3D iselIntExpr_AMode_wrk(env, e);
+ PPCAMode* am =3D iselWordExpr_AMode_wrk(env, e);
vassert(sane_AMode(env, am));
return am;
}
=20
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCAMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e )
+static PPCAMode* iselWordExpr_AMode_wrk ( ISelEnv* env, IRExpr* e )
{
IRType ty =3D typeOfIRExpr(env->type_env,e);
- vassert(ty =3D=3D (env->mode64 ? Ity_I64 : Ity_I32));
+
+ if (env->mode64) {
+
+ vassert(ty =3D=3D Ity_I64);
=20
- /* Add32(expr,i), where i =3D=3D sign-extend of (i & 0xFFFF) */
- if (e->tag =3D=3D Iex_Binop=20
- && e->Iex.Binop.op =3D=3D Iop_Add32
- && e->Iex.Binop.arg2->tag =3D=3D Iex_Const
- && e->Iex.Binop.arg2->Iex.Const.con->tag =3D=3D Ico_U32
- && fits16bits(e->Iex.Binop.arg2->Iex.Const.con->Ico.U32)) {
- return PPCAMode_IR( e->Iex.Binop.arg2->Iex.Const.con->Ico.U32,
- iselIntExpr_R(env, e->Iex.Binop.arg1) );
- }
+ /* Add64(expr,i), where i =3D=3D sign-extend of (i & 0xFFFF) */
+ if (e->tag =3D=3D Iex_Binop=20
+ && e->Iex.Binop.op =3D=3D Iop_Add64
+ && e->Iex.Binop.arg2->tag =3D=3D Iex_Const
+ && e->Iex.Binop.arg2->Iex.Const.con->tag =3D=3D Ico_U64
+ && uLong_fits_in_16_bits(e->Iex.Binop.arg2
+ ->Iex.Const.con->Ico.U64)) {
+ return PPCAMode_IR( (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.=
U64,
+ iselWordExpr_R(env, e->Iex.Binop.arg1) );
+ }
=20
- /* Add32(expr,expr) */
- if (e->tag =3D=3D Iex_Binop=20
- && e->Iex.Binop.op =3D=3D Iop_Add32) {
- HReg r_base =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_idx =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
- return PPCAMode_RR( r_idx, r_base );
+ /* Add64(expr,expr) */
+ if (e->tag =3D=3D Iex_Binop=20
+ && e->Iex.Binop.op =3D=3D Iop_Add64) {
+ HReg r_base =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_idx =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
+ return PPCAMode_RR( r_idx, r_base );
+ }
+
+ } else {
+
+ vassert(ty =3D=3D Ity_I32);
+ =20
+ /* Add32(expr,i), where i =3D=3D sign-extend of (i & 0xFFFF) */
+ if (e->tag =3D=3D Iex_Binop=20
+ && e->Iex.Binop.op =3D=3D Iop_Add32
+ && e->Iex.Binop.arg2->tag =3D=3D Iex_Const
+ && e->Iex.Binop.arg2->Iex.Const.con->tag =3D=3D Ico_U32
+ && uInt_fits_in_16_bits(e->Iex.Binop.arg2
+ ->Iex.Const.con->Ico.U32)) {
+ return PPCAMode_IR( (Int)e->Iex.Binop.arg2->Iex.Const.con->Ico.=
U32,
+ iselWordExpr_R(env, e->Iex.Binop.arg1) );
+ }
+ =20
+ /* Add32(expr,expr) */
+ if (e->tag =3D=3D Iex_Binop=20
+ && e->Iex.Binop.op =3D=3D Iop_Add32) {
+ HReg r_base =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_idx =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
+ return PPCAMode_RR( r_idx, r_base );
+ }
+
}
=20
/* Doesn't match anything in particular. Generate it into
a register and use that. */
- {
- HReg r1 =3D iselIntExpr_R(env, e);
- return PPCAMode_IR( 0, r1 );
- }
+ return PPCAMode_IR( 0, iselWordExpr_R(env,e) );
}
=20
=20
/* --------------------- RH --------------------- */
=20
-/* Compute an I8/I16/I32 into a RH (reg-or-halfword-immediate). It's
- important to specify whether the immediate is to be regarded as
- signed or not. If yes, this will never return -32768 as an
- immediate; this guaranteed that all signed immediates that are
- return can have their sign inverted if need be. */
+/* Compute an I8/I16/I32 (and I64, in 64-bit mode) into a RH
+ (reg-or-halfword-immediate). It's important to specify whether the
+ immediate is to be regarded as signed or not. If yes, this will
+ never return -32768 as an immediate; this guaranteed that all
+ signed immediates that are return can have their sign inverted if
+ need be. */
=20
-static PPCRH* iselIntExpr_RH ( ISelEnv* env, Bool syned, IRExpr* e )
+static PPCRH* iselWordExpr_RH ( ISelEnv* env, Bool syned, IRExpr* e )
{
- PPCRH* ri =3D iselIntExpr_RH_wrk(env, syned, e);
+ PPCRH* ri =3D iselWordExpr_RH_wrk(env, syned, e);
/* sanity checks ... */
switch (ri->tag) {
case Prh_Imm:
@@ -1817,7 +1868,7 @@
}
=20
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCRH* iselIntExpr_RH_wrk ( ISelEnv* env, Bool syned, IRExpr* e )
+static PPCRH* iselWordExpr_RH_wrk ( ISelEnv* env, Bool syned, IRExpr* e =
)
{
ULong u;
Long l;
@@ -1850,21 +1901,19 @@
}
=20
/* default case: calculate into a register and return that */
- {
- HReg r =3D iselIntExpr_R ( env, e );
- return PPCRH_Reg(r);
- }
+ return PPCRH_Reg( iselWordExpr_R ( env, e ) );
}
=20
=20
/* --------------------- RIs --------------------- */
=20
/* Calculate an expression into an PPCRI operand. As with
- iselIntExpr_R, the expression can have type 32, 16 or 8 bits. */
+ iselIntExpr_R, the expression can have type 32, 16 or 8 bits, or,
+ in 64-bit mode, 64 bits. */
=20
-static PPCRI* iselIntExpr_RI ( ISelEnv* env, IRExpr* e )
+static PPCRI* iselWordExpr_RI ( ISelEnv* env, IRExpr* e )
{
- PPCRI* ri =3D iselIntExpr_RI_wrk(env, e);
+ PPCRI* ri =3D iselWordExpr_RI_wrk(env, e);
/* sanity checks ... */
switch (ri->tag) {
case Pri_Imm:
@@ -1879,7 +1928,7 @@
}
=20
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCRI* iselIntExpr_RI_wrk ( ISelEnv* env, IRExpr* e )
+static PPCRI* iselWordExpr_RI_wrk ( ISelEnv* env, IRExpr* e )
{
Long l;
IRType ty =3D typeOfIRExpr(env->type_env,e);
@@ -1901,10 +1950,7 @@
}
=20
/* default case: calculate into a register and return that */
- {
- HReg r =3D iselIntExpr_R ( env, e );
- return PPCRI_Reg(r);
- }
+ return PPCRI_Reg( iselWordExpr_R ( env, e ) );
}
=20
=20
@@ -1912,11 +1958,13 @@
=20
/* Compute an I8 into a reg-or-5-bit-unsigned-immediate, the latter
being an immediate in the range 1 .. 31 inclusive. Used for doing
- shift amounts. */
+ shift amounts. Only used in 32-bit mode. */
=20
-static PPCRH* iselIntExpr_RH5u ( ISelEnv* env, IRExpr* e )
+static PPCRH* iselWordExpr_RH5u ( ISelEnv* env, IRExpr* e )
{
- PPCRH* ri =3D iselIntExpr_RH5u_wrk(env, e);
+ PPCRH* ri;
+ vassert(!env->mode64);
+ ri =3D iselWordExpr_RH5u_wrk(env, e);
/* sanity checks ... */
switch (ri->tag) {
case Prh_Imm:
@@ -1933,7 +1981,7 @@
}
=20
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCRH* iselIntExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e )
+static PPCRH* iselWordExpr_RH5u_wrk ( ISelEnv* env, IRExpr* e )
{
IRType ty =3D typeOfIRExpr(env->type_env,e);
vassert(ty =3D=3D Ity_I8);
@@ -1947,10 +1995,7 @@
}
=20
/* default case: calculate into a register and return that */
- {
- HReg r =3D iselIntExpr_R ( env, e );
- return PPCRH_Reg(r);
- }
+ return PPCRH_Reg( iselWordExpr_R ( env, e ) );
}
=20
=20
@@ -1958,11 +2003,13 @@
=20
/* Compute an I8 into a reg-or-6-bit-unsigned-immediate, the latter
being an immediate in the range 1 .. 63 inclusive. Used for doing
- shift amounts. */
+ shift amounts. Only used in 64-bit mode. */
=20
-static PPCRH* iselIntExpr_RH6u ( ISelEnv* env, IRExpr* e )
+static PPCRH* iselWordExpr_RH6u ( ISelEnv* env, IRExpr* e )
{
- PPCRH* ri =3D iselIntExpr_RH6u_wrk(env, e);
+ PPCRH* ri;=20
+ vassert(env->mode64);
+ ri =3D iselWordExpr_RH6u_wrk(env, e);
/* sanity checks ... */
switch (ri->tag) {
case Prh_Imm:
@@ -1979,7 +2026,7 @@
}
=20
/* DO NOT CALL THIS DIRECTLY ! */
-static PPCRH* iselIntExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e )
+static PPCRH* iselWordExpr_RH6u_wrk ( ISelEnv* env, IRExpr* e )
{
IRType ty =3D typeOfIRExpr(env->type_env,e);
vassert(ty =3D=3D Ity_I8);
@@ -1993,10 +2040,7 @@
}
=20
/* default case: calculate into a register and return that */
- {
- HReg r =3D iselIntExpr_R ( env, e );
- return PPCRH_Reg(r);
- }
+ return PPCRH_Reg( iselWordExpr_R ( env, e ) );
}
=20
=20
@@ -2036,12 +2080,12 @@
return cond;
}
=20
- /* --- patterns rooted at: 32to1 --- */
+ /* --- patterns rooted at: 32to1 or 64to1 --- */
=20
- /* 32to1 */
+ /* 32to1, 64to1 */
if (e->tag =3D=3D Iex_Unop &&
(e->Iex.Unop.op =3D=3D Iop_32to1 || e->Iex.Unop.op =3D=3D Iop_64t=
o1)) {
- HReg src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
HReg tmp =3D newVRegI(env);
/* could do better, probably -- andi. */
addInstr(env, PPCInstr_Alu(Palu_AND, tmp,
@@ -2057,12 +2101,12 @@
/* could do better -- andi. */
if (e->tag =3D=3D Iex_Unop
&& e->Iex.Unop.op =3D=3D Iop_CmpNEZ8) {
- HReg r_32 =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- HReg r_l =3D newVRegI(env);
- addInstr(env, PPCInstr_Alu(Palu_AND, r_l, r_32,
+ HReg arg =3D iselWordExpr_R(env, e->Iex.Unop.arg);
+ HReg tmp =3D newVRegI(env);
+ addInstr(env, PPCInstr_Alu(Palu_AND, tmp, arg,
PPCRH_Imm(False,0xFF)));
addInstr(env, PPCInstr_Cmp(False/*unsigned*/, True/*32bit cmp*/,
- 7/*cr*/, r_l, PPCRH_Imm(False,0)));
+ 7/*cr*/, tmp, PPCRH_Imm(False,0)));
return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
}
=20
@@ -2071,13 +2115,13 @@
/* CmpNEZ32(x) */
if (e->tag =3D=3D Iex_Unop
&& e->Iex.Unop.op =3D=3D Iop_CmpNEZ32) {
- HReg r1 =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r1 =3D iselWordExpr_R(env, e->Iex.Unop.arg);
addInstr(env, PPCInstr_Cmp(False/*unsigned*/, True/*32bit cmp*/,
7/*cr*/, r1, PPCRH_Imm(False,0)));
return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
}
=20
- /* --- patterns rooted at: Cmp{EQ,NE}{8,16} --- */
+ /* --- patterns rooted at: Cmp*32* --- */
=20
/* Cmp*32*(x,y) */
if (e->tag =3D=3D Iex_Binop=20
@@ -2089,8 +2133,8 @@
|| e->Iex.Binop.op =3D=3D Iop_CmpLE32U)) {
Bool syned =3D (e->Iex.Binop.op =3D=3D Iop_CmpLT32S ||
e->Iex.Binop.op =3D=3D Iop_CmpLE32S);
- HReg r1 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- PPCRH* ri2 =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2);
+ HReg r1 =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ PPCRH* ri2 =3D iselWordExpr_RH(env, syned, e->Iex.Binop.arg2);
addInstr(env, PPCInstr_Cmp(syned, True/*32bit cmp*/,
7/*cr*/, r1, ri2));
=20
@@ -2103,6 +2147,30 @@
}
}
=20
+ /* --- patterns rooted at: CmpNEZ64 --- */
+
+ /* CmpNEZ64 */
+ if (e->tag =3D=3D Iex_Unop=20
+ && e->Iex.Unop.op =3D=3D Iop_CmpNEZ64) {
+ if (!env->mode64) {
+ HReg hi, lo;
+ HReg tmp =3D newVRegI(env);
+ iselInt64Expr( &hi, &lo, env, e->Iex.Unop.arg );
+ addInstr(env, mk_iMOVds_RR(tmp, lo));
+ addInstr(env, PPCInstr_Alu(Palu_OR, tmp, tmp, PPCRH_Reg(hi)));
+ addInstr(env, PPCInstr_Cmp(False/*sign*/, True/*32bit cmp*/,
+ 7/*cr*/, tmp,PPCRH_Imm(False,0)));
+ return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
+ } else { // mode64
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ addInstr(env, PPCInstr_Cmp(False/*sign*/, False/*64bit cmp*/,
+ 7/*cr*/, r_src,PPCRH_Imm(False,0)));
+ return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
+ }
+ }
+
+ /* --- patterns rooted at: Cmp*64* --- */
+
/* Cmp*64*(x,y) */
if (e->tag =3D=3D Iex_Binop=20
&& (e->Iex.Binop.op =3D=3D Iop_CmpEQ64
@@ -2113,8 +2181,8 @@
|| e->Iex.Binop.op =3D=3D Iop_CmpLE64U)) {
Bool syned =3D (e->Iex.Binop.op =3D=3D Iop_CmpLT64S ||
e->Iex.Binop.op =3D=3D Iop_CmpLE64S);
- HReg r1 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- PPCRH* ri2 =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2);
+ HReg r1 =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ PPCRH* ri2 =3D iselWordExpr_RH(env, syned, e->Iex.Binop.arg2);
vassert(env->mode64);
addInstr(env, PPCInstr_Cmp(syned, False/*64bit cmp*/,
7/*cr*/, r1, ri2));
@@ -2128,26 +2196,6 @@
}
}
=20
- /* CmpNEZ64 */
- if (e->tag =3D=3D Iex_Unop=20
- && e->Iex.Unop.op =3D=3D Iop_CmpNEZ64) {
- if (!env->mode64) {
- HReg hi, lo;
- HReg tmp =3D newVRegI(env);
- iselInt64Expr( &hi, &lo, env, e->Iex.Unop.arg );
- addInstr(env, mk_iMOVds_RR(tmp, lo));
- addInstr(env, PPCInstr_Alu(Palu_OR, tmp, tmp, PPCRH_Reg(hi)));
- addInstr(env, PPCInstr_Cmp(False/*sign*/, True/*32bit cmp*/,
- 7/*cr*/, tmp,PPCRH_Imm(False,0)));
- return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
- } else { // mode64
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- addInstr(env, PPCInstr_Cmp(False/*sign*/, False/*64bit cmp*/,
- 7/*cr*/, r_src,PPCRH_Imm(False,0)));
- return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
- }
- }
-
/* var */
if (e->tag =3D=3D Iex_Tmp) {
HReg r_src =3D lookupIRTemp(env, e->Iex.Tmp.tmp);
@@ -2168,13 +2216,14 @@
=20
=20
/*---------------------------------------------------------*/
-/*--- ISEL: Integer expressions (128 bit) ---*/
+/*--- ISEL: Integer expressions (128 bit) ---*/
/*---------------------------------------------------------*/
=20
-/* Compute a 128-bit value into a register pair, which is returned as
- the first two parameters. As with iselIntExpr_R, these may be
- either real or virtual regs; in any case they must not be changed
- by subsequent code emitted by the caller. */
+/* 64-bit mode ONLY: compute a 128-bit value into a register pair,
+ which is returned as the first two parameters. As with
+ iselWordExpr_R, these may be either real or virtual regs; in any
+ case they must not be changed by subsequent code emitted by the
+ caller. */
=20
static void iselInt128Expr ( HReg* rHi, HReg* rLo,
ISelEnv* env, IRExpr* e )
@@ -2199,7 +2248,7 @@
=20
/* read 128-bit IRTemp */
if (e->tag =3D=3D Iex_Tmp) {
- lookupIRTemp128( rHi, rLo, env, e->Iex.Tmp.tmp);
+ lookupIRTempPair( rHi, rLo, env, e->Iex.Tmp.tmp);
return;
}
=20
@@ -2212,8 +2261,8 @@
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_MullS64)=
;
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, PPCInstr_MulL(False/*signedness irrelevant*/,=20
False/*lo64*/, False/*64bit mul*/,
tLo, r_srcL, r_srcR));
@@ -2227,8 +2276,8 @@
=20
/* 64HLto128(e1,e2) */
case Iop_64HLto128:
- *rHi =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- *rLo =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ *rHi =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ *rLo =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
return;
=20
default:=20
@@ -2255,10 +2304,11 @@
/*--- ISEL: Integer expressions (64 bit) ---*/
/*---------------------------------------------------------*/
=20
-/* Compute a 64-bit value into a register pair, which is returned as
- the first two parameters. As with iselIntExpr_R, these may be
- either real or virtual regs; in any case they must not be changed
- by subsequent code emitted by the caller. */
+/* 32-bit mode ONLY: compute a 64-bit value into a register pair,
+ which is returned as the first two parameters. As with
+ iselIntExpr_R, these may be either real or virtual regs; in any
+ case they must not be changed by subsequent code emitted by the
+ caller. */
=20
static void iselInt64Expr ( HReg* rHi, HReg* rLo,
ISelEnv* env, IRExpr* e )
@@ -2278,8 +2328,6 @@
static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,
ISelEnv* env, IRExpr* e )
{
- Bool mode64 =3D env->mode64;
-// HWord fn =3D 0; /* helper fn for most SIMD64 stuff */
vassert(e);
vassert(typeOfIRExpr(env->type_env,e) =3D=3D Ity_I64);
=20
@@ -2291,8 +2339,8 @@
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
vassert(e->Iex.Const.con->tag =3D=3D Ico_U64);
- addInstr(env, PPCInstr_LI(tHi, wHi, mode64));
- addInstr(env, PPCInstr_LI(tLo, wLo, mode64));
+ addInstr(env, PPCInstr_LI(tHi, wHi, False/*mode32*/));
+ addInstr(env, PPCInstr_LI(tLo, wLo, False/*mode32*/));
*rHi =3D tHi;
*rLo =3D tLo;
return;
@@ -2300,19 +2348,19 @@
=20
/* read 64-bit IRTemp */
if (e->tag =3D=3D Iex_Tmp) {
- lookupIRTemp64( rHi, rLo, env, e->Iex.Tmp.tmp);
+ lookupIRTempPair( rHi, rLo, env, e->Iex.Tmp.tmp);
return;
}
=20
/* 64-bit GET */
if (e->tag =3D=3D Iex_Get) {
PPCAMode* am_addr =3D PPCAMode_IR( e->Iex.Get.offset,
- GuestStatePtr(mode64) );
+ GuestStatePtr(False/*mode32*/) );
PPCAMode* am_addr4 =3D advance4(env, am_addr);
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
- addInstr(env, PPCInstr_Load( 4, False, tHi, am_addr, mode64 ));
- addInstr(env, PPCInstr_Load( 4, False, tLo, am_addr4, mode64 ));
+ addInstr(env, PPCInstr_Load( 4, False, tHi, am_addr, False/*mode3=
2*/ ));
+ addInstr(env, PPCInstr_Load( 4, False, tLo, am_addr4, False/*mode3=
2*/ ));
*rHi =3D tHi;
*rLo =3D tLo;
return;
@@ -2325,7 +2373,7 @@
HReg tHi =3D newVRegI(env);
=20
PPCCondCode cc =3D mk_PPCCondCode( Pct_TRUE, Pcf_7EQ );
- HReg r_cond =3D iselIntExpr_R(env, e->Iex.Mux0X.cond);
+ HReg r_cond =3D iselWordExpr_R(env, e->Iex.Mux0X.cond);
HReg r_tmp =3D newVRegI(env);
=20
iselInt64Expr(&e0Hi, &e0Lo, env, e->Iex.Mux0X.expr0);
@@ -2355,8 +2403,8 @@
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
Bool syned =3D toBool(op_binop =3D=3D Iop_MullS32);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_srcL =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
addInstr(env, PPCInstr_MulL(False/*signedness irrelevant*/,=20
False/*lo32*/, True/*32bit mul*/=
,
tLo, r_srcL, r_srcR));
@@ -2404,8 +2452,8 @@
=20
/* 32HLto64(e1,e2) */
case Iop_32HLto64:
- *rHi =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- *rLo =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ *rHi =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ *rLo =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
return;
=20
default:=20
@@ -2421,7 +2469,7 @@
/* 32Sto64(e) */
case Iop_32Sto64: {
HReg tHi =3D newVRegI(env);
- HReg src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
addInstr(env, PPCInstr_Shft(Pshft_SAR, True/*32bit shift*/,
tHi, src, PPCRH_Imm(False,31)));
*rHi =3D tHi;
@@ -2432,8 +2480,8 @@
/* 32Uto64(e) */
case Iop_32Uto64: {
HReg tHi =3D newVRegI(env);
- HReg tLo =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- addInstr(env, PPCInstr_LI(tHi, 0, mode64));
+ HReg tLo =3D iselWordExpr_R(env, e->Iex.Unop.arg);
+ addInstr(env, PPCInstr_LI(tHi, 0, False/*mode32*/));
*rHi =3D tHi;
*rLo =3D tLo;
return;
@@ -2462,9 +2510,9 @@
=20
// load hi,lo words (of hi/lo half of vec) as Ity_I32's
addInstr(env,
- PPCInstr_Load( 4, False, tHi, am_offHI, mode64 ));
+ PPCInstr_Load( 4, False, tHi, am_offHI, False/*mode32*=
/ ));
addInstr(env,
- PPCInstr_Load( 4, False, tLo, am_offLO, mode64 ));
+ PPCInstr_Load( 4, False, tLo, am_offLO, False/*mode32*=
/ ));
=20
add_to_sp( env, 32 ); // Reset SP
*rHi =3D tHi;
@@ -2494,7 +2542,7 @@
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
iselInt64Expr(&yHi, &yLo, env, e->Iex.Unop.arg);
- addInstr(env, PPCInstr_LI(zero, 0, mode64));
+ addInstr(env, PPCInstr_LI(zero, 0, False/*mode32*/));
addInstr(env, PPCInstr_AddSubC( False/*sub*/, True/*set carry*/=
,
tLo, zero, yLo));
addInstr(env, PPCInstr_AddSubC( False/*sub*/, False/*read carry=
*/,
@@ -2514,8 +2562,8 @@
HReg r_dstHi =3D newVRegI(env);
=20
sub_from_sp( env, 16 ); // Move SP down 16 bytes
- am_addr0 =3D PPCAMode_IR( 0, StackFramePtr(mode64) );
- am_addr1 =3D PPCAMode_IR( 4, StackFramePtr(mode64) );
+ am_addr0 =3D PPCAMode_IR( 0, StackFramePtr(False/*mode32*/) );
+ am_addr1 =3D PPCAMode_IR( 4, StackFramePtr(False/*mode32*/) );
=20
// store as F64
addInstr(env, PPCInstr_FpLdSt( False/*store*/, 8,
@@ -2523,9 +2571,9 @@
=20
// load hi,lo as Ity_I32's
addInstr(env, PPCInstr_Load( 4, False, r_dstHi,
- am_addr0, mode64 ));
+ am_addr0, False/*mode32*/ ));
addInstr(env, PPCInstr_Load( 4, False, r_dstLo,
- am_addr1, mode64 ));
+ am_addr1, False/*mode32*/ ));
*rHi =3D r_dstHi;
*rLo =3D r_dstLo;
=20
@@ -2576,7 +2624,7 @@
PPCAMode* am_addr;
HReg r_dst =3D newVRegF(env);
vassert(e->Iex.Load.ty =3D=3D Ity_F32);
- am_addr =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
+ am_addr =3D iselWordExpr_AMode(env, e->Iex.Load.addr);
addInstr(env, PPCInstr_FpLdSt(True/*load*/, 4, r_dst, am_addr));
return r_dst;
}
@@ -2692,7 +2740,7 @@
HReg r_dst =3D newVRegF(env);
PPCAMode* am_addr;
vassert(e->Iex.Load.ty =3D=3D Ity_F64);
- am_addr =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
+ am_addr =3D iselWordExpr_AMode(env, e->Iex.Load.addr);
addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, r_dst, am_addr));
return r_dst;
}
@@ -2724,7 +2772,7 @@
=20
if (e->Iex.Binop.op =3D=3D Iop_I64toF64) {
HReg fr_dst =3D newVRegF(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
vassert(mode64);
=20
/* Set host rounding mode */
@@ -2766,7 +2814,7 @@
iselInt64Expr( &r_srcHi, &r_srcLo, env, e->Iex.Unop.arg);
return mk_LoadRR32toFPR( env, r_srcHi, r_srcLo );
} else {
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
return mk_LoadR64toFPR( env, r_src );
}
}
@@ -2785,7 +2833,7 @@
if (ty =3D=3D Ity_F64
&& typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) =3D=3D Ity_I8=
) {
PPCCondCode cc =3D mk_PPCCondCode( Pct_TRUE, Pcf_7EQ );
- HReg r_cond =3D iselIntExpr_R(env, e->Iex.Mux0X.cond);
+ HReg r_cond =3D iselWordExpr_R(env, e->Iex.Mux0X.cond);
HReg frX =3D iselDblExpr(env, e->Iex.Mux0X.exprX);
HReg fr0 =3D iselDblExpr(env, e->Iex.Mux0X.expr0);
HReg fr_dst =3D newVRegF(env);
@@ -2849,7 +2897,7 @@
PPCAMode* am_addr;
HReg v_dst =3D newVRegV(env);
vassert(e->Iex.Load.ty =3D=3D Ity_V128);
- am_addr =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
+ am_addr =3D iselWordExpr_AMode(env, e->Iex.Load.addr);
addInstr(env, PPCInstr_AvLdSt( True/*load*/, 16, v_dst, am_addr));
return v_dst;
}
@@ -2914,7 +2962,7 @@
=20
case Iop_32UtoV128: {
HReg r_aligned16, r_zeros;
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg r_src =3D iselWordExpr_R(env, e->Iex.Unop.arg);
HReg dst =3D newVRegV(env);
PPCAMode *am_off0, *am_off4, *am_off8, *am_off12;
sub_from_sp( env, 32 ); // Move SP down
@@ -2986,8 +3034,8 @@
add_to_sp( env, 32 ); // Reset SP
return dst;
} else {
- HReg rHi =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg rLo =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ HReg rHi =3D iselWordExpr_R(env, e->Iex.Binop.arg1);
+ HReg rLo =3D iselWordExpr_R(env, e->Iex.Binop.arg2);
HReg dst =3D newVRegV(env);
HReg r_aligned16;
PPCAMode *am_off0, *am_off8;
@@ -3248,10 +3296,10 @@
( mode64 && (tya !=3D Ity_I64)) )
goto stmt_fail;
=20
- am_addr =3D iselIntExpr_AMode(env, stmt->Ist.Store.addr);
+ am_addr =3D iselWordExpr_AMode(env, stmt->Ist.Store.addr);
if (tyd =3D=3D Ity_I8 || tyd =3D=3D Ity_I16 || tyd =3D=3D Ity_I32 =
||
(mode64 && (tyd =3D=3D Ity_I64))) {
- HReg r_src =3D iselIntExpr_R(env, stmt->Ist.Store.data);
+ HReg r_src =3D iselWordExpr_R(env, stmt->Ist.Store.data);
addInstr(env, PPCInstr_Store( toUChar(sizeofIRType(tyd)),=20
am_addr, r_src, mode64 ));
return;
@@ -3282,7 +3330,7 @@
IRType ty =3D typeOfIRExpr(env->type_env, stmt->Ist.Put.data);
if (ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 ||
ty =3D=3D Ity_I32 || ((ty =3D=3D Ity_I64) && mode64)) {
- HReg r_src =3D iselIntExpr_R(env, stmt->Ist.Put.data);
+ HReg r_src =3D iselWordExpr_R(env, stmt->Ist.Put.data);
PPCAMode* am_addr =3D PPCAMode_IR( stmt->Ist.Put.offset,
GuestStatePtr(mode64) );
addInstr(env, PPCInstr_Store( toUChar(sizeofIRType(ty)),=20
@@ -3329,7 +3377,7 @@
stmt->Ist.PutI.ix, stmt->Ist.PutI.bias );
IRType ty =3D typeOfIRExpr(env->type_env, stmt->Ist.PutI.data);
if (ty =3D=3D Ity_I64) {
- HReg r_src =3D iselIntExpr_R(env, stmt->Ist.PutI.data);
+ HReg r_src =3D iselWordExpr_R(env, stmt->Ist.PutI.data);
addInstr(env, PPCInstr_Store( toUChar(8),
dst_am, r_src, mode64 ));
return;
@@ -3344,14 +3392,14 @@
if (ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 ||
ty =3D=3D Ity_I32 || ((ty =3D=3D Ity_I64) && mode64)) {
HReg r_dst =3D lookupIRTemp(env, tmp);
- HReg r_src =3D iselIntExpr_R(env, stmt->Ist.Tmp.data);
+ HReg r_src =3D iselWordExpr_R(env, stmt->Ist.Tmp.data);
addInstr(env, mk_iMOVds_RR( r_dst, r_src ));
return;
}
if (!mode64 && ty =3D=3D Ity_I64) {
HReg r_srcHi, r_srcLo, r_dstHi, r_dstLo;
iselInt64Expr(&r_srcHi,&r_srcLo, env, stmt->Ist.Tmp.data);
- lookupIRTemp64( &r_dstHi, &r_dstLo, env, tmp);
+ lookupIRTempPair( &r_dstHi, &r_dstLo, env, tmp);
addInstr(env, mk_iMOVds_RR(r_dstHi, r_srcHi) );
addInstr(env, mk_iMOVds_RR(r_dstLo, r_srcLo) );
return;
@@ -3359,7 +3407,7 @@
if (mode64 && ty =3D=3D Ity_I128) {
HReg r_srcHi, r_srcLo, r_dstHi, r_dstLo;
iselInt...
[truncated message content] |
|
From: <sv...@va...> - 2006-01-25 02:58:35
|
Author: sewardj Date: 2006-01-25 02:58:28 +0000 (Wed, 25 Jan 2006) New Revision: 5593 Log: Ensure -Wdeclaration-after-statement gets through to vex-land. Modified: trunk/Makefile.tool.am trunk/configure.in Modified: trunk/Makefile.tool.am =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/Makefile.tool.am 2006-01-24 18:50:38 UTC (rev 5592) +++ trunk/Makefile.tool.am 2006-01-25 02:58:28 UTC (rev 5593) @@ -37,16 +37,20 @@ ##.PHONY: @VEX_DIR@/libvex.a =20 @VEX_DIR@/libvex_x86_linux.a: @VEX_DIR@/priv/main/vex_svnversion.h - $(MAKE) -C @VEX_DIR@ CC=3D"$(CC)" libvex_x86_linux.a EXTRA_CFLAGS=3D"$(= AM_CFLAGS_X86_LINUX)" + $(MAKE) -C @VEX_DIR@ CC=3D"$(CC)" libvex_x86_linux.a \ + EXTRA_CFLAGS=3D"$(AM_CFLAGS_X86_LINUX) @FLAG_WDECL_AFTER_STMT@" =20 @VEX_DIR@/libvex_amd64_linux.a: @VEX_DIR@/priv/main/vex_svnversion.h - $(MAKE) -C @VEX_DIR@ CC=3D"$(CC)" libvex_amd64_linux.a EXTRA_CFLAGS=3D"= $(AM_CFLAGS_AMD64_LINUX)" + $(MAKE) -C @VEX_DIR@ CC=3D"$(CC)" libvex_amd64_linux.a \ + EXTRA_CFLAGS=3D"$(AM_CFLAGS_AMD64_LINUX) @FLAG_WDECL_AFTER_STMT@" =20 @VEX_DIR@/libvex_ppc32_linux.a: @VEX_DIR@/priv/main/vex_svnversion.h - $(MAKE) -C @VEX_DIR@ CC=3D"$(CC)" libvex_ppc32_linux.a EXTRA_CFLAGS=3D"= $(AM_CFLAGS_PPC32_LINUX)" + $(MAKE) -C @VEX_DIR@ CC=3D"$(CC)" libvex_ppc32_linux.a \ + EXTRA_CFLAGS=3D"$(AM_CFLAGS_PPC32_LINUX) @FLAG_WDECL_AFTER_STMT@" =20 @VEX_DIR@/libvex_ppc64_linux.a: @VEX_DIR@/priv/main/vex_svnversion.h - $(MAKE) -C @VEX_DIR@ CC=3D"$(CC)" libvex_ppc64_linux.a EXTRA_CFLAGS=3D"= $(AM_CFLAGS_PPC64_LINUX)" + $(MAKE) -C @VEX_DIR@ CC=3D"$(CC)" libvex_ppc64_linux.a \ + EXTRA_CFLAGS=3D"$(AM_CFLAGS_PPC64_LINUX) @FLAG_WDECL_AFTER_STMT@" =20 @VEX_DIR@/priv/main/vex_svnversion.h: $(MAKE) -C @VEX_DIR@ CC=3D"$(CC)" version Modified: trunk/configure.in =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/configure.in 2006-01-24 18:50:38 UTC (rev 5592) +++ trunk/configure.in 2006-01-25 02:58:28 UTC (rev 5593) @@ -486,13 +486,17 @@ ], [ declaration_after_statement=3Dyes +FLAG_WDECL_AFTER_STMT=3D"-Wdeclaration-after-statement" AC_MSG_RESULT([yes]) ], [ declaration_after_statement=3Dno +FLAG_WDECL_AFTER_STMT=3D"" AC_MSG_RESULT([no]) ]) CFLAGS=3D$safe_CFLAGS =20 +AC_SUBST(FLAG_WDECL_AFTER_STMT) + if test x$declaration_after_statement =3D xyes; then CFLAGS=3D"$CFLAGS -Wdeclaration-after-statement" fi |
|
From: Adam S. <sim...@ne...> - 2006-01-25 00:29:35
|
Below is a patch that I've found extremely handy. It modifies
valgrind in the following two ways:
- When memory leaks are detected, the addresses of the first 3
leaked blocks in each loss record are printed.
- If "--db-attach=yes" is specified, valgrind prompts to attach the
db after each loss record is printed.
For instance, I use this in a network server that reads messages from
a socket. All of the messages are allocated in the same place when
they are read, but they are processed differently based on their
contents. With this enhancement, I can examine the contents of leaked
messages to figure out which part of the code should have been
responsible for processing and freeing them.
I've been using this modification for quite a while now. I was a
little concerned at first about attaching the db to a process that has
already exited, but everything seems to work fine. I noticed that
with valgrind 3.1.0 there is actually a backtrace now when the db
attaches. (I used to use valgrind 2.2 and 1.9.6 with this patch, and
there was no backtrace--gdb would just report "???".)
--
Adam Simpkins
sim...@ne...
diff -Naur valgrind-3.1.0/memcheck/mac_leakcheck.c valgrind-3.1.0.db-on-leak/memcheck/mac_leakcheck.c
--- valgrind-3.1.0/memcheck/mac_leakcheck.c 2005-11-25 04:36:02.000000000 -0800
+++ valgrind-3.1.0.db-on-leak/memcheck/mac_leakcheck.c 2006-01-24 13:17:51.000000000 -0800
@@ -126,6 +126,9 @@
}
Reachedness;
+/* The maximum number of lost addresses we store */
+enum { NUM_LOST_ADDRESSES = 3 };
+
/* An entry in the mark stack */
typedef
struct {
@@ -147,6 +150,8 @@
SizeT total_bytes;
SizeT indirect_bytes;
UInt num_blocks;
+ /* The addresses of the first few lost blocks */
+ Addr addresses[NUM_LOST_ADDRESSES];
}
LossRecord;
@@ -272,6 +277,7 @@
LeakExtra* extra = (LeakExtra*)vextra;
LossRecord* l = extra->lossRecord;
const Char *loss = str_lossmode(l->loss_mode);
+ unsigned int n;
if (VG_(clo_xml)) {
VG_(message)(Vg_UserMsg, " <kind>%t</kind>", xml_kind(l->loss_mode));
@@ -312,6 +318,12 @@
l->num_blocks);
}
}
+ for (n = 0; n < NUM_LOST_ADDRESSES; ++n) {
+ if (n >= l->num_blocks)
+ break;
+ VG_(message)(Vg_UserMsg, " Block %d of %d: 0x%x",
+ n + 1, l->num_blocks, l->addresses[n]);
+ }
VG_(pp_ExeContext)(l->allocated_at);
}
@@ -561,6 +573,8 @@
p->num_blocks ++;
p->total_bytes += lc_shadows[i]->size;
p->indirect_bytes += lc_markstack[i].indirect;
+ if (p->num_blocks - 1 < NUM_LOST_ADDRESSES)
+ p->addresses[p->num_blocks - 1] = lc_shadows[i]->data;
} else {
n_lossrecords ++;
p = VG_(malloc)(sizeof(LossRecord));
@@ -569,6 +583,7 @@
p->total_bytes = lc_shadows[i]->size;
p->indirect_bytes = lc_markstack[i].indirect;
p->num_blocks = 1;
+ p->addresses[0] = lc_shadows[i]->data;
p->next = errlist;
errlist = p;
}
@@ -577,6 +592,7 @@
/* Print out the commoned-up blocks and collect summary stats. */
for (i = 0; i < n_lossrecords; i++) {
Bool print_record;
+ Bool allow_db_attach;
LossRecord* p_min = NULL;
SizeT n_min = ~(0x0L);
for (p = errlist; p != NULL; p = p->next) {
@@ -596,6 +612,8 @@
print_record = ( MAC_(clo_show_reachable) ||
Unreached == p_min->loss_mode ||
Interior == p_min->loss_mode );
+ /* Allow attaching the debugger if we print the error */
+ allow_db_attach = print_record;
// Nb: because VG_(unique_error) does all the error processing
// immediately, and doesn't save the error, leakExtra can be
@@ -607,7 +625,7 @@
VG_(unique_error) ( tid, LeakErr, /*Addr*/0, /*s*/NULL,
/*extra*/&leak_extra,
/*where*/p_min->allocated_at, print_record,
- /*allow_GDB_attach*/False, /*count_error*/False );
+ allow_db_attach, /*count_error*/False );
if (is_suppressed) {
blocks_suppressed += p_min->num_blocks;
|