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From: Nicholas N. <nj...@cs...> - 2006-01-24 22:23:20
|
On Tue, 24 Jan 2006, Nicholas Nethercote wrote: > I'm currently writing some documentation about the compressed V bits, I've > attached the part about the secondary V bits table in case it's of interest. I've actually attached it this time. N |
|
From: Nicholas N. <nj...@cs...> - 2006-01-24 22:10:15
|
On Mon, 23 Jan 2006, David Kimdon wrote: >> The bad news is that I have a 90%-complete implementation already. It's > > That's actually good news too, depending on how we look at it, I > wasn't really looking forward to doing all the load/store routines . . (: This stuff is pretty gnarly. >> Looking at your code, I see you have one secondary V bits table per >> SecMap, which is an interesting idea; I have a single table for >> everything. Your approach makes for faster lookups, but the garbage >> collection of stale nodes becomes more complicated... hmm, interesting. > > I wonder if we even need to collect them. In my current implementation > I never remove from the OSet. The nodes _could_ be removed when the > avbits changed to allow it, but are there so few of them that we can > just leave them to rot? I considered that, but decided against it because it could lead to slow-downs and space leaks in bad cases. I'm currently writing some documentation about the compressed V bits, I've attached the part about the secondary V bits table in case it's of interest. It may still be possible to have one sec-V-bits table per sec-map and still do the same basic garbage collection. Nick |
|
From: <sv...@va...> - 2006-01-24 19:39:12
|
Author: sewardj
Date: 2006-01-24 19:39:02 +0000 (Tue, 24 Jan 2006)
New Revision: 1547
Log:
Comment-only change: remove commented out code (lots of), change
indentation in a couple of places, adjust comment at top.
Modified:
trunk/priv/host-ppc/isel.c
Modified: trunk/priv/host-ppc/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc/isel.c 2006-01-24 19:00:05 UTC (rev 1546)
+++ trunk/priv/host-ppc/isel.c 2006-01-24 19:39:02 UTC (rev 1547)
@@ -143,11 +143,6 @@
}
#endif
=20
-//.. static IRExpr* mkU64 ( ULong i )
-//.. {
-//.. return IRExpr_Const(IRConst_U64(i));
-//.. }
-
static IRExpr* mkU32 ( UInt i )
{
return IRExpr_Const(IRConst_U32(i));
@@ -176,11 +171,12 @@
same set of IRTemps as the type mapping does.
=20
- vregmap holds the primary register for the IRTemp.
- - vregmapHI is only used in 32bit mode, for 64-bit integer-
- typed IRTemps. It holds the identity of a second 32-bit
- virtual HReg, which holds the high half of the value.
+ - vregmapHI holds the secondary register for the IRTemp,
+ if any is needed. That's only for Ity_I64 temps
+ in 32 bit mode or Ity_I128 temps in 64-bit mode.
=20
- - A copy of the link reg, so helper functions don't kill it.
+ - The name of the vreg in which we stash a copy of the link reg,
+ so helper functions don't kill it.
=20
- The code array, that is, the insns selected so far.
=20
@@ -351,15 +347,6 @@
/*--- ISEL: Misc helpers ---*/
/*---------------------------------------------------------*/
=20
-//.. /* Is this a 32-bit zero expression? */
-//..=20
-//.. static Bool isZero32 ( IRExpr* e )
-//.. {
-//.. return e->tag =3D=3D Iex_Const
-//.. && e->Iex.Const.con->tag =3D=3D Ico_U32
-//.. && e->Iex.Const.con->Ico.U32 =3D=3D 0;
-//.. }
-
/* Make an int reg-reg move. */
=20
static PPCInstr* mk_iMOVds_RR ( HReg r_dst, HReg r_src )
@@ -370,15 +357,6 @@
return PPCInstr_Alu(Palu_OR, r_dst, r_src, PPCRH_Reg(r_src));
}
=20
-//.. /* Make a vector reg-reg move. */
-//..=20
-//.. static X86Instr* mk_vMOVsd_RR ( HReg src, HReg dst )
-//.. {
-//.. vassert(hregClass(src) =3D=3D HRcVec128);
-//.. vassert(hregClass(dst) =3D=3D HRcVec128);
-//.. return X86Instr_SseReRg(Xsse_MOV, src, dst);
-//.. }
-
/* Advance/retreat %sp by n. */
=20
static void add_to_sp ( ISelEnv* env, UInt n )
@@ -882,41 +860,6 @@
}
=20
=20
-//.. /* Generate !src into a new vector register, and be sure that the c=
ode
-//.. is SSE1 compatible. Amazing that Intel doesn't offer a less cra=
ppy
-//.. way to do this.=20
-//.. */
-//.. static HReg do_sse_Not128 ( ISelEnv* env, HReg src )
-//.. {
-//.. HReg dst =3D newVRegV(env);
-//.. /* Set dst to zero. Not strictly necessary, but the idea of doi=
ng
-//.. a FP comparison on whatever junk happens to be floating aroun=
d
-//.. in it is just too scary. */
-//.. addInstr(env, X86Instr_SseReRg(Xsse_XOR, dst, dst));
-//.. /* And now make it all 1s ... */
-//.. addInstr(env, X86Instr_Sse32Fx4(Xsse_CMPEQF, dst, dst));
-//.. /* Finally, xor 'src' into it. */
-//.. addInstr(env, X86Instr_SseReRg(Xsse_XOR, src, dst));
-//.. return dst;
-//.. }
-
-
-//.. /* Round an x87 FPU value to 53-bit-mantissa precision, to be used
-//.. after most non-simple FPU operations (simple =3D +, -, *, / and
-//.. sqrt).
-//..=20
-//.. This could be done a lot more efficiently if needed, by loading
-//.. zero and adding it to the value to be rounded (fldz ; faddp?).
-//.. */
-//.. static void roundToF64 ( ISelEnv* env, HReg reg )
-//.. {
-//.. X86AMode* zero_esp =3D X86AMode_IR(0, hregX86_ESP());
-//.. sub_from_esp(env, 8);
-//.. addInstr(env, X86Instr_FpLdSt(False/*store*/, 8, reg, zero_esp))=
;
-//.. addInstr(env, X86Instr_FpLdSt(True/*load*/, 8, reg, zero_esp));
-//.. add_to_esp(env, 8);
-//.. }
-
/*
Generates code for AvSplat
- takes in IRExpr* of type 8|16|32
@@ -1095,15 +1038,6 @@
PPCAluOp aluOp;
PPCShftOp shftOp;
=20
-//.. /* Pattern: Sub32(0,x) */
-//.. if (e->Iex.Binop.op =3D=3D Iop_Sub32 && isZero32(e->Iex.Binop=
.arg1)) {
-//.. HReg dst =3D newVRegI(env);
-//.. HReg reg =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
-//.. addInstr(env, mk_iMOVsd_RR(reg,dst));
-//.. addInstr(env, PPCInstr_Unary(Xun_NEG,PPCRM_Reg(dst)));
-//.. return dst;
-//.. }
-
/* Is it an addition or logical style op? */
switch (e->Iex.Binop.op) {
case Iop_Add8: case Iop_Add16: case Iop_Add32: case Iop_Add64:
@@ -1288,32 +1222,6 @@
return dst;
}
=20
-//zz /* Handle misc other ops. */
-//zz if (e->Iex.Binop.op =3D=3D Iop_8HLto16) {
-//zz HReg hi8 =3D newVRegI32(env);
-//zz HReg lo8 =3D newVRegI32(env);
-//zz HReg hi8s =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
-//zz HReg lo8s =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
-//zz addInstr(env,=20
-//zz PPCInstr_Alu(Palu_SHL, hi8, hi8s, PPCRH_Imm(False,8)));
-//zz addInstr(env,=20
-//zz PPCInstr_Alu(Palu_AND, lo8, lo8s, PPCRH_Imm(False,0xFF)=
));
-//zz addInstr(env,=20
-//zz PPCInstr_Alu(Palu_OR, hi8, hi8, PPCRI_Reg(lo8)));
-//zz return hi8;
-//zz }
-//zz=20
-//zz if (e->Iex.Binop.op =3D=3D Iop_16HLto32) {
-//zz HReg hi16 =3D newVRegI32(env);
-//zz HReg lo16 =3D newVRegI32(env);
-//zz HReg hi16s =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
-//zz HReg lo16s =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
-//zz addInstr(env, mk_sh32(env, Psh_SHL, hi16, hi16s, PPCRI_Imm=
(16)));
-//zz addInstr(env, PPCInstr_Alu(Palu_AND, lo16, lo16s, PPCRI_Im=
m(0xFFFF)));
-//zz addInstr(env, PPCInstr_Alu(Palu_OR, hi16, hi16, PPCRI_Reg(=
lo16)));
-//zz return hi16;
-//zz }
-
if (e->Iex.Binop.op =3D=3D Iop_32HLto64) {
HReg r_Hi =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
HReg r_Lo =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
@@ -1331,29 +1239,6 @@
return r_dst;
}
=20
-//.. if (e->Iex.Binop.op =3D=3D Iop_MullS16 || e->Iex.Binop.op =3D=
=3D Iop_MullS8
-//.. || e->Iex.Binop.op =3D=3D Iop_MullU16 || e->Iex.Binop.op =
=3D=3D Iop_MullU8) {
-//.. HReg a16 =3D newVRegI32(env);
-//.. HReg b16 =3D newVRegI32(env);
-//.. HReg a16s =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
-//.. HReg b16s =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
-//.. Int shift =3D (e->Iex.Binop.op =3D=3D Iop_MullS8=20
-//.. || e->Iex.Binop.op =3D=3D Iop_MullU8)
-//.. ? 24 : 16;
-//.. X86ShiftOp shr_op =3D (e->Iex.Binop.op =3D=3D Iop_MullS8=20
-//.. || e->Iex.Binop.op =3D=3D Iop_MullS16=
)
-//.. ? Xsh_SAR : Xsh_SHR;
-//..=20
-//.. addInstr(env, mk_iMOVsd_RR(a16s, a16));
-//.. addInstr(env, mk_iMOVsd_RR(b16s, b16));
-//.. addInstr(env, X86Instr_Sh32(Xsh_SHL, shift, X86RM_Reg(a16)=
));
-//.. addInstr(env, X86Instr_Sh32(Xsh_SHL, shift, X86RM_Reg(b16)=
));
-//.. addInstr(env, X86Instr_Sh32(shr_op, shift, X86RM_Reg(a16)=
));
-//.. addInstr(env, X86Instr_Sh32(shr_op, shift, X86RM_Reg(b16)=
));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_MUL, X86RMI_Reg(a16), b=
16));
-//.. return b16;
-//.. }
-
if (e->Iex.Binop.op =3D=3D Iop_CmpF64) {
HReg fr_srcL =3D iselDblExpr(env, e->Iex.Binop.arg1);
HReg fr_srcR =3D iselDblExpr(env, e->Iex.Binop.arg2);
@@ -1443,28 +1328,6 @@
return r_dst;
}
=20
-
-//.. /* C3210 flags following FPU partial remainder (fprem), both
-//.. IEEE compliant (PREM1) and non-IEEE compliant (PREM). */
-//.. if (e->Iex.Binop.op =3D=3D Iop_PRemC3210F64
-//.. || e->Iex.Binop.op =3D=3D Iop_PRem1C3210F64) {
-//.. HReg junk =3D newVRegF(env);
-//.. HReg dst =3D newVRegI32(env);
-//.. HReg srcL =3D iselDblExpr(env, e->Iex.Binop.arg1);
-//.. HReg srcR =3D iselDblExpr(env, e->Iex.Binop.arg2);
-//.. addInstr(env, X86Instr_FpBinary(
-//.. e->Iex.Binop.op=3D=3DIop_PRemC3210F64=20
-//.. ? Xfp_PREM : Xfp_PREM1,
-//.. srcL,srcR,junk
-//.. ));
-//.. /* The previous pseudo-insn will have left the FPU's C3210
-//.. flags set correctly. So bag them. */
-//.. addInstr(env, X86Instr_FpStSW_AX());
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EAX(), dst));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_AND, X86RMI_Imm(0x4700)=
, dst));
-//.. return dst;
-//.. }
-
break;
}
=20
@@ -1578,40 +1441,6 @@
}
}
case Iop_64to32: {
-
-//:: /* 64to32(MullS32(expr,expr)) */
-//:: {
-//:: DECLARE_PATTERN(p_MullS32_then_64to32);
-//:: DEFINE_PATTERN(p_MullS32_then_64to32,
-//:: unop(Iop_64to32,
-//:: binop(Iop_MullS32, bind(0), bind(1)=
)));
-//:: if (matchIRExpr(&mi,p_MullS32_then_64to32,e)) {
-//:: HReg r_dst =3D newVRegI32(env);
-//:: HReg r_srcL =3D iselIntExpr_R( env, mi.bindee[0=
] );
-//:: PPCRI* ri_srcR =3D mk_FitRI16_S(env, iselIntExpr_RI(=
env, mi.bindee[1] ));
-//:: addInstr(env, PPCInstr_MulL(True, 0, r_dst, r_srcL, =
ri_srcR));
-//:: return r_dst;
-//:: }
-//:: }
-//::=20
-//:: /* 64to32(MullU32(expr,expr)) */
-//:: {
-//:: DECLARE_PATTERN(p_MullU32_then_64to32);
-//:: DEFINE_PATTERN(p_MullU32_then_64to32,
-//:: unop(Iop_64to32,
-//:: binop(Iop_MullU32, bind(0), bind(1)=
)));
-//:: if (matchIRExpr(&mi,p_MullU32_then_64to32,e)) {
-//:: HReg r_dst =3D newVRegI32(env);
-//:: HReg r_srcL =3D iselIntExpr_R( env, mi.bindee[0=
] );
-//:: PPCRI* ri_srcR =3D mk_FitRI16_S(env, iselIntExpr_RI(=
env, mi.bindee[1] ));
-//:: addInstr(env, PPCInstr_MulL(False, 0, r_dst, r_srcL,=
ri_srcR));
-//:: return r_dst;
-//:: }
-//:: }
-//::=20
-//:: // CAB: Also: 64HIto32(MullU32(expr,expr))
-//:: // CAB: Also: 64HIto32(MullS32(expr,expr))
-
if (!mode64) {
HReg rHi, rLo;
iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
@@ -2186,11 +2015,6 @@
/* DO NOT CALL THIS DIRECTLY ! */
static PPCCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e )
{
-// MatchInfo mi;
-// DECLARE_PATTERN(p_32to1);
-//.. DECLARE_PATTERN(p_1Uto32_then_32to1);
-//.. DECLARE_PATTERN(p_1Sto32_then_32to1);
-
vassert(e);
vassert(typeOfIRExpr(env->type_env,e) =3D=3D Ity_I1);
=20
@@ -2214,22 +2038,6 @@
=20
/* --- patterns rooted at: 32to1 --- */
=20
-//.. /* 32to1(1Uto32(expr1)) -- the casts are pointless, ignore them =
*/
-//.. DEFINE_PATTERN(p_1Uto32_then_32to1,
-//.. unop(Iop_32to1,unop(Iop_1Uto32,bind(0))));
-//.. if (matchIRExpr(&mi,p_1Uto32_then_32to1,e)) {
-//.. IRExpr* expr1 =3D mi.bindee[0];
-//.. return iselCondCode(env, expr1);
-//.. }
-//..=20
-//.. /* 32to1(1Sto32(expr1)) -- the casts are pointless, ignore them =
*/
-//.. DEFINE_PATTERN(p_1Sto32_then_32to1,
-//.. unop(Iop_32to1,unop(Iop_1Sto32,bind(0))));
-//.. if (matchIRExpr(&mi,p_1Sto32_then_32to1,e)) {
-//.. IRExpr* expr1 =3D mi.bindee[0];
-//.. return iselCondCode(env, expr1);
-//.. }
-
/* 32to1 */
if (e->tag =3D=3D Iex_Unop &&
(e->Iex.Unop.op =3D=3D Iop_32to1 || e->Iex.Unop.op =3D=3D Iop_64t=
o1)) {
@@ -2271,51 +2079,6 @@
=20
/* --- patterns rooted at: Cmp{EQ,NE}{8,16} --- */
=20
-//.. /* CmpEQ8 / CmpNE8 */
-//.. if (e->tag =3D=3D Iex_Binop=20
-//.. && (e->Iex.Binop.op =3D=3D Iop_CmpEQ8
-//.. || e->Iex.Binop.op =3D=3D Iop_CmpNE8)) {
-//.. HReg r1 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
-//.. X86RMI* rmi2 =3D iselIntExpr_RMI(env, e->Iex.Binop.arg2);
-//.. HReg r =3D newVRegI32(env);
-//.. addInstr(env, mk_iMOVsd_RR(r1,r));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_XOR,rmi2,r));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_AND,X86RMI_Imm(0xFF),r));
-//.. switch (e->Iex.Binop.op) {
-//.. case Iop_CmpEQ8: return Xcc_Z;
-//.. case Iop_CmpNE8: return Xcc_NZ;
-//.. default: vpanic("iselCondCode(x86): CmpXX8");
-//.. }
-//.. }
-//..=20
-//.. /* CmpEQ16 / CmpNE16 */
-//.. if (e->tag =3D=3D Iex_Binop=20
-//.. && (e->Iex.Binop.op =3D=3D Iop_CmpEQ16
-//.. || e->Iex.Binop.op =3D=3D Iop_CmpNE16)) {
-//.. HReg r1 =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
-//.. X86RMI* rmi2 =3D iselIntExpr_RMI(env, e->Iex.Binop.arg2);
-//.. HReg r =3D newVRegI32(env);
-//.. addInstr(env, mk_iMOVsd_RR(r1,r));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_XOR,rmi2,r));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_AND,X86RMI_Imm(0xFFFF),r))=
;
-//.. switch (e->Iex.Binop.op) {
-//.. case Iop_CmpEQ16: return Xcc_Z;
-//.. case Iop_CmpNE16: return Xcc_NZ;
-//.. default: vpanic("iselCondCode(x86): CmpXX16");
-//.. }
-//.. }
-//..=20
-//.. /* CmpNE32(1Sto32(b), 0) =3D=3D> b */
-//.. {
-//.. DECLARE_PATTERN(p_CmpNE32_1Sto32);
-//.. DEFINE_PATTERN(
-//.. p_CmpNE32_1Sto32,
-//.. binop(Iop_CmpNE32, unop(Iop_1Sto32,bind(0)), mkU32(0)));
-//.. if (matchIRExpr(&mi, p_CmpNE32_1Sto32, e)) {
-//.. return iselCondCode(env, mi.bindee[0]);
-//.. }
-//.. }
-
/* Cmp*32*(x,y) */
if (e->tag =3D=3D Iex_Binop=20
&& (e->Iex.Binop.op =3D=3D Iop_CmpEQ32
@@ -2334,9 +2097,7 @@
switch (e->Iex.Binop.op) {
case Iop_CmpEQ32: return mk_PPCCondCode( Pct_TRUE, Pcf_7EQ );
case Iop_CmpNE32: return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
-// case Iop_CmpLT32S: return mk_PPCCondCode( Pct_TRUE, Pcf_7LT );
case Iop_CmpLT32U: return mk_PPCCondCode( Pct_TRUE, Pcf_7LT );
-// case Iop_CmpLE32S: return mk_PPCCondCode( Pct_FALSE, Pcf_7GT );
case Iop_CmpLE32U: return mk_PPCCondCode( Pct_FALSE, Pcf_7GT );
default: vpanic("iselCondCode(ppc): CmpXX32");
}
@@ -2361,62 +2122,12 @@
switch (e->Iex.Binop.op) {
case Iop_CmpEQ64: return mk_PPCCondCode( Pct_TRUE, Pcf_7EQ );
case Iop_CmpNE64: return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ );
-// case Iop_CmpLT64S: return mk_PPCCondCode( Pct_TRUE, Pcf_7LT );
case Iop_CmpLT64U: return mk_PPCCondCode( Pct_TRUE, Pcf_7LT );
-// case Iop_CmpLE64S: return mk_PPCCondCode( Pct_FALSE, Pcf_7GT );
case Iop_CmpLE64U: return mk_PPCCondCode( Pct_FALSE, Pcf_7GT );
default: vpanic("iselCondCode(ppc): CmpXX64");
}
}
=20
-//.. /* CmpNE64(1Sto64(b), 0) =3D=3D> b */
-//.. {
-//.. DECLARE_PATTERN(p_CmpNE64_1Sto64);
-//.. DEFINE_PATTERN(
-//.. p_CmpNE64_1Sto64,
-//.. binop(Iop_CmpNE64, unop(Iop_1Sto64,bind(0)), mkU64(0)));
-//.. if (matchIRExpr(&mi, p_CmpNE64_1Sto64, e)) {
-//.. return iselCondCode(env, mi.bindee[0]);
-//.. }
-//.. }
-//..=20
-//.. /* CmpNE64(x, 0) */
-//.. {
-//.. DECLARE_PATTERN(p_CmpNE64_x_zero);
-//.. DEFINE_PATTERN(
-//.. p_CmpNE64_x_zero,
-//.. binop(Iop_CmpNE64, bind(0), mkU64(0)) );
-//.. if (matchIRExpr(&mi, p_CmpNE64_x_zero, e)) {
-//.. HReg hi, lo;
-//.. IRExpr* x =3D mi.bindee[0];
-//.. HReg tmp =3D newVRegI32(env);
-//.. iselInt64Expr( &hi, &lo, env, x );
-//.. addInstr(env, mk_iMOVsd_RR(hi, tmp));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_OR,X86RMI_Reg(lo), tmp)=
);
-//.. return Xcc_NZ;
-//.. }
-//.. }
-//..=20
-//.. /* CmpNE64 */
-//.. if (e->tag =3D=3D Iex_Binop=20
-//.. && e->Iex.Binop.op =3D=3D Iop_CmpNE64) {
-//.. HReg hi1, hi2, lo1, lo2;
-//.. HReg tHi =3D newVRegI32(env);
-//.. HReg tLo =3D newVRegI32(env);
-//.. iselInt64Expr( &hi1, &lo1, env, e->Iex.Binop.arg1 );
-//.. iselInt64Expr( &hi2, &lo2, env, e->Iex.Binop.arg2 );
-//.. addInstr(env, mk_iMOVsd_RR(hi1, tHi));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_XOR,X86RMI_Reg(hi2), tHi))=
;
-//.. addInstr(env, mk_iMOVsd_RR(lo1, tLo));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_XOR,X86RMI_Reg(lo2), tLo))=
;
-//.. addInstr(env, X86Instr_Alu32R(Xalu_OR,X86RMI_Reg(tHi), tLo));
-//.. switch (e->Iex.Binop.op) {
-//.. case Iop_CmpNE64: return Xcc_NZ;
-//.. default: vpanic("iselCondCode(x86): CmpXX64");
-//.. }
-//.. }
-
-
/* CmpNEZ64 */
if (e->tag =3D=3D Iex_Unop=20
&& e->Iex.Unop.op =3D=3D Iop_CmpNEZ64) {
@@ -2593,22 +2304,6 @@
return;
}
=20
-//.. /* 64-bit load */
-//.. if (e->tag =3D=3D Iex_LDle) {
-//.. HReg tLo, tHi;
-//.. X86AMode *am0, *am4;
-//.. vassert(e->Iex.LDle.ty =3D=3D Ity_I64);
-//.. tLo =3D newVRegI32(env);
-//.. tHi =3D newVRegI32(env);
-//.. am0 =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
-//.. am4 =3D advance4(am0);
-//.. addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(am0), tLo=
));
-//.. addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(am4), tHi=
));
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
-
/* 64-bit GET */
if (e->tag =3D=3D Iex_Get) {
PPCAMode* am_addr =3D PPCAMode_IR( e->Iex.Get.offset,
@@ -2623,21 +2318,6 @@
return;
}
=20
-//.. /* 64-bit GETI */
-//.. if (e->tag =3D=3D Iex_GetI) {
-//.. X86AMode* am=20
-//.. =3D genGuestArrayOffset( env, e->Iex.GetI.descr,=20
-//.. e->Iex.GetI.ix, e->Iex.GetI.bi=
as );
-//.. X86AMode* am4 =3D advance4(am);
-//.. HReg tLo =3D newVRegI32(env);
-//.. HReg tHi =3D newVRegI32(env);
-//.. addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(am), tLo =
));
-//.. addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(am4), tHi=
));
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
-
/* 64-bit Mux0X */
if (e->tag =3D=3D Iex_Mux0X) {
HReg e0Lo, e0Hi, eXLo, eXHi;
@@ -2669,46 +2349,25 @@
if (e->tag =3D=3D Iex_Binop) {
IROp op_binop =3D e->Iex.Binop.op;
switch (op_binop) {
- /* 32 x 32 -> 64 multiply */
- case Iop_MullU32:
- case Iop_MullS32: {
- HReg tLo =3D newVRegI(env);
- HReg tHi =3D newVRegI(env);
- Bool syned =3D toBool(op_binop =3D=3D Iop_MullS32);
- HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
- HReg r_srcR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
- addInstr(env, PPCInstr_MulL(False/*signedness irrelevant*/,=20
- False/*lo32*/, True/*32bit mul*/,
- tLo, r_srcL, r_srcR));
- addInstr(env, PPCInstr_MulL(syned,
- True/*hi32*/, True/*32bit mul*/,
- tHi, r_srcL, r_srcR));
- *rHi =3D tHi;
- *rLo =3D tLo;
- return;
- }
+ /* 32 x 32 -> 64 multiply */
+ case Iop_MullU32:
+ case Iop_MullS32: {
+ HReg tLo =3D newVRegI(env);
+ HReg tHi =3D newVRegI(env);
+ Bool syned =3D toBool(op_binop =3D=3D Iop_MullS32);
+ HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
+ HReg r_srcR =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
+ addInstr(env, PPCInstr_MulL(False/*signedness irrelevant*/,=20
+ False/*lo32*/, True/*32bit mul*/=
,
+ tLo, r_srcL, r_srcR));
+ addInstr(env, PPCInstr_MulL(syned,
+ True/*hi32*/, True/*32bit mul*/,
+ tHi, r_srcL, r_srcR));
+ *rHi =3D tHi;
+ *rLo =3D tLo;
+ return;
+ }
=20
-//.. /* 64 x 32 -> (32(rem),32(div)) division */
-//.. case Iop_DivModU64to32:
-//.. case Iop_DivModS64to32: {
-//.. /* Get the 64-bit operand into edx:eax, and the other i=
nto
-//.. any old R/M. */
-//.. HReg sHi, sLo;
-//.. HReg tLo =3D newVRegI32(env);
-//.. HReg tHi =3D newVRegI32(env);
-//.. Bool syned =3D op_binop =3D=3D Iop_DivModS64to32;
-//.. X86RM* rmRight =3D iselIntExpr_RM(env, e->Iex.Binop.arg=
2);
-//.. iselInt64Expr(&sHi,&sLo, env, e->Iex.Binop.arg1);
-//.. addInstr(env, mk_iMOVsd_RR(sHi, hregX86_EDX()));
-//.. addInstr(env, mk_iMOVsd_RR(sLo, hregX86_EAX()));
-//.. addInstr(env, X86Instr_Div(syned, Xss_32, rmRight));
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EDX(), tHi));
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EAX(), tLo));
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
-
/* Or64/And64/Xor64 */
case Iop_Or64:
case Iop_And64:
@@ -2729,19 +2388,15 @@
=20
/* Add64/Sub64 */
case Iop_Add64: {
-//.. case Iop_Sub64: {
HReg xLo, xHi, yLo, yHi;
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
-//.. if (op_binop=3D=3DIop_Add64) {
addInstr(env, PPCInstr_AddSubC( True/*add*/, True /*set carr=
y*/,
tLo, xLo, yLo));
addInstr(env, PPCInstr_AddSubC( True/*add*/, False/*read car=
ry*/,
tHi, xHi, yHi));
-//.. } else { // Sub64
-//.. }
*rHi =3D tHi;
*rLo =3D tLo;
return;
@@ -2753,290 +2408,8 @@
*rLo =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
return;
=20
-//.. /* 64-bit shifts */
-//.. case Iop_Shl64: {
-//.. /* We use the same ingenious scheme as gcc. Put the va=
lue
-//.. to be shifted into %hi:%lo, and the shift amount int=
o
-//.. %cl. Then (dsts on right, a la ATT syntax):
-//.. =20
-//.. shldl %cl, %lo, %hi -- make %hi be right for the
-//.. -- shift amt %cl % 32
-//.. shll %cl, %lo -- make %lo be right for the
-//.. -- shift amt %cl % 32
-//..=20
-//.. Now, if (shift amount % 64) is in the range 32 .. 63=
,
-//.. we have to do a fixup, which puts the result low hal=
f
-//.. into the result high half, and zeroes the low half:
-//..=20
-//.. testl $32, %ecx
-//..=20
-//.. cmovnz %lo, %hi
-//.. movl $0, %tmp -- sigh; need yet another reg
-//.. cmovnz %tmp, %lo=20
-//.. */
-//.. HReg rAmt, sHi, sLo, tHi, tLo, tTemp;
-//.. tLo =3D newVRegI32(env);
-//.. tHi =3D newVRegI32(env);
-//.. tTemp =3D newVRegI32(env);
-//.. rAmt =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
-//.. iselInt64Expr(&sHi,&sLo, env, e->Iex.Binop.arg1);
-//.. addInstr(env, mk_iMOVsd_RR(rAmt, hregX86_ECX()));
-//.. addInstr(env, mk_iMOVsd_RR(sHi, tHi));
-//.. addInstr(env, mk_iMOVsd_RR(sLo, tLo));
-//.. /* Ok. Now shift amt is in %ecx, and value is in tHi/t=
Lo
-//.. and those regs are legitimately modifiable. */
-//.. addInstr(env, X86Instr_Sh3232(Xsh_SHL, 0/*%cl*/, tLo, t=
Hi));
-//.. addInstr(env, X86Instr_Sh32(Xsh_SHL, 0/*%cl*/, X86RM_Re=
g(tLo)));
-//.. addInstr(env, X86Instr_Test32(X86RI_Imm(32),=20
-//.. X86RM_Reg(hregX86_ECX())));
-//.. addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(tLo), t=
Hi));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(0), =
tTemp));
-//.. addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(tTemp),=
tLo));
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
-//..=20
-//.. case Iop_Shr64: {
-//.. /* We use the same ingenious scheme as gcc. Put the va=
lue
-//.. to be shifted into %hi:%lo, and the shift amount int=
o
-//.. %cl. Then:
-//.. =20
-//.. shrdl %cl, %hi, %lo -- make %lo be right for the
-//.. -- shift amt %cl % 32
-//.. shrl %cl, %hi -- make %hi be right for the
-//.. -- shift amt %cl % 32
-//..=20
-//.. Now, if (shift amount % 64) is in the range 32 .. 63=
,
-//.. we have to do a fixup, which puts the result high ha=
lf
-//.. into the result low half, and zeroes the high half:
-//..=20
-//.. testl $32, %ecx
-//..=20
-//.. cmovnz %hi, %lo
-//.. movl $0, %tmp -- sigh; need yet another reg
-//.. cmovnz %tmp, %hi
-//.. */
-//.. HReg rAmt, sHi, sLo, tHi, tLo, tTemp;
-//.. tLo =3D newVRegI32(env);
-//.. tHi =3D newVRegI32(env);
-//.. tTemp =3D newVRegI32(env);
-//.. rAmt =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
-//.. iselInt64Expr(&sHi,&sLo, env, e->Iex.Binop.arg1);
-//.. addInstr(env, mk_iMOVsd_RR(rAmt, hregX86_ECX()));
-//.. addInstr(env, mk_iMOVsd_RR(sHi, tHi));
-//.. addInstr(env, mk_iMOVsd_RR(sLo, tLo));
-//.. /* Ok. Now shift amt is in %ecx, and value is in tHi/t=
Lo
-//.. and those regs are legitimately modifiable. */
-//.. addInstr(env, X86Instr_Sh3232(Xsh_SHR, 0/*%cl*/, tHi, t=
Lo));
-//.. addInstr(env, X86Instr_Sh32(Xsh_SHR, 0/*%cl*/, X86RM_Re=
g(tHi)));
-//.. addInstr(env, X86Instr_Test32(X86RI_Imm(32),=20
-//.. X86RM_Reg(hregX86_ECX())));
-//.. addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(tHi), t=
Lo));
-//.. addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Imm(0), =
tTemp));
-//.. addInstr(env, X86Instr_CMov32(Xcc_NZ, X86RM_Reg(tTemp),=
tHi));
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
-//..=20
-//.. /* F64 -> I64 */
-//.. /* Sigh, this is an almost exact copy of the F64 -> I32/I1=
6
-//.. case. Unfortunately I see no easy way to avoid the
-//.. duplication. */
-//.. case Iop_F64toI64: {
-//.. HReg rf =3D iselDblExpr(env, e->Iex.Binop.arg2);
-//.. HReg tLo =3D newVRegI32(env);
-//.. HReg tHi =3D newVRegI32(env);
-//..=20
-//.. /* Used several times ... */
-//.. /* Careful ... this sharing is only safe because
-//.. zero_esp/four_esp do not hold any registers which the
-//.. register allocator could attempt to swizzle later. */
-//.. X86AMode* zero_esp =3D X86AMode_IR(0, hregX86_ESP());
-//.. X86AMode* four_esp =3D X86AMode_IR(4, hregX86_ESP());
-//..=20
-//.. /* rf now holds the value to be converted, and rrm hold=
s
-//.. the rounding mode value, encoded as per the
-//.. IRRoundingMode enum. The first thing to do is set t=
he
-//.. FPU's rounding mode accordingly. */
-//..=20
-//.. /* Create a space for the format conversion. */
-//.. /* subl $8, %esp */
-//.. sub_from_esp(env, 8);
-//..=20
-//.. /* Set host rounding mode */
-//.. set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
-//..=20
-//.. /* gistll %rf, 0(%esp) */
-//.. addInstr(env, X86Instr_FpLdStI(False/*store*/, 8, rf, z=
ero_esp));
-//..=20
-//.. /* movl 0(%esp), %dstLo */
-//.. /* movl 4(%esp), %dstHi */
-//.. addInstr(env, X86Instr_Alu32R(
-//.. Xalu_MOV, X86RMI_Mem(zero_esp), tLo));
-//.. addInstr(env, X86Instr_Alu32R(
-//.. Xalu_MOV, X86RMI_Mem(four_esp), tHi));
-//..=20
-//.. /* Restore default FPU rounding. */
-//.. set_FPU_rounding_default( env );
-//..=20
-//.. /* addl $8, %esp */
-//.. add_to_esp(env, 8);
-//..=20
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
-//..=20
-//.. case Iop_Add8x8:
-//.. fn =3D (HWord)h_generic_calc_Add8x8; goto binnish;
-//.. case Iop_Add16x4:
-//.. fn =3D (HWord)h_generic_calc_Add16x4; goto binnish;
-//.. case Iop_Add32x2:
-//.. fn =3D (HWord)h_generic_calc_Add32x2; goto binnish;
-//..=20
-//.. case Iop_Avg8Ux8:
-//.. fn =3D (HWord)h_generic_calc_Avg8Ux8; goto binnish;
-//.. case Iop_Avg16Ux4:
-//.. fn =3D (HWord)h_generic_calc_Avg16Ux4; goto binnish;
-//..=20
-//.. case Iop_CmpEQ8x8:
-//.. fn =3D (HWord)h_generic_calc_CmpEQ8x8; goto binnish;
-//.. case Iop_CmpEQ16x4:
-//.. fn =3D (HWord)h_generic_calc_CmpEQ16x4; goto binnish;
-//.. case Iop_CmpEQ32x2:
-//.. fn =3D (HWord)h_generic_calc_CmpEQ32x2; goto binnish;
-//..=20
-//.. case Iop_CmpGT8Sx8:
-//.. fn =3D (HWord)h_generic_calc_CmpGT8Sx8; goto binnish;
-//.. case Iop_CmpGT16Sx4:
-//.. fn =3D (HWord)h_generic_calc_CmpGT16Sx4; goto binnish;
-//.. case Iop_CmpGT32Sx2:
-//.. fn =3D (HWord)h_generic_calc_CmpGT32Sx2; goto binnish;
-//..=20
-//.. case Iop_InterleaveHI8x8:
-//.. fn =3D (HWord)h_generic_calc_InterleaveHI8x8; goto binn=
ish;
-//.. case Iop_InterleaveLO8x8:
-//.. fn =3D (HWord)h_generic_calc_InterleaveLO8x8; goto binn=
ish;
-//.. case Iop_InterleaveHI16x4:
-//.. fn =3D (HWord)h_generic_calc_InterleaveHI16x4; goto bin=
nish;
-//.. case Iop_InterleaveLO16x4:
-//.. fn =3D (HWord)h_generic_calc_InterleaveLO16x4; goto bin=
nish;
-//.. case Iop_InterleaveHI32x2:
-//.. fn =3D (HWord)h_generic_calc_InterleaveHI32x2; goto bin=
nish;
-//.. case Iop_InterleaveLO32x2:
-//.. fn =3D (HWord)h_generic_calc_InterleaveLO32x2; goto bin=
nish;
-//..=20
-//.. case Iop_Max8Ux8:
-//.. fn =3D (HWord)h_generic_calc_Max8Ux8; goto binnish;
-//.. case Iop_Max16Sx4:
-//.. fn =3D (HWord)h_generic_calc_Max16Sx4; goto binnish;
-//.. case Iop_Min8Ux8:
-//.. fn =3D (HWord)h_generic_calc_Min8Ux8; goto binnish;
-//.. case Iop_Min16Sx4:
-//.. fn =3D (HWord)h_generic_calc_Min16Sx4; goto binnish;
-//..=20
-//.. case Iop_Mul16x4:
-//.. fn =3D (HWord)h_generic_calc_Mul16x4; goto binnish;
-//.. case Iop_MulHi16Sx4:
-//.. fn =3D (HWord)h_generic_calc_MulHi16Sx4; goto binnish;
-//.. case Iop_MulHi16Ux4:
-//.. fn =3D (HWord)h_generic_calc_MulHi16Ux4; goto binnish;
-//..=20
-//.. case Iop_QAdd8Sx8:
-//.. fn =3D (HWord)h_generic_calc_QAdd8Sx8; goto binnish;
-//.. case Iop_QAdd16Sx4:
-//.. fn =3D (HWord)h_generic_calc_QAdd16Sx4; goto binnish;
-//.. case Iop_QAdd8Ux8:
-//.. fn =3D (HWord)h_generic_calc_QAdd8Ux8; goto binnish;
-//.. case Iop_QAdd16Ux4:
-//.. fn =3D (HWord)h_generic_calc_QAdd16Ux4; goto binnish;
-//..=20
-//.. case Iop_QNarrow32Sx2:
-//.. fn =3D (HWord)h_generic_calc_QNarrow32Sx2; goto binnish=
;
-//.. case Iop_QNarrow16Sx4:
-//.. fn =3D (HWord)h_generic_calc_QNarrow16Sx4; goto binnish=
;
-//.. case Iop_QNarrow16Ux4:
-//.. fn =3D (HWord)h_generic_calc_QNarrow16Ux4; goto binnish=
;
-//..=20
-//.. case Iop_QSub8Sx8:
-//.. fn =3D (HWord)h_generic_calc_QSub8Sx8; goto binnish;
-//.. case Iop_QSub16Sx4:
-//.. fn =3D (HWord)h_generic_calc_QSub16Sx4; goto binnish;
-//.. case Iop_QSub8Ux8:
-//.. fn =3D (HWord)h_generic_calc_QSub8Ux8; goto binnish;
-//.. case Iop_QSub16Ux4:
-//.. fn =3D (HWord)h_generic_calc_QSub16Ux4; goto binnish;
-//..=20
-//.. case Iop_Sub8x8:
-//.. fn =3D (HWord)h_generic_calc_Sub8x8; goto binnish;
-//.. case Iop_Sub16x4:
-//.. fn =3D (HWord)h_generic_calc_Sub16x4; goto binnish;
-//.. case Iop_Sub32x2:
-//.. fn =3D (HWord)h_generic_calc_Sub32x2; goto binnish;
-//..=20
-//.. binnish: {
-//.. /* Note: the following assumes all helpers are of
-//.. signature=20
-//.. ULong fn ( ULong, ULong ), and they are
-//.. not marked as regparm functions.=20
-//.. */
-//.. HReg xLo, xHi, yLo, yHi;
-//.. HReg tLo =3D newVRegI32(env);
-//.. HReg tHi =3D newVRegI32(env);
-//.. iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(yHi)));
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(yLo)));
-//.. iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(xHi)));
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(xLo)));
-//.. addInstr(env, X86Instr_Call( Xcc_ALWAYS, (UInt)fn, 0 ))=
;
-//.. add_to_esp(env, 4*4);
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EDX(), tHi));
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EAX(), tLo));
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
-//..=20
-//.. case Iop_ShlN32x2:
-//.. fn =3D (HWord)h_generic_calc_ShlN32x2; goto shifty;
-//.. case Iop_ShlN16x4:
-//.. fn =3D (HWord)h_generic_calc_ShlN16x4; goto shifty;
-//.. case Iop_ShrN32x2:
-//.. fn =3D (HWord)h_generic_calc_ShrN32x2; goto shifty;
-//.. case Iop_ShrN16x4:
-//.. fn =3D (HWord)h_generic_calc_ShrN16x4; goto shifty;
-//.. case Iop_SarN32x2:
-//.. fn =3D (HWord)h_generic_calc_SarN32x2; goto shifty;
-//.. case Iop_SarN16x4:
-//.. fn =3D (HWord)h_generic_calc_SarN16x4; goto shifty;
-//.. shifty: {
-//.. /* Note: the following assumes all helpers are of
-//.. signature=20
-//.. ULong fn ( ULong, UInt ), and they are
-//.. not marked as regparm functions.=20
-//.. */
-//.. HReg xLo, xHi;
-//.. HReg tLo =3D newVRegI32(env);
-//.. HReg tHi =3D newVRegI32(env);
-//.. X86RMI* y =3D iselIntExpr_RMI(env, e->Iex.Binop.arg2);
-//.. addInstr(env, X86Instr_Push(y));
-//.. iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(xHi)));
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(xLo)));
-//.. addInstr(env, X86Instr_Call( Xcc_ALWAYS, (UInt)fn, 0 ))=
;
-//.. add_to_esp(env, 3*4);
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EDX(), tHi));
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EAX(), tLo));
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
-
- default:=20
- break;
+ default:=20
+ break;
}
} /* if (e->tag =3D=3D Iex_Binop) */
=20
@@ -3131,21 +2504,6 @@
return;
}
=20
-//.. /* Not64(e) */
-//.. case Iop_Not64: {
-//.. HReg tLo =3D newVRegI32(env);
-//.. HReg tHi =3D newVRegI32(env);
-//.. HReg sHi, sLo;
-//.. iselInt64Expr(&sHi, &sLo, env, e->Iex.Unop.arg);
-//.. addInstr(env, mk_iMOVsd_RR(sHi, tHi));
-//.. addInstr(env, mk_iMOVsd_RR(sLo, tLo));
-//.. addInstr(env, X86Instr_Unary32(Xun_NOT,X86RM_Reg(tHi)))=
;
-//.. addInstr(env, X86Instr_Unary32(Xun_NOT,X86RM_Reg(tLo)))=
;
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
-
/* ReinterpF64asI64(e) */
/* Given an IEEE754 double, produce an I64 with the same bit
pattern. */
@@ -3175,54 +2533,11 @@
return;
}
=20
-//.. case Iop_CmpNEZ32x2:
-//.. fn =3D (HWord)h_generic_calc_CmpNEZ32x2; goto unish;
-//.. case Iop_CmpNEZ16x4:
-//.. fn =3D (HWord)h_generic_calc_CmpNEZ16x4; goto unish;
-//.. case Iop_CmpNEZ8x8:
-//.. fn =3D (HWord)h_generic_calc_CmpNEZ8x8; goto unish;
-//.. unish: {
-//.. /* Note: the following assumes all helpers are of
-//.. signature=20
-//.. ULong fn ( ULong ), and they are
-//.. not marked as regparm functions.=20
-//.. */
-//.. HReg xLo, xHi;
-//.. HReg tLo =3D newVRegI32(env);
-//.. HReg tHi =3D newVRegI32(env);
-//.. iselInt64Expr(&xHi, &xLo, env, e->Iex.Unop.arg);
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(xHi)));
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(xLo)));
-//.. addInstr(env, X86Instr_Call( Xcc_ALWAYS, (UInt)fn, 0 ))=
;
-//.. add_to_esp(env, 2*4);
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EDX(), tHi));
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EAX(), tLo));
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
-
default:
break;
}
} /* if (e->tag =3D=3D Iex_Unop) */
=20
-
-//.. /* --------- CCALL --------- */
-//.. if (e->tag =3D=3D Iex_CCall) {
-//.. HReg tLo =3D newVRegI32(env);
-//.. HReg tHi =3D newVRegI32(env);
-//..=20
-//.. /* Marshal args, do the call, clear stack. */
-//.. doHelperCall( env, False, NULL, e->Iex.CCall.cee, e->Iex.CCal=
l.args );
-//..=20
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EDX(), tHi));
-//.. addInstr(env, mk_iMOVsd_RR(hregX86_EAX(), tLo));
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
-
vex_printf("iselInt64Expr(ppc): No such tag(%u)\n", e->tag);
ppIRExpr(e);
vpanic("iselInt64Expr(ppc)");
@@ -3287,21 +2602,6 @@
return r_dst;
}
=20
-//.. if (e->tag =3D=3D Iex_Unop
-//.. && e->Iex.Unop.op =3D=3D Iop_ReinterpI32asF32) {
-//.. /* Given an I32, produce an IEEE754 float with the same bit
-//.. pattern. */
-//.. HReg dst =3D newVRegF(env);
-//.. X86RMI* rmi =3D iselIntExpr_RMI(env, e->Iex.Unop.arg);
-//.. /* paranoia */
-//.. addInstr(env, X86Instr_Push(rmi));
-//.. addInstr(env, X86Instr_FpLdSt(
-//.. True/*load*/, 4, dst,
-//.. X86AMode_IR(0, hregX86_ESP())));
-//.. add_to_esp(env, 4);
-//.. return dst;
-//.. }
-
vex_printf("iselFltExpr(ppc): No such tag(%u)\n", e->tag);
ppIRExpr(e);
vpanic("iselFltExpr_wrk(ppc)");
@@ -3405,16 +2705,6 @@
return r_dst;
}
=20
-//.. if (e->tag =3D=3D Iex_GetI) {
-//.. X86AMode* am=20
-//.. =3D genGuestArrayOffset(
-//.. env, e->Iex.GetI.descr,=20
-//.. e->Iex.GetI.ix, e->Iex.GetI.bias );
-//.. HReg res =3D newVRegF(env);
-//.. addInstr(env, X86Instr_FpLdSt( True/*load*/, 8, res, am ));
-//.. return res;
-//.. }
-
if (e->tag =3D=3D Iex_Binop) {
PPCFpOp fpop =3D Pfp_INVALID;
switch (e->Iex.Binop.op) {
@@ -3450,107 +2740,44 @@
}
}
=20
-//.. if (e->tag =3D=3D Iex_Binop && e->Iex.Binop.op =3D=3D Iop_RoundF=
64) {
-//.. HReg rf =3D iselDblExpr(env, e->Iex.Binop.arg2);
-//.. HReg dst =3D newVRegF(env);
-//..=20
-//.. /* rf now holds the value to be rounded. The first thing to =
do
-//.. is set the FPU's rounding mode accordingly. */
-//..=20
-//.. /* Set host rounding mode */
-//.. set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
-//..=20
-//.. /* grndint %rf, %dst */
-//.. addInstr(env, X86Instr_FpUnary(Xfp_ROUND, rf, dst));
-//..=20
-//.. /* Restore default FPU rounding. */
-//.. set_FPU_rounding_default( env );
-//..=20
-//.. return dst;
-//.. }
-
-//.. if (e->tag =3D=3D Iex_Binop && e->Iex.Binop.op =3D=3D Iop_I64toF=
64) {
-//.. HReg fr_dst =3D newVRegF(env);
-//.. HReg rHi,rLo;
-//.. iselInt64Expr( &rHi, &rLo, env, e->Iex.Binop.arg2);
-//.. addInstr(env, PPCInstr_Push(PPCRMI_Reg(rHi)));
-//.. addInstr(env, PPCInstr_Push(PPCRMI_Reg(rLo)));
-//..=20
-//.. /* Set host rounding mode */
-//.. set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
-//..=20
-//.. PPCAMode* am_addr =3D ...
-//.. addInstr(env, PPCInstr_FpLdSt( True/*load*/, 8, r_dst,
-//.. PPCAMode_IR(0, GuestStatePtr=
) ));
-//..=20
-//..=20
-//.. addInstr(env, PPCInstr_FpLdStI(
-//.. True/*load*/, 8, fr_dst,=20
-//.. PPCAMode_IR(0, hregPPC_ESP())));
-//..=20
-//.. /* Restore default FPU rounding. */
-//.. set_FPU_rounding_default( env );
-//..=20
-//.. add_to_esp(env, 8);
-//.. return fr_dst;
-//.. }
-
if (e->tag =3D=3D Iex_Unop) {
PPCFpOp fpop =3D Pfp_INVALID;
switch (e->Iex.Unop.op) {
case Iop_NegF64: fpop =3D Pfp_NEG; break;
case Iop_AbsF64: fpop =3D Pfp_ABS; break;
case Iop_SqrtF64: fpop =3D Pfp_SQRT; break;
-//.. case Iop_SinF64: fpop =3D Xfp_SIN; break;
-//.. case Iop_CosF64: fpop =3D Xfp_COS; break;
-//.. case Iop_TanF64: fpop =3D Xfp_TAN; break;
-//.. case Iop_2xm1F64: fpop =3D Xfp_2XM1; break;
default: break;
}
if (fpop !=3D Pfp_INVALID) {
HReg fr_dst =3D newVRegF(env);
HReg fr_src =3D iselDblExpr(env, e->Iex.Unop.arg);
addInstr(env, PPCInstr_FpUnary(fpop, fr_dst, fr_src));
-//.. if (fpop !=3D Pfp_SQRT && fpop !=3D Xfp_NEG && fpop !=3D Xf=
p_ABS)
-//.. roundToF64(env, fr_dst);
return fr_dst;
}
}
=20
if (e->tag =3D=3D Iex_Unop) {
switch (e->Iex.Unop.op) {
-//.. case Iop_I32toF64: {
-//.. HReg dst =3D newVRegF(env);
-//.. HReg ri =3D iselIntExpr_R(env, e->Iex.Unop.arg);
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(ri)));
-//.. set_FPU_rounding_default(env);
-//.. addInstr(env, X86Instr_FpLdStI(
-//.. True/*load*/, 4, dst,=20
-//.. X86AMode_IR(0, hregX86_ESP())));
-//.. add_to_esp(env, 4);
-//.. return dst;
-//.. }
-
- case Iop_ReinterpI64asF64: {
- /* Given an I64, produce an IEEE754 double with the same
- bit pattern. */
- if (!mode64) {
- HReg r_srcHi, r_srcLo;
- iselInt64Expr( &r_srcHi, &r_srcLo, env, e->Iex.Unop.arg);
- return mk_LoadRR32toFPR( env, r_srcHi, r_srcLo );
- } else {
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- return mk_LoadR64toFPR( env, r_src );
+ case Iop_ReinterpI64asF64: {
+ /* Given an I64, produce an IEEE754 double with the same
+ bit pattern. */
+ if (!mode64) {
+ HReg r_srcHi, r_srcLo;
+ iselInt64Expr( &r_srcHi, &r_srcLo, env, e->Iex.Unop.arg);
+ return mk_LoadRR32toFPR( env, r_srcHi, r_srcLo );
+ } else {
+ HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ return mk_LoadR64toFPR( env, r_src );
+ }
}
+ case Iop_F32toF64: {
+ /* this is a no-op */
+ HReg res =3D iselFltExpr(env, e->Iex.Unop.arg);
+ return res;
+ }
+ default:=20
+ break;
}
- case Iop_F32toF64: {
- /* this is a no-op */
- HReg res =3D iselFltExpr(env, e->Iex.Unop.arg);
- return res;
- }
- default:=20
- break;
- }
}
=20
/* --------- MULTIPLEX --------- */
@@ -3598,7 +2825,6 @@
static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
{
Bool mode64 =3D env->mode64;
-//.. Bool arg1isEReg =3D False;
PPCAvOp op =3D Pav_INVALID;
IRType ty =3D typeOfIRExpr(env->type_env,e);
vassert(e);
@@ -3628,13 +2854,6 @@
return v_dst;
}
=20
-//.. if (e->tag =3D=3D Iex_Const) {
-//.. HReg dst =3D newVRegV(env);
-//.. vassert(e->Iex.Const.con->tag =3D=3D Ico_V128);
-//.. addInstr(env, X86Instr_SseConst(e->Iex.Const.con->Ico.V128, d=
st));
-//.. return dst;
-//.. }
-
if (e->tag =3D=3D Iex_Unop) {
switch (e->Iex.Unop.op) {
=20
@@ -3645,34 +2864,6 @@
return dst;
}
=20
-//.. case Iop_CmpNEZ64x2: {
-//.. /* We can use SSE2 instructions for this. */
-//.. /* Ideally, we want to do a 64Ix2 comparison against zero =
of
-//.. the operand. Problem is no such insn exists. Solution
-//.. therefore is to do a 32Ix4 comparison instead, and bitw=
ise-
-//.. negate (NOT) the result. Let a,b,c,d be 32-bit lanes, =
and=20
-//.. let the not'd result of this initial comparison be a:b:=
c:d.
-//.. What we need to compute is (a|b):(a|b):(c|d):(c|d). So=
, use
-//.. pshufd to create a value b:a:d:c, and OR that with a:b:=
c:d,
-//.. giving the required result.
-//..=20
-//.. The required selection sequence is 2,3,0,1, which
-//.. according to Intel's documentation means the pshufd
-//.. literal value is 0xB1, that is,=20
-//.. (2 << 6) | (3 << 4) | (0 << 2) | (1 << 0)=20
-//.. */
-//.. HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
-//.. HReg tmp =3D newVRegV(env);
-//.. HReg dst =3D newVRegV(env);
-//.. REQUIRE_SSE2;
-//.. addInstr(env, X86Instr_SseReRg(Xsse_XOR, tmp, tmp));
-//.. addInstr(env, X86Instr_SseReRg(Xsse_CMPEQ32, arg, tmp));
-//.. tmp =3D do_sse_Not128(env, tmp);
-//.. addInstr(env, X86Instr_SseShuf(0xB1, tmp, dst));
-//.. addInstr(env, X86Instr_SseReRg(Xsse_OR, tmp, dst));
-//.. return dst;
-//.. }
-
case Iop_CmpNEZ8x16: {
HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
HReg zero =3D newVRegV(env);
@@ -3703,42 +2894,16 @@
return dst;
}
=20
-//.. case Iop_CmpNEZ16x8: {
-//.. /* We can use SSE2 instructions for this. */
-//.. HReg arg;
-//.. HReg vec0 =3D newVRegV(env);
-//.. HReg vec1 =3D newVRegV(env);
-//.. HReg dst =3D newVRegV(env);
-//.. X86SseOp cmpOp=20
-//.. =3D e->Iex.Unop.op=3D=3DIop_CmpNEZ16x8 ? Xsse_CMPEQ16
-//.. : Xsse_CMPEQ8;
-//.. REQUIRE_SSE2;
-//.. addInstr(env, X86Instr_SseReRg(Xsse_XOR, vec0, vec0));
-//.. addInstr(env, mk_vMOVsd_RR(vec0, vec1));
-//.. addInstr(env, X86Instr_Sse32Fx4(Xsse_CMPEQF, vec1, vec1));
-//.. /* defer arg computation to here so as to give CMPEQF as l=
ong
-//.. as possible to complete */
-//.. arg =3D iselVecExpr(env, e->Iex.Unop.arg);
-//.. /* vec0 is all 0s; vec1 is all 1s */
-//.. addInstr(env, mk_vMOVsd_RR(arg, dst));
-//.. /* 16x8 or 8x16 comparison =3D=3D */
-//.. addInstr(env, X86Instr_SseReRg(cmpOp, vec0, dst));
-//.. /* invert result */
-//.. addInstr(env, X86Instr_SseReRg(Xsse_XOR, vec1, dst));
-//.. return dst;
-//.. }
-
- case Iop_Recip32Fx4: op =3D Pavfp_RCPF; goto do_32Fx4_unary;
- case Iop_RSqrt32Fx4: op =3D Pavfp_RSQRTF; goto do_32Fx4_unary;
-//.. case Iop_Sqrt32Fx4: op =3D Xsse_SQRTF; goto do_32Fx4_unary;
+ case Iop_Recip32Fx4: op =3D Pavfp_RCPF; goto do_32Fx4_unary;
+ case Iop_RSqrt32Fx4: op =3D Pavfp_RSQRTF; goto do_32Fx4_unary;
case Iop_I32UtoFx4: op =3D Pavfp_CVTU2F; goto do_32Fx4_unary;
case Iop_I32StoFx4: op =3D Pavfp_CVTS2F; goto do_32Fx4_unary;
case Iop_QFtoI32Ux4_RZ: op =3D Pavfp_QCVTF2U; goto do_32Fx4_unary;
case Iop_QFtoI32Sx4_RZ: op =3D Pavfp_QCVTF2S; goto do_32Fx4_unary;
- case Iop_RoundF32x4_RM: op =3D Pavfp_ROUNDM; goto do_32Fx4_unar=
y;
- case Iop_RoundF32x4_RP: op =3D Pavfp_ROUNDP; goto do_32Fx4_unar=
y;
- case Iop_RoundF32x4_RN: op =3D Pavfp_ROUNDN; goto do_32Fx4_unar=
y;
- case Iop_RoundF32x4_RZ: op =3D Pavfp_ROUNDZ; goto do_32Fx4_unar=
y;
+ case Iop_RoundF32x4_RM: op =3D Pavfp_ROUNDM; goto do_32Fx4_unary;
+ case Iop_RoundF32x4_RP: op =3D Pavfp_ROUNDP; goto do_32Fx4_unary;
+ case Iop_RoundF32x4_RN: op =3D Pavfp_ROUNDN; goto do_32Fx4_unary;
+ case Iop_RoundF32x4_RZ: op =3D Pavfp_ROUNDZ; goto do_32Fx4_unary;
do_32Fx4_unary:
{
HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
@@ -3747,55 +2912,6 @@
return dst;
}
=20
-//.. case Iop_Recip64Fx2: op =3D Xsse_RCPF; goto do_64Fx2_unary;
-//.. case Iop_RSqrt64Fx2: op =3D Xsse_RSQRTF; goto do_64Fx2_unary;
-//.. case Iop_Sqrt64Fx2: op =3D Xsse_SQRTF; goto do_64Fx2_unary;
-//.. do_64Fx2_unary:
-//.. {
-//.. HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
-//.. HReg dst =3D newVRegV(env);
-//.. REQUIRE_SSE2;
-//.. addInstr(env, X86Instr_Sse64Fx2(op, arg, dst));
-//.. return dst;
-//.. }
-//..=20
-//.. case Iop_Recip32F0x4: op =3D Xsse_RCPF; goto do_32F0x4_unar=
y;
-//.. case Iop_RSqrt32F0x4: op =3D Xsse_RSQRTF; goto do_32F0x4_unar=
y;
-//.. case Iop_Sqrt32F0x4: op =3D Xsse_SQRTF; goto do_32F0x4_unar=
y;
-//.. do_32F0x4_unary:
-//.. {
-//.. /* A bit subtle. We have to copy the arg to the result
-//.. register first, because actually doing the SSE scalar i=
nsn
-//.. leaves the upper 3/4 of the destination register
-//.. unchanged. Whereas the required semantics of these
-//.. primops is that the upper 3/4 is simply copied in from =
the
-//.. argument. */
-//.. HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
-//.. HReg dst =3D newVRegV(env);
-//.. addInstr(env, mk_vMOVsd_RR(arg, dst));
-//.. addInstr(env, X86Instr_Sse32FLo(op, arg, dst));
-//.. return dst;
-//.. }
-//..=20
-//.. case Iop_Recip64F0x2: op =3D Xsse_RCPF; goto do_64F0x2_unar=
y;
-//.. case Iop_RSqrt64F0x2: op =3D Xsse_RSQRTF; goto do_64F0x2_unar=
y;
-//.. case Iop_Sqrt64F0x2: op =3D Xsse_SQRTF; goto do_64F0x2_unar=
y;
-//.. do_64F0x2_unary:
-//.. {
-//.. /* A bit subtle. We have to copy the arg to the result
-//.. register first, because actually doing the SSE scalar i=
nsn
-//.. leaves the upper half of the destination register
-//.. unchanged. Whereas the required semantics of these
-//.. primops is that the upper half is simply copied in from=
the
-//.. argument. */
-//.. HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
-//.. HReg dst =3D newVRegV(env);
-//.. REQUIRE_SSE2;
-//.. addInstr(env, mk_vMOVsd_RR(arg, dst));
-//.. addInstr(env, X86Instr_Sse64FLo(op, arg, dst));
-//.. return dst;
-//.. }
-
case Iop_32UtoV128: {
HReg r_aligned16, r_zeros;
HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
@@ -3827,18 +2943,6 @@
return dst;
}
=20
-//.. case Iop_64UtoV128: {
-//.. HReg rHi, rLo;
-//.. HReg dst =3D newVRegV(env);
-//.. X86AMode* esp0 =3D X86AMode_IR(0, hregX86_ESP());
-//.. iselInt64Expr(&rHi, &rLo, env, e->Iex.Unop.arg);
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(rHi)));
-//.. addInstr(env, X86Instr_Push(X86RMI_Reg(rLo)));
-//.. addInstr(env, X86Instr_SseLdzLO(8, dst, esp0));
-//.. add_to_esp(env, 8);
-//.. return dst;
-//.. }
-
case Iop_Dup8x16:
case Iop_Dup16x8:
case Iop_Dup32x4:
@@ -3852,35 +2956,6 @@
if (e->tag =3D=3D Iex_Binop) {
switch (e->Iex.Binop.op) {
=20
-//.. case Iop_SetV128lo32: {
-//.. HReg dst =3D newVRegV(env);
-//.. HReg srcV =3D iselVecExpr(env, e->Iex.Binop.arg1);
-//.. HReg srcI =3D iselIntExpr_R(env, e->Iex.Binop.arg2);
-//.. X86AMode* esp0 =3D X86AMode_IR(0, hregX86_ESP());
-//.. sub_from_esp(env, 16);
-//.. addInstr(env, X86Instr_SseLdSt(False/*store*/, srcV, esp0)=
);
-//.. addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(srcI), e=
sp0));
-//.. addInstr(env, X86Instr_SseLdSt(True/*load*/, dst, esp0));
-//.. add_to_esp(env, 16);
-//.. return dst;
-//.. }
-//..=20
-//.. case Iop_SetV128lo64: {
-//.. HReg dst =3D newVRegV(env);
-//.. HReg srcV =3D iselVecExpr(env, e->Iex.Binop.arg1);
-//.. HReg srcIhi, srcIlo;
-//.. X86AMode* esp0 =3D X86AMode_IR(0, hregX86_ESP());
-//.. X86AMode* esp4 =3D advance4(esp0);
-//.. iselInt64Expr(&srcIhi, &srcIlo, env, e->Iex.Binop.arg2);
-//.. sub_from_esp(env, 16);
-//.. addInstr(env, X86Instr_SseLdSt(False/*store*/, srcV, esp0)=
);
-//.. addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(srcIlo),=
esp0));
-//.. addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(srcIhi),=
esp4));
-//.. addInstr(env, X86Instr_SseLdSt(True/*load*/, dst, esp0));
-//.. add_to_esp(env, 16);
-//.. return dst;
-//.. }
-//..=20
case Iop_64HLtoV128: {
if (!mode64) {
HReg r3, r2, r1, r0, r_aligned16;
@@ -3941,11 +3016,9 @@
case Iop_Max32Fx4: op =3D Pavfp_MAXF; goto do_32Fx4;
case Iop_Min32Fx4: op =3D Pavfp_MINF; goto do_32Fx4;
case Iop_Mul32Fx4: op =3D Pavfp_MULF; goto do_32Fx4;
-//.. case Iop_Div32Fx4: op =3D Xsse_DIVF; goto do_32Fx4;
case Iop_CmpEQ32Fx4: op =3D Pavfp_CMPEQF; goto do_32Fx4;
case Iop_CmpGT32Fx4: op =3D Pavfp_CMPGTF; goto do_32Fx4;
case Iop_CmpGE32Fx4: op =3D Pavfp_CMPGEF; goto do_32Fx4;
-//.. case Iop_CmpLT32Fx4:
do_32Fx4:
{
HReg argL =3D iselVecExpr(env, e->Iex.Binop.arg1);
@@ -3977,63 +3050,6 @@
return dst;
}
=20
-//.. case Iop_CmpEQ64Fx2: op =3D Xsse_CMPEQF; goto do_64Fx2;
-//.. case Iop_CmpLT64Fx2: op =3D Xsse_CMPLTF; goto do_64Fx2;
-//.. case Iop_CmpLE64Fx2: op =3D Xsse_CMPLEF; goto do_64Fx2;
-//.. case Iop_Add64Fx2: op =3D Xsse_ADDF; goto do_64Fx2;
-//.. case Iop_Div64Fx2: op =3D Xsse_DIVF; goto do_64Fx2;
-//.. case Iop_Max64Fx2: op =3D Xsse_MAXF; goto do_64Fx2;
-//.. case Iop_Min64Fx2: op =3D Xsse_MINF; goto do_64Fx2;
-//.. case Iop_Mul64Fx2: op =3D Xsse_MULF; goto do_64Fx2;
-//.. case Iop_Sub64Fx2: op =3D Xsse_SUBF; goto do_64Fx2;
-//.. do_64Fx2:
-//.. {
-//.. HReg argL =3D iselVecExpr(env, e->Iex.Binop.arg1);
-//.. HReg argR =3D iselVecExpr(env, e->Iex.Binop.arg2);
-//.. HReg dst =3D newVRegV(env);
-//.. REQUIRE_SSE2;
-//.. addInstr(env, mk_vMOVsd_RR(argL, dst));
-//.. addInstr(env, X86Instr_Sse64Fx2(op, argR, dst));
-//.. return dst;
-//.. }
-
-//.. case Iop_CmpEQ32F0x4: op =3D Xsse_CMPEQF; goto do_32F0x4;
-//.. case Iop_CmpLT32F0x4: op =3D Xsse_CMPLTF; goto do_32F0x4;
-//.. case Iop_CmpLE32F0x4: op =3D Xsse_CMPLEF; goto do_32F0x4;
-//.. case Iop_Add32F0x4: op =3D Xsse_ADDF; goto do_32F0x4;
-//.. case Iop_Div32F0x4: op =3D Xsse_DIVF; goto do_32F0x4;
-//.. case Iop_Max32F0x4: op =3D Xsse_MAXF; goto do_32F0x4;
-//.. case Iop_Min32F0x4: op =3D Xsse_MINF; goto do_32F0x4;
-//.. case Iop_Mul32F0x4: op =3D Xsse_MULF; goto do_32F0x4;
-//.. case Iop_Sub32F0x4: op =3D Xsse_SUBF; goto do_32F0x4;
-//.. do_32F0x4: {
-//.. HReg argL =3D iselVecExpr(env, e->Iex.Binop.arg1);
-//.. HReg argR =3D iselVecExpr(env, e->Iex.Binop.arg2);
-//.. HReg dst =3D newVRegV(env);
-//.. addInstr(env, mk_vMOVsd_RR(argL, dst));
-//.. addInstr(env, X86Instr_Sse32FLo(op, argR, dst));
-//.. return dst;
-//.. }
-
-//.. case Iop_CmpEQ64F0x2: op =3D Xsse_CMPEQF; goto do_64F0x2;
-//.. case Iop_CmpLT64F0x2: op =3D Xsse_CMPLTF; goto do_64F0x2;
-//.. case Iop_CmpLE64F0x2: op =3D Xsse_CMPLEF; goto do_64F0x2;
-//.. case Iop_Add64F0x2: op =3D Xsse_ADDF; goto do_64F0x2;
-//.. case Iop_Div64F0x2: op =3D Xsse_DIVF; goto do_64F0x2;
-//.. case Iop_Max64F0x2: op =3D Xsse_MAXF; goto do_64F0x2;
-//.. case Iop_Min64F0x2: op =3D Xsse_MINF; goto do_64F0x2;
-//.. case Iop_Mul64F0x2: op =3D Xsse_MULF; goto do_64F0x2;
-//.. case Iop_Sub64F0x2: op =3D Xsse_SUBF; goto do_64F0x2;
-//.. do_64F0x2: {
-//.. HReg argL =3D iselVecExpr(env, e->Iex.Binop.arg1);
-//.. HReg argR =3D iselVecExpr(env, e->Iex.Binop.arg2);
-//.. HReg dst =3D newVRegV(env);
-//.. REQUIRE_SSE2;
-//.. addInstr(env, mk_vMOVsd_RR(argL, dst));
-//.. addInstr(env, X86Instr_Sse64FLo(op, argR, dst));
-//.. return dst;
-//.. }
-
case Iop_AndV128: op =3D Pav_AND; goto do_AvBin;
case Iop_OrV128: op =3D Pav_OR; goto do_AvBin;
case Iop_XorV128: op =3D Pav_XOR; goto do_AvBin;
@@ -4045,8 +3061,6 @@
return dst;
}
=20
-//.. case Iop_Mul16x8: op =3D Xsse_MUL16; goto do_SseReRg;
-
case Iop_Shl8x16: op =3D Pav_SHL; goto do_AvBin8x16;
case Iop_Shr8x16: op =3D Pav_SHR; goto do_AvBin8x16;
case Iop_Sar8x16: op =3D Pav_SAR; goto do_AvBin8x16;
@@ -4200,18 +3214,6 @@
} /* switch (e->Iex.Binop.op) */
} /* if (e->tag =3D=3D Iex_Binop) */
=20
-//.. if (e->tag =3D=3D Iex_Mux0X) {
-//.. HReg r8 =3D iselIntExpr_R(env, e->Iex.Mux0X.cond);
-//.. HReg rX =3D iselVecExpr(env, e->Iex.Mux0X.exprX);
-//.. HReg r0 =3D iselVecExpr(env, e->Iex.Mux0X.expr0);
-//.. HReg dst =3D newVRegV(env);
-//.. addInstr(env, mk_vMOVsd_RR(rX,dst));
-//.. addInstr(env, X86Instr_Test32(X86RI_Imm(0xFF), X86RM_Reg(r8))=
);
-//.. addInstr(env, X86Instr_SseCMov(Xcc_Z,r0,dst));
-//.. return dst;
-//.. }
-
- // unused: vec_fail:
vex_printf("iselVecExpr(ppc) (subarch =3D %s): can't reduce\n",
LibVEX_ppVexSubArch(env->subarch));
ppIRExpr(e);
@...
[truncated message content] |
|
From: <sv...@va...> - 2006-01-24 19:00:13
|
Author: sewardj
Date: 2006-01-24 19:00:05 +0000 (Tue, 24 Jan 2006)
New Revision: 1546
Log:
Minor tweaks to handle instructions created by xlc 7.0.
Modified:
trunk/priv/guest-ppc/toIR.c
Modified: trunk/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/toIR.c 2006-01-24 03:33:43 UTC (rev 1545)
+++ trunk/priv/guest-ppc/toIR.c 2006-01-24 19:00:05 UTC (rev 1546)
@@ -4273,8 +4273,11 @@
break;
=20
case 0x13:
- if (b11to15!=3D0) {
- vex_printf("dis_int_branch(ppc)(0x13,b11to15)\n");
+ /* For bclr and bcctr, it appears that the lowest two bits of
+ b11to15 are a branch hint, and so we only need to ensure it's
+ of the form 000XX. */
+ if ((b11to15 & ~3) !=3D 0) {
+ vex_printf("dis_int_branch(ppc)(0x13,b11to15)(%d)\n", (Int)b11t=
o15);
return False;
}
=20
@@ -5214,7 +5217,18 @@
=20
IRType ty =3D mode64 ? Ity_I64 : Ity_I32;
=20
+ /* For dcbt, the lowest two bits of b21to25 encode an
+ access-direction hint (TH field) which we ignore. Well, that's
+ what the PowerPC documentation says. In fact xlc -O4 on POWER5
+ seems to generate values of 8 and 10 for b21to25. */
+ if (opc1 =3D=3D 0x1F && opc2 =3D=3D 0x116) {
+ /* b21to25 &=3D ~3; */ /* if the docs were true */
+ b21to25 =3D 0; /* blunt instrument */
+ }
+
if (opc1 !=3D 0x1F || b21to25 !=3D 0 || b0 !=3D 0) {
+ if (0) vex_printf("dis_cache_manage %d %d %d\n",=20
+ (Int)opc1, (Int)b21to25, (Int)b0);
vex_printf("dis_cache_manage(ppc)(opc1|b21to25|b0)\n");
return False;
}
@@ -5232,7 +5246,6 @@
case 0x056: // dcbf (Data Cache Block Flush, PPC32 p382)
DIP("dcbf r%u,r%u\n", rA_addr, rB_addr);
/* nop as far as vex is concerned */
- if (0) vex_printf("vex ppc->IR: kludged dcbf\n");
break;
=20
case 0x036: // dcbst (Data Cache Block Store, PPC32 p384)
@@ -6062,13 +6075,11 @@
=20
case 0x00F: // fctiwz (Float Conv to Int, Round to Zero, PPC32 p405)
DIP("fctiwz%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr);
- assign( r_tmp32, binop(Iop_F64toI32, mkU32(0x3), mkexpr(frB)) );
+ assign( r_tmp32, binop(Iop_F64toI32, mkU32(Irrm_ZERO), mkexpr(frB)=
) );
assign( frD, unop( Iop_ReinterpI64asF64,
unop( Iop_32Uto64, mkexpr(r_tmp32))));
break;
=20
-
- /* 64bit FP conversions */
case 0x32E: // fctid (Float Conv to Int DWord, PPC64 p437)
DIP("fctid%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr);
assign( r_tmp64,
@@ -6078,7 +6089,7 @@
=20
case 0x32F: // fctidz (Float Conv to Int DWord, Round to Zero, PPC64 =
p437)
DIP("fctidz%s fr%u,fr%u\n", flag_rC ? ".":"", frD_addr, frB_addr);
- assign( r_tmp64, binop(Iop_F64toI64, mkU32(0x3), mkexpr(frB)) );
+ assign( r_tmp64, binop(Iop_F64toI64, mkU32(Irrm_ZERO), mkexpr(frB)=
) );
assign( frD, unop( Iop_ReinterpI64asF64, mkexpr(r_tmp64)) );
break;
=20
@@ -8645,6 +8656,9 @@
case 0x00C: // frsp
case 0x00E: // fctiw
case 0x00F: // fctiwz
+ case 0x32E: // fctid
+ case 0x32F: // fctidz
+ case 0x34E: // fcfid
if (dis_fp_round(theInstr)) goto decode_success;
goto decode_failure;
=20
@@ -8658,7 +8672,7 @@
=20
/* Floating Point Status/Control Register Instructions */ =20
case 0x026: // mtfsb1
-//zz case 0x040: // mcrfs
+ /* case 0x040: // mcrfs */
case 0x046: // mtfsb0
case 0x086: // mtfsfi
case 0x247: // mffs
@@ -8666,14 +8680,6 @@
if (dis_fp_scr( theInstr )) goto decode_success;
goto decode_failure;
=20
- /* 64bit FP conversions */
- case 0x32E: // fctid
- case 0x32F: // fctidz
- case 0x34E: // fcfid
- if (!mode64) goto decode_failure;
- if (dis_fp_round(theInstr)) goto decode_success;
- goto decode_failure;
-
default:
goto decode_failure;
}
|
|
From: <sv...@va...> - 2006-01-24 18:50:53
|
Author: sewardj
Date: 2006-01-24 18:50:38 +0000 (Tue, 24 Jan 2006)
New Revision: 5592
Log:
Don't build the Altivec constant tables unless Altivec instruction
tests have been requested.
Modified:
trunk/none/tests/ppc32/jm-insns.c
Modified: trunk/none/tests/ppc32/jm-insns.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/jm-insns.c 2006-01-24 01:01:17 UTC (rev 5591)
+++ trunk/none/tests/ppc32/jm-insns.c 2006-01-24 18:50:38 UTC (rev 5592)
@@ -4107,18 +4107,19 @@
static int verbose =3D 0;
static int arg_list_size =3D 0;
=20
-static double *fargs;
-static int nb_fargs;
-static int nb_normal_fargs;
-static HWord_t *iargs;
-static int nb_iargs;
-static uint16_t *ii16;
-static int nb_ii16;
+static double *fargs =3D NULL;
+static int nb_fargs =3D 0;
+static int nb_normal_fargs =3D 0;
+static HWord_t *iargs =3D NULL;
+static int nb_iargs =3D 0;
+static uint16_t *ii16 =3D NULL;
+static int nb_ii16 =3D 0;
+
#if defined (HAS_ALTIVEC)
-static vector unsigned int* viargs;
-static int nb_viargs;
-static vector float* vfargs;
-static int nb_vfargs;
+static vector unsigned int* viargs =3D NULL;
+static int nb_viargs =3D 0;
+static vector float* vfargs =3D NULL;
+static int nb_vfargs =3D 0;
=20
//#define TEST_VSCR_SAT
#endif
@@ -8399,8 +8400,10 @@
build_fargs_table();
build_ii16_table();
#if defined (HAS_ALTIVEC)
- build_viargs_table();
- build_vfargs_table();
+ if (flags.altivec || flags.faltivec) {
+ build_viargs_table();
+ build_vfargs_table();
+ }
#endif
// dump_iargs();
// dump_iargs16();
|
|
From: <js...@ac...> - 2006-01-24 10:25:20
|
Nightly build on minnie ( SuSE 10.0, ppc32 ) started at 2006-01-24 05:00:01 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 188 tests, 10 stderr failures, 2 stdout failures ================= memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/mempool (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigaltstack (stderr) memcheck/tests/stack_changes (stdout) memcheck/tests/stack_changes (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/mremap (stderr) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-fp (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 187 tests, 10 stderr failures, 3 stdout failures ================= memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/mempool (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigaltstack (stderr) memcheck/tests/stack_changes (stdout) memcheck/tests/stack_changes (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/mremap (stderr) none/tests/ppc32/jm-fp (stdout) none/tests/ppc32/jm-fp (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Tue Jan 24 05:10:24 2006 --- new.short Tue Jan 24 05:20:38 2006 *************** *** 8,13 **** ! == 187 tests, 10 stderr failures, 3 stdout failures ================= memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) - memcheck/tests/leakotron (stdout) memcheck/tests/mempool (stderr) --- 8,12 ---- ! == 188 tests, 10 stderr failures, 2 stdout failures ================= memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/mempool (stderr) |
|
From: David K. <dw...@gm...> - 2006-01-24 06:08:37
|
On 1/23/06, Nicholas Nethercote <nj...@cs...> wrote: > On Sun, 22 Jan 2006, David Kimdon wrote: > The good news is you've made a good start! Thanks for the support :-) > > The bad news is that I have a 90%-complete implementation already. It's That's actually good news too, depending on how we look at it, I wasn't really looking forward to doing all the load/store routines . . . > in the COMPVBITS branch (use svn co > svn://svn.valgrind.org/valgrind/branches/COMPVBITS to check it out). > It's actually quite a bit faster (typically 15%-ish?) than the current > head, because the fast cases are more streamlined. The plan is to merge > it into the trunk fairly soon. cool, I will take a look. > Looking at your code, I see you have one secondary V bits table per > SecMap, which is an interesting idea; I have a single table for > everything. Your approach makes for faster lookups, but the garbage > collection of stale nodes becomes more complicated... hmm, interesting. I wonder if we even need to collect them. In my current implementation I never remove from the OSet. The nodes _could_ be removed when the avbits changed to allow it, but are there so few of them that we can just leave them to rot? |
|
From: <js...@ac...> - 2006-01-24 04:01:22
|
Nightly build on phoenix ( SuSE 10.0 ) started at 2006-01-24 03:30:01 GMT Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 221 tests, 7 stderr failures, 0 stdout failures ================= memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 219 tests, 7 stderr failures, 0 stdout failures ================= memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Tue Jan 24 03:46:29 2006 --- new.short Tue Jan 24 04:02:01 2006 *************** *** 10,12 **** ! == 219 tests, 7 stderr failures, 0 stdout failures ================= memcheck/tests/leak-tree (stderr) --- 10,12 ---- ! == 221 tests, 7 stderr failures, 0 stdout failures ================= memcheck/tests/leak-tree (stderr) |
|
From: <js...@ac...> - 2006-01-24 03:56:47
|
Nightly build on g5 ( YDL 4.0, ppc970 ) started at 2006-01-24 04:40:01 CET Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 191 tests, 6 stderr failures, 1 stdout failure ================= memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_fcntl (stderr) none/tests/mremap (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 190 tests, 6 stderr failures, 1 stdout failure ================= memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_fcntl (stderr) none/tests/mremap (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Tue Jan 24 04:48:19 2006 --- new.short Tue Jan 24 04:56:40 2006 *************** *** 8,10 **** ! == 190 tests, 6 stderr failures, 1 stdout failure ================= memcheck/tests/leak-cycle (stderr) --- 8,10 ---- ! == 191 tests, 6 stderr failures, 1 stdout failure ================= memcheck/tests/leak-cycle (stderr) |
|
From: Tom H. <to...@co...> - 2006-01-24 03:44:47
|
Nightly build on dunsmere ( athlon, Fedora Core 4 ) started at 2006-01-24 03:30:05 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 223 tests, 8 stderr failures, 1 stdout failure ================= memcheck/tests/leak-tree (stderr) memcheck/tests/mempool (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 221 tests, 8 stderr failures, 1 stdout failure ================= memcheck/tests/leak-tree (stderr) memcheck/tests/mempool (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Tue Jan 24 03:37:25 2006 --- new.short Tue Jan 24 03:44:36 2006 *************** *** 8,10 **** ! == 221 tests, 8 stderr failures, 1 stdout failure ================= memcheck/tests/leak-tree (stderr) --- 8,10 ---- ! == 223 tests, 8 stderr failures, 1 stdout failure ================= memcheck/tests/leak-tree (stderr) |
|
From: <sv...@va...> - 2006-01-24 03:33:50
|
Author: sewardj
Date: 2006-01-24 03:33:43 +0000 (Tue, 24 Jan 2006)
New Revision: 1545
Log:
Re-enable fsqrts.
Modified:
trunk/priv/guest-ppc/toIR.c
Modified: trunk/priv/guest-ppc/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc/toIR.c 2006-01-24 00:59:00 UTC (rev 1544)
+++ trunk/priv/guest-ppc/toIR.c 2006-01-24 03:33:43 UTC (rev 1545)
@@ -5672,15 +5672,15 @@
binop(Iop_AddF64, mkexpr(frA), mkexpr(frB)) ));
break;
=20
-//zz case 0x16: // fsqrts (Floating SqRt (Single-Precision), PPC32=
p428)
-//zz if (frA_addr !=3D 0 || frC_addr !=3D 0) {
-//zz vex_printf("dis_fp_arith(ppc)(instr,fsqrts)\n");
-//zz return False;
-//zz }
-//zz DIP("fsqrts%s fr%u,fr%u\n", flag_rC ? ".":"",
-//zz frD_addr, frB_addr);
-//zz assign( frD, roundToSgl( unop(Iop_SqrtF64, mkexpr(frB)) ))=
;
-//zz break;
+ case 0x16: // fsqrts (Floating SqRt (Single-Precision), PPC32 p428=
)
+ if (frA_addr !=3D 0 || frC_addr !=3D 0) {
+ vex_printf("dis_fp_arith(ppc)(instr,fsqrts)\n");
+ return False;
+ }
+ DIP("fsqrts%s fr%u,fr%u\n", flag_rC ? ".":"",
+ frD_addr, frB_addr);
+ assign( frD, roundToSgl( unop(Iop_SqrtF64, mkexpr(frB)) ));
+ break;
=20
//zz case 0x18: // fres (Floating Reciprocal Estimate Single, PPC3=
2 p421)
//zz if (frA_addr !=3D 0 || frC_addr !=3D 0) {
|
|
From: Tom H. <th...@cy...> - 2006-01-24 03:30:06
|
Nightly build on alvis ( i686, Red Hat 7.3 ) started at 2006-01-24 03:15:03 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 222 tests, 21 stderr failures, 2 stdout failures ================= memcheck/tests/addressable (stderr) memcheck/tests/badjump (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/erringfds (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/match-overrun (stderr) memcheck/tests/mempool (stderr) memcheck/tests/partial_load_dflt (stderr) memcheck/tests/partial_load_ok (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigkill (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) memcheck/tests/xml1 (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 220 tests, 21 stderr failures, 2 stdout failures ================= memcheck/tests/addressable (stderr) memcheck/tests/badjump (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/erringfds (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/leakotron (stdout) memcheck/tests/match-overrun (stderr) memcheck/tests/mempool (stderr) memcheck/tests/partial_load_dflt (stderr) memcheck/tests/partial_load_ok (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigkill (stderr) memcheck/tests/stack_changes (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) memcheck/tests/xml1 (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Tue Jan 24 03:22:46 2006 --- new.short Tue Jan 24 03:29:57 2006 *************** *** 8,10 **** ! == 220 tests, 21 stderr failures, 2 stdout failures ================= memcheck/tests/addressable (stderr) --- 8,10 ---- ! == 222 tests, 21 stderr failures, 2 stdout failures ================= memcheck/tests/addressable (stderr) |
|
From: Tom H. <th...@cy...> - 2006-01-24 03:22:50
|
Nightly build on dellow ( x86_64, Fedora Core 4 ) started at 2006-01-24 03:10:08 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 242 tests, 6 stderr failures, 2 stdout failures ================= memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) none/tests/amd64/faultstatus (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 240 tests, 6 stderr failures, 1 stdout failure ================= memcheck/tests/pointer-trace (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) none/tests/amd64/faultstatus (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Tue Jan 24 03:16:54 2006 --- new.short Tue Jan 24 03:22:40 2006 *************** *** 8,10 **** ! == 240 tests, 6 stderr failures, 1 stdout failure ================= memcheck/tests/pointer-trace (stderr) --- 8,11 ---- ! == 242 tests, 6 stderr failures, 2 stdout failures ================= ! memcheck/tests/leakotron (stdout) memcheck/tests/pointer-trace (stderr) |
|
From: Tom H. <th...@cy...> - 2006-01-24 03:19:29
|
Nightly build on aston ( x86_64, Fedora Core 3 ) started at 2006-01-24 03:05:18 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 242 tests, 6 stderr failures, 1 stdout failure ================= memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) none/tests/amd64/faultstatus (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 240 tests, 6 stderr failures, 1 stdout failure ================= memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) none/tests/amd64/faultstatus (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Tue Jan 24 03:12:52 2006 --- new.short Tue Jan 24 03:19:22 2006 *************** *** 8,10 **** ! == 240 tests, 6 stderr failures, 1 stdout failure ================= memcheck/tests/stack_switch (stderr) --- 8,10 ---- ! == 242 tests, 6 stderr failures, 1 stdout failure ================= memcheck/tests/stack_switch (stderr) |
|
From: Tom H. <th...@cy...> - 2006-01-24 03:17:36
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2006-01-24 03:00:03 GMT Results differ from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 242 tests, 7 stderr failures, 1 stdout failure ================= memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) none/tests/amd64/faultstatus (stderr) none/tests/fdleak_fcntl (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) ================================================= == Results from 24 hours ago == ================================================= Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 240 tests, 7 stderr failures, 1 stdout failure ================= memcheck/tests/stack_switch (stderr) memcheck/tests/x86/scalar (stderr) memcheck/tests/x86/scalar_supp (stderr) memcheck/tests/x86/sse1_memory (stdout) none/tests/amd64/faultstatus (stderr) none/tests/fdleak_fcntl (stderr) none/tests/x86/faultstatus (stderr) none/tests/x86/int (stderr) ================================================= == Difference between 24 hours ago and now == ================================================= *** old.short Tue Jan 24 03:08:32 2006 --- new.short Tue Jan 24 03:17:17 2006 *************** *** 8,10 **** ! == 240 tests, 7 stderr failures, 1 stdout failure ================= memcheck/tests/stack_switch (stderr) --- 8,10 ---- ! == 242 tests, 7 stderr failures, 1 stdout failure ================= memcheck/tests/stack_switch (stderr) |
|
From: <sv...@va...> - 2006-01-24 01:01:25
|
Author: sewardj
Date: 2006-01-24 01:01:17 +0000 (Tue, 24 Jan 2006)
New Revision: 5591
Log:
Vex can't simulate floor() or ceil() correctly on ppc32/64 from
glibc-2.3.4 onwards, so just replace the functions with the older
glibc implementation. This is an ugly kludge.
Modified:
trunk/coregrind/vg_preloaded.c
Modified: trunk/coregrind/vg_preloaded.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/vg_preloaded.c 2006-01-24 00:40:35 UTC (rev 5590)
+++ trunk/coregrind/vg_preloaded.c 2006-01-24 01:01:17 UTC (rev 5591)
@@ -65,6 +65,184 @@
*(int *)0 =3D 'x';
}
=20
+/* ---------------------------------------------------------------------
+ Avoid glibc's floor/ceil functions on ppc32/64. In recent glibcs
+ (about 2.3.4 and after) these rely on doing fadd/fsub with with
+ round to +inf/-inf set, which vex does not currently handle
+ correctly. This just reroutes to the glibc default implementations.
+ This is a really ugly hack.
+ ------------------------------------------------------------------ */
+
+#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
+/*
+ * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D
+ */
+/*
+ * floor(x)
+ * Return x rounded toward -inf to integral value
+ * Method:
+ * Bit twiddling.
+ * Exception:
+ * Inexact flag raised if x not equal to floor(x).
+ */
+
+typedef union
+{
+ double value;
+ struct
+ {
+ /*u_int32_t*/ UInt msw;
+ /*u_int32_t*/ UInt lsw;
+ } parts;
+} ieee_double_shape_type;
+
+/* Get two 32 bit ints from a double. */
+#define EXTRACT_WORDS(ix0,ix1,d) \
+do { \
+ ieee_double_shape_type ew_u; \
+ ew_u.value =3D (d); \
+ (ix0) =3D ew_u.parts.msw; \
+ (ix1) =3D ew_u.parts.lsw; \
+} while (0)
+
+/* Set a double from two 32 bit ints. */
+#define INSERT_WORDS(d,ix0,ix1) \
+do { \
+ ieee_double_shape_type iw_u; \
+ iw_u.parts.msw =3D (ix0); \
+ iw_u.parts.lsw =3D (ix1); \
+ (d) =3D iw_u.value; \
+} while (0)
+
+static double bit_twiddling_floor ( double x )
+{
+ static const double huge =3D 1.0e300;
+ /*int32_t*/ Int i0,i1,j0;
+ /*u_int32_t*/ UInt i,j;
+ EXTRACT_WORDS(i0,i1,x);
+ j0 =3D ((i0>>20)&0x7ff)-0x3ff;
+ if(j0<20) {
+ if(j0<0) { /* raise inexact if x !=3D 0 */
+ if(huge+x>0.0) {/* return 0*sign(x) if |x|<1 */
+ if(i0>=3D0) {i0=3Di1=3D0;}
+ else if(((i0&0x7fffffff)|i1)!=3D0)
+ { i0=3D0xbff00000;i1=3D0;}
+ }
+ } else {
+ i =3D (0x000fffff)>>j0;
+ if(((i0&i)|i1)=3D=3D0) return x; /* x is integral */
+ if(huge+x>0.0) { /* raise inexact flag */
+ if(i0<0) i0 +=3D (0x00100000)>>j0;
+ i0 &=3D (~i); i1=3D0;
+ }
+ }
+ } else if (j0>51) {
+ if(j0=3D=3D0x400) return x+x; /* inf or NaN */
+ else return x; /* x is integral */
+ } else {
+ i =3D ((/*u_int32_t*/UInt)(0xffffffff))>>(j0-20);
+ if((i1&i)=3D=3D0) return x; /* x is integral */
+ if(huge+x>0.0) { /* raise inexact flag */
+ if(i0<0) {
+ if(j0=3D=3D20) i0+=3D1;
+ else {
+ j =3D i1+(1<<(52-j0));
+ if(j<i1) i0 +=3D1 ; /* got a carry */
+ i1=3Dj;
+ }
+ }
+ i1 &=3D (~i);
+ }
+ }
+ INSERT_WORDS(x,i0,i1);
+ return x;
+}
+
+/* Catch libm.so.6:__floor */
+double VG_REPLACE_FUNCTION_ZZ(libmZdsoZd6,ZuZufloor)(double);
+double VG_REPLACE_FUNCTION_ZZ(libmZdsoZd6,ZuZufloor)(double x) {
+ return bit_twiddling_floor(x);
+}
+
+/* Catch libm.so.6:floor */
+double VG_REPLACE_FUNCTION_ZZ(libmZdsoZd6,floor)(double);
+double VG_REPLACE_FUNCTION_ZZ(libmZdsoZd6,floor)(double x) {
+ return bit_twiddling_floor(x);
+}
+
+
+/*
+ * ceil(x)
+ * Return x rounded toward -inf to integral value
+ * Method:
+ * Bit twiddling.
+ * Exception:
+ * Inexact flag raised if x not equal to ceil(x).
+ */
+static double bit_twiddling_ceil ( double x )
+{
+ static const double huge =3D 1.0e300;
+ /*int32_t*/ Int i0,i1,j0;
+ /*u_int32_t*/ UInt i,j;
+ EXTRACT_WORDS(i0,i1,x);
+ j0 =3D ((i0>>20)&0x7ff)-0x3ff;
+ if(j0<20) {
+ if(j0<0) { /* raise inexact if x !=3D 0 */
+ if(huge+x>0.0) {/* return 0*sign(x) if |x|<1 */
+ if(i0<0) {i0=3D0x80000000;i1=3D0;}
+ else if((i0|i1)!=3D0) { i0=3D0x3ff00000;i1=3D0;}
+ }
+ } else {
+ i =3D (0x000fffff)>>j0;
+ if(((i0&i)|i1)=3D=3D0) return x; /* x is integral */
+ if(huge+x>0.0) { /* raise inexact flag */
+ if(i0>0) i0 +=3D (0x00100000)>>j0;
+ i0 &=3D (~i); i1=3D0;
+ }
+ }
+ } else if (j0>51) {
+ if(j0=3D=3D0x400) return x+x; /* inf or NaN */
+ else return x; /* x is integral */
+ } else {
+ i =3D ((/*u_int32_t*/UInt)(0xffffffff))>>(j0-20);
+ if((i1&i)=3D=3D0) return x; /* x is integral */
+ if(huge+x>0.0) { /* raise inexact flag */
+ if(i0>0) {
+ if(j0=3D=3D20) i0+=3D1;
+ else {
+ j =3D i1 + (1<<(52-j0));
+ if(j<i1) i0+=3D1; /* got a carry */
+ i1 =3D j;
+ }
+ }
+ i1 &=3D (~i);
+ }
+ }
+ INSERT_WORDS(x,i0,i1);
+ return x;
+}
+
+/* Catch libm.so.6:__ceil */
+double VG_REPLACE_FUNCTION_ZZ(libmZdsoZd6,ZuZuceil)(double);
+double VG_REPLACE_FUNCTION_ZZ(libmZdsoZd6,ZuZuceil)(double x) {
+ return bit_twiddling_ceil(x);
+}
+
+/* Catch libm.so.6:ceil */
+double VG_REPLACE_FUNCTION_ZZ(libmZdsoZd6,ceil)(double);
+double VG_REPLACE_FUNCTION_ZZ(libmZdsoZd6,ceil)(double x) {
+ return bit_twiddling_ceil(x);
+}
+
+#endif
+
/*--------------------------------------------------------------------*/
/*--- end ---*/
/*--------------------------------------------------------------------*/
|
|
From: <sv...@va...> - 2006-01-24 00:59:15
|
Author: sewardj
Date: 2006-01-24 00:59:00 +0000 (Tue, 24 Jan 2006)
New Revision: 1544
Log:
The ppc32 port ran itself out of spill slots on some heavy duty FP
code.
Modified:
trunk/pub/libvex.h
Modified: trunk/pub/libvex.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/pub/libvex.h 2006-01-20 14:19:25 UTC (rev 1543)
+++ trunk/pub/libvex.h 2006-01-24 00:59:00 UTC (rev 1544)
@@ -245,7 +245,7 @@
On entry, the baseblock pointer register must be 8-aligned.
*/
=20
-#define LibVEX_N_SPILL_BYTES 1024
+#define LibVEX_N_SPILL_BYTES 1536
=20
=20
/*-------------------------------------------------------*/
|
|
From: <sv...@va...> - 2006-01-24 00:40:45
|
Author: sewardj
Date: 2006-01-24 00:40:35 +0000 (Tue, 24 Jan 2006)
New Revision: 5590
Log:
Test program to check the behaviour of a bunch of FP functions.
Added:
trunk/memcheck/tests/vcpu_fnfns.c
trunk/memcheck/tests/vcpu_fnfns.stderr.exp
trunk/memcheck/tests/vcpu_fnfns.stdout.exp
trunk/memcheck/tests/vcpu_fnfns.vgtest
Modified:
trunk/memcheck/tests/Makefile.am
Modified: trunk/memcheck/tests/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/tests/Makefile.am 2006-01-23 04:34:22 UTC (rev 5589)
+++ trunk/memcheck/tests/Makefile.am 2006-01-24 00:40:35 UTC (rev 5590)
@@ -109,6 +109,7 @@
metadata.stderr.exp metadata.stdout.exp metadata.vgtest-HIDING \
vcpu_bz2.stdout.exp vcpu_bz2.stderr.exp vcpu_bz2.vgtest \
vcpu_fbench.stdout.exp vcpu_fbench.stderr.exp vcpu_fbench.vgtest \
+ vcpu_fnfns.stdout.exp vcpu_fnfns.stderr.exp vcpu_fnfns.vgtest \
vgtest_ume.stderr.exp vgtest_ume.disabled \
wrap1.vgtest wrap1.stdout.exp wrap1.stderr.exp \
wrap2.vgtest wrap2.stdout.exp wrap2.stderr.exp \
@@ -151,7 +152,7 @@
supp_unknown supp1 supp2 suppfree \
trivialleak \
mismatches new_override metadata \
- vcpu_bz2 vcpu_fbench \
+ vcpu_bz2 vcpu_fbench vcpu_fnfns \
xml1 \
wrap1 wrap2 wrap3 wrap4 wrap5 wrap6 wrap7 wrap7so.so wrap8 \
writev zeropage
@@ -169,6 +170,9 @@
-DVGA_$(VG_ARCH)=3D1 -DVGO_$(VG_OS)=3D1 \
-DVGP_$(VG_ARCH)_$(VG_OS)=3D1
vcpu_bz2_CFLAGS =3D $(AM_FLAG_M3264_PRI) $(AM_CFLAGS) -O2 -g
+vcpu_fbench_CFLAGS =3D $(AM_FLAG_M3264_PRI) $(AM_CFLAGS) -O2 -g
+vcpu_fnfns_CFLAGS =3D $(AM_FLAG_M3264_PRI) $(AM_CFLAGS) -O2 -g
+vcpu_fnfns_LDADD =3D -lm
=20
# Don't allow GCC to inline memcpy(), because then we can't intercept it
overlap_CFLAGS =3D $(AM_CFLAGS) -fno-builtin-memcpy
Added: trunk/memcheck/tests/vcpu_fnfns.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/tests/vcpu_fnfns.c (rev 0)
+++ trunk/memcheck/tests/vcpu_fnfns.c 2006-01-24 00:40:35 UTC (rev 5590)
@@ -0,0 +1,180 @@
+
+/* Program to check that the FP stuff underlying these common FP
+ functions isn't too badly broken. Carefully kludged to print the
+ same answers on different platforms (even when run natively). */
+
+#include <stdio.h>
+#include <math.h>
+
+int main ( void )
+{
+ double d;
+ float f;
+ int i;
+
+ const double tinyD =3D 0.0000000001;
+ const double tinyF =3D 0.0001;
+
+ /* -------------------- any arg -------------------- */
+
+ d =3D -2.0;
+ for (i =3D 0; i < 41; i++) {
+ printf("floorD(%+20.13e) =3D %+20.13e\n", d, floor(d));
+ d +=3D 0.1-tinyD;
+ }
+ f =3D -2.0;
+ for (i =3D 0; i < 41; i++) {
+ printf("floorF(%+20.4e) =3D %+20.4e\n", (double)f, (double)floorf(=
f));
+ f +=3D 0.1-tinyF;
+ }
+
+
+ d =3D -2.0;
+ for (i =3D 0; i < 41; i++) {
+ printf(" ceilD(%+20.13e) =3D %+20.13e\n", d, ceil(d));
+ d +=3D 0.1-tinyD;
+ }
+ f =3D -2.0;
+ for (i =3D 0; i < 41; i++) {
+ printf(" ceilF(%+20.4e) =3D %+20.4e\n", (double)f, (double)ceilf(f=
));
+ f +=3D 0.1-tinyF;
+ }
+
+
+ d =3D -2.0;
+ for (i =3D 0; i < 41; i++) {
+ printf(" sinD(%+20.13e) =3D %+20.13e\n", d, sin(d));
+ d +=3D 0.1-tinyD;
+ }
+ f =3D -2.0;
+ for (i =3D 0; i < 41; i++) {
+ printf(" sinF(%+20.4e) =3D %+20.4e\n", (double)f, (double)sinf(f)=
);
+ f +=3D 0.1-tinyF;
+ }
+
+
+ d =3D -2.0;
+ for (i =3D 0; i < 41; i++) {
+ printf(" cosD(%+20.13e) =3D %+20.13e\n", d, cos(d));
+ d +=3D 0.1-tinyD;
+ }
+ f =3D -2.0;
+ for (i =3D 0; i < 41; i++) {
+ printf(" cosF(%+20.4e) =3D %+20.4e\n", (double)f, (double)cosf(f)=
);
+ f +=3D 0.1-tinyF;
+ }
+
+
+ d =3D -2.0;
+ for (i =3D 0; i < 41; i++) {
+ printf(" tanD(%+20.13e) =3D %+20.13e\n", d, tan(d));
+ d +=3D 0.1-tinyD;
+ }
+ f =3D -2.0;
+ for (i =3D 0; i < 41; i++) {
+ printf(" tanF(%+20.4e) =3D %+20.4e\n", (double)f, (double)tanf(f)=
);
+ f +=3D 0.1-tinyF;
+ }
+
+
+ d =3D -2.0;
+ for (i =3D 0; i < 41; i++) {
+ printf(" expD(%+20.13e) =3D %+20.13e\n", d, exp(d));
+ d +=3D 0.1-tinyD;
+ }
+ f =3D -2.0;
+ for (i =3D 0; i < 41; i++) {
+ printf(" expF(%+20.4e) =3D %+20.4e\n", (double)f, (double)expf(f)=
);
+ f +=3D 0.1-tinyF;
+ }
+
+ /* -------------------- >=3D 0 arg -------------------- */
+
+ d =3D 0.0;
+ for (i =3D 0; i < 21; i++) {
+ printf(" sqrtD(%+20.13e) =3D %+20.13e\n", d, sqrt(d));
+ d +=3D 0.1-tinyD;
+ }
+ f =3D 0.0;
+ for (i =3D 0; i < 21; i++) {
+ printf(" sqrtF(%+20.4e) =3D %+20.4e\n", (double)f, (double)sqrtf(f=
));
+ f +=3D 0.1-tinyF;
+ }
+
+
+ d =3D 0.0;
+ for (i =3D 0; i < 21; i++) {
+ printf(" logD(%+20.13e) =3D %+20.13e\n", d, log(d));
+ d +=3D 0.1-tinyD;
+ }
+ f =3D 0.0;
+ for (i =3D 0; i < 21; i++) {
+ printf(" logF(%+20.4e) =3D %+20.4e\n", (double)f, (double)logf(f)=
);
+ f +=3D 0.1-tinyF;
+ }
+
+
+ d =3D 0.0;
+ for (i =3D 0; i < 21; i++) {
+ printf("log10D(%+20.13e) =3D %+20.13e\n", d, log10(d));
+ d +=3D 0.1-tinyD;
+ }
+ f =3D 0.0;
+ for (i =3D 0; i < 21; i++) {
+ printf("log10F(%+20.4e) =3D %+20.4e\n", (double)f, (double)log10f(=
f));
+ f +=3D 0.1-tinyF;
+ }
+
+ /* -------------------- -1 .. +1 arg -------------------- */
+
+ d =3D -1.0;
+ for (i =3D 0; i < 21; i++) {
+ printf(" asinD(%+20.13e) =3D %+20.13e\n", d, asin(d));
+ d +=3D 0.1-tinyD;
+ }
+ f =3D -1.0;
+ for (i =3D 0; i < 21; i++) {
+ printf(" asinF(%+20.4e) =3D %+20.4e\n", (double)f, (double)asinf(f=
));
+ f +=3D 0.1-tinyF;
+ }
+
+ /* acos(double) seems very prone to accuracy loss near the end of
+ the range (arg --> +1.0). Hence is different from the rest to
+ stop it getting so close to 1.0. */
+ d =3D -1.0;
+ for (i =3D 0; i < 21; i++) {
+ printf(" acosD(%+20.13e) =3D %+20.10e\n", d, acos(d));
+ d +=3D 0.1 - 1000.0*tinyD;
+ }
+ f =3D -1.0;
+ for (i =3D 0; i < 21; i++) {
+ printf(" acosF(%+20.4e) =3D %+20.4e\n", (double)f, (double)acosf(f=
));
+ f +=3D 0.1-tinyF;
+ }
+
+
+ d =3D -1.0;
+ for (i =3D 0; i < 21; i++) {
+ printf(" atanD(%+20.13e) =3D %+20.13e\n", d, atan(d));
+ d +=3D 0.1-tinyD;
+ }
+ f =3D -1.0;
+ for (i =3D 0; i < 21; i++) {
+ printf(" atanF(%+20.4e) =3D %+20.4e\n", (double)f, (double)atanf(f=
));
+ f +=3D 0.1-tinyF;
+ }
+
+
+ d =3D -1.0;
+ for (i =3D 0; i < 21; i++) {
+ printf("atan2D(%+20.13e) =3D %+20.13e\n", d, atan2(d, 1.0));
+ d +=3D 0.1-tinyD;
+ }
+ f =3D -1.0;
+ for (i =3D 0; i < 21; i++) {
+ printf("atan2F(%+20.4e) =3D %+20.4e\n", (double)f, (double)atan2f(=
f,1.0));
+ f +=3D 0.1-tinyF;
+ }
+
+ return 0;
+}
Added: trunk/memcheck/tests/vcpu_fnfns.stderr.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Added: trunk/memcheck/tests/vcpu_fnfns.stdout.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/tests/vcpu_fnfns.stdout.exp (r=
ev 0)
+++ trunk/memcheck/tests/vcpu_fnfns.stdout.exp 2006-01-24 00:40:35 UTC (r=
ev 5590)
@@ -0,0 +1,786 @@
+floorD(-2.0000000000000e+00) =3D -2.0000000000000e+00
+floorD(-1.9000000001000e+00) =3D -2.0000000000000e+00
+floorD(-1.8000000002000e+00) =3D -2.0000000000000e+00
+floorD(-1.7000000003000e+00) =3D -2.0000000000000e+00
+floorD(-1.6000000004000e+00) =3D -2.0000000000000e+00
+floorD(-1.5000000005000e+00) =3D -2.0000000000000e+00
+floorD(-1.4000000006000e+00) =3D -2.0000000000000e+00
+floorD(-1.3000000007000e+00) =3D -2.0000000000000e+00
+floorD(-1.2000000008000e+00) =3D -2.0000000000000e+00
+floorD(-1.1000000009000e+00) =3D -2.0000000000000e+00
+floorD(-1.0000000010000e+00) =3D -2.0000000000000e+00
+floorD(-9.0000000110000e-01) =3D -1.0000000000000e+00
+floorD(-8.0000000120000e-01) =3D -1.0000000000000e+00
+floorD(-7.0000000130000e-01) =3D -1.0000000000000e+00
+floorD(-6.0000000140000e-01) =3D -1.0000000000000e+00
+floorD(-5.0000000150000e-01) =3D -1.0000000000000e+00
+floorD(-4.0000000160000e-01) =3D -1.0000000000000e+00
+floorD(-3.0000000170000e-01) =3D -1.0000000000000e+00
+floorD(-2.0000000180000e-01) =3D -1.0000000000000e+00
+floorD(-1.0000000190000e-01) =3D -1.0000000000000e+00
+floorD(-1.9999992495467e-09) =3D -1.0000000000000e+00
+floorD(+9.9999997900001e-02) =3D +0.0000000000000e+00
+floorD(+1.9999999780000e-01) =3D +0.0000000000000e+00
+floorD(+2.9999999770000e-01) =3D +0.0000000000000e+00
+floorD(+3.9999999760000e-01) =3D +0.0000000000000e+00
+floorD(+4.9999999750000e-01) =3D +0.0000000000000e+00
+floorD(+5.9999999740000e-01) =3D +0.0000000000000e+00
+floorD(+6.9999999730000e-01) =3D +0.0000000000000e+00
+floorD(+7.9999999720000e-01) =3D +0.0000000000000e+00
+floorD(+8.9999999710000e-01) =3D +0.0000000000000e+00
+floorD(+9.9999999700000e-01) =3D +0.0000000000000e+00
+floorD(+1.0999999969000e+00) =3D +1.0000000000000e+00
+floorD(+1.1999999968000e+00) =3D +1.0000000000000e+00
+floorD(+1.2999999967000e+00) =3D +1.0000000000000e+00
+floorD(+1.3999999966000e+00) =3D +1.0000000000000e+00
+floorD(+1.4999999965000e+00) =3D +1.0000000000000e+00
+floorD(+1.5999999964000e+00) =3D +1.0000000000000e+00
+floorD(+1.6999999963000e+00) =3D +1.0000000000000e+00
+floorD(+1.7999999962000e+00) =3D +1.0000000000000e+00
+floorD(+1.8999999961000e+00) =3D +1.0000000000000e+00
+floorD(+1.9999999960000e+00) =3D +1.0000000000000e+00
+floorF( -2.0000e+00) =3D -2.0000e+00
+floorF( -1.9001e+00) =3D -2.0000e+00
+floorF( -1.8002e+00) =3D -2.0000e+00
+floorF( -1.7003e+00) =3D -2.0000e+00
+floorF( -1.6004e+00) =3D -2.0000e+00
+floorF( -1.5005e+00) =3D -2.0000e+00
+floorF( -1.4006e+00) =3D -2.0000e+00
+floorF( -1.3007e+00) =3D -2.0000e+00
+floorF( -1.2008e+00) =3D -2.0000e+00
+floorF( -1.1009e+00) =3D -2.0000e+00
+floorF( -1.0010e+00) =3D -2.0000e+00
+floorF( -9.0110e-01) =3D -1.0000e+00
+floorF( -8.0120e-01) =3D -1.0000e+00
+floorF( -7.0130e-01) =3D -1.0000e+00
+floorF( -6.0140e-01) =3D -1.0000e+00
+floorF( -5.0150e-01) =3D -1.0000e+00
+floorF( -4.0160e-01) =3D -1.0000e+00
+floorF( -3.0170e-01) =3D -1.0000e+00
+floorF( -2.0180e-01) =3D -1.0000e+00
+floorF( -1.0190e-01) =3D -1.0000e+00
+floorF( -1.9999e-03) =3D -1.0000e+00
+floorF( +9.7900e-02) =3D +0.0000e+00
+floorF( +1.9780e-01) =3D +0.0000e+00
+floorF( +2.9770e-01) =3D +0.0000e+00
+floorF( +3.9760e-01) =3D +0.0000e+00
+floorF( +4.9750e-01) =3D +0.0000e+00
+floorF( +5.9740e-01) =3D +0.0000e+00
+floorF( +6.9730e-01) =3D +0.0000e+00
+floorF( +7.9720e-01) =3D +0.0000e+00
+floorF( +8.9710e-01) =3D +0.0000e+00
+floorF( +9.9700e-01) =3D +0.0000e+00
+floorF( +1.0969e+00) =3D +1.0000e+00
+floorF( +1.1968e+00) =3D +1.0000e+00
+floorF( +1.2967e+00) =3D +1.0000e+00
+floorF( +1.3966e+00) =3D +1.0000e+00
+floorF( +1.4965e+00) =3D +1.0000e+00
+floorF( +1.5964e+00) =3D +1.0000e+00
+floorF( +1.6963e+00) =3D +1.0000e+00
+floorF( +1.7962e+00) =3D +1.0000e+00
+floorF( +1.8961e+00) =3D +1.0000e+00
+floorF( +1.9960e+00) =3D +1.0000e+00
+ ceilD(-2.0000000000000e+00) =3D -2.0000000000000e+00
+ ceilD(-1.9000000001000e+00) =3D -1.0000000000000e+00
+ ceilD(-1.8000000002000e+00) =3D -1.0000000000000e+00
+ ceilD(-1.7000000003000e+00) =3D -1.0000000000000e+00
+ ceilD(-1.6000000004000e+00) =3D -1.0000000000000e+00
+ ceilD(-1.5000000005000e+00) =3D -1.0000000000000e+00
+ ceilD(-1.4000000006000e+00) =3D -1.0000000000000e+00
+ ceilD(-1.3000000007000e+00) =3D -1.0000000000000e+00
+ ceilD(-1.2000000008000e+00) =3D -1.0000000000000e+00
+ ceilD(-1.1000000009000e+00) =3D -1.0000000000000e+00
+ ceilD(-1.0000000010000e+00) =3D -1.0000000000000e+00
+ ceilD(-9.0000000110000e-01) =3D -0.0000000000000e+00
+ ceilD(-8.0000000120000e-01) =3D -0.0000000000000e+00
+ ceilD(-7.0000000130000e-01) =3D -0.0000000000000e+00
+ ceilD(-6.0000000140000e-01) =3D -0.0000000000000e+00
+ ceilD(-5.0000000150000e-01) =3D -0.0000000000000e+00
+ ceilD(-4.0000000160000e-01) =3D -0.0000000000000e+00
+ ceilD(-3.0000000170000e-01) =3D -0.0000000000000e+00
+ ceilD(-2.0000000180000e-01) =3D -0.0000000000000e+00
+ ceilD(-1.0000000190000e-01) =3D -0.0000000000000e+00
+ ceilD(-1.9999992495467e-09) =3D -0.0000000000000e+00
+ ceilD(+9.9999997900001e-02) =3D +1.0000000000000e+00
+ ceilD(+1.9999999780000e-01) =3D +1.0000000000000e+00
+ ceilD(+2.9999999770000e-01) =3D +1.0000000000000e+00
+ ceilD(+3.9999999760000e-01) =3D +1.0000000000000e+00
+ ceilD(+4.9999999750000e-01) =3D +1.0000000000000e+00
+ ceilD(+5.9999999740000e-01) =3D +1.0000000000000e+00
+ ceilD(+6.9999999730000e-01) =3D +1.0000000000000e+00
+ ceilD(+7.9999999720000e-01) =3D +1.0000000000000e+00
+ ceilD(+8.9999999710000e-01) =3D +1.0000000000000e+00
+ ceilD(+9.9999999700000e-01) =3D +1.0000000000000e+00
+ ceilD(+1.0999999969000e+00) =3D +2.0000000000000e+00
+ ceilD(+1.1999999968000e+00) =3D +2.0000000000000e+00
+ ceilD(+1.2999999967000e+00) =3D +2.0000000000000e+00
+ ceilD(+1.3999999966000e+00) =3D +2.0000000000000e+00
+ ceilD(+1.4999999965000e+00) =3D +2.0000000000000e+00
+ ceilD(+1.5999999964000e+00) =3D +2.0000000000000e+00
+ ceilD(+1.6999999963000e+00) =3D +2.0000000000000e+00
+ ceilD(+1.7999999962000e+00) =3D +2.0000000000000e+00
+ ceilD(+1.8999999961000e+00) =3D +2.0000000000000e+00
+ ceilD(+1.9999999960000e+00) =3D +2.0000000000000e+00
+ ceilF( -2.0000e+00) =3D -2.0000e+00
+ ceilF( -1.9001e+00) =3D -1.0000e+00
+ ceilF( -1.8002e+00) =3D -1.0000e+00
+ ceilF( -1.7003e+00) =3D -1.0000e+00
+ ceilF( -1.6004e+00) =3D -1.0000e+00
+ ceilF( -1.5005e+00) =3D -1.0000e+00
+ ceilF( -1.4006e+00) =3D -1.0000e+00
+ ceilF( -1.3007e+00) =3D -1.0000e+00
+ ceilF( -1.2008e+00) =3D -1.0000e+00
+ ceilF( -1.1009e+00) =3D -1.0000e+00
+ ceilF( -1.0010e+00) =3D -1.0000e+00
+ ceilF( -9.0110e-01) =3D -0.0000e+00
+ ceilF( -8.0120e-01) =3D -0.0000e+00
+ ceilF( -7.0130e-01) =3D -0.0000e+00
+ ceilF( -6.0140e-01) =3D -0.0000e+00
+ ceilF( -5.0150e-01) =3D -0.0000e+00
+ ceilF( -4.0160e-01) =3D -0.0000e+00
+ ceilF( -3.0170e-01) =3D -0.0000e+00
+ ceilF( -2.0180e-01) =3D -0.0000e+00
+ ceilF( -1.0190e-01) =3D -0.0000e+00
+ ceilF( -1.9999e-03) =3D -0.0000e+00
+ ceilF( +9.7900e-02) =3D +1.0000e+00
+ ceilF( +1.9780e-01) =3D +1.0000e+00
+ ceilF( +2.9770e-01) =3D +1.0000e+00
+ ceilF( +3.9760e-01) =3D +1.0000e+00
+ ceilF( +4.9750e-01) =3D +1.0000e+00
+ ceilF( +5.9740e-01) =3D +1.0000e+00
+ ceilF( +6.9730e-01) =3D +1.0000e+00
+ ceilF( +7.9720e-01) =3D +1.0000e+00
+ ceilF( +8.9710e-01) =3D +1.0000e+00
+ ceilF( +9.9700e-01) =3D +1.0000e+00
+ ceilF( +1.0969e+00) =3D +2.0000e+00
+ ceilF( +1.1968e+00) =3D +2.0000e+00
+ ceilF( +1.2967e+00) =3D +2.0000e+00
+ ceilF( +1.3966e+00) =3D +2.0000e+00
+ ceilF( +1.4965e+00) =3D +2.0000e+00
+ ceilF( +1.5964e+00) =3D +2.0000e+00
+ ceilF( +1.6963e+00) =3D +2.0000e+00
+ ceilF( +1.7962e+00) =3D +2.0000e+00
+ ceilF( +1.8961e+00) =3D +2.0000e+00
+ ceilF( +1.9960e+00) =3D +2.0000e+00
+ sinD(-2.0000000000000e+00) =3D -9.0929742682568e-01
+ sinD(-1.9000000001000e+00) =3D -9.4630008765509e-01
+ sinD(-1.8000000002000e+00) =3D -9.7384763083275e-01
+ sinD(-1.7000000003000e+00) =3D -9.9166481041382e-01
+ sinD(-1.6000000004000e+00) =3D -9.9957360302983e-01
+ sinD(-1.5000000005000e+00) =3D -9.9749498663942e-01
+ sinD(-1.4000000006000e+00) =3D -9.8544973009044e-01
+ sinD(-1.3000000007000e+00) =3D -9.6355818560444e-01
+ sinD(-1.2000000008000e+00) =3D -9.3203908625711e-01
+ sinD(-1.1000000009000e+00) =3D -8.9120736046967e-01
+ sinD(-1.0000000010000e+00) =3D -8.4147098534820e-01
+ sinD(-9.0000000110000e-01) =3D -7.8332691031125e-01
+ sinD(-8.0000000120000e-01) =3D -7.1735609173557e-01
+ sinD(-7.0000000130000e-01) =3D -6.4421768823199e-01
+ sinD(-6.0000000140000e-01) =3D -5.6464247455050e-01
+ sinD(-5.0000000150000e-01) =3D -4.7942553992058e-01
+ sinD(-4.0000000160000e-01) =3D -3.8941834378235e-01
+ sinD(-3.0000000170000e-01) =3D -2.9552020828541e-01
+ sinD(-2.0000000180000e-01) =3D -1.9866933255918e-01
+ sinD(-1.0000000190000e-01) =3D -9.9833418537335e-02
+ sinD(-1.9999992495467e-09) =3D -1.9999992495467e-09
+ sinD(+9.9999997900001e-02) =3D +9.9833414557320e-02
+ sinD(+1.9999999780000e-01) =3D +1.9866932863892e-01
+ sinD(+2.9999999770000e-01) =3D +2.9552020446407e-01
+ sinD(+3.9999999760000e-01) =3D +3.8941834009810e-01
+ sinD(+4.9999999750000e-01) =3D +4.7942553641025e-01
+ sinD(+5.9999999740000e-01) =3D +5.6464247124916e-01
+ sinD(+6.9999999730000e-01) =3D +6.4421768517262e-01
+ sinD(+7.9999999720000e-01) =3D +7.1735608894874e-01
+ sinD(+8.9999999710000e-01) =3D +7.8332690782481e-01
+ sinD(+9.9999999700000e-01) =3D +8.4147098318699e-01
+ sinD(+1.0999999969000e+00) =3D +8.9120735865529e-01
+ sinD(+1.1999999968000e+00) =3D +9.3203908480768e-01
+ sinD(+1.2999999967000e+00) =3D +9.6355818453445e-01
+ sinD(+1.3999999966000e+00) =3D +9.8544972941057e-01
+ sinD(+1.4999999965000e+00) =3D +9.9749498635647e-01
+ sinD(+1.5999999964000e+00) =3D +9.9957360314662e-01
+ sinD(+1.6999999963000e+00) =3D +9.9166481092919e-01
+ sinD(+1.7999999962000e+00) =3D +9.7384763174156e-01
+ sinD(+1.8999999961000e+00) =3D +9.4630008894824e-01
+ sinD(+1.9999999960000e+00) =3D +9.0929742849027e-01
+ sinF( -2.0000e+00) =3D -9.0930e-01
+ sinF( -1.9001e+00) =3D -9.4627e-01
+ sinF( -1.8002e+00) =3D -9.7380e-01
+ sinF( -1.7003e+00) =3D -9.9163e-01
+ sinF( -1.6004e+00) =3D -9.9956e-01
+ sinF( -1.5005e+00) =3D -9.9753e-01
+ sinF( -1.4006e+00) =3D -9.8555e-01
+ sinF( -1.3007e+00) =3D -9.6375e-01
+ sinF( -1.2008e+00) =3D -9.3233e-01
+ sinF( -1.1009e+00) =3D -8.9162e-01
+ sinF( -1.0010e+00) =3D -8.4201e-01
+ sinF( -9.0110e-01) =3D -7.8401e-01
+ sinF( -8.0120e-01) =3D -7.1819e-01
+ sinF( -7.0130e-01) =3D -6.4521e-01
+ sinF( -6.0140e-01) =3D -5.6580e-01
+ sinF( -5.0150e-01) =3D -4.8074e-01
+ sinF( -4.0160e-01) =3D -3.9089e-01
+ sinF( -3.0170e-01) =3D -2.9714e-01
+ sinF( -2.0180e-01) =3D -2.0043e-01
+ sinF( -1.0190e-01) =3D -1.0172e-01
+ sinF( -1.9999e-03) =3D -1.9999e-03
+ sinF( +9.7900e-02) =3D +9.7744e-02
+ sinF( +1.9780e-01) =3D +1.9651e-01
+ sinF( +2.9770e-01) =3D +2.9332e-01
+ sinF( +3.9760e-01) =3D +3.8721e-01
+ sinF( +4.9750e-01) =3D +4.7723e-01
+ sinF( +5.9740e-01) =3D +5.6249e-01
+ sinF( +6.9730e-01) =3D +6.4215e-01
+ sinF( +7.9720e-01) =3D +7.1540e-01
+ sinF( +8.9710e-01) =3D +7.8152e-01
+ sinF( +9.9700e-01) =3D +8.3985e-01
+ sinF( +1.0969e+00) =3D +8.8980e-01
+ sinF( +1.1968e+00) =3D +9.3087e-01
+ sinF( +1.2967e+00) =3D +9.6267e-01
+ sinF( +1.3966e+00) =3D +9.8487e-01
+ sinF( +1.4965e+00) =3D +9.9724e-01
+ sinF( +1.5964e+00) =3D +9.9967e-01
+ sinF( +1.6963e+00) =3D +9.9213e-01
+ sinF( +1.7962e+00) =3D +9.7470e-01
+ sinF( +1.8961e+00) =3D +9.4755e-01
+ sinF( +1.9960e+00) =3D +9.1095e-01
+ cosD(-2.0000000000000e+00) =3D -4.1614683654714e-01
+ cosD(-1.9000000001000e+00) =3D -3.2328956695813e-01
+ cosD(-1.8000000002000e+00) =3D -2.2720209488786e-01
+ cosD(-1.7000000003000e+00) =3D -1.2884449459302e-01
+ cosD(-1.6000000004000e+00) =3D -2.9199522701118e-02
+ cosD(-1.5000000005000e+00) =3D +7.0737201168956e-02
+ cosD(-1.4000000006000e+00) =3D +1.6996714230897e-01
+ cosD(-1.3000000007000e+00) =3D +2.6749882795010e-01
+ cosD(-1.2000000008000e+00) =3D +3.6235775373104e-01
+ cosD(-1.1000000009000e+00) =3D +4.5359612062349e-01
+ cosD(-1.0000000010000e+00) =3D +5.4030230502667e-01
+ cosD(-9.0000000110000e-01) =3D +6.2160996740901e-01
+ cosD(-8.0000000120000e-01) =3D +6.9670670848634e-01
+ cosD(-7.0000000130000e-01) =3D +7.6484218644701e-01
+ cosD(-6.0000000140000e-01) =3D +8.2533561411918e-01
+ cosD(-5.0000000150000e-01) =3D +8.7758256117123e-01
+ cosD(-4.0000000160000e-01) =3D +9.2106099337982e-01
+ cosD(-3.0000000170000e-01) =3D +9.5533648862322e-01
+ cosD(-2.0000000180000e-01) =3D +9.8006657748364e-01
+ cosD(-1.0000000190000e-01) =3D +9.9500416508834e-01
+ cosD(-1.9999992495467e-09) =3D +1.0000000000000e+00
+ cosD(+9.9999997900001e-02) =3D +9.9500416548768e-01
+ cosD(+1.9999999780000e-01) =3D +9.8006657827831e-01
+ cosD(+2.9999999770000e-01) =3D +9.5533648980530e-01
+ cosD(+3.9999999760000e-01) =3D +9.2106099493749e-01
+ cosD(+4.9999999750000e-01) =3D +8.7758256308894e-01
+ cosD(+5.9999999740000e-01) =3D +8.2533561637775e-01
+ cosD(+6.9999999730000e-01) =3D +7.6484218902388e-01
+ cosD(+7.9999999720000e-01) =3D +6.9670671135576e-01
+ cosD(+8.9999999710000e-01) =3D +6.2160997054231e-01
+ cosD(+9.9999999700000e-01) =3D +5.4030230839255e-01
+ cosD(+1.0999999969000e+00) =3D +4.5359612418832e-01
+ cosD(+1.1999999968000e+00) =3D +3.6235775745920e-01
+ cosD(+1.2999999967000e+00) =3D +2.6749883180433e-01
+ cosD(+1.3999999966000e+00) =3D +1.6996714625077e-01
+ cosD(+1.4999999965000e+00) =3D +7.0737205158934e-02
+ cosD(+1.5999999964000e+00) =3D -2.9199518702825e-02
+ cosD(+1.6999999963000e+00) =3D -1.2884449062637e-01
+ cosD(+1.7999999962000e+00) =3D -2.2720209099247e-01
+ cosD(+1.8999999961000e+00) =3D -3.2328956317293e-01
+ cosD(+1.9999999960000e+00) =3D -4.1614683290995e-01
+ cosF( -2.0000e+00) =3D -4.1615e-01
+ cosF( -1.9001e+00) =3D -3.2338e-01
+ cosF( -1.8002e+00) =3D -2.2740e-01
+ cosF( -1.7003e+00) =3D -1.2914e-01
+ cosF( -1.6004e+00) =3D -2.9599e-02
+ cosF( -1.5005e+00) =3D +7.0238e-02
+ cosF( -1.4006e+00) =3D +1.6938e-01
+ cosF( -1.3007e+00) =3D +2.6682e-01
+ cosF( -1.2008e+00) =3D +3.6161e-01
+ cosF( -1.1009e+00) =3D +4.5279e-01
+ cosF( -1.0010e+00) =3D +5.3946e-01
+ cosF( -9.0110e-01) =3D +6.2075e-01
+ cosF( -8.0120e-01) =3D +6.9585e-01
+ cosF( -7.0130e-01) =3D +7.6400e-01
+ cosF( -6.0140e-01) =3D +8.2454e-01
+ cosF( -5.0150e-01) =3D +8.7686e-01
+ cosF( -4.0160e-01) =3D +9.2044e-01
+ cosF( -3.0170e-01) =3D +9.5483e-01
+ cosF( -2.0180e-01) =3D +9.7971e-01
+ cosF( -1.0190e-01) =3D +9.9481e-01
+ cosF( -1.9999e-03) =3D +1.0000e-00
+ cosF( +9.7900e-02) =3D +9.9521e-01
+ cosF( +1.9780e-01) =3D +9.8050e-01
+ cosF( +2.9770e-01) =3D +9.5601e-01
+ cosF( +3.9760e-01) =3D +9.2199e-01
+ cosF( +4.9750e-01) =3D +8.7878e-01
+ cosF( +5.9740e-01) =3D +8.2680e-01
+ cosF( +6.9730e-01) =3D +7.6658e-01
+ cosF( +7.9720e-01) =3D +6.9871e-01
+ cosF( +8.9710e-01) =3D +6.2388e-01
+ cosF( +9.9700e-01) =3D +5.4282e-01
+ cosF( +1.0969e+00) =3D +4.5636e-01
+ cosF( +1.1968e+00) =3D +3.6534e-01
+ cosF( +1.2967e+00) =3D +2.7068e-01
+ cosF( +1.3966e+00) =3D +1.7332e-01
+ cosF( +1.4965e+00) =3D +7.4228e-02
+ cosF( +1.5964e+00) =3D -2.5601e-02
+ cosF( +1.6963e+00) =3D -1.2517e-01
+ cosF( +1.7962e+00) =3D -2.2350e-01
+ cosF( +1.8961e+00) =3D -3.1960e-01
+ cosF( +1.9960e+00) =3D -4.1251e-01
+ tanD(-2.0000000000000e+00) =3D +2.1850398632615e+00
+ tanD(-1.9000000001000e+00) =3D +2.9270975137210e+00
+ tanD(-1.8000000002000e+00) =3D +4.2862616707537e+00
+ tanD(-1.7000000003000e+00) =3D +7.6966021213879e+00
+ tanD(-1.6000000004000e+00) =3D +3.4232532266411e+01
+ tanD(-1.5000000005000e+00) =3D -1.4101420047097e+01
+ tanD(-1.4000000006000e+00) =3D -5.7978837362521e+00
+ tanD(-1.3000000007000e+00) =3D -3.6021024577506e+00
+ tanD(-1.2000000008000e+00) =3D -2.5721516282191e+00
+ tanD(-1.1000000009000e+00) =3D -1.9647596616229e+00
+ tanD(-1.0000000010000e+00) =3D -1.5574077280804e+00
+ tanD(-9.0000000110000e-01) =3D -1.2601582203971e+00
+ tanD(-8.0000000120000e-01) =3D -1.0296385595225e+00
+ tanD(-7.0000000130000e-01) =3D -8.4228838268536e-01
+ tanD(-6.0000000140000e-01) =3D -6.8413681039695e-01
+ tanD(-5.0000000150000e-01) =3D -5.4630249179146e-01
+ tanD(-4.0000000160000e-01) =3D -4.2279322062417e-01
+ tanD(-3.0000000170000e-01) =3D -3.0933625147229e-01
+ tanD(-2.0000000180000e-01) =3D -2.0271003738264e-01
+ tanD(-1.0000000190000e-01) =3D -1.0033467400458e-01
+ tanD(-1.9999992495467e-09) =3D -1.9999992495467e-09
+ tanD(+9.9999997900001e-02) =3D +1.0033466996431e-01
+ tanD(+1.9999999780000e-01) =3D +2.0271003321827e-01
+ tanD(+2.9999999770000e-01) =3D +3.0933624708954e-01
+ tanD(+3.9999999760000e-01) =3D +4.2279321590915e-01
+ tanD(+4.9999999750000e-01) =3D +5.4630248659768e-01
+ tanD(+5.9999999740000e-01) =3D +6.8413680452478e-01
+ tanD(+6.9999999730000e-01) =3D +8.4228837584757e-01
+ tanD(+7.9999999720000e-01) =3D +1.0296385512819e+00
+ tanD(+8.9999999710000e-01) =3D +1.2601582100451e+00
+ tanD(+9.9999999700000e-01) =3D +1.5574077143783e+00
+ tanD(+1.0999999969000e+00) =3D +1.9647596421818e+00
+ tanD(+1.1999999968000e+00) =3D +2.5721515977552e+00
+ tanD(+1.2999999967000e+00) =3D +3.6021024018500e+00
+ tanD(+1.3999999966000e+00) =3D +5.7978835977904e+00
+ tanD(+1.4999999965000e+00) =3D +1.4101419247697e+01
+ tanD(+1.5999999964000e+00) =3D -3.4232536957875e+01
+ tanD(+1.6999999963000e+00) =3D -7.6966023623385e+00
+ tanD(+1.7999999962000e+00) =3D -4.2862617482418e+00
+ tanD(+1.8999999961000e+00) =3D -2.9270975519926e+00
+ tanD(+1.9999999960000e+00) =3D -2.1850398863591e+00
+ tanF( -2.0000e+00) =3D +2.1850e+00
+ tanF( -1.9001e+00) =3D +2.9261e+00
+ tanF( -1.8002e+00) =3D +4.2824e+00
+ tanF( -1.7003e+00) =3D +7.6786e+00
+ tanF( -1.6004e+00) =3D +3.3770e+01
+ tanF( -1.5005e+00) =3D -1.4202e+01
+ tanF( -1.4006e+00) =3D -5.8187e+00
+ tanF( -1.3007e+00) =3D -3.6119e+00
+ tanF( -1.2008e+00) =3D -2.5783e+00
+ tanF( -1.1009e+00) =3D -1.9691e+00
+ tanF( -1.0010e+00) =3D -1.5608e+00
+ tanF( -9.0110e-01) =3D -1.2630e+00
+ tanF( -8.0120e-01) =3D -1.0321e+00
+ tanF( -7.0130e-01) =3D -8.4451e-01
+ tanF( -6.0140e-01) =3D -6.8619e-01
+ tanF( -5.0150e-01) =3D -5.4825e-01
+ tanF( -4.0160e-01) =3D -4.2468e-01
+ tanF( -3.0170e-01) =3D -3.1120e-01
+ tanF( -2.0180e-01) =3D -2.0458e-01
+ tanF( -1.0190e-01) =3D -1.0225e-01
+ tanF( -1.9999e-03) =3D -1.9999e-03
+ tanF( +9.7900e-02) =3D +9.8214e-02
+ tanF( +1.9780e-01) =3D +2.0042e-01
+ tanF( +2.9770e-01) =3D +3.0682e-01
+ tanF( +3.9760e-01) =3D +4.1997e-01
+ tanF( +4.9750e-01) =3D +5.4306e-01
+ tanF( +5.9740e-01) =3D +6.8033e-01
+ tanF( +6.9730e-01) =3D +8.3768e-01
+ tanF( +7.9720e-01) =3D +1.0239e+00
+ tanF( +8.9710e-01) =3D +1.2527e+00
+ tanF( +9.9700e-01) =3D +1.5472e+00
+ tanF( +1.0969e+00) =3D +1.9498e+00
+ tanF( +1.1968e+00) =3D +2.5480e+00
+ tanF( +1.2967e+00) =3D +3.5565e+00
+ tanF( +1.3966e+00) =3D +5.6825e+00
+ tanF( +1.4965e+00) =3D +1.3435e+01
+ tanF( +1.5964e+00) =3D -3.9048e+01
+ tanF( +1.6963e+00) =3D -7.9260e+00
+ tanF( +1.7962e+00) =3D -4.3611e+00
+ tanF( +1.8961e+00) =3D -2.9648e+00
+ tanF( +1.9960e+00) =3D -2.2083e+00
+ expD(-2.0000000000000e+00) =3D +1.3533528323661e-01
+ expD(-1.9000000001000e+00) =3D +1.4956861920768e-01
+ expD(-1.8000000002000e+00) =3D +1.6529888818853e-01
+ expD(-1.7000000003000e+00) =3D +1.8268352399793e-01
+ expD(-1.6000000004000e+00) =3D +2.0189651791390e-01
+ expD(-1.5000000005000e+00) =3D +2.2313016003686e-01
+ expD(-1.4000000006000e+00) =3D +2.4659696379365e-01
+ expD(-1.3000000007000e+00) =3D +2.7253179284324e-01
+ expD(-1.2000000008000e+00) =3D +3.0119421167125e-01
+ expD(-1.1000000009000e+00) =3D +3.3287108339850e-01
+ expD(-1.0000000010000e+00) =3D +3.6787944080356e-01
+ expD(-9.0000000110000e-01) =3D +4.0656965929337e-01
+ expD(-8.0000000120000e-01) =3D +4.4932896357803e-01
+ expD(-7.0000000130000e-01) =3D +4.9658530314585e-01
+ expD(-6.0000000140000e-01) =3D +5.4881163532569e-01
+ expD(-5.0000000150000e-01) =3D +6.0653065880284e-01
+ expD(-4.0000000160000e-01) =3D +6.7032004496313e-01
+ expD(-3.0000000170000e-01) =3D +7.4081821942233e-01
+ expD(-2.0000000180000e-01) =3D +8.1873075160427e-01
+ expD(-1.0000000190000e-01) =3D +9.0483741631677e-01
+ expD(-1.9999992495467e-09) =3D +9.9999999800000e-01
+ expD(+9.9999997900001e-02) =3D +1.1051709157548e+00
+ expD(+1.9999999780000e-01) =3D +1.2214027554731e+00
+ expD(+2.9999999770000e-01) =3D +1.3498588044713e+00
+ expD(+3.9999999760000e-01) =3D +1.4918246940609e+00
+ expD(+4.9999999750000e-01) =3D +1.6487212665783e+00
+ expD(+5.9999999740000e-01) =3D +1.8221187956530e+00
+ expD(+6.9999999730000e-01) =3D +2.0137527020333e+00
+ expD(+7.9999999720000e-01) =3D +2.2255409222610e+00
+ expD(+8.9999999710000e-01) =3D +2.4596031040241e+00
+ expD(+9.9999999700000e-01) =3D +2.7182818203042e+00
+ expD(+1.0999999969000e+00) =3D +3.0041660146335e+00
+ expD(+1.1999999968000e+00) =3D +3.3201169121122e+00
+ expD(+1.2999999967000e+00) =3D +3.6692966555106e+00
+ expD(+1.3999999966000e+00) =3D +4.0551999530570e+00
+ expD(+1.4999999965000e+00) =3D +4.4816890546522e+00
+ expD(+1.5999999964000e+00) =3D +4.9530324065642e+00
+ expD(+1.6999999963000e+00) =3D +5.4739473714736e+00
+ expD(+1.7999999962000e+00) =3D +6.0496474414243e+00
+ expD(+1.8999999961000e+00) =3D +6.6858944162043e+00
+ expD(+1.9999999960000e+00) =3D +7.3890560693744e+00
+ expF( -2.0000e+00) =3D +1.3534e-01
+ expF( -1.9001e+00) =3D +1.4955e-01
+ expF( -1.8002e+00) =3D +1.6527e-01
+ expF( -1.7003e+00) =3D +1.8263e-01
+ expF( -1.6004e+00) =3D +2.0182e-01
+ expF( -1.5005e+00) =3D +2.2302e-01
+ expF( -1.4006e+00) =3D +2.4645e-01
+ expF( -1.3007e+00) =3D +2.7234e-01
+ expF( -1.2008e+00) =3D +3.0095e-01
+ expF( -1.1009e+00) =3D +3.3257e-01
+ expF( -1.0010e+00) =3D +3.6751e-01
+ expF( -9.0110e-01) =3D +4.0612e-01
+ expF( -8.0120e-01) =3D +4.4879e-01
+ expF( -7.0130e-01) =3D +4.9594e-01
+ expF( -6.0140e-01) =3D +5.4804e-01
+ expF( -5.0150e-01) =3D +6.0562e-01
+ expF( -4.0160e-01) =3D +6.6925e-01
+ expF( -3.0170e-01) =3D +7.3956e-01
+ expF( -2.0180e-01) =3D +8.1726e-01
+ expF( -1.0190e-01) =3D +9.0312e-01
+ expF( -1.9999e-03) =3D +9.9800e-01
+ expF( +9.7900e-02) =3D +1.1029e+00
+ expF( +1.9780e-01) =3D +1.2187e+00
+ expF( +2.9770e-01) =3D +1.3468e+00
+ expF( +3.9760e-01) =3D +1.4882e+00
+ expF( +4.9750e-01) =3D +1.6446e+00
+ expF( +5.9740e-01) =3D +1.8174e+00
+ expF( +6.9730e-01) =3D +2.0083e+00
+ expF( +7.9720e-01) =3D +2.2193e+00
+ expF( +8.9710e-01) =3D +2.4525e+00
+ expF( +9.9700e-01) =3D +2.7101e+00
+ expF( +1.0969e+00) =3D +2.9949e+00
+ expF( +1.1968e+00) =3D +3.3095e+00
+ expF( +1.2967e+00) =3D +3.6572e+00
+ expF( +1.3966e+00) =3D +4.0414e+00
+ expF( +1.4965e+00) =3D +4.4660e+00
+ expF( +1.5964e+00) =3D +4.9352e+00
+ expF( +1.6963e+00) =3D +5.4537e+00
+ expF( +1.7962e+00) =3D +6.0267e+00
+ expF( +1.8961e+00) =3D +6.6599e+00
+ expF( +1.9960e+00) =3D +7.3596e+00
+ sqrtD(+0.0000000000000e+00) =3D +0.0000000000000e+00
+ sqrtD(+9.9999999900000e-02) =3D +3.1622776585872e-01
+ sqrtD(+1.9999999980000e-01) =3D +4.4721359527635e-01
+ sqrtD(+2.9999999970000e-01) =3D +5.4772255723130e-01
+ sqrtD(+3.9999999960000e-01) =3D +6.3245553171745e-01
+ sqrtD(+4.9999999950000e-01) =3D +7.0710678083299e-01
+ sqrtD(+5.9999999940000e-01) =3D +7.7459666885419e-01
+ sqrtD(+6.9999999930000e-01) =3D +8.3666002611575e-01
+ sqrtD(+7.9999999920000e-01) =3D +8.9442719055270e-01
+ sqrtD(+8.9999999910000e-01) =3D +9.4868329757617e-01
+ sqrtD(+9.9999999900000e-01) =3D +9.9999999950000e-01
+ sqrtD(+1.0999999989000e+00) =3D +1.0488088476457e+00
+ sqrtD(+1.1999999988000e+00) =3D +1.0954451144626e+00
+ sqrtD(+1.2999999987000e+00) =3D +1.1401754245291e+00
+ sqrtD(+1.3999999986000e+00) =3D +1.1832159560283e+00
+ sqrtD(+1.4999999985000e+00) =3D +1.2247448707792e+00
+ sqrtD(+1.5999999984000e+00) =3D +1.2649110634349e+00
+ sqrtD(+1.6999999983000e+00) =3D +1.3038404803886e+00
+ sqrtD(+1.7999999982000e+00) =3D +1.3416407858291e+00
+ sqrtD(+1.8999999981000e+00) =3D +1.3784048745198e+00
+ sqrtD(+1.9999999980000e+00) =3D +1.4142135616660e+00
+ sqrtF( +0.0000e+00) =3D +0.0000e+00
+ sqrtF( +9.9900e-02) =3D +3.1607e-01
+ sqrtF( +1.9980e-01) =3D +4.4699e-01
+ sqrtF( +2.9970e-01) =3D +5.4745e-01
+ sqrtF( +3.9960e-01) =3D +6.3214e-01
+ sqrtF( +4.9950e-01) =3D +7.0675e-01
+ sqrtF( +5.9940e-01) =3D +7.7421e-01
+ sqrtF( +6.9930e-01) =3D +8.3624e-01
+ sqrtF( +7.9920e-01) =3D +8.9398e-01
+ sqrtF( +8.9910e-01) =3D +9.4821e-01
+ sqrtF( +9.9900e-01) =3D +9.9950e-01
+ sqrtF( +1.0989e+00) =3D +1.0483e+00
+ sqrtF( +1.1988e+00) =3D +1.0949e+00
+ sqrtF( +1.2987e+00) =3D +1.1396e+00
+ sqrtF( +1.3986e+00) =3D +1.1826e+00
+ sqrtF( +1.4985e+00) =3D +1.2241e+00
+ sqrtF( +1.5984e+00) =3D +1.2643e+00
+ sqrtF( +1.6983e+00) =3D +1.3032e+00
+ sqrtF( +1.7982e+00) =3D +1.3410e+00
+ sqrtF( +1.8981e+00) =3D +1.3777e+00
+ sqrtF( +1.9980e+00) =3D +1.4135e+00
+ logD(+0.0000000000000e+00) =3D -inf
+ logD(+9.9999999900000e-02) =3D -2.3025850939940e+00
+ logD(+1.9999999980000e-01) =3D -1.6094379134341e+00
+ logD(+2.9999999970000e-01) =3D -1.2039728053259e+00
+ logD(+3.9999999960000e-01) =3D -9.1629073287415e-01
+ logD(+4.9999999950000e-01) =3D -6.9314718155995e-01
+ logD(+5.9999999940000e-01) =3D -5.1082562476599e-01
+ logD(+6.9999999930000e-01) =3D -3.5667494493873e-01
+ logD(+7.9999999920000e-01) =3D -2.2314355231421e-01
+ logD(+8.9999999910000e-01) =3D -1.0536051665783e-01
+ logD(+9.9999999900000e-01) =3D -1.0000000832404e-09
+ logD(+1.0999999989000e+00) =3D +9.5310178804325e-02
+ logD(+1.1999999988000e+00) =3D +1.8232155579395e-01
+ logD(+1.2999999987000e+00) =3D +2.6236426346749e-01
+ logD(+1.3999999986000e+00) =3D +3.3647223562121e-01
+ logD(+1.4999999985000e+00) =3D +4.0546510710816e-01
+ logD(+1.5999999984000e+00) =3D +4.7000362824574e-01
+ logD(+1.6999999983000e+00) =3D +5.3062825006217e-01
+ logD(+1.7999999982000e+00) =3D +5.8778666390212e-01
+ logD(+1.8999999981000e+00) =3D +6.4185388517240e-01
+ logD(+1.9999999980000e+00) =3D +6.9314717955995e-01
+ logF( +0.0000e+00) =3D -inf
+ logF( +9.9900e-02) =3D -2.3036e+00
+ logF( +1.9980e-01) =3D -1.6104e+00
+ logF( +2.9970e-01) =3D -1.2050e+00
+ logF( +3.9960e-01) =3D -9.1729e-01
+ logF( +4.9950e-01) =3D -6.9415e-01
+ logF( +5.9940e-01) =3D -5.1183e-01
+ logF( +6.9930e-01) =3D -3.5768e-01
+ logF( +7.9920e-01) =3D -2.2414e-01
+ logF( +8.9910e-01) =3D -1.0636e-01
+ logF( +9.9900e-01) =3D -1.0005e-03
+ logF( +1.0989e+00) =3D +9.4310e-02
+ logF( +1.1988e+00) =3D +1.8132e-01
+ logF( +1.2987e+00) =3D +2.6136e-01
+ logF( +1.3986e+00) =3D +3.3547e-01
+ logF( +1.4985e+00) =3D +4.0446e-01
+ logF( +1.5984e+00) =3D +4.6900e-01
+ logF( +1.6983e+00) =3D +5.2963e-01
+ logF( +1.7982e+00) =3D +5.8679e-01
+ logF( +1.8981e+00) =3D +6.4085e-01
+ logF( +1.9980e+00) =3D +6.9215e-01
+log10D(+0.0000000000000e+00) =3D -inf
+log10D(+9.9999999900000e-02) =3D -1.0000000004343e+00
+log10D(+1.9999999980000e-01) =3D -6.9897000477031e-01
+log10D(+2.9999999970000e-01) =3D -5.2287874571463e-01
+log10D(+3.9999999960000e-01) =3D -3.9794000910633e-01
+log10D(+4.9999999950000e-01) =3D -3.0102999609828e-01
+log10D(+5.9999999940000e-01) =3D -2.2184875005065e-01
+log10D(+6.9999999930000e-01) =3D -1.5490196042004e-01
+log10D(+7.9999999920000e-01) =3D -9.6910013442351e-02
+log10D(+8.9999999910000e-01) =3D -4.5757490994970e-02
+log10D(+9.9999999900000e-01) =3D -4.3429451805409e-10
+log10D(+1.0999999989000e+00) =3D +4.1392684723931e-02
+log10D(+1.1999999988000e+00) =3D +7.9181245613330e-02
+log10D(+1.2999999987000e+00) =3D +1.1394335187254e-01
+log10D(+1.3999999986000e+00) =3D +1.4612803524394e-01
+log10D(+1.4999999985000e+00) =3D +1.7609125862139e-01
+log10D(+1.5999999984000e+00) =3D +2.0411998222163e-01
+log10D(+1.6999999983000e+00) =3D +2.3044892094398e-01
+log10D(+1.7999999982000e+00) =3D +2.5527250466901e-01
+log10D(+1.8999999981000e+00) =3D +2.7875360051853e-01
+log10D(+1.9999999980000e+00) =3D +3.0102999522969e-01
+log10F( +0.0000e+00) =3D -inf
+log10F( +9.9900e-02) =3D -1.0004e+00
+log10F( +1.9980e-01) =3D -6.9940e-01
+log10F( +2.9970e-01) =3D -5.2331e-01
+log10F( +3.9960e-01) =3D -3.9837e-01
+log10F( +4.9950e-01) =3D -3.0146e-01
+log10F( +5.9940e-01) =3D -2.2228e-01
+log10F( +6.9930e-01) =3D -1.5534e-01
+log10F( +7.9920e-01) =3D -9.7345e-02
+log10F( +8.9910e-01) =3D -4.6192e-02
+log10F( +9.9900e-01) =3D -4.3451e-04
+log10F( +1.0989e+00) =3D +4.0958e-02
+log10F( +1.1988e+00) =3D +7.8747e-02
+log10F( +1.2987e+00) =3D +1.1351e-01
+log10F( +1.3986e+00) =3D +1.4569e-01
+log10F( +1.4985e+00) =3D +1.7566e-01
+log10F( +1.5984e+00) =3D +2.0369e-01
+log10F( +1.6983e+00) =3D +2.3001e-01
+log10F( +1.7982e+00) =3D +2.5484e-01
+log10F( +1.8981e+00) =3D +2.7832e-01
+log10F( +1.9980e+00) =3D +3.0060e-01
+ asinD(-1.0000000000000e+00) =3D -1.5707963267949e+00
+ asinD(-9.0000000010000e-01) =3D -1.1197695152281e+00
+ asinD(-8.0000000020000e-01) =3D -9.2729521833495e-01
+ asinD(-7.0000000030000e-01) =3D -7.7539749703084e-01
+ asinD(-6.0000000040000e-01) =3D -6.4350110929328e-01
+ asinD(-5.0000000050000e-01) =3D -5.2359877617565e-01
+ asinD(-4.0000000060000e-01) =3D -4.1151684672214e-01
+ asinD(-3.0000000070000e-01) =3D -3.0469265474920e-01
+ asinD(-2.0000000080000e-01) =3D -2.0135792160683e-01
+ asinD(-1.0000000090000e-01) =3D -1.0016742206609e-01
+ asinD(-1.0000000549848e-09) =3D -1.0000000549848e-09
+ asinD(+9.9999998900000e-02) =3D +1.0016742005602e-01
+ asinD(+1.9999999880000e-01) =3D +2.0135791956559e-01
+ asinD(+2.9999999870000e-01) =3D +3.0469265265263e-01
+ asinD(+3.9999999860000e-01) =3D +4.1151684453996e-01
+ asinD(+4.9999999850000e-01) =3D +5.2359877386625e-01
+ asinD(+5.9999999840000e-01) =3D +6.4350110679328e-01
+ asinD(+6.9999999830000e-01) =3D +7.7539749423028e-01
+ asinD(+7.9999999820000e-01) =3D +9.2729521500161e-01
+ asinD(+8.9999999810000e-01) =3D +1.1197695106397e+00
+ asinD(+9.9999999800000e-01) =3D +1.5707330812408e+00
+ asinF( -1.0000e+00) =3D -1.5708e+00
+ asinF( -9.0010e-01) =3D -1.1200e+00
+ asinF( -8.0020e-01) =3D -9.2763e-01
+ asinF( -7.0030e-01) =3D -7.7582e-01
+ asinF( -6.0040e-01) =3D -6.4400e-01
+ asinF( -5.0050e-01) =3D -5.2418e-01
+ asinF( -4.0060e-01) =3D -4.1217e-01
+ asinF( -3.0070e-01) =3D -3.0543e-01
+ asinF( -2.0080e-01) =3D -2.0217e-01
+ asinF( -1.0090e-01) =3D -1.0107e-01
+ asinF( -9.9994e-04) =3D -9.9994e-04
+ asinF( +9.8900e-02) =3D +9.9062e-02
+ asinF( +1.9880e-01) =3D +2.0013e-01
+ asinF( +2.9870e-01) =3D +3.0333e-01
+ asinF( +3.9860e-01) =3D +4.0999e-01
+ asinF( +4.9850e-01) =3D +5.2187e-01
+ asinF( +5.9840e-01) =3D +6.4150e-01
+ asinF( +6.9830e-01) =3D +7.7302e-01
+ asinF( +7.9820e-01) =3D +9.2430e-01
+ asinF( +8.9810e-01) =3D +1.1154e+00
+ asinF( +9.9800e-01) =3D +1.5075e+00
+ acosD(-1.0000000000000e+00) =3D +3.1415926536e+00
+ acosD(-9.0000010000000e-01) =3D +2.6905660712e+00
+ acosD(-8.0000020000000e-01) =3D +2.4980918781e+00
+ acosD(-7.0000030000000e-01) =3D +2.3461942435e+00
+ acosD(-6.0000040000000e-01) =3D +2.2142979356e+00
+ acosD(-5.0000050000000e-01) =3D +2.0943956797e+00
+ acosD(-4.0000060000000e-01) =3D +1.9823138275e+00
+ acosD(-3.0000070000000e-01) =3D +1.8754897146e+00
+ acosD(-2.0000080000000e-01) =3D +1.7721550641e+00
+ acosD(-1.0000090000000e-01) =3D +1.6709646525e+00
+ acosD(-9.9999999977896e-07) =3D +1.5707973268e+00
+ acosD(+9.9998900000000e-02) =3D +1.4706300112e+00
+ acosD(+1.9999880000000e-01) =3D +1.3694396307e+00
+ acosD(+2.9999870000000e-01) =3D +1.2661050355e+00
+ acosD(+3.9999860000000e-01) =3D +1.1592810083e+00
+ acosD(+4.9999850000000e-01) =3D +1.0471992832e+00
+ acosD(+5.9999840000000e-01) =3D +9.2729721800e-01
+ acosD(+6.9999830000000e-01) =3D +7.9540121066e-01
+ acosD(+7.9999820000000e-01) =3D +6.4350410879e-01
+ acosD(+8.9999810000000e-01) =3D +4.5103117068e-01
+ acosD(+9.9999800000000e-01) =3D +2.0000003331e-03
+ acosF( -1.0000e+00) =3D +3.1416e+00
+ acosF( -9.0010e-01) =3D +2.6908e+00
+ acosF( -8.0020e-01) =3D +2.4984e+00
+ acosF( -7.0030e-01) =3D +2.3466e+00
+ acosF( -6.0040e-01) =3D +2.2148e+00
+ acosF( -5.0050e-01) =3D +2.0950e+00
+ acosF( -4.0060e-01) =3D +1.9830e+00
+ acosF( -3.0070e-01) =3D +1.8762e+00
+ acosF( -2.0080e-01) =3D +1.7730e+00
+ acosF( -1.0090e-01) =3D +1.6719e+00
+ acosF( -9.9994e-04) =3D +1.5718e+00
+ acosF( +9.8900e-02) =3D +1.4717e+00
+ acosF( +1.9880e-01) =3D +1.3707e+00
+ acosF( +2.9870e-01) =3D +1.2675e+00
+ acosF( +3.9860e-01) =3D +1.1608e+00
+ acosF( +4.9850e-01) =3D +1.0489e+00
+ acosF( +5.9840e-01) =3D +9.2929e-01
+ acosF( +6.9830e-01) =3D +7.9778e-01
+ acosF( +7.9820e-01) =3D +6.4650e-01
+ acosF( +8.9810e-01) =3D +4.5537e-01
+ acosF( +9.9800e-01) =3D +6.3255e-02
+ atanD(-1.0000000000000e+00) =3D -7.8539816339745e-01
+ atanD(-9.0000000010000e-01) =3D -7.3281510184176e-01
+ atanD(-8.0000000020000e-01) =3D -6.7474094234550e-01
+ atanD(-7.0000000030000e-01) =3D -6.1072596459055e-01
+ atanD(-6.0000000040000e-01) =3D -5.4041950056470e-01
+ atanD(-5.0000000050000e-01) =3D -4.6364760940081e-01
+ atanD(-4.0000000060000e-01) =3D -3.8050637762961e-01
+ atanD(-3.0000000070000e-01) =3D -2.9145679512007e-01
+ atanD(-2.0000000080000e-01) =3D -1.9739556061911e-01
+ atanD(-1.0000000090000e-01) =3D -9.9668653382251e-02
+ atanD(-1.0000000549848e-09) =3D -1.0000000549848e-09
+ atanD(+9.9999998900000e-02) =3D +9.9668651402053e-02
+ atanD(+1.9999999880000e-01) =3D +1.9739555869603e-01
+ atanD(+2.9999999870000e-01) =3D +2.9145679328521e-01
+ atanD(+3.9999999860000e-01) =3D +3.8050637590547e-01
+ atanD(+4.9999999850000e-01) =3D +4.6364760780081e-01
+ atanD(+5.9999999840000e-01) =3D +5.4041949909411e-01
+ atanD(+6.9999999830000e-01) =3D +6.1072596324827e-01
+ atanD(+7.9999999820000e-01) =3D +6.7474094112599e-01
+ atanD(+8.9999999810000e-01) =3D +7.3281510073678e-01
+ atanD(+9.9999999800000e-01) =3D +7.8539816239745e-01
+ atanF( -1.0000e+00) =3D -7.8540e-01
+ atanF( -9.0010e-01) =3D -7.3287e-01
+ atanF( -8.0020e-01) =3D -6.7486e-01
+ atanF( -7.0030e-01) =3D -6.1093e-01
+ atanF( -6.0040e-01) =3D -5.4071e-01
+ atanF( -5.0050e-01) =3D -4.6405e-01
+ atanF( -4.0060e-01) =3D -3.8102e-01
+ atanF( -3.0070e-01) =3D -2.9210e-01
+ atanF( -2.0080e-01) =3D -1.9816e-01
+ atanF( -1.0090e-01) =3D -1.0056e-01
+ atanF( -9.9994e-04) =3D -9.9994e-04
+ atanF( +9.8900e-02) =3D +9.8579e-02
+ atanF( +1.9880e-01) =3D +1.9624e-01
+ atanF( +2.9870e-01) =3D +2.9026e-01
+ atanF( +3.9860e-01) =3D +3.7930e-01
+ atanF( +4.9850e-01) =3D +4.6245e-01
+ atanF( +5.9840e-01) =3D +5.3924e-01
+ atanF( +6.9830e-01) =3D +6.0958e-01
+ atanF( +7.9820e-01) =3D +6.7364e-01
+ atanF( +8.9810e-01) =3D +7.3176e-01
+ atanF( +9.9800e-01) =3D +7.8440e-01
+atan2D(-1.0000000000000e+00) =3D -7.8539816339745e-01
+atan2D(-9.0000000010000e-01) =3D -7.3281510184176e-01
+atan2D(-8.0000000020000e-01) =3D -6.7474094234550e-01
+atan2D(-7.0000000030000e-01) =3D -6.1072596459055e-01
+atan2D(-6.0000000040000e-01) =3D -5.4041950056470e-01
+atan2D(-5.0000000050000e-01) =3D -4.6364760940081e-01
+atan2D(-4.0000000060000e-01) =3D -3.8050637762961e-01
+atan2D(-3.0000000070000e-01) =3D -2.9145679512007e-01
+atan2D(-2.0000000080000e-01) =3D -1.9739556061911e-01
+atan2D(-1.0000000090000e-01) =3D -9.9668653382251e-02
+atan2D(-1.0000000549848e-09) =3D -1.0000000549848e-09
+atan2D(+9.9999998900000e-02) =3D +9.9668651402053e-02
+atan2D(+1.9999999880000e-01) =3D +1.9739555869603e-01
+atan2D(+2.9999999870000e-01) =3D +2.9145679328521e-01
+atan2D(+3.9999999860000e-01) =3D +3.8050637590547e-01
+atan2D(+4.9999999850000e-01) =3D +4.6364760780081e-01
+atan2D(+5.9999999840000e-01) =3D +5.4041949909411e-01
+atan2D(+6.9999999830000e-01) =3D +6.1072596324827e-01
+atan2D(+7.9999999820000e-01) =3D +6.7474094112599e-01
+atan2D(+8.9999999810000e-01) =3D +7.3281510073678e-01
+atan2D(+9.9999999800000e-01) =3D +7.8539816239745e-01
+atan2F( -1.0000e+00) =3D -7.8540e-01
+atan2F( -9.0010e-01) =3D -7.3287e-01
+atan2F( -8.0020e-01) =3D -6.7486e-01
+atan2F( -7.0030e-01) =3D -6.1093e-01
+atan2F( -6.0040e-01) =3D -5.4071e-01
+atan2F( -5.0050e-01) =3D -4.6405e-01
+atan2F( -4.0060e-01) =3D -3.8102e-01
+atan2F( -3.0070e-01) =3D -2.9210e-01
+atan2F( -2.0080e-01) =3D -1.9816e-01
+atan2F( -1.0090e-01) =3D -1.0056e-01
+atan2F( -9.9994e-04) =3D -9.9994e-04
+atan2F( +9.8900e-02) =3D +9.8579e-02
+atan2F( +1.9880e-01) =3D +1.9624e-01
+atan2F( +2.9870e-01) =3D +2.9026e-01
+atan2F( +3.9860e-01) =3D +3.7930e-01
+atan2F( +4.9850e-01) =3D +4.6245e-01
+atan2F( +5.9840e-01) =3D +5.3924e-01
+atan2F( +6.9830e-01) =3D +6.0958e-01
+atan2F( +7.9820e-01) =3D +6.7364e-01
+atan2F( +8.9810e-01) =3D +7.3176e-01
+atan2F( +9.9800e-01) =3D +7.8440e-01
Added: trunk/memcheck/tests/vcpu_fnfns.vgtest
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/tests/vcpu_fnfns.vgtest (rev 0=
)
+++ trunk/memcheck/tests/vcpu_fnfns.vgtest 2006-01-24 00:40:35 UTC (rev 5=
590)
@@ -0,0 +1,2 @@
+prog: vcpu_fnfns
+vgopts: -q
|