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From: Tom H. <th...@cy...> - 2005-11-14 03:17:02
|
Nightly build on aston ( x86_64, Fedora Core 3 ) started at 2005-11-14 03:05:06 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... failed Last 20 lines of verbose log follow echo -c priv/host-x86/hdefs.c gcc -g -O -Wall -Wmissing-prototypes -Wshadow -Winline -Wpointer-arith -Wbad-function-cast -Wcast-qual -Wcast-align -Wmissing-declarations -m32 -O -g -Wmissing-prototypes -Winline -Wall -Wshadow -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations -Ipub -Ipriv -o priv/host-amd64/hdefs.o \ -c priv/host-amd64/hdefs.c gcc -g -O -Wall -Wmissing-prototypes -Wshadow -Winline -Wpointer-arith -Wbad-function-cast -Wcast-qual -Wcast-align -Wmissing-declarations -m32 -O -g -Wmissing-prototypes -Winline -Wall -Wshadow -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations -Ipub -Ipriv -o priv/host-arm/hdefs.o \ -c priv/host-arm/hdefs.c gcc -g -O -Wall -Wmissing-prototypes -Wshadow -Winline -Wpointer-arith -Wbad-function-cast -Wcast-qual -Wcast-align -Wmissing-declarations -m32 -O -g -Wmissing-prototypes -Winline -Wall -Wshadow -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations -Ipub -Ipriv -o priv/host-ppc32/hdefs.o \ -c priv/host-ppc32/hdefs.c priv/host-ppc32/hdefs.c:696: error: conflicting types for 'showPPC32AvFpOp' priv/host-ppc32/hdefs.h:420: error: previous declaration of 'showPPC32AvFpOp' was here priv/host-ppc32/hdefs.c:696: error: conflicting types for 'showPPC32AvFpOp' priv/host-ppc32/hdefs.h:420: error: previous declaration of 'showPPC32AvFpOp' was here make[4]: *** [priv/host-ppc32/hdefs.o] Error 1 make[4]: Leaving directory `/tmp/valgrind.19593/valgrind/VEX' make[3]: *** [../VEX/libvex_x86_linux.a] Error 2 make[3]: Leaving directory `/tmp/valgrind.19593/valgrind/memcheck' make[2]: *** [all-recursive] Error 1 make[2]: Leaving directory `/tmp/valgrind.19593/valgrind/memcheck' make[1]: *** [all-recursive] Error 1 make[1]: Leaving directory `/tmp/valgrind.19593/valgrind' make: *** [all] Error 2 |
|
From: Tom H. <th...@cy...> - 2005-11-14 03:14:10
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2005-11-14 03:00:03 GMT Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Last 20 lines of verbose log follow echo make[3]: Leaving directory `/tmp/valgrind.23458/valgrind/docs/lib' Making check in images make[3]: Entering directory `/tmp/valgrind.23458/valgrind/docs/images' make[3]: Nothing to be done for `check'. make[3]: Leaving directory `/tmp/valgrind.23458/valgrind/docs/images' Making check in internals make[3]: Entering directory `/tmp/valgrind.23458/valgrind/docs/internals' make[3]: Nothing to be done for `check'. make[3]: Leaving directory `/tmp/valgrind.23458/valgrind/docs/internals' make[3]: Entering directory `/tmp/valgrind.23458/valgrind/docs' make[3]: Nothing to be done for `check-am'. make[3]: Leaving directory `/tmp/valgrind.23458/valgrind/docs' make[2]: Leaving directory `/tmp/valgrind.23458/valgrind/docs' make[1]: Leaving directory `/tmp/valgrind.23458/valgrind' /usr/bin/perl tests/vg_regtest memcheck cachegrind massif lackey none -- Running tests in memcheck/tests ------------------------------------ addressable: valgrind ./addressable Bad line in insn_basic.vgtest: link ../../../none/tests/amd64/insn_basic.vgtest -- Running tests in memcheck/tests/amd64 ------------------------------ make: *** [regtest] Error 255 |
|
From: <sv...@va...> - 2005-11-14 03:00:41
|
Author: cerion
Date: 2005-11-14 03:00:35 +0000 (Mon, 14 Nov 2005)
New Revision: 5121
Log:
Couple more irops for memcheck.
Modified:
trunk/memcheck/mc_translate.c
Modified: trunk/memcheck/mc_translate.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/mc_translate.c 2005-11-14 02:43:09 UTC (rev 5120)
+++ trunk/memcheck/mc_translate.c 2005-11-14 03:00:35 UTC (rev 5121)
@@ -1784,6 +1784,8 @@
case Iop_CmpLE32Fx4:
case Iop_CmpEQ32Fx4:
case Iop_CmpUN32Fx4:
+ case Iop_CmpGT32Fx4:
+ case Iop_CmpGE32Fx4:
case Iop_Add32Fx4:
return binary32Fx4(mce, vatom1, vatom2); =20
=20
|
|
From: <sv...@va...> - 2005-11-14 02:43:13
|
Author: cerion
Date: 2005-11-14 02:43:09 +0000 (Mon, 14 Nov 2005)
New Revision: 5120
Log:
comment out altivec tests for unsupported insns
Modified:
trunk/none/tests/ppc32/jm-insns.c
Modified: trunk/none/tests/ppc32/jm-insns.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/jm-insns.c 2005-11-13 18:51:31 UTC (rev 5119)
+++ trunk/none/tests/ppc32/jm-insns.c 2005-11-14 02:43:09 UTC (rev 5120)
@@ -2540,14 +2540,14 @@
}
=20
static test_t tests_afa_ops_one[] =3D {
- { &test_vrfin , " vrfin", },
- { &test_vrfiz , " vrfiz", },
- { &test_vrfip , " vrfip", },
- { &test_vrfim , " vrfim", },
+ // { &test_vrfin , " vrfin", }, // TODO: Not ye=
t supported
+ // { &test_vrfiz , " vrfiz", }, // TODO: Not ye=
t supported
+ // { &test_vrfip , " vrfip", }, // TODO: Not ye=
t supported
+ // { &test_vrfim , " vrfim", }, // TODO: Not ye=
t supported
{ &test_vrefp , " vrefp", },
{ &test_vrsqrtefp , " vrsqrtefp", },
- { &test_vlogefp , " vlogefp", },
- { &test_vexptefp , " vexptefp", },
+ // { &test_vlogefp , " vlogefp", }, // TODO: Not ye=
t supported
+ // { &test_vexptefp , " vexptefp", }, // TODO: Not ye=
t supported
{ NULL, NULL, },
};
#endif /* defined (HAS_ALTIVEC) */
@@ -6382,10 +6382,6 @@
#endif
=20
=20
- // NO FLOAT ALTIVEC
- flags.faltivec =3D 0;
-
-
build_iargs_table();
build_fargs_table();
build_ii16_table();
|
|
From: <sv...@va...> - 2005-11-14 02:37:53
|
Author: cerion
Date: 2005-11-14 02:37:44 +0000 (Mon, 14 Nov 2005)
New Revision: 1457
Log:
More av insns: vmaddfp, vnmsubfp
Rough 'n ready IR used - results will be rounded along the way, not just =
at the end of the calculations, giving some error.
Modified:
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-11-14 00:44:47 UTC (rev 1456)
+++ trunk/priv/guest-ppc32/toIR.c 2005-11-14 02:37:44 UTC (rev 1457)
@@ -6806,13 +6806,21 @@
switch (opc2) {
case 0x2E: // vmaddfp (Multiply Add FP, AV p177)
DIP("vmaddfp v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vC_addr, vB_add=
r);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Add32Fx4, mkexpr(vB),
+ binop(Iop_Mul32Fx4, mkexpr(vA), mkexpr(vC)=
)) );
+ return True;
=20
- case 0x2F: // vnmsubfp (Negative Multiply-Subtract FP, AV p215)
+ case 0x2F: { // vnmsubfp (Negative Multiply-Subtract FP, AV p215)
+ IRTemp zeros =3D newTemp(Ity_V128);
DIP("vnmsubfp v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vC_addr, vB_ad=
dr);
- DIP(" =3D> not implemented\n");
- return False;
+ assign( zeros, unop(Iop_Dup32x4, mkU32(0)) );
+ putVReg( vD_addr,
+ binop(Iop_Sub32Fx4, mkexpr(zeros),
+ binop(Iop_Sub32Fx4,
+ binop(Iop_Mul32Fx4, mkexpr(vA), mkexpr(vC)),
+ mkexpr(vB))) );
+ return True;
+ }
=20
default:
break; // Fall through...
|
|
From: <sv...@va...> - 2005-11-14 00:44:50
|
Author: cerion
Date: 2005-11-14 00:44:47 +0000 (Mon, 14 Nov 2005)
New Revision: 1456
Log:
Frontend
--------
Added a bunch of altivec float insns:
vaddfp, vsubfp, vmaxfp, vminfp,
vrefp, vrsqrtefp
vcmpgefp, vcmpgtfp, vcmpbfp
Made use of fact that ppc backend for compare insns return
zero'd lanes if either of the corresponding args is a nan.
- perhaps better to have an irop Iop_isNan32Fx4, but seems unecessary wo=
rk until we get into running non-native code through vex.
- better still, tighten down the spec for compare irops wrt nan
Backend
-------
Separated av float ops to own insn group - they're only ever type 32x4
Added av float unary insns
Added av float cmp insns - for irops that don't map directly to native in=
sns, native behaviour wrt nan's is followed, requiring lane value=3D=3Dna=
n comparisons for each argument vector.
Modified:
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/hdefs.h
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-11-14 00:35:59 UTC (rev 1455)
+++ trunk/priv/guest-ppc32/toIR.c 2005-11-14 00:44:47 UTC (rev 1456)
@@ -1386,7 +1386,7 @@
=20
=20
/* Set the CR6 flags following an AltiVec compare operation. */
-static void set_AV_CR6 ( IRExpr* result )
+static void set_AV_CR6 ( IRExpr* result, Bool test_all_ones )
{
/* CR6[0:3] =3D {all_ones, 0, all_zeros, 0}
all_ones =3D (v[0] && v[1] && v[2] && v[3])
@@ -1406,13 +1406,6 @@
assign( v2, binop(Iop_ShrV128, result, mkU8(64)) );
assign( v3, binop(Iop_ShrV128, result, mkU8(96)) );
=20
- assign( rOnes, unop(Iop_1Uto8,
- binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF),
- unop(Iop_V128to32,
- binop(Iop_AndV128,
- binop(Iop_AndV128, mkexpr(v0), mkexpr(v1)),
- binop(Iop_AndV128, mkexpr(v2), mkexpr(v3)))))) );
-
assign( rZeros, unop(Iop_1Uto8,
binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF),
unop(Iop_Not32,
@@ -1422,9 +1415,19 @@
binop(Iop_OrV128, mkexpr(v2), mkexpr(v3))))
))) );
=20
- putCR321( 6, binop(Iop_Or8,
- binop(Iop_Shl8, mkexpr(rOnes), mkU8(3)),
- binop(Iop_Shl8, mkexpr(rZeros), mkU8(1))) );
+ if (test_all_ones) {
+ assign( rOnes, unop(Iop_1Uto8,
+ binop(Iop_CmpEQ32, mkU32(0xFFFFFFFF),
+ unop(Iop_V128to32,
+ binop(Iop_AndV128,
+ binop(Iop_AndV128, mkexpr(v0), mkexpr(v1)),
+ binop(Iop_AndV128, mkexpr(v2), mkexpr(v3))))))=
);
+ putCR321( 6, binop(Iop_Or8,
+ binop(Iop_Shl8, mkexpr(rOnes), mkU8(3)),
+ binop(Iop_Shl8, mkexpr(rZeros), mkU8(1))) );
+ } else {
+ putCR321( 6, binop(Iop_Shl8, mkexpr(rZeros), mkU8(1)) );
+ }
putCR0( 6, mkU8(0) );
}=20
=20
@@ -5954,7 +5957,7 @@
putVReg( vD_addr, mkexpr(vD) );
=20
if (flag_Rc) {
- set_AV_CR6( mkexpr(vD) );
+ set_AV_CR6( mkexpr(vD), True );
}
return True;
}
@@ -6787,6 +6790,13 @@
UChar vC_addr =3D toUChar((theInstr >> 6) & 0x1F); /* theInstr[6:10=
] */
UInt opc2=3D0;
=20
+ IRTemp vA =3D newTemp(Ity_V128);
+ IRTemp vB =3D newTemp(Ity_V128);
+ IRTemp vC =3D newTemp(Ity_V128);
+ assign( vA, getVReg(vA_addr));
+ assign( vB, getVReg(vB_addr));
+ assign( vC, getVReg(vC_addr));
+
if (opc1 !=3D 0x4) {
vex_printf("dis_av_fp_arith(PPC32)(instr)\n");
return False;
@@ -6812,23 +6822,23 @@
switch (opc2) {
case 0x00A: // vaddfp (Add FP, AV p137)
DIP("vaddfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Add32Fx4, mkexpr(vA), mkexpr(vB)) );
+ return True;
=20
case 0x04A: // vsubfp (Subtract FP, AV p261)
DIP("vsubfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Sub32Fx4, mkexpr(vA), mkexpr(vB)) );
+ return True;
=20
case 0x40A: // vmaxfp (Maximum FP, AV p178)
DIP("vmaxfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Max32Fx4, mkexpr(vA), mkexpr(vB)) );
+ return True;
=20
case 0x44A: // vminfp (Minimum FP, AV p187)
DIP("vminfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Min32Fx4, mkexpr(vA), mkexpr(vB)) );
+ return True;
=20
default:
break; // Fall through...
@@ -6843,13 +6853,13 @@
switch (opc2) {
case 0x10A: // vrefp (Reciprocal Esimate FP, AV p228)
DIP("vrefp v%d,v%d\n", vD_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, unop(Iop_Recip32Fx4, mkexpr(vB)) );
+ return True;
=20
case 0x14A: // vrsqrtefp (Reciprocal Square Root Estimate FP, AV p237=
)
DIP("vrsqrtefp v%d,v%d\n", vD_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, unop(Iop_RSqrt32Fx4, mkexpr(vB)) );
+ return True;
=20
case 0x18A: // vexptefp (2 Raised to the Exp Est FP, AV p173)
DIP("vexptefp v%d,v%d\n", vD_addr, vB_addr);
@@ -6880,6 +6890,14 @@
UChar flag_Rc =3D toUChar((theInstr >> 10) & 0x1); /* theInstr[10] =
*/
UInt opc2 =3D (theInstr >> 0) & 0x3FF; /* theInstr[0:9]=
*/
=20
+ Bool cmp_bounds =3D False;
+
+ IRTemp vA =3D newTemp(Ity_V128);
+ IRTemp vB =3D newTemp(Ity_V128);
+ IRTemp vD =3D newTemp(Ity_V128);
+ assign( vA, getVReg(vA_addr));
+ assign( vB, getVReg(vB_addr));
+
if (opc1 !=3D 0x4) {
vex_printf("dis_av_fp_cmp(PPC32)(instr)\n");
return False;
@@ -6888,28 +6906,61 @@
switch (opc2) {
case 0x0C6: // vcmpeqfp (Compare Equal-to FP, AV p159)
DIP("vcmpeqfp%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ assign( vD, binop(Iop_CmpEQ32Fx4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x1C6: // vcmpgefp (Compare Greater-than-or-Equal-to FP, AV p163=
)
DIP("vcmpgefp%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ assign( vD, binop(Iop_CmpGE32Fx4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x2C6: // vcmpgtfp (Compare Greater-than FP, AV p164)
DIP("vcmpgtfp%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ assign( vD, binop(Iop_CmpGT32Fx4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
- case 0x3C6: // vcmpbfp (Compare Bounds FP, AV p157)
+ case 0x3C6: { // vcmpbfp (Compare Bounds FP, AV p157)
+ IRTemp gt =3D newTemp(Ity_V128);
+ IRTemp lt =3D newTemp(Ity_V128);
+ IRTemp zeros =3D newTemp(Ity_V128);
DIP("vcmpbfp%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_add=
r, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ cmp_bounds =3D True;
+ assign( zeros, unop(Iop_Dup32x4, mkU32(0)) );
=20
+ /* Note: making use of fact that the ppc backend for compare insns
+ return zero'd lanes if either of the corresponding arg lanes is=
a nan.
+
+ Perhaps better to have an irop Iop_isNan32Fx4, but then we'd
+ need this for the other compares too (vcmpeqfp etc)...
+ Better still, tighten down the spec for compare irops.
+ */
+ assign( gt, unop(Iop_NotV128,
+ binop(Iop_CmpLE32Fx4, mkexpr(vA), mkexpr(vB))) );
+ assign( lt, unop(Iop_NotV128,
+ binop(Iop_CmpGE32Fx4, mkexpr(vA),
+ binop(Iop_Sub32Fx4, mkexpr(zeros), mkexpr(v=
B)))) );
+
+ // finally, just shift gt,lt to correct position
+ assign( vD, binop(Iop_ShlN32x4,
+ binop(Iop_OrV128,
+ binop(Iop_AndV128, mkexpr(gt),
+ unop(Iop_Dup32x4, mkU32(0x2))),
+ binop(Iop_AndV128, mkexpr(lt),
+ unop(Iop_Dup32x4, mkU32(0x1)))),
+ mkU8(30)) );
+ break;
+ }
+
default:
vex_printf("dis_av_fp_cmp(PPC32)(opc2)\n");
return False;
}
+
+ putVReg( vD_addr, mkexpr(vD) );
+
+ if (flag_Rc) {
+ set_AV_CR6( mkexpr(vD), !cmp_bounds );
+ }
return True;
}
=20
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-11-14 00:35:59 UTC (rev 1455)
+++ trunk/priv/host-ppc32/hdefs.c 2005-11-14 00:44:47 UTC (rev 1456)
@@ -689,16 +689,26 @@
case Pav_MRGHI: return "vmrgh"; // b,h,w
case Pav_MRGLO: return "vmrgl"; // b,h,w
=20
+ default: vpanic("showPPC32AvOp");
+ }
+}
+
+HChar* showPPC32AvFpOp ( PPC32AvOp op ) {
+ switch (op) {
/* Floating Point Binary */
- case Pav_ADDF: return "vaddfp";
- case Pav_SUBF: return "vsubfp";
- case Pav_MULF: return "vmaddfp";
- case Pav_MAXF: return "vmaxfp";
- case Pav_MINF: return "vminfp";
- case Pav_CMPEQF: return "vcmpeqfp";
- case Pav_CMPGTF: return "vcmpgtfp";
- case Pav_CMPGEF: return "vcmpgefp";
+ case Pavfp_ADDF: return "vaddfp";
+ case Pavfp_SUBF: return "vsubfp";
+ case Pavfp_MULF: return "vmaddfp";
+ case Pavfp_MAXF: return "vmaxfp";
+ case Pavfp_MINF: return "vminfp";
+ case Pavfp_CMPEQF: return "vcmpeqfp";
+ case Pavfp_CMPGTF: return "vcmpgtfp";
+ case Pavfp_CMPGEF: return "vcmpgefp";
=20
+ /* Floating Point Unary */
+ case Pavfp_RCPF: return "vrefp";
+ case Pavfp_RSQRTF: return "vrsqrtefp";
+
default: vpanic("showPPC32AvOp");
}
}
@@ -931,8 +941,8 @@
return i;
}
PPC32Instr* PPC32Instr_AvUnary ( PPC32AvOp op, HReg dst, HReg src ) {
- PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
- i->tag =3D Pin_AvUnary;
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvUnary;
i->Pin.AvUnary.op =3D op;
i->Pin.AvUnary.dst =3D dst;
i->Pin.AvUnary.src =3D src;
@@ -983,6 +993,14 @@
i->Pin.AvBin32Fx4.srcR =3D srcR;
return i;
}
+PPC32Instr* PPC32Instr_AvUn32Fx4 ( PPC32AvOp op, HReg dst, HReg src ) {
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvUn32Fx4;
+ i->Pin.AvUn32Fx4.op =3D op;
+ i->Pin.AvUn32Fx4.dst =3D dst;
+ i->Pin.AvUn32Fx4.src =3D src;
+ return i;
+}
PPC32Instr* PPC32Instr_AvPerm ( HReg dst, HReg srcL, HReg srcR, HReg ctl=
) {
PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
i->tag =3D Pin_AvPerm;
@@ -1401,6 +1419,12 @@
vex_printf(",");
ppHRegPPC32(i->Pin.AvBin32Fx4.srcR);
return;
+ case Pin_AvUn32Fx4:
+ vex_printf("%s ", showPPC32AvOp(i->Pin.AvUn32Fx4.op));
+ ppHRegPPC32(i->Pin.AvUn32Fx4.dst);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvUn32Fx4.src);
+ return;
case Pin_AvPerm:
vex_printf("vperm ");
ppHRegPPC32(i->Pin.AvPerm.dst);
@@ -1660,14 +1684,18 @@
addHRegUse(u, HRmWrite, i->Pin.AvBin32x4.dst);
addHRegUse(u, HRmRead, i->Pin.AvBin32x4.srcL);
addHRegUse(u, HRmRead, i->Pin.AvBin32x4.srcR);
- if (i->Pin.AvBin32x4.op =3D=3D Pav_MULF)
- addHRegUse(u, HRmWrite, hregPPC32_GPR29());
return;
case Pin_AvBin32Fx4:
addHRegUse(u, HRmWrite, i->Pin.AvBin32Fx4.dst);
addHRegUse(u, HRmRead, i->Pin.AvBin32Fx4.srcL);
addHRegUse(u, HRmRead, i->Pin.AvBin32Fx4.srcR);
+ if (i->Pin.AvBin32Fx4.op =3D=3D Pavfp_MULF)
+ addHRegUse(u, HRmWrite, hregPPC32_GPR29());
return;
+ case Pin_AvUn32Fx4:
+ addHRegUse(u, HRmWrite, i->Pin.AvUn32Fx4.dst);
+ addHRegUse(u, HRmRead, i->Pin.AvUn32Fx4.src);
+ return;
case Pin_AvPerm:
addHRegUse(u, HRmWrite, i->Pin.AvPerm.dst);
addHRegUse(u, HRmRead, i->Pin.AvPerm.srcL);
@@ -1837,6 +1865,10 @@
mapReg(m, &i->Pin.AvBin32Fx4.srcL);
mapReg(m, &i->Pin.AvBin32Fx4.srcR);
return;
+ case Pin_AvUn32Fx4:
+ mapReg(m, &i->Pin.AvUn32Fx4.dst);
+ mapReg(m, &i->Pin.AvUn32Fx4.src);
+ return;
case Pin_AvPerm:
mapReg(m, &i->Pin.AvPerm.dst);
mapReg(m, &i->Pin.AvPerm.srcL);
@@ -2212,8 +2244,8 @@
return emit32(p, theInstr);
}
=20
-static UChar* mkFormVXR ( UChar* p, UInt opc1, UInt r1, UInt r2, UInt Rc=
,
- UInt r3, UInt opc2 )
+static UChar* mkFormVXR ( UChar* p, UInt opc1, UInt r1, UInt r2,
+ UInt r3, UInt Rc, UInt opc2 )
{
UInt theInstr;
vassert(opc1 < 0x40);
@@ -2915,8 +2947,8 @@
p =3D mkFormVX( p, 4, v_dst, v_src, v_src, opc2 );
break;
default:
- p =3D mkFormVX( p, 4, v_dst, 0, v_src, opc2 );
- break;
+ p =3D mkFormVX( p, 4, v_dst, 0, v_src, opc2 );
+ break;
}
goto done;
}
@@ -3100,30 +3132,30 @@
UInt v_srcR =3D vregNo(i->Pin.AvBin32Fx4.srcR);
switch (i->Pin.AvBin32Fx4.op) {
=20
- case Pav_ADDF:
+ case Pavfp_ADDF:
p =3D mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 10 ); // vaddfp
break;
- case Pav_SUBF:
+ case Pavfp_SUBF:
p =3D mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 74 ); // vsubfp
break;
- case Pav_MAXF:
+ case Pavfp_MAXF:
p =3D mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1034 ); // vmaxfp
break;
- case Pav_MINF:
+ case Pavfp_MINF:
p =3D mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1098 ); // vminfp
break;
=20
- case Pav_MULF: {
+ case Pavfp_MULF: {
/* Make a vmulfp from a vmaddfp:
load -0.0 (0x8000_0000) to each 32-bit word of vB
this makes the add a noop.
*/
UInt vB =3D 29; // XXX: Using r29 for temp
- UInt zero_simm =3D 0x80000000;
+ UInt konst =3D 0x1F;
=20
// Better way to load zero_imm?
// vspltisw vB,0x1F (0x1F =3D> each word of vB)
- p =3D mkFormVX( p, 4, vB, zero_simm, 0, 908 );
+ p =3D mkFormVX( p, 4, vB, konst, 0, 908 );
=20
// vslw vB,vB,vB (each word of vB =3D (0x1F << 0x1F) =3D 0x800=
00000
p =3D mkFormVX( p, 4, vB, vB, vB, 388 );
@@ -3132,14 +3164,14 @@
p =3D mkFormVA( p, 4, v_dst, v_srcL, vB, v_srcR, 46 );
break;
}
- case Pav_CMPEQF:
+ case Pavfp_CMPEQF:
p =3D mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 0, 198 ); // vcmp=
eqfp
break;
- case Pav_CMPGTF:
- p =3D mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 1, 710 ); // vcmp=
gtfp
+ case Pavfp_CMPGTF:
+ p =3D mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 0, 710 ); // vcmp=
gtfp
break;
- case Pav_CMPGEF:
- p =3D mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 1, 454 ); // vcmp=
gefp
+ case Pavfp_CMPGEF:
+ p =3D mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 0, 454 ); // vcmp=
gefp
break;
=20
default:
@@ -3148,6 +3180,20 @@
goto done;
}
=20
+ case Pin_AvUn32Fx4: {
+ UInt v_dst =3D vregNo(i->Pin.AvUn32Fx4.dst);
+ UInt v_src =3D vregNo(i->Pin.AvUn32Fx4.src);
+ UInt opc2;
+ switch (i->Pin.AvUn32Fx4.op) {
+ case Pavfp_RCPF: opc2 =3D 266; break; // vrefp
+ case Pavfp_RSQRTF: opc2 =3D 330; break; // vrsqrtefp
+ default:
+ goto bad;
+ }
+ p =3D mkFormVX( p, 4, v_dst, 0, v_src, opc2 );
+ goto done;
+ }
+
case Pin_AvPerm: { // vperm
UInt v_dst =3D vregNo(i->Pin.AvPerm.dst);
UInt v_srcL =3D vregNo(i->Pin.AvPerm.srcL);
Modified: trunk/priv/host-ppc32/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.h 2005-11-14 00:35:59 UTC (rev 1455)
+++ trunk/priv/host-ppc32/hdefs.h 2005-11-14 00:44:47 UTC (rev 1456)
@@ -376,14 +376,10 @@
Pav_UNPCKHPIX, Pav_UNPCKLPIX,
=20
/* Integer Binary */
- Pav_AND, Pav_OR, Pav_XOR, /* Bitwise */
-
+ Pav_AND, Pav_OR, Pav_XOR, /* Bitwise */
Pav_ADDU, Pav_QADDU, Pav_QADDS,
-
Pav_SUBU, Pav_QSUBU, Pav_QSUBS,
-
Pav_OMULU, Pav_OMULS, Pav_EMULU, Pav_EMULS,
-
Pav_AVGU, Pav_AVGS,
Pav_MAXU, Pav_MAXS,
Pav_MINU, Pav_MINS,
@@ -400,18 +396,28 @@
=20
/* Merge */
Pav_MRGHI, Pav_MRGLO,
+ }
+ PPC32AvOp;
=20
+extern HChar* showPPC32AvOp ( PPC32AvOp );
+
+
+/* --------- */
+typedef
+ enum {
+ Pavfp_INVALID,
+
/* Floating point binary */
- Pav_ADDF, Pav_SUBF, Pav_MULF,
- Pav_MAXF, Pav_MINF,
- Pav_CMPEQF, Pav_CMPGTF, Pav_CMPGEF,
+ Pavfp_ADDF, Pavfp_SUBF, Pavfp_MULF,
+ Pavfp_MAXF, Pavfp_MINF,
+ Pavfp_CMPEQF, Pavfp_CMPGTF, Pavfp_CMPGEF,
=20
-//.. /* Floating point unary */
-//.. Xsse_RCPF, Xsse_RSQRTF, Xsse_SQRTF,
+ /* Floating point unary */
+ Pavfp_RCPF, Pavfp_RSQRTF,
}
- PPC32AvOp;
+ PPC32AvFpOp;
=20
-extern HChar* showPPC32AvOp ( PPC32AvOp );
+extern HChar* showPPC32AvFpOp ( PPC32AvFpOp );
=20
=20
/* --------- */
@@ -453,6 +459,7 @@
Pin_AvBin32x4, /* AV binary, 32x4 */
=20
Pin_AvBin32Fx4, /* AV FP binary, 32Fx4 */
+ Pin_AvUn32Fx4, /* AV FP unary, 32Fx4 */
=20
Pin_AvPerm, /* AV permute (shuffle) */
Pin_AvSel, /* AV select */
@@ -672,11 +679,16 @@
HReg srcR;
} AvBin32x4;
struct {
- PPC32AvOp op;
+ PPC32AvFpOp op;
HReg dst;
HReg srcL;
HReg srcR;
} AvBin32Fx4;
+ struct {
+ PPC32AvFpOp op;
+ HReg dst;
+ HReg src;
+ } AvUn32Fx4;
/* Perm,Sel,SlDbl,Splat are all weird AV permutations */
struct {
HReg dst;
@@ -752,6 +764,7 @@
extern PPC32Instr* PPC32Instr_AvBin16x8 ( PPC32AvOp op, HReg dst, HReg =
srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvBin32x4 ( PPC32AvOp op, HReg dst, HReg =
srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvBin32Fx4 ( PPC32AvOp op, HReg dst, HReg =
srcL, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvUn32Fx4 ( PPC32AvOp op, HReg dst, HReg =
src );
extern PPC32Instr* PPC32Instr_AvPerm ( HReg dst, HReg srcL, HReg src=
R, HReg ctl );
extern PPC32Instr* PPC32Instr_AvSel ( HReg ctl, HReg dst, HReg srcL=
, HReg srcR );
extern PPC32Instr* PPC32Instr_AvShlDbl ( UChar shift, HReg dst, HReg s=
rcL, HReg srcR );
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-11-14 00:35:59 UTC (rev 1455)
+++ trunk/priv/host-ppc32/isel.c 2005-11-14 00:44:47 UTC (rev 1456)
@@ -123,20 +123,18 @@
//.. {
//.. return IRExpr_Const(IRConst_U64(i));
//.. }
-//..=20
-//.. static IRExpr* mkU32 ( UInt i )
-//.. {
-//.. return IRExpr_Const(IRConst_U32(i));
-//.. }
=20
+static IRExpr* mkU32 ( UInt i )
+{
+ return IRExpr_Const(IRConst_U32(i));
+}
+
static IRExpr* bind ( Int binder )
{
return IRExpr_Binder(binder);
}
=20
=20
-
-
/*---------------------------------------------------------*/
/*--- ISelEnv ---*/
/*---------------------------------------------------------*/
@@ -838,6 +836,30 @@
}
=20
=20
+/* for each lane of vSrc: lane =3D=3D nan ? laneX =3D all 1's : all 0's =
*/
+static HReg isNan ( ISelEnv* env, HReg vSrc )
+{
+ vassert(hregClass(vSrc) =3D=3D HRcVec128);
+
+ HReg zeros =3D mk_AvDuplicateRI(env, mkU32(0));
+ HReg msk_exp =3D mk_AvDuplicateRI(env, mkU32(0x7F800000));
+ HReg msk_mnt =3D mk_AvDuplicateRI(env, mkU32(0x7FFFFF));
+ HReg expt =3D newVRegV(env);
+ HReg mnts =3D newVRegV(env);
+ HReg vIsNan =3D newVRegV(env);=20
+
+ /* 32bit float =3D> sign(1) | expontent(8) | mantissa(23)
+ nan =3D> exponent all ones, mantissa > 0 */
+
+ addInstr(env, PPC32Instr_AvBinary(Pav_AND, expt, vSrc, msk_exp));
+ addInstr(env, PPC32Instr_AvBin32x4(Pav_CMPEQU, expt, expt, msk_exp));
+ addInstr(env, PPC32Instr_AvBinary(Pav_AND, mnts, vSrc, msk_mnt));
+ addInstr(env, PPC32Instr_AvBin32x4(Pav_CMPGTU, mnts, mnts, zeros));
+ addInstr(env, PPC32Instr_AvBinary(Pav_AND, vIsNan, expt, mnts));
+ return vIsNan;
+}
+
+
/*---------------------------------------------------------*/
/*--- ISEL: Integer expressions (32/16/8 bit) ---*/
/*---------------------------------------------------------*/
@@ -2978,35 +3000,7 @@
//.. addInstr(env, X86Instr_SseReRg(Xsse_OR, tmp, dst));
//.. return dst;
//.. }
-//..=20
-//.. case Iop_CmpNEZ32x4: {
-//.. /* Sigh, we have to generate lousy code since this has to
-//.. work on SSE1 hosts */
-//.. /* basically, the idea is: for each lane:
-//.. movl lane, %r ; negl %r (now CF =3D lane=3D=3D0 ? =
0 : 1)
-//.. sbbl %r, %r (now %r =3D 1Sto32(CF))
-//.. movl %r, lane
-//.. */
-//.. Int i;
-//.. X86AMode* am;
-//.. X86AMode* esp0 =3D X86AMode_IR(0, hregX86_ESP());
-//.. HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
-//.. HReg dst =3D newVRegV(env);
-//.. HReg r32 =3D newVRegI(env);
-//.. sub_from_esp(env, 16);
-//.. addInstr(env, X86Instr_SseLdSt(False/*store*/, arg, esp0))=
;
-//.. for (i =3D 0; i < 4; i++) {
-//.. am =3D X86AMode_IR(i*4, hregX86_ESP());
-//.. addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Mem(am),=
r32));
-//.. addInstr(env, X86Instr_Unary32(Xun_NEG, X86RM_Reg(r32))=
);
-//.. addInstr(env, X86Instr_Alu32R(Xalu_SBB, X86RMI_Reg(r32)=
, r32));
-//.. addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(r32),=
am));
-//.. }
-//.. addInstr(env, X86Instr_SseLdSt(True/*load*/, dst, esp0));
-//.. add_to_esp(env, 16);
-//.. return dst;
-//.. }
-//..=20
+
case Iop_CmpNEZ8x16: {
HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
HReg zero =3D newVRegV(env);
@@ -3061,18 +3055,18 @@
//.. addInstr(env, X86Instr_SseReRg(Xsse_XOR, vec1, dst));
//.. return dst;
//.. }
-//..=20
-//.. case Iop_Recip32Fx4: op =3D Xsse_RCPF; goto do_32Fx4_unary;
-//.. case Iop_RSqrt32Fx4: op =3D Xsse_RSQRTF; goto do_32Fx4_unary;
+
+ case Iop_Recip32Fx4: op =3D Pavfp_RCPF; goto do_32Fx4_unary;
+ case Iop_RSqrt32Fx4: op =3D Pavfp_RSQRTF; goto do_32Fx4_unary;
//.. case Iop_Sqrt32Fx4: op =3D Xsse_SQRTF; goto do_32Fx4_unary;
-//.. do_32Fx4_unary:
-//.. {
-//.. HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
-//.. HReg dst =3D newVRegV(env);
-//.. addInstr(env, X86Instr_Sse32Fx4(op, arg, dst));
-//.. return dst;
-//.. }
-//..=20
+ do_32Fx4_unary:
+ {
+ HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
+ HReg dst =3D newVRegV(env);
+ addInstr(env, PPC32Instr_AvUn32Fx4(op, dst, arg));
+ return dst;
+ }
+
//.. case Iop_Recip64Fx2: op =3D Xsse_RCPF; goto do_64Fx2_unary;
//.. case Iop_RSqrt64Fx2: op =3D Xsse_RSQRTF; goto do_64Fx2_unary;
//.. case Iop_Sqrt64Fx2: op =3D Xsse_SQRTF; goto do_64Fx2_unary;
@@ -3237,25 +3231,45 @@
return dst;
}
=20
-//.. case Iop_CmpEQ32Fx4: op =3D Xsse_CMPEQF; goto do_32Fx4;
-//.. case Iop_CmpLT32Fx4: op =3D Xsse_CMPLTF; goto do_32Fx4;
-//.. case Iop_CmpLE32Fx4: op =3D Xsse_CMPLEF; goto do_32Fx4;
-//.. case Iop_Add32Fx4: op =3D Xsse_ADDF; goto do_32Fx4;
+ case Iop_Add32Fx4: op =3D Pavfp_ADDF; goto do_32Fx4;
+ case Iop_Sub32Fx4: op =3D Pavfp_SUBF; goto do_32Fx4;
+ case Iop_Max32Fx4: op =3D Pavfp_MAXF; goto do_32Fx4;
+ case Iop_Min32Fx4: op =3D Pavfp_MINF; goto do_32Fx4;
+ case Iop_Mul32Fx4: op =3D Pavfp_MULF; goto do_32Fx4;
//.. case Iop_Div32Fx4: op =3D Xsse_DIVF; goto do_32Fx4;
-//.. case Iop_Max32Fx4: op =3D Xsse_MAXF; goto do_32Fx4;
-//.. case Iop_Min32Fx4: op =3D Xsse_MINF; goto do_32Fx4;
-//.. case Iop_Mul32Fx4: op =3D Xsse_MULF; goto do_32Fx4;
-//.. case Iop_Sub32Fx4: op =3D Xsse_SUBF; goto do_32Fx4;
-//.. do_32Fx4:
-//.. {
-//.. HReg argL =3D iselVecExpr(env, e->Iex.Binop.arg1);
-//.. HReg argR =3D iselVecExpr(env, e->Iex.Binop.arg2);
-//.. HReg dst =3D newVRegV(env);
-//.. addInstr(env, mk_vMOVsd_RR(argL, dst));
-//.. addInstr(env, X86Instr_Sse32Fx4(op, argR, dst));
-//.. return dst;
-//.. }
+ case Iop_CmpEQ32Fx4: op =3D Pavfp_CMPEQF; goto do_32Fx4;
+ case Iop_CmpGT32Fx4: op =3D Pavfp_CMPGTF; goto do_32Fx4;
+ case Iop_CmpGE32Fx4: op =3D Pavfp_CMPGEF; goto do_32Fx4;
+//.. case Iop_CmpLT32Fx4:
+ do_32Fx4:
+ {
+ HReg argL =3D iselVecExpr(env, e->Iex.Binop.arg1);
+ HReg argR =3D iselVecExpr(env, e->Iex.Binop.arg2);
+ HReg dst =3D newVRegV(env);
+ addInstr(env, PPC32Instr_AvBin32Fx4(op, dst, argL, argR));
+ return dst;
+ }
=20
+ case Iop_CmpLE32Fx4: {
+ HReg argL =3D iselVecExpr(env, e->Iex.Binop.arg1);
+ HReg argR =3D iselVecExpr(env, e->Iex.Binop.arg2);
+ HReg dst =3D newVRegV(env);
+ =20
+ /* stay consistent with native ppc compares:
+ if a left/right lane holds a nan, return zeros for that lane
+ so: le =3D=3D NOT(gt OR isNan)
+ */
+ HReg isNanLR =3D newVRegV(env);
+ HReg isNanL =3D isNan(env, argL);
+ HReg isNanR =3D isNan(env, argR);
+ addInstr(env, PPC32Instr_AvBinary(Pav_OR, isNanLR, isNanL, isNa=
nR));
+
+ addInstr(env, PPC32Instr_AvBin32Fx4(Pavfp_CMPGTF, dst, argL, ar=
gR));
+ addInstr(env, PPC32Instr_AvBinary(Pav_OR, dst, dst, isNanLR));
+ addInstr(env, PPC32Instr_AvUnary(Pav_NOT, dst, dst));
+ return dst;
+ }
+
//.. case Iop_CmpEQ64Fx2: op =3D Xsse_CMPEQF; goto do_64Fx2;
//.. case Iop_CmpLT64Fx2: op =3D Xsse_CMPLTF; goto do_64Fx2;
//.. case Iop_CmpLE64Fx2: op =3D Xsse_CMPLEF; goto do_64Fx2;
|
|
From: <sv...@va...> - 2005-11-14 00:36:01
|
Author: cerion
Date: 2005-11-14 00:35:59 +0000 (Mon, 14 Nov 2005)
New Revision: 1455
Log:
New irops: Iop_CmpGT32Fx4, Iop_CmpGE32Fx4
Modified:
trunk/priv/ir/irdefs.c
trunk/pub/libvex_ir.h
Modified: trunk/priv/ir/irdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/irdefs.c 2005-11-13 20:30:24 UTC (rev 1454)
+++ trunk/priv/ir/irdefs.c 2005-11-14 00:35:59 UTC (rev 1455)
@@ -372,6 +372,8 @@
case Iop_CmpEQ32Fx4: vex_printf("CmpEQ32Fx4"); return;
case Iop_CmpLT32Fx4: vex_printf("CmpLT32Fx4"); return;
case Iop_CmpLE32Fx4: vex_printf("CmpLE32Fx4"); return;
+ case Iop_CmpGT32Fx4: vex_printf("CmpGT32Fx4"); return;
+ case Iop_CmpGE32Fx4: vex_printf("CmpGE32Fx4"); return;
case Iop_CmpUN32Fx4: vex_printf("CmpUN32Fx4"); return;
case Iop_CmpEQ64Fx2: vex_printf("CmpEQ64Fx2"); return;
case Iop_CmpLT64Fx2: vex_printf("CmpLT64Fx2"); return;
@@ -1531,6 +1533,7 @@
case Iop_CmpEQ64Fx2: case Iop_CmpLT64Fx2:
case Iop_CmpLE32Fx4: case Iop_CmpUN32Fx4:
case Iop_CmpLE64Fx2: case Iop_CmpUN64Fx2:
+ case Iop_CmpGT32Fx4: case Iop_CmpGE32Fx4:
case Iop_CmpEQ32F0x4: case Iop_CmpLT32F0x4:
case Iop_CmpEQ64F0x2: case Iop_CmpLT64F0x2:
case Iop_CmpLE32F0x4: case Iop_CmpUN32F0x4:
Modified: trunk/pub/libvex_ir.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/pub/libvex_ir.h 2005-11-13 20:30:24 UTC (rev 1454)
+++ trunk/pub/libvex_ir.h 2005-11-14 00:35:59 UTC (rev 1455)
@@ -470,6 +470,7 @@
Iop_Add32Fx4, Iop_Sub32Fx4, Iop_Mul32Fx4, Iop_Div32Fx4,=20
Iop_Max32Fx4, Iop_Min32Fx4,
Iop_CmpEQ32Fx4, Iop_CmpLT32Fx4, Iop_CmpLE32Fx4, Iop_CmpUN32Fx4,=20
+ Iop_CmpGT32Fx4, Iop_CmpGE32Fx4,
=20
/* unary */
Iop_Recip32Fx4, Iop_Sqrt32Fx4, Iop_RSqrt32Fx4,
|