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|
From: <sv...@va...> - 2005-11-13 02:42:28
|
Author: sewardj
Date: 2005-11-13 02:42:23 +0000 (Sun, 13 Nov 2005)
New Revision: 5113
Log:
Hacks needed for MontaVista Linux 3.1 (ppc32).
Modified:
trunk/coregrind/m_aspacemgr/aspacemgr.c
trunk/glibc-2.3.supp
Modified: trunk/coregrind/m_aspacemgr/aspacemgr.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_aspacemgr/aspacemgr.c 2005-11-13 02:41:58 UTC (rev =
5112)
+++ trunk/coregrind/m_aspacemgr/aspacemgr.c 2005-11-13 02:42:23 UTC (rev =
5113)
@@ -1139,11 +1139,16 @@
=3D nsegments[i].dev !=3D 0 || nsegments[i].ino !=3D 0;
=20
/* Consider other reasons to not compare dev/inode */
+
/* bproc does some godawful hack on /dev/zero at process
migration, which changes the name of it, and its dev & ino */
if (filename && 0=3D=3DVG_(strcmp)(filename, "/dev/zero (deleted)"=
))
cmp_devino =3D False;
=20
+ /* hack apparently needed on MontaVista Linux */
+ if (filename && VG_(strstr)(filename, "/.lib-ro/"))
+ cmp_devino =3D False;
+
/* If we are doing sloppy execute permission checks then we
allow segment to have X permission when we weren't expecting
it (but not vice versa) so if the kernel reported execute
Modified: trunk/glibc-2.3.supp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/glibc-2.3.supp 2005-11-13 02:41:58 UTC (rev 5112)
+++ trunk/glibc-2.3.supp 2005-11-13 02:42:23 UTC (rev 5113)
@@ -503,3 +503,30 @@
obj:*
fun:_dl_sysdep_start
}
+
+##----------------------------------------------------------------------=
##
+## MontaVista 3.1 on ppc32 integer only
+{
+ MontaVista-3.1-ppc32-#1
+ Memcheck:Value4
+ obj:/lib/ld-2.3.2.so
+ obj:/lib/ld-2.3.2.so
+ fun:*dl_map_object*
+ obj:/lib/libc-2.3.2.so
+}
+
+{
+ MontaVista-3.1-ppc32-#2
+ Memcheck:Value4
+ fun:malloc
+ obj:/lib/ld-2.3.2.so
+ obj:/lib/ld-2.3.2.so
+ obj:/lib/libc-2.3.2.so
+}
+
+{
+ MontaVista-3.1-ppc32-#3
+ Memcheck:Value4
+ obj:/lib/ld-2.3.2.so
+ obj:/lib/ld-2.3.2.so
+}
|
|
From: <sv...@va...> - 2005-11-13 02:42:02
|
Author: sewardj
Date: 2005-11-13 02:41:58 +0000 (Sun, 13 Nov 2005)
New Revision: 5112
Log:
Enable a couple more syscalls.
Modified:
trunk/coregrind/m_syswrap/syswrap-ppc32-linux.c
Modified: trunk/coregrind/m_syswrap/syswrap-ppc32-linux.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syswrap-ppc32-linux.c 2005-11-13 02:41:35 U=
TC (rev 5111)
+++ trunk/coregrind/m_syswrap/syswrap-ppc32-linux.c 2005-11-13 02:41:58 U=
TC (rev 5112)
@@ -1437,7 +1437,7 @@
const SyscallTableEntry ML_(syscall_table)[] =3D {
//.. (restart_syscall) // 0
GENX_(__NR_exit, sys_exit), // 1
-//.. GENX_(__NR_fork, sys_fork), // 2
+ GENX_(__NR_fork, sys_fork), // 2
GENXY(__NR_read, sys_read), // 3
GENX_(__NR_write, sys_write), // 4
=20
@@ -1571,7 +1571,7 @@
//.. LINX_(__NR_vhangup, sys_vhangup), // 111
//.. GENX_(__NR_idle, sys_ni_syscall), // 112
//.. // (__NR_vm86old, sys_vm86old), // 113 x86=
/Linux-only
-//.. GENXY(__NR_wait4, sys_wait4), // 114
+ GENXY(__NR_wait4, sys_wait4), // 114
//..=20
//.. // (__NR_swapoff, sys_swapoff), // 115 */L=
inux=20
//.. LINXY(__NR_sysinfo, sys_sysinfo), // 116
|
|
From: <sv...@va...> - 2005-11-13 02:41:39
|
Author: sewardj
Date: 2005-11-13 02:41:35 +0000 (Sun, 13 Nov 2005)
New Revision: 5111
Log:
ppc32 stack unwind: if the initial FP looks bad, don't use it.
Modified:
trunk/coregrind/m_stacktrace.c
Modified: trunk/coregrind/m_stacktrace.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_stacktrace.c 2005-11-13 01:59:22 UTC (rev 5110)
+++ trunk/coregrind/m_stacktrace.c 2005-11-13 02:41:35 UTC (rev 5111)
@@ -189,32 +189,37 @@
=20
ips[0] =3D ip;
i =3D 1;
- fp =3D (((UWord*)fp)[0]);
=20
- while (True) {
+ if (fp_min <=3D fp && fp < fp_max-4+1) {
=20
- if (i >=3D n_ips)
- break;
+ /* initial FP is sane; keep going */
+ fp =3D (((UWord*)fp)[0]);
=20
- /* Try to derive a new (ip,fp) pair from the current set. */
+ while (True) {
=20
- if (fp_min <=3D fp && fp <=3D fp_max) {
- /* fp looks sane, so use it. */
+ if (i >=3D n_ips)
+ break;
=20
- if (i =3D=3D 1 && lr_is_first_RA)
- ip =3D lr;
- else
- ip =3D (((UWord*)fp)[1]);
+ /* Try to derive a new (ip,fp) pair from the current set. */
=20
- fp =3D (((UWord*)fp)[0]);
- ips[i++] =3D ip;
- if (debug)
- VG_(printf)(" ipsF[%d]=3D%08p\n", i-1, ips[i-1]);
- continue;
+ if (fp_min <=3D fp && fp <=3D fp_max) {
+ /* fp looks sane, so use it. */
+
+ if (i =3D=3D 1 && lr_is_first_RA)
+ ip =3D lr;
+ else
+ ip =3D (((UWord*)fp)[1]);
+
+ fp =3D (((UWord*)fp)[0]);
+ ips[i++] =3D ip;
+ if (debug)
+ VG_(printf)(" ipsF[%d]=3D%08p\n", i-1, ips[i-1]);
+ continue;
+ }
+
+ /* No luck there. We have to give up. */
+ break;
}
-
- /* No luck there. We have to give up. */
- break;
}
=20
# else
|
|
From: Greg P. <gp...@us...> - 2005-11-13 02:39:45
|
Nicholas Nethercote writes: > Is there an easy way to learn when GCC options were introduced? > > I've found that I can speed up Cachegrind by 6--8% by inlining the > cachesim_*_doref() functions. But because they're big, I need to set > "--param max-inline-insns-single=2000", which says "inline big functions > that are marked 'inline'". So I want to know when this --param option was > introduced, to know if I can just use it straight up or if some fiddling > is required. gcc's inlining options change frequently. Even if the option is present, its meaning may change. You may have better luck with __attribute__((always_inline)), which dates from gcc 3.1 or so. -- Greg Parker gp...@us... |
|
From: <sv...@va...> - 2005-11-13 01:59:25
|
Author: sewardj
Date: 2005-11-13 01:59:22 +0000 (Sun, 13 Nov 2005)
New Revision: 5110
Log:
The absolute bare minimum changes needed to make it work on an
integer-only PPC processor (PPC440GX).
Modified:
trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S
trunk/coregrind/m_machine.c
trunk/coregrind/pub_core_machine.h
Modified: trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S 2005-11-13 00:53:33=
UTC (rev 5109)
+++ trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S 2005-11-13 01:59:22=
UTC (rev 5110)
@@ -58,6 +58,11 @@
stwu 1,-496(1) /* sp should maintain 16-byte alignment */
=20
/* Save callee-saved registers... */
+ /* r3 is live here (guest state ptr), so use r4 */
+ lis 4,VG_(machine_ppc32_has_FP)@ha
+ lwz 4,VG_(machine_ppc32_has_FP)@l(4)
+ cmplwi 4,0
+ beq LafterFP1
=20
/* Floating-point reg save area : 144 bytes */
stfd 31,488(1)
@@ -78,6 +83,7 @@
stfd 16,368(1)
stfd 15,360(1)
stfd 14,352(1)
+LafterFP1:
=20
/* General reg save area : 72 bytes */
stw 31,348(1)
@@ -105,6 +111,11 @@
/* It's necessary to save/restore VRSAVE in the AIX / Darwin ABI=
.
The Linux kernel might not actually use VRSAVE for its intend=
ed
purpose, but it should be harmless to preserve anyway. */
+ /* r3 is live here (guest state ptr), so use r4 */
+ lis 4,VG_(machine_ppc32_has_VMX)@ha
+ lwz 4,VG_(machine_ppc32_has_VMX)@l(4)
+ cmplwi 4,0
+ beq LafterVMX1
=20
/* VRSAVE save word : 32 bytes */
mfspr 4,256 /* vrsave reg is spr number 256 */
@@ -137,6 +148,7 @@
stvx 21,4,1
li 4,48
stvx 20,4,1
+LafterVMX1:
=20
/* Save cr */
mfcr 0
@@ -154,7 +166,7 @@
20(sp) : TOC save area
16(sp) : link editor word
12(sp) : compiler word
- 8(sp) : LR
+ 8(sp) : LR
4(sp) : CR
0(sp) : back-chain
*/
@@ -162,7 +174,7 @@
// CAB TODO: Use a caller-saved reg for orig guest_state ptr
// - rem to set non-allocateable in isel.c
=20
- /* hold dispach_ctr in ctr reg */
+ /* hold dispatch_ctr in ctr reg */
lis 17,VG_(dispatch_ctr)@ha
lwz 17,VG_(dispatch_ctr)@l(17)
mtctr 17
@@ -173,21 +185,27 @@
/* set host FPU control word to the default mode expected=20
by VEX-generated code. See comments in libvex.h for
more info. */
+ lis 3,VG_(machine_ppc32_has_FP)@ha
+ lwz 3,VG_(machine_ppc32_has_FP)@l(3)
+ cmplwi 3,0
+ beq LafterFP2
fsub 3,3,3 /* generate zero */
mtfsf 0xFF,3
+LafterFP2:
=20
/* set host AltiVec control word to the default mode expected=20
by VEX-generated code. */
lis 3,VG_(machine_ppc32_has_VMX)@ha
lwz 3,VG_(machine_ppc32_has_VMX)@l(3)
cmplwi 3,0
- beq L1
+ beq LafterVMX2
/* generate vector {0x0,0x0,0x0,0x00010000} */
vspltisw 3,0x1 /* 4x 0x00000001 */
vspltisw 4,0x0 /* generate zero */
vsldoi 3,4,3,0x6 /* v3 =3D v3 >> 10 bytes */
mtvscr 3
-L1:
+LafterVMX2:
+
/* make a stack frame for the code we are calling */
stwu 1,-16(1)
=20
@@ -312,6 +330,12 @@
=20
/* Restore callee-saved registers... */
=20
+ /* must use r4 since r3 holds return value */
+ lis 4,VG_(machine_ppc32_has_FP)@ha
+ lwz 4,VG_(machine_ppc32_has_FP)@l(4)
+ cmplwi 4,0
+ beq LafterFP9
+
/* Floating-point regs */
lfd 31,488(1)
lfd 30,480(1)
@@ -331,6 +355,7 @@
lfd 16,368(1)
lfd 15,360(1)
lfd 14,352(1)
+LafterFP9:
=20
/* General regs */
lwz 31,348(1)
@@ -353,6 +378,12 @@
lwz 14,280(1)
lwz 13,276(1)
=20
+ /* must use r4 since r3 holds return value */
+ lis 4,VG_(machine_ppc32_has_VMX)@ha
+ lwz 4,VG_(machine_ppc32_has_VMX)@l(4)
+ cmplwi 4,0
+ beq LafterVMX9
+
/* VRSAVE */
lwz 4,244(1)
mfspr 4,256 /* VRSAVE reg is spr number 256 */
@@ -382,6 +413,7 @@
lvx 21,4,1
li 4,48
lvx 20,4,1
+LafterVMX9:
=20
/* reset lr & sp */
lwz 0,500(1) /* stack_size + 4 */
Modified: trunk/coregrind/m_machine.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_machine.c 2005-11-13 00:53:33 UTC (rev 5109)
+++ trunk/coregrind/m_machine.c 2005-11-13 01:59:22 UTC (rev 5110)
@@ -236,7 +236,7 @@
call VG_(machine_ppc32_set_clszB)
=20
then safe to use VG_(machine_get_VexArchInfo)=20
- and VG_(machine_ppc32_has_FPU)
+ and VG_(machine_ppc32_has_FP)
and VG_(machine_ppc32_has_VMX)
=20
VG_(machine_get_hwcaps) may use signals (although it attempts to
@@ -255,7 +255,7 @@
UInt VG_(machine_x86_have_mxcsr) =3D 0;
#endif
#if defined(VGA_ppc32)
-UInt VG_(machine_ppc32_has_FPU) =3D 0;
+UInt VG_(machine_ppc32_has_FP) =3D 0;
UInt VG_(machine_ppc32_has_VMX) =3D 0;
#endif
=20
@@ -331,7 +331,7 @@
vki_sigset_t saved_set, tmp_set;
struct vki_sigaction saved_act, tmp_act;
=20
- Bool have_fp, have_vmx;
+ volatile Bool have_fp, have_vmx;
=20
VG_(sigemptyset)(&tmp_set);
VG_(sigaddset)(&tmp_set, VKI_SIGILL);
@@ -374,7 +374,7 @@
if (have_vmx && !have_fp)
have_vmx =3D False;
=20
- VG_(machine_ppc32_has_FPU) =3D have_fp ? 1 : 0;
+ VG_(machine_ppc32_has_FP) =3D have_fp ? 1 : 0;
VG_(machine_ppc32_has_VMX) =3D have_vmx ? 1 : 0;
=20
va =3D VexArchPPC32;
Modified: trunk/coregrind/pub_core_machine.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/pub_core_machine.h 2005-11-13 00:53:33 UTC (rev 5109)
+++ trunk/coregrind/pub_core_machine.h 2005-11-13 01:59:22 UTC (rev 5110)
@@ -98,7 +98,7 @@
call VG_(machine_ppc32_set_clszB)
=20
then safe to use VG_(machine_get_VexArchInfo)=20
- and VG_(machine_ppc32_has_FPU)
+ and VG_(machine_ppc32_has_FP)
and VG_(machine_ppc32_has_VMX)
=20
VG_(machine_get_hwcaps) may use signals (although it attempts to
@@ -131,7 +131,7 @@
else 0. Is referenced from assembly code, so do not change from a
32-bit int. */
#if defined(VGA_ppc32)
-extern UInt VG_(machine_ppc32_has_FPU);
+extern UInt VG_(machine_ppc32_has_FP);
#endif
=20
/* PPC32: set to 1 if Altivec instructions are supported in
|
|
From: Paul M. <pa...@sa...> - 2005-11-13 00:54:39
|
sv...@va... writes: > Hook the ppc32 stuff up to the revised CPU detection machinery, and > add a bunch of code to detect what the cpu can do at startup by > catching SIGILLs. Shame PPC doesn't offer any sane mechanism for > finding out what instruction subsets the CPU is capable of (a la > x86/amd64 cpuid). What do you need that the AT_HWCAP aux table entry doesn't tell you? Paul. |
|
From: <sv...@va...> - 2005-11-13 00:53:36
|
Author: sewardj
Date: 2005-11-13 00:53:33 +0000 (Sun, 13 Nov 2005)
New Revision: 5109
Log:
Use revised PPC32 subarchitecture categories.
Modified:
trunk/coregrind/m_machine.c
Modified: trunk/coregrind/m_machine.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_machine.c 2005-11-13 00:30:22 UTC (rev 5108)
+++ trunk/coregrind/m_machine.c 2005-11-13 00:53:33 UTC (rev 5109)
@@ -380,13 +380,13 @@
va =3D VexArchPPC32;
=20
if (have_fp =3D=3D False && have_vmx =3D=3D False) {
- vai.subarch =3D VexSubArchPPC32_noAV; // _I
+ vai.subarch =3D VexSubArchPPC32_I;
}
else if (have_fp =3D=3D True && have_vmx =3D=3D False) {
- vai.subarch =3D VexSubArchPPC32_noAV; // _FI
+ vai.subarch =3D VexSubArchPPC32_FI;
}
else if (have_fp =3D=3D True && have_vmx =3D=3D True) {
- vai.subarch =3D VexSubArchPPC32_AV; // _VFI
+ vai.subarch =3D VexSubArchPPC32_VFI;
} else {
/* this can't happen. */
vg_assert2(0, "VG_(machine_get_hwcaps)(ppc32)");
|
|
From: <sv...@va...> - 2005-11-13 00:53:07
|
Author: sewardj
Date: 2005-11-13 00:53:05 +0000 (Sun, 13 Nov 2005)
New Revision: 1452
Log:
Revise the PPC32 subarchitecture kinds, so as to facilitated
supporting CPUs that have neither Altivec nor FPU.
Modified:
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/isel.c
trunk/priv/main/vex_main.c
trunk/pub/libvex.h
trunk/test_main.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-11-12 12:56:31 UTC (rev 1451)
+++ trunk/priv/guest-ppc32/toIR.c 2005-11-13 00:53:05 UTC (rev 1452)
@@ -7012,6 +7012,12 @@
DisResult dres;
UInt theInstr;
=20
+ /* What insn variants are we supporting today? */
+ Bool allow_FP =3D archinfo->subarch =3D=3D VexSubArchPPC32_FI
+ || archinfo->subarch =3D=3D VexSubArchPPC32_VFI;
+
+ Bool allow_VMX =3D archinfo->subarch =3D=3D VexSubArchPPC32_VFI;
+
/* The running delta */
Int delta =3D (Int)delta64;
=20
@@ -7134,16 +7140,19 @@
/* Floating Point Load Instructions */
case 0x30: case 0x31: case 0x32: // lfs, lfsu, lfd
case 0x33: // lfdu
+ if (!allow_FP) goto decode_failure;
if (dis_fp_load( theInstr )) goto decode_success;
goto decode_failure;
=20
/* Floating Point Store Instructions */
case 0x34: case 0x35: case 0x36: // stfsx, stfsux, stfdx
case 0x37: // stfdux
+ if (!allow_FP) goto decode_failure;
if (dis_fp_store( theInstr )) goto decode_success;
goto decode_failure;
=20
case 0x3B:
+ if (!allow_FP) goto decode_failure;
opc2 =3D (theInstr >> 1) & 0x1F; /* theInstr[1:5] */
switch (opc2) {
/* Floating Point Arith Instructions */
@@ -7164,6 +7173,7 @@
break;
=20
case 0x3F:
+ if (!allow_FP) goto decode_failure;
/* Instrs using opc[1:5] never overlap with instrs using opc[1:10]=
,
so we can simply fall through the first switch statement */
=20
@@ -7357,12 +7367,14 @@
/* Floating Point Load Instructions */
case 0x217: case 0x237: case 0x257: // lfsx, lfsux, lfdx
case 0x277: // lfdux
+ if (!allow_FP) goto decode_failure;
if (dis_fp_load( theInstr )) goto decode_success;
goto decode_failure;
=20
/* Floating Point Store Instructions */
case 0x297: case 0x2B7: case 0x2D7: // stfs, stfsu, stfd
case 0x2F7: case 0x3D7: // stfdu, stfiwx
+ if (!allow_FP) goto decode_failure;
if (dis_fp_store( theInstr )) goto decode_success;
goto decode_failure;
=20
@@ -7371,6 +7383,7 @@
=20
/* AV Cache Control - Data streams */
case 0x156: case 0x176: case 0x336: // dst, dstst, dss
+ if (!allow_VMX) goto decode_failure;
if (dis_av_datastream( theInstr )) goto decode_success;
goto decode_failure;
=20
@@ -7378,12 +7391,14 @@
case 0x006: case 0x026: // lvsl, lvsr
case 0x007: case 0x027: case 0x047: // lvebx, lvehx, lvewx
case 0x067: case 0x167: // lvx, lvxl
+ if (!allow_VMX) goto decode_failure;
if (dis_av_load( theInstr )) goto decode_success;
goto decode_failure;
=20
/* AV Store */
case 0x087: case 0x0A7: case 0x0C7: // stvebx, stvehx, stvewx
case 0x0E7: case 0x1E7: // stvx, stvxl
+ if (!allow_VMX) goto decode_failure;
if (dis_av_store( theInstr )) goto decode_success;
goto decode_failure;
=20
@@ -7402,6 +7417,7 @@
case 0x20: case 0x21: case 0x22: // vmhaddshs, vmhraddshs, vmladdu=
hm
case 0x24: case 0x25: case 0x26: // vmsumubm, vmsummbm, vmsumuhm
case 0x27: case 0x28: case 0x29: // vmsumuhs, vmsumshm, vmsumshs
+ if (!allow_VMX) goto decode_failure;
if (dis_av_multarith( theInstr )) goto decode_success;
goto decode_failure;
=20
@@ -7409,11 +7425,13 @@
case 0x2A: // vsel
case 0x2B: // vperm
case 0x2C: // vsldoi
+ if (!allow_VMX) goto decode_failure;
if (dis_av_permute( theInstr )) goto decode_success;
goto decode_failure;
=20
/* AV Floating Point Mult-Add/Sub */
case 0x2E: case 0x2F: // vmaddfp, vnmsubfp
+ if (!allow_VMX) goto decode_failure;
if (dis_av_fp_arith( theInstr )) goto decode_success;
goto decode_failure;
=20
@@ -7444,6 +7462,7 @@
case 0x308: case 0x348: // vmulesb, vmulesh
case 0x608: case 0x708: case 0x648: // vsum4ubs, vsum4sbs, vsum4sh=
s
case 0x688: case 0x788: // vsum2sws, vsumsws
+ if (!allow_VMX) goto decode_failure;
if (dis_av_arith( theInstr )) goto decode_success;
goto decode_failure;
=20
@@ -7454,17 +7473,20 @@
case 0x304: case 0x344: case 0x384: // vsrab, vsrah, vsraw
case 0x1C4: case 0x2C4: // vsl, vsr
case 0x40C: case 0x44C: // vslo, vsro
+ if (!allow_VMX) goto decode_failure;
if (dis_av_shift( theInstr )) goto decode_success;
goto decode_failure;
=20
/* AV Logic */
case 0x404: case 0x444: case 0x484: // vand, vandc, vor
case 0x4C4: case 0x504: // vxor, vnor
+ if (!allow_VMX) goto decode_failure;
if (dis_av_logic( theInstr )) goto decode_success;
goto decode_failure;
=20
/* AV Processor Control */
case 0x604: case 0x644: // mfvscr, mtvscr
+ if (!allow_VMX) goto decode_failure;
if (dis_av_procctl( theInstr )) goto decode_success;
goto decode_failure;
=20
@@ -7473,6 +7495,7 @@
case 0x10A: case 0x14A: case 0x18A: // vrefp, vrsqrtefp, vexptefp
case 0x1CA: // vlogefp
case 0x40A: case 0x44A: // vmaxfp, vminfp
+ if (!allow_VMX) goto decode_failure;
if (dis_av_fp_arith( theInstr )) goto decode_success;
goto decode_failure;
=20
@@ -7481,6 +7504,7 @@
case 0x2CA: // vrfim
case 0x30A: case 0x34A: case 0x38A: // vcfux, vcfsx, vctuxs
case 0x3CA: // vctsxs
+ if (!allow_VMX) goto decode_failure;
if (dis_av_fp_convert( theInstr )) goto decode_success;
goto decode_failure;
=20
@@ -7489,6 +7513,7 @@
case 0x10C: case 0x14C: case 0x18C: // vmrglb, vmrglh, vmrglw
case 0x20C: case 0x24C: case 0x28C: // vspltb, vsplth, vspltw
case 0x30C: case 0x34C: case 0x38C: // vspltisb, vspltish, vspltis=
w
+ if (!allow_VMX) goto decode_failure;
if (dis_av_permute( theInstr )) goto decode_success;
goto decode_failure;
=20
@@ -7500,6 +7525,7 @@
case 0x20E: case 0x24E: case 0x28E: // vupkhsb, vupkhsh, vupklsb
case 0x2CE: // vupklsh
case 0x30E: case 0x34E: case 0x3CE: // vpkpx, vupkhpx, vupklpx
+ if (!allow_VMX) goto decode_failure;
if (dis_av_pack( theInstr )) goto decode_success;
goto decode_failure;
=20
@@ -7514,12 +7540,14 @@
case 0x006: case 0x046: case 0x086: // vcmpequb, vcmpequh, vcmpequ=
w
case 0x206: case 0x246: case 0x286: // vcmpgtub, vcmpgtuh, vcmpgtu=
w
case 0x306: case 0x346: case 0x386: // vcmpgtsb, vcmpgtsh, vcmpgts=
w
+ if (!allow_VMX) goto decode_failure;
if (dis_av_cmp( theInstr )) goto decode_success;
goto decode_failure;
=20
/* AV Floating Point Compare */
case 0x0C6: case 0x1C6: case 0x2C6: // vcmpeqfp, vcmpgefp, vcmpgtf=
p
case 0x3C6: // vcmpbfp
+ if (!allow_VMX) goto decode_failure;
if (dis_av_fp_cmp( theInstr )) goto decode_success;
goto decode_failure;
=20
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-11-12 12:56:31 UTC (rev 1451)
+++ trunk/priv/host-ppc32/isel.c 2005-11-13 00:53:05 UTC (rev 1452)
@@ -3783,8 +3783,9 @@
VexSubArch subarch_host =3D archinfo_host->subarch;
=20
/* sanity ... */
- vassert(subarch_host =3D=3D VexSubArchPPC32_noAV
- || subarch_host =3D=3D VexSubArchPPC32_AV);
+ vassert(subarch_host =3D=3D VexSubArchPPC32_I
+ || subarch_host =3D=3D VexSubArchPPC32_FI
+ || subarch_host =3D=3D VexSubArchPPC32_VFI);
=20
/* Make up an initial environment to use. */
env =3D LibVEX_Alloc(sizeof(ISelEnv));
Modified: trunk/priv/main/vex_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/main/vex_main.c 2005-11-12 12:56:31 UTC (rev 1451)
+++ trunk/priv/main/vex_main.c 2005-11-13 00:53:05 UTC (rev 1452)
@@ -321,8 +321,9 @@
emit =3D (Int(*)(UChar*,Int,HInstr*)) emit_PPC32Instr;
host_is_bigendian =3D True;
host_word_type =3D Ity_I32;
- vassert(archinfo_guest->subarch =3D=3D VexSubArchPPC32_noAV
- || archinfo_guest->subarch =3D=3D VexSubArchPPC32_AV);
+ vassert(archinfo_guest->subarch =3D=3D VexSubArchPPC32_I
+ || archinfo_guest->subarch =3D=3D VexSubArchPPC32_FI
+ || archinfo_guest->subarch =3D=3D VexSubArchPPC32_VFI);
break;
=20
default:
@@ -385,8 +386,9 @@
guest_layout =3D &ppc32Guest_layout;
offB_TISTART =3D offsetof(VexGuestPPC32State,guest_TISTART)=
;
offB_TILEN =3D offsetof(VexGuestPPC32State,guest_TILEN);
- vassert(archinfo_guest->subarch =3D=3D VexSubArchPPC32_noAV
- || archinfo_guest->subarch =3D=3D VexSubArchPPC32_AV);
+ vassert(archinfo_guest->subarch =3D=3D VexSubArchPPC32_I
+ || archinfo_guest->subarch =3D=3D VexSubArchPPC32_FI
+ || archinfo_guest->subarch =3D=3D VexSubArchPPC32_VFI);
vassert(0 =3D=3D sizeof(VexGuestPPC32State) % 8);
vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TISTART ) =3D=3D=
4);
vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TILEN ) =3D=3D =
4);
@@ -655,8 +657,9 @@
case VexSubArchX86_sse1: return "x86-sse1";
case VexSubArchX86_sse2: return "x86-sse2";
case VexSubArchARM_v4: return "arm-v4";
- case VexSubArchPPC32_noAV: return "ppc32-noAltivec";
- case VexSubArchPPC32_AV: return "ppc32-Altivec";
+ case VexSubArchPPC32_I: return "ppc32-int-only";
+ case VexSubArchPPC32_FI: return "ppc32-int-and-fp";
+ case VexSubArchPPC32_VFI: return "ppc32-int-fp-and-AV";
default: return "VexSubArch???";
}
}
Modified: trunk/pub/libvex.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/pub/libvex.h 2005-11-12 12:56:31 UTC (rev 1451)
+++ trunk/pub/libvex.h 2005-11-13 00:53:05 UTC (rev 1452)
@@ -78,8 +78,9 @@
VexSubArchX86_sse1, /* SSE1 support (Pentium III) */
VexSubArchX86_sse2, /* SSE2 support (Pentium 4) */
VexSubArchARM_v4, /* ARM version 4 */
- VexSubArchPPC32_noAV, /* 32-bit PowerPC, no Altivec */
- VexSubArchPPC32_AV /* 32-bit PowerPC with Altivec */
+ VexSubArchPPC32_I, /* 32-bit PowerPC, no FP, no Altivec */
+ VexSubArchPPC32_FI, /* 32-bit PowerPC, with FP but no Altivec =
*/
+ VexSubArchPPC32_VFI /* 32-bit PowerPC, with FP and Altivec */
}
VexSubArch;
=20
Modified: trunk/test_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/test_main.c 2005-11-12 12:56:31 UTC (rev 1451)
+++ trunk/test_main.c 2005-11-13 00:53:05 UTC (rev 1452)
@@ -130,7 +130,7 @@
vai_amd64.subarch =3D VexSubArch_NONE;
=20
LibVEX_default_VexArchInfo(&vai_ppc32);
- vai_ppc32.subarch =3D VexSubArchPPC32_AV;
+ vai_ppc32.subarch =3D VexSubArchPPC32_VFI;
vai_ppc32.ppc32_cache_line_szB =3D 128;
=20
for (i =3D 0; i < TEST_N_ITERS; i++)
|
|
From: <sv...@va...> - 2005-11-13 00:30:28
|
Author: sewardj
Date: 2005-11-13 00:30:22 +0000 (Sun, 13 Nov 2005)
New Revision: 5108
Log:
Hook the ppc32 stuff up to the revised CPU detection machinery, and
add a bunch of code to detect what the cpu can do at startup by
catching SIGILLs. Shame PPC doesn't offer any sane mechanism for
finding out what instruction subsets the CPU is capable of (a la
x86/amd64 cpuid).
Modified:
trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S
trunk/coregrind/m_machine.c
trunk/coregrind/m_main.c
trunk/coregrind/m_transtab.c
Modified: trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S 2005-11-13 00:09:49=
UTC (rev 5107)
+++ trunk/coregrind/m_dispatch/dispatch-ppc32-linux.S 2005-11-13 00:30:22=
UTC (rev 5108)
@@ -178,8 +178,8 @@
=20
/* set host AltiVec control word to the default mode expected=20
by VEX-generated code. */
- lis 3,VG_(have_altivec_ppc32)@ha
- lwz 3,VG_(have_altivec_ppc32)@l(3)
+ lis 3,VG_(machine_ppc32_has_VMX)@ha
+ lwz 3,VG_(machine_ppc32_has_VMX)@l(3)
cmplwi 3,0
beq L1
/* generate vector {0x0,0x0,0x0,0x00010000} */
Modified: trunk/coregrind/m_machine.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_machine.c 2005-11-13 00:09:49 UTC (rev 5107)
+++ trunk/coregrind/m_machine.c 2005-11-13 00:30:22 UTC (rev 5108)
@@ -34,7 +34,9 @@
#include "pub_core_libcbase.h"
#include "pub_core_machine.h"
#include "pub_core_cpuid.h"
+#include "pub_core_libcsignal.h" // for ppc32 messing with SIGILL
=20
+
#define INSTR_PTR(regs) ((regs).vex.VG_INSTR_PTR)
#define STACK_PTR(regs) ((regs).vex.VG_STACK_PTR)
#define FRAME_PTR(regs) ((regs).vex.VG_FRAME_PTR)
@@ -262,6 +264,12 @@
record it. To be called once at system startup. Returns False if
this a CPU incapable of running Valgrind. */
=20
+#if defined(VGA_ppc32)
+#include <setjmp.h> // For jmp_buf
+static jmp_buf env_sigill;
+static void handler_sigill ( Int x ) { __builtin_longjmp(env_sigill,1); =
}
+#endif
+
Bool VG_(machine_get_hwcaps)( void )
{
vg_assert(hwcaps_done =3D=3D False);
@@ -317,25 +325,108 @@
return True;
=20
#elif defined(VGA_ppc32)
- va =3D VexArchPPC32;
- vai.subarch =3D VexSubArchPPC32_AV;
- /* But we're not done yet: VG_(machine_ppc32_set_clszB) must be
- called before we're ready to go. */
- return True;
+ { /* ppc32 doesn't seem to have a sane way to find out what insn
+ sets the CPU supports. So we have to arse around with
+ SIGILLs. Yuck. */
+ vki_sigset_t saved_set, tmp_set;
+ struct vki_sigaction saved_act, tmp_act;
=20
+ Bool have_fp, have_vmx;
+
+ VG_(sigemptyset)(&tmp_set);
+ VG_(sigaddset)(&tmp_set, VKI_SIGILL);
+
+ VG_(sigprocmask)(VKI_SIG_UNBLOCK, &tmp_set, &saved_set);
+
+ VG_(sigaction)(VKI_SIGILL, NULL, &saved_act);
+ tmp_act =3D saved_act;
+
+ tmp_act.sa_flags &=3D ~VKI_SA_RESETHAND;
+ tmp_act.sa_flags &=3D ~VKI_SA_SIGINFO;
+
+ tmp_act.ksa_handler =3D handler_sigill;
+ VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
+
+ have_fp =3D True;
+ if (__builtin_setjmp(env_sigill)) {
+ have_fp =3D False;
+ } else {
+ __asm__ __volatile__("fmr 0,0");
+ }
+
+ tmp_act.ksa_handler =3D handler_sigill;
+ VG_(sigaction)(VKI_SIGILL, &tmp_act, NULL);
+
+ have_vmx =3D True;
+ if (__builtin_setjmp(env_sigill)) {
+ have_vmx =3D False;
+ } else {
+ __asm__ __volatile__("vor 0,0,0");
+ }
+
+ VG_(sigaction)(VKI_SIGILL, &saved_act, NULL);
+ VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);
+
+ /* VG_(printf)("FP %d VMX %d\n", (Int)have_fp, (Int)have_vmx); */
+
+ /* We can only support 3 cases, not 4 (vmx but no fp). So make
+ fp a prerequisite for vmx. */
+ if (have_vmx && !have_fp)
+ have_vmx =3D False;
+
+ VG_(machine_ppc32_has_FPU) =3D have_fp ? 1 : 0;
+ VG_(machine_ppc32_has_VMX) =3D have_vmx ? 1 : 0;
+
+ va =3D VexArchPPC32;
+
+ if (have_fp =3D=3D False && have_vmx =3D=3D False) {
+ vai.subarch =3D VexSubArchPPC32_noAV; // _I
+ }
+ else if (have_fp =3D=3D True && have_vmx =3D=3D False) {
+ vai.subarch =3D VexSubArchPPC32_noAV; // _FI
+ }
+ else if (have_fp =3D=3D True && have_vmx =3D=3D True) {
+ vai.subarch =3D VexSubArchPPC32_AV; // _VFI
+ } else {
+ /* this can't happen. */
+ vg_assert2(0, "VG_(machine_get_hwcaps)(ppc32)");
+ }
+
+ /* But we're not done yet: VG_(machine_ppc32_set_clszB) must be
+ called before we're ready to go. */
+ return True;
+ }
+
#else
# error "Unknown arch"
#endif
}
=20
+/* Notify host cpu cache line size, as per above comment. */
+#if defined(VGA_ppc32)
+void VG_(machine_ppc32_set_clszB)( Int szB )
+{
+ vg_assert(hwcaps_done);
=20
+ /* Either the value must not have been set yet (zero) or we can
+ tolerate it being set to the same value multiple times, as the
+ stack scanning logic in m_main is a bit stupid. */
+ vg_assert(vai.ppc32_cache_line_szB =3D=3D 0
+ || vai.ppc32_cache_line_szB =3D=3D szB);
+
+ vg_assert(szB =3D=3D 32 || szB =3D=3D 128);
+ vai.ppc32_cache_line_szB =3D szB;
+}
+#endif
+
+
/* Fetch host cpu info, once established. */
void VG_(machine_get_VexArchInfo)( /*OUT*/VexArch* pVa,
/*OUT*/VexArchInfo* pVai )
{
vg_assert(hwcaps_done);
- *pVa =3D va;
- *pVai =3D vai;
+ if (pVa) *pVa =3D va;
+ if (pVai) *pVai =3D vai;
}
=20
=20
Modified: trunk/coregrind/m_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_main.c 2005-11-13 00:09:49 UTC (rev 5107)
+++ trunk/coregrind/m_main.c 2005-11-13 00:30:22 UTC (rev 5108)
@@ -545,15 +545,6 @@
break;
=20
case AT_HWCAP:
-# if defined(VGP_ppc32_linux)
- /* Acquire altivecness info */
- VG_(debugLog)(2, "main", "PPC32 hwcaps: 0x%x\n",=20
- (UInt)auxv->u.a_val);
- if (auxv->u.a_val & 0x10000000)
- VG_(have_altivec_ppc32) =3D 1;
- VG_(debugLog)(2, "main", "PPC32 AltiVec support: %u\n",=20
- VG_(have_altivec_ppc32));
-# endif
break;
=20
case AT_DCACHEBSIZE:
@@ -562,7 +553,7 @@
# if defined(VGP_ppc32_linux)
/* acquire cache info */
if (auxv->u.a_val > 0) {
- VG_(cache_line_size_ppc32) =3D auxv->u.a_val;
+ VG_(machine_ppc32_set_clszB)( auxv->u.a_val );
VG_(debugLog)(2, "main",=20
"PPC32 cache line size %u (type %u)\n",=20
(UInt)auxv->u.a_val, (UInt)auxv->a_type =
);
Modified: trunk/coregrind/m_transtab.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_transtab.c 2005-11-13 00:09:49 UTC (rev 5107)
+++ trunk/coregrind/m_transtab.c 2005-11-13 00:30:22 UTC (rev 5108)
@@ -737,9 +737,13 @@
# if defined(VGA_ppc32)
Addr startaddr =3D (Addr) ptr;
Addr endaddr =3D startaddr + nbytes;
- Addr cls =3D VG_(cache_line_size_ppc32);
+ Addr cls;
Addr addr;
+ VexArchInfo vai;
=20
+ VG_(machine_get_VexArchInfo)( NULL, &vai );
+ cls =3D vai.ppc32_cache_line_szB;
+
/* Stay sane .. */
vg_assert(cls =3D=3D 32 || cls =3D=3D 128);
=20
|
|
From: <sv...@va...> - 2005-11-13 00:09:52
|
Author: tom Date: 2005-11-13 00:09:49 +0000 (Sun, 13 Nov 2005) New Revision: 5107 Log: Update bug status. Modified: trunk/docs/internals/3_0_BUGSTATUS.txt Modified: trunk/docs/internals/3_0_BUGSTATUS.txt =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/docs/internals/3_0_BUGSTATUS.txt 2005-11-13 00:08:03 UTC (rev 5= 106) +++ trunk/docs/internals/3_0_BUGSTATUS.txt 2005-11-13 00:09:49 UTC (rev 5= 107) @@ -324,7 +324,13 @@ FIXED-TRUNK: vg:5079 FIXED-30BRANCH: TODO =20 +---------------------------------------------------------------- +116200 enable fsetxattr, fgetxattr, and fremovexattr for amd64 =20 +FIXED-TRUNK: vg:5106 +FIXED-30BRANCH: TODO + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D Bugs targeted for 3.1.0 and 3.0.1 (all done, 3.0.1 released) = =3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D |
|
From: <sv...@va...> - 2005-11-13 00:08:05
|
Author: tom
Date: 2005-11-13 00:08:03 +0000 (Sun, 13 Nov 2005)
New Revision: 5106
Log:
Enable remaining *xattr system calls on amd64. Fixes bug #116200.
Modified:
trunk/coregrind/m_syswrap/syswrap-amd64-linux.c
Modified: trunk/coregrind/m_syswrap/syswrap-amd64-linux.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syswrap-amd64-linux.c 2005-11-13 00:01:20 U=
TC (rev 5105)
+++ trunk/coregrind/m_syswrap/syswrap-amd64-linux.c 2005-11-13 00:08:03 U=
TC (rev 5106)
@@ -1186,20 +1186,20 @@
// (__NR_security, sys_ni_syscall), // 185=20
LINX_(__NR_gettid, sys_gettid), // 186=20
// (__NR_readahead, sys_readahead), // 187=20
- //LINX_(__NR_setxattr, sys_setxattr), // 188=20
- //LINX_(__NR_lsetxattr, sys_lsetxattr), // 189=20
+ LINX_(__NR_setxattr, sys_setxattr), // 188=20
+ LINX_(__NR_lsetxattr, sys_lsetxattr), // 189=20
=20
- //LINX_(__NR_fsetxattr, sys_fsetxattr), // 190=20
+ LINX_(__NR_fsetxattr, sys_fsetxattr), // 190=20
LINXY(__NR_getxattr, sys_getxattr), // 191=20
- //LINXY(__NR_lgetxattr, sys_lgetxattr), // 192=20
- //LINXY(__NR_fgetxattr, sys_fgetxattr), // 193=20
- //LINXY(__NR_listxattr, sys_listxattr), // 194=20
+ LINXY(__NR_lgetxattr, sys_lgetxattr), // 192=20
+ LINXY(__NR_fgetxattr, sys_fgetxattr), // 193=20
+ LINXY(__NR_listxattr, sys_listxattr), // 194=20
=20
- //LINXY(__NR_llistxattr, sys_llistxattr), // 195=20
- //LINXY(__NR_flistxattr, sys_flistxattr), // 196=20
- //LINX_(__NR_removexattr, sys_removexattr), // 197=20
- //LINX_(__NR_lremovexattr, sys_lremovexattr), // 198=20
- //LINX_(__NR_fremovexattr, sys_fremovexattr), // 199=20
+ LINXY(__NR_llistxattr, sys_llistxattr), // 195=20
+ LINXY(__NR_flistxattr, sys_flistxattr), // 196=20
+ LINX_(__NR_removexattr, sys_removexattr), // 197=20
+ LINX_(__NR_lremovexattr, sys_lremovexattr), // 198=20
+ LINX_(__NR_fremovexattr, sys_fremovexattr), // 199=20
=20
// (__NR_tkill, sys_tkill), // 200=20
GENXY(__NR_time, sys_time), /*was sys_time64*/ // 201=20
|
|
From: <sv...@va...> - 2005-11-13 00:01:29
|
Author: tom
Date: 2005-11-13 00:01:20 +0000 (Sun, 13 Nov 2005)
New Revision: 5105
Log:
Mask out the top 16 bits of si_code at the start of the signal
handlers because the kernel sometimes forgets to do so.
Modified:
trunk/coregrind/m_signals.c
Modified: trunk/coregrind/m_signals.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_signals.c 2005-11-12 23:10:48 UTC (rev 5104)
+++ trunk/coregrind/m_signals.c 2005-11-13 00:01:20 UTC (rev 5105)
@@ -1354,6 +1354,14 @@
=20
vg_assert(tst->status =3D=3D VgTs_WaitSys);
=20
+#ifdef VGO_linux
+ /* The linux kernel uses the top 16 bits of si_code for it's own
+ use and only exports the bottom 16 bits to user space - at least
+ that is the theory, but it turns out that there are some kernels
+ around that forget to mask out the top 16 bits so we do it here. *=
/
+ info->si_code &=3D 0xffff;
+#endif
+
/* The thread isn't currently running, make it so before going on */
VG_(set_running)(tid);
=20
@@ -1463,6 +1471,14 @@
sigNo =3D=3D VKI_SIGILL ||
sigNo =3D=3D VKI_SIGTRAP);
=20
+#ifdef VGO_linux
+ /* The linux kernel uses the top 16 bits of si_code for it's own
+ use and only exports the bottom 16 bits to user space - at least
+ that is the theory, but it turns out that there are some kernels
+ around that forget to mask out the top 16 bits so we do it here. *=
/
+ info->si_code &=3D 0xffff;
+#endif
+
if (info->si_code <=3D VKI_SI_USER) {
/* If some user-process sent us one of these signals (ie,
they're not the result of a faulting instruction), then treat
|