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From: <sv...@va...> - 2005-09-09 22:31:53
|
Author: sewardj
Date: 2005-09-09 23:31:49 +0100 (Fri, 09 Sep 2005)
New Revision: 1384
Log:
Typechecker cleanups (non-functional changes)
Modified:
trunk/priv/guest-amd64/toIR.c
trunk/priv/guest-ppc32/ghelpers.c
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/isel.c
trunk/priv/host-x86/hdefs.c
trunk/priv/main/vex_util.c
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-09-09 19:45:36 UTC (rev 1383)
+++ trunk/priv/guest-amd64/toIR.c 2005-09-09 22:31:49 UTC (rev 1384)
@@ -5387,7 +5387,7 @@
=20
case 0xD0 ... 0xD7: /* FST %st(0),%st(?) */
r_dst =3D (UInt)modrm - 0xD0;
- DIP("fst %%st(0),%%st(%d)\n", r_dst);
+ DIP("fst %%st(0),%%st(%u)\n", r_dst);
/* P4 manual says: "If the destination operand is a
non-empty register, the invalid-operation exception
is not generated. Hence put_ST_UNCHECKED. */
Modified: trunk/priv/guest-ppc32/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/ghelpers.c 2005-09-09 19:45:36 UTC (rev 1383)
+++ trunk/priv/guest-ppc32/ghelpers.c 2005-09-09 22:31:49 UTC (rev 1384)
@@ -141,8 +141,8 @@
# define FIELD(_n) \
do { \
t =3D cr_native >> (4*(7-(_n))); \
- vex_state->guest_CR##_n##_0 =3D (UChar)(t & 1); \
- vex_state->guest_CR##_n##_321 =3D (UChar)(t & (7<<1)); \
+ vex_state->guest_CR##_n##_0 =3D toUChar(t & 1); \
+ vex_state->guest_CR##_n##_321 =3D toUChar(t & (7<<1)); \
} while (0)
=20
FIELD(0);
@@ -174,10 +174,10 @@
void LibVEX_GuestPPC32_put_XER ( UInt xer_native,
/*OUT*/VexGuestPPC32State* vex_state )
{
- vex_state->guest_XER_BC =3D (UChar)(xer_native & 0xFF);
- vex_state->guest_XER_SO =3D (UChar)((xer_native >> 31) & 0x1);
- vex_state->guest_XER_OV =3D (UChar)((xer_native >> 30) & 0x1);
- vex_state->guest_XER_CA =3D (UChar)((xer_native >> 29) & 0x1);
+ vex_state->guest_XER_BC =3D toUChar(xer_native & 0xFF);
+ vex_state->guest_XER_SO =3D toUChar((xer_native >> 31) & 0x1);
+ vex_state->guest_XER_OV =3D toUChar((xer_native >> 30) & 0x1);
+ vex_state->guest_XER_CA =3D toUChar((xer_native >> 29) & 0x1);
}
=20
=20
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-09 19:45:36 UTC (rev 1383)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-09 22:31:49 UTC (rev 1384)
@@ -776,7 +776,7 @@
return binop( Iop_And32,=20
binop( Iop_Shr32,=20
unop(Iop_8Uto32, getCR321(n)),
- mkU8(3-off) ),
+ mkU8(toUChar(3-off)) ),
mkU32(1) );
}
}
@@ -805,7 +805,7 @@
binop(Iop_And32, unop(Iop_8Uto32, getCR321(n)),
mkU32(~(1 << off))),
/* new value in the right place */
- binop(Iop_Shl32, safe, mkU8(off))
+ binop(Iop_Shl32, safe, mkU8(toUChar(off)))
)
)
);
@@ -879,7 +879,7 @@
if ((mask & (1 << (7-cr))) =3D=3D 0)
continue;
t =3D newTemp(Ity_I32);
- assign( t, binop(Iop_Shr32, w32, mkU8(4*(7-cr))) );
+ assign( t, binop(Iop_Shr32, w32, mkU8(toUChar(4*(7-cr)))) );
putCR0( cr, unop(Iop_32to8,=20
binop(Iop_And32, mkexpr(t), mkU32(1))) );
putCR321( cr, unop(Iop_32to8,
@@ -999,7 +999,7 @@
break;
=20
default:=20
- vex_printf("set_XER_OV: op =3D %d\n", op);
+ vex_printf("set_XER_OV: op =3D %u\n", op);
vpanic("set_XER_OV(ppc32)");
}
=20
@@ -1136,7 +1136,7 @@
break;
=20
default:=20
- vex_printf("set_XER_CA: op =3D %d\n", op);
+ vex_printf("set_XER_CA: op =3D %u\n", op);
vpanic("set_XER_CA(ppc32)");
}
=20
@@ -1450,10 +1450,10 @@
// li rD,val =3D=3D addi rD,0,val
// la disp(rA) =3D=3D addi rD,rA,disp
if ( Ra_addr =3D=3D 0 ) {
- DIP("li r%d,%d\n", Rd_addr, EXTS_SIMM);
+ DIP("li r%d,%d\n", Rd_addr, (Int)EXTS_SIMM);
assign( Rd, mkU32(EXTS_SIMM) );
} else {
- DIP("addi r%d,r%d,0x%x\n", Rd_addr, Ra_addr, SIMM_16);
+ DIP("addi r%d,r%d,0x%x\n", Rd_addr, Ra_addr, (Int)SIMM_16);
assign( Rd, binop( Iop_Add32, mkexpr(Ra), mkU32(EXTS_SIMM) ) );
}
break;
@@ -1461,7 +1461,7 @@
case 0x0F: // addis (Add Immediate Shifted, PPC32 p353)
// lis rD,val =3D=3D addis rD,0,val
if ( Ra_addr =3D=3D 0 ) {
- DIP("lis r%d,%d\n", Rd_addr, SIMM_16);
+ DIP("lis r%d,%d\n", Rd_addr, (Int)SIMM_16);
assign( Rd, mkU32(SIMM_16 << 16) );
} else {
DIP("addis r%d,r%d,0x%x\n", Rd_addr, Ra_addr, SIMM_16);
@@ -1815,7 +1815,7 @@
switch (opc1) {
case 0x0B: // cmpi (Compare Immediate, PPC32 p368)
EXTS_SIMM =3D extend_s_16to32(UIMM_16);
- DIP("cmp cr%d,r%d,%d\n", crfD, Ra_addr, EXTS_SIMM);
+ DIP("cmp cr%d,r%d,%d\n", crfD, Ra_addr, (Int)EXTS_SIMM);
putCR321( crfD, unop(Iop_32to8,
binop(Iop_CmpORD32S, mkexpr(Ra),=20
mkU32(EXTS_SIMM))) );
@@ -2166,7 +2166,7 @@
=20
switch (opc1) {
case 0x22: // lbz (Load B & Zero, PPC32 p433)
- DIP("lbz r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
+ DIP("lbz r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, unop(Iop_8Uto32,
loadBE(Ity_I8, mkexpr(EA_imm))) );
break;
@@ -2176,14 +2176,14 @@
vex_printf("dis_int_load(PPC32)(lbzu,Ra_addr|Rd_addr)\n");
return False;
}
- DIP("lbzu r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
+ DIP("lbzu r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, unop(Iop_8Uto32,
loadBE(Ity_I8, mkexpr(EA_imm))) );
putIReg( Ra_addr, mkexpr(EA_imm) );
break;
=20
case 0x2A: // lha (Load HW Algebraic, PPC32 p445)
- DIP("lha r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
+ DIP("lha r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, unop(Iop_16Sto32,
loadBE(Ity_I16, mkexpr(EA_imm))) );
break;
@@ -2193,14 +2193,14 @@
vex_printf("dis_int_load(PPC32)(lhau,Ra_addr|Rd_addr)\n");
return False;
}
- DIP("lhau r%d,%d(r%d)\n", Rd_addr, (Int)d_imm, Ra_addr);
+ DIP("lhau r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, unop(Iop_16Sto32,
loadBE(Ity_I16, mkexpr(EA_imm))) );
putIReg( Ra_addr, mkexpr(EA_imm) );
break;
=20
case 0x28: // lhz (Load HW & Zero, PPC32 p450)
- DIP("lhz r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
+ DIP("lhz r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, unop(Iop_16Uto32,
loadBE(Ity_I16, mkexpr(EA_imm))) );
break;
@@ -2210,14 +2210,14 @@
vex_printf("dis_int_load(PPC32)(lhzu,Ra_addr|Rd_addr)\n");
return False;
}
- DIP("lhzu r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
+ DIP("lhzu r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, unop(Iop_16Uto32,
loadBE(Ity_I16, mkexpr(EA_imm))) );
putIReg( Ra_addr, mkexpr(EA_imm) );
break;
=20
case 0x20: // lwz (Load W & Zero, PPC32 p460)
- DIP("lwz r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
+ DIP("lwz r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, loadBE(Ity_I32, mkexpr(EA_imm)) );
break;
=20
@@ -2226,7 +2226,7 @@
vex_printf("dis_int_load(PPC32)(lwzu,Ra_addr|Rd_addr)\n");
return False;
}
- DIP("lwzu r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
+ DIP("lwzu r%d,%d(r%d)\n", Rd_addr, (Int)exts_d_imm, Ra_addr);
putIReg( Rd_addr, loadBE(Ity_I32, mkexpr(EA_imm)) );
putIReg( Ra_addr, mkexpr(EA_imm) );
break;
@@ -2351,7 +2351,7 @@
=20
switch (opc1) {
case 0x26: // stb (Store B, PPC32 p509)
- DIP("stb r%d,%d(r%d)\n", Rs_addr, simm16, Ra_addr);
+ DIP("stb r%u,%d(r%u)\n", Rs_addr, simm16, Ra_addr);
storeBE( mkexpr(EA_imm), unop(Iop_32to8, mkexpr(Rs)) );
break;
=20
@@ -2360,13 +2360,13 @@
vex_printf("dis_int_store(PPC32)(stbu,Ra_addr)\n");
return False;
}
- DIP("stbu r%d,%d(r%d)\n", Rs_addr, simm16, Ra_addr);
+ DIP("stbu r%u,%d(r%u)\n", Rs_addr, simm16, Ra_addr);
putIReg( Ra_addr, mkexpr(EA_imm) );
storeBE( mkexpr(EA_imm), unop(Iop_32to8, mkexpr(Rs)) );
break;
=20
case 0x2C: // sth (Store HW, PPC32 p522)
- DIP("sth r%d,%d(r%d)\n", Rs_addr, simm16, Ra_addr);
+ DIP("sth r%u,%d(r%u)\n", Rs_addr, simm16, Ra_addr);
storeBE( mkexpr(EA_imm), unop(Iop_32to16, mkexpr(Rs)) );
break;
=20
@@ -2375,13 +2375,13 @@
vex_printf("dis_int_store(PPC32)(sthu,Ra_addr)\n");
return False;
}
- DIP("sthu r%d,%d(r%d)\n", Rs_addr, simm16, Ra_addr);
+ DIP("sthu r%u,%d(r%u)\n", Rs_addr, simm16, Ra_addr);
putIReg( Ra_addr, mkexpr(EA_imm) );
storeBE( mkexpr(EA_imm), unop(Iop_32to16, mkexpr(Rs)) );
break;
=20
case 0x24: // stw (Store W, PPC32 p530)
- DIP("stw r%d,%d(r%d)\n", Rs_addr, simm16, Ra_addr);
+ DIP("stw r%u,%d(r%u)\n", Rs_addr, simm16, Ra_addr);
storeBE( mkexpr(EA_imm), mkexpr(Rs) );
break;
=20
@@ -2390,7 +2390,7 @@
vex_printf("dis_int_store(PPC32)(stwu,Ra_addr)\n");
return False;
}
- DIP("stwu r%d,%d(r%d)\n", Rs_addr, simm16, Ra_addr);
+ DIP("stwu r%u,%d(r%u)\n", Rs_addr, simm16, Ra_addr);
putIReg( Ra_addr, mkexpr(EA_imm) );
storeBE( mkexpr(EA_imm), mkexpr(Rs) );
break;
@@ -2409,13 +2409,13 @@
vex_printf("dis_int_store(PPC32)(stbux,Ra_addr)\n");
return False;
}
- DIP("stbux r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ DIP("stbux r%u,r%u,r%u\n", Rs_addr, Ra_addr, Rb_addr);
putIReg( Ra_addr, mkexpr(EA_reg) );
storeBE( mkexpr(EA_reg), unop(Iop_32to8, mkexpr(Rs)) );
break;
=20
case 0x0D7: // stbx (Store B Indexed, PPC32 p512)
- DIP("stbx r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ DIP("stbx r%u,r%u,r%u\n", Rs_addr, Ra_addr, Rb_addr);
storeBE( mkexpr(EA_reg), unop(Iop_32to8, mkexpr(Rs)) );
break;
=20
@@ -2424,13 +2424,13 @@
vex_printf("dis_int_store(PPC32)(sthux,Ra_addr)\n");
return False;
}
- DIP("sthux r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ DIP("sthux r%u,r%u,r%u\n", Rs_addr, Ra_addr, Rb_addr);
putIReg( Ra_addr, mkexpr(EA_reg) );
storeBE( mkexpr(EA_reg), unop(Iop_32to16, mkexpr(Rs)) );
break;
=20
case 0x197: // sthx (Store HW Indexed, PPC32 p526)
- DIP("sthx r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ DIP("sthx r%u,r%u,r%u\n", Rs_addr, Ra_addr, Rb_addr);
storeBE( mkexpr(EA_reg), unop(Iop_32to16, mkexpr(Rs)) );
break;
=20
@@ -2439,13 +2439,13 @@
vex_printf("dis_int_store(PPC32)(stwux,Ra_addr)\n");
return False;
}
- DIP("stwux r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ DIP("stwux r%u,r%u,r%u\n", Rs_addr, Ra_addr, Rb_addr);
putIReg( Ra_addr, mkexpr(EA_reg) );
storeBE( mkexpr(EA_reg), mkexpr(Rs) );
break;
=20
case 0x097: // stwx (Store W Indexed, PPC32 p536)
- DIP("stwx r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ DIP("stwx r%u,r%u,r%u\n", Rs_addr, Ra_addr, Rb_addr);
storeBE( mkexpr(EA_reg), mkexpr(Rs) );
break;
=20
@@ -2562,7 +2562,7 @@
unop(Iop_8Uto32,=20
loadBE(Ity_I8,=20
binop(Iop_Add32, e_EA, mkU32(i)))),=20
- mkU8(shift))=20
+ mkU8(toUChar(shift)))=20
));
shift -=3D 8;
}
@@ -2597,7 +2597,7 @@
storeBE(
binop(Iop_Add32, e_EA, mkU32(i)),
unop(Iop_32to8,
- binop(Iop_Shr32, getIReg(rS), mkU8(shift)))
+ binop(Iop_Shr32, getIReg(rS), mkU8(toUChar(shift))))
);
shift -=3D 8;
}
@@ -3650,7 +3650,7 @@
//zz return False;
=20
default:
- vex_printf("dis_proc_ctl(PPC32)(mtspr,SPR_flipped)(%d)\n",
+ vex_printf("dis_proc_ctl(PPC32)(mtspr,SPR_flipped)(%u)\n",
SPR_flipped);
return False;
}
@@ -6092,7 +6092,7 @@
}
=20
=20
- opc1 =3D ifieldOPC(theInstr);
+ opc1 =3D toUChar(ifieldOPC(theInstr));
opc2 =3D ifieldOPClo10(theInstr);
=20
#if PPC32_TOIR_DEBUG
@@ -6567,7 +6567,7 @@
/* All decode failures end up here. */
vex_printf("disInstr(ppc32): unhandled instruction: "
"0x%x\n", theInstr);
- vex_printf(" primary %d(0x%x), secondary %d(0x%x)\n",=
=20
+ vex_printf(" primary %d(0x%x), secondary %u(0x%x)\n",=
=20
opc1, opc1, opc2, opc2);
=20
#if PPC32_TOIR_DEBUG
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-09-09 19:45:36 UTC (rev 1383)
+++ trunk/priv/host-ppc32/hdefs.c 2005-09-09 22:31:49 UTC (rev 1384)
@@ -435,7 +435,7 @@
if (op->Prh.Imm.syned)
vex_printf("%d", (Int)(Short)op->Prh.Imm.imm16);
else
- vex_printf("%d", (UInt)(UShort)op->Prh.Imm.imm16);
+ vex_printf("%u", (UInt)(UShort)op->Prh.Imm.imm16);
return;
case Prh_Reg:=20
ppHRegPPC32(op->Prh.Reg.reg);
@@ -1015,7 +1015,7 @@
/* generic */
vex_printf("%s ",=20
showPPC32AluOp(i->Pin.Alu32.op,
- i->Pin.Alu32.srcR->tag =3D=3D Prh_Imm=
));
+ toBool(i->Pin.Alu32.srcR->tag =3D=3D =
Prh_Imm)));
ppHRegPPC32(i->Pin.Alu32.dst);
vex_printf(",");
ppHRegPPC32(i->Pin.Alu32.srcL);
@@ -2169,7 +2169,7 @@
=20
case Pin_Alu32: {
PPC32RH* srcR =3D i->Pin.Alu32.srcR;
- Bool immR =3D srcR->tag =3D=3D Prh_Imm;
+ Bool immR =3D toBool(srcR->tag =3D=3D Prh_Imm);
UInt r_dst =3D iregNo(i->Pin.Alu32.dst);
UInt r_srcL =3D iregNo(i->Pin.Alu32.srcL);
UInt r_srcR =3D immR ? (-1)/*bogus*/ : iregNo(srcR->Prh.Reg.re=
g);
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-09-09 19:45:36 UTC (rev 1383)
+++ trunk/priv/host-ppc32/isel.c 2005-09-09 22:31:49 UTC (rev 1384)
@@ -332,14 +332,16 @@
{
HReg sp =3D StackFramePtr;
vassert(n > 0 && n < 256 && (n%16) =3D=3D 0);
- addInstr(env, PPC32Instr_Alu32(Palu_ADD, sp, sp, PPC32RH_Imm(True,n))=
);
+ addInstr(env, PPC32Instr_Alu32(
+ Palu_ADD, sp, sp, PPC32RH_Imm(True,toUShort(n))));
}
=20
static void sub_from_sp ( ISelEnv* env, Int n )
{
HReg sp =3D StackFramePtr;
vassert(n > 0 && n < 256 && (n%16) =3D=3D 0);
- addInstr(env, PPC32Instr_Alu32(Palu_SUB, sp, sp, PPC32RH_Imm(True,n))=
);
+ addInstr(env, PPC32Instr_Alu32(
+ Palu_SUB, sp, sp, PPC32RH_Imm(True,toUShort(n))));
}
=20
=20
@@ -850,8 +852,8 @@
/* widen the left arg if needed */
if ((aluOp =3D=3D Palu_SHR || aluOp =3D=3D Palu_SAR)
&& (ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16)) {
- PPC32RH* amt =3D PPC32RH_Imm(False, ty =3D=3D Ity_I8 ? 24 : =
16);
- HReg tmp =3D newVRegI(env);
+ PPC32RH* amt =3D PPC32RH_Imm(False, toUShort(ty =3D=3D Ity_I=
8 ? 24 : 16));
+ HReg tmp =3D newVRegI(env);
addInstr(env, PPC32Instr_Alu32(Palu_SHL, tmp, r_srcL, amt));
addInstr(env, PPC32Instr_Alu32(aluOp, tmp, tmp, amt));
r_srcL =3D tmp;
@@ -887,7 +889,7 @@
/* El-mutanto 3-way compare? */
if (e->Iex.Binop.op =3D=3D Iop_CmpORD32S
|| e->Iex.Binop.op =3D=3D Iop_CmpORD32U) {
- Bool syned =3D e->Iex.Binop.op =3D=3D Iop_CmpORD32S;
+ Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_CmpORD32S)=
;
HReg dst =3D newVRegI(env);
HReg srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
PPC32RH* srcR =3D iselIntExpr_RH(env, syned, e->Iex.Binop.arg2=
);
@@ -1062,20 +1064,23 @@
case Iop_8Uto16:
case Iop_8Uto32:
case Iop_16Uto32: {
- HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- UInt mask =3D e->Iex.Unop.op=3D=3DIop_16Uto32 ? 0xFFFF : 0xFF;
- addInstr(env, PPC32Instr_Alu32(Palu_AND,r_dst,r_src,PPC32RH_Imm=
(False,mask)));
+ HReg r_dst =3D newVRegI(env);
+ HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ UShort mask =3D toUShort(e->Iex.Unop.op=3D=3DIop_16Uto32 ? 0xF=
FFF : 0xFF);
+ addInstr(env, PPC32Instr_Alu32(Palu_AND,r_dst,r_src,
+ PPC32RH_Imm(False,mask)=
));
return r_dst;
}
case Iop_8Sto16:
case Iop_8Sto32:
case Iop_16Sto32: {
- HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- UInt amt =3D e->Iex.Unop.op=3D=3DIop_16Sto32 ? 16 : 24;
- addInstr(env, PPC32Instr_Alu32(Palu_SHL, r_dst, r_src, PPC32RH_=
Imm(False,amt)));
- addInstr(env, PPC32Instr_Alu32(Palu_SAR, r_dst, r_dst, PPC32RH_=
Imm(False,amt)));
+ HReg r_dst =3D newVRegI(env);
+ HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ UShort amt =3D toUShort(e->Iex.Unop.op=3D=3DIop_16Sto32 ? 16 =
: 24);
+ addInstr(env, PPC32Instr_Alu32(Palu_SHL, r_dst, r_src,=20
+ PPC32RH_Imm(False,amt)=
));
+ addInstr(env, PPC32Instr_Alu32(Palu_SAR, r_dst, r_dst,=20
+ PPC32RH_Imm(False,amt)=
));
return r_dst;
}
case Iop_Not8:
@@ -1132,10 +1137,11 @@
}
case Iop_16HIto8:
case Iop_32HIto16: {
- HReg r_dst =3D newVRegI(env);
- HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
- UInt shift =3D e->Iex.Unop.op =3D=3D Iop_16HIto8 ? 8 : 16;
- addInstr(env, PPC32Instr_Alu32(Palu_SHR, r_dst, r_src, PPC32RH_=
Imm(False,shift)));
+ HReg r_dst =3D newVRegI(env);
+ HReg r_src =3D iselIntExpr_R(env, e->Iex.Unop.arg);
+ UShort shift =3D toUShort(e->Iex.Unop.op =3D=3D Iop_16HIto8 ? 8=
: 16);
+ addInstr(env, PPC32Instr_Alu32(Palu_SHR, r_dst, r_src,=20
+ PPC32RH_Imm(False,shif=
t)));
return r_dst;
}
case Iop_1Uto32:
@@ -1152,8 +1158,10 @@
HReg r_dst =3D newVRegI(env);
PPC32CondCode cond =3D iselCondCode(env, e->Iex.Unop.arg);
addInstr(env, PPC32Instr_Set32(cond,r_dst));
- addInstr(env, PPC32Instr_Alu32(Palu_SHL, r_dst, r_dst, PPC32RH_=
Imm(False,31)));
- addInstr(env, PPC32Instr_Alu32(Palu_SAR, r_dst, r_dst, PPC32RH_=
Imm(False,31)));
+ addInstr(env, PPC32Instr_Alu32(Palu_SHL, r_dst, r_dst,=20
+ PPC32RH_Imm(False,31))=
);
+ addInstr(env, PPC32Instr_Alu32(Palu_SAR, r_dst, r_dst,=20
+ PPC32RH_Imm(False,31))=
);
return r_dst;
}
=20
@@ -1420,10 +1428,10 @@
i =3D (Int)u;
/* Now figure out if it's representable. */
if (!syned && u <=3D 65535) {
- return PPC32RH_Imm(False/*unsigned*/, u & 0xFFFF);
+ return PPC32RH_Imm(False/*unsigned*/, toUShort(u & 0xFFFF));
}
if (syned && i >=3D -32767 && i <=3D 32767) {
- return PPC32RH_Imm(True/*signed*/, u & 0xFFFF);
+ return PPC32RH_Imm(True/*signed*/, toUShort(u & 0xFFFF));
}
/* no luck; use the Slow Way. */
}
Modified: trunk/priv/host-x86/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-x86/hdefs.c 2005-09-09 19:45:36 UTC (rev 1383)
+++ trunk/priv/host-x86/hdefs.c 2005-09-09 22:31:49 UTC (rev 1384)
@@ -2221,7 +2221,7 @@
=20
/* Alternative version which works on any x86 variant. */
/* jmp fwds if !condition */
- *p++ =3D 0x70 + (i->Xin.CMov32.cond ^ 1);
+ *p++ =3D toUChar(0x70 + (i->Xin.CMov32.cond ^ 1));
*p++ =3D 0; /* # of bytes in the next bit, which we don't know yet=
*/
ptmp =3D p;
=20
@@ -2245,7 +2245,7 @@
goto bad;
}
/* Fill in the jump offset. */
- *(ptmp-1) =3D p - ptmp;
+ *(ptmp-1) =3D toUChar(p - ptmp);
goto done;
=20
break;
Modified: trunk/priv/main/vex_util.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/main/vex_util.c 2005-09-09 19:45:36 UTC (rev 1383)
+++ trunk/priv/main/vex_util.c 2005-09-09 22:31:49 UTC (rev 1384)
@@ -106,6 +106,7 @@
/* ugly hack -- do not remove */
//extern void* malloc ( int );
//return malloc(nbytes);
+ return NULL;
} else {
nbytes =3D (nbytes + ALIGN) & ~ALIGN;
if (mode =3D=3D VexAllocModeTEMP) {
@@ -223,7 +224,7 @@
}
=20
while (1) {
- buf[bufi++] =3D '0' + (HChar)(u0 % base);
+ buf[bufi++] =3D toHChar('0' + toUInt(u0 % base));
u0 /=3D base;
if (u0 =3D=3D 0) break;
}
@@ -233,7 +234,7 @@
buf[bufi] =3D 0;
for (i =3D 0; i < bufi; i++)
if (buf[i] > '9')=20
- buf[i] +=3D ((hexcaps ? 'A' : 'a') - '9' - 1);
+ buf[i] =3D toHChar(buf[i] + (hexcaps ? 'A' : 'a') - '9' - 1);
=20
i =3D 0;
j =3D bufi-1;
@@ -374,7 +375,7 @@
}
case 'p':=20
case 'P': {
- Bool hexcaps =3D *format =3D=3D 'P';
+ Bool hexcaps =3D toBool(*format =3D=3D 'P');
ULong l =3D Ptr_to_ULong( va_arg(ap, void*) );
convert_int(intbuf, l, 16/*base*/, False/*unsigned*/, hexcap=
s);
len1 =3D len3 =3D 0;
@@ -415,7 +416,7 @@
=20
static void add_to_myprintf_buf ( HChar c )
{
- Bool emit =3D c =3D=3D '\n' || n_myprintf_buf >=3D 1000-10 /*paranoia=
*/;
+ Bool emit =3D toBool(c =3D=3D '\n' || n_myprintf_buf >=3D 1000-10 /*p=
aranoia*/);
myprintf_buf[n_myprintf_buf++] =3D c;
myprintf_buf[n_myprintf_buf] =3D 0;
if (emit) {
|
|
From: <sv...@va...> - 2005-09-09 19:45:38
|
Author: sewardj
Date: 2005-09-09 20:45:36 +0100 (Fri, 09 Sep 2005)
New Revision: 1383
Log:
iselInt64Expr: handle 64-bit Mux0X.
Modified:
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-09-09 19:45:02 UTC (rev 1382)
+++ trunk/priv/host-ppc32/isel.c 2005-09-09 19:45:36 UTC (rev 1383)
@@ -1868,26 +1868,33 @@
//.. return;
//.. }
=20
-//.. /* 64-bit Mux0X */
-//.. if (e->tag =3D=3D Iex_Mux0X) {
-//.. HReg e0Lo, e0Hi, eXLo, eXHi, r8;
-//.. HReg tLo =3D newVRegI(env);
-//.. HReg tHi =3D newVRegI(env);
-//.. iselInt64Expr(&e0Hi, &e0Lo, env, e->Iex.Mux0X.expr0);
-//.. iselInt64Expr(&eXHi, &eXLo, env, e->Iex.Mux0X.exprX);
-//.. addInstr(env, mk_iMOVsd_RR(eXHi, tHi));
-//.. addInstr(env, mk_iMOVsd_RR(eXLo, tLo));
-//.. r8 =3D iselIntExpr_R(env, e->Iex.Mux0X.cond);
-//.. addInstr(env, X86Instr_Test32(X86RI_Imm(0xFF), X86RM_Reg(r8))=
);
-//.. /* This assumes the first cmov32 doesn't trash the condition
-//.. codes, so they are still available for the second cmov32 *=
/
-//.. addInstr(env, X86Instr_CMov32(Xcc_Z,X86RM_Reg(e0Hi),tHi));
-//.. addInstr(env, X86Instr_CMov32(Xcc_Z,X86RM_Reg(e0Lo),tLo));
-//.. *rHi =3D tHi;
-//.. *rLo =3D tLo;
-//.. return;
-//.. }
+ /* 64-bit Mux0X */
+ if (e->tag =3D=3D Iex_Mux0X) {
+ HReg e0Lo, e0Hi, eXLo, eXHi;
+ HReg tLo =3D newVRegI(env);
+ HReg tHi =3D newVRegI(env);
=20
+ PPC32CondCode cc =3D mk_PPCCondCode( Pct_TRUE, Pcf_7EQ );
+ HReg r_cond =3D iselIntExpr_R(env, e->Iex.Mux0X.cond);
+ HReg r_tmp =3D newVRegI(env);
+
+ iselInt64Expr(&e0Hi, &e0Lo, env, e->Iex.Mux0X.expr0);
+ iselInt64Expr(&eXHi, &eXLo, env, e->Iex.Mux0X.exprX);
+ addInstr(env, mk_iMOVds_RR(tHi,eXHi));
+ addInstr(env, mk_iMOVds_RR(tLo,eXLo));
+
+ addInstr(env, PPC32Instr_Alu32(Palu_AND,=20
+ r_tmp, r_cond, PPC32RH_Imm(False,0x=
FF)));
+ addInstr(env, PPC32Instr_Cmp32(False/*unsigned*/,=20
+ 7/*cr*/, r_tmp, PPC32RH_Imm(False,0=
)));
+
+ addInstr(env, PPC32Instr_CMov32(cc,tHi,PPC32RI_Reg(e0Hi)));
+ addInstr(env, PPC32Instr_CMov32(cc,tLo,PPC32RI_Reg(e0Lo)));
+ *rHi =3D tHi;
+ *rLo =3D tLo;
+ return;
+ }
+
/* --------- BINARY ops --------- */
if (e->tag =3D=3D Iex_Binop) {
switch (e->Iex.Binop.op) {
|
|
From: <sv...@va...> - 2005-09-09 19:45:10
|
Author: sewardj
Date: 2005-09-09 20:45:02 +0100 (Fri, 09 Sep 2005)
New Revision: 1382
Log:
Fix mcrxr.
Modified:
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-09 16:38:19 UTC (rev 1381)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-09 19:45:02 UTC (rev 1382)
@@ -3418,45 +3418,55 @@
=20
switch (opc2) {
/* X-Form */
- case 0x200: // mcrxr (Move to Condition Register from XER, PPC32 p466=
)
+ case 0x200: { // mcrxr (Move to Condition Register from XER, PPC32 p4=
66)
+ IRTemp xer_0to3 =3D newTemp(Ity_I8);
if (b21to22 !=3D 0 || b11to20 !=3D 0) {
vex_printf("dis_proc_ctl(PPC32)(mcrxr,b21to22|b11to20)\n");
return False;
}
DIP("mcrxr crf%d\n", crfD);
- =20
- // CR[7-crfD] =3D XER[28-31]
- putCR321( crfD, unop( Iop_32to8,=20
- binop(
- Iop_Or32,
- binop(
- Iop_Or32,
- binop( Iop_Shl32,=20
- binop( Iop_And32,=20
- unop( Iop_8Uto32,=20
- IRExpr_Get( OFFB_XER_SO, Ity_I8=
)),=20
- mkU32(1)),=20
- mkU8(31)),
- binop( Iop_Shl32,=20
- binop( Iop_And32,=20
- unop( Iop_8Uto32,=20
- IRExpr_Get( OFFB_XER_OV, Ity_I8=
)),=20
- mkU32(1)),=20
- mkU8(30))
- ),
- binop( Iop_Shl32,=20
- binop( Iop_And32,=20
- unop( Iop_8Uto32,=20
- IRExpr_Get( OFFB_XER_CA, Ity_I8 ))=
,=20
- mkU32(1)),=20
- mkU8(29))
- ) ) );
=20
- // Clear XER[28 - 31]
+ /* Compute XER[0-3] (the top 4 bits of XER) into the bottom
+ 4 bits of xer_0to3. */
+ assign(=20
+ xer_0to3,
+ unop(Iop_32to8,
+ binop(
+ Iop_Or32,
+ binop(
+ Iop_Or32,
+ binop( Iop_Shl32,=20
+ binop( Iop_And32,=20
+ unop( Iop_8Uto32,=20
+ IRExpr_Get( OFFB_XER_SO, Ity_I8 =
)),=20
+ mkU32(1)),=20
+ mkU8(31 -28)),
+ binop( Iop_Shl32,=20
+ binop( Iop_And32,=20
+ unop( Iop_8Uto32,=20
+ IRExpr_Get( OFFB_XER_OV, Ity_I8 =
)),=20
+ mkU32(1)),=20
+ mkU8(30 -28))
+ ),
+ binop( Iop_Shl32,=20
+ binop( Iop_And32,=20
+ unop( Iop_8Uto32,=20
+ IRExpr_Get( OFFB_XER_CA, Ity_I8 )),=
=20
+ mkU32(1)),=20
+ mkU8(29 -28))
+ )
+ )
+ );
+
+ putCR321( crfD, binop(Iop_And8, mkexpr(xer_0to3), mkU8(7<<1)) );
+ putCR0 ( crfD, binop(Iop_And8, mkexpr(xer_0to3), mkU8(1)) );
+
+ // Clear XER[0-3]
stmt( IRStmt_Put( OFFB_XER_SO, mkU8(0) ) );
stmt( IRStmt_Put( OFFB_XER_OV, mkU8(0) ) );
stmt( IRStmt_Put( OFFB_XER_CA, mkU8(0) ) );
break;
+ }
=20
case 0x013: // mfcr (Move from Condition Register, PPC32 p467)
if (b11to20 !=3D 0) {
|
|
From: <sv...@va...> - 2005-09-09 16:38:21
|
Author: cerion
Date: 2005-09-09 17:38:19 +0100 (Fri, 09 Sep 2005)
New Revision: 1381
Log:
reinstate lhau, lhaux, sthux, mcrxr
Modified:
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-09 16:31:24 UTC (rev 1380)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-09 16:38:19 UTC (rev 1381)
@@ -2188,16 +2188,16 @@
loadBE(Ity_I16, mkexpr(EA_imm))) );
break;
=20
-//zz case 0x2B: // lhau (Load HW Algebraic with Update, PPC32 p446)
-//zz if (Ra_addr =3D=3D 0 || Ra_addr =3D=3D Rd_addr) {
-//zz vex_printf("dis_int_load(PPC32)(lhau,Ra_addr|Rd_addr)\n");
-//zz return False;
-//zz }
-//zz DIP("lhau r%d,%d(r%d)\n", Rd_addr, (Int)d_imm, Ra_addr);
-//zz putIReg( Rd_addr, unop(Iop_16Sto32,
-//zz loadBE(Ity_I16, mkexpr(EA_imm))) );
-//zz putIReg( Ra_addr, mkexpr(EA_imm) );
-//zz break;
+ case 0x2B: // lhau (Load HW Algebraic with Update, PPC32 p446)
+ if (Ra_addr =3D=3D 0 || Ra_addr =3D=3D Rd_addr) {
+ vex_printf("dis_int_load(PPC32)(lhau,Ra_addr|Rd_addr)\n");
+ return False;
+ }
+ DIP("lhau r%d,%d(r%d)\n", Rd_addr, (Int)d_imm, Ra_addr);
+ putIReg( Rd_addr, unop(Iop_16Sto32,
+ loadBE(Ity_I16, mkexpr(EA_imm))) );
+ putIReg( Ra_addr, mkexpr(EA_imm) );
+ break;
=20
case 0x28: // lhz (Load HW & Zero, PPC32 p450)
DIP("lhz r%d,%d(r%d)\n", Rd_addr, exts_d_imm, Ra_addr);
@@ -2257,16 +2257,16 @@
loadBE(Ity_I8, mkexpr(EA_reg))) );
break;
=20
-//zz case 0x177: // lhaux (Load HW Algebraic with Update Indexed, =
PPC32 p447)
-//zz if (Ra_addr =3D=3D 0 || Ra_addr =3D=3D Rd_addr) {
-//zz vex_printf("dis_int_load(PPC32)(lhaux,Ra_addr|Rd_addr)\=
n");
-//zz return False;
-//zz }
-//zz DIP("lhaux r%d,r%d,r%d\n", Rd_addr, Ra_addr, Rb_addr);
-//zz putIReg( Rd_addr, unop(Iop_16Sto32,
-//zz loadBE(Ity_I16, mkexpr(EA_reg))) );
-//zz putIReg( Ra_addr, mkexpr(EA_reg) );
-//zz break;
+ case 0x177: // lhaux (Load HW Algebraic with Update Indexed, PPC32=
p447)
+ if (Ra_addr =3D=3D 0 || Ra_addr =3D=3D Rd_addr) {
+ vex_printf("dis_int_load(PPC32)(lhaux,Ra_addr|Rd_addr)\n");
+ return False;
+ }
+ DIP("lhaux r%d,r%d,r%d\n", Rd_addr, Ra_addr, Rb_addr);
+ putIReg( Rd_addr, unop(Iop_16Sto32,
+ loadBE(Ity_I16, mkexpr(EA_reg))) );
+ putIReg( Ra_addr, mkexpr(EA_reg) );
+ break;
=20
case 0x157: // lhax (Load HW Algebraic Indexed, PPC32 p448)
DIP("lhax r%d,r%d,r%d\n", Rd_addr, Ra_addr, Rb_addr);
@@ -2419,15 +2419,15 @@
storeBE( mkexpr(EA_reg), unop(Iop_32to8, mkexpr(Rs)) );
break;
=20
-//zz case 0x1B7: // sthux (Store HW with Update Indexed, PPC32 p52=
5)
-//zz if (Ra_addr =3D=3D 0) {
-//zz vex_printf("dis_int_store(PPC32)(sthux,Ra_addr)\n");
-//zz return False;
-//zz }
-//zz DIP("sthux r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
-//zz putIReg( Ra_addr, mkexpr(EA_reg) );
-//zz storeBE( mkexpr(EA_reg), mkexpr(Rs_16) );
-//zz break;
+ case 0x1B7: // sthux (Store HW with Update Indexed, PPC32 p525)
+ if (Ra_addr =3D=3D 0) {
+ vex_printf("dis_int_store(PPC32)(sthux,Ra_addr)\n");
+ return False;
+ }
+ DIP("sthux r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ putIReg( Ra_addr, mkexpr(EA_reg) );
+ storeBE( mkexpr(EA_reg), unop(Iop_32to16, mkexpr(Rs)) );
+ break;
=20
case 0x197: // sthx (Store HW Indexed, PPC32 p526)
DIP("sthx r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
@@ -3385,8 +3385,8 @@
UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
=20
/* X-Form */
-//uu UChar crfD =3D toUChar((theInstr >> 23) & 0x7); /* theInstr[=
23:25] */
-//uu UChar b21to22 =3D toUChar((theInstr >> 21) & 0x3); /* theInstr[=
21:22] */
+ UChar crfD =3D toUChar((theInstr >> 23) & 0x7); /* theInstr[23:2=
5] */
+ UChar b21to22 =3D toUChar((theInstr >> 21) & 0x3); /* theInstr[21:2=
2] */
UChar Rd_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
UInt b11to20 =3D (theInstr >> 11) & 0x3FF; /* theInstr[11:2=
0] */
=20
@@ -3417,22 +3417,47 @@
}
=20
switch (opc2) {
-//zz /* X-Form */
-//zz case 0x200: // mcrxr (Move to Condition Register from XER, PPC32=
p466)
-//zz if (b21to22 !=3D 0 || b11to20 !=3D 0) {
-//zz vex_printf("dis_proc_ctl(PPC32)(mcrxr,b21to22|b11to20)\n")=
;
-//zz return False;
-//zz }
-//zz DIP("mcrxr crf%d\n", crfD);
-//zz =20
-//zz // CR[7-crfD] =3D XER[28-31]
-//zz assign( tmp, getReg_field( PPC32_SPR_XER, 7 ) );
-//zz putReg_field( PPC32_SPR_CR, mkexpr(tmp), 7-crfD );
-//zz =20
-//zz // Clear XER[28 - 31]
-//zz putReg_field( PPC32_SPR_XER, mkU32(0), 7 );
-//zz break;
+ /* X-Form */
+ case 0x200: // mcrxr (Move to Condition Register from XER, PPC32 p466=
)
+ if (b21to22 !=3D 0 || b11to20 !=3D 0) {
+ vex_printf("dis_proc_ctl(PPC32)(mcrxr,b21to22|b11to20)\n");
+ return False;
+ }
+ DIP("mcrxr crf%d\n", crfD);
=20
+ // CR[7-crfD] =3D XER[28-31]
+ putCR321( crfD, unop( Iop_32to8,=20
+ binop(
+ Iop_Or32,
+ binop(
+ Iop_Or32,
+ binop( Iop_Shl32,=20
+ binop( Iop_And32,=20
+ unop( Iop_8Uto32,=20
+ IRExpr_Get( OFFB_XER_SO, Ity_I8=
)),=20
+ mkU32(1)),=20
+ mkU8(31)),
+ binop( Iop_Shl32,=20
+ binop( Iop_And32,=20
+ unop( Iop_8Uto32,=20
+ IRExpr_Get( OFFB_XER_OV, Ity_I8=
)),=20
+ mkU32(1)),=20
+ mkU8(30))
+ ),
+ binop( Iop_Shl32,=20
+ binop( Iop_And32,=20
+ unop( Iop_8Uto32,=20
+ IRExpr_Get( OFFB_XER_CA, Ity_I8 ))=
,=20
+ mkU32(1)),=20
+ mkU8(29))
+ ) ) );
+
+ // Clear XER[28 - 31]
+ stmt( IRStmt_Put( OFFB_XER_SO, mkU8(0) ) );
+ stmt( IRStmt_Put( OFFB_XER_OV, mkU8(0) ) );
+ stmt( IRStmt_Put( OFFB_XER_CA, mkU8(0) ) );
+ break;
+ =20
case 0x013: // mfcr (Move from Condition Register, PPC32 p467)
if (b11to20 !=3D 0) {
vex_printf("dis_proc_ctl(PPC32)(mfcr,b11to20)\n");
|
|
From: <sv...@va...> - 2005-09-09 16:31:29
|
Author: cerion
Date: 2005-09-09 17:31:24 +0100 (Fri, 09 Sep 2005)
New Revision: 1380
Log:
implemented Iop_64HLtoV128 in iselVecExpr_wrk
Modified:
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-09-09 10:36:55 UTC (rev 1379)
+++ trunk/priv/host-ppc32/isel.c 2005-09-09 16:31:24 UTC (rev 1380)
@@ -2798,10 +2798,10 @@
//.. addInstr(env, X86Instr_SseConst(e->Iex.Const.con->Ico.V128, d=
st));
//.. return dst;
//.. }
-//..=20
-//.. if (e->tag =3D=3D Iex_Unop) {
-//.. switch (e->Iex.Unop.op) {
-//..=20
+
+ if (e->tag =3D=3D Iex_Unop) {
+ switch (e->Iex.Unop.op) {
+
//.. case Iop_Not128: {
//.. HReg arg =3D iselVecExpr(env, e->Iex.Unop.arg);
//.. return do_sse_Not128(env, arg);
@@ -2970,15 +2970,15 @@
//.. add_to_esp(env, 8);
//.. return dst;
//.. }
-//..=20
-//.. default:
-//.. break;
-//.. } /* switch (e->Iex.Unop.op) */
-//.. } /* if (e->tag =3D=3D Iex_Unop) */
-//..=20
-//.. if (e->tag =3D=3D Iex_Binop) {
-//.. switch (e->Iex.Binop.op) {
-//..=20
+
+ default:
+ break;
+ } /* switch (e->Iex.Unop.op) */
+ } /* if (e->tag =3D=3D Iex_Unop) */
+
+ if (e->tag =3D=3D Iex_Binop) {
+ switch (e->Iex.Binop.op) {
+
//.. case Iop_SetV128lo32: {
//.. HReg dst =3D newVRegV(env);
//.. HReg srcV =3D iselVecExpr(env, e->Iex.Binop.arg1);
@@ -3008,29 +3008,29 @@
//.. return dst;
//.. }
//..=20
-//.. case Iop_64HLtoV128: {
-//.. HReg r3, r2, r1, r0;
-//.. X86AMode* esp0 =3D X86AMode_IR(0, hregX86_ESP());
-//.. X86AMode* esp4 =3D advance4(esp0);
-//.. X86AMode* esp8 =3D advance4(esp4);
-//.. X86AMode* esp12 =3D advance4(esp8);
-//.. HReg dst =3D newVRegV(env);
-//.. /* do this via the stack (easy, convenient, etc) */
-//.. sub_from_esp(env, 16);
-//.. /* Do the less significant 64 bits */
-//.. iselInt64Expr(&r1, &r0, env, e->Iex.Binop.arg2);
-//.. addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(r0), esp=
0));
-//.. addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(r1), esp=
4));
-//.. /* Do the more significant 64 bits */
-//.. iselInt64Expr(&r3, &r2, env, e->Iex.Binop.arg1);
-//.. addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(r2), esp=
8));
-//.. addInstr(env, X86Instr_Alu32M(Xalu_MOV, X86RI_Reg(r3), esp=
12));
-//.. /* Fetch result back from stack. */
-//.. addInstr(env, X86Instr_SseLdSt(True/*load*/, dst, esp0));
-//.. add_to_esp(env, 16);
-//.. return dst;
-//.. }
-//..=20
+ case Iop_64HLtoV128: {
+ HReg r3, r2, r1, r0;
+ PPC32AMode *sp0 =3D PPC32AMode_IR(0, StackFramePtr);
+ PPC32AMode *sp4 =3D PPC32AMode_IR(4, StackFramePtr);
+ PPC32AMode *sp8 =3D PPC32AMode_IR(8, StackFramePtr);
+ PPC32AMode *sp12 =3D PPC32AMode_IR(12, StackFramePtr);
+ HReg dst =3D newVRegV(env);
+ /* do this via the stack (easy, convenient, etc) */
+ sub_from_sp( env, 16 ); // Move SP down 16 bytes
+ /* Do the less significant 64 bits */
+ iselInt64Expr(&r1, &r0, env, e->Iex.Binop.arg2);
+ addInstr(env, PPC32Instr_Store( 4, sp12, r0 ));
+ addInstr(env, PPC32Instr_Store( 4, sp8, r1 ));
+ /* Do the more significant 64 bits */
+ iselInt64Expr(&r3, &r2, env, e->Iex.Binop.arg1);
+ addInstr(env, PPC32Instr_Store( 4, sp4, r2 ));
+ addInstr(env, PPC32Instr_Store( 4, sp0, r3 ));
+ /* Fetch result back from stack. */
+ addInstr(env, PPC32Instr_AvLdSt(True/*load*/, 16, dst, sp0));
+ add_to_sp( env, 16 ); // Reset SP
+ return dst;
+ }
+
//.. case Iop_CmpEQ32Fx4: op =3D Xsse_CMPEQF; goto do_32Fx4;
//.. case Iop_CmpLT32Fx4: op =3D Xsse_CMPLTF; goto do_32Fx4;
//.. case Iop_CmpLE32Fx4: op =3D Xsse_CMPLEF; goto do_32Fx4;
@@ -3207,12 +3207,12 @@
//.. add_to_esp(env, 16);
//.. return dst;
//.. }
-//..=20
-//.. default:
-//.. break;
-//.. } /* switch (e->Iex.Binop.op) */
-//.. } /* if (e->tag =3D=3D Iex_Binop) */
-//..=20
+
+ default:
+ break;
+ } /* switch (e->Iex.Binop.op) */
+ } /* if (e->tag =3D=3D Iex_Binop) */
+
//.. if (e->tag =3D=3D Iex_Mux0X) {
//.. HReg r8 =3D iselIntExpr_R(env, e->Iex.Mux0X.cond);
//.. HReg rX =3D iselVecExpr(env, e->Iex.Mux0X.exprX);
|
|
From: <sv...@va...> - 2005-09-09 12:03:35
|
Author: sewardj
Date: 2005-09-09 13:03:28 +0100 (Fri, 09 Sep 2005)
New Revision: 4614
Log:
Fix register constraints to this works with both -O and without (David
Woodhouse).
Modified:
trunk/none/tests/ppc32/lsw.c
Modified: trunk/none/tests/ppc32/lsw.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/lsw.c 2005-09-09 11:33:25 UTC (rev 4613)
+++ trunk/none/tests/ppc32/lsw.c 2005-09-09 12:03:28 UTC (rev 4614)
@@ -3,6 +3,11 @@
#include <stdlib.h>
#include <string.h>
=20
+/* Apparently the "b" register constraint is like "r" except that it
+ disallows the use of r0, which means it is safe to use in places
+ where the appearance of r0 would cause a problem due to it being
+ read as zero. */
+
static void announce ( char* str )
{
printf("------ %s ------\n", str);
@@ -21,7 +26,7 @@
"stw 3,0(%1)\n\t"
"stw 4,4(%1)\n\t"
"stw 5,8(%1)\n\t"
- : : "r"(a1), "r"(a2) : "r3", "r4", "r5",=20
+ : : "b"(a1), "b"(a2) : "r3", "r4", "r5",=20
"cc", "memory" );
printf("%s\n", a2);
for (i =3D 0; i < 12; i++)
@@ -34,7 +39,7 @@
"stw 3,0(%1)\n\t"
"stw 4,4(%1)\n\t"
"stw 5,8(%1)\n\t"
- : : "r"(a1), "r"(a2) : "r3", "r4", "r5",=20
+ : : "b"(a1), "b"(a2) : "r3", "r4", "r5",=20
"cc", "memory" );
printf("%s\n", a2);
for (i =3D 0; i < 12; i++)
@@ -51,7 +56,7 @@
"stw 3,0(%1)\n\t"
"stw 4,4(%1)\n\t"
"stw 5,8(%1)\n\t"
- : : "r"(a1), "r"(a2), "r"(16) : "r3", "r4", "r5", "r8",=20
+ : : "b"(a1), "b"(a2), "b"(16) : "r3", "r4", "r5", "r8",=20
"cc", "memory" );
printf("%s\n", a2);
for (i =3D 0; i < 12; i++)
@@ -64,7 +69,7 @@
a2 =3D calloc(100,1);
asm volatile("lswi 3,%0, 19\n\t"
"stswi 3,%1, 8\n"
- : : "r"(a1), "r"(a2) : "r3","r4","r5","r6","r7",
+ : : "b"(a1), "b"(a2) : "r3","r4","r5","r6","r7",
"cc", "memory" );
printf("%s\n", a2);
printf("\n");
@@ -75,7 +80,7 @@
a2 =3D calloc(100,1);
asm volatile("lswi 3,%0, 19\n\t"
"stswi 3,%1, 17\n"
- : : "r"(a1), "r"(a2) : "r3","r4","r5","r6","r7",
+ : : "b"(a1), "b"(a2) : "r3","r4","r5","r6","r7",
"cc", "memory" );
printf("%s\n", a2);
printf("\n");
@@ -88,7 +93,7 @@
"mtxer 8\n\t"
"lswx 3,%0,%2\n\t"=20
"stswx 3,%1,%2\n\t"=20
- : : "r"(a1), "r"(a2), "r"(16) : "r3", "r4", "r5", "r8",=20
+ : : "b"(a1), "b"(a2), "b"(16) : "r3", "r4", "r5", "r8",=20
"cc", "memory" );
printf("%s\n", a2+16);
printf("\n");
|
|
From: <sv...@va...> - 2005-09-09 11:33:31
|
Author: sewardj
Date: 2005-09-09 12:33:25 +0100 (Fri, 09 Sep 2005)
New Revision: 4613
Log:
Add a test for {l,st}sw{s,i}. At the moment only works when the program =
is
compiled -O due to inline assembly problems, and so it fails in a standar=
d
'make regtest'.
Added:
trunk/none/tests/ppc32/lsw.c
trunk/none/tests/ppc32/lsw.stderr.exp
trunk/none/tests/ppc32/lsw.stdout.exp
trunk/none/tests/ppc32/lsw.vgtest
Modified:
trunk/none/tests/ppc32/Makefile.am
Modified: trunk/none/tests/ppc32/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/Makefile.am 2005-09-09 11:28:02 UTC (rev 4612)
+++ trunk/none/tests/ppc32/Makefile.am 2005-09-09 11:33:25 UTC (rev 4613)
@@ -0,0 +1,13 @@
+
+noinst_SCRIPTS =3D filter_cpuid filter_stderr filter_int
+
+CLEANFILES =3D $(addsuffix .c,$(INSN_TESTS))
+
+EXTRA_DIST =3D $(noinst_SCRIPTS) \
+ lsw.stderr.exp lsw.stdout.exp lsw.vgtest
+
+check_PROGRAMS =3D \
+ lsw
+
+AM_CFLAGS =3D $(WERROR) -Winline -Wall -Wshadow -g -I$(top_srcdir)/inc=
lude
+AM_CXXFLAGS =3D $(AM_CFLAGS)
Added: trunk/none/tests/ppc32/lsw.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/lsw.c 2005-09-09 11:28:02 UTC (rev 4612)
+++ trunk/none/tests/ppc32/lsw.c 2005-09-09 11:33:25 UTC (rev 4613)
@@ -0,0 +1,97 @@
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+static void announce ( char* str )
+{
+ printf("------ %s ------\n", str);
+}
+
+int main ( void )
+{
+ int i;
+ char* a1 =3D malloc(100);
+ char* a2 =3D malloc(100);
+ strcpy(a1,"here is a stringHERE IS A STRING");
+
+ announce("lswi n =3D=3D 8 (fe special cased)");
+ asm volatile("li 5,0\n\t"
+ "lswi 3,%0, 8\n\t"=20
+ "stw 3,0(%1)\n\t"
+ "stw 4,4(%1)\n\t"
+ "stw 5,8(%1)\n\t"
+ : : "r"(a1), "r"(a2) : "r3", "r4", "r5",=20
+ "cc", "memory" );
+ printf("%s\n", a2);
+ for (i =3D 0; i < 12; i++)
+ printf("%d =3D 0x%2x\n", i, a2[i]);
+ printf("\n");
+
+
+ announce("lswi n /=3D 8");
+ asm volatile("lswi 3,%0, 9\n\t"=20
+ "stw 3,0(%1)\n\t"
+ "stw 4,4(%1)\n\t"
+ "stw 5,8(%1)\n\t"
+ : : "r"(a1), "r"(a2) : "r3", "r4", "r5",=20
+ "cc", "memory" );
+ printf("%s\n", a2);
+ for (i =3D 0; i < 12; i++)
+ printf("%d =3D 0x%2x\n", i, a2[i]);
+ printf("\n");
+
+
+ announce("lswx");
+ free(a2);
+ a2 =3D malloc(100);
+ asm volatile("li 8, 11\n\t"
+ "mtxer 8\n\t"
+ "lswx 3,%0,%2\n\t"=20
+ "stw 3,0(%1)\n\t"
+ "stw 4,4(%1)\n\t"
+ "stw 5,8(%1)\n\t"
+ : : "r"(a1), "r"(a2), "r"(16) : "r3", "r4", "r5", "r8",=20
+ "cc", "memory" );
+ printf("%s\n", a2);
+ for (i =3D 0; i < 12; i++)
+ printf("%d =3D 0x%2x\n", i, a2[i]);
+ printf("\n");
+
+
+ announce("stswi n =3D=3D 8 (fe special cased)");
+ free(a2);
+ a2 =3D calloc(100,1);
+ asm volatile("lswi 3,%0, 19\n\t"
+ "stswi 3,%1, 8\n"
+ : : "r"(a1), "r"(a2) : "r3","r4","r5","r6","r7",
+ "cc", "memory" );
+ printf("%s\n", a2);
+ printf("\n");
+
+
+ announce("stswi n /=3D 8");
+ free(a2);
+ a2 =3D calloc(100,1);
+ asm volatile("lswi 3,%0, 19\n\t"
+ "stswi 3,%1, 17\n"
+ : : "r"(a1), "r"(a2) : "r3","r4","r5","r6","r7",
+ "cc", "memory" );
+ printf("%s\n", a2);
+ printf("\n");
+
+
+ announce("stswx");
+ free(a2);
+ a2 =3D calloc(100,1);
+ asm volatile("li 8, 11\n\t"
+ "mtxer 8\n\t"
+ "lswx 3,%0,%2\n\t"=20
+ "stswx 3,%1,%2\n\t"=20
+ : : "r"(a1), "r"(a2), "r"(16) : "r3", "r4", "r5", "r8",=20
+ "cc", "memory" );
+ printf("%s\n", a2+16);
+ printf("\n");
+
+ return 0;
+}
Added: trunk/none/tests/ppc32/lsw.stderr.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/lsw.stderr.exp 2005-09-09 11:28:02 UTC (rev 46=
12)
+++ trunk/none/tests/ppc32/lsw.stderr.exp 2005-09-09 11:33:25 UTC (rev 46=
13)
@@ -0,0 +1,2 @@
+
+
Added: trunk/none/tests/ppc32/lsw.stdout.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/lsw.stdout.exp 2005-09-09 11:28:02 UTC (rev 46=
12)
+++ trunk/none/tests/ppc32/lsw.stdout.exp 2005-09-09 11:33:25 UTC (rev 46=
13)
@@ -0,0 +1,54 @@
+------ lswi n =3D=3D 8 (fe special cased) ------
+here is=20
+0 =3D 0x68
+1 =3D 0x65
+2 =3D 0x72
+3 =3D 0x65
+4 =3D 0x20
+5 =3D 0x69
+6 =3D 0x73
+7 =3D 0x20
+8 =3D 0x 0
+9 =3D 0x 0
+10 =3D 0x 0
+11 =3D 0x 0
+
+------ lswi n /=3D 8 ------
+here is a
+0 =3D 0x68
+1 =3D 0x65
+2 =3D 0x72
+3 =3D 0x65
+4 =3D 0x20
+5 =3D 0x69
+6 =3D 0x73
+7 =3D 0x20
+8 =3D 0x61
+9 =3D 0x 0
+10 =3D 0x 0
+11 =3D 0x 0
+
+------ lswx ------
+HERE IS A S
+0 =3D 0x48
+1 =3D 0x45
+2 =3D 0x52
+3 =3D 0x45
+4 =3D 0x20
+5 =3D 0x49
+6 =3D 0x53
+7 =3D 0x20
+8 =3D 0x41
+9 =3D 0x20
+10 =3D 0x53
+11 =3D 0x 0
+
+------ stswi n =3D=3D 8 (fe special cased) ------
+here is=20
+
+------ stswi n /=3D 8 ------
+here is a stringH
+
+------ stswx ------
+HERE IS A S
+
Added: trunk/none/tests/ppc32/lsw.vgtest
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ppc32/lsw.vgtest 2005-09-09 11:28:02 UTC (rev 4612)
+++ trunk/none/tests/ppc32/lsw.vgtest 2005-09-09 11:33:25 UTC (rev 4613)
@@ -0,0 +1 @@
+prog: lsw
|
|
From: <sv...@va...> - 2005-09-09 11:28:07
|
Author: sewardj Date: 2005-09-09 12:28:02 +0100 (Fri, 09 Sep 2005) New Revision: 4612 Log: These seem to be needed to make regtesting work. Not sure why -- they ar= e identical to the x86 and amd64 ones. Added: trunk/none/tests/ppc32/filter_cpuid trunk/none/tests/ppc32/filter_int trunk/none/tests/ppc32/filter_stderr Added: trunk/none/tests/ppc32/filter_cpuid =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/ppc32/filter_cpuid 2005-09-08 09:30:35 UTC (rev 4611= ) +++ trunk/none/tests/ppc32/filter_cpuid 2005-09-09 11:28:02 UTC (rev 4612= ) @@ -0,0 +1,5 @@ +#! /bin/sh + +dir=3D`dirname $0` + +$dir/filter_stderr Property changes on: trunk/none/tests/ppc32/filter_cpuid ___________________________________________________________________ Name: svn:executable + * Added: trunk/none/tests/ppc32/filter_int =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/ppc32/filter_int 2005-09-08 09:30:35 UTC (rev 4611) +++ trunk/none/tests/ppc32/filter_int 2005-09-09 11:28:02 UTC (rev 4612) @@ -0,0 +1,6 @@ +#! /bin/sh + +dir=3D`dirname $0` + +$dir/filter_stderr | $dir/../../../tests/filter_addresses + Property changes on: trunk/none/tests/ppc32/filter_int ___________________________________________________________________ Name: svn:executable + * Added: trunk/none/tests/ppc32/filter_stderr =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/none/tests/ppc32/filter_stderr 2005-09-08 09:30:35 UTC (rev 461= 1) +++ trunk/none/tests/ppc32/filter_stderr 2005-09-09 11:28:02 UTC (rev 461= 2) @@ -0,0 +1,4 @@ +#! /bin/sh + +../filter_stderr + Property changes on: trunk/none/tests/ppc32/filter_stderr ___________________________________________________________________ Name: svn:executable + * |
|
From: <sv...@va...> - 2005-09-09 10:36:59
|
Author: sewardj
Date: 2005-09-09 11:36:55 +0100 (Fri, 09 Sep 2005)
New Revision: 1379
Log:
Reinstate stfdux, fctiw.
Modified:
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-09 10:25:39 UTC (rev 1378)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-09 10:36:55 UTC (rev 1379)
@@ -4010,17 +4010,17 @@
storeBE( mkexpr(EA), mkexpr(frS) );
break;
=20
-//zz case 0x2F7: // stfdux (Store Float Double with Update Indexed=
, PPC32 p515)
-//zz if (rA_addr =3D=3D 0) {
-//zz vex_printf("dis_fp_store(PPC32)(instr,stfdux)\n");
-//zz return False;
-//zz }
-//zz DIP("stfdux fr%d,r%d,r%d\n", frS_addr, rA_addr, rB_addr);
-//zz assign( EA, binop(Iop_Add32, mkexpr(rB), mkexpr(rA)) );
-//zz storeBE( mkexpr(EA), mkexpr(frS) );
-//zz putIReg( rA_addr, mkexpr(EA) );
-//zz break;
-//zz=20
+ case 0x2F7: // stfdux (Store Float Double with Update Indexed, =
PPC32 p515)
+ if (rA_addr =3D=3D 0) {
+ vex_printf("dis_fp_store(PPC32)(instr,stfdux)\n");
+ return False;
+ }
+ DIP("stfdux fr%d,r%d,r%d\n", frS_addr, rA_addr, rB_addr);
+ assign( EA, binop(Iop_Add32, mkexpr(rB), mkexpr(rA)) );
+ storeBE( mkexpr(EA), mkexpr(frS) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
//zz case 0x3D7: // stfiwx (Store Float as Int, Indexed, PPC32 p51=
7)
//zz DIP("stfiwx fr%d,r%d,r%d\n", frS_addr, rA_addr, rB_addr);
//zz assign( EA, binop(Iop_Add32, mkexpr(rB), mkexpr(rA_or_0)) =
);
@@ -4488,12 +4488,12 @@
assign( frD, roundToSgl( mkexpr(frB) ));
break;
=20
-//zz case 0x00E: // fctiw (Floating Conv to Int, PPC32 p404)
-//zz DIP("fctiw%s fr%d,fr%d\n", flag_Rc ? "." : "", frD_addr, frB_=
addr);
-//zz assign( r_tmp, binop(Iop_F64toI32, get_roundingmode(), mkexpr=
(frB)) );
-//zz assign( frD, unop( Iop_ReinterpI64asF64,
-//zz unop( Iop_32Uto64, mkexpr(r_tmp))));
-//zz break;
+ case 0x00E: // fctiw (Floating Conv to Int, PPC32 p404)
+ DIP("fctiw%s fr%d,fr%d\n", flag_Rc ? "." : "", frD_addr, frB_ad=
dr);
+ assign( r_tmp, binop(Iop_F64toI32, get_roundingmode(), mkexpr(f=
rB)) );
+ assign( frD, unop( Iop_ReinterpI64asF64,
+ unop( Iop_32Uto64, mkexpr(r_tmp))));
+ break;
=20
case 0x00F: // fctiwz (Floating Conv to Int, Round to Zero, PPC32 =
p405)
DIP("fctiwz%s fr%d,fr%d\n", flag_Rc ? "." : "", frD_addr, frB_a=
ddr);
|
|
From: <sv...@va...> - 2005-09-09 10:25:46
|
Author: sewardj
Date: 2005-09-09 11:25:39 +0100 (Fri, 09 Sep 2005)
New Revision: 1378
Log:
Cleanups:
- remove various unused vars
- try and use ea_standard/ea_rA_or_zero where possible to do
effective-address computations
Modified:
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-09 09:50:34 UTC (rev 1377)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-09 10:25:39 UTC (rev 1378)
@@ -2160,7 +2160,7 @@
assign( Ra, getIReg(Ra_addr) );
assign( Rb, getIReg(Rb_addr) );
=20
- assign( Ra_or_0, ((Ra_addr =3D=3D 0) ? mkU32(0) : mkexpr(Ra)) );
+ assign( Ra_or_0, ea_rA_or_zero(Ra_addr));
=20
assign( EA_imm, binop(Iop_Add32, mkexpr(Ra_or_0), mkU32(exts_d_imm)) =
);
=20
@@ -2337,33 +2337,23 @@
UInt opc2 =3D ifieldOPClo10(theInstr); /* theInstr[1:10] */
UInt b0 =3D ifieldBIT0(theInstr); /* theInstr[0] */
=20
- IRTemp Ra =3D newTemp(Ity_I32);
IRTemp Ra_or_0 =3D newTemp(Ity_I32);
IRTemp Rb =3D newTemp(Ity_I32);
IRTemp Rs =3D newTemp(Ity_I32);
-// IRTemp Rs_8 =3D newTemp(Ity_I8);
-//IRTemp Rs_16 =3D newTemp(Ity_I16);
IRTemp EA_imm =3D newTemp(Ity_I32);
IRTemp EA_reg =3D newTemp(Ity_I32);
=20
- assign( Ra, getIReg(Ra_addr) );
assign( Rb, getIReg(Rb_addr) );
assign( Rs, getIReg(Rs_addr) );
- //assign( Rs_8, unop(Iop_32to8, mkexpr(Rs)) );
- //assign( Rs_16, unop(Iop_32to16, mkexpr(Rs)) );
=20
- if (Ra_addr =3D=3D 0) {
- assign( Ra_or_0, mkU32(0) );
- } else {
- assign( Ra_or_0, mkexpr(Ra) );
- }
+ assign( Ra_or_0, ea_rA_or_zero(Ra_addr) );
assign( EA_imm, binop(Iop_Add32, mkexpr(Ra_or_0), mkU32(simm16)) );
=20
switch (opc1) {
- case 0x26: // stb (Store B, PPC32 p509)
- DIP("stb r%d,%d(r%d)\n", Rs_addr, simm16, Ra_addr);
- storeBE( mkexpr(EA_imm), unop(Iop_32to8, mkexpr(Rs)) );
- break;
+ case 0x26: // stb (Store B, PPC32 p509)
+ DIP("stb r%d,%d(r%d)\n", Rs_addr, simm16, Ra_addr);
+ storeBE( mkexpr(EA_imm), unop(Iop_32to8, mkexpr(Rs)) );
+ break;
=20
case 0x27: // stbu (Store B with Update, PPC32 p510)
if (Ra_addr =3D=3D 0 ) {
@@ -2696,7 +2686,6 @@
}
return True;
=20
-
case 0x295: // stswx (Store String Word Indexed, PPC32 p529)
DIP("stswx r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
t_nbytes =3D newTemp(Ity_I32);
@@ -3083,14 +3072,10 @@
UChar b0 =3D toUChar((theInstr >> 0) & 1); /* theInstr[0]=
*/
=20
IRTemp EA =3D newTemp(Ity_I32);
- IRTemp Ra =3D newTemp(Ity_I32);
- IRTemp Rb =3D newTemp(Ity_I32);
IRTemp Rs =3D newTemp(Ity_I32);
-//uu IRTemp xer_so =3D newTemp(Ity_I32);
-//uu IRTemp cr_f7 =3D newTemp(Ity_I32);
=20
switch (opc1) {
- /* XL-Form */
+ /* XL-Form */
case 0x13: // isync (Instruction Synchronize, PPC32 p432)
if (opc2 !=3D 0x096) {
vex_printf("dis_int_memsync(PPC32)(0x13,opc2)\n");
@@ -3118,47 +3103,28 @@
break;
=20
case 0x014: // lwarx (Load Word and Reserve Indexed, PPC32 p458)
- /* Note: RESERVE, RESERVE_ADDR not implemented.
- stwcx. is assumed to be always successful
- */
if (b0 !=3D 0) {
vex_printf("dis_int_memsync(PPC32)(lwarx,b0)\n");
return False;
}
DIP("lwarx r%d,r%d,r%d\n", Rd_addr, Ra_addr, Rb_addr);
- assign( Rb, getIReg(Rb_addr) );
- if (Ra_addr =3D=3D 0) {
- assign( EA, mkexpr(Rb) );
- } else {
- assign( Ra, getIReg(Ra_addr) );
- assign( EA, binop(Iop_Add32, mkexpr(Ra), mkexpr(Rb)) );
- }
+ assign( EA, ea_standard(Ra_addr, Rb_addr) );
putIReg( Rd_addr, loadBE(Ity_I32, mkexpr(EA)) );
/* Take a reservation */
stmt( IRStmt_Put( OFFB_RESVN, mkexpr(EA) ));
-// stmt( IRStmt_Put( OFFB_RESVN, mkU32(1) ));
break;
=20
case 0x096: {=20
// stwcx. (Store Word Conditional Indexed, PPC32 p532)
- /* Note: RESERVE, RESERVE_ADDR not implemented.
- stwcx. is assumed to be always successful
- */
IRTemp resaddr =3D newTemp(Ity_I32);
if (b0 !=3D 1) {
vex_printf("dis_int_memsync(PPC32)(stwcx.,b0)\n");
return False;
}
DIP("stwcx. r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
- =20
- assign( Rb, getIReg(Rb_addr) );
assign( Rs, getIReg(Rs_addr) );
- if (Ra_addr =3D=3D 0) {
- assign( EA, mkexpr(Rb) );
- } else {
- assign( Ra, getIReg(Ra_addr) );
- assign( EA, binop(Iop_Add32, mkexpr(Ra), mkexpr(Rb)) );
- }
+ assign( EA, ea_standard(Ra_addr, Rb_addr) );
+
/* First set up as if the reservation failed */
// Set CR0[LT GT EQ S0] =3D 0b000 || XER[SO]
putCR321(0, mkU8(0<<1));
@@ -3173,8 +3139,6 @@
stmt( IRStmt_Exit(
binop(Iop_CmpNE32, mkexpr(resaddr),
mkexpr(EA)),
- // binop(Iop_CmpEQ32, IRExpr_Get(OFFB_RESVN, Ity_I32),
- // mkU32(0)),
Ijk_Boring,
IRConst_U32(guest_CIA_curr_instr + 4)
)
@@ -3228,18 +3192,12 @@
UInt opc2 =3D (theInstr >> 1) & 0x3FF; /* theInstr[1:10]=
*/
UChar flag_Rc =3D toUChar((theInstr >> 0) & 1); /* theInstr[0] =
*/
=20
-//uu UInt flag_op =3D PPC32G_FLAG_OP_NUMBER;
- =20
IRTemp sh_amt =3D newTemp(Ity_I8);
-//uu IRTemp sign =3D newTemp(Ity_I32);
IRTemp rb_b5 =3D newTemp(Ity_I32);
-//uu IRTemp sext =3D newTemp(Ity_I32);
IRTemp Rs =3D newTemp(Ity_I32);
IRTemp Rs_sh =3D newTemp(Ity_I32);
-//uu IRTemp Rs_msk =3D newTemp(Ity_I32);
IRTemp Ra =3D newTemp(Ity_I32);
IRTemp Rb =3D newTemp(Ity_I32);
-//uu IRTemp mask =3D newTemp(Ity_I32);
IRTemp sh_amt32 =3D newTemp(Ity_I32);
IRTemp outofrange =3D newTemp(Ity_I8);
=20
@@ -3351,21 +3309,13 @@
/* X-Form */
UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
UChar Rd_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
-// UChar Rs_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21=
:25] */
+ UChar Rs_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
UChar Ra_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:2=
0] */
UChar Rb_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
UInt opc2 =3D (theInstr >> 1) & 0x3FF; /* theInstr[1:10=
] */
UChar b0 =3D toUChar((theInstr >> 0) & 1); /* theInstr[0] =
*/
=20
IRTemp EA =3D newTemp(Ity_I32);
-// IRTemp Rd =3D newTemp(Ity_I32);
-// IRTemp Rs =3D newTemp(Ity_I32);
-// IRTemp byte0 =3D newTemp(Ity_I32);
-// IRTemp byte1 =3D newTemp(Ity_I32);
-// IRTemp byte2 =3D newTemp(Ity_I32);
-// IRTemp byte3 =3D newTemp(Ity_I32);
-// IRTemp tmp16 =3D newTemp(Ity_I16);
-// IRTemp tmp32 =3D newTemp(Ity_I32);
IRTemp w1 =3D newTemp(Ity_I32);
IRTemp w2 =3D newTemp(Ity_I32);
=20
@@ -3373,13 +3323,9 @@
vex_printf("dis_int_ldst_rev(PPC32)(opc1|b0)\n");
return False;
}
+
+ assign( EA, ea_standard(Ra_addr, Rb_addr) );
=20
- if (Ra_addr =3D=3D 0) {
- assign( EA, getIReg(Rb_addr));
- } else {
- assign( EA, binop(Iop_Add32, getIReg(Ra_addr), getIReg(Rb_addr)) )=
;
- }
- =20
switch (opc2) {
//zz case 0x316: // lhbrx (Load Half Word Byte-Reverse Indexed, PPC32=
p449)
//zz vassert(0);
@@ -3417,8 +3363,8 @@
//zz break;
=20
case 0x296: // stwbrx (Store Word Byte-Reverse Indexed, PPC32 p531=
)
- DIP("stwbrx r%d,r%d,r%d\n", Rd_addr, Ra_addr, Rb_addr);
- assign( w1, getIReg(Rd_addr) );
+ DIP("stwbrx r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ assign( w1, getIReg(Rs_addr) );
storeBE( mkexpr(EA), gen_byterev32(w1) );
break;
=20
@@ -3871,7 +3817,7 @@
=20
assign( rA, getIReg(rA_addr) );
assign( rB, getIReg(rB_addr) );
- assign( rA_or_0, (rA_addr =3D=3D 0) ? mkU32(0) : mkexpr(rA) );
+ assign( rA_or_0, ea_rA_or_zero(rA_addr) );
=20
switch(opc1) {
case 0x30: // lfs (Load Float Single, PPC32 p441)
@@ -3992,7 +3938,7 @@
assign( frS, getFReg(frS_addr) );
assign( rA, getIReg(rA_addr) );
assign( rB, getIReg(rB_addr) );
- assign( rA_or_0, (rA_addr =3D=3D 0) ? mkU32(0) : mkexpr(rA) );
+ assign( rA_or_0, ea_rA_or_zero(rA_addr) );
=20
switch(opc1) {
=20
@@ -4873,9 +4819,7 @@
return False;
}
=20
- assign( EA, binop(Iop_Add32,
- ((rA_addr =3D=3D 0) ? mkU32(0) : getIReg(rA_addr)),
- getIReg(rB_addr) ));
+ assign( EA, ea_standard(rA_addr, rB_addr) );
=20
switch (opc2) {
=20
@@ -4945,11 +4889,7 @@
assign( rB, getIReg(rB_addr));
assign( vS, getVReg(vS_addr));
=20
- if (rA_addr =3D=3D 0) {
- assign( EA, mkexpr(rB) );
- } else {
- assign( EA, binop(Iop_Add32, mkexpr(rA), mkexpr(rB)) );
- }
+ assign( EA, ea_standard(rA_addr, rB_addr) );
=20
if (opc1 !=3D 0x1F || b0 !=3D 0) {
vex_printf("dis_av_store(PPC32)(instr)\n");
|
|
From: <sv...@va...> - 2005-09-09 09:50:37
|
Author: sewardj
Date: 2005-09-09 10:50:34 +0100 (Fri, 09 Sep 2005)
New Revision: 1377
Log:
rm unused vars in dis_int_ldst_str
Modified:
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-09 09:35:29 UTC (rev 1376)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-09 09:50:34 UTC (rev 1377)
@@ -2626,17 +2626,8 @@
UInt opc2 =3D (theInstr >> 1) & 0x3FF; /* theInstr[1:10=
] */
UChar b0 =3D toUChar((theInstr >> 0) & 1); /* theInstr[0] =
*/
=20
- UInt reg_idx, bit_idx, n_byte;
- UInt EA_offset =3D 0;
- UInt n_regs, reg_first, reg_last;
- =20
- IRTemp Ra =3D newTemp(Ity_I32);
-// IRTemp Rb =3D newTemp(Ity_I32);
- IRTemp EA =3D newTemp(Ity_I32);
- IRTemp t_EA =3D newTemp(Ity_I32);
+ IRTemp t_EA =3D newTemp(Ity_I32);
IRTemp t_nbytes =3D IRTemp_INVALID;
- IRExpr* irx_byte;
- IRExpr* irx_shl;
=20
*stopHere =3D False;
=20
|
|
From: <sv...@va...> - 2005-09-09 09:35:35
|
Author: sewardj
Date: 2005-09-09 10:35:29 +0100 (Fri, 09 Sep 2005)
New Revision: 1376
Log:
Implement stswi/stswx.
Modified:
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-09 08:33:03 UTC (rev 1375)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-09 09:35:29 UTC (rev 1376)
@@ -2547,6 +2547,7 @@
IRExpr* e_nbytes =3D mkexpr(tNBytes);
IRExpr* e_EA =3D mkexpr(EA);
=20
+ vassert(rD >=3D 0 && rD < 32);
rD--; if (rD < 0) rD =3D 31;
=20
for (i =3D 0; i < maxBytes; i++) {
@@ -2577,7 +2578,42 @@
}
}
=20
+static=20
+void generate_stsw_sequence ( IRTemp tNBytes, // # bytes, :: Ity_I32
+ IRTemp EA, // EA
+ Int rS, // first src register
+ Int maxBytes, // 32 or 128
+ Addr32 NIA ) // where next?
+{
+ Int i, shift =3D 24;
+ IRExpr* e_nbytes =3D mkexpr(tNBytes);
+ IRExpr* e_EA =3D mkexpr(EA);
=20
+ vassert(rS >=3D 0 && rS < 32);
+ rS--; if (rS < 0) rS =3D 31;
+
+ for (i =3D 0; i < maxBytes; i++) {
+ /* if (nBytes < (i+1)) goto NIA; */
+ stmt( IRStmt_Exit( binop(Iop_CmpLT32U, e_nbytes, mkU32(i+1)),
+ Ijk_Boring,=20
+ IRConst_U32(NIA)) );
+ /* check for crossing into a new src register. */
+ if ((i % 4) =3D=3D 0) {
+ rS++; if (rS =3D=3D 32) rS =3D 0;
+ shift =3D 24;
+ }
+ /* *(EA+i) =3D 32to8(rS >> shift) */
+ vassert(shift =3D=3D 0 || shift =3D=3D 8 || shift =3D=3D 16 || shi=
ft =3D=3D 24);
+ storeBE(
+ binop(Iop_Add32, e_EA, mkU32(i)),
+ unop(Iop_32to8,
+ binop(Iop_Shr32, getIReg(rS), mkU8(shift)))
+ );
+ shift -=3D 8;
+ }
+}
+
+
static Bool dis_int_ldst_str ( UInt theInstr, /*OUT*/Bool* stopHere )
{
/* X-Form */
@@ -2620,7 +2656,6 @@
/* Rd =3D Mem[EA]; (Rd+1)%32 =3D Mem[EA+4] */
putIReg( Rd_addr, =20
loadBE(Ity_I32, mkexpr(t_EA)) );
-
putIReg( (Rd_addr+1) % 32,=20
loadBE(Ity_I32, binop(Iop_Add32, mkexpr(t_EA), mkU32(4=
))) );
} else {
@@ -2651,92 +2686,37 @@
*stopHere =3D True;
return True;
=20
-//zz case 0x2D5: // stswi (Store String Word Immediate, PPC32 p528)
-//zz=20
-//zz if (NumBytes =3D=3D 8) {
-//zz /* Special case hack */
-//zz /* Mem[EA] =3D Rd; Mem[EA+4] =3D (Rd+1)%32 */
-//zz DIP("stswi r%d,r%d,%d\n", Rs_addr, Ra_addr, NumBytes);
-//zz storeBE( mkexpr(b_EA),=20
-//zz getIReg(Rd_addr) );
-//zz storeBE( binop(Iop_Add32, mkexpr(b_EA), mkU32(4)),=20
-//zz getIReg((Rd_addr+1) % 32) );
-//zz return True;
-//zz }
-//zz=20
-//zz /* else too difficult */
-//zz return False;
-//zz=20
-//zz vassert(0);
-//zz=20
-//zz DIP("stswi r%d,r%d,%d\n", Rs_addr, Ra_addr, NumBytes);
-//zz if (Ra_addr =3D=3D 0) {
-//zz assign( EA, mkU32(0) );
-//zz } else {
-//zz assign( EA, mkexpr(b_EA) );
-//zz }
-//zz =20
-//zz n_byte =3D NumBytes;
-//zz if (n_byte =3D=3D 0) { n_byte =3D 32; }
-//zz reg_idx =3D Rs_addr - 1;
-//zz bit_idx =3D 0;
-//zz =20
-//zz for (; n_byte>0; n_byte--) {
-//zz if (bit_idx =3D=3D 0) {
-//zz reg_idx++;
-//zz if (reg_idx=3D=3D32) reg_idx =3D 0;
-//zz }
-//zz irx_byte =3D unop(Iop_32to8,
-//zz binop(Iop_Shr32,
-//zz getIReg(reg_idx),=20
-//zz mkU8(toUChar(24 - bit_idx))));
-//zz storeBE( binop(Iop_Add32, mkexpr(EA), mkU32(EA_offset)),
-//zz irx_byte );
-//zz =20
-//zz bit_idx +=3D 8;
-//zz if (bit_idx =3D=3D 32) { bit_idx =3D 0; }
-//zz EA_offset++;
-//zz }
-//zz break;
-//zz=20
-//zz case 0x295: // stswx (Store String Word Indexed, PPC32 p529)
-//zz vassert(0);
-//zz=20
-//zz DIP("stswx r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
-//zz return False;
-//zz #if 0
-//zz // CAB: Might something like this work ?
-//zz // won't produce very nice code (ir_ctr will get _rather_ long...),=
but hey.
-//zz // or perhaps arrays of IRTemp...
-//zz assign( NumBytes, AND(get(xer_bc), 0x1F) );
-//zz IRExpr* irx_ea;
-//zz IRExpr* irx_orig_byte;
-//zz IRExpr* irx_tostore;
-//zz IRExpr* ir_ctr =3D mkU8(0);
-//zz Uint EA_offset =3D 0;
-//zz UInt start =3D Rs_addr;
-//zz UInt reg_idx;
-//zz UInt i;
-//zz for (i=3D0; i<128; i++) {
-//zz bit_idx =3D (i % 4) * 8;
-//zz reg_idx =3D (i / 4) + start;
-//zz reg_idx =3D reg_idx % 32;
-//zz word =3D getIReg(reg_idx);
-//zz byte =3D get_byte(word, bit_idx);
-//zz =20
-//zz irx_ea =3D (EA + EA_offset);
-//zz irx_orig_byte =3D loadBE(Ity_I8, irx_ea);
-//zz irx_tostore =3D IRExpr_Mux0X( (ir_ctr <=3D NumBytes),
-//zz irx_orig_byte,
-//zz mkexpr(byte0) );
-//zz storeBE( irx_ea, irx_tostore );
-//zz =20
-//zz ir_ctr =3D binop(Iop_And8, ir_ctr, mkU8(1));
-//zz EA_offset++;
-//zz }
-//zz break;
-//zz #endif
+ case 0x2D5: // stswi (Store String Word Immediate, PPC32 p528)
+ DIP("stswi r%d,r%d,%d\n", Rs_addr, Ra_addr, NumBytes);
+ assign( t_EA, ea_rA_or_zero(Ra_addr) );
+ if (NumBytes =3D=3D 8) {
+ /* Special case hack */
+ /* Mem[EA] =3D Rd; Mem[EA+4] =3D (Rd+1)%32 */
+ storeBE( mkexpr(t_EA),=20
+ getIReg(Rd_addr) );
+ storeBE( binop(Iop_Add32, mkexpr(t_EA), mkU32(4)),=20
+ getIReg((Rd_addr+1) % 32) );
+ } else {
+ t_nbytes =3D newTemp(Ity_I32);
+ assign( t_nbytes, mkU32(NumBytes=3D=3D0 ? 32 : NumBytes) );
+ generate_stsw_sequence( t_nbytes, t_EA, Rd_addr,=20
+ 32, guest_CIA_curr_instr+4 );
+ *stopHere =3D True;
+ }
+ return True;
=20
+
+ case 0x295: // stswx (Store String Word Indexed, PPC32 p529)
+ DIP("stswx r%d,r%d,r%d\n", Rs_addr, Ra_addr, Rb_addr);
+ t_nbytes =3D newTemp(Ity_I32);
+ assign( t_EA, ea_standard(Ra_addr,Rb_addr) );
+ assign( t_nbytes, unop( Iop_8Uto32,=20
+ IRExpr_Get( OFFB_XER_BC, Ity_I8 )));
+ generate_stsw_sequence( t_nbytes, t_EA, Rs_addr,=20
+ 128, guest_CIA_curr_instr+4 );
+ *stopHere =3D True;
+ return True;
+
default:
vex_printf("dis_int_ldst_str(PPC32)(opc2)\n");
return False;
|
|
From: Julian S. <js...@ac...> - 2005-09-09 08:39:24
|
> On Friday 09 September 2005 09:33, sv...@va... wrote:
> Author: sewardj
> Date: 2005-09-09 09:33:03 +0100 (Fri, 09 Sep 2005)
> New Revision: 1375
>
> Log:
> Enhance the dead-code removal pass so that it detects unconditional
> side exits and deletes all code after them. This helps clean up the
> IR created by {l,st}sw{i,x} from the ppc32 front end. It's also a
> general transformation which ought to have been implemented long ago.
Folks -- note -- this is an IR optimiser change which affects all
targets. As far as I know it should not have any discernable
effect on correctness of the simulation, but ...
so be aware of possible strangeness after you svn up.
J
|
|
From: <sv...@va...> - 2005-09-09 08:33:06
|
Author: sewardj
Date: 2005-09-09 09:33:03 +0100 (Fri, 09 Sep 2005)
New Revision: 1375
Log:
Enhance the dead-code removal pass so that it detects unconditional
side exits and deletes all code after them. This helps clean up the
IR created by {l,st}sw{i,x} from the ppc32 front end. It's also a
general transformation which ought to have been implemented long ago.
Modified:
trunk/priv/ir/iropt.c
Modified: trunk/priv/ir/iropt.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/iropt.c 2005-09-09 08:31:18 UTC (rev 1374)
+++ trunk/priv/ir/iropt.c 2005-09-09 08:33:03 UTC (rev 1375)
@@ -1648,9 +1648,10 @@
return IRStmt_NoOp();
} else {
vassert(fcond->Iex.Const.con->Ico.U1 =3D=3D True);
- /* Hmmm. The exit has become unconditional. Leave it as
- it is for now, since we'd have to truncate the BB at
- this point, which is tricky. */
+ /* Hmmm. The exit has become unconditional. Leave it
+ as it is for now, since we'd have to truncate the BB
+ at this point, which is tricky. Such truncation is
+ done later by the dead-code elimination pass. */
/* fall out into the reconstruct-the-exit code. */
if (vex_control.iropt_verbosity > 0)=20
/* really a misuse of vex_control.iropt_verbosity */
@@ -1737,11 +1738,13 @@
}
=20
=20
-
/*---------------------------------------------------------------*/
/*--- Dead code (t =3D E) removal ---*/
/*---------------------------------------------------------------*/
=20
+/* As a side effect, also removes all code following an unconditional
+ side exit. */
+
/* The type of the HashHW map is: a map from IRTemp to nothing
-- really just operating a set or IRTemps.
*/
@@ -1844,17 +1847,32 @@
&& e->Iex.Const.con->Ico.U1 =3D=3D False );
}
=20
+/* Is this literally IRExpr_Const(IRConst_U1(True)) ? */
+static Bool isOneU1 ( IRExpr* e )
+{
+ return toBool( e->tag =3D=3D Iex_Const
+ && e->Iex.Const.con->tag =3D=3D Ico_U1
+ && e->Iex.Const.con->Ico.U1 =3D=3D True );
+}
=20
+
/* Note, this destructively modifies the given IRBB. */
=20
/* Scan backwards through statements, carrying a set of IRTemps which
are known to be used after the current point. On encountering 't =3D
E', delete the binding if it is not used. Otherwise, add any temp
- uses to the set and keep on moving backwards. */
+ uses to the set and keep on moving backwards.
=20
+ As an enhancement, the first (backwards) pass searches for IR exits
+ with always-taken conditions and notes the location of the earliest
+ one in the block. If any such are found, a second pass copies the
+ exit destination and jump kind to the bb-end. Then, the exit and
+ all statements following it are turned into no-ops.
+*/
+
/* notstatic */ void do_deadcode_BB ( IRBB* bb )
{
- Int i;
+ Int i, i_unconditional_exit;
Int n_tmps =3D bb->tyenv->types_used;
Bool* set =3D LibVEX_Alloc(n_tmps * sizeof(Bool));
IRStmt* st;
@@ -1865,11 +1883,18 @@
/* start off by recording IRTemp uses in the next field. */
addUses_Expr(set, bb->next);
=20
+ /* First pass */
+
/* Work backwards through the stmts */
+ i_unconditional_exit =3D -1;
for (i =3D bb->stmts_used-1; i >=3D 0; i--) {
st =3D bb->stmts[i];
if (st->tag =3D=3D Ist_NoOp)
continue;
+ /* take note of any unconditional exits */
+ if (st->tag =3D=3D Ist_Exit
+ && isOneU1(st->Ist.Exit.guard))
+ i_unconditional_exit =3D i;
if (st->tag =3D=3D Ist_Tmp
&& set[(Int)(st->Ist.Tmp.tmp)] =3D=3D False) {
/* it's an IRTemp which never got used. Delete it. */
@@ -1893,8 +1918,25 @@
addUses_Stmt(set, st);
}
}
+
+ /* Optional second pass: if any unconditional exits were found,=20
+ delete them and all following statements. */
+
+ if (i_unconditional_exit !=3D -1) {
+ if (0) vex_printf("ZAPPING ALL FORWARDS from %d\n",=20
+ i_unconditional_exit);
+ vassert(i_unconditional_exit >=3D 0=20
+ && i_unconditional_exit < bb->stmts_used);
+ bb->next=20
+ =3D IRExpr_Const( bb->stmts[i_unconditional_exit]->Ist.Exit.dst=
);
+ bb->jumpkind
+ =3D bb->stmts[i_unconditional_exit]->Ist.Exit.jk;
+ for (i =3D i_unconditional_exit; i < bb->stmts_used; i++)
+ bb->stmts[i] =3D IRStmt_NoOp();
+ }
}
=20
+
/*---------------------------------------------------------------*/
/*--- Specialisation of helper function calls, in ---*/
/*--- collaboration with the front end ---*/
|
|
From: <sv...@va...> - 2005-09-09 08:31:24
|
Author: sewardj
Date: 2005-09-09 09:31:18 +0100 (Fri, 09 Sep 2005)
New Revision: 1374
Log:
Implement lswi and lswx. The generated IR should be good for
instrumentation by memcheck and does not reference any memory it
should not. Unfortunately the IR is long and inefficient.
Modified:
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-08 17:53:03 UTC (rev 1373)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-09 08:31:18 UTC (rev 1374)
@@ -46,12 +46,18 @@
=20
/* TODO 2005 07 15:
=20
- Get rid of all vestiges of flag helper fns.
-
Spot rlwini cases which are simply left/right shifts and
emit Shl32/Shr32 accordingly.
=20
Move mtxer/mfxer code into its own function.
+
+ LIMITATIONS:
+
+ Various, including:
+
+ - Some invalid forms of lswi and lswx are accepted when they should
+ not be.
+
*/
=20
=20
@@ -692,7 +698,30 @@
);
}
=20
+/* Do the standard effective address calculation: (rA|0) + rB. */
+static IRExpr* /* :: Ity_I32 */ ea_standard ( Int rA, Int rB )
+{
+ vassert(rA >=3D 0 && rA < 32);
+ vassert(rB >=3D 0 && rB < 32);
+ if (rA =3D=3D 0) {
+ return getIReg(rB);
+ } else {
+ return binop(Iop_Add32, getIReg(rA), getIReg(rB));
+ }
+}
=20
+/* Do the effective address calculation: (rA|0). */
+static IRExpr* /* :: Ity_I32 */ ea_rA_or_zero ( Int rA )
+{
+ vassert(rA >=3D 0 && rA < 32);
+ if (rA =3D=3D 0) {
+ return mkU32(0);
+ } else {
+ return getIReg(rA);
+ }
+}
+
+
/*------------------------------------------------------------*/
/*--- Helpers for condition codes. ---*/
/*------------------------------------------------------------*/
@@ -2504,111 +2533,124 @@
=20
=20
=20
-//zz /*
-//zz Integer Load/Store String Instructions
-//zz */
-//zz static Bool dis_int_ldst_str ( UInt theInstr )
-//zz {
-//zz /* X-Form */
-//zz UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr=
[26:31] */
-//zz UChar Rd_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr=
[21:25] */
-//zz UChar Rs_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr=
[21:25] */
-//zz UChar Ra_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr=
[16:20] */
-//zz UChar NumBytes =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr=
[11:15] */
-//zz UChar Rb_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr=
[11:15] */
-//zz UInt opc2 =3D (theInstr >> 1) & 0x3FF; /* theInstr=
[1:10] */
-//zz UChar b0 =3D toUChar((theInstr >> 0) & 1); /* theInstr=
[0] */
-//zz =20
-//zz UInt reg_idx, bit_idx, n_byte;
-//zz UInt EA_offset =3D 0;
-//zz UInt n_regs, reg_first, reg_last;
-//zz =20
-//zz IRTemp Ra =3D newTemp(Ity_I32);
-//zz // IRTemp Rb =3D newTemp(Ity_I32);
-//zz IRTemp EA =3D newTemp(Ity_I32);
-//zz IRTemp b_EA =3D newTemp(Ity_I32);
-//zz IRExpr* irx_byte;
-//zz IRExpr* irx_shl;
-//zz =20
-//zz if (Ra_addr =3D=3D 0) {
-//zz assign( b_EA, mkU32(0) );
-//zz } else {
-//zz assign( Ra, getIReg(Ra_addr) );
-//zz assign( b_EA, mkexpr(Ra) );
-//zz } =20
-//zz =20
-//zz if (opc1 !=3D 0x1F || b0 !=3D 0) {
-//zz vex_printf("dis_int_ldst_str(PPC32)(opc1)\n");
-//zz return False;
-//zz }
-//zz=20
-//zz switch (opc2) {
-//zz case 0x255: // lswi (Load String Word Immediate, PPC32 p455)
-//zz=20
-//zz if (NumBytes =3D=3D 8) {
-//zz /* Special case hack */
-//zz /* Rd =3D Mem[EA]; (Rd+1)%32 =3D Mem[EA+4] */
-//zz DIP("lswi r%d,r%d,%d\n", Rd_addr, Ra_addr, NumBytes);
-//zz putIReg( Rd_addr, =20
-//zz loadBE(Ity_I32, mkexpr(b_EA)) );
-//zz=20
-//zz putIReg( (Rd_addr+1) % 32,=20
-//zz loadBE(Ity_I32, binop(Iop_Add32, mkexpr(b_EA), mk=
U32(4))) );
-//zz return True;
-//zz }
-//zz=20
-//zz /* else too difficult */
-//zz return False;
-//zz vassert(0);
-//zz=20
-//zz n_regs =3D (NumBytes / 4) + (NumBytes%4 =3D=3D 0 ? 0:1); // c=
eil(nb/4)
-//zz reg_first =3D Rd_addr;
-//zz reg_last =3D Rd_addr + n_regs - 1;
-//zz =20
-//zz if (reg_last < reg_first) {
-//zz if (Ra_addr >=3D reg_first || Ra_addr <=3D reg_last) {
-//zz vex_printf("dis_int_ldst_str(PPC32)(lswi,Ra_addr,1)\n")=
;
-//zz return False;
-//zz }
-//zz } else {
-//zz if (Ra_addr >=3D reg_first && Ra_addr <=3D reg_last) {
-//zz vex_printf("dis_int_ldst_str(PPC32)(lswi,Ra_addr,2)\n")=
;
-//zz return False;
-//zz }
-//zz }
-//zz DIP("lswi r%d,r%d,%d\n", Rd_addr, Ra_addr, NumBytes);
-//zz =20
-//zz assign( EA, mkexpr(b_EA) );
-//zz =20
-//zz bit_idx =3D 0;
-//zz reg_idx =3D Rd_addr - 1;
-//zz n_byte =3D NumBytes;
-//zz if (n_byte =3D=3D 0) { n_byte =3D 32; }
-//zz =20
-//zz for (; n_byte>0; n_byte--) {
-//zz if (bit_idx =3D=3D 0) {
-//zz reg_idx++;
-//zz if (reg_idx =3D=3D 32) reg_idx =3D 0;
-//zz putIReg( reg_idx, mkU32(0) );
-//zz }
-//zz irx_byte =3D loadBE(Ity_I8, binop(Iop_Add32,
-//zz mkexpr(EA),
-//zz mkU32(EA_offset)));
-//zz irx_shl =3D binop(Iop_Shl32, irx_byte,=20
-//zz mkU8(toUChar(24 - bit_idx)));
-//zz putIReg( reg_idx, binop(Iop_Or32, getIReg(reg_idx), irx_sh=
l) );
-//zz bit_idx +=3D 8;
-//zz if (bit_idx =3D=3D 32) { bit_idx =3D 0; }
-//zz EA_offset++;
-//zz }
-//zz break; =20
-//zz=20
-//zz case 0x215: // lswx (Load String Word Indexed, PPC32 p456)
-//zz vassert(0);
-//zz=20
-//zz DIP("lswx r%d,r%d,r%d\n", Rd_addr, Ra_addr, Rb_addr);
-//zz return False;
-//zz=20
+/*
+ Integer Load/Store String Instructions
+*/
+static=20
+void generate_lsw_sequence ( IRTemp tNBytes, // # bytes, :: Ity_I32
+ IRTemp EA, // EA
+ Int rD, // first dst register
+ Int maxBytes, // 32 or 128
+ Addr32 NIA ) // where next?
+{
+ Int i, shift =3D 24;
+ IRExpr* e_nbytes =3D mkexpr(tNBytes);
+ IRExpr* e_EA =3D mkexpr(EA);
+
+ rD--; if (rD < 0) rD =3D 31;
+
+ for (i =3D 0; i < maxBytes; i++) {
+
+ /* if (nBytes < (i+1)) goto NIA; */
+ stmt( IRStmt_Exit( binop(Iop_CmpLT32U, e_nbytes, mkU32(i+1)),
+ Ijk_Boring,=20
+ IRConst_U32(NIA)) );
+ /* when crossing into a new dest register, set it to zero. */
+ if ((i % 4) =3D=3D 0) {
+ rD++; if (rD =3D=3D 32) rD =3D 0;
+ putIReg(rD, mkU32(0));
+ shift =3D 24;
+ }
+ /* rD |=3D (8Uto32(*(EA+i))) << shift */
+ vassert(shift =3D=3D 0 || shift =3D=3D 8 || shift =3D=3D 16 || shi=
ft =3D=3D 24);
+ putIReg(
+ rD,=20
+ binop(Iop_Or32,=20
+ getIReg(rD),
+ binop(Iop_Shl32,=20
+ unop(Iop_8Uto32,=20
+ loadBE(Ity_I8,=20
+ binop(Iop_Add32, e_EA, mkU32(i)))),=20
+ mkU8(shift))=20
+ ));
+ shift -=3D 8;
+ }
+}
+
+
+static Bool dis_int_ldst_str ( UInt theInstr, /*OUT*/Bool* stopHere )
+{
+ /* X-Form */
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
+ UChar Rd_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
+ UChar Rs_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
+ UChar Ra_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:2=
0] */
+ UChar NumBytes =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
+ UChar Rb_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
+ UInt opc2 =3D (theInstr >> 1) & 0x3FF; /* theInstr[1:10=
] */
+ UChar b0 =3D toUChar((theInstr >> 0) & 1); /* theInstr[0] =
*/
+ =20
+ UInt reg_idx, bit_idx, n_byte;
+ UInt EA_offset =3D 0;
+ UInt n_regs, reg_first, reg_last;
+ =20
+ IRTemp Ra =3D newTemp(Ity_I32);
+// IRTemp Rb =3D newTemp(Ity_I32);
+ IRTemp EA =3D newTemp(Ity_I32);
+ IRTemp t_EA =3D newTemp(Ity_I32);
+ IRTemp t_nbytes =3D IRTemp_INVALID;
+ IRExpr* irx_byte;
+ IRExpr* irx_shl;
+ =20
+ *stopHere =3D False;
+ =20
+ if (opc1 !=3D 0x1F || b0 !=3D 0) {
+ vex_printf("dis_int_ldst_str(PPC32)(opc1)\n");
+ return False;
+ }
+
+ switch (opc2) {
+ case 0x255: // lswi (Load String Word Immediate, PPC32 p455)
+ /* NB: does not reject the case where RA is in the range of
+ registers to be loaded. It should. */
+ DIP("lswi r%d,r%d,%d\n", Rd_addr, Ra_addr, NumBytes);
+ assign( t_EA, ea_rA_or_zero(Ra_addr) );
+ if (NumBytes =3D=3D 8) {
+ /* Special case hack */
+ /* Rd =3D Mem[EA]; (Rd+1)%32 =3D Mem[EA+4] */
+ putIReg( Rd_addr, =20
+ loadBE(Ity_I32, mkexpr(t_EA)) );
+
+ putIReg( (Rd_addr+1) % 32,=20
+ loadBE(Ity_I32, binop(Iop_Add32, mkexpr(t_EA), mkU32(4=
))) );
+ } else {
+ t_nbytes =3D newTemp(Ity_I32);
+ assign( t_nbytes, mkU32(NumBytes=3D=3D0 ? 32 : NumBytes) );
+ generate_lsw_sequence( t_nbytes, t_EA, Rd_addr,=20
+ 32, guest_CIA_curr_instr+4 );
+ *stopHere =3D True;
+ }
+ return True;
+
+ case 0x215: // lswx (Load String Word Indexed, PPC32 p456)
+ /* NB: does not reject the case where RA is in the range of
+ registers to be loaded. It should. Although considering
+ that that can only be detected at run time, it's not easy to
+ do so. */
+ if (Rd_addr =3D=3D Ra_addr || Rd_addr =3D=3D Rb_addr)
+ return False;
+ if (Rd_addr =3D=3D 0 && Ra_addr =3D=3D 0)
+ return False;
+ DIP("lswx r%d,r%d,r%d\n", Rd_addr, Ra_addr, Rb_addr);
+ t_nbytes =3D newTemp(Ity_I32);
+ assign( t_EA, ea_standard(Ra_addr,Rb_addr) );
+ assign( t_nbytes, unop( Iop_8Uto32,=20
+ IRExpr_Get( OFFB_XER_BC, Ity_I8 )));
+ generate_lsw_sequence( t_nbytes, t_EA, Rd_addr,=20
+ 128, guest_CIA_curr_instr+4 );
+ *stopHere =3D True;
+ return True;
+
//zz case 0x2D5: // stswi (Store String Word Immediate, PPC32 p528)
//zz=20
//zz if (NumBytes =3D=3D 8) {
@@ -2694,16 +2736,15 @@
//zz }
//zz break;
//zz #endif
-//zz=20
-//zz default:
-//zz vex_printf("dis_int_ldst_str(PPC32)(opc2)\n");
-//zz return False;
-//zz }
-//zz return True;
-//zz }
-//zz=20
-//zz=20
=20
+ default:
+ vex_printf("dis_int_ldst_str(PPC32)(opc2)\n");
+ return False;
+ }
+ return True;
+}
+
+
/* ------------------------------------------------------------------
Integer Branch Instructions
------------------------------------------------------------------ */
@@ -6353,11 +6394,19 @@
if (dis_int_ldst_rev( theInstr )) goto decode_success;
goto decode_failure;
=20
-//zz /* Integer Load and Store String Instructions */
-//zz case 0x255: case 0x215: case 0x2D5: // lswi, lswx, stswi
-//zz case 0x295: // stswx
-//zz if (dis_int_ldst_str( theInstr )) goto decode_success;
-//zz goto decode_failure;
+ /* Integer Load and Store String Instructions */
+ case 0x255: case 0x215: case 0x2D5: // lswi, lswx, stswi
+ case 0x295: { // stswx
+ Bool stopHere =3D False;
+ Bool ok =3D dis_int_ldst_str( theInstr, &stopHere );
+ if (!ok) goto decode_failure;
+ if (stopHere) {
+ irbb->next =3D mkU32(guest_CIA_curr_instr+4);
+ irbb->jumpkind =3D Ijk_Boring;
+ dres.whatNext =3D Dis_StopHere;
+ }
+ goto decode_success;
+ }
=20
/* Memory Synchronization Instructions */
case 0x356: case 0x014: case 0x096: // eieio, lwarx, stwcx.
|
|
From: Tom H. <th...@cy...> - 2005-09-09 03:06:55
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2005-09-09 03:00:03 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 164 tests, 7 stderr failures, 1 stdout failure ================= memcheck/tests/sigprocmask (stderr) memcheck/tests/strchr (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_fcntl (stderr) none/tests/tls (stdout) |
|
From: <js...@ac...> - 2005-09-09 02:58:14
|
Nightly build on phoenix ( SuSE 9.1 ) started at 2005-09-09 03:30:00 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 185 tests, 2 stderr failures, 0 stdout failures ================= none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: <js...@ac...> - 2005-09-09 02:44:48
|
Nightly build on g5 ( YDL 4.0, ppc970 ) started at 2005-09-09 04:40:00 CEST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 158 tests, 18 stderr failures, 1 stdout failure ================= memcheck/tests/badjump (stderr) memcheck/tests/badjump2 (stderr) memcheck/tests/fprw (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigaltstack (stderr) memcheck/tests/supp1 (stderr) memcheck/tests/supp_unknown (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) cachegrind/tests/chdir (stderr) cachegrind/tests/dlclose (stdout) cachegrind/tests/dlclose (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/fdleak_ipv4 (stderr) |
|
From: Tom H. <to...@co...> - 2005-09-09 02:41:07
|
Nightly build on dunsmere ( athlon, Fedora Core 4 ) started at 2005-09-09 03:30:04 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 187 tests, 5 stderr failures, 0 stdout failures ================= memcheck/tests/leak-tree (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-09 02:28:04
|
Nightly build on alvis ( i686, Red Hat 7.3 ) started at 2005-09-09 03:15:03 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 186 tests, 14 stderr failures, 1 stdout failure ================= memcheck/tests/addressable (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/erringfds (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigkill (stderr) memcheck/tests/stack_changes (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) none/tests/x86/yield (stdout) |
|
From: Tom H. <th...@cy...> - 2005-09-09 02:25:38
|
Nightly build on ginetta ( i686, Red Hat 8.0 ) started at 2005-09-09 03:10:11 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 186 tests, 2 stderr failures, 0 stdout failures ================= none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-09 02:21:16
|
Nightly build on dellow ( x86_64, Fedora Core 4 ) started at 2005-09-09 03:10:11 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 164 tests, 6 stderr failures, 0 stdout failures ================= memcheck/tests/sigprocmask (stderr) memcheck/tests/strchr (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-09 02:19:37
|
Nightly build on aston ( x86_64, Fedora Core 3 ) started at 2005-09-09 03:05:11 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 164 tests, 6 stderr failures, 0 stdout failures ================= memcheck/tests/sigprocmask (stderr) memcheck/tests/strchr (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) |