You can subscribe to this list here.
| 2002 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
(1) |
Oct
(122) |
Nov
(152) |
Dec
(69) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2003 |
Jan
(6) |
Feb
(25) |
Mar
(73) |
Apr
(82) |
May
(24) |
Jun
(25) |
Jul
(10) |
Aug
(11) |
Sep
(10) |
Oct
(54) |
Nov
(203) |
Dec
(182) |
| 2004 |
Jan
(307) |
Feb
(305) |
Mar
(430) |
Apr
(312) |
May
(187) |
Jun
(342) |
Jul
(487) |
Aug
(637) |
Sep
(336) |
Oct
(373) |
Nov
(441) |
Dec
(210) |
| 2005 |
Jan
(385) |
Feb
(480) |
Mar
(636) |
Apr
(544) |
May
(679) |
Jun
(625) |
Jul
(810) |
Aug
(838) |
Sep
(634) |
Oct
(521) |
Nov
(965) |
Dec
(543) |
| 2006 |
Jan
(494) |
Feb
(431) |
Mar
(546) |
Apr
(411) |
May
(406) |
Jun
(322) |
Jul
(256) |
Aug
(401) |
Sep
(345) |
Oct
(542) |
Nov
(308) |
Dec
(481) |
| 2007 |
Jan
(427) |
Feb
(326) |
Mar
(367) |
Apr
(255) |
May
(244) |
Jun
(204) |
Jul
(223) |
Aug
(231) |
Sep
(354) |
Oct
(374) |
Nov
(497) |
Dec
(362) |
| 2008 |
Jan
(322) |
Feb
(482) |
Mar
(658) |
Apr
(422) |
May
(476) |
Jun
(396) |
Jul
(455) |
Aug
(267) |
Sep
(280) |
Oct
(253) |
Nov
(232) |
Dec
(304) |
| 2009 |
Jan
(486) |
Feb
(470) |
Mar
(458) |
Apr
(423) |
May
(696) |
Jun
(461) |
Jul
(551) |
Aug
(575) |
Sep
(134) |
Oct
(110) |
Nov
(157) |
Dec
(102) |
| 2010 |
Jan
(226) |
Feb
(86) |
Mar
(147) |
Apr
(117) |
May
(107) |
Jun
(203) |
Jul
(193) |
Aug
(238) |
Sep
(300) |
Oct
(246) |
Nov
(23) |
Dec
(75) |
| 2011 |
Jan
(133) |
Feb
(195) |
Mar
(315) |
Apr
(200) |
May
(267) |
Jun
(293) |
Jul
(353) |
Aug
(237) |
Sep
(278) |
Oct
(611) |
Nov
(274) |
Dec
(260) |
| 2012 |
Jan
(303) |
Feb
(391) |
Mar
(417) |
Apr
(441) |
May
(488) |
Jun
(655) |
Jul
(590) |
Aug
(610) |
Sep
(526) |
Oct
(478) |
Nov
(359) |
Dec
(372) |
| 2013 |
Jan
(467) |
Feb
(226) |
Mar
(391) |
Apr
(281) |
May
(299) |
Jun
(252) |
Jul
(311) |
Aug
(352) |
Sep
(481) |
Oct
(571) |
Nov
(222) |
Dec
(231) |
| 2014 |
Jan
(185) |
Feb
(329) |
Mar
(245) |
Apr
(238) |
May
(281) |
Jun
(399) |
Jul
(382) |
Aug
(500) |
Sep
(579) |
Oct
(435) |
Nov
(487) |
Dec
(256) |
| 2015 |
Jan
(338) |
Feb
(357) |
Mar
(330) |
Apr
(294) |
May
(191) |
Jun
(108) |
Jul
(142) |
Aug
(261) |
Sep
(190) |
Oct
(54) |
Nov
(83) |
Dec
(22) |
| 2016 |
Jan
(49) |
Feb
(89) |
Mar
(33) |
Apr
(50) |
May
(27) |
Jun
(34) |
Jul
(53) |
Aug
(53) |
Sep
(98) |
Oct
(206) |
Nov
(93) |
Dec
(53) |
| 2017 |
Jan
(65) |
Feb
(82) |
Mar
(102) |
Apr
(86) |
May
(187) |
Jun
(67) |
Jul
(23) |
Aug
(93) |
Sep
(65) |
Oct
(45) |
Nov
(35) |
Dec
(17) |
| 2018 |
Jan
(26) |
Feb
(35) |
Mar
(38) |
Apr
(32) |
May
(8) |
Jun
(43) |
Jul
(27) |
Aug
(30) |
Sep
(43) |
Oct
(42) |
Nov
(38) |
Dec
(67) |
| 2019 |
Jan
(32) |
Feb
(37) |
Mar
(53) |
Apr
(64) |
May
(49) |
Jun
(18) |
Jul
(14) |
Aug
(53) |
Sep
(25) |
Oct
(30) |
Nov
(49) |
Dec
(31) |
| 2020 |
Jan
(87) |
Feb
(45) |
Mar
(37) |
Apr
(51) |
May
(99) |
Jun
(36) |
Jul
(11) |
Aug
(14) |
Sep
(20) |
Oct
(24) |
Nov
(40) |
Dec
(23) |
| 2021 |
Jan
(14) |
Feb
(53) |
Mar
(85) |
Apr
(15) |
May
(19) |
Jun
(3) |
Jul
(14) |
Aug
(1) |
Sep
(57) |
Oct
(73) |
Nov
(56) |
Dec
(22) |
| 2022 |
Jan
(3) |
Feb
(22) |
Mar
(6) |
Apr
(55) |
May
(46) |
Jun
(39) |
Jul
(15) |
Aug
(9) |
Sep
(11) |
Oct
(34) |
Nov
(20) |
Dec
(36) |
| 2023 |
Jan
(79) |
Feb
(41) |
Mar
(99) |
Apr
(169) |
May
(48) |
Jun
(16) |
Jul
(16) |
Aug
(57) |
Sep
(19) |
Oct
|
Nov
|
Dec
|
| S | M | T | W | T | F | S |
|---|---|---|---|---|---|---|
|
|
|
|
|
1
(12) |
2
(11) |
3
(8) |
|
4
(9) |
5
(10) |
6
(18) |
7
(8) |
8
(12) |
9
(23) |
10
(14) |
|
11
(15) |
12
(31) |
13
(45) |
14
(28) |
15
(20) |
16
(16) |
17
(9) |
|
18
(18) |
19
(26) |
20
(49) |
21
(14) |
22
(18) |
23
(24) |
24
(28) |
|
25
(39) |
26
(17) |
27
(27) |
28
(27) |
29
(14) |
30
(44) |
|
|
From: Tammy F. <tf...@re...> - 2005-09-16 20:21:46
|
Hi, A few people have suggested an article on valgrind for Red Hat Magazine (redhat.com/magazine). Next month, the feature topic is Linux development, from basic programming to debugging and profiling. If anyone is interested in writing the article, please contact me off- list. The deadline is the first week in October, and monetary compensation is involved. The word count is appropriately 2000 words. Regards, Tammy Fox Editor, Red Hat Magazine |
|
From: <sv...@va...> - 2005-09-16 16:02:20
|
Author: cerion
Date: 2005-09-16 17:02:11 +0100 (Fri, 16 Sep 2005)
New Revision: 1404
Log:
Some AltiVec vector-multiply arith insns
(those that don't need >32bit signed adds)
- vmhaddshs, vmhraddshs, vmladduhm, vmsumubm, vmsumuhm, vmsumshm
Modified:
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-16 08:55:50 UTC (rev 1403)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-16 16:02:11 UTC (rev 1404)
@@ -5004,16 +5004,11 @@
UInt opc2 =3D (theInstr >> 1) & 0x3FF; /* theInstr[1:10=
] */
UChar b0 =3D toUChar((theInstr >> 0) & 1); /* theInstr[0] =
*/
=20
- // IRTemp rA =3D newTemp(Ity_I32);
- // IRTemp rB =3D newTemp(Ity_I32);
IRTemp vS =3D newTemp(Ity_V128);
IRTemp EA =3D newTemp(Ity_I32);
IRTemp EA_aligned =3D newTemp(Ity_I32);
=20
- // assign( rA, getIReg(rA_addr));
- // assign( rB, getIReg(rB_addr));
assign( vS, getVReg(vS_addr));
-
assign( EA, ea_standard(rA_addr, rB_addr) );
=20
if (opc1 !=3D 0x1F || b0 !=3D 0) {
@@ -5064,10 +5059,6 @@
break;
}
=20
-// EA_aligned =3D EA & 0xFFFF_FFFC
-// eb =3D EA_aligned & 0xF;
-// STORE(vS[eb*8:eb*8+31], 4, EA_aligned);
-
case 0x0E7: // stvx (Store Vector Indexed, AV p134)
DIP("stvx v%d,r%d,r%d\n", vS_addr, rA_addr, rB_addr);
assign( EA_aligned, binop( Iop_And32, mkexpr(EA), mkU32(0xFFFFFFF0=
) ));
@@ -5558,56 +5549,184 @@
UChar vC_addr =3D toUChar((theInstr >> 6) & 0x1F); /* theInstr[6:10=
] */
UChar opc2 =3D toUChar((theInstr >> 0) & 0x3F); /* theInstr[0:5]=
*/
=20
+ IRTemp vA =3D newTemp(Ity_V128);
+ IRTemp vB =3D newTemp(Ity_V128);
+ IRTemp vC =3D newTemp(Ity_V128);
+ assign( vA, getVReg(vA_addr));
+ assign( vB, getVReg(vB_addr));
+ assign( vC, getVReg(vC_addr));
+
if (opc1 !=3D 0x4) {
vex_printf("dis_av_multarith(PPC32)(instr)\n");
return False;
}
=20
+ IRTemp zeros =3D newTemp(Ity_V128);
+ assign( zeros, unop(Iop_Dup32x4, mkU32(0)) );
+
switch (opc2) {
-
/* Multiply-Add */
- case 0x20: // vmhaddshs (Multiply High, Add Signed HW Saturate, AV p1=
85)
+ case 0x20: { // vmhaddshs (Multiply High, Add Signed HW Saturate, AV =
p185)
DIP("vmhaddshs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_a=
ddr);
- DIP(" =3D> not implemented\n");
- return False;
+ IRTemp aLo =3D newTemp(Ity_V128);
+ IRTemp bLo =3D newTemp(Ity_V128);
+ IRTemp cLo =3D newTemp(Ity_V128);
+ IRTemp zLo =3D newTemp(Ity_V128);
+ IRTemp aHi =3D newTemp(Ity_V128);
+ IRTemp bHi =3D newTemp(Ity_V128);
+ IRTemp cHi =3D newTemp(Ity_V128);
+ IRTemp zHi =3D newTemp(Ity_V128);
+ IRTemp cSigns =3D newTemp(Ity_V128);
+ assign( cSigns, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vC)) )=
;
+ assign( aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA=
)) );
+ assign( bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB=
)) );
+ assign( cLo, binop(Iop_InterleaveLO16x8, mkexpr(cSigns), mkexpr(vC=
)) );
+ assign( aHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vA=
)) );
+ assign( bHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vB=
)) );
+ assign( cHi, binop(Iop_InterleaveHI16x8, mkexpr(cSigns), mkexpr(vC=
)) );
=20
- case 0x21: // vmhraddshs (Multiply High Round, Add Signed HW Saturate=
, AV p186)
+ assign( zLo, binop(Iop_Add32x4,
+ binop(Iop_SarN32x4,
+ binop(Iop_MulLo32Sx4, mkexpr(aLo), mkexpr=
(bLo)),
+ mkU8(15)),
+ mkexpr(cLo)) );
+
+ assign( zHi, binop(Iop_Add32x4,
+ binop(Iop_SarN32x4,
+ binop(Iop_MulLo32Sx4, mkexpr(aHi), mkexpr=
(bHi)),
+ mkU8(15)),
+ mkexpr(cHi)) );
+
+ putVReg( vD_addr, binop(Iop_QNarrow32Sx4, mkexpr(zHi), mkexpr(zLo)=
) );
+ break;
+ }
+ case 0x21: { // vmhraddshs (Multiply High Round, Add Signed HW Satura=
te, AV p186)
DIP("vmhraddshs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_=
addr);
- DIP(" =3D> not implemented\n");
- return False;
+ IRTemp zKonst =3D newTemp(Ity_V128);
+ IRTemp aLo =3D newTemp(Ity_V128);
+ IRTemp bLo =3D newTemp(Ity_V128);
+ IRTemp cLo =3D newTemp(Ity_V128);
+ IRTemp zLo =3D newTemp(Ity_V128);
+ IRTemp aHi =3D newTemp(Ity_V128);
+ IRTemp bHi =3D newTemp(Ity_V128);
+ IRTemp cHi =3D newTemp(Ity_V128);
+ IRTemp zHi =3D newTemp(Ity_V128);
+ IRTemp cSigns =3D newTemp(Ity_V128);
+ assign( cSigns, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vC)) )=
;
+ assign( aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA=
)) );
+ assign( bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB=
)) );
+ assign( cLo, binop(Iop_InterleaveLO16x8, mkexpr(cSigns), mkexpr(vC=
)) );
+ assign( aHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vA=
)) );
+ assign( bHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vB=
)) );
+ assign( cHi, binop(Iop_InterleaveHI16x8, mkexpr(cSigns), mkexpr(vC=
)) );
=20
- case 0x22: // vmladduhm (Multiply Low, Add Unsigned HW Modulo, AV p19=
4)
+ /* shifting our const avoids store/load version of Dup */
+ assign( zKonst, binop(Iop_ShlN32x4, unop(Iop_Dup32x4,
+ mkU32(0x1)), mkU8(14)) );
+
+ assign( zLo, binop(Iop_Add32x4,
+ binop(Iop_SarN32x4,
+ binop(Iop_Add32x4, mkexpr(zKonst),
+ binop(Iop_MulLo32Sx4, mkexpr(aLo), =
mkexpr(bLo))),
+ mkU8(15)),
+ mkexpr(cLo)) );
+
+ assign( zHi, binop(Iop_Add32x4,
+ binop(Iop_SarN32x4,
+ binop(Iop_Add32x4, mkexpr(zKonst),
+ binop(Iop_MulLo32Sx4, mkexpr(aHi), =
mkexpr(bHi))),
+ mkU8(15)),
+ mkexpr(cHi)) );
+
+ putVReg( vD_addr, binop(Iop_QNarrow32Sx4, mkexpr(zHi), mkexpr(zLo)=
) );
+ break;
+ }
+ case 0x22: { // vmladduhm (Multiply Low, Add Unsigned HW Modulo, AV p=
194)
DIP("vmladduhm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_a=
ddr);
- DIP(" =3D> not implemented\n");
- return False;
+ IRTemp aLo =3D newTemp(Ity_V128);
+ IRTemp bLo =3D newTemp(Ity_V128);
+ IRTemp cLo =3D newTemp(Ity_V128);
+ IRTemp zLo =3D newTemp(Ity_V128);
+ IRTemp aHi =3D newTemp(Ity_V128);
+ IRTemp bHi =3D newTemp(Ity_V128);
+ IRTemp cHi =3D newTemp(Ity_V128);
+ IRTemp zHi =3D newTemp(Ity_V128);
+ assign( aLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vA)=
) );
+ assign( bLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vB)=
) );
+ assign( cLo, binop(Iop_InterleaveLO16x8, mkexpr(zeros), mkexpr(vC)=
) );
+ assign( aHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vA)=
) );
+ assign( bHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vB)=
) );
+ assign( cHi, binop(Iop_InterleaveHI16x8, mkexpr(zeros), mkexpr(vC)=
) );
+ assign( zLo, binop(Iop_Add32x4,
+ binop(Iop_MulLo32Ux4, mkexpr(aLo), mkexpr(bLo))=
,
+ mkexpr(cLo)) );
+ assign( zHi, binop(Iop_Add32x4,
+ binop(Iop_MulLo32Ux4, mkexpr(aHi), mkexpr(bHi))=
,
+ mkexpr(cHi)) );
+ putVReg( vD_addr, binop(Iop_Narrow32Ux4, mkexpr(zHi), mkexpr(zLo))=
);
+ break;
+ }
=20
=20
/* Multiply-Sum */
- case 0x24: // vmsumubm (Multiply Sum Unsigned B Modulo, AV p204)
+ case 0x24: { // vmsumubm (Multiply Sum Unsigned B Modulo, AV p204)
DIP("vmsumubm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
- DIP(" =3D> not implemented\n");
- return False;
+ IRTemp zKonst =3D newTemp(Ity_V128);
+ IRTemp odd =3D newTemp(Ity_V128);
+ IRTemp even =3D newTemp(Ity_V128);
+ IRTemp odd_odd =3D newTemp(Ity_V128);
+ IRTemp odd_even =3D newTemp(Ity_V128);
+ IRTemp even_odd =3D newTemp(Ity_V128);
+ IRTemp even_even =3D newTemp(Ity_V128);
+ assign( odd, binop(Iop_MulLo16Ux8, mkexpr(vA), mkexpr(vB)) );
+ assign( even, binop(Iop_MulHi16Ux8, mkexpr(vA), mkexpr(vB)) );
+ /* zKonst just used to separate the lanes out */
+ assign( zKonst, unop(Iop_Dup16x8, mkU16(0x1)) );
=20
+ assign( odd_odd, binop(Iop_MulLo32Ux4, mkexpr(odd), mkexpr(zKon=
st)) );
+ assign( odd_even, binop(Iop_MulHi32Ux4, mkexpr(odd), mkexpr(zKon=
st)) );
+ assign( even_odd, binop(Iop_MulLo32Ux4, mkexpr(even), mkexpr(zKon=
st)) );
+ assign( even_even, binop(Iop_MulHi32Ux4, mkexpr(even), mkexpr(zKon=
st)) );
+
+ putVReg( vD_addr,
+ binop(Iop_Add32x4, mkexpr(vC),
+ binop(Iop_Add32x4,
+ binop(Iop_Add32x4, mkexpr(odd_even), mkexpr(o=
dd_odd)),
+ binop(Iop_Add32x4, mkexpr(even_even), mkexpr(=
even_odd)))) );
+ break;
+ }
case 0x25: // vmsummbm (Multiply Sum Mixed-Sign B Modulo, AV p201)
DIP("vmsummbm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
DIP(" =3D> not implemented\n");
return False;
=20
- case 0x26: // vmsumuhm (Multiply Sum Unsigned HW Modulo, AV p205)
+ case 0x26: { // vmsumuhm (Multiply Sum Unsigned HW Modulo, AV p205)
DIP("vmsumuhm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
- DIP(" =3D> not implemented\n");
- return False;
-
+ IRTemp odd =3D newTemp(Ity_V128);
+ IRTemp even =3D newTemp(Ity_V128);
+ assign( odd, binop(Iop_MulLo32Ux4, mkexpr(vA), mkexpr(vB)) );
+ assign( even, binop(Iop_MulHi32Ux4, mkexpr(vA), mkexpr(vB)) );
+ putVReg( vD_addr,
+ binop(Iop_Add32x4, mkexpr(vC),
+ binop(Iop_Add32x4, mkexpr(odd), mkexpr(even))) );
+ break;
+ }
case 0x27: // vmsumuhs (Multiply Sum Unsigned HW Saturate, AV p206)
DIP("vmsumuhs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
DIP(" =3D> not implemented\n");
return False;
=20
- case 0x28: // vmsumshm (Multiply Sum Signed HW Modulo, AV p202)
+ case 0x28: { // vmsumshm (Multiply Sum Signed HW Modulo, AV p202)
DIP("vmsumshm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
- DIP(" =3D> not implemented\n");
- return False;
-
+ IRTemp odd =3D newTemp(Ity_V128);
+ IRTemp even =3D newTemp(Ity_V128);
+ assign( odd, binop(Iop_MulLo32Sx4, mkexpr(vA), mkexpr(vB)) );
+ assign( even, binop(Iop_MulHi32Sx4, mkexpr(vA), mkexpr(vB)) );
+ putVReg( vD_addr,
+ binop(Iop_Add32x4, mkexpr(vC),
+ binop(Iop_Add32x4, mkexpr(odd), mkexpr(even))) );
+ break;
+ }
case 0x29: // vmsumshs (Multiply Sum Signed HW Saturate, AV p203)
DIP("vmsumshs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
DIP(" =3D> not implemented\n");
|
|
From: <sv...@va...> - 2005-09-16 08:55:55
|
Author: cerion
Date: 2005-09-16 09:55:50 +0100 (Fri, 16 Sep 2005)
New Revision: 1403
Log:
spacing and var name chages only
- 'saturated' op names get a preceding Q instead of a trailing S
Modified:
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/hdefs.h
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-09-16 07:54:40 UTC (rev 1402)
+++ trunk/priv/host-ppc32/hdefs.c 2005-09-16 08:55:50 UTC (rev 1403)
@@ -645,13 +645,13 @@
case Pav_UNPCKLPIX: return "vupklpx";
=20
/* Integer binary */
- case Pav_ADDUM: return "vaddu_m"; // b,h,w
- case Pav_ADDUS: return "vaddu_s"; // b,h,w
- case Pav_ADDSS: return "vadds_s"; // b,h,w
+ case Pav_ADDU: return "vaddu_m"; // b,h,w
+ case Pav_QADDU: return "vaddu_s"; // b,h,w
+ case Pav_QADDS: return "vadds_s"; // b,h,w
=20
- case Pav_SUBUM: return "vsubu_m"; // b,h,w
- case Pav_SUBUS: return "vsubu_s"; // b,h,w
- case Pav_SUBSS: return "vsubs_s"; // b,h,w
+ case Pav_SUBU: return "vsubu_m"; // b,h,w
+ case Pav_QSUBU: return "vsubu_s"; // b,h,w
+ case Pav_QSUBS: return "vsubs_s"; // b,h,w
=20
case Pav_OMULU: return "vmulou"; // b,h
case Pav_OMULS: return "vmulos"; // b,h
@@ -679,17 +679,16 @@
case Pav_ROTL: return "vrl"; // b,h,w
=20
/* Pack */
- case Pav_PACKUUM: return "vpku_um"; // h,w
- case Pav_PACKUUS: return "vpku_us"; // h,w
- case Pav_PACKSUS: return "vpks_us"; // h,w
- case Pav_PACKSSS: return "vpks_ss"; // h,w
+ case Pav_PACKUU: return "vpku_um"; // h,w
+ case Pav_QPACKUU: return "vpku_us"; // h,w
+ case Pav_QPACKSU: return "vpks_us"; // h,w
+ case Pav_QPACKSS: return "vpks_ss"; // h,w
case Pav_PACKPXL: return "vpkpx";
=20
/* Merge */
case Pav_MRGHI: return "vmrgh"; // b,h,w
case Pav_MRGLO: return "vmrgl"; // b,h,w
=20
-
/* Floating Point Binary */
case Pav_ADDF: return "vaddfp";
case Pav_SUBF: return "vsubfp";
@@ -2894,13 +2893,13 @@
UInt opc2;
switch (i->Pin.AvBin8x16.op) {
=20
- case Pav_ADDUM: opc2 =3D 0; break; // vaddubm
- case Pav_ADDUS: opc2 =3D 512; break; // vaddubs
- case Pav_ADDSS: opc2 =3D 768; break; // vaddsbs
+ case Pav_ADDU: opc2 =3D 0; break; // vaddubm
+ case Pav_QADDU: opc2 =3D 512; break; // vaddubs
+ case Pav_QADDS: opc2 =3D 768; break; // vaddsbs
=20
- case Pav_SUBUM: opc2 =3D 1024; break; // vsububm
- case Pav_SUBUS: opc2 =3D 1536; break; // vsububs
- case Pav_SUBSS: opc2 =3D 1792; break; // vsubsbs
+ case Pav_SUBU: opc2 =3D 1024; break; // vsububm
+ case Pav_QSUBU: opc2 =3D 1536; break; // vsububs
+ case Pav_QSUBS: opc2 =3D 1792; break; // vsubsbs
=20
case Pav_AVGU: opc2 =3D 1026; break; // vavgub
case Pav_AVGS: opc2 =3D 1282; break; // vavgsb
@@ -2935,18 +2934,18 @@
UInt opc2;
switch (i->Pin.AvBin16x8.op) {
=20
- case Pav_ADDUM: opc2 =3D 64; break; // vadduhm
- case Pav_ADDUS: opc2 =3D 576; break; // vadduhs
- case Pav_ADDSS: opc2 =3D 832; break; // vaddshs
+ case Pav_ADDU: opc2 =3D 64; break; // vadduhm
+ case Pav_QADDU: opc2 =3D 576; break; // vadduhs
+ case Pav_QADDS: opc2 =3D 832; break; // vaddshs
=20
- case Pav_SUBUM: opc2 =3D 1088; break; // vsubuhm
- case Pav_SUBUS: opc2 =3D 1600; break; // vsubuhs
- case Pav_SUBSS: opc2 =3D 1856; break; // vsubshs
+ case Pav_SUBU: opc2 =3D 1088; break; // vsubuhm
+ case Pav_QSUBU: opc2 =3D 1600; break; // vsubuhs
+ case Pav_QSUBS: opc2 =3D 1856; break; // vsubshs
=20
- case Pav_OMULU: opc2 =3D 8; break; // vmuloub
- case Pav_OMULS: opc2 =3D 264; break; // vmulosb
- case Pav_EMULU: opc2 =3D 520; break; // vmuleub
- case Pav_EMULS: opc2 =3D 776; break; // vmulesb
+ case Pav_OMULU: opc2 =3D 8; break; // vmuloub
+ case Pav_OMULS: opc2 =3D 264; break; // vmulosb
+ case Pav_EMULU: opc2 =3D 520; break; // vmuleub
+ case Pav_EMULS: opc2 =3D 776; break; // vmulesb
=20
case Pav_AVGU: opc2 =3D 1090; break; // vavguh
case Pav_AVGS: opc2 =3D 1346; break; // vavgsh
@@ -2964,11 +2963,11 @@
case Pav_SAR: opc2 =3D 836; break; // vsrah
case Pav_ROTL: opc2 =3D 68; break; // vrlh
=20
- case Pav_PACKUUM: opc2 =3D 14; break; // vpkuhum
- case Pav_PACKUUS: opc2 =3D 142; break; // vpkuhus
- case Pav_PACKSUS: opc2 =3D 270; break; // vpkshus
- case Pav_PACKSSS: opc2 =3D 398; break; // vpkshss
- case Pav_PACKPXL: opc2 =3D 782; break; // vpkpx
+ case Pav_PACKUU: opc2 =3D 14; break; // vpkuhum
+ case Pav_QPACKUU: opc2 =3D 142; break; // vpkuhus
+ case Pav_QPACKSU: opc2 =3D 270; break; // vpkshus
+ case Pav_QPACKSS: opc2 =3D 398; break; // vpkshss
+ case Pav_PACKPXL: opc2 =3D 782; break; // vpkpx
=20
case Pav_MRGHI: opc2 =3D 76; break; // vmrghh
case Pav_MRGLO: opc2 =3D 332; break; // vmrglh
@@ -2987,13 +2986,13 @@
UInt opc2;
switch (i->Pin.AvBin32x4.op) {
=20
- case Pav_ADDUM: opc2 =3D 128; break; // vadduwm
- case Pav_ADDUS: opc2 =3D 640; break; // vadduws
- case Pav_ADDSS: opc2 =3D 896; break; // vaddsws
+ case Pav_ADDU: opc2 =3D 128; break; // vadduwm
+ case Pav_QADDU: opc2 =3D 640; break; // vadduws
+ case Pav_QADDS: opc2 =3D 896; break; // vaddsws
=20
- case Pav_SUBUM: opc2 =3D 1152; break; // vsubuwm
- case Pav_SUBUS: opc2 =3D 1664; break; // vsubuws
- case Pav_SUBSS: opc2 =3D 1920; break; // vsubsws
+ case Pav_SUBU: opc2 =3D 1152; break; // vsubuwm
+ case Pav_QSUBU: opc2 =3D 1664; break; // vsubuws
+ case Pav_QSUBS: opc2 =3D 1920; break; // vsubsws
=20
case Pav_OMULU: opc2 =3D 72; break; // vmulouh
case Pav_OMULS: opc2 =3D 328; break; // vmulosh
@@ -3018,10 +3017,10 @@
case Pav_SAR: opc2 =3D 900; break; // vsraw
case Pav_ROTL: opc2 =3D 132; break; // vrlw
=20
- case Pav_PACKUUM: opc2 =3D 78; break; // vpkuwum
- case Pav_PACKUUS: opc2 =3D 206; break; // vpkuwus
- case Pav_PACKSUS: opc2 =3D 334; break; // vpkswus
- case Pav_PACKSSS: opc2 =3D 462; break; // vpkswss
+ case Pav_PACKUU: opc2 =3D 78; break; // vpkuwum
+ case Pav_QPACKUU: opc2 =3D 206; break; // vpkuwus
+ case Pav_QPACKSU: opc2 =3D 334; break; // vpkswus
+ case Pav_QPACKSS: opc2 =3D 462; break; // vpkswss
=20
case Pav_MRGHI: opc2 =3D 140; break; // vmrghw
case Pav_MRGLO: opc2 =3D 396; break; // vmrglw
Modified: trunk/priv/host-ppc32/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.h 2005-09-16 07:54:40 UTC (rev 1402)
+++ trunk/priv/host-ppc32/hdefs.h 2005-09-16 08:55:50 UTC (rev 1403)
@@ -378,9 +378,9 @@
/* Integer Binary */
Pav_AND, Pav_OR, Pav_XOR, /* Bitwise */
=20
- Pav_ADDUM, Pav_ADDUS,Pav_ADDSS,
+ Pav_ADDU, Pav_QADDU, Pav_QADDS,
=20
- Pav_SUBUM, Pav_SUBUS, Pav_SUBSS,
+ Pav_SUBU, Pav_QSUBU, Pav_QSUBS,
=20
Pav_OMULU, Pav_OMULS, Pav_EMULU, Pav_EMULS,
=20
@@ -395,7 +395,7 @@
Pav_SHL, Pav_SHR, Pav_SAR, Pav_ROTL,
=20
/* Pack */
- Pav_PACKUUM, Pav_PACKUUS, Pav_PACKSUS, Pav_PACKSSS,
+ Pav_PACKUU, Pav_QPACKUU, Pav_QPACKSU, Pav_QPACKSS,
Pav_PACKPXL,
=20
/* Merge */
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-09-16 07:54:40 UTC (rev 1402)
+++ trunk/priv/host-ppc32/isel.c 2005-09-16 08:55:50 UTC (rev 1403)
@@ -781,9 +781,9 @@
addInstr(env, PPC32Instr_AvSplat(sz, v1, PPC32VI5s_Imm(-16))=
);
addInstr(env, PPC32Instr_AvSplat(sz, v2, PPC32VI5s_Imm(simm6=
-16)));
addInstr(env,
- (sz=3D=3D 8) ? PPC32Instr_AvBin8x16(Pav_SUBUM, dst, v2, v=
1) :
- (sz=3D=3D16) ? PPC32Instr_AvBin16x8(Pav_SUBUM, dst, v2, v=
1)
- : PPC32Instr_AvBin32x4(Pav_SUBUM, dst, v2, v1) )=
;
+ (sz=3D=3D 8) ? PPC32Instr_AvBin8x16(Pav_SUBU, dst, v2, v1=
) :
+ (sz=3D=3D16) ? PPC32Instr_AvBin16x8(Pav_SUBU, dst, v2, v1=
)
+ : PPC32Instr_AvBin32x4(Pav_SUBU, dst, v2, v1) );
return dst;
}
if (simm6 < -16) { /* -32:-17 inclusive */
@@ -792,9 +792,9 @@
addInstr(env, PPC32Instr_AvSplat(sz, v1, PPC32VI5s_Imm(-16))=
);
addInstr(env, PPC32Instr_AvSplat(sz, v2, PPC32VI5s_Imm(simm6=
+16)));
addInstr(env,
- (sz=3D=3D 8) ? PPC32Instr_AvBin8x16(Pav_ADDUM, dst, v2, v=
1) :
- (sz=3D=3D16) ? PPC32Instr_AvBin16x8(Pav_ADDUM, dst, v2, v=
1)
- : PPC32Instr_AvBin32x4(Pav_ADDUM, dst, v2, v1) )=
;
+ (sz=3D=3D 8) ? PPC32Instr_AvBin8x16(Pav_ADDU, dst, v2, v1=
) :
+ (sz=3D=3D16) ? PPC32Instr_AvBin16x8(Pav_ADDU, dst, v2, v1=
)
+ : PPC32Instr_AvBin32x4(Pav_ADDU, dst, v2, v1) );
return dst;
}
/* simplest form: -16:15 inclusive */
@@ -3294,12 +3294,12 @@
case Iop_Rotl8x16: op =3D Pav_ROTL; goto do_AvBin8x16;
case Iop_InterleaveHI8x16: op =3D Pav_MRGHI; goto do_AvBin8x16;
case Iop_InterleaveLO8x16: op =3D Pav_MRGLO; goto do_AvBin8x16;
- case Iop_Add8x16: op =3D Pav_ADDUM; goto do_AvBin8x16;
- case Iop_QAdd8Ux16: op =3D Pav_ADDUS; goto do_AvBin8x16;
- case Iop_QAdd8Sx16: op =3D Pav_ADDSS; goto do_AvBin8x16;
- case Iop_Sub8x16: op =3D Pav_SUBUM; goto do_AvBin8x16;
- case Iop_QSub8Ux16: op =3D Pav_SUBUS; goto do_AvBin8x16;
- case Iop_QSub8Sx16: op =3D Pav_SUBSS; goto do_AvBin8x16;
+ case Iop_Add8x16: op =3D Pav_ADDU; goto do_AvBin8x16;
+ case Iop_QAdd8Ux16: op =3D Pav_QADDU; goto do_AvBin8x16;
+ case Iop_QAdd8Sx16: op =3D Pav_QADDS; goto do_AvBin8x16;
+ case Iop_Sub8x16: op =3D Pav_SUBU; goto do_AvBin8x16;
+ case Iop_QSub8Ux16: op =3D Pav_QSUBU; goto do_AvBin8x16;
+ case Iop_QSub8Sx16: op =3D Pav_QSUBS; goto do_AvBin8x16;
case Iop_Avg8Ux16: op =3D Pav_AVGU; goto do_AvBin8x16;
case Iop_Avg8Sx16: op =3D Pav_AVGS; goto do_AvBin8x16;
case Iop_Max8Ux16: op =3D Pav_MAXU; goto do_AvBin8x16;
@@ -3321,17 +3321,17 @@
case Iop_Shr16x8: op =3D Pav_SHR; goto do_AvBin16x8;
case Iop_Sar16x8: op =3D Pav_SAR; goto do_AvBin16x8;
case Iop_Rotl16x8: op =3D Pav_ROTL; goto do_AvBin16x8;
- case Iop_Narrow16Ux8: op =3D Pav_PACKUUM; goto do_AvBin16x8;
- case Iop_QNarrow16Ux8: op =3D Pav_PACKUUS; goto do_AvBin16x8;
- case Iop_QNarrow16Sx8: op =3D Pav_PACKSSS; goto do_AvBin16x8;
+ case Iop_Narrow16Ux8: op =3D Pav_PACKUU; goto do_AvBin16x8;
+ case Iop_QNarrow16Ux8: op =3D Pav_QPACKUU; goto do_AvBin16x8;
+ case Iop_QNarrow16Sx8: op =3D Pav_QPACKSS; goto do_AvBin16x8;
case Iop_InterleaveHI16x8: op =3D Pav_MRGHI; goto do_AvBin16x8;
case Iop_InterleaveLO16x8: op =3D Pav_MRGLO; goto do_AvBin16x8;
- case Iop_Add16x8: op =3D Pav_ADDUM; goto do_AvBin16x8;
- case Iop_QAdd16Ux8: op =3D Pav_ADDUS; goto do_AvBin16x8;
- case Iop_QAdd16Sx8: op =3D Pav_ADDSS; goto do_AvBin16x8;
- case Iop_Sub16x8: op =3D Pav_SUBUM; goto do_AvBin16x8;
- case Iop_QSub16Ux8: op =3D Pav_SUBUS; goto do_AvBin16x8;
- case Iop_QSub16Sx8: op =3D Pav_SUBSS; goto do_AvBin16x8;
+ case Iop_Add16x8: op =3D Pav_ADDU; goto do_AvBin16x8;
+ case Iop_QAdd16Ux8: op =3D Pav_QADDU; goto do_AvBin16x8;
+ case Iop_QAdd16Sx8: op =3D Pav_QADDS; goto do_AvBin16x8;
+ case Iop_Sub16x8: op =3D Pav_SUBU; goto do_AvBin16x8;
+ case Iop_QSub16Ux8: op =3D Pav_QSUBU; goto do_AvBin16x8;
+ case Iop_QSub16Sx8: op =3D Pav_QSUBS; goto do_AvBin16x8;
case Iop_Avg16Ux8: op =3D Pav_AVGU; goto do_AvBin16x8;
case Iop_Avg16Sx8: op =3D Pav_AVGS; goto do_AvBin16x8;
case Iop_Max16Ux8: op =3D Pav_MAXU; goto do_AvBin16x8;
@@ -3357,17 +3357,17 @@
case Iop_Shr32x4: op =3D Pav_SHR; goto do_AvBin32x4;
case Iop_Sar32x4: op =3D Pav_SAR; goto do_AvBin32x4;
case Iop_Rotl32x4: op =3D Pav_ROTL; goto do_AvBin32x4;
- case Iop_Narrow32Ux4: op =3D Pav_PACKUUM; goto do_AvBin32x4;
- case Iop_QNarrow32Ux4: op =3D Pav_PACKUUS; goto do_AvBin32x4;
- case Iop_QNarrow32Sx4: op =3D Pav_PACKSSS; goto do_AvBin32x4;
+ case Iop_Narrow32Ux4: op =3D Pav_PACKUU; goto do_AvBin32x4;
+ case Iop_QNarrow32Ux4: op =3D Pav_QPACKUU; goto do_AvBin32x4;
+ case Iop_QNarrow32Sx4: op =3D Pav_QPACKSS; goto do_AvBin32x4;
case Iop_InterleaveHI32x4: op =3D Pav_MRGHI; goto do_AvBin32x4;
case Iop_InterleaveLO32x4: op =3D Pav_MRGLO; goto do_AvBin32x4;
- case Iop_Add32x4: op =3D Pav_ADDUM; goto do_AvBin32x4;
- case Iop_QAdd32Ux4: op =3D Pav_ADDUS; goto do_AvBin32x4;
- case Iop_QAdd32Sx4: op =3D Pav_ADDSS; goto do_AvBin32x4;
- case Iop_Sub32x4: op =3D Pav_SUBUM; goto do_AvBin32x4;
- case Iop_QSub32Ux4: op =3D Pav_SUBUS; goto do_AvBin32x4;
- case Iop_QSub32Sx4: op =3D Pav_SUBSS; goto do_AvBin32x4;
+ case Iop_Add32x4: op =3D Pav_ADDU; goto do_AvBin32x4;
+ case Iop_QAdd32Ux4: op =3D Pav_QADDU; goto do_AvBin32x4;
+ case Iop_QAdd32Sx4: op =3D Pav_QADDS; goto do_AvBin32x4;
+ case Iop_Sub32x4: op =3D Pav_SUBU; goto do_AvBin32x4;
+ case Iop_QSub32Ux4: op =3D Pav_QSUBU; goto do_AvBin32x4;
+ case Iop_QSub32Sx4: op =3D Pav_QSUBS; goto do_AvBin32x4;
case Iop_Avg32Ux4: op =3D Pav_AVGU; goto do_AvBin32x4;
case Iop_Avg32Sx4: op =3D Pav_AVGS; goto do_AvBin32x4;
case Iop_Max32Ux4: op =3D Pav_MAXU; goto do_AvBin32x4;
|
|
From: <sv...@va...> - 2005-09-16 07:54:42
|
Author: cerion
Date: 2005-09-16 08:54:40 +0100 (Fri, 16 Sep 2005)
New Revision: 1402
Log:
More AltiVec: shifts and rotates
- vrl*, vsl*, vsr*
Modified:
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-16 07:53:31 UTC (rev 1401)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-16 07:54:40 UTC (rev 1402)
@@ -5645,61 +5645,73 @@
/* Rotate */
case 0x004: // vrlb (Rotate Left Integer B, AV p234)
DIP("vrlb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Rotl8x16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x044: // vrlh (Rotate Left Integer HW, AV p235)
DIP("vrlh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Rotl16x8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x084: // vrlw (Rotate Left Integer W, AV p236)
DIP("vrlw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Rotl32x4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
=20
/* Shift Left */
case 0x104: // vslb (Shift Left Integer B, AV p240)
DIP("vslb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Shl8x16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x144: // vslh (Shift Left Integer HW, AV p242)
DIP("vslh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Shl16x8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x184: // vslw (Shift Left Integer W, AV p244)
DIP("vslw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Shl32x4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
- case 0x1C4: // vsl (Shift Left, AV p239)
+ case 0x1C4: { // vsl (Shift Left, AV p239)
DIP("vsl v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
-
- case 0x40C: // vslo (Shift Left by Octet, AV p243)
+ IRTemp sh =3D newTemp(Ity_I8);
+ assign( sh, binop(Iop_And8, mkU8(0x7),
+ unop(Iop_32to8,
+ unop(Iop_V128to32, mkexpr(vB)))) );
+ putVReg( vD_addr,
+ binop(Iop_ShlV128, mkexpr(vA), mkexpr(sh)) );
+ break;
+ }
+ case 0x40C: { // vslo (Shift Left by Octet, AV p243)
DIP("vslo v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ IRTemp sh =3D newTemp(Ity_I8);
+ assign( sh, binop(Iop_And8, mkU8(0x78),
+ unop(Iop_32to8,
+ unop(Iop_V128to32, mkexpr(vB)))) );
+ putVReg( vD_addr,
+ binop(Iop_ShlV128, mkexpr(vA), mkexpr(sh)) );
+ break;
+ }
=20
+
/* Shift Right */
case 0x204: // vsrb (Shift Right B, AV p256)
DIP("vsrb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Shr8x16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x244: // vsrh (Shift Right HW, AV p257)
DIP("vsrh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Shr16x8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x284: // vsrw (Shift Right W, AV p259)
DIP("vsrw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Shr32x4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x2C4: { // vsr (Shift Right, AV p251)
DIP("vsr v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
@@ -5713,23 +5725,29 @@
}
case 0x304: // vsrab (Shift Right Algebraic B, AV p253)
DIP("vsrab v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Sar8x16, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x344: // vsrah (Shift Right Algebraic HW, AV p254)
DIP("vsrah v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Sar16x8, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
case 0x384: // vsraw (Shift Right Algebraic W, AV p255)
DIP("vsraw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Sar32x4, mkexpr(vA), mkexpr(vB)) );
+ break;
=20
- case 0x44C: // vsro (Shift Right by Octet, AV p258)
+ case 0x44C: { // vsro (Shift Right by Octet, AV p258)
DIP("vsro v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ IRTemp sh =3D newTemp(Ity_I8);
+ assign( sh, binop(Iop_And8, mkU8(0x78),
+ unop(Iop_32to8,
+ unop(Iop_V128to32, mkexpr(vB)))) );
+ putVReg( vD_addr,
+ binop(Iop_ShrV128, mkexpr(vA), mkexpr(sh)) );
+ break;
+ }
=20
default:
vex_printf("dis_av_shift(PPC32)(opc2)\n");
@@ -6054,7 +6072,6 @@
return False;
}
=20
-
IRTemp signs =3D newTemp(Ity_V128);
IRTemp zeros =3D newTemp(Ity_V128);
assign( zeros, unop(Iop_Dup32x4, mkU32(0)) );
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-09-16 07:53:31 UTC (rev 1401)
+++ trunk/priv/host-ppc32/isel.c 2005-09-16 07:54:40 UTC (rev 1402)
@@ -3275,13 +3275,6 @@
//.. return dst;
//.. }
=20
-//.. case Iop_QNarrow32Sx4:=20
-//.. op =3D Xsse_PACKSSD; arg1isEReg =3D True; goto do_SseReRg;
-//.. case Iop_QNarrow16Sx8:=20
-//.. op =3D Xsse_PACKSSW; arg1isEReg =3D True; goto do_SseReRg;
-//.. case Iop_QNarrow16Ux8:=20
-//.. op =3D Xsse_PACKUSW; arg1isEReg =3D True; goto do_SseReRg;
-
case Iop_AndV128: op =3D Pav_AND; goto do_AvBin;
case Iop_OrV128: op =3D Pav_OR; goto do_AvBin;
case Iop_XorV128: op =3D Pav_XOR; goto do_AvBin;
@@ -3293,27 +3286,12 @@
return dst;
}
=20
-//.. case Iop_Add8x16: op =3D Xsse_ADD8; goto do_SseReRg;
-//.. case Iop_Add64x2: op =3D Xsse_ADD64; goto do_SseReRg;
-//.. case Iop_QAdd8Sx16: op =3D Xsse_QADD8S; goto do_SseReRg;
-//.. case Iop_QAdd16Sx8: op =3D Xsse_QADD16S; goto do_SseReRg;
-//.. case Iop_QAdd8Ux16: op =3D Xsse_QADD8U; goto do_SseReRg;
-//.. case Iop_QAdd16Ux8: op =3D Xsse_QADD16U; goto do_SseReRg;
-//.. case Iop_Avg8Ux16: op =3D Xsse_AVG8U; goto do_SseReRg;
-//.. case Iop_Avg16Ux8: op =3D Xsse_AVG16U; goto do_SseReRg;
-//.. case Iop_CmpEQ8x16: op =3D Xsse_CMPEQ8; goto do_SseReRg;
-//.. case Iop_CmpEQ16x8: op =3D Xsse_CMPEQ16; goto do_SseReRg;
-//.. case Iop_CmpEQ32x4: op =3D Xsse_CMPEQ32; goto do_SseReRg;
-//.. case Iop_CmpGT8Sx16: op =3D Xsse_CMPGT8S; goto do_SseReRg;
-//.. case Iop_CmpGT16Sx8: op =3D Xsse_CMPGT16S; goto do_SseReRg;
-//.. case Iop_CmpGT32Sx4: op =3D Xsse_CMPGT32S; goto do_SseReRg;
//.. case Iop_Mul16x8: op =3D Xsse_MUL16; goto do_SseReRg;
-//.. case Iop_Sub64x2: op =3D Xsse_SUB64; goto do_SseReRg;
-//.. case Iop_QSub8Sx16: op =3D Xsse_QSUB8S; goto do_SseReRg;
-//.. case Iop_QSub16Sx8: op =3D Xsse_QSUB16S; goto do_SseReRg;
-//.. case Iop_QSub8Ux16: op =3D Xsse_QSUB8U; goto do_SseReRg;
-//.. case Iop_QSub16Ux8: op =3D Xsse_QSUB16U; goto do_SseReRg;
=20
+ case Iop_Shl8x16: op =3D Pav_SHL; goto do_AvBin8x16;
+ case Iop_Shr8x16: op =3D Pav_SHR; goto do_AvBin8x16;
+ case Iop_Sar8x16: op =3D Pav_SAR; goto do_AvBin8x16;
+ case Iop_Rotl8x16: op =3D Pav_ROTL; goto do_AvBin8x16;
case Iop_InterleaveHI8x16: op =3D Pav_MRGHI; goto do_AvBin8x16;
case Iop_InterleaveLO8x16: op =3D Pav_MRGLO; goto do_AvBin8x16;
case Iop_Add8x16: op =3D Pav_ADDUM; goto do_AvBin8x16;
@@ -3339,6 +3317,10 @@
return dst;
}
=20
+ case Iop_Shl16x8: op =3D Pav_SHL; goto do_AvBin16x8;
+ case Iop_Shr16x8: op =3D Pav_SHR; goto do_AvBin16x8;
+ case Iop_Sar16x8: op =3D Pav_SAR; goto do_AvBin16x8;
+ case Iop_Rotl16x8: op =3D Pav_ROTL; goto do_AvBin16x8;
case Iop_Narrow16Ux8: op =3D Pav_PACKUUM; goto do_AvBin16x8;
case Iop_QNarrow16Ux8: op =3D Pav_PACKUUS; goto do_AvBin16x8;
case Iop_QNarrow16Sx8: op =3D Pav_PACKSSS; goto do_AvBin16x8;
@@ -3371,6 +3353,10 @@
return dst;
}
=20
+ case Iop_Shl32x4: op =3D Pav_SHL; goto do_AvBin32x4;
+ case Iop_Shr32x4: op =3D Pav_SHR; goto do_AvBin32x4;
+ case Iop_Sar32x4: op =3D Pav_SAR; goto do_AvBin32x4;
+ case Iop_Rotl32x4: op =3D Pav_ROTL; goto do_AvBin32x4;
case Iop_Narrow32Ux4: op =3D Pav_PACKUUM; goto do_AvBin32x4;
case Iop_QNarrow32Ux4: op =3D Pav_PACKUUS; goto do_AvBin32x4;
case Iop_QNarrow32Sx4: op =3D Pav_PACKSSS; goto do_AvBin32x4;
@@ -3403,30 +3389,6 @@
return dst;
}
=20
-//.. do_SseReRg: {
-//.. HReg arg1 =3D iselVecExpr(env, e->Iex.Binop.arg1);
-//.. HReg arg2 =3D iselVecExpr(env, e->Iex.Binop.arg2);
-//.. HReg dst =3D newVRegV(env);
-//.. if (op !=3D Xsse_OR && op !=3D Xsse_AND && op !=3D Xsse_XO=
R)
-//.. REQUIRE_SSE2;
-//.. if (arg1isEReg) {
-//.. addInstr(env, mk_vMOVsd_RR(arg2, dst));
-//.. addInstr(env, X86Instr_SseReRg(op, arg1, dst));
-//.. } else {
-//.. addInstr(env, mk_vMOVsd_RR(arg1, dst));
-//.. addInstr(env, X86Instr_SseReRg(op, arg2, dst));
-//.. }
-//.. return dst;
-//.. }
-//..=20
-//.. case Iop_ShlN16x8: op =3D Xsse_SHL16; goto do_SseShift;
-//.. case Iop_ShlN32x4: op =3D Xsse_SHL32; goto do_SseShift;
-//.. case Iop_ShlN64x2: op =3D Xsse_SHL64; goto do_SseShift;
-//.. case Iop_SarN16x8: op =3D Xsse_SAR16; goto do_SseShift;
-//.. case Iop_SarN32x4: op =3D Xsse_SAR32; goto do_SseShift;
-//.. case Iop_ShrN16x8: op =3D Xsse_SHR16; goto do_SseShift;
-//.. case Iop_ShrN64x2: op =3D Xsse_SHR64; goto do_SseShift;
-
case Iop_ShlN8x16: op =3D Pav_SHL; goto do_AvShift8x16;
case Iop_SarN8x16: op =3D Pav_SAR; goto do_AvShift8x16;
do_AvShift8x16: {
|
|
From: <sv...@va...> - 2005-09-16 07:53:37
|
Author: cerion
Date: 2005-09-16 08:53:31 +0100 (Fri, 16 Sep 2005)
New Revision: 1401
Log:
Rename primop Iop_Rot* Iop_Rotl*
Modified:
trunk/priv/ir/irdefs.c
trunk/pub/libvex_ir.h
Modified: trunk/priv/ir/irdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/irdefs.c 2005-09-16 07:13:44 UTC (rev 1400)
+++ trunk/priv/ir/irdefs.c 2005-09-16 07:53:31 UTC (rev 1401)
@@ -499,9 +499,9 @@
case Iop_Sar8x16: vex_printf("Sar8x16"); return;
case Iop_Sar16x8: vex_printf("Sar16x8"); return;
case Iop_Sar32x4: vex_printf("Sar32x4"); return;
- case Iop_Rot8x16: vex_printf("Rot8x16"); return;
- case Iop_Rot16x8: vex_printf("Rot16x8"); return;
- case Iop_Rot32x4: vex_printf("Rot32x4"); return;
+ case Iop_Rotl8x16: vex_printf("Rotl8x16"); return;
+ case Iop_Rotl16x8: vex_printf("Rotl16x8"); return;
+ case Iop_Rotl32x4: vex_printf("Rotl32x4"); return;
=20
case Iop_Narrow16Ux8: vex_printf("Narrow16Ux8"); return;
case Iop_Narrow32Ux4: vex_printf("Narrow32Ux4"); return;
@@ -1566,7 +1566,7 @@
case Iop_Shl8x16: case Iop_Shl16x8: case Iop_Shl32x4:
case Iop_Shr8x16: case Iop_Shr16x8: case Iop_Shr32x4:
case Iop_Sar8x16: case Iop_Sar16x8: case Iop_Sar32x4:
- case Iop_Rot8x16: case Iop_Rot16x8: case Iop_Rot32x4:
+ case Iop_Rotl8x16: case Iop_Rotl16x8: case Iop_Rotl32x4:
case Iop_QNarrow16Ux8: case Iop_QNarrow32Ux4:
case Iop_QNarrow16Sx8: case Iop_QNarrow32Sx4:
case Iop_Narrow16Ux8: case Iop_Narrow32Ux4:
Modified: trunk/pub/libvex_ir.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/pub/libvex_ir.h 2005-09-16 07:13:44 UTC (rev 1400)
+++ trunk/pub/libvex_ir.h 2005-09-16 07:53:31 UTC (rev 1401)
@@ -578,7 +578,7 @@
Iop_Shl8x16, Iop_Shl16x8, Iop_Shl32x4,
Iop_Shr8x16, Iop_Shr16x8, Iop_Shr32x4,
Iop_Sar8x16, Iop_Sar16x8, Iop_Sar32x4,
- Iop_Rot8x16, Iop_Rot16x8, Iop_Rot32x4,
+ Iop_Rotl8x16, Iop_Rotl16x8, Iop_Rotl32x4,
=20
/* NARROWING -- narrow 2xV128 into 1xV128, hi half from left arg *=
/
Iop_QNarrow16Ux8, Iop_QNarrow32Ux4,
|
|
From: <sv...@va...> - 2005-09-16 07:13:49
|
Author: cerion
Date: 2005-09-16 08:13:44 +0100 (Fri, 16 Sep 2005)
New Revision: 1400
Log:
Added packing/unpacking AltiVec insns
- vpk*, vupk*
Modified:
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-09-15 21:58:50 UTC (rev 1399)
+++ trunk/priv/guest-ppc32/toIR.c 2005-09-16 07:13:44 UTC (rev 1400)
@@ -5917,6 +5917,11 @@
UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
UInt opc2 =3D (theInstr >> 0) & 0x7FF; /* theInstr[0:10=
] */
=20
+ IRTemp vA =3D newTemp(Ity_V128);
+ IRTemp vB =3D newTemp(Ity_V128);
+ assign( vA, getVReg(vA_addr));
+ assign( vB, getVReg(vB_addr));
+
if (opc1 !=3D 0x4) {
vex_printf("dis_av_pack(PPC32)(instr)\n");
return False;
@@ -5926,49 +5931,119 @@
/* Packing */
case 0x00E: // vpkuhum (Pack Unsigned HW Unsigned Modulo, AV p224)
DIP("vpkuhum v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Narrow16Ux8, mkexpr(vA), mkexpr(vB)) )=
;
+ return True;
=20
case 0x04E: // vpkuwum (Pack Unsigned W Unsigned Modulo, AV p226)
DIP("vpkuwum v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_Narrow32Ux4, mkexpr(vA), mkexpr(vB)) )=
;
+ return True;
=20
case 0x08E: // vpkuhus (Pack Unsigned HW Unsigned Saturate, AV p225)
DIP("vpkuhus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_QNarrow16Ux8, mkexpr(vA), mkexpr(vB)) =
);
+ // TODO: set VSCR[SAT]
+ return True;
=20
case 0x0CE: // vpkuwus (Pack Unsigned W Unsigned Saturate, AV p227)
DIP("vpkuwus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_QNarrow32Ux4, mkexpr(vA), mkexpr(vB)) =
);
+ // TODO: set VSCR[SAT]
+ return True;
=20
- case 0x10E: // vpkshus (Pack Signed HW Unsigned Saturate, AV p221)
+ case 0x10E: { // vpkshus (Pack Signed HW Unsigned Saturate, AV p221)
DIP("vpkshus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
-
- case 0x14E: // vpkswus (Pack Signed W Unsigned Saturate, AV p223)
+ // This insn does a signed->unsigned saturating conversion.
+ // Conversion done here, then uses unsigned->unsigned vpk insn:
+ // =3D> UnsignedSaturatingNarrow( x & ~ (x >>s 15) )
+ IRTemp vA_tmp =3D newTemp(Ity_V128);
+ IRTemp vB_tmp =3D newTemp(Ity_V128);
+ assign( vA_tmp, binop(Iop_AndV128, mkexpr(vA),
+ unop(Iop_NotV128,
+ binop(Iop_SarN16x8,
+ mkexpr(vA), mkU8(15)))) );
+ assign( vB_tmp, binop(Iop_AndV128, mkexpr(vB),
+ unop(Iop_NotV128,
+ binop(Iop_SarN16x8,
+ mkexpr(vB), mkU8(15)))) );
+ putVReg( vD_addr, binop(Iop_QNarrow16Ux8,
+ mkexpr(vA_tmp), mkexpr(vB_tmp)) );
+ // TODO: set VSCR[SAT]
+ return True;
+ }
+ case 0x14E: { // vpkswus (Pack Signed W Unsigned Saturate, AV p223)
DIP("vpkswus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
-
+ // This insn does a signed->unsigned saturating conversion.
+ // Conversion done here, then uses unsigned->unsigned vpk insn:
+ // =3D> UnsignedSaturatingNarrow( x & ~ (x >>s 31) )
+ IRTemp vA_tmp =3D newTemp(Ity_V128);
+ IRTemp vB_tmp =3D newTemp(Ity_V128);
+ assign( vA_tmp, binop(Iop_AndV128, mkexpr(vA),
+ unop(Iop_NotV128,
+ binop(Iop_SarN32x4,
+ mkexpr(vA), mkU8(31)))) );
+ assign( vB_tmp, binop(Iop_AndV128, mkexpr(vB),
+ unop(Iop_NotV128,
+ binop(Iop_SarN32x4,
+ mkexpr(vB), mkU8(31)))) );
+ putVReg( vD_addr, binop(Iop_QNarrow32Ux4,
+ mkexpr(vA_tmp), mkexpr(vB_tmp)) );
+ // TODO: set VSCR[SAT]
+ return True;
+ }
case 0x18E: // vpkshss (Pack Signed HW Signed Saturate, AV p220)
DIP("vpkshss v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_QNarrow16Sx8, mkexpr(vA), mkexpr(vB)) =
);
+ // TODO: set VSCR[SAT]
+ return True;
=20
case 0x1CE: // vpkswss (Pack Signed W Signed Saturate, AV p222)
DIP("vpkswss v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ putVReg( vD_addr, binop(Iop_QNarrow32Sx4, mkexpr(vA), mkexpr(vB)) =
);
+ // TODO: set VSCR[SAT]
+ return True;
=20
- case 0x30E: // vpkpx (Pack Pixel, AV p219)
+ case 0x30E: { // vpkpx (Pack Pixel, AV p219)
DIP("vpkpx v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
+ /* CAB: Worth a new primop? */
+ /* Using shifts to compact pixel elements, then packing them them =
*/
+ IRTemp a1 =3D newTemp(Ity_V128);
+ IRTemp a2 =3D newTemp(Ity_V128);
+ IRTemp a3 =3D newTemp(Ity_V128);
+ IRTemp a_tmp =3D newTemp(Ity_V128);
+ IRTemp b1 =3D newTemp(Ity_V128);
+ IRTemp b2 =3D newTemp(Ity_V128);
+ IRTemp b3 =3D newTemp(Ity_V128);
+ IRTemp b_tmp =3D newTemp(Ity_V128);
+ assign( a1, binop(Iop_ShlN16x8,
+ binop(Iop_ShrN32x4, mkexpr(vA), mkU8(19)),
+ mkU8(10)) );
+ assign( a2, binop(Iop_ShlN16x8,=20
+ binop(Iop_ShrN16x8, mkexpr(vA), mkU8(11)),
+ mkU8(5)) );
+ assign( a3, binop(Iop_ShrN16x8,=20
+ binop(Iop_ShlN16x8, mkexpr(vA), mkU8(8)),
+ mkU8(11)) );
+ assign( a_tmp, binop(Iop_OrV128, mkexpr(a1),
+ binop(Iop_OrV128, mkexpr(a2), mkexpr(a3))) );
=20
+ assign( b1, binop(Iop_ShlN16x8,
+ binop(Iop_ShrN32x4, mkexpr(vB), mkU8(19)),
+ mkU8(10)) );
+ assign( b2, binop(Iop_ShlN16x8,=20
+ binop(Iop_ShrN16x8, mkexpr(vB), mkU8(11)),
+ mkU8(5)) );
+ assign( b3, binop(Iop_ShrN16x8,=20
+ binop(Iop_ShlN16x8, mkexpr(vB), mkU8(8)),
+ mkU8(11)) );
+ assign( b_tmp, binop(Iop_OrV128, mkexpr(b1),
+ binop(Iop_OrV128, mkexpr(b2), mkexpr(b3))) );
+
+ putVReg( vD_addr, binop(Iop_Narrow32Ux4,
+ mkexpr(a_tmp), mkexpr(b_tmp)) );
+ return True;
+ }
+
default:
break; // Fall through...
}
@@ -5979,38 +6054,102 @@
return False;
}
=20
+
+ IRTemp signs =3D newTemp(Ity_V128);
+ IRTemp zeros =3D newTemp(Ity_V128);
+ assign( zeros, unop(Iop_Dup32x4, mkU32(0)) );
+
switch (opc2) {
/* Unpacking */
- case 0x20E: // vupkhsb (Unpack High Signed B, AV p277)
+ case 0x20E: { // vupkhsb (Unpack High Signed B, AV p277)
DIP("vupkhsb v%d,v%d\n", vD_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
-
- case 0x24E: // vupkhsh (Unpack High Signed HW, AV p278)
+ assign( signs, binop(Iop_CmpGT8Sx16, mkexpr(zeros), mkexpr(vB)) );
+ putVReg( vD_addr, binop(Iop_InterleaveHI8x16, mkexpr(signs), mkexp=
r(vB)) );
+ break;
+ }
+ case 0x24E: { // vupkhsh (Unpack High Signed HW, AV p278)
DIP("vupkhsh v%d,v%d\n", vD_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
-
- case 0x28E: // vupklsb (Unpack Low Signed B, AV p280)
+ assign( signs, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vB)) );
+ putVReg( vD_addr, binop(Iop_InterleaveHI16x8, mkexpr(signs), mkexp=
r(vB)) );
+ break;
+ }
+ case 0x28E: { // vupklsb (Unpack Low Signed B, AV p280)
DIP("vupklsb v%d,v%d\n", vD_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
-
- case 0x2CE: // vupklsh (Unpack Low Signed HW, AV p281)
+ assign( signs, binop(Iop_CmpGT8Sx16, mkexpr(zeros), mkexpr(vB)) );
+ putVReg( vD_addr, binop(Iop_InterleaveLO8x16, mkexpr(signs), mkexp=
r(vB)) );
+ break;
+ }
+ case 0x2CE: { // vupklsh (Unpack Low Signed HW, AV p281)
DIP("vupklsh v%d,v%d\n", vD_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
-
- case 0x34E: // vupkhpx (Unpack High Pixel16, AV p276)
+ assign( signs, binop(Iop_CmpGT16Sx8, mkexpr(zeros), mkexpr(vB)) );
+ putVReg( vD_addr, binop(Iop_InterleaveLO16x8, mkexpr(signs), mkexp=
r(vB)) );
+ break;
+ }
+ case 0x34E: { // vupkhpx (Unpack High Pixel16, AV p276)
DIP("vupkhpx v%d,v%d\n", vD_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
-
- case 0x3CE: // vupklpx (Unpack Low Pixel16, AV p279)
+ /* CAB: Worth a new primop? */
+ /* Using shifts to isolate pixel elements, then expanding them */
+ IRTemp z0 =3D newTemp(Ity_V128);
+ IRTemp z1 =3D newTemp(Ity_V128);
+ IRTemp z01 =3D newTemp(Ity_V128);
+ IRTemp z2 =3D newTemp(Ity_V128);
+ IRTemp z3 =3D newTemp(Ity_V128);
+ IRTemp z23 =3D newTemp(Ity_V128);
+ assign( z0, binop(Iop_ShlN16x8,
+ binop(Iop_SarN16x8, mkexpr(vB), mkU8(15)),
+ mkU8(8)) );
+ assign( z1, binop(Iop_ShrN16x8,=20
+ binop(Iop_ShlN16x8, mkexpr(vB), mkU8(1)),
+ mkU8(11)) );
+ assign( z01, binop(Iop_InterleaveHI16x8, mkexpr(zeros),
+ binop(Iop_OrV128, mkexpr(z0), mkexpr(z1))) );
+ assign( z2, binop(Iop_ShrN16x8,
+ binop(Iop_ShlN16x8,=20
+ binop(Iop_ShrN16x8, mkexpr(vB), mkU8(5)),
+ mkU8(11)),
+ mkU8(3)) );
+ assign( z3, binop(Iop_ShrN16x8,=20
+ binop(Iop_ShlN16x8, mkexpr(vB), mkU8(11)),
+ mkU8(11)) );
+ assign( z23, binop(Iop_InterleaveHI16x8, mkexpr(zeros),
+ binop(Iop_OrV128, mkexpr(z2), mkexpr(z3))) );
+ putVReg( vD_addr, binop(Iop_OrV128,
+ binop(Iop_ShlN32x4, mkexpr(z01), mkU8(16))=
,
+ mkexpr(z23)) );
+ break;
+ }
+ case 0x3CE: { // vupklpx (Unpack Low Pixel16, AV p279)
DIP("vupklpx v%d,v%d\n", vD_addr, vB_addr);
- DIP(" =3D> not implemented\n");
- return False;
-
+ /* identical to vupkhpx, except interleaving LO */
+ IRTemp z0 =3D newTemp(Ity_V128);
+ IRTemp z1 =3D newTemp(Ity_V128);
+ IRTemp z01 =3D newTemp(Ity_V128);
+ IRTemp z2 =3D newTemp(Ity_V128);
+ IRTemp z3 =3D newTemp(Ity_V128);
+ IRTemp z23 =3D newTemp(Ity_V128);
+ assign( z0, binop(Iop_ShlN16x8,
+ binop(Iop_SarN16x8, mkexpr(vB), mkU8(15)),
+ mkU8(8)) );
+ assign( z1, binop(Iop_ShrN16x8,=20
+ binop(Iop_ShlN16x8, mkexpr(vB), mkU8(1)),
+ mkU8(11)) );
+ assign( z01, binop(Iop_InterleaveLO16x8, mkexpr(zeros),
+ binop(Iop_OrV128, mkexpr(z0), mkexpr(z1))) );
+ assign( z2, binop(Iop_ShrN16x8,
+ binop(Iop_ShlN16x8,=20
+ binop(Iop_ShrN16x8, mkexpr(vB), mkU8(5)),
+ mkU8(11)),
+ mkU8(3)) );
+ assign( z3, binop(Iop_ShrN16x8,=20
+ binop(Iop_ShlN16x8, mkexpr(vB), mkU8(11)),
+ mkU8(11)) );
+ assign( z23, binop(Iop_InterleaveLO16x8, mkexpr(zeros),
+ binop(Iop_OrV128, mkexpr(z2), mkexpr(z3))) );
+ putVReg( vD_addr, binop(Iop_OrV128,
+ binop(Iop_ShlN32x4, mkexpr(z01), mkU8(16))=
,
+ mkexpr(z23)) );
+ break;
+ }
default:
vex_printf("dis_av_pack(PPC32)(opc2)\n");
return False;
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-09-15 21:58:50 UTC (rev 1399)
+++ trunk/priv/host-ppc32/isel.c 2005-09-16 07:13:44 UTC (rev 1400)
@@ -3282,24 +3282,6 @@
//.. case Iop_QNarrow16Ux8:=20
//.. op =3D Xsse_PACKUSW; arg1isEReg =3D True; goto do_SseReRg;
=20
-//.. case Iop_InterleaveHI8x16:=20
-//.. op =3D Xsse_UNPCKHB; arg1isEReg =3D True; goto do_SseReRg;
-//.. case Iop_InterleaveHI16x8:=20
-//.. op =3D Xsse_UNPCKHW; arg1isEReg =3D True; goto do_SseReRg;
-//.. case Iop_InterleaveHI32x4:=20
-//.. op =3D Xsse_UNPCKHD; arg1isEReg =3D True; goto do_SseReRg;
-//.. case Iop_InterleaveHI64x2:=20
-//.. op =3D Xsse_UNPCKHQ; arg1isEReg =3D True; goto do_SseReRg;
-
-//.. case Iop_InterleaveLO8x16:=20
-//.. op =3D Xsse_UNPCKLB; arg1isEReg =3D True; goto do_SseReRg;
-//.. case Iop_InterleaveLO16x8:=20
-//.. op =3D Xsse_UNPCKLW; arg1isEReg =3D True; goto do_SseReRg;
-//.. case Iop_InterleaveLO32x4:=20
-//.. op =3D Xsse_UNPCKLD; arg1isEReg =3D True; goto do_SseReRg;
-//.. case Iop_InterleaveLO64x2:=20
-//.. op =3D Xsse_UNPCKLQ; arg1isEReg =3D True; goto do_SseReRg;
-
case Iop_AndV128: op =3D Pav_AND; goto do_AvBin;
case Iop_OrV128: op =3D Pav_OR; goto do_AvBin;
case Iop_XorV128: op =3D Pav_XOR; goto do_AvBin;
@@ -3357,6 +3339,9 @@
return dst;
}
=20
+ case Iop_Narrow16Ux8: op =3D Pav_PACKUUM; goto do_AvBin16x8;
+ case Iop_QNarrow16Ux8: op =3D Pav_PACKUUS; goto do_AvBin16x8;
+ case Iop_QNarrow16Sx8: op =3D Pav_PACKSSS; goto do_AvBin16x8;
case Iop_InterleaveHI16x8: op =3D Pav_MRGHI; goto do_AvBin16x8;
case Iop_InterleaveLO16x8: op =3D Pav_MRGLO; goto do_AvBin16x8;
case Iop_Add16x8: op =3D Pav_ADDUM; goto do_AvBin16x8;
@@ -3386,6 +3371,9 @@
return dst;
}
=20
+ case Iop_Narrow32Ux4: op =3D Pav_PACKUUM; goto do_AvBin32x4;
+ case Iop_QNarrow32Ux4: op =3D Pav_PACKUUS; goto do_AvBin32x4;
+ case Iop_QNarrow32Sx4: op =3D Pav_PACKSSS; goto do_AvBin32x4;
case Iop_InterleaveHI32x4: op =3D Pav_MRGHI; goto do_AvBin32x4;
case Iop_InterleaveLO32x4: op =3D Pav_MRGLO; goto do_AvBin32x4;
case Iop_Add32x4: op =3D Pav_ADDUM; goto do_AvBin32x4;
@@ -3449,7 +3437,20 @@
return dst;
}
=20
+ case Iop_ShlN16x8: op =3D Pav_SHL; goto do_AvShift16x8;
+ case Iop_ShrN16x8: op =3D Pav_SHR; goto do_AvShift16x8;
+ case Iop_SarN16x8: op =3D Pav_SAR; goto do_AvShift16x8;
+ do_AvShift16x8: {
+ HReg r_src =3D iselVecExpr(env, e->Iex.Binop.arg1);
+ HReg dst =3D newVRegV(env);
+ HReg v_shft =3D mk_AvDuplicateRI(env, e->Iex.Binop.arg2);
+ addInstr(env, PPC32Instr_AvBin16x8(op, dst, r_src, v_shft));
+ return dst;
+ }
+
+ case Iop_ShlN32x4: op =3D Pav_SHL; goto do_AvShift32x4;
case Iop_ShrN32x4: op =3D Pav_SHR; goto do_AvShift32x4;
+ case Iop_SarN32x4: op =3D Pav_SAR; goto do_AvShift32x4;
do_AvShift32x4: {
HReg r_src =3D iselVecExpr(env, e->Iex.Binop.arg1);
HReg dst =3D newVRegV(env);
|
|
From: <sv...@va...> - 2005-09-16 04:16:20
|
Author: njn
Date: 2005-09-16 05:16:18 +0100 (Fri, 16 Sep 2005)
New Revision: 4669
Log:
Fixed "make distcheck", and VPATH builds, backported from main trunk, plu=
s=20
an additional change to fix the path to valt_load_address.lds. It's not
all working yet, but should be soon, hopefully.
Modified:
branches/ASPACEM/Makefile.tool.am
branches/ASPACEM/configure.in
branches/ASPACEM/docs/Makefile.am
branches/ASPACEM/docs/xml/Makefile.am
branches/ASPACEM/memcheck/tests/Makefile.am
Modified: branches/ASPACEM/Makefile.tool.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ASPACEM/Makefile.tool.am 2005-09-16 03:59:37 UTC (rev 4668)
+++ branches/ASPACEM/Makefile.tool.am 2005-09-16 04:16:18 UTC (rev 4669)
@@ -27,6 +27,6 @@
TOOL_LINKFLAGS =3D \
-static \
-Wl,-defsym,valt_load_address=3D@VALT_LOAD_ADDRESS@ \
- -Wl,-T,$(top_srcdir)/valt_load_address.lds \
+ -Wl,-T,$(top_builddir)/valt_load_address.lds \
-nodefaultlibs -nostartfiles -u _start
=20
Modified: branches/ASPACEM/configure.in
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ASPACEM/configure.in 2005-09-16 03:59:37 UTC (rev 4668)
+++ branches/ASPACEM/configure.in 2005-09-16 04:16:18 UTC (rev 4669)
@@ -20,7 +20,7 @@
[AC_MSG_ERROR([Directory '$withval' does not exist, or does not =
contain Vex])])
],
[
- VEX_DIR=3D`pwd`/VEX
+ VEX_DIR=3D'$(top_srcdir)/VEX'
])
AC_SUBST(VEX_DIR)
=20
Modified: branches/ASPACEM/docs/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ASPACEM/docs/Makefile.am 2005-09-16 03:59:37 UTC (rev 4668)
+++ branches/ASPACEM/docs/Makefile.am 2005-09-16 04:16:18 UTC (rev 4669)
@@ -24,13 +24,13 @@
##-------------------------------------------------------------------
## Below here is more ordinary make stuff...
##-------------------------------------------------------------------
-docdir =3D ./
-xmldir =3D $(docdir)xml
-imgdir =3D $(docdir)images
-libdir =3D $(docdir)lib
-htmldir =3D $(docdir)html
-printdir =3D $(docdir)print
+myxmldir =3D $(top_srcdir)/docs/xml
+myimgdir =3D $(top_srcdir)/docs/images
+mylibdir =3D $(top_srcdir)/docs/lib
=20
+myhtmldir =3D $(top_builddir)/docs/html
+myprintdir =3D $(top_builddir)/docs/print
+
XML_CATALOG_FILES =3D /etc/xml/catalog
=20
# file to log print output to
@@ -47,40 +47,40 @@
XSLTPROC_FLAGS =3D --nonet --xinclude=20
=20
# stylesheets
-XSL_HTML_CHUNK_STYLE =3D $(libdir)/vg-html-chunk.xsl
-XSL_HTML_SINGLE_STYLE =3D $(libdir)/vg-html-single.xsl
-XSL_FO_STYLE =3D $(libdir)/vg-fo.xsl
+XSL_HTML_CHUNK_STYLE =3D $(mylibdir)/vg-html-chunk.xsl
+XSL_HTML_SINGLE_STYLE =3D $(mylibdir)/vg-html-single.xsl
+XSL_FO_STYLE =3D $(mylibdir)/vg-fo.xsl
=20
all-docs: html-docs print-docs
=20
valid:
- $(XMLLINT) $(XMLLINT_FLAGS) $(xmldir)/index.xml
+ $(XMLLINT) $(XMLLINT_FLAGS) $(myxmldir)/index.xml
=20
# chunked html
html-docs:
@echo "Generating html files..."
export XML_CATALOG_FILES=3D$(XML_CATALOG_FILES) && \
- mkdir -p $(htmldir) && \
- /bin/rm -fr $(htmldir)/ && \
- mkdir -p $(htmldir)/ && \
- mkdir -p $(htmldir)/images && \
- cp $(libdir)/vg_basic.css $(htmldir)/ && \
- cp $(imgdir)/*.png $(htmldir)/images && \
- $(XSLTPROC) $(XSLTPROC_FLAGS) -o $(htmldir)/ $(XSL_HTML_CHUNK_STYLE) $(=
xmldir)/index.xml
+ mkdir -p $(myhtmldir) && \
+ /bin/rm -fr $(myhtmldir)/ && \
+ mkdir -p $(myhtmldir)/ && \
+ mkdir -p $(myhtmldir)/images && \
+ cp $(mylibdir)/vg_basic.css $(myhtmldir)/ && \
+ cp $(myimgdir)/*.png $(myhtmldir)/images && \
+ $(XSLTPROC) $(XSLTPROC_FLAGS) -o $(myhtmldir)/ $(XSL_HTML_CHUNK_STYLE) =
$(myxmldir)/index.xml
=20
# pdf and postscript
print-docs:
- @echo "Generating PDF file: $(printdir)/index.pdf (please be patient)..=
.";
+ @echo "Generating PDF file: $(myprintdir)/index.pdf (please be patient)=
...";
export XML_CATALOG_FILES=3D$(XML_CATALOG_FILES) && \
- mkdir -p $(printdir) && \
- mkdir -p $(printdir)/images && \
- cp $(imgdir)/massif-graph-sm.png $(printdir)/images && \
- $(XSLTPROC) $(XSLTPROC_FLAGS) -o $(printdir)/index.fo $(XSL_FO_STYLE) $=
(xmldir)/index.xml && \
- (cd $(printdir) && \
+ mkdir -p $(myprintdir) && \
+ mkdir -p $(myprintdir)/images && \
+ cp $(myimgdir)/massif-graph-sm.png $(myprintdir)/images && \
+ $(XSLTPROC) $(XSLTPROC_FLAGS) -o $(myprintdir)/index.fo $(XSL_FO_STYLE)=
$(myxmldir)/index.xml && \
+ (cd $(myprintdir) && \
( pdfxmltex index.fo && \
pdfxmltex index.fo && \
pdfxmltex index.fo ) &> $(LOGFILE) && \
- echo "Generating PS file: $(printdir)/index.ps ..." && \
+ echo "Generating PS file: $(myprintdir)/index.ps ..." && \
pdftops index.pdf && \
rm -f *.log *.aux *.fo *.out)
=20
Modified: branches/ASPACEM/docs/xml/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ASPACEM/docs/xml/Makefile.am 2005-09-16 03:59:37 UTC (rev 46=
68)
+++ branches/ASPACEM/docs/xml/Makefile.am 2005-09-16 04:16:18 UTC (rev 46=
69)
@@ -1,10 +1,11 @@
EXTRA_DIST =3D \
+ FAQ.xml \
+ dist-docs.xml \
index.xml \
- FAQ.xml \
+ licenses.xml \
manual.xml manual-intro.xml manual-core.xml \
+ quick-start-guide.xml \
writing-tools.xml \
- dist-docs.xml \
tech-docs.xml \
- licenses.xml \
vg-entities.xml \
xml_help.txt
Modified: branches/ASPACEM/memcheck/tests/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- branches/ASPACEM/memcheck/tests/Makefile.am 2005-09-16 03:59:37 UTC (=
rev 4668)
+++ branches/ASPACEM/memcheck/tests/Makefile.am 2005-09-16 04:16:18 UTC (=
rev 4669)
@@ -135,8 +135,8 @@
=20
# Valgrind unit self-tests
hello_LDFLAGS =3D -Wl,-defsym,valt_load_address=3D0x50000000 \
- -Wl,-T,$(top_srcdir)/valt_load_address.lds
-hello_DEPENDENCIES =3D $(top_srcdir)/valt_load_address.lds
+ -Wl,-T,$(top_builddir)/valt_load_address.lds
+hello_DEPENDENCIES =3D $(top_builddir)/valt_load_address.lds
=20
# vgtest_ume is not working
#vgtest_ume_CFLAGS =3D -DVGA_$(VG_ARCH) -DVGO_$(VG_OS)
|
|
From: <sv...@va...> - 2005-09-16 03:59:43
|
Author: njn
Date: 2005-09-16 04:59:37 +0100 (Fri, 16 Sep 2005)
New Revision: 4668
Log:
Make VPATH builds work again.
Modified:
trunk/configure.in
Modified: trunk/configure.in
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/configure.in 2005-09-15 09:31:45 UTC (rev 4667)
+++ trunk/configure.in 2005-09-16 03:59:37 UTC (rev 4668)
@@ -20,7 +20,7 @@
[AC_MSG_ERROR([Directory '$withval' does not exist, or does not =
contain Vex])])
],
[
- VEX_DIR=3D`pwd`/VEX
+ VEX_DIR=3D'$(top_srcdir)/VEX'
])
AC_SUBST(VEX_DIR)
=20
|
|
From: <js...@ac...> - 2005-09-16 02:57:22
|
Nightly build on phoenix ( SuSE 9.1 ) started at 2005-09-16 03:30:00 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 185 tests, 2 stderr failures, 0 stdout failures ================= none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: <js...@ac...> - 2005-09-16 02:44:57
|
Nightly build on g5 ( YDL 4.0, ppc970 ) started at 2005-09-16 04:40:00 CEST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 158 tests, 17 stderr failures, 1 stdout failure ================= memcheck/tests/badjump (stderr) memcheck/tests/badjump2 (stderr) memcheck/tests/fprw (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/sigaltstack (stderr) memcheck/tests/supp1 (stderr) memcheck/tests/supp_unknown (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) cachegrind/tests/chdir (stderr) cachegrind/tests/dlclose (stdout) cachegrind/tests/dlclose (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_cmsg (stderr) none/tests/fdleak_ipv4 (stderr) |
|
From: Tom H. <to...@co...> - 2005-09-16 02:41:13
|
Nightly build on dunsmere ( athlon, Fedora Core 4 ) started at 2005-09-16 03:30:05 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 187 tests, 5 stderr failures, 0 stdout failures ================= memcheck/tests/leak-tree (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-16 02:28:53
|
Nightly build on alvis ( i686, Red Hat 7.3 ) started at 2005-09-16 03:15:04 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 186 tests, 14 stderr failures, 0 stdout failures ================= memcheck/tests/addressable (stderr) memcheck/tests/describe-block (stderr) memcheck/tests/erringfds (stderr) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-cycle (stderr) memcheck/tests/leak-regroot (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/match-overrun (stderr) memcheck/tests/partiallydefinedeq (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigkill (stderr) memcheck/tests/stack_changes (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-16 02:25:28
|
Nightly build on ginetta ( i686, Red Hat 8.0 ) started at 2005-09-16 03:10:09 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 186 tests, 2 stderr failures, 0 stdout failures ================= none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-16 02:21:05
|
Nightly build on dellow ( x86_64, Fedora Core 4 ) started at 2005-09-16 03:10:09 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 164 tests, 6 stderr failures, 0 stdout failures ================= memcheck/tests/sigprocmask (stderr) memcheck/tests/strchr (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-16 02:19:05
|
Nightly build on aston ( x86_64, Fedora Core 3 ) started at 2005-09-16 03:05:05 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 164 tests, 6 stderr failures, 0 stdout failures ================= memcheck/tests/sigprocmask (stderr) memcheck/tests/strchr (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) |
|
From: Tom H. <th...@cy...> - 2005-09-16 02:13:34
|
Nightly build on gill ( x86_64, Fedora Core 2 ) started at 2005-09-16 03:00:04 BST Results unchanged from 24 hours ago Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 164 tests, 7 stderr failures, 0 stdout failures ================= memcheck/tests/sigprocmask (stderr) memcheck/tests/strchr (stderr) memcheck/tests/vgtest_ume (stderr) memcheck/tests/weirdioctl (stderr) memcheck/tests/xml1 (stderr) none/tests/faultstatus (stderr) none/tests/fdleak_fcntl (stderr) |