You can subscribe to this list here.
| 2002 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
(1) |
Oct
(122) |
Nov
(152) |
Dec
(69) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2003 |
Jan
(6) |
Feb
(25) |
Mar
(73) |
Apr
(82) |
May
(24) |
Jun
(25) |
Jul
(10) |
Aug
(11) |
Sep
(10) |
Oct
(54) |
Nov
(203) |
Dec
(182) |
| 2004 |
Jan
(307) |
Feb
(305) |
Mar
(430) |
Apr
(312) |
May
(187) |
Jun
(342) |
Jul
(487) |
Aug
(637) |
Sep
(336) |
Oct
(373) |
Nov
(441) |
Dec
(210) |
| 2005 |
Jan
(385) |
Feb
(480) |
Mar
(636) |
Apr
(544) |
May
(679) |
Jun
(625) |
Jul
(810) |
Aug
(838) |
Sep
(634) |
Oct
(521) |
Nov
(965) |
Dec
(543) |
| 2006 |
Jan
(494) |
Feb
(431) |
Mar
(546) |
Apr
(411) |
May
(406) |
Jun
(322) |
Jul
(256) |
Aug
(401) |
Sep
(345) |
Oct
(542) |
Nov
(308) |
Dec
(481) |
| 2007 |
Jan
(427) |
Feb
(326) |
Mar
(367) |
Apr
(255) |
May
(244) |
Jun
(204) |
Jul
(223) |
Aug
(231) |
Sep
(354) |
Oct
(374) |
Nov
(497) |
Dec
(362) |
| 2008 |
Jan
(322) |
Feb
(482) |
Mar
(658) |
Apr
(422) |
May
(476) |
Jun
(396) |
Jul
(455) |
Aug
(267) |
Sep
(280) |
Oct
(253) |
Nov
(232) |
Dec
(304) |
| 2009 |
Jan
(486) |
Feb
(470) |
Mar
(458) |
Apr
(423) |
May
(696) |
Jun
(461) |
Jul
(551) |
Aug
(575) |
Sep
(134) |
Oct
(110) |
Nov
(157) |
Dec
(102) |
| 2010 |
Jan
(226) |
Feb
(86) |
Mar
(147) |
Apr
(117) |
May
(107) |
Jun
(203) |
Jul
(193) |
Aug
(238) |
Sep
(300) |
Oct
(246) |
Nov
(23) |
Dec
(75) |
| 2011 |
Jan
(133) |
Feb
(195) |
Mar
(315) |
Apr
(200) |
May
(267) |
Jun
(293) |
Jul
(353) |
Aug
(237) |
Sep
(278) |
Oct
(611) |
Nov
(274) |
Dec
(260) |
| 2012 |
Jan
(303) |
Feb
(391) |
Mar
(417) |
Apr
(441) |
May
(488) |
Jun
(655) |
Jul
(590) |
Aug
(610) |
Sep
(526) |
Oct
(478) |
Nov
(359) |
Dec
(372) |
| 2013 |
Jan
(467) |
Feb
(226) |
Mar
(391) |
Apr
(281) |
May
(299) |
Jun
(252) |
Jul
(311) |
Aug
(352) |
Sep
(481) |
Oct
(571) |
Nov
(222) |
Dec
(231) |
| 2014 |
Jan
(185) |
Feb
(329) |
Mar
(245) |
Apr
(238) |
May
(281) |
Jun
(399) |
Jul
(382) |
Aug
(500) |
Sep
(579) |
Oct
(435) |
Nov
(487) |
Dec
(256) |
| 2015 |
Jan
(338) |
Feb
(357) |
Mar
(330) |
Apr
(294) |
May
(191) |
Jun
(108) |
Jul
(142) |
Aug
(261) |
Sep
(190) |
Oct
(54) |
Nov
(83) |
Dec
(22) |
| 2016 |
Jan
(49) |
Feb
(89) |
Mar
(33) |
Apr
(50) |
May
(27) |
Jun
(34) |
Jul
(53) |
Aug
(53) |
Sep
(98) |
Oct
(206) |
Nov
(93) |
Dec
(53) |
| 2017 |
Jan
(65) |
Feb
(82) |
Mar
(102) |
Apr
(86) |
May
(187) |
Jun
(67) |
Jul
(23) |
Aug
(93) |
Sep
(65) |
Oct
(45) |
Nov
(35) |
Dec
(17) |
| 2018 |
Jan
(26) |
Feb
(35) |
Mar
(38) |
Apr
(32) |
May
(8) |
Jun
(43) |
Jul
(27) |
Aug
(30) |
Sep
(43) |
Oct
(42) |
Nov
(38) |
Dec
(67) |
| 2019 |
Jan
(32) |
Feb
(37) |
Mar
(53) |
Apr
(64) |
May
(49) |
Jun
(18) |
Jul
(14) |
Aug
(53) |
Sep
(25) |
Oct
(30) |
Nov
(49) |
Dec
(31) |
| 2020 |
Jan
(87) |
Feb
(45) |
Mar
(37) |
Apr
(51) |
May
(99) |
Jun
(36) |
Jul
(11) |
Aug
(14) |
Sep
(20) |
Oct
(24) |
Nov
(40) |
Dec
(23) |
| 2021 |
Jan
(14) |
Feb
(53) |
Mar
(85) |
Apr
(15) |
May
(19) |
Jun
(3) |
Jul
(14) |
Aug
(1) |
Sep
(57) |
Oct
(73) |
Nov
(56) |
Dec
(22) |
| 2022 |
Jan
(3) |
Feb
(22) |
Mar
(6) |
Apr
(55) |
May
(46) |
Jun
(39) |
Jul
(15) |
Aug
(9) |
Sep
(11) |
Oct
(34) |
Nov
(20) |
Dec
(36) |
| 2023 |
Jan
(79) |
Feb
(41) |
Mar
(99) |
Apr
(169) |
May
(48) |
Jun
(16) |
Jul
(16) |
Aug
(57) |
Sep
(19) |
Oct
|
Nov
|
Dec
|
| S | M | T | W | T | F | S |
|---|---|---|---|---|---|---|
|
|
|
|
1
(21) |
2
(18) |
3
(19) |
4
(17) |
|
5
(6) |
6
(5) |
7
(9) |
8
(21) |
9
(16) |
10
(21) |
11
(22) |
|
12
(19) |
13
(19) |
14
(8) |
15
(16) |
16
(17) |
17
(16) |
18
(33) |
|
19
(33) |
20
(34) |
21
(32) |
22
(26) |
23
(23) |
24
(16) |
25
(21) |
|
26
(19) |
27
(7) |
28
(29) |
29
(27) |
30
(55) |
|
|
|
From: <sv...@va...> - 2005-06-28 23:42:06
|
Author: rjwalsh Date: 2005-06-29 00:41:57 +0100 (Wed, 29 Jun 2005) New Revision: 4047 Log: Update ignores. Modified: trunk/cachegrind/tests/ppc32/ trunk/memcheck/tests/ppc32/ trunk/none/tests/ppc32/ Property changes on: trunk/cachegrind/tests/ppc32 ___________________________________________________________________ Name: svn:ignore + Makefile.in Property changes on: trunk/memcheck/tests/ppc32 ___________________________________________________________________ Name: svn:ignore + Makefile.in Property changes on: trunk/none/tests/ppc32 ___________________________________________________________________ Name: svn:ignore + Makefile.in |
|
From: <sv...@va...> - 2005-06-28 22:39:07
|
Author: njn
Date: 2005-06-28 23:38:24 +0100 (Tue, 28 Jun 2005)
New Revision: 4046
Log:
Fix off-by-one error that was causing four leak-checking regression test
failures for me, and also fixes bug #106293 for me. Let's hope it has=20
the same effect for others.
Modified:
trunk/coregrind/m_aspacemgr/aspacemgr.c
Modified: trunk/coregrind/m_aspacemgr/aspacemgr.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_aspacemgr/aspacemgr.c 2005-06-28 22:14:53 UTC (rev =
4045)
+++ trunk/coregrind/m_aspacemgr/aspacemgr.c 2005-06-28 22:38:24 UTC (rev =
4046)
@@ -1163,15 +1163,14 @@
=20
for (i =3D 0; i < segments_used; i++) {
s =3D &segments[i];
- flags =3D s->flags & (SF_SHARED|SF_MMAP|SF_VALGRIND
- |SF_CORE|SF_STACK);
+ flags =3D s->flags & (SF_SHARED|SF_MMAP|SF_VALGRIND|SF_CORE|SF_STA=
CK);
if (flags !=3D SF_MMAP && flags !=3D SF_STACK)
continue;
if ((s->prot & (VKI_PROT_READ|VKI_PROT_WRITE))=20
!=3D (VKI_PROT_READ|VKI_PROT_WRITE))
continue;
if (!VG_(is_client_addr)(s->addr) ||
- !VG_(is_client_addr)(s->addr+s->len))
+ !VG_(is_client_addr)(s->addr+s->len-1))
continue;
=20
(*add_rootrange)(s->addr, s->len);
|
|
From: <sv...@va...> - 2005-06-28 22:14:56
|
Author: njn
Date: 2005-06-28 23:14:53 +0100 (Tue, 28 Jun 2005)
New Revision: 4045
Log:
Remove all the completely unused SF_* flags. I suspect some of the
remaining ones have no interesting effect, but I left them in.
Also simplify the signature for VG_(get_memory_from_mmap_for_client)().
Modified:
trunk/coregrind/m_aspacemgr/aspacemgr.c
trunk/coregrind/m_libcmman.c
trunk/coregrind/m_main.c
trunk/coregrind/m_mallocfree.c
trunk/coregrind/m_signals.c
trunk/coregrind/m_syswrap/syswrap-generic.c
trunk/coregrind/m_syswrap/syswrap-linux.c
trunk/coregrind/pub_core_aspacemgr.h
trunk/coregrind/pub_core_libcmman.h
Modified: trunk/coregrind/m_aspacemgr/aspacemgr.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_aspacemgr/aspacemgr.c 2005-06-28 19:44:10 UTC (rev =
4044)
+++ trunk/coregrind/m_aspacemgr/aspacemgr.c 2005-06-28 22:14:53 UTC (rev =
4045)
@@ -802,9 +802,6 @@
) {
s->seginfo =3D VG_(read_seg_symbols)(s->addr, s->len, s->offset=
,
s->filename);
- if (s->seginfo !=3D NULL) {
- s->flags |=3D SF_DYNLIB;
- }
} else if (flags & SF_MMAP) {
#if 0
const SegInfo *info;
@@ -1167,7 +1164,7 @@
for (i =3D 0; i < segments_used; i++) {
s =3D &segments[i];
flags =3D s->flags & (SF_SHARED|SF_MMAP|SF_VALGRIND
- |SF_CORE|SF_STACK|SF_DEVICE);
+ |SF_CORE|SF_STACK);
if (flags !=3D SF_MMAP && flags !=3D SF_STACK)
continue;
if ((s->prot & (VKI_PROT_READ|VKI_PROT_WRITE))=20
Modified: trunk/coregrind/m_libcmman.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_libcmman.c 2005-06-28 19:44:10 UTC (rev 4044)
+++ trunk/coregrind/m_libcmman.c 2005-06-28 22:14:53 UTC (rev 4045)
@@ -65,7 +65,6 @@
}
=20
sf_flags |=3D SF_MMAP;
- if ( flags & VKI_MAP_FIXED) sf_flags |=3D SF_FIXED;
if ( flags & VKI_MAP_SHARED) sf_flags |=3D SF_SHARED;
if (!(flags & VKI_MAP_ANONYMOUS)) sf_flags |=3D SF_FILE;
if (!(flags & VKI_MAP_CLIENT)) sf_flags |=3D SF_VALGRIND;
@@ -106,7 +105,7 @@
void* p;
p =3D VG_(mmap)(0, nBytes,
VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC,
- VKI_MAP_PRIVATE|VKI_MAP_ANONYMOUS, 0, -1, 0);
+ VKI_MAP_PRIVATE|VKI_MAP_ANONYMOUS, SF_VALGRIND, -1, 0);
=20
if (p !=3D ((void*)(-1))) {
vg_assert((void*)VG_(valgrind_base) <=3D p && p <=3D (void*)VG_(va=
lgrind_last));
@@ -131,17 +130,16 @@
}
=20
// Returns 0 on failure.
-Addr VG_(get_memory_from_mmap_for_client)
- (Addr addr, SizeT len, UInt prot, UInt sf_flags)
+Addr VG_(get_memory_from_mmap_for_client) (SizeT len)
{
+ Addr addr;
+
len =3D VG_PGROUNDUP(len);
=20
- tl_assert(!(sf_flags & SF_FIXED));
- tl_assert(0 =3D=3D addr);
-
- addr =3D (Addr)VG_(mmap)((void *)addr, len, prot,=20
- VKI_MAP_PRIVATE | VKI_MAP_ANONYMOUS | VKI_MAP_=
CLIENT,
- sf_flags | SF_CORE, -1, 0);
+ addr =3D (Addr)VG_(mmap)(NULL, len,=20
+ VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC,
+ VKI_MAP_PRIVATE|VKI_MAP_ANONYMOUS|VKI_MAP_CLIE=
NT,
+ SF_CORE, -1, 0);
if ((Addr)-1 !=3D addr)
return addr;
else
Modified: trunk/coregrind/m_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_main.c 2005-06-28 19:44:10 UTC (rev 4044)
+++ trunk/coregrind/m_main.c 2005-06-28 22:14:53 UTC (rev 4045)
@@ -2138,7 +2138,7 @@
if (is_stack_segment)
flags =3D SF_STACK | SF_GROWDOWN;
else
- flags =3D SF_EXEC|SF_MMAP;
+ flags =3D SF_MMAP;
=20
if (filename !=3D NULL)
flags |=3D SF_FILE;
Modified: trunk/coregrind/m_mallocfree.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_mallocfree.c 2005-06-28 19:44:10 UTC (rev 4044)
+++ trunk/coregrind/m_mallocfree.c 2005-06-28 22:14:53 UTC (rev 4045)
@@ -484,9 +484,7 @@
VG_MIN_MALLOC_SZB );
} else if (a->clientmem) {
// client allocation -- return 0 to client if it fails
- sb =3D (Superblock *)
- VG_(get_memory_from_mmap_for_client)
- (0, cszB, VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC, 0);
+ sb =3D (Superblock*)VG_(get_memory_from_mmap_for_client)(cszB);
if (NULL =3D=3D sb)
return 0;
} else {
Modified: trunk/coregrind/m_signals.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_signals.c 2005-06-28 19:44:10 UTC (rev 4044)
+++ trunk/coregrind/m_signals.c 2005-06-28 22:14:53 UTC (rev 4045)
@@ -926,7 +926,7 @@
/* If true, then this Segment may be mentioned in the core */
static Bool may_dump(const Segment *seg)
{
- return (seg->flags & (SF_DEVICE|SF_VALGRIND)) =3D=3D 0 && VG_(is_clie=
nt_addr)(seg->addr);
+ return (seg->flags & SF_VALGRIND) =3D=3D 0 && VG_(is_client_addr)(seg=
->addr);
}
=20
/* If true, then this Segment's contents will be in the core */
Modified: trunk/coregrind/m_syswrap/syswrap-generic.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syswrap-generic.c 2005-06-28 19:44:10 UTC (=
rev 4044)
+++ trunk/coregrind/m_syswrap/syswrap-generic.c 2005-06-28 22:14:53 UTC (=
rev 4045)
@@ -138,8 +138,6 @@
=20
flags =3D SF_MMAP;
=20
- if (mm_flags & VKI_MAP_FIXED)
- flags |=3D SF_FIXED;
if (!(mm_flags & VKI_MAP_PRIVATE))
flags |=3D SF_SHARED;
=20
@@ -826,7 +824,7 @@
} else if ((void*)-1 !=3D VG_(mmap)((void*)current, newaddr-cur=
rent,
VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC,
VKI_MAP_PRIVATE|VKI_MAP_ANONYMOUS|VKI_MAP_FIXED|VKI_MAP_C=
LIENT,
- SF_FIXED|SF_BRK, -1, 0))=20
+ 0, -1, 0))=20
{
ret =3D newbrk;
}
Modified: trunk/coregrind/m_syswrap/syswrap-linux.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syswrap-linux.c 2005-06-28 19:44:10 UTC (re=
v 4044)
+++ trunk/coregrind/m_syswrap/syswrap-linux.c 2005-06-28 22:14:53 UTC (re=
v 4045)
@@ -685,7 +685,7 @@
return;
}
=20
- VG_(map_segment)(addr, size, VKI_PROT_READ|VKI_PROT_WRITE, SF_FIXED);
+ VG_(map_segment)(addr, size, VKI_PROT_READ|VKI_PROT_WRITE, 0);
=20
VG_(pad_address_space)(0);
SET_STATUS_from_SysRes( VG_(do_syscall2)(SYSNO, ARG1, ARG2) );
Modified: trunk/coregrind/pub_core_aspacemgr.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/pub_core_aspacemgr.h 2005-06-28 19:44:10 UTC (rev 404=
4)
+++ trunk/coregrind/pub_core_aspacemgr.h 2005-06-28 22:14:53 UTC (rev 404=
5)
@@ -68,24 +68,18 @@
/* A Segment is mapped piece of client memory. This covers all kinds
of mapped memory (exe, brk, mmap, .so, shm, stack, etc)
=20
- We try to encode everything we know about a particular segment here.
+ We encode relevant info about each segment with these constants.
*/
-#define SF_FIXED (1 << 0) // client asked for MAP_FIXED
-#define SF_SHARED (1 << 1) // shared
-#define SF_SHM (1 << 2) // SYSV SHM (also SF_SHARED)
-#define SF_MMAP (1 << 3) // mmap memory
-#define SF_FILE (1 << 4) // mapping is backed by a file
-#define SF_STACK (1 << 5) // is a stack
-#define SF_GROWDOWN (1 << 6) // segment grows down
-#define SF_GROWUP (1 << 7) // segment grows up
-#define SF_EXEC (1 << 8) // segment created by exec
-#define SF_DYNLIB (1 << 9) // mapped from dynamic library
-#define SF_NOSYMS (1 << 10) // don't load syms, even if present
-#define SF_BRK (1 << 11) // brk segment
-#define SF_CORE (1 << 12) // allocated by core on behalf of the clie=
nt
-#define SF_VALGRIND (1 << 13) // a valgrind-internal mapping - not in cl=
ient
-#define SF_CODE (1 << 14) // segment contains cached code
-#define SF_DEVICE (1 << 15) // device mapping; avoid careless touching
+#define SF_SHARED (1 << 0) // shared
+#define SF_SHM (1 << 1) // SYSV SHM (also SF_SHARED)
+#define SF_MMAP (1 << 2) // mmap memory
+#define SF_FILE (1 << 3) // mapping is backed by a file
+#define SF_STACK (1 << 4) // is a stack
+#define SF_GROWDOWN (1 << 5) // segment grows down
+#define SF_NOSYMS (1 << 6) // don't load syms, even if present
+#define SF_CORE (1 << 7) // allocated by core on behalf of the clie=
nt
+#define SF_VALGRIND (1 << 8) // a valgrind-internal mapping - not in cl=
ient
+#define SF_CODE (1 << 9) // segment contains cached code
=20
typedef struct _Segment Segment;
=20
Modified: trunk/coregrind/pub_core_libcmman.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/pub_core_libcmman.h 2005-06-28 19:44:10 UTC (rev 4044=
)
+++ trunk/coregrind/pub_core_libcmman.h 2005-06-28 22:14:53 UTC (rev 4045=
)
@@ -43,8 +43,7 @@
extern Int VG_(munmap) ( void* start, SizeT length );
extern Int VG_(mprotect) ( void *start, SizeT length, UInt prot );
=20
-extern Addr VG_(get_memory_from_mmap_for_client)
- (Addr base, SizeT len, UInt prot, UInt flags);
+extern Addr VG_(get_memory_from_mmap_for_client)(SizeT len);
=20
#endif // __PUB_CORE_LIBCMMAN_H
=20
|
|
From: <sv...@va...> - 2005-06-28 21:07:04
|
Author: cerion
Date: 2005-06-28 22:07:02 +0100 (Tue, 28 Jun 2005)
New Revision: 1228
Log:
Implemented just enough of isel for an AltiVec store
- ls runs on g5 now, yay!
Modified:
trunk/priv/host-ppc32/isel.c
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-06-28 20:59:18 UTC (rev 1227)
+++ trunk/priv/host-ppc32/isel.c 2005-06-28 21:07:02 UTC (rev 1228)
@@ -54,12 +54,13 @@
GPR2 TOC pointer - not used
GPR3:12 Allocateable
GPR13 Thread-specific pointer - not used
- GPR14:30 Allocateable
+ GPR14:29 Allocateable
+ GPR30 AltiVec temp spill register
GPR31 GuestStatePointer
=20
Of Allocateable regs:
GPR3:12 Caller-saved regs
- GPR14:30 Callee-saved regs
+ GPR14:29 Callee-saved regs
=20
GPR3 [Return | Parameter] - carrying reg
GPR4:10 Parameter-carrying regs
@@ -218,12 +219,12 @@
return reg;
}
=20
-//.. static HReg newVRegV ( ISelEnv* env )
-//.. {
-//.. HReg reg =3D mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*=
/);
-//.. env->vreg_ctr++;
-//.. return reg;
-//.. }
+static HReg newVRegV ( ISelEnv* env )
+{
+ HReg reg =3D mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/);
+ env->vreg_ctr++;
+ return reg;
+}
=20
=20
/*---------------------------------------------------------*/
@@ -259,8 +260,8 @@
static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e );
static HReg iselFltExpr ( ISelEnv* env, IRExpr* e );
=20
-//.. static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e );
-//.. static HReg iselVecExpr ( ISelEnv* env, IRExpr* e );
+static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e );
+static HReg iselVecExpr ( ISelEnv* env, IRExpr* e );
=20
=20
/*---------------------------------------------------------*/
@@ -2768,61 +2769,42 @@
}
=20
=20
-//.. /*---------------------------------------------------------*/
-//.. /*--- ISEL: SIMD (Vector) expressions, 128 bit. ---*/
-//.. /*---------------------------------------------------------*/
-//..=20
-//.. static HReg iselVecExpr ( ISelEnv* env, IRExpr* e )
-//.. {
-//.. HReg r =3D iselVecExpr_wrk( env, e );
-//.. # if 0
-//.. vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
-//.. # endif
-//.. vassert(hregClass(r) =3D=3D HRcVec128);
-//.. vassert(hregIsVirtual(r));
-//.. return r;
-//.. }
-//..=20
-//..=20
-//.. /* DO NOT CALL THIS DIRECTLY */
-//.. static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
-//.. {
-//..=20
-/*
-//.. # define REQUIRE_SSE1 \
-//.. do { if (env->subarch =3D=3D VexSubArchX86_sse0) \
-//.. goto vec_fail; \
-//.. } while (0)
-//..=20
-//.. # define REQUIRE_SSE2 \
-//.. do { if (env->subarch =3D=3D VexSubArchX86_sse0 \
-//.. || env->subarch =3D=3D VexSubArchX86_sse1) \
-//.. goto vec_fail; \
-//.. } while (0)
-*/
+/*---------------------------------------------------------*/
+/*--- ISEL: SIMD (Vector) expressions, 128 bit. ---*/
+/*---------------------------------------------------------*/
+
+static HReg iselVecExpr ( ISelEnv* env, IRExpr* e )
+{
+ HReg r =3D iselVecExpr_wrk( env, e );
+# if 0
+ vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
+# endif
+ vassert(hregClass(r) =3D=3D HRcVec128);
+ vassert(hregIsVirtual(r));
+ return r;
+}
+
+/* DO NOT CALL THIS DIRECTLY */
+static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
+{
//.. Bool arg1isEReg =3D False;
-//.. X86SseOp op =3D Xsse_INVALID;
-//.. IRType ty =3D typeOfIRExpr(env->type_env,e);
-//.. vassert(e);
-//.. vassert(ty =3D=3D Ity_V128);
-//..=20
-//.. REQUIRE_SSE1;
-//..=20
-//.. if (e->tag =3D=3D Iex_Tmp) {
-//.. return lookupIRTemp(env, e->Iex.Tmp.tmp);
-//.. }
-//..=20
-//.. if (e->tag =3D=3D Iex_Get) {
-//.. HReg dst =3D newVRegV(env);
-//.. addInstr(env, X86Instr_SseLdSt(
-//.. True/*load*/,=20
-//.. dst,
-//.. X86AMode_IR(e->Iex.Get.offset, hregX86_EBP()=
)
-//.. )
-//.. );
-//.. return dst;
-//.. }
-//..=20
+ PPC32AvOp op =3D Pav_INVALID;
+ IRType ty =3D typeOfIRExpr(env->type_env,e);
+ vassert(e);
+ vassert(ty =3D=3D Ity_V128);
+
+ if (e->tag =3D=3D Iex_Tmp) {
+ return lookupIRTemp(env, e->Iex.Tmp.tmp);
+ }
+
+ if (e->tag =3D=3D Iex_Get) {
+ HReg dst =3D newVRegV(env);
+ addInstr(env,
+ PPC32Instr_AvLdSt( True/*load*/, 16, dst,
+ PPC32AMode_IR(e->Iex.Get.offset, Guest=
StatePtr)));
+ return dst;
+ }
+
//.. if (e->tag =3D=3D Iex_LDle) {
//.. HReg dst =3D newVRegV(env);
//.. X86AMode* am =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
@@ -3261,18 +3243,15 @@
//.. addInstr(env, X86Instr_SseCMov(Xcc_Z,r0,dst));
//.. return dst;
//.. }
-//..=20
-//.. vec_fail:
-//.. vex_printf("iselVecExpr (subarch =3D %s): can't reduce\n",
-//.. LibVEX_ppVexSubArch(env->subarch));
-//.. ppIRExpr(e);
-//.. vpanic("iselVecExpr_wrk");
-//..=20
-//.. # undef REQUIRE_SSE1
-//.. # undef REQUIRE_SSE2
-//.. }
=20
+ vec_fail:
+ vex_printf("iselVecExpr(ppc32) (subarch =3D %s): can't reduce\n",
+ LibVEX_ppVexSubArch(env->subarch));
+ ppIRExpr(e);
+ vpanic("iselVecExpr_wrk(ppc32)");
+}
=20
+
/*---------------------------------------------------------*/
/*--- ISEL: Statements ---*/
/*---------------------------------------------------------*/
@@ -3320,11 +3299,11 @@
//.. Xalu_MOV, X86RI_Reg(vHi), X86AMode_IR(4, =
rA)));
//.. return;
//.. }
-//.. if (tyd =3D=3D Ity_V128) {
-//.. HReg r =3D iselVecExpr(env, stmt->Ist.STle.data);
-//.. addInstr(env, X86Instr_SseLdSt(False/*store*/, r, am));
-//.. return;
-//.. }
+ if (tyd =3D=3D Ity_V128) {
+ HReg v_src =3D iselVecExpr(env, stmt->Ist.STle.data);
+ addInstr(env, PPC32Instr_AvLdSt(False/*store*/, 16, v_src, am_a=
ddr));
+ return;
+ }
break;
}
=20
|
|
From: <sv...@va...> - 2005-06-28 21:00:09
|
Author: cerion
Date: 2005-06-28 21:59:18 +0100 (Tue, 28 Jun 2005)
New Revision: 1227
Log:
Reshuffled host-ppc32 AltiVec integer insns
Added some AltiVec fp insns and CMov
Modified:
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/hdefs.h
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-06-28 18:06:23 UTC (rev 1226)
+++ trunk/priv/host-ppc32/hdefs.c 2005-06-28 20:59:18 UTC (rev 1227)
@@ -513,119 +513,77 @@
=20
HChar* showPPC32AvOp ( PPC32AvOp op ) {
switch (op) {
- /* mov */
- case Pav_MOV: return "vmr";
+
+ /* Unary */
+ case Pav_MOV: return "vmr"; /* Mov */
=20
- /* Bitwise */
- case Pav_AND: return "vand";
+ case Pav_AND: return "vand"; /* Bitwise */
case Pav_OR: return "vor";
case Pav_XOR: return "vxor";
case Pav_NOT: return "vnot";
=20
+ case Pav_UNPCKH8S: return "vupkhsb"; /* Unpack */
+ case Pav_UNPCKH16S: return "vupkhsh";
+ case Pav_UNPCKL8S: return "vupklsb";
+ case Pav_UNPCKL16S: return "vupklsh";
+ case Pav_UNPCKHPIX: return "vupkhpx";
+ case Pav_UNPCKLPIX: return "vupklpx";
+
/* Integer binary */
- case Pav_ADD8UM: return "vaddubm";
- case Pav_ADD16UM: return "vadduhm";
- case Pav_ADD32UM: return "vadduwm";
- case Pav_ADD8US: return "vaddubs";
- case Pav_ADD16US: return "vadduhs";
- case Pav_ADD32US: return "vadduws";
- case Pav_ADD8SS: return "vaddsbs";
- case Pav_ADD16SS: return "vaddshs";
- case Pav_ADD32SS: return "vaddsws";
+ case Pav_ADDUM: return "vaddu_m"; // b,h,w
+ case Pav_ADDUS: return "vaddu_s"; // b,h,w
+ case Pav_ADDSS: return "vadds_s"; // b,h,w
=20
- case Pav_SUB8UM: return "vsububm";
- case Pav_SUB16UM: return "vsubuhm";
- case Pav_SUB32UM: return "vsubuwm";
- case Pav_SUB8US: return "vsububs";
- case Pav_SUB16US: return "vsubuhs";
- case Pav_SUB32US: return "vsubuws";
- case Pav_SUB8SS: return "vsubsbs";
- case Pav_SUB16SS: return "vsubshs";
- case Pav_SUB32SS: return "vsubsws";
+ case Pav_SUBUM: return "vsubu_m"; // b,h,w
+ case Pav_SUBUS: return "vsubu_s"; // b,h,w
+ case Pav_SUBSS: return "vsubs_s"; // b,h,w
=20
- case Pav_OMUL8U: return "vmuloub";
- case Pav_OMUL16U: return "vmulouh";
- case Pav_OMUL8S: return "vmulosb";
- case Pav_OMUL16S: return "vmulosh";
- case Pav_EMUL8U: return "vmuleub";
- case Pav_EMUL16U: return "vmuleuh";
- case Pav_EMUL8S: return "vmulesb";
- case Pav_EMUL16S: return "vmulesh";
+ case Pav_OMULU: return "vmulou"; // b,h
+ case Pav_OMULS: return "vmulos"; // b,h
+ case Pav_EMULU: return "vmuleu"; // b,h
+ case Pav_EMULS: return "vmules"; // b,h
=20
- case Pav_AVG8U: return "vavgub";
- case Pav_AVG16U: return "vavguh";
- case Pav_AVG32U: return "vavguw";
- case Pav_AVG8S: return "vavgsb";
- case Pav_AVG16S: return "vavgsh";
- case Pav_AVG32S: return "vavgsw";
+ case Pav_AVGU: return "vavgu"; // b,h,w
+ case Pav_AVGS: return "vavgs"; // b,h,w
=20
- case Pav_MAX8U: return "vmaxub";
- case Pav_MAX16U: return "vmaxuh";
- case Pav_MAX32U: return "vmaxuw";
- case Pav_MAX8S: return "vmaxsb";
- case Pav_MAX16S: return "vmaxsh";
- case Pav_MAX32S: return "vmaxsw";
+ case Pav_MAXU: return "vmaxu"; // b,h,w
+ case Pav_MAXS: return "vmaxs"; // b,h,w
=20
- case Pav_MIN8U: return "vminub";
- case Pav_MIN16U: return "vminuh";
- case Pav_MIN32U: return "vminuw";
- case Pav_MIN8S: return "vminsb";
- case Pav_MIN16S: return "vminsh";
- case Pav_MIN32S: return "vminsw";
+ case Pav_MINU: return "vminu"; // b,h,w
+ case Pav_MINS: return "vmins"; // b,h,w
=20
/* Compare (always affects CR field 6) */
- case Pav_CMPEQ8U: return "vcmpequb";
- case Pav_CMPEQ16U: return "vcmpequh";
- case Pav_CMPEQ32U: return "vcmpequw";
- case Pav_CMPGT8U: return "vcmpgtub";
- case Pav_CMPGT16U: return "vcmpgtuh";
- case Pav_CMPGT32U: return "vcmpgtuw";
- case Pav_CMPGT8S: return "vcmpgtsb";
- case Pav_CMPGT16S: return "vcmpgtsh";
- case Pav_CMPGT32S: return "vcmpgtsw";
+ case Pav_CMPEQU: return "vcmpequ"; // b,h,w
+ case Pav_CMPGTU: return "vcmpgtu"; // b,h,w
+ case Pav_CMPGTS: return "vcmpgts"; // b,h,w
=20
/* Shift */
- case Pav_SHL8: return "vslb";
- case Pav_SHL16: return "vslh";
- case Pav_SHL32: return "vslw";
- case Pav_SHL128: return "vsl";
- case Pav_SHR8: return "vsrb";
- case Pav_SHR16: return "vsrh";
- case Pav_SHR32: return "vsrw";
- case Pav_SHR128: return "vsr";
- case Pav_SAR8: return "vsrab";
- case Pav_SAR16: return "vsrah";
- case Pav_SAR32: return "vsraw";
- case Pav_ROTL8: return "vrlb";
- case Pav_ROTL16: return "vrlh";
- case Pav_ROTL32: return "vrlw";
- =20
+ case Pav_SHL: return "vsl"; // ' ',b,h,w
+ case Pav_SHR: return "vsr"; // ' ',b,h,w
+ case Pav_SAR: return "vsra"; // b,h,w
+ case Pav_ROTL: return "vrl"; // b,h,w
+
/* Pack */
- case Pav_PACKU16UM: return "vpkuhum";
- case Pav_PACKU32UM: return "vpkuwum";
- case Pav_PACKU16US: return "vpkuhus";
- case Pav_PACKU32US: return "vpkuwus";
- case Pav_PACKS16US: return "vpkshus";
- case Pav_PACKS32US: return "vpkswus";
- case Pav_PACKS16SS: return "vpkshss";
- case Pav_PACKS32SS: return "vpkswss";
+ case Pav_PACKUUM: return "vpku_um"; // h,w
+ case Pav_PACKUUS: return "vpku_us"; // h,w
+ case Pav_PACKSUS: return "vpks_us"; // h,w
+ case Pav_PACKSSS: return "vpks_ss"; // h,w
case Pav_PACKPXL: return "vpkpx";
=20
- /* Unpack (srcL ignored) */
- case Pav_UNPCKH8S: return "vupkhsb";
- case Pav_UNPCKH16S: return "vupkhsh";
- case Pav_UNPCKL8S: return "vupklsb";
- case Pav_UNPCKL16S: return "vupklsh";
- case Pav_UNPCKHPIX: return "vupkhpx";
- case Pav_UNPCKLPIX: return "vupklpx";
- =20
/* Merge */
- case Pav_MRG8HI: return "vmrghb";
- case Pav_MRG16HI: return "vmrghh";
- case Pav_MRG32HI: return "vmrghw";
- case Pav_MRG8LO: return "vmrglb";
- case Pav_MRG16LO: return "vmrglh";
- case Pav_MRG32LO: return "vmrglw";
+ case Pav_MRGHI: return "vmrgh"; // b,h,w
+ case Pav_MRGLO: return "vmrgl"; // b,h,w
+
+
+ /* Floating Point Binary */
+ case Pav_ADDF: return "vaddfp";
+ case Pav_SUBF: return "vsubfp";
+ case Pav_MULF: return "vmaddfp";
+ case Pav_MAXF: return "vmaxfp";
+ case Pav_MINF: return "vminfp";
+ case Pav_CMPEQF: return "vcmpeqfp";
+ case Pav_CMPGTF: return "vcmpgtfp";
+ case Pav_CMPGEF: return "vcmpgefp";
=20
default: vpanic("showPPC32AvOp");
}
@@ -873,6 +831,42 @@
i->Pin.AvBinary.srcR =3D srcR;
return i;
}
+PPC32Instr* PPC32Instr_AvBin8x16 ( PPC32AvOp op, HReg dst, HReg srcL, HR=
eg srcR ) {
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvBin8x16;
+ i->Pin.AvBin8x16.op =3D op;
+ i->Pin.AvBin8x16.dst =3D dst;
+ i->Pin.AvBin8x16.srcL =3D srcL;
+ i->Pin.AvBin8x16.srcR =3D srcR;
+ return i;
+}
+PPC32Instr* PPC32Instr_AvBin16x8 ( PPC32AvOp op, HReg dst, HReg srcL, HR=
eg srcR ) {
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvBin16x8;
+ i->Pin.AvBin16x8.op =3D op;
+ i->Pin.AvBin16x8.dst =3D dst;
+ i->Pin.AvBin16x8.srcL =3D srcL;
+ i->Pin.AvBin16x8.srcR =3D srcR;
+ return i;
+}
+PPC32Instr* PPC32Instr_AvBin32x4 ( PPC32AvOp op, HReg dst, HReg srcL, HR=
eg srcR ) {
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvBin32x4;
+ i->Pin.AvBin32x4.op =3D op;
+ i->Pin.AvBin32x4.dst =3D dst;
+ i->Pin.AvBin32x4.srcL =3D srcL;
+ i->Pin.AvBin32x4.srcR =3D srcR;
+ return i;
+}
+PPC32Instr* PPC32Instr_AvBin32Fx4 ( PPC32AvOp op, HReg dst, HReg srcL, H=
Reg srcR ) {
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvBin32Fx4;
+ i->Pin.AvBin32Fx4.op =3D op;
+ i->Pin.AvBin32Fx4.dst =3D dst;
+ i->Pin.AvBin32Fx4.srcL =3D srcL;
+ i->Pin.AvBin32Fx4.srcR =3D srcR;
+ return i;
+}
PPC32Instr* PPC32Instr_AvPerm ( HReg ctl, HReg dst, HReg srcL, HReg srcR=
) {
PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
i->tag =3D Pin_AvPerm;
@@ -908,6 +902,15 @@
i->Pin.AvSplat.src =3D src;
return i;
}
+PPC32Instr* PPC32Instr_AvCMov ( PPC32CondCode cond, HReg dst, HReg src )=
{
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvCMov;
+ i->Pin.AvCMov.cond =3D cond;
+ i->Pin.AvCMov.dst =3D dst;
+ i->Pin.AvCMov.src =3D src;
+ vassert(cond.test !=3D Pct_ALWAYS);
+ return i;
+}
PPC32Instr* PPC32Instr_AvLdVSCR ( HReg src ) {
PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
i->tag =3D Pin_AvLdVSCR;
@@ -1258,6 +1261,38 @@
vex_printf(",");
ppHRegPPC32(i->Pin.AvBinary.srcR);
return;
+ case Pin_AvBin8x16:
+ vex_printf("%s(b) ", showPPC32AvOp(i->Pin.AvBin8x16.op));
+ ppHRegPPC32(i->Pin.AvBin8x16.dst);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvBin8x16.srcL);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvBin8x16.srcR);
+ return;
+ case Pin_AvBin16x8:
+ vex_printf("%s(h) ", showPPC32AvOp(i->Pin.AvBin16x8.op));
+ ppHRegPPC32(i->Pin.AvBin16x8.dst);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvBin16x8.srcL);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvBin16x8.srcR);
+ return;
+ case Pin_AvBin32x4:
+ vex_printf("%s(w) ", showPPC32AvOp(i->Pin.AvBin32x4.op));
+ ppHRegPPC32(i->Pin.AvBin32x4.dst);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvBin32x4.srcL);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvBin32x4.srcR);
+ return;
+ case Pin_AvBin32Fx4:
+ vex_printf("%s ", showPPC32AvOp(i->Pin.AvBin32Fx4.op));
+ ppHRegPPC32(i->Pin.AvBin32Fx4.dst);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvBin32Fx4.srcL);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvBin32Fx4.srcR);
+ return;
case Pin_AvPerm:
vex_printf("vperm ");
ppHRegPPC32(i->Pin.AvPerm.dst);
@@ -1306,6 +1341,25 @@
return;
}
=20
+ case Pin_AvCMov:
+ vex_printf("avcmov (%s) ", showPPC32CondCode(i->Pin.AvCMov.cond));
+ ppHRegPPC32(i->Pin.AvCMov.dst);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvCMov.src);
+ vex_printf(": ");
+ vex_printf("if (v_dst !=3D v_src) { ");
+ if (i->Pin.AvCMov.cond.test !=3D Pct_ALWAYS) {
+ vex_printf("if (%%crf0.%s) { ", showPPC32CondCode(i->Pin.AvCMov=
.cond));
+ }
+ vex_printf("vmr ");
+ ppHRegPPC32(i->Pin.AvCMov.dst);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvCMov.src);
+ if (i->Pin.FpCMov.cond.test !=3D Pct_ALWAYS)
+ vex_printf(" }");
+ vex_printf(" }");
+ return;
+
case Pin_AvLdVSCR:
vex_printf("mtvscr ");
ppHRegPPC32(i->Pin.AvLdVSCR.src);
@@ -1482,6 +1536,28 @@
addHRegUse(u, HRmRead, i->Pin.AvBinary.srcL);
addHRegUse(u, HRmRead, i->Pin.AvBinary.srcR);
return;
+ case Pin_AvBin8x16:
+ addHRegUse(u, HRmWrite, i->Pin.AvBin8x16.dst);
+ addHRegUse(u, HRmRead, i->Pin.AvBin8x16.srcL);
+ addHRegUse(u, HRmRead, i->Pin.AvBin8x16.srcR);
+ return;
+ case Pin_AvBin16x8:
+ addHRegUse(u, HRmWrite, i->Pin.AvBin16x8.dst);
+ addHRegUse(u, HRmRead, i->Pin.AvBin16x8.srcL);
+ addHRegUse(u, HRmRead, i->Pin.AvBin16x8.srcR);
+ return;
+ case Pin_AvBin32x4:
+ addHRegUse(u, HRmWrite, i->Pin.AvBin32x4.dst);
+ addHRegUse(u, HRmRead, i->Pin.AvBin32x4.srcL);
+ addHRegUse(u, HRmRead, i->Pin.AvBin32x4.srcR);
+ if (i->Pin.AvBin32x4.op =3D=3D Pav_MULF)
+ addHRegUse(u, HRmWrite, hregPPC32_GPR29());
+ return;
+ case Pin_AvBin32Fx4:
+ addHRegUse(u, HRmWrite, i->Pin.AvBin32Fx4.dst);
+ addHRegUse(u, HRmRead, i->Pin.AvBin32Fx4.srcL);
+ addHRegUse(u, HRmRead, i->Pin.AvBin32Fx4.srcR);
+ return;
case Pin_AvPerm:
addHRegUse(u, HRmWrite, i->Pin.AvPerm.dst);
addHRegUse(u, HRmRead, i->Pin.AvPerm.ctl);
@@ -1503,6 +1579,10 @@
addHRegUse(u, HRmWrite, i->Pin.AvSplat.dst);
addRegUsage_PPC32RI(u, i->Pin.AvSplat.src);
return;
+ case Pin_AvCMov:
+ addHRegUse(u, HRmModify, i->Pin.AvCMov.dst);
+ addHRegUse(u, HRmRead, i->Pin.AvCMov.src);
+ return;
case Pin_AvLdVSCR:
addHRegUse(u, HRmRead, i->Pin.AvLdVSCR.src);
return;
@@ -1629,6 +1709,26 @@
mapReg(m, &i->Pin.AvBinary.srcL);
mapReg(m, &i->Pin.AvBinary.srcR);
return;
+ case Pin_AvBin8x16:
+ mapReg(m, &i->Pin.AvBin8x16.dst);
+ mapReg(m, &i->Pin.AvBin8x16.srcL);
+ mapReg(m, &i->Pin.AvBin8x16.srcR);
+ return;
+ case Pin_AvBin16x8:
+ mapReg(m, &i->Pin.AvBin16x8.dst);
+ mapReg(m, &i->Pin.AvBin16x8.srcL);
+ mapReg(m, &i->Pin.AvBin16x8.srcR);
+ return;
+ case Pin_AvBin32x4:
+ mapReg(m, &i->Pin.AvBin32x4.dst);
+ mapReg(m, &i->Pin.AvBin32x4.srcL);
+ mapReg(m, &i->Pin.AvBin32x4.srcR);
+ return;
+ case Pin_AvBin32Fx4:
+ mapReg(m, &i->Pin.AvBin32Fx4.dst);
+ mapReg(m, &i->Pin.AvBin32Fx4.srcL);
+ mapReg(m, &i->Pin.AvBin32Fx4.srcR);
+ return;
case Pin_AvPerm:
mapReg(m, &i->Pin.AvPerm.dst);
mapReg(m, &i->Pin.AvPerm.srcL);
@@ -1650,6 +1750,10 @@
mapReg(m, &i->Pin.AvSplat.dst);
mapRegs_PPC32RI(m, i->Pin.AvSplat.src);
return;
+ case Pin_AvCMov:
+ mapReg(m, &i->Pin.AvCMov.dst);
+ mapReg(m, &i->Pin.AvCMov.src);
+ return;
case Pin_AvLdVSCR:
mapReg(m, &i->Pin.AvLdVSCR.src);
return;
@@ -1997,10 +2101,24 @@
vassert(r2 < 0x20);
vassert(r3 < 0x20);
vassert(opc2 < 0x800);
- theInstr =3D ((opc1<<26) | (r1<<21) | (r2<<16) | (r3<<11) | (opc2<<1)=
);
+ theInstr =3D ((opc1<<26) | (r1<<21) | (r2<<16) | (r3<<11) | opc2);
return emit32(p, theInstr);
}
=20
+static UChar* mkFormVXR ( UChar* p, UInt opc1, UInt r1, UInt r2, UInt Rc=
,
+ UInt r3, UInt opc2 )
+{
+ UInt theInstr;
+ vassert(opc1 < 0x40);
+ vassert(r1 < 0x20);
+ vassert(r2 < 0x20);
+ vassert(r3 < 0x20);
+ vassert(Rc < 0x2);
+ vassert(opc2 < 0x400);
+ theInstr =3D ((opc1<<26) | (r1<<21) | (r2<<16) | (r3<<11) | (Rc<<10) =
| opc2);
+ return emit32(p, theInstr);
+}
+
static UChar* mkFormVA ( UChar* p, UInt opc1, UInt r1, UInt r2,
UInt r3, UInt r4, UInt opc2 )
{
@@ -2669,108 +2787,107 @@
case Pav_OR: opc2 =3D 1156; break; // vor
case Pav_XOR: opc2 =3D 1120; break; // vxor
=20
- /* Add */
- case Pav_ADD8UM: opc2 =3D 0; break; // vaddubm
- case Pav_ADD16UM: opc2 =3D 64; break; // vadduhm
- case Pav_ADD32UM: opc2 =3D 128; break; // vadduwm
- case Pav_ADD8US: opc2 =3D 512; break; // vaddubs
- case Pav_ADD16US: opc2 =3D 576; break; // vadduhs
- case Pav_ADD32US: opc2 =3D 640; break; // vadduws
- case Pav_ADD8SS: opc2 =3D 768; break; // vaddsbs
- case Pav_ADD16SS: opc2 =3D 832; break; // vaddshs
- case Pav_ADD32SS: opc2 =3D 896; break; // vaddsws
+ /* Shift */
+ case Pav_SHL: opc2 =3D 452; break; // vsl
+ case Pav_SHR: opc2 =3D 708; break; // vsr
=20
- /* Subtract */
- case Pav_SUB8UM: opc2 =3D 1024; break; // vsububm
- case Pav_SUB16UM: opc2 =3D 1088; break; // vsubuhm
- case Pav_SUB32UM: opc2 =3D 1152; break; // vsubuwm
- case Pav_SUB8US: opc2 =3D 1536; break; // vsububs
- case Pav_SUB16US: opc2 =3D 1600; break; // vsubuhs
- case Pav_SUB32US: opc2 =3D 1664; break; // vsubuws
- case Pav_SUB8SS: opc2 =3D 1792; break; // vsubsbs
- case Pav_SUB16SS: opc2 =3D 1856; break; // vsubshs
- case Pav_SUB32SS: opc2 =3D 1920; break; // vsubsws
+ default:
+ goto bad;
+ }
+ p =3D mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2 );
+ goto done;
+ }
=20
- /* Multiply odd/even */
- case Pav_OMUL8U: opc2 =3D 8; break; // vmuloub
- case Pav_OMUL16U: opc2 =3D 72; break; // vmulouh
- case Pav_OMUL8S: opc2 =3D 264; break; // vmulosb
- case Pav_OMUL16S: opc2 =3D 328; break; // vmulosh
- case Pav_EMUL8U: opc2 =3D 520; break; // vmuleub
- case Pav_EMUL16U: opc2 =3D 584; break; // vmuleuh
- case Pav_EMUL8S: opc2 =3D 776; break; // vmulesb
- case Pav_EMUL16S: opc2 =3D 840; break; // vmulesh
+ case Pin_AvBin8x16: {
+ UInt v_dst =3D vregNo(i->Pin.AvBin8x16.dst);
+ UInt v_srcL =3D vregNo(i->Pin.AvBin8x16.srcL);
+ UInt v_srcR =3D vregNo(i->Pin.AvBin8x16.srcR);
+ UInt opc2;
+ switch (i->Pin.AvBin8x16.op) {
=20
- /* Average */
- case Pav_AVG8U: opc2 =3D 1026; break; // vavgub
- case Pav_AVG16U: opc2 =3D 1090; break; // vavguh
- case Pav_AVG32U: opc2 =3D 1154; break; // vavguw
- case Pav_AVG8S: opc2 =3D 1282; break; // vavgsb
- case Pav_AVG16S: opc2 =3D 1346; break; // vavgsh
- case Pav_AVG32S: opc2 =3D 1410; break; // vavgsw
+ case Pav_ADDUM: opc2 =3D 0; break; // vaddubm
+ case Pav_ADDUS: opc2 =3D 512; break; // vaddubs
+ case Pav_ADDSS: opc2 =3D 768; break; // vaddsbs
=20
- /* Maximum */
- case Pav_MAX8U: opc2 =3D 2; break; // vmaxub
- case Pav_MAX16U: opc2 =3D 66; break; // vmaxuh
- case Pav_MAX32U: opc2 =3D 130; break; // vmaxuw
- case Pav_MAX8S: opc2 =3D 258; break; // vmaxsb
- case Pav_MAX16S: opc2 =3D 322; break; // vmaxsh
- case Pav_MAX32S: opc2 =3D 386; break; // vmaxsw
+ case Pav_SUBUM: opc2 =3D 1024; break; // vsububm
+ case Pav_SUBUS: opc2 =3D 1536; break; // vsububs
+ case Pav_SUBSS: opc2 =3D 1792; break; // vsubsbs
=20
- /* Minimum */
- case Pav_MIN8U: opc2 =3D 514; break; // vminub
- case Pav_MIN16U: opc2 =3D 578; break; // vminuh
- case Pav_MIN32U: opc2 =3D 642; break; // vminuw
- case Pav_MIN8S: opc2 =3D 770; break; // vminsb
- case Pav_MIN16S: opc2 =3D 834; break; // vminsh
- case Pav_MIN32S: opc2 =3D 898; break; // vminsw
+ case Pav_OMULU: opc2 =3D 8; break; // vmuloub
+ case Pav_OMULS: opc2 =3D 264; break; // vmulosb
+ case Pav_EMULU: opc2 =3D 520; break; // vmuleub
+ case Pav_EMULS: opc2 =3D 776; break; // vmulesb
=20
- /* Compare (always affects CR field 6) */
- /* XXX: Actually VXR-Form, but Rc always 0, so keep life easy... *=
/
- case Pav_CMPEQ8U: opc2 =3D 6; break; // vcmpequb
- case Pav_CMPEQ16U: opc2 =3D 70; break; // vcmpequh
- case Pav_CMPEQ32U: opc2 =3D 134; break; // vcmpequw
- case Pav_CMPGT8U: opc2 =3D 518; break; // vcmpgtub
- case Pav_CMPGT16U: opc2 =3D 582; break; // vcmpgtuh
- case Pav_CMPGT32U: opc2 =3D 646; break; // vcmpgtuw
- case Pav_CMPGT8S: opc2 =3D 774; break; // vcmpgtsb
- case Pav_CMPGT16S: opc2 =3D 838; break; // vcmpgtsh
- case Pav_CMPGT32S: opc2 =3D 902; break; // vcmpgtsw
+ case Pav_AVGU: opc2 =3D 1026; break; // vavgub
+ case Pav_AVGS: opc2 =3D 1282; break; // vavgsb
+ case Pav_MAXU: opc2 =3D 2; break; // vmaxub
+ case Pav_MAXS: opc2 =3D 258; break; // vmaxsb
+ case Pav_MINU: opc2 =3D 514; break; // vminub
+ case Pav_MINS: opc2 =3D 770; break; // vminsb
=20
- /* Shift */
- case Pav_SHL8: opc2 =3D 260; break; // vslb
- case Pav_SHL16: opc2 =3D 324; break; // vslh
- case Pav_SHL32: opc2 =3D 388; break; // vslw
- case Pav_SHL128: opc2 =3D 452; break; // vsl
- case Pav_SHR8: opc2 =3D 516; break; // vsrb
- case Pav_SHR16: opc2 =3D 580; break; // vsrh
- case Pav_SHR32: opc2 =3D 644; break; // vsrw
- case Pav_SHR128: opc2 =3D 708; break; // vsr
- case Pav_SAR8: opc2 =3D 772; break; // vsrab
- case Pav_SAR16: opc2 =3D 836; break; // vsrah
- case Pav_SAR32: opc2 =3D 900; break; // vsraw
- case Pav_ROTL8: opc2 =3D 4; break; // vrlb
- case Pav_ROTL16: opc2 =3D 68; break; // vrlh
- case Pav_ROTL32: opc2 =3D 132; break; // vrlw
+ case Pav_CMPEQU: opc2 =3D 6; break; // vcmpequb
+ case Pav_CMPGTU: opc2 =3D 518; break; // vcmpgtub
+ case Pav_CMPGTS: opc2 =3D 774; break; // vcmpgtsb
=20
- /* Pack */
- case Pav_PACKU16UM: opc2 =3D 14; break; // vpkuhum
- case Pav_PACKU32UM: opc2 =3D 78; break; // vpkuwum
- case Pav_PACKU16US: opc2 =3D 142; break; // vpkuhus
- case Pav_PACKU32US: opc2 =3D 206; break; // vpkuwus
- case Pav_PACKS16US: opc2 =3D 270; break; // vpkshus
- case Pav_PACKS32US: opc2 =3D 334; break; // vpkswus
- case Pav_PACKS16SS: opc2 =3D 398; break; // vpkshss
- case Pav_PACKS32SS: opc2 =3D 462; break; // vpkswss
+ case Pav_SHL: opc2 =3D 260; break; // vslb
+ case Pav_SHR: opc2 =3D 516; break; // vsrb
+ case Pav_SAR: opc2 =3D 772; break; // vsrab
+ case Pav_ROTL: opc2 =3D 4; break; // vrlb
+
+ case Pav_MRGHI: opc2 =3D 12; break; // vmrghb
+ case Pav_MRGLO: opc2 =3D 268; break; // vmrglb
+
+ default:
+ goto bad;
+ }
+ p =3D mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2 );
+ goto done;
+ }
+
+ case Pin_AvBin16x8: {
+ UInt v_dst =3D vregNo(i->Pin.AvBin16x8.dst);
+ UInt v_srcL =3D vregNo(i->Pin.AvBin16x8.srcL);
+ UInt v_srcR =3D vregNo(i->Pin.AvBin16x8.srcR);
+ UInt opc2;
+ switch (i->Pin.AvBin16x8.op) {
+
+ case Pav_ADDUM: opc2 =3D 64; break; // vadduhm
+ case Pav_ADDUS: opc2 =3D 576; break; // vadduhs
+ case Pav_ADDSS: opc2 =3D 832; break; // vaddshs
+
+ case Pav_SUBUM: opc2 =3D 1088; break; // vsubuhm
+ case Pav_SUBUS: opc2 =3D 1600; break; // vsubuhs
+ case Pav_SUBSS: opc2 =3D 1856; break; // vsubshs
+
+ case Pav_OMULU: opc2 =3D 72; break; // vmulouh
+ case Pav_OMULS: opc2 =3D 328; break; // vmulosh
+ case Pav_EMULU: opc2 =3D 584; break; // vmuleuh
+ case Pav_EMULS: opc2 =3D 840; break; // vmulesh
+
+ case Pav_AVGU: opc2 =3D 1090; break; // vavguh
+ case Pav_AVGS: opc2 =3D 1346; break; // vavgsh
+ case Pav_MAXU: opc2 =3D 66; break; // vmaxuh
+ case Pav_MAXS: opc2 =3D 322; break; // vmaxsh
+ case Pav_MINS: opc2 =3D 834; break; // vminsh
+ case Pav_MINU: opc2 =3D 578; break; // vminuh
+
+ case Pav_CMPEQU: opc2 =3D 70; break; // vcmpequh
+ case Pav_CMPGTU: opc2 =3D 582; break; // vcmpgtuh
+ case Pav_CMPGTS: opc2 =3D 838; break; // vcmpgtsh
+
+ case Pav_SHL: opc2 =3D 324; break; // vslh
+ case Pav_SHR: opc2 =3D 580; break; // vsrh
+ case Pav_SAR: opc2 =3D 836; break; // vsrah
+ case Pav_ROTL: opc2 =3D 68; break; // vrlh
+
+ case Pav_PACKUUM: opc2 =3D 14; break; // vpkuhum
+ case Pav_PACKUUS: opc2 =3D 142; break; // vpkuhus
+ case Pav_PACKSUS: opc2 =3D 270; break; // vpkshus
+ case Pav_PACKSSS: opc2 =3D 398; break; // vpkshss
case Pav_PACKPXL: opc2 =3D 782; break; // vpkpx
=20
- /* Merge */
- case Pav_MRG8HI: opc2 =3D 12; break; // vmrghb
- case Pav_MRG16HI: opc2 =3D 76; break; // vmrghh
- case Pav_MRG32HI: opc2 =3D 140; break; // vmrghw
- case Pav_MRG8LO: opc2 =3D 268; break; // vmrglb
- case Pav_MRG16LO: opc2 =3D 332; break; // vmrglh
- case Pav_MRG32LO: opc2 =3D 396; break; // vmrglw
+ case Pav_MRGHI: opc2 =3D 76; break; // vmrghh
+ case Pav_MRGLO: opc2 =3D 332; break; // vmrglh
=20
default:
goto bad;
@@ -2779,6 +2896,108 @@
goto done;
}
=20
+ case Pin_AvBin32x4: {
+ UInt v_dst =3D vregNo(i->Pin.AvBin32x4.dst);
+ UInt v_srcL =3D vregNo(i->Pin.AvBin32x4.srcL);
+ UInt v_srcR =3D vregNo(i->Pin.AvBin32x4.srcR);
+ UInt opc2;
+ switch (i->Pin.AvBin32x4.op) {
+
+ case Pav_ADDUM: opc2 =3D 128; break; // vadduwm
+ case Pav_ADDUS: opc2 =3D 640; break; // vadduws
+ case Pav_ADDSS: opc2 =3D 896; break; // vaddsws
+
+ case Pav_SUBUM: opc2 =3D 1152; break; // vsubuwm
+ case Pav_SUBUS: opc2 =3D 1664; break; // vsubuws
+ case Pav_SUBSS: opc2 =3D 1920; break; // vsubsws
+
+ case Pav_AVGU: opc2 =3D 1154; break; // vavguw
+ case Pav_AVGS: opc2 =3D 1410; break; // vavgsw
+
+ case Pav_MAXU: opc2 =3D 130; break; // vmaxuw
+ case Pav_MAXS: opc2 =3D 386; break; // vmaxsw
+
+ case Pav_MINS: opc2 =3D 898; break; // vminsw
+ case Pav_MINU: opc2 =3D 642; break; // vminuw
+
+ case Pav_CMPEQU: opc2 =3D 134; break; // vcmpequw
+ case Pav_CMPGTS: opc2 =3D 902; break; // vcmpgtsw
+ case Pav_CMPGTU: opc2 =3D 646; break; // vcmpgtuw
+
+ case Pav_SHL: opc2 =3D 388; break; // vslw
+ case Pav_SHR: opc2 =3D 644; break; // vsrw
+ case Pav_SAR: opc2 =3D 900; break; // vsraw
+ case Pav_ROTL: opc2 =3D 132; break; // vrlw
+
+ case Pav_PACKUUM: opc2 =3D 78; break; // vpkuwum
+ case Pav_PACKUUS: opc2 =3D 206; break; // vpkuwus
+ case Pav_PACKSUS: opc2 =3D 334; break; // vpkswus
+ case Pav_PACKSSS: opc2 =3D 462; break; // vpkswss
+
+ case Pav_MRGHI: opc2 =3D 140; break; // vmrghw
+ case Pav_MRGLO: opc2 =3D 396; break; // vmrglw
+
+ default:
+ goto bad;
+ }
+ p =3D mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2 );
+ goto done;
+ }
+
+ case Pin_AvBin32Fx4: {
+ UInt v_dst =3D vregNo(i->Pin.AvBin32Fx4.dst);
+ UInt v_srcL =3D vregNo(i->Pin.AvBin32Fx4.srcL);
+ UInt v_srcR =3D vregNo(i->Pin.AvBin32Fx4.srcR);
+ switch (i->Pin.AvBin32Fx4.op) {
+
+ case Pav_ADDF:
+ p =3D mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 10 ); // vaddfp
+ break;
+ case Pav_SUBF:
+ p =3D mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 74 ); // vsubfp
+ break;
+ case Pav_MAXF:
+ p =3D mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1034 ); // vmaxfp
+ break;
+ case Pav_MINF:
+ p =3D mkFormVX( p, 4, v_dst, v_srcL, v_srcR, 1098 ); // vminfp
+ break;
+
+ case Pav_MULF: {
+ /* Make a vmulfp from a vmaddfp:
+ load -0.0 (0x8000_0000) to each 32-bit word of vB
+ this makes the add a noop.
+ */
+ UInt vB =3D 29; // XXX: Using r29 for temp
+ UInt zero_simm =3D 0x80000000;
+
+ // Better way to load zero_imm?
+ // vspltisw vB,0x1F (0x1F =3D> each word of vB)
+ p =3D mkFormVX( p, 4, vB, zero_simm, 0, 908 );
+
+ // vslw vB,vB,vB (each word of vB =3D (0x1F << 0x1F) =3D 0x800=
00000
+ p =3D mkFormVX( p, 4, vB, vB, vB, 388 );
+
+ // Finally, do the multiply:
+ p =3D mkFormVA( p, 4, v_dst, v_srcL, vB, v_srcR, 46 );
+ break;
+ }
+ case Pav_CMPEQF:
+ p =3D mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 0, 198 ); // vcmp=
eqfp
+ break;
+ case Pav_CMPGTF:
+ p =3D mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 1, 710 ); // vcmp=
gtfp
+ break;
+ case Pav_CMPGEF:
+ p =3D mkFormVXR( p, 4, v_dst, v_srcL, v_srcR, 1, 454 ); // vcmp=
gefp
+ break;
+
+ default:
+ goto bad;
+ }
+ goto done;
+ }
+
case Pin_AvPerm: { // vperm
UInt v_ctl =3D vregNo(i->Pin.AvPerm.ctl);
UInt v_dst =3D vregNo(i->Pin.AvPerm.dst);
@@ -2814,7 +3033,7 @@
vassert(sz =3D=3D 8 || sz =3D=3D 16 || sz =3D=3D 32);
=20
if (i->Pin.AvSplat.src->tag =3D=3D Pri_Imm) {
- opc2 =3D (sz =3D=3D 8) ? 780 : (sz =3D=3D 16) ? 844 : 908; // 8,16,32
+ opc2 =3D (sz =3D=3D 8) ? 780 : (sz =3D=3D 16) ? 844 : 908; //=
8,16,32
simm_src =3D i->Pin.AvSplat.src->Pri.Imm.imm32;
p =3D mkFormVX( p, 4, v_dst, simm_src, 0, opc2 );
} else { // Pri_Reg
@@ -2825,6 +3044,25 @@
goto done;
}
=20
+ case Pin_AvCMov: {
+ UInt v_dst =3D vregNo(i->Pin.AvCMov.dst);
+ UInt v_src =3D vregNo(i->Pin.AvCMov.src);
+ PPC32CondCode cc =3D i->Pin.AvCMov.cond;
+
+ if (v_dst =3D=3D v_src) goto done;
+ =20
+ vassert(cc.test !=3D Pct_ALWAYS);
+
+ /* jmp fwds 2 insns if !condition */
+ if (cc.test !=3D Pct_ALWAYS) {
+ /* bc !ct,cf,n_bytes>>2 */
+ p =3D mkFormB(p, invertCondTest(cc.test), cc.flag, 8>>2, 0, 0);
+ }
+ /* vmr */
+ p =3D mkFormVX( p, 4, v_dst, v_src, v_src, 1156 );
+ goto done;
+ }
+
case Pin_AvLdVSCR: { // mtvscr
UInt v_src =3D vregNo(i->Pin.AvLdVSCR.src);
p =3D mkFormVX( p, 4, 0, 0, v_src, 1604 );
Modified: trunk/priv/host-ppc32/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.h 2005-06-28 18:06:23 UTC (rev 1226)
+++ trunk/priv/host-ppc32/hdefs.h 2005-06-28 20:59:18 UTC (rev 1227)
@@ -340,52 +340,34 @@
/* Integer Binary */
Pav_AND, Pav_OR, Pav_XOR, /* Bitwise */
=20
- Pav_ADD8UM, Pav_ADD16UM, Pav_ADD32UM,
- Pav_ADD8US, Pav_ADD16US, Pav_ADD32US,
- Pav_ADD8SS, Pav_ADD16SS, Pav_ADD32SS,
+ Pav_ADDUM, Pav_ADDUS,Pav_ADDSS,
=20
- Pav_SUB8UM, Pav_SUB16UM, Pav_SUB32UM,
- Pav_SUB8US, Pav_SUB16US, Pav_SUB32US,
- Pav_SUB8SS, Pav_SUB16SS, Pav_SUB32SS,
+ Pav_SUBUM, Pav_SUBUS, Pav_SUBSS,
=20
- Pav_OMUL8U, Pav_OMUL16U,
- Pav_OMUL8S, Pav_OMUL16S,
- Pav_EMUL8U, Pav_EMUL16U,
- Pav_EMUL8S, Pav_EMUL16S,
+ Pav_OMULU, Pav_OMULS, Pav_EMULU, Pav_EMULS,
=20
- Pav_AVG8U, Pav_AVG16U, Pav_AVG32U,
- Pav_AVG8S, Pav_AVG16S, Pav_AVG32S,
- Pav_MAX8U, Pav_MAX16U, Pav_MAX32U,
- Pav_MAX8S, Pav_MAX16S, Pav_MAX32S,
- Pav_MIN8U, Pav_MIN16U, Pav_MIN32U,
- Pav_MIN8S, Pav_MIN16S, Pav_MIN32S,
+ Pav_AVGU, Pav_AVGS,
+ Pav_MAXU, Pav_MAXS,
+ Pav_MINU, Pav_MINS,
=20
/* Compare (always affects CR field 6) */
- Pav_CMPEQ8U, Pav_CMPEQ16U, Pav_CMPEQ32U,
- Pav_CMPGT8U, Pav_CMPGT16U, Pav_CMPGT32U,
- Pav_CMPGT8S, Pav_CMPGT16S, Pav_CMPGT32S,
+ Pav_CMPEQU, Pav_CMPGTU, Pav_CMPGTS,
=20
/* Shift */
- Pav_SHL8, Pav_SHL16, Pav_SHL32, Pav_SHL128,
- Pav_SHR8, Pav_SHR16, Pav_SHR32, Pav_SHR128,
- Pav_SAR8, Pav_SAR16, Pav_SAR32,
- Pav_ROTL8, Pav_ROTL16, Pav_ROTL32,
+ Pav_SHL, Pav_SHR, Pav_SAR, Pav_ROTL,
=20
/* Pack */
- Pav_PACKU16UM, Pav_PACKU32UM,
- Pav_PACKU16US, Pav_PACKU32US,
- Pav_PACKS16US, Pav_PACKS32US,
- Pav_PACKS16SS, Pav_PACKS32SS, Pav_PACKPXL,
+ Pav_PACKUUM, Pav_PACKUUS, Pav_PACKSUS, Pav_PACKSSS,
+ Pav_PACKPXL,
=20
/* Merge */
- Pav_MRG8HI, Pav_MRG16HI, Pav_MRG32HI,
- Pav_MRG8LO, Pav_MRG16LO, Pav_MRG32LO,
+ Pav_MRGHI, Pav_MRGLO,
=20
-//.. /* Floating point binary */
-//.. Xsse_ADDF, Xsse_SUBF, Xsse_MULF, Xsse_DIVF,
-//.. Xsse_MAXF, Xsse_MINF,
-//.. Xsse_CMPEQF, Xsse_CMPLTF, Xsse_CMPLEF, Xsse_CMPUNF,
-//..=20
+ /* Floating point binary */
+ Pav_ADDF, Pav_SUBF, Pav_MULF,
+ Pav_MAXF, Pav_MINF,
+ Pav_CMPEQF, Pav_CMPGTF, Pav_CMPGEF,
+
//.. /* Floating point unary */
//.. Xsse_RCPF, Xsse_RSQRTF, Xsse_SQRTF,
}
@@ -425,20 +407,20 @@
// Pin_AvConst, /* Generate restricted AV literal */
Pin_AvLdSt, /* AV load/store (kludging for AMode_IR) */
Pin_AvUnary, /* AV unary general reg=3D>reg */
+
Pin_AvBinary, /* AV binary general reg,reg=3D>reg */
+ Pin_AvBin8x16, /* AV binary, 8x4 */
+ Pin_AvBin16x8, /* AV binary, 16x4 */
+ Pin_AvBin32x4, /* AV binary, 32x4 */
=20
+ Pin_AvBin32Fx4, /* AV FP binary, 32Fx4 */
+
Pin_AvPerm, /* AV permute (shuffle) */
Pin_AvSel, /* AV select */
Pin_AvShlDbl, /* AV shift-left double by imm */
Pin_AvSplat, /* One elem repeated throughout dst */
- Pin_AvLdVSCR /* mtvscr */
-
-//.. Xin_SseLdzLO, /* SSE load low 32/64 bits, zero remainder of =
reg */
-//.. Xin_Sse32Fx4, /* SSE binary, 32Fx4 */
-//.. Xin_Sse32FLo, /* SSE binary, 32F in lowest lane only */
-//.. Xin_Sse64Fx2, /* SSE binary, 64Fx2 */
-//.. Xin_Sse64FLo, /* SSE binary, 64F in lowest lane only */
-//.. Xin_SseCMov, /* SSE conditional move */
+ Pin_AvLdVSCR, /* mtvscr */
+ Pin_AvCMov /* AV conditional move */
}
PPC32InstrTag;
=20
@@ -612,6 +594,30 @@
HReg srcL;
HReg srcR;
} AvBinary;
+ struct {
+ PPC32AvOp op;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ } AvBin8x16;
+ struct {
+ PPC32AvOp op;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ } AvBin16x8;
+ struct {
+ PPC32AvOp op;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ } AvBin32x4;
+ struct {
+ PPC32AvOp op;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ } AvBin32Fx4;
/* Perm,Sel,SlDbl,Splat are all weird AV permutations */
struct {
HReg ctl;
@@ -636,6 +642,13 @@
HReg dst;
PPC32RI* src;
} AvSplat;
+ /* Mov src to dst on the given condition, which may not
+ be the bogus Xcc_ALWAYS. */
+ struct {
+ PPC32CondCode cond;
+ HReg dst;
+ HReg src;
+ } AvCMov;
/* Load AlitVec Status & Control Register */
struct {
HReg src;
@@ -675,10 +688,15 @@
extern PPC32Instr* PPC32Instr_AvLdSt ( Bool isLoad, UChar sz, HReg, =
PPC32AMode* );
extern PPC32Instr* PPC32Instr_AvUnary ( PPC32FpOp op, HReg dst, HReg =
src );
extern PPC32Instr* PPC32Instr_AvBinary ( PPC32FpOp op, HReg dst, HReg =
srcL, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvBin8x16 ( PPC32FpOp op, HReg dst, HReg =
srcL, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvBin16x8 ( PPC32FpOp op, HReg dst, HReg =
srcL, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvBin32x4 ( PPC32FpOp op, HReg dst, HReg =
srcL, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvBin32Fx4 ( PPC32FpOp op, HReg dst, HReg =
srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvPerm ( HReg ctl, HReg dst, HReg srcL=
, HReg srcR );
extern PPC32Instr* PPC32Instr_AvSel ( HReg ctl, HReg dst, HReg srcL=
, HReg srcR );
extern PPC32Instr* PPC32Instr_AvShlDbl ( UChar shift, HReg dst, HReg s=
rcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvSplat ( UChar sz, HReg dst, PPC32RI* =
src );
+extern PPC32Instr* PPC32Instr_AvCMov ( PPC32CondCode, HReg dst, HReg=
src );
extern PPC32Instr* PPC32Instr_AvLdVSCR ( HReg src );
=20
extern void ppPPC32Instr ( PPC32Instr* );
|
|
From: Nicholas N. <nj...@cs...> - 2005-06-28 19:47:26
|
SVN commit 429765 by nethercote:
Don't use non-ansi features in valgrind.h in case it's used in a file =
=20
compiled with -ansi. Added a regtest for it. Fixed bug #103182. =20
MERGED FROM 3.0 REPOSITORY
M +4 -4 valgrind.h.in =20
--- trunk/valgrind/include/valgrind.h.in #429764:429765
@@ -61,7 +61,7 @@
#include <stdarg.h>
=20
#undef __@VG_ARCH@__
-#define __@VG_ARCH@__ 1 // Architecture we're installed on
+#define __@VG_ARCH@__ 1 /* Architecture we're installed on */
=20
=20
/* If we're not compiling for our target architecture, don't generate
@@ -119,7 +119,7 @@
_zzq_args[2] =3D (unsigned int)(_zzq_arg2); \
_zzq_args[3] =3D (unsigned int)(_zzq_arg3); \
_zzq_args[4] =3D (unsigned int)(_zzq_arg4); \
- asm volatile("roll $29, %%eax ; roll $3, %%eax\n\t" \
+ __asm__ volatile("roll $29, %%eax ; roll $3, %%eax\n\t" \
"rorl $27, %%eax ; rorl $5, %%eax\n\t" \
"roll $13, %%eax ; roll $19, %%eax" \
: "=3Dd" (_zzq_rlval) \
@@ -127,9 +127,9 @@
: "cc", "memory" \
); \
}
-#endif // __x86__
+#endif /* __x86__ */
=20
-// Insert assembly code for other architectures here...
+/* Insert assembly code for other architectures here... */
=20
#else /* NVALGRIND */
/* Define NVALGRIND to completely remove the Valgrind magic sequence
|
|
From: <sv...@va...> - 2005-06-28 19:44:13
|
Author: njn
Date: 2005-06-28 20:44:10 +0100 (Tue, 28 Jun 2005)
New Revision: 4044
Log:
Don't use non-ansi features in valgrind.h in case it's used in a file
compiled with -ansi. Added a regtest for it. Fixed bug #103182.
Added:
trunk/none/tests/ansi.c
trunk/none/tests/ansi.stderr.exp
trunk/none/tests/ansi.vgtest
Modified:
trunk/include/valgrind.h
trunk/none/tests/Makefile.am
Modified: trunk/include/valgrind.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/include/valgrind.h 2005-06-28 19:20:46 UTC (rev 4043)
+++ trunk/include/valgrind.h 2005-06-28 19:44:10 UTC (rev 4044)
@@ -74,6 +74,10 @@
=20
#include <stdarg.h>
=20
+/* Nb: this file might be included in a file compiled with -ansi. So
+ we can't use C++ style "//" comments nor the "asm" keyword (instead
+ use "__asm__"). */
+
/* If we're not compiling for our target architecture, don't generate
any inline asms. Note that in this file we're using the compiler's
CPP symbols for identifying architectures, which are different to
@@ -132,15 +136,15 @@
_zzq_args[2] =3D (volatile unsigned long long)(_zzq_arg2); \
_zzq_args[3] =3D (volatile unsigned long long)(_zzq_arg3); \
_zzq_args[4] =3D (volatile unsigned long long)(_zzq_arg4); \
- asm volatile("roll $29, %%eax ; roll $3, %%eax\n\t" \
- "rorl $27, %%eax ; rorl $5, %%eax\n\t" \
- "roll $13, %%eax ; roll $19, %%eax" \
- : "=3Dd" (_zzq_rlval) \
- : "a" (&_zzq_args[0]), "0" (_zzq_default) \
- : "cc", "memory" \
- ); \
+ __asm__ volatile("roll $29, %%eax ; roll $3, %%eax\n\t" \
+ "rorl $27, %%eax ; rorl $5, %%eax\n\t" \
+ "roll $13, %%eax ; roll $19, %%eax" \
+ : "=3Dd" (_zzq_rlval) \
+ : "a" (&_zzq_args[0]), "0" (_zzq_default) \
+ : "cc", "memory" \
+ ); \
}
-#endif // __x86_64__
+#endif /* __x86_64__ */
=20
#ifdef __i386__
#define VALGRIND_MAGIC_SEQUENCE( \
@@ -153,18 +157,18 @@
_zzq_args[2] =3D (unsigned int)(_zzq_arg2); \
_zzq_args[3] =3D (unsigned int)(_zzq_arg3); \
_zzq_args[4] =3D (unsigned int)(_zzq_arg4); \
- asm volatile("roll $29, %%eax ; roll $3, %%eax\n\t" \
- "rorl $27, %%eax ; rorl $5, %%eax\n\t" \
- "roll $13, %%eax ; roll $19, %%eax" \
- : "=3Dd" (_zzq_rlval) \
- : "a" (&_zzq_args[0]), "0" (_zzq_default) \
- : "cc", "memory" \
- ); \
+ __asm__ volatile("roll $29, %%eax ; roll $3, %%eax\n\t" \
+ "rorl $27, %%eax ; rorl $5, %%eax\n\t" \
+ "roll $13, %%eax ; roll $19, %%eax" \
+ : "=3Dd" (_zzq_rlval) \
+ : "a" (&_zzq_args[0]), "0" (_zzq_default) \
+ : "cc", "memory" \
+ ); \
}
-#endif // __i386__
+#endif /* __i386__ */
=20
#ifdef __arm__
-// XXX: temporary, until MAGIC_SEQUENCE is written properly
+/* XXX: temporary, until MAGIC_SEQUENCE is written properly */
extern int printf (__const char *__restrict __format, ...);
extern void exit (int __status);
#define VALGRIND_MAGIC_SEQUENCE( =
\
@@ -179,11 +183,11 @@
_zzq_args[4] =3D (volatile unsigned int)(_zzq_arg4); =
\
(_zzq_rlval) =3D (_zzq_default);/* temporary only */ \
printf("argh: MAGIC_SEQUENCE"); exit(1); \
- asm volatile(""); =
\
+ __asm__ volatile(""); =
\
}
-// XXX: make sure that the register holding the args and the register ta=
king
-// the return value match what the scheduler is expecting.
-#endif // __arm__
+/* XXX: make sure that the register holding the args and the register ta=
king
+ * the return value match what the scheduler is expecting. */
+#endif /* __arm__ */
=20
#ifdef __powerpc__
#define VALGRIND_MAGIC_SEQUENCE( =
\
@@ -199,20 +203,20 @@
_zzq_args[3] =3D (volatile unsigned int)(_zzq_arg3); =
\
_zzq_args[4] =3D (volatile unsigned int)(_zzq_arg4); =
\
_zzq_ptr =3D _zzq_args; =
\
- asm volatile("tw 0,3,27\n\t" =
\
- "rlwinm 0,0,29,0,0\n\t" =
\
- "rlwinm 0,0,3,0,0\n\t" =
\
- "rlwinm 0,0,13,0,0\n\t" =
\
- "rlwinm 0,0,19,0,0\n\t" =
\
- "nop\n\t" =
\
- : "=3Dr" (_zzq_tmp) =
\
- : "0" (_zzq_default), "r" (_zzq_ptr) =
\
- : "memory"); =
\
+ __asm__ volatile("tw 0,3,27\n\t" =
\
+ "rlwinm 0,0,29,0,0\n\t" =
\
+ "rlwinm 0,0,3,0,0\n\t" =
\
+ "rlwinm 0,0,13,0,0\n\t" =
\
+ "rlwinm 0,0,19,0,0\n\t" =
\
+ "nop\n\t" =
\
+ : "=3Dr" (_zzq_tmp) =
\
+ : "0" (_zzq_default), "r" (_zzq_ptr) =
\
+ : "memory"); =
\
_zzq_rlval =3D (__typeof__(_zzq_rlval)) _zzq_tmp; =
\
}
-#endif // __powerpc__
+#endif /* __powerpc__ */
=20
-// Insert assembly code for other architectures here...
+/* Insert assembly code for other architectures here... */
=20
#endif /* NVALGRIND */
=20
@@ -229,8 +233,8 @@
start at 0x2000.
*/
=20
-// These macros are used by tools -- they must be public, but don't embe=
d them
-// into other programs.
+/* These macros are used by tools -- they must be public, but don't embe=
d them
+ * into other programs. */
#define VG_USERREQ_TOOL_BASE(a,b) \
((unsigned int)(((a)&0xff) << 24 | ((b)&0xff) << 16))
#define VG_IS_TOOL_USERREQ(a, b, v) \
Modified: trunk/none/tests/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/Makefile.am 2005-06-28 19:20:46 UTC (rev 4043)
+++ trunk/none/tests/Makefile.am 2005-06-28 19:44:10 UTC (rev 4044)
@@ -4,6 +4,7 @@
noinst_SCRIPTS =3D filter_none_discards filter_stderr
=20
EXTRA_DIST =3D $(noinst_SCRIPTS) \
+ ansi.stderr.exp ansi.vgtest \
args.stderr.exp args.stdout.exp args.vgtest \
async-sigs.stderr.exp async-sigs.stdout.exp async-sigs.vgtest \
bitfield1.stderr.exp bitfield1.vgtest \
@@ -65,7 +66,7 @@
yield.stderr.exp yield.stdout.exp yield.vgtest
=20
check_PROGRAMS =3D \
- args async-sigs bitfield1 blockfault closeall coolo_strlen \
+ ansi args async-sigs bitfield1 blockfault closeall coolo_strlen \
discard exec-sigmask execve faultstatus fcntl_setown floored fork \
fucomip \
manythreads \
@@ -84,6 +85,8 @@
AM_CXXFLAGS =3D $(AM_CFLAGS)
=20
# generic C ones
+ansi_SOURCES =3D ansi.c
+ansi_CFLAGS =3D -ansi
args_SOURCES =3D args.c
async_sigs_SOURCES =3D async-sigs.c
bitfield1_SOURCES =3D bitfield1.c
Added: trunk/none/tests/ansi.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ansi.c 2005-06-28 19:20:46 UTC (rev 4043)
+++ trunk/none/tests/ansi.c 2005-06-28 19:44:10 UTC (rev 4044)
@@ -0,0 +1,14 @@
+/* It's possible that people #include valgrind.h in files compiled with
+ * -ansi. So valgrind.h shouldn't contain any code that won't pass -ans=
i,
+ * such as C++ style "//" comments. This test ensures that. So the tes=
t is
+ * really that it compiles ok, rather than it runs ok. From bug report
+ * #103182. */
+
+#include "valgrind.h"
+#include "../../memcheck/memcheck.h"
+#include "../../helgrind/helgrind.h"
+
+int main(void)
+{
+ return 0;
+}
Added: trunk/none/tests/ansi.stderr.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ansi.stderr.exp 2005-06-28 19:20:46 UTC (rev 4043)
+++ trunk/none/tests/ansi.stderr.exp 2005-06-28 19:44:10 UTC (rev 4044)
@@ -0,0 +1,2 @@
+
+
Added: trunk/none/tests/ansi.vgtest
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/ansi.vgtest 2005-06-28 19:20:46 UTC (rev 4043)
+++ trunk/none/tests/ansi.vgtest 2005-06-28 19:44:10 UTC (rev 4044)
@@ -0,0 +1 @@
+prog: ansi
|
|
From: <sv...@va...> - 2005-06-28 19:20:51
|
Author: njn
Date: 2005-06-28 20:20:46 +0100 (Tue, 28 Jun 2005)
New Revision: 4043
Log:
Free memory in the error case. Fixes bug #103168.
Modified:
trunk/coregrind/m_ume.c
Modified: trunk/coregrind/m_ume.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_ume.c 2005-06-28 19:04:51 UTC (rev 4042)
+++ trunk/coregrind/m_ume.c 2005-06-28 19:20:46 UTC (rev 4043)
@@ -275,37 +275,37 @@
if (pread(fd, &e->e, sizeof(e->e), 0) !=3D sizeof(e->e)) {
fprintf(stderr, "valgrind: %s: can't read ELF header: %s\n",=20
filename, strerror(errno));
- return NULL;
+ goto bad;
}
=20
if (memcmp(&e->e.e_ident[0], ELFMAG, SELFMAG) !=3D 0) {
fprintf(stderr, "valgrind: %s: bad ELF magic number\n", filename);
- return NULL;
+ goto bad;
}
if (e->e.e_ident[EI_CLASS] !=3D VG_ELF_CLASS) {
fprintf(stderr,=20
"valgrind: wrong ELF executable class "
"(eg. 32-bit instead of 64-bit)\n");
- return NULL;
+ goto bad;
}
if (e->e.e_ident[EI_DATA] !=3D VG_ELF_ENDIANNESS) {
fprintf(stderr, "valgrind: executable has wrong endian-ness\n");
- return NULL;
+ goto bad;
}
if (!(e->e.e_type =3D=3D ET_EXEC || e->e.e_type =3D=3D ET_DYN)) {
fprintf(stderr, "valgrind: this is not an executable\n");
- return NULL;
+ goto bad;
}
=20
if (e->e.e_machine !=3D VG_ELF_MACHINE) {
fprintf(stderr, "valgrind: executable is not for "
"this architecture\n");
- return NULL;
+ goto bad;
}
=20
if (e->e.e_phentsize !=3D sizeof(ESZ(Phdr))) {
fprintf(stderr, "valgrind: sizeof ELF Phdr wrong\n");
- return NULL;
+ goto bad;
}
=20
phsz =3D sizeof(ESZ(Phdr)) * e->e.e_phnum;
@@ -314,10 +314,15 @@
=20
if (pread(fd, e->p, phsz, e->e.e_phoff) !=3D phsz) {
fprintf(stderr, "valgrind: can't read phdr: %s\n", strerror(errno)=
);
- return NULL;
+ free(e->p);
+ goto bad;
}
=20
return e;
+
+ bad:
+ free(e);
+ return NULL;
}
=20
/* Map an ELF file. Returns the brk address. */
|
|
From: <sv...@va...> - 2005-06-28 19:05:05
|
Author: sewardj
Date: 2005-06-28 20:04:51 +0100 (Tue, 28 Jun 2005)
New Revision: 4042
Log:
Change scope from VG_ to ML_ various assembly symbols to do with doing
syscalls for the client.
Modified:
trunk/coregrind/m_syswrap/syscall-amd64-linux.S
trunk/coregrind/m_syswrap/syscall-ppc32-linux.S
trunk/coregrind/m_syswrap/syscall-x86-linux.S
trunk/coregrind/m_syswrap/syswrap-main.c
Modified: trunk/coregrind/m_syswrap/syscall-amd64-linux.S
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syscall-amd64-linux.S 2005-06-28 18:51:35 U=
TC (rev 4041)
+++ trunk/coregrind/m_syswrap/syscall-amd64-linux.S 2005-06-28 19:04:51 U=
TC (rev 4042)
@@ -55,12 +55,13 @@
sigprocmasks failed (there's no way to determine which one
failed).
=20
- VG_(interrupted_syscall)() does the thread state fixup in the
- case where we were interrupted by a signal.
+ VG_(fixup_guest_state_after_syscall_interrupted) does the
+ thread state fixup in the case where we were interrupted by a
+ signal.
=09
Prototype:
=20
- Int VG_(do_syscall_for_client_WRK(
+ Int ML_(do_syscall_for_client_WRK(
Int syscallno, // rdi
void* guest_state, // rsi
const vki_sigset_t *sysmask, // rdx
@@ -72,8 +73,8 @@
/* from vki_arch.h */=09
#define VKI_SIG_SETMASK 2
=09
-.globl VG_(do_syscall_for_client_WRK)
-VG_(do_syscall_for_client_WRK):
+.globl ML_(do_syscall_for_client_WRK)
+ML_(do_syscall_for_client_WRK):
/* save callee-saved regs */
pushq %rbx
pushq %rbp
@@ -170,19 +171,20 @@
ret
=20
.section .rodata
-/* export the ranges so that VG_(interrupted_syscall) can do the
- right thing */
+/* export the ranges so that
+ VG_(fixup_guest_state_after_syscall_interrupted) can do the
+ right thing */
=09
-.globl VG_(blksys_setup)
-.globl VG_(blksys_restart)
-.globl VG_(blksys_complete)
-.globl VG_(blksys_committed)
-.globl VG_(blksys_finished)
-VG_(blksys_setup): .quad 1b
-VG_(blksys_restart): .quad 2b
-VG_(blksys_complete): .quad 3b
-VG_(blksys_committed): .quad 4b
-VG_(blksys_finished): .quad 5b
+.globl ML_(blksys_setup)
+.globl ML_(blksys_restart)
+.globl ML_(blksys_complete)
+.globl ML_(blksys_committed)
+.globl ML_(blksys_finished)
+ML_(blksys_setup): .quad 1b
+ML_(blksys_restart): .quad 2b
+ML_(blksys_complete): .quad 3b
+ML_(blksys_committed): .quad 4b
+ML_(blksys_finished): .quad 5b
.previous
=20
/* Let the linker know we don't need an executable stack */
Modified: trunk/coregrind/m_syswrap/syscall-ppc32-linux.S
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syscall-ppc32-linux.S 2005-06-28 18:51:35 U=
TC (rev 4041)
+++ trunk/coregrind/m_syswrap/syscall-ppc32-linux.S 2005-06-28 19:04:51 U=
TC (rev 4042)
@@ -54,12 +54,13 @@
sigprocmasks failed (there's no way to determine which one
failed).
=20
- VG_(interrupted_syscall)() does the thread state fixup in the
- case where we were interrupted by a signal.
+ VG_(fixup_guest_state_after_syscall_interrupted) does the
+ thread state fixup in the case where we were interrupted by a
+ signal.
=20
Prototype:
=20
- Int VG_(do_syscall_for_client_WRK)(
+ Int ML_(do_syscall_for_client_WRK)(
Int syscallno, // r3
void* guest_state, // r4
const vki_sigset_t *sysmask, // r5
@@ -69,8 +70,8 @@
/* from vki_arch.h */
#define VKI_SIG_SETMASK 2
=20
-.globl VG_(do_syscall_for_client_WRK)
-VG_(do_syscall_for_client_WRK):
+.globl ML_(do_syscall_for_client_WRK)
+ML_(do_syscall_for_client_WRK):
/* make a stack frame */
stwu 1,-32(1)
stw 31,28(1)
@@ -140,16 +141,16 @@
VG_(fixup_guest_state_after_syscall_interrupted) can do the
right thing */
=20
-.globl VG_(blksys_setup)
-.globl VG_(blksys_restart)
-.globl VG_(blksys_complete)
-.globl VG_(blksys_committed)
-.globl VG_(blksys_finished)
-VG_(blksys_setup): .long 1b
-VG_(blksys_restart): .long 2b
-VG_(blksys_complete): .long 3b
-VG_(blksys_committed): .long 4b
-VG_(blksys_finished): .long 5b
+.globl ML_(blksys_setup)
+.globl ML_(blksys_restart)
+.globl ML_(blksys_complete)
+.globl ML_(blksys_committed)
+.globl ML_(blksys_finished)
+ML_(blksys_setup): .long 1b
+ML_(blksys_restart): .long 2b
+ML_(blksys_complete): .long 3b
+ML_(blksys_committed): .long 4b
+ML_(blksys_finished): .long 5b
=20
.previous
=09
Modified: trunk/coregrind/m_syswrap/syscall-x86-linux.S
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syscall-x86-linux.S 2005-06-28 18:51:35 UTC=
(rev 4041)
+++ trunk/coregrind/m_syswrap/syscall-x86-linux.S 2005-06-28 19:04:51 UTC=
(rev 4042)
@@ -55,12 +55,13 @@
sigprocmasks failed (there's no way to determine which one
failed).
=20
- VG_(interrupted_syscall)() does the thread state fixup in the
- case where we were interrupted by a signal.
+ VG_(fixup_guest_state_after_syscall_interrupted) does the
+ thread state fixup in the case where we were interrupted by a
+ signal.
=09
Prototype:
=20
- Int VG_(do_syscall_for_client_WRK)(
+ Int ML_(do_syscall_for_client_WRK)(
Int syscallno, // 0
void* guest_state, // 4
const vki_sigset_t *sysmask, // 8
@@ -72,8 +73,8 @@
/* from vki_arch.h */=09
#define VKI_SIG_SETMASK 2
=09
-.globl VG_(do_syscall_for_client_WRK)
-VG_(do_syscall_for_client_WRK):
+.globl ML_(do_syscall_for_client_WRK)
+ML_(do_syscall_for_client_WRK):
/* save callee-saved regs */
push %esi
push %edi
@@ -136,16 +137,16 @@
VG_(fixup_guest_state_after_syscall_interrupted) can do the
right thing */
=09
-.globl VG_(blksys_setup)
-.globl VG_(blksys_restart)
-.globl VG_(blksys_complete)
-.globl VG_(blksys_committed)
-.globl VG_(blksys_finished)
-VG_(blksys_setup): .long 1b
-VG_(blksys_restart): .long 2b
-VG_(blksys_complete): .long 3b
-VG_(blksys_committed): .long 4b
-VG_(blksys_finished): .long 5b
+.globl ML_(blksys_setup)
+.globl ML_(blksys_restart)
+.globl ML_(blksys_complete)
+.globl ML_(blksys_committed)
+.globl ML_(blksys_finished)
+ML_(blksys_setup): .long 1b
+ML_(blksys_restart): .long 2b
+ML_(blksys_complete): .long 3b
+ML_(blksys_committed): .long 4b
+ML_(blksys_finished): .long 5b
.previous
=09
/* Let the linker know we don't need an executable stack */
Modified: trunk/coregrind/m_syswrap/syswrap-main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_syswrap/syswrap-main.c 2005-06-28 18:51:35 UTC (rev=
4041)
+++ trunk/coregrind/m_syswrap/syswrap-main.c 2005-06-28 19:04:51 UTC (rev=
4042)
@@ -185,12 +185,13 @@
VG_(fixup_guest_state_after_syscall_interrupted) to adjust the
thread's context to do the right thing.
=20
- The _WRK function is handwritten assembly. It has some very magic
+ The _WRK function is handwritten assembly, implemented per-platform
+ in coregrind/m_syswrap/syscall-$PLAT.S. It has some very magic
properties. See comments at the top of
VG_(fixup_guest_state_after_syscall_interrupted) below for details.
*/
extern
-void VG_(do_syscall_for_client_WRK)( Int syscallno,=20
+void ML_(do_syscall_for_client_WRK)( Int syscallno,=20
void* guest_state,
const vki_sigset_t *syscall_mask,
const vki_sigset_t *restore_mask,
@@ -202,7 +203,7 @@
const vki_sigset_t* syscall_mask )
{
vki_sigset_t saved;
- VG_(do_syscall_for_client_WRK)(
+ ML_(do_syscall_for_client_WRK)(
syscallno, &tst->arch.vex,=20
syscall_mask, &saved, _VKI_NSIG_WORDS * sizeof(UWord)
);
@@ -901,13 +902,14 @@
*/
=20
=20
-/* These are addresses within VG_(_do_syscall_for_client). See syscall.=
S for
- details. */
-extern const Addr VG_(blksys_setup);
-extern const Addr VG_(blksys_restart);
-extern const Addr VG_(blksys_complete);
-extern const Addr VG_(blksys_committed);
-extern const Addr VG_(blksys_finished);
+/* These are addresses within ML_(do_syscall_for_client_WRK). See
+ syscall-$PLAT.S for details.=20
+*/
+extern const Addr ML_(blksys_setup);
+extern const Addr ML_(blksys_restart);
+extern const Addr ML_(blksys_complete);
+extern const Addr ML_(blksys_committed);
+extern const Addr ML_(blksys_finished);
=20
=20
/* Back up guest state to restart a system call. */
@@ -1046,9 +1048,9 @@
/* Figure out what the state of the syscall was by examining the
(real) IP at the time of the signal, and act accordingly. */
=20
- if (ip < VG_(blksys_setup) || ip >=3D VG_(blksys_finished)) {
+ if (ip < ML_(blksys_setup) || ip >=3D ML_(blksys_finished)) {
VG_(printf)(" not in syscall (%p - %p)\n",=20
- VG_(blksys_setup), VG_(blksys_finished));
+ ML_(blksys_setup), ML_(blksys_finished));
/* Looks like we weren't in a syscall at all. Hmm. */
vg_assert(sci->status.what !=3D SsIdle);
return;
@@ -1059,7 +1061,7 @@
Hence: */
vg_assert(sci->status.what !=3D SsIdle);
=20
- if (ip >=3D VG_(blksys_setup) && ip < VG_(blksys_restart)) {
+ if (ip >=3D ML_(blksys_setup) && ip < ML_(blksys_restart)) {
/* syscall hasn't even started; go around again */
if (debug)
VG_(printf)(" not started: restart\n");
@@ -1068,7 +1070,7 @@
}=20
=20
else=20
- if (ip =3D=3D VG_(blksys_restart)) {
+ if (ip =3D=3D ML_(blksys_restart)) {
/* We're either about to run the syscall, or it was interrupted
and the kernel restarted it. Restart if asked, otherwise
EINTR it. */
@@ -1085,7 +1087,7 @@
}
=20
else=20
- if (ip >=3D VG_(blksys_complete) && ip < VG_(blksys_committed)) {
+ if (ip >=3D ML_(blksys_complete) && ip < ML_(blksys_committed)) {
/* Syscall complete, but result hasn't been written back yet.
Write the SysRes we were supplied with back to the guest
state. */
@@ -1098,7 +1100,7 @@
}=20
=20
else=20
- if (ip >=3D VG_(blksys_committed) && ip < VG_(blksys_finished)) {
+ if (ip >=3D ML_(blksys_committed) && ip < ML_(blksys_finished)) {
/* Result committed, but the signal mask has not been restored;
we expect our caller (the signal handler) will have fixed
this up. */
|
|
From: <sv...@va...> - 2005-06-28 18:51:40
|
Author: sewardj Date: 2005-06-28 19:51:35 +0100 (Tue, 28 Jun 2005) New Revision: 4041 Log: Remove prototype which is not of a fn exported by this module and=20 in any case is actually a module-local fn for m_syswrap. Modified: trunk/coregrind/pub_core_syscall.h Modified: trunk/coregrind/pub_core_syscall.h =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/coregrind/pub_core_syscall.h 2005-06-28 02:54:52 UTC (rev 4040) +++ trunk/coregrind/pub_core_syscall.h 2005-06-28 18:51:35 UTC (rev 4041) @@ -67,16 +67,6 @@ extern SysRes VG_(mk_SysRes_Error) ( UWord val ); extern SysRes VG_(mk_SysRes_Success) ( UWord val ); =20 -// The _WRK function is handwritten assembly. It has some very magic -// properties. See comments at the top of -// VG_(fixup_guest_state_after_syscall_interrupted) below for details. -extern -void VG_(do_syscall_for_client_WRK)( Int syscallno,=20 - void* guest_state, - const vki_sigset_t *syscall_mask, - const vki_sigset_t *restore_mask, - Int nsigwords ); - #endif // __PUB_CORE_SYSCALL_H =20 /*--------------------------------------------------------------------*/ |
|
From: Greg P. <gp...@us...> - 2005-06-28 18:09:21
|
Julian Seward writes: > Comments? In particular, are there other bad consequences I haven't > thought of? Also, [GregP] how would this play for making V work > for MacOS ? No problem for Mac OS X. In fact, ditching dlopen is likely to be a bigger win on Mac OS X than elsewhere, because running two copies of the dynamic loader (one for Valgrind and one for the target) is hard. -- Greg Parker gp...@us... |
|
From: <sv...@va...> - 2005-06-28 18:06:27
|
Author: cerion
Date: 2005-06-28 19:06:23 +0100 (Tue, 28 Jun 2005)
New Revision: 1226
Log:
PPC32 AltiVec host-end framework & intruction output
- no fp yet
Modified:
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/hdefs.h
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-06-28 17:30:56 UTC (rev 1225)
+++ trunk/priv/host-ppc32/hdefs.c 2005-06-28 18:06:23 UTC (rev 1226)
@@ -69,6 +69,11 @@
vassert(r >=3D 0 && r < 32);
vex_printf("%%fr%d", r);
return;
+ case HRcVec128:
+ r =3D hregNumber(reg);
+ vassert(r >=3D 0 && r < 32);
+ vex_printf("%%v%d", r);
+ return;
default:
vpanic("ppHRegPPC32");
}
@@ -140,75 +145,142 @@
HReg hregPPC32_FPR30 ( void ) { return mkHReg(30, HRcFlt64, False); }
HReg hregPPC32_FPR31 ( void ) { return mkHReg(31, HRcFlt64, False); }
=20
+HReg hregPPC32_VR0 ( void ) { return mkHReg( 0, HRcVec128, False); }
+HReg hregPPC32_VR1 ( void ) { return mkHReg( 1, HRcVec128, False); }
+HReg hregPPC32_VR2 ( void ) { return mkHReg( 2, HRcVec128, False); }
+HReg hregPPC32_VR3 ( void ) { return mkHReg( 3, HRcVec128, False); }
+HReg hregPPC32_VR4 ( void ) { return mkHReg( 4, HRcVec128, False); }
+HReg hregPPC32_VR5 ( void ) { return mkHReg( 5, HRcVec128, False); }
+HReg hregPPC32_VR6 ( void ) { return mkHReg( 6, HRcVec128, False); }
+HReg hregPPC32_VR7 ( void ) { return mkHReg( 7, HRcVec128, False); }
+HReg hregPPC32_VR8 ( void ) { return mkHReg( 8, HRcVec128, False); }
+HReg hregPPC32_VR9 ( void ) { return mkHReg( 9, HRcVec128, False); }
+HReg hregPPC32_VR10 ( void ) { return mkHReg(10, HRcVec128, False); }
+HReg hregPPC32_VR11 ( void ) { return mkHReg(11, HRcVec128, False); }
+HReg hregPPC32_VR12 ( void ) { return mkHReg(12, HRcVec128, False); }
+HReg hregPPC32_VR13 ( void ) { return mkHReg(13, HRcVec128, False); }
+HReg hregPPC32_VR14 ( void ) { return mkHReg(14, HRcVec128, False); }
+HReg hregPPC32_VR15 ( void ) { return mkHReg(15, HRcVec128, False); }
+HReg hregPPC32_VR16 ( void ) { return mkHReg(16, HRcVec128, False); }
+HReg hregPPC32_VR17 ( void ) { return mkHReg(17, HRcVec128, False); }
+HReg hregPPC32_VR18 ( void ) { return mkHReg(18, HRcVec128, False); }
+HReg hregPPC32_VR19 ( void ) { return mkHReg(19, HRcVec128, False); }
+HReg hregPPC32_VR20 ( void ) { return mkHReg(20, HRcVec128, False); }
+HReg hregPPC32_VR21 ( void ) { return mkHReg(21, HRcVec128, False); }
+HReg hregPPC32_VR22 ( void ) { return mkHReg(22, HRcVec128, False); }
+HReg hregPPC32_VR23 ( void ) { return mkHReg(23, HRcVec128, False); }
+HReg hregPPC32_VR24 ( void ) { return mkHReg(24, HRcVec128, False); }
+HReg hregPPC32_VR25 ( void ) { return mkHReg(25, HRcVec128, False); }
+HReg hregPPC32_VR26 ( void ) { return mkHReg(26, HRcVec128, False); }
+HReg hregPPC32_VR27 ( void ) { return mkHReg(27, HRcVec128, False); }
+HReg hregPPC32_VR28 ( void ) { return mkHReg(28, HRcVec128, False); }
+HReg hregPPC32_VR29 ( void ) { return mkHReg(29, HRcVec128, False); }
+HReg hregPPC32_VR30 ( void ) { return mkHReg(30, HRcVec128, False); }
+HReg hregPPC32_VR31 ( void ) { return mkHReg(31, HRcVec128, False); }
+
void getAllocableRegs_PPC32 ( Int* nregs, HReg** arr )
{
+ UInt i=3D0;
*nregs =3D 59;
*arr =3D LibVEX_Alloc(*nregs * sizeof(HReg));
// GPR0 =3D scratch reg where possible - some ops interpret as value =
zero
// GPR1 =3D stack pointer
// GPR2 =3D TOC pointer
- (*arr)[ 0] =3D hregPPC32_GPR3();
- (*arr)[ 1] =3D hregPPC32_GPR4();
- (*arr)[ 2] =3D hregPPC32_GPR5();
- (*arr)[ 3] =3D hregPPC32_GPR6();
- (*arr)[ 4] =3D hregPPC32_GPR7();
- (*arr)[ 5] =3D hregPPC32_GPR8();
- (*arr)[ 6] =3D hregPPC32_GPR9();
- (*arr)[ 7] =3D hregPPC32_GPR10();
- (*arr)[ 8] =3D hregPPC32_GPR11();
- (*arr)[ 9] =3D hregPPC32_GPR12();
+ (*arr)[i++] =3D hregPPC32_GPR3();
+ (*arr)[i++] =3D hregPPC32_GPR4();
+ (*arr)[i++] =3D hregPPC32_GPR5();
+ (*arr)[i++] =3D hregPPC32_GPR6();
+ (*arr)[i++] =3D hregPPC32_GPR7();
+ (*arr)[i++] =3D hregPPC32_GPR8();
+ (*arr)[i++] =3D hregPPC32_GPR9();
+ (*arr)[i++] =3D hregPPC32_GPR10();
+ (*arr)[i++] =3D hregPPC32_GPR11();
+ (*arr)[i++] =3D hregPPC32_GPR12();
// GPR13 =3D thread specific pointer
- (*arr)[10] =3D hregPPC32_GPR14();
- (*arr)[11] =3D hregPPC32_GPR15();
- (*arr)[12] =3D hregPPC32_GPR16();
- (*arr)[13] =3D hregPPC32_GPR17();
- (*arr)[14] =3D hregPPC32_GPR18();
- (*arr)[15] =3D hregPPC32_GPR19();
- (*arr)[16] =3D hregPPC32_GPR20();
- (*arr)[17] =3D hregPPC32_GPR21();
- (*arr)[18] =3D hregPPC32_GPR22();
- (*arr)[19] =3D hregPPC32_GPR23();
- (*arr)[20] =3D hregPPC32_GPR24();
- (*arr)[21] =3D hregPPC32_GPR25();
- (*arr)[22] =3D hregPPC32_GPR26();
- (*arr)[23] =3D hregPPC32_GPR27();
- (*arr)[24] =3D hregPPC32_GPR28();
- (*arr)[25] =3D hregPPC32_GPR29();
- (*arr)[26] =3D hregPPC32_GPR30();
+ (*arr)[i++] =3D hregPPC32_GPR14();
+ (*arr)[i++] =3D hregPPC32_GPR15();
+ (*arr)[i++] =3D hregPPC32_GPR16();
+ (*arr)[i++] =3D hregPPC32_GPR17();
+ (*arr)[i++] =3D hregPPC32_GPR18();
+ (*arr)[i++] =3D hregPPC32_GPR19();
+ (*arr)[i++] =3D hregPPC32_GPR20();
+ (*arr)[i++] =3D hregPPC32_GPR21();
+ (*arr)[i++] =3D hregPPC32_GPR22();
+ (*arr)[i++] =3D hregPPC32_GPR23();
+ (*arr)[i++] =3D hregPPC32_GPR24();
+ (*arr)[i++] =3D hregPPC32_GPR25();
+ (*arr)[i++] =3D hregPPC32_GPR26();
+ (*arr)[i++] =3D hregPPC32_GPR27();
+ (*arr)[i++] =3D hregPPC32_GPR28();
+ (*arr)[i++] =3D hregPPC32_GPR29();
+ // GPR30 AltiVec spill reg temporary
// GPR31 =3D GuestStatePtr
=20
- (*arr)[27] =3D hregPPC32_FPR0();
- (*arr)[28] =3D hregPPC32_FPR1();
- (*arr)[29] =3D hregPPC32_FPR2();
- (*arr)[30] =3D hregPPC32_FPR3();
- (*arr)[31] =3D hregPPC32_FPR4();
- (*arr)[32] =3D hregPPC32_FPR5();
- (*arr)[33] =3D hregPPC32_FPR6();
- (*arr)[34] =3D hregPPC32_FPR7();
- (*arr)[35] =3D hregPPC32_FPR8();
- (*arr)[36] =3D hregPPC32_FPR9();
- (*arr)[37] =3D hregPPC32_FPR10();
- (*arr)[38] =3D hregPPC32_FPR11();
- (*arr)[39] =3D hregPPC32_FPR12();
- (*arr)[40] =3D hregPPC32_FPR13();
- (*arr)[41] =3D hregPPC32_FPR14();
- (*arr)[42] =3D hregPPC32_FPR15();
- (*arr)[43] =3D hregPPC32_FPR16();
- (*arr)[44] =3D hregPPC32_FPR17();
- (*arr)[45] =3D hregPPC32_FPR18();
- (*arr)[46] =3D hregPPC32_FPR19();
- (*arr)[47] =3D hregPPC32_FPR20();
- (*arr)[48] =3D hregPPC32_FPR21();
- (*arr)[49] =3D hregPPC32_FPR22();
- (*arr)[50] =3D hregPPC32_FPR23();
- (*arr)[51] =3D hregPPC32_FPR24();
- (*arr)[52] =3D hregPPC32_FPR25();
- (*arr)[53] =3D hregPPC32_FPR26();
- (*arr)[54] =3D hregPPC32_FPR27();
- (*arr)[55] =3D hregPPC32_FPR28();
- (*arr)[56] =3D hregPPC32_FPR29();
- (*arr)[57] =3D hregPPC32_FPR30();
- (*arr)[58] =3D hregPPC32_FPR31();
+ (*arr)[i++] =3D hregPPC32_FPR0();
+ (*arr)[i++] =3D hregPPC32_FPR1();
+ (*arr)[i++] =3D hregPPC32_FPR2();
+ (*arr)[i++] =3D hregPPC32_FPR3();
+ (*arr)[i++] =3D hregPPC32_FPR4();
+ (*arr)[i++] =3D hregPPC32_FPR5();
+ (*arr)[i++] =3D hregPPC32_FPR6();
+ (*arr)[i++] =3D hregPPC32_FPR7();
+ (*arr)[i++] =3D hregPPC32_FPR8();
+ (*arr)[i++] =3D hregPPC32_FPR9();
+ (*arr)[i++] =3D hregPPC32_FPR10();
+ (*arr)[i++] =3D hregPPC32_FPR11();
+ (*arr)[i++] =3D hregPPC32_FPR12();
+ (*arr)[i++] =3D hregPPC32_FPR13();
+ (*arr)[i++] =3D hregPPC32_FPR14();
+ (*arr)[i++] =3D hregPPC32_FPR15();
+ (*arr)[i++] =3D hregPPC32_FPR16();
+ (*arr)[i++] =3D hregPPC32_FPR17();
+ (*arr)[i++] =3D hregPPC32_FPR18();
+ (*arr)[i++] =3D hregPPC32_FPR19();
+ (*arr)[i++] =3D hregPPC32_FPR20();
+ (*arr)[i++] =3D hregPPC32_FPR21();
+ (*arr)[i++] =3D hregPPC32_FPR22();
+ (*arr)[i++] =3D hregPPC32_FPR23();
+ (*arr)[i++] =3D hregPPC32_FPR24();
+ (*arr)[i++] =3D hregPPC32_FPR25();
+ (*arr)[i++] =3D hregPPC32_FPR26();
+ (*arr)[i++] =3D hregPPC32_FPR27();
+ (*arr)[i++] =3D hregPPC32_FPR28();
+ (*arr)[i++] =3D hregPPC32_FPR29();
+ (*arr)[i++] =3D hregPPC32_FPR30();
+ (*arr)[i++] =3D hregPPC32_FPR31();
+
+ (*arr)[i++] =3D hregPPC32_VR0();
+ (*arr)[i++] =3D hregPPC32_VR1();
+ (*arr)[i++] =3D hregPPC32_VR2();
+ (*arr)[i++] =3D hregPPC32_VR3();
+ (*arr)[i++] =3D hregPPC32_VR4();
+ (*arr)[i++] =3D hregPPC32_VR5();
+ (*arr)[i++] =3D hregPPC32_VR6();
+ (*arr)[i++] =3D hregPPC32_VR7();
+ (*arr)[i++] =3D hregPPC32_VR8();
+ (*arr)[i++] =3D hregPPC32_VR9();
+ (*arr)[i++] =3D hregPPC32_VR10();
+ (*arr)[i++] =3D hregPPC32_VR11();
+ (*arr)[i++] =3D hregPPC32_VR12();
+ (*arr)[i++] =3D hregPPC32_VR13();
+ (*arr)[i++] =3D hregPPC32_VR14();
+ (*arr)[i++] =3D hregPPC32_VR15();
+ (*arr)[i++] =3D hregPPC32_VR16();
+ (*arr)[i++] =3D hregPPC32_VR17();
+ (*arr)[i++] =3D hregPPC32_VR18();
+ (*arr)[i++] =3D hregPPC32_VR19();
+ (*arr)[i++] =3D hregPPC32_VR20();
+ (*arr)[i++] =3D hregPPC32_VR21();
+ (*arr)[i++] =3D hregPPC32_VR22();
+ (*arr)[i++] =3D hregPPC32_VR23();
+ (*arr)[i++] =3D hregPPC32_VR24();
+ (*arr)[i++] =3D hregPPC32_VR25();
+ (*arr)[i++] =3D hregPPC32_VR26();
+ (*arr)[i++] =3D hregPPC32_VR27();
+ (*arr)[i++] =3D hregPPC32_VR28();
+ (*arr)[i++] =3D hregPPC32_VR29();
+ (*arr)[i++] =3D hregPPC32_VR30();
+ (*arr)[i++] =3D hregPPC32_VR31();
}
=20
=20
@@ -439,6 +511,126 @@
}
}
=20
+HChar* showPPC32AvOp ( PPC32AvOp op ) {
+ switch (op) {
+ /* mov */
+ case Pav_MOV: return "vmr";
+ =20
+ /* Bitwise */
+ case Pav_AND: return "vand";
+ case Pav_OR: return "vor";
+ case Pav_XOR: return "vxor";
+ case Pav_NOT: return "vnot";
+
+ /* Integer binary */
+ case Pav_ADD8UM: return "vaddubm";
+ case Pav_ADD16UM: return "vadduhm";
+ case Pav_ADD32UM: return "vadduwm";
+ case Pav_ADD8US: return "vaddubs";
+ case Pav_ADD16US: return "vadduhs";
+ case Pav_ADD32US: return "vadduws";
+ case Pav_ADD8SS: return "vaddsbs";
+ case Pav_ADD16SS: return "vaddshs";
+ case Pav_ADD32SS: return "vaddsws";
+ =20
+ case Pav_SUB8UM: return "vsububm";
+ case Pav_SUB16UM: return "vsubuhm";
+ case Pav_SUB32UM: return "vsubuwm";
+ case Pav_SUB8US: return "vsububs";
+ case Pav_SUB16US: return "vsubuhs";
+ case Pav_SUB32US: return "vsubuws";
+ case Pav_SUB8SS: return "vsubsbs";
+ case Pav_SUB16SS: return "vsubshs";
+ case Pav_SUB32SS: return "vsubsws";
+ =20
+ case Pav_OMUL8U: return "vmuloub";
+ case Pav_OMUL16U: return "vmulouh";
+ case Pav_OMUL8S: return "vmulosb";
+ case Pav_OMUL16S: return "vmulosh";
+ case Pav_EMUL8U: return "vmuleub";
+ case Pav_EMUL16U: return "vmuleuh";
+ case Pav_EMUL8S: return "vmulesb";
+ case Pav_EMUL16S: return "vmulesh";
+ =20
+ case Pav_AVG8U: return "vavgub";
+ case Pav_AVG16U: return "vavguh";
+ case Pav_AVG32U: return "vavguw";
+ case Pav_AVG8S: return "vavgsb";
+ case Pav_AVG16S: return "vavgsh";
+ case Pav_AVG32S: return "vavgsw";
+ =20
+ case Pav_MAX8U: return "vmaxub";
+ case Pav_MAX16U: return "vmaxuh";
+ case Pav_MAX32U: return "vmaxuw";
+ case Pav_MAX8S: return "vmaxsb";
+ case Pav_MAX16S: return "vmaxsh";
+ case Pav_MAX32S: return "vmaxsw";
+ =20
+ case Pav_MIN8U: return "vminub";
+ case Pav_MIN16U: return "vminuh";
+ case Pav_MIN32U: return "vminuw";
+ case Pav_MIN8S: return "vminsb";
+ case Pav_MIN16S: return "vminsh";
+ case Pav_MIN32S: return "vminsw";
+ =20
+ /* Compare (always affects CR field 6) */
+ case Pav_CMPEQ8U: return "vcmpequb";
+ case Pav_CMPEQ16U: return "vcmpequh";
+ case Pav_CMPEQ32U: return "vcmpequw";
+ case Pav_CMPGT8U: return "vcmpgtub";
+ case Pav_CMPGT16U: return "vcmpgtuh";
+ case Pav_CMPGT32U: return "vcmpgtuw";
+ case Pav_CMPGT8S: return "vcmpgtsb";
+ case Pav_CMPGT16S: return "vcmpgtsh";
+ case Pav_CMPGT32S: return "vcmpgtsw";
+
+ /* Shift */
+ case Pav_SHL8: return "vslb";
+ case Pav_SHL16: return "vslh";
+ case Pav_SHL32: return "vslw";
+ case Pav_SHL128: return "vsl";
+ case Pav_SHR8: return "vsrb";
+ case Pav_SHR16: return "vsrh";
+ case Pav_SHR32: return "vsrw";
+ case Pav_SHR128: return "vsr";
+ case Pav_SAR8: return "vsrab";
+ case Pav_SAR16: return "vsrah";
+ case Pav_SAR32: return "vsraw";
+ case Pav_ROTL8: return "vrlb";
+ case Pav_ROTL16: return "vrlh";
+ case Pav_ROTL32: return "vrlw";
+ =20
+ /* Pack */
+ case Pav_PACKU16UM: return "vpkuhum";
+ case Pav_PACKU32UM: return "vpkuwum";
+ case Pav_PACKU16US: return "vpkuhus";
+ case Pav_PACKU32US: return "vpkuwus";
+ case Pav_PACKS16US: return "vpkshus";
+ case Pav_PACKS32US: return "vpkswus";
+ case Pav_PACKS16SS: return "vpkshss";
+ case Pav_PACKS32SS: return "vpkswss";
+ case Pav_PACKPXL: return "vpkpx";
+
+ /* Unpack (srcL ignored) */
+ case Pav_UNPCKH8S: return "vupkhsb";
+ case Pav_UNPCKH16S: return "vupkhsh";
+ case Pav_UNPCKL8S: return "vupklsb";
+ case Pav_UNPCKL16S: return "vupklsh";
+ case Pav_UNPCKHPIX: return "vupkhpx";
+ case Pav_UNPCKLPIX: return "vupklpx";
+ =20
+ /* Merge */
+ case Pav_MRG8HI: return "vmrghb";
+ case Pav_MRG16HI: return "vmrghh";
+ case Pav_MRG32HI: return "vmrghw";
+ case Pav_MRG8LO: return "vmrglb";
+ case Pav_MRG16LO: return "vmrglh";
+ case Pav_MRG32LO: return "vmrglw";
+ =20
+ default: vpanic("showPPC32AvOp");
+ }
+}
+
PPC32Instr* PPC32Instr_Alu32 ( PPC32AluOp op, HReg dst, HReg srcL, PPC32=
RI* srcR ) {
PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
if (srcR->tag =3D=3D Pri_Imm)
@@ -646,8 +838,7 @@
}
=20
/* Read/Write Link Register */
-PPC32Instr* PPC32Instr_RdWrLR ( Bool wrLR, HReg gpr )
-{
+PPC32Instr* PPC32Instr_RdWrLR ( Bool wrLR, HReg gpr ) {
PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
i->tag =3D Pin_RdWrLR;
i->Pin.RdWrLR.wrLR =3D wrLR;
@@ -655,7 +846,76 @@
return i;
}
=20
+/* AltiVec */
+PPC32Instr* PPC32Instr_AvLdSt ( Bool isLoad, UChar sz, HReg reg, PPC32AM=
ode* addr ) {
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvLdSt;
+ i->Pin.AvLdSt.isLoad =3D isLoad;
+ i->Pin.AvLdSt.sz =3D sz;
+ i->Pin.AvLdSt.reg =3D reg;
+ i->Pin.AvLdSt.addr =3D addr;
+ return i;
+}
+PPC32Instr* PPC32Instr_AvUnary ( PPC32AvOp op, HReg dst, HReg src ) {
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvUnary;
+ i->Pin.AvUnary.op =3D op;
+ i->Pin.AvUnary.dst =3D dst;
+ i->Pin.AvUnary.src =3D src;
+ return i;
+}
+PPC32Instr* PPC32Instr_AvBinary ( PPC32AvOp op, HReg dst, HReg srcL, HRe=
g srcR ) {
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvBinary;
+ i->Pin.AvBinary.op =3D op;
+ i->Pin.AvBinary.dst =3D dst;
+ i->Pin.AvBinary.srcL =3D srcL;
+ i->Pin.AvBinary.srcR =3D srcR;
+ return i;
+}
+PPC32Instr* PPC32Instr_AvPerm ( HReg ctl, HReg dst, HReg srcL, HReg srcR=
) {
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvPerm;
+ i->Pin.AvPerm.ctl =3D ctl;
+ i->Pin.AvPerm.dst =3D dst;
+ i->Pin.AvPerm.srcL =3D srcL;
+ i->Pin.AvPerm.srcR =3D srcR;
+ return i;
+}
+PPC32Instr* PPC32Instr_AvSel ( HReg ctl, HReg dst, HReg srcL, HReg srcR =
) {
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvSel;
+ i->Pin.AvSel.ctl =3D ctl;
+ i->Pin.AvSel.dst =3D dst;
+ i->Pin.AvSel.srcL =3D srcL;
+ i->Pin.AvSel.srcR =3D srcR;
+ return i;
+}
+PPC32Instr* PPC32Instr_AvShlDbl ( UChar shift, HReg dst, HReg srcL, HReg=
srcR ) {
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvShlDbl;
+ i->Pin.AvShlDbl.shift =3D shift;
+ i->Pin.AvShlDbl.dst =3D dst;
+ i->Pin.AvShlDbl.srcL =3D srcL;
+ i->Pin.AvShlDbl.srcR =3D srcR;
+ return i;
+}
+PPC32Instr* PPC32Instr_AvSplat ( UChar sz, HReg dst, PPC32RI* src ) {
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvSplat;
+ i->Pin.AvSplat.sz =3D sz;
+ i->Pin.AvSplat.dst =3D dst;
+ i->Pin.AvSplat.src =3D src;
+ return i;
+}
+PPC32Instr* PPC32Instr_AvLdVSCR ( HReg src ) {
+ PPC32Instr* i =3D LibVEX_Alloc(sizeof(PPC32Instr));
+ i->tag =3D Pin_AvLdVSCR;
+ i->Pin.AvLdVSCR.src =3D src;
+ return i;
+}
=20
+
/* Pretty Print instructions */
static void ppLoadImm ( HReg dst, UInt imm ) {
if (imm < 0x10000) {
@@ -961,6 +1221,96 @@
ppHRegPPC32(i->Pin.RdWrLR.gpr);
return;
=20
+ case Pin_AvLdSt: {
+ UChar sz =3D i->Pin.AvLdSt.sz;
+ UChar* str_sz =3D (sz =3D=3D 8) ? "eb" :
+ (sz =3D=3D 16) ? "eh" :
+ (sz =3D=3D 32) ? "ew" : "";
+ if (i->Pin.AvLdSt.addr->tag =3D=3D Pam_IR) {
+ vex_printf("{ ");
+ ppLoadImm(hregPPC32_GPR30(), i->Pin.AvLdSt.addr->Pam.RR.index);
+ vex_printf(" }");
+ }
+ if (i->Pin.AvLdSt.isLoad) {
+ vex_printf("lv%sx ", str_sz);
+ ppHRegPPC32(i->Pin.AvLdSt.reg);
+ vex_printf(",");
+ ppPPC32AMode(i->Pin.AvLdSt.addr);
+ } else {
+ vex_printf("stv%sx ", str_sz);
+ ppHRegPPC32(i->Pin.AvLdSt.reg);
+ vex_printf(",");
+ ppPPC32AMode(i->Pin.AvLdSt.addr);
+ }
+ return;
+ }
+ case Pin_AvUnary:
+ vex_printf("%s ", showPPC32AvOp(i->Pin.AvUnary.op));
+ ppHRegPPC32(i->Pin.AvUnary.dst);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvUnary.src);
+ return;
+ case Pin_AvBinary:
+ vex_printf("%s ", showPPC32AvOp(i->Pin.AvBinary.op));
+ ppHRegPPC32(i->Pin.AvBinary.dst);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvBinary.srcL);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvBinary.srcR);
+ return;
+ case Pin_AvPerm:
+ vex_printf("vperm ");
+ ppHRegPPC32(i->Pin.AvPerm.dst);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvPerm.srcL);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvPerm.srcR);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvPerm.ctl);
+ return;
+
+ case Pin_AvSel:
+ vex_printf("vsel ");
+ ppHRegPPC32(i->Pin.AvSel.dst);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvSel.srcL);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvSel.srcR);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvSel.ctl);
+ return;
+
+ case Pin_AvShlDbl:
+ vex_printf("vsldoi ");
+ ppHRegPPC32(i->Pin.AvShlDbl.dst);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvShlDbl.srcL);
+ vex_printf(",");
+ ppHRegPPC32(i->Pin.AvShlDbl.srcR);
+ vex_printf(",%u", i->Pin.AvShlDbl.shift);
+ return;
+
+ case Pin_AvSplat: {
+ UChar ch_sz =3D (i->Pin.AvSplat.sz =3D=3D 8) ? 'b' :
+ (i->Pin.AvSplat.sz =3D=3D 16) ? 'h' : 'w';
+ vex_printf("vsplt%s%c ",
+ i->Pin.AvSplat.src->tag =3D=3D Pri_Imm ? "is" : "", ch_=
sz);
+ ppHRegPPC32(i->Pin.AvSplat.dst);
+ vex_printf(",");
+ if (i->Pin.AvSplat.src->tag =3D=3D Pri_Imm) {
+ vex_printf("%d", (Char)(i->Pin.AvSplat.src->Pri.Imm.imm32));
+ } else {
+ ppHRegPPC32(i->Pin.AvSplat.src->Pri.Reg.reg);
+ vex_printf(", 0");
+ }
+ return;
+ }
+
+ case Pin_AvLdVSCR:
+ vex_printf("mtvscr ");
+ ppHRegPPC32(i->Pin.AvLdVSCR.src);
+ return;
+
default:
vex_printf("\nppPPC32Instr(ppc32): No such tag(%d)\n", (Int)i->tag=
);
vpanic("ppPPC32Instr(ppc32)");
@@ -1116,6 +1466,47 @@
i->Pin.RdWrLR.gpr);
return;
=20
+ case Pin_AvLdSt:
+ addHRegUse(u, (i->Pin.AvLdSt.isLoad ? HRmWrite : HRmRead),
+ i->Pin.AvLdSt.reg);
+ if (i->Pin.AvLdSt.addr->tag =3D=3D Pam_IR)
+ addHRegUse(u, HRmWrite, hregPPC32_GPR30());
+ addRegUsage_PPC32AMode(u, i->Pin.AvLdSt.addr);
+ return;
+ case Pin_AvUnary:
+ addHRegUse(u, HRmWrite, i->Pin.AvUnary.dst);
+ addHRegUse(u, HRmRead, i->Pin.AvUnary.src);
+ return;
+ case Pin_AvBinary:
+ addHRegUse(u, HRmWrite, i->Pin.AvBinary.dst);
+ addHRegUse(u, HRmRead, i->Pin.AvBinary.srcL);
+ addHRegUse(u, HRmRead, i->Pin.AvBinary.srcR);
+ return;
+ case Pin_AvPerm:
+ addHRegUse(u, HRmWrite, i->Pin.AvPerm.dst);
+ addHRegUse(u, HRmRead, i->Pin.AvPerm.ctl);
+ addHRegUse(u, HRmRead, i->Pin.AvPerm.srcL);
+ addHRegUse(u, HRmRead, i->Pin.AvPerm.srcR);
+ return;
+ case Pin_AvSel:
+ addHRegUse(u, HRmWrite, i->Pin.AvSel.dst);
+ addHRegUse(u, HRmRead, i->Pin.AvSel.ctl);
+ addHRegUse(u, HRmRead, i->Pin.AvSel.srcL);
+ addHRegUse(u, HRmRead, i->Pin.AvSel.srcR);
+ return;
+ case Pin_AvShlDbl:
+ addHRegUse(u, HRmWrite, i->Pin.AvShlDbl.dst);
+ addHRegUse(u, HRmRead, i->Pin.AvShlDbl.srcL);
+ addHRegUse(u, HRmRead, i->Pin.AvShlDbl.srcR);
+ return;
+ case Pin_AvSplat:
+ addHRegUse(u, HRmWrite, i->Pin.AvSplat.dst);
+ addRegUsage_PPC32RI(u, i->Pin.AvSplat.src);
+ return;
+ case Pin_AvLdVSCR:
+ addHRegUse(u, HRmRead, i->Pin.AvLdVSCR.src);
+ return;
+
default:
ppPPC32Instr(i);
vpanic("getRegUsage_PPC32Instr");
@@ -1225,6 +1616,44 @@
mapReg(m, &i->Pin.RdWrLR.gpr);
return;
=20
+ case Pin_AvLdSt:
+ mapReg(m, &i->Pin.AvLdSt.reg);
+ mapRegs_PPC32AMode(m, i->Pin.AvLdSt.addr);
+ return;
+ case Pin_AvUnary:
+ mapReg(m, &i->Pin.AvUnary.dst);
+ mapReg(m, &i->Pin.AvUnary.src);
+ return;
+ case Pin_AvBinary:
+ mapReg(m, &i->Pin.AvBinary.dst);
+ mapReg(m, &i->Pin.AvBinary.srcL);
+ mapReg(m, &i->Pin.AvBinary.srcR);
+ return;
+ case Pin_AvPerm:
+ mapReg(m, &i->Pin.AvPerm.dst);
+ mapReg(m, &i->Pin.AvPerm.srcL);
+ mapReg(m, &i->Pin.AvPerm.srcR);
+ mapReg(m, &i->Pin.AvPerm.ctl);
+ return;
+ case Pin_AvSel:
+ mapReg(m, &i->Pin.AvSel.dst);
+ mapReg(m, &i->Pin.AvSel.srcL);
+ mapReg(m, &i->Pin.AvSel.srcR);
+ mapReg(m, &i->Pin.AvSel.ctl);
+ return;
+ case Pin_AvShlDbl:
+ mapReg(m, &i->Pin.AvShlDbl.dst);
+ mapReg(m, &i->Pin.AvShlDbl.srcL);
+ mapReg(m, &i->Pin.AvShlDbl.srcR);
+ return;
+ case Pin_AvSplat:
+ mapReg(m, &i->Pin.AvSplat.dst);
+ mapRegs_PPC32RI(m, i->Pin.AvSplat.src);
+ return;
+ case Pin_AvLdVSCR:
+ mapReg(m, &i->Pin.AvLdVSCR.src);
+ return;
+
default:
ppPPC32Instr(i);
vpanic("mapRegs_PPC32Instr");
@@ -1265,11 +1694,9 @@
/* Generate ppc32 spill/reload instructions under the direction of the
register allocator. Note it's critical these don't write the
condition codes. */
-
-PPC32Instr* genSpill_PPC32 ( HReg rreg, Int offsetB )
+PPC32Instr* genSpill_PPC32 ( HReg rreg, UShort offsetB )
{
PPC32AMode* am;
- vassert(offsetB >=3D 0);
vassert(!hregIsVirtual(rreg));
am =3D PPC32AMode_IR(offsetB, GuestStatePtr);
=20
@@ -1278,16 +1705,18 @@
return PPC32Instr_Store( 4, am, rreg);
case HRcFlt64:
return PPC32Instr_FpLdSt ( False/*store*/, 8, rreg, am );
+ case HRcVec128:
+ // XXX: GPR30 used as spill register to kludge AltiVec AMode_IR
+ return PPC32Instr_AvLdSt ( False/*store*/, 16, rreg, am );
default:=20
ppHRegClass(hregClass(rreg));
vpanic("genSpill_PPC32: unimplemented regclass");
}
}
=20
-PPC32Instr* genReload_PPC32 ( HReg rreg, Int offsetB )
+PPC32Instr* genReload_PPC32 ( HReg rreg, UShort offsetB )
{
PPC32AMode* am;
- vassert(offsetB >=3D 0);
vassert(!hregIsVirtual(rreg));
am =3D PPC32AMode_IR(offsetB, GuestStatePtr);
=20
@@ -1296,6 +1725,9 @@
return PPC32Instr_Load( 4, False, rreg, am );
case HRcFlt64:
return PPC32Instr_FpLdSt ( True/*load*/, 8, rreg, am );
+ case HRcVec128:
+ // XXX: GPR30 used as spill register to kludge AltiVec AMode_IR
+ return PPC32Instr_AvLdSt ( True/*load*/, 16, rreg, am );
default:=20
ppHRegClass(hregClass(rreg));
vpanic("genReload_PPC32: unimplemented regclass");
@@ -1325,6 +1757,16 @@
return n;
}
=20
+static UInt vregNo ( HReg v )
+{
+ UInt n;
+ vassert(hregClass(v) =3D=3D HRcVec128);
+ vassert(!hregIsVirtual(v));
+ n =3D hregNumber(v);
+ vassert(n <=3D 32);
+ return n;
+}
+
/* Emit 32bit instruction big-endianly */
static UChar* emit32 ( UChar* p, UInt w32 )
{
@@ -1533,7 +1975,6 @@
return p;
}
=20
-
/* Move r_dst to r_src */
static UChar* mkMoveReg ( UChar* p, UInt r_dst, UInt r_src )
{
@@ -1547,7 +1988,35 @@
return p;
}
=20
+static UChar* mkFormVX ( UChar* p, UInt opc1, UInt r1, UInt r2,
+ UInt r3, UInt opc2 )
+{
+ UInt theInstr;
+ vassert(opc1 < 0x40);
+ vassert(r1 < 0x20);
+ vassert(r2 < 0x20);
+ vassert(r3 < 0x20);
+ vassert(opc2 < 0x800);
+ theInstr =3D ((opc1<<26) | (r1<<21) | (r2<<16) | (r3<<11) | (opc2<<1)=
);
+ return emit32(p, theInstr);
+}
=20
+static UChar* mkFormVA ( UChar* p, UInt opc1, UInt r1, UInt r2,
+ UInt r3, UInt r4, UInt opc2 )
+{
+ UInt theInstr;
+ vassert(opc1 < 0x40);
+ vassert(r1 < 0x20);
+ vassert(r2 < 0x20);
+ vassert(r3 < 0x20);
+ vassert(r4 < 0x20);
+ vassert(opc2 < 0x40);
+ theInstr =3D ((opc1<<26) | (r1<<21) | (r2<<16) | (r3<<11) | (r4<<6) |=
opc2);
+ return emit32(p, theInstr);
+}
+
+
+
/* Emit an instruction into buf and return the number of bytes used.
Note that buf is not the insn's final place, and therefore it is
imperative to emit position-independent code. */
@@ -2132,6 +2601,236 @@
goto done;
}
=20
+
+ /* AltiVec */
+ case Pin_AvLdSt: {
+ UInt opc2, v_reg, r_idx, r_base;
+ UChar sz =3D i->Pin.AvLdSt.sz;
+ Bool idxd =3D toBool(i->Pin.AvLdSt.addr->tag =3D=3D Pam_RR);
+ vassert(sz =3D=3D 8 || sz =3D=3D 16 || sz =3D=3D 32 || sz =3D=3D 1=
28);
+
+ v_reg =3D vregNo(i->Pin.AvLdSt.reg);
+ r_base =3D iregNo(i->Pin.AvLdSt.addr->Pam.RR.base);
+
+ // Only have AltiVec AMode_RR: kludge AMode_IR
+ if (!idxd) {
+ r_idx =3D 30; // XXX: Using r30 as temp
+ p =3D mkLoadImm(p, r_idx, i->Pin.AvLdSt.addr->Pam.IR.index);
+ } else {
+ r_idx =3D iregNo(i->Pin.AvLdSt.addr->Pam.RR.index);
+ }
+
+ if (i->Pin.FpLdSt.isLoad) { // Load from memory (8,16,32,128)
+ opc2 =3D (sz =3D=3D 8) ? 7 : (sz =3D=3D 16) ? 39 : (sz =3D=3D 3=
2) ? 71 : 103;
+ p =3D mkFormX(p, 31, v_reg, r_idx, r_base, opc2, 0);
+ } else { // Store to memory (8,16,32,128)
+ opc2 =3D (sz =3D=3D 8) ? 135 : (sz =3D=3D 16) ? 167 : (sz =3D=3D=
32) ? 199 : 231;
+ p =3D mkFormX(p, 31, v_reg, r_idx, r_base, opc2, 0);
+ }
+ goto done;
+ }
+
+ case Pin_AvUnary: {
+ UInt v_dst =3D vregNo(i->Pin.AvUnary.dst);
+ UInt v_src =3D vregNo(i->Pin.AvUnary.src);
+ UInt opc2;
+ switch (i->Pin.AvUnary.op) {
+ case Pav_MOV: opc2 =3D 1156; break; // vor vD,vS,vS
+ case Pav_NOT: opc2 =3D 1284; break; // vnor vD,vS,vS
+ case Pav_UNPCKH8S: opc2 =3D 526; break; // vupkhsb
+ case Pav_UNPCKH16S: opc2 =3D 590; break; // vupkhsh
+ case Pav_UNPCKL8S: opc2 =3D 654; break; // vupklsb
+ case Pav_UNPCKL16S: opc2 =3D 718; break; // vupklsh
+ case Pav_UNPCKHPIX: opc2 =3D 846; break; // vupkhpx
+ case Pav_UNPCKLPIX: opc2 =3D 974; break; // vupklpx
+ default:
+ goto bad;
+ }
+ switch (i->Pin.AvUnary.op) {
+ case Pav_MOV:
+ case Pav_NOT:
+ p =3D mkFormVX( p, 4, v_dst, v_src, v_src, opc2 );
+ break;
+ default:
+ p =3D mkFormVX( p, 4, v_dst, 0, v_src, opc2 );
+ break;
+ }
+ goto done;
+ }
+
+ case Pin_AvBinary: {
+ UInt v_dst =3D vregNo(i->Pin.AvBinary.dst);
+ UInt v_srcL =3D vregNo(i->Pin.AvBinary.srcL);
+ UInt v_srcR =3D vregNo(i->Pin.AvBinary.srcR);
+ UInt opc2;
+ switch (i->Pin.AvBinary.op) {
+ /* Bitwise */
+ case Pav_AND: opc2 =3D 1026; break; // vand
+ case Pav_OR: opc2 =3D 1156; break; // vor
+ case Pav_XOR: opc2 =3D 1120; break; // vxor
+
+ /* Add */
+ case Pav_ADD8UM: opc2 =3D 0; break; // vaddubm
+ case Pav_ADD16UM: opc2 =3D 64; break; // vadduhm
+ case Pav_ADD32UM: opc2 =3D 128; break; // vadduwm
+ case Pav_ADD8US: opc2 =3D 512; break; // vaddubs
+ case Pav_ADD16US: opc2 =3D 576; break; // vadduhs
+ case Pav_ADD32US: opc2 =3D 640; break; // vadduws
+ case Pav_ADD8SS: opc2 =3D 768; break; // vaddsbs
+ case Pav_ADD16SS: opc2 =3D 832; break; // vaddshs
+ case Pav_ADD32SS: opc2 =3D 896; break; // vaddsws
+
+ /* Subtract */
+ case Pav_SUB8UM: opc2 =3D 1024; break; // vsububm
+ case Pav_SUB16UM: opc2 =3D 1088; break; // vsubuhm
+ case Pav_SUB32UM: opc2 =3D 1152; break; // vsubuwm
+ case Pav_SUB8US: opc2 =3D 1536; break; // vsububs
+ case Pav_SUB16US: opc2 =3D 1600; break; // vsubuhs
+ case Pav_SUB32US: opc2 =3D 1664; break; // vsubuws
+ case Pav_SUB8SS: opc2 =3D 1792; break; // vsubsbs
+ case Pav_SUB16SS: opc2 =3D 1856; break; // vsubshs
+ case Pav_SUB32SS: opc2 =3D 1920; break; // vsubsws
+
+ /* Multiply odd/even */
+ case Pav_OMUL8U: opc2 =3D 8; break; // vmuloub
+ case Pav_OMUL16U: opc2 =3D 72; break; // vmulouh
+ case Pav_OMUL8S: opc2 =3D 264; break; // vmulosb
+ case Pav_OMUL16S: opc2 =3D 328; break; // vmulosh
+ case Pav_EMUL8U: opc2 =3D 520; break; // vmuleub
+ case Pav_EMUL16U: opc2 =3D 584; break; // vmuleuh
+ case Pav_EMUL8S: opc2 =3D 776; break; // vmulesb
+ case Pav_EMUL16S: opc2 =3D 840; break; // vmulesh
+
+ /* Average */
+ case Pav_AVG8U: opc2 =3D 1026; break; // vavgub
+ case Pav_AVG16U: opc2 =3D 1090; break; // vavguh
+ case Pav_AVG32U: opc2 =3D 1154; break; // vavguw
+ case Pav_AVG8S: opc2 =3D 1282; break; // vavgsb
+ case Pav_AVG16S: opc2 =3D 1346; break; // vavgsh
+ case Pav_AVG32S: opc2 =3D 1410; break; // vavgsw
+
+ /* Maximum */
+ case Pav_MAX8U: opc2 =3D 2; break; // vmaxub
+ case Pav_MAX16U: opc2 =3D 66; break; // vmaxuh
+ case Pav_MAX32U: opc2 =3D 130; break; // vmaxuw
+ case Pav_MAX8S: opc2 =3D 258; break; // vmaxsb
+ case Pav_MAX16S: opc2 =3D 322; break; // vmaxsh
+ case Pav_MAX32S: opc2 =3D 386; break; // vmaxsw
+
+ /* Minimum */
+ case Pav_MIN8U: opc2 =3D 514; break; // vminub
+ case Pav_MIN16U: opc2 =3D 578; break; // vminuh
+ case Pav_MIN32U: opc2 =3D 642; break; // vminuw
+ case Pav_MIN8S: opc2 =3D 770; break; // vminsb
+ case Pav_MIN16S: opc2 =3D 834; break; // vminsh
+ case Pav_MIN32S: opc2 =3D 898; break; // vminsw
+
+ /* Compare (always affects CR field 6) */
+ /* XXX: Actually VXR-Form, but Rc always 0, so keep life easy... *=
/
+ case Pav_CMPEQ8U: opc2 =3D 6; break; // vcmpequb
+ case Pav_CMPEQ16U: opc2 =3D 70; break; // vcmpequh
+ case Pav_CMPEQ32U: opc2 =3D 134; break; // vcmpequw
+ case Pav_CMPGT8U: opc2 =3D 518; break; // vcmpgtub
+ case Pav_CMPGT16U: opc2 =3D 582; break; // vcmpgtuh
+ case Pav_CMPGT32U: opc2 =3D 646; break; // vcmpgtuw
+ case Pav_CMPGT8S: opc2 =3D 774; break; // vcmpgtsb
+ case Pav_CMPGT16S: opc2 =3D 838; break; // vcmpgtsh
+ case Pav_CMPGT32S: opc2 =3D 902; break; // vcmpgtsw
+
+ /* Shift */
+ case Pav_SHL8: opc2 =3D 260; break; // vslb
+ case Pav_SHL16: opc2 =3D 324; break; // vslh
+ case Pav_SHL32: opc2 =3D 388; break; // vslw
+ case Pav_SHL128: opc2 =3D 452; break; // vsl
+ case Pav_SHR8: opc2 =3D 516; break; // vsrb
+ case Pav_SHR16: opc2 =3D 580; break; // vsrh
+ case Pav_SHR32: opc2 =3D 644; break; // vsrw
+ case Pav_SHR128: opc2 =3D 708; break; // vsr
+ case Pav_SAR8: opc2 =3D 772; break; // vsrab
+ case Pav_SAR16: opc2 =3D 836; break; // vsrah
+ case Pav_SAR32: opc2 =3D 900; break; // vsraw
+ case Pav_ROTL8: opc2 =3D 4; break; // vrlb
+ case Pav_ROTL16: opc2 =3D 68; break; // vrlh
+ case Pav_ROTL32: opc2 =3D 132; break; // vrlw
+
+ /* Pack */
+ case Pav_PACKU16UM: opc2 =3D 14; break; // vpkuhum
+ case Pav_PACKU32UM: opc2 =3D 78; break; // vpkuwum
+ case Pav_PACKU16US: opc2 =3D 142; break; // vpkuhus
+ case Pav_PACKU32US: opc2 =3D 206; break; // vpkuwus
+ case Pav_PACKS16US: opc2 =3D 270; break; // vpkshus
+ case Pav_PACKS32US: opc2 =3D 334; break; // vpkswus
+ case Pav_PACKS16SS: opc2 =3D 398; break; // vpkshss
+ case Pav_PACKS32SS: opc2 =3D 462; break; // vpkswss
+ case Pav_PACKPXL: opc2 =3D 782; break; // vpkpx
+
+ /* Merge */
+ case Pav_MRG8HI: opc2 =3D 12; break; // vmrghb
+ case Pav_MRG16HI: opc2 =3D 76; break; // vmrghh
+ case Pav_MRG32HI: opc2 =3D 140; break; // vmrghw
+ case Pav_MRG8LO: opc2 =3D 268; break; // vmrglb
+ case Pav_MRG16LO: opc2 =3D 332; break; // vmrglh
+ case Pav_MRG32LO: opc2 =3D 396; break; // vmrglw
+
+ default:
+ goto bad;
+ }
+ p =3D mkFormVX( p, 4, v_dst, v_srcL, v_srcR, opc2 );
+ goto done;
+ }
+
+ case Pin_AvPerm: { // vperm
+ UInt v_ctl =3D vregNo(i->Pin.AvPerm.ctl);
+ UInt v_dst =3D vregNo(i->Pin.AvPerm.dst);
+ UInt v_srcL =3D vregNo(i->Pin.AvPerm.srcL);
+ UInt v_srcR =3D vregNo(i->Pin.AvPerm.srcR);
+ p =3D mkFormVA( p, 4, v_dst, v_srcL, v_srcR, v_ctl, 43 );
+ goto done;
+ }
+
+ case Pin_AvSel: { // vsel
+ UInt v_ctl =3D vregNo(i->Pin.AvSel.ctl);
+ UInt v_dst =3D vregNo(i->Pin.AvSel.dst);
+ UInt v_srcL =3D vregNo(i->Pin.AvSel.srcL);
+ UInt v_srcR =3D vregNo(i->Pin.AvSel.srcR);
+ p =3D mkFormVA( p, 4, v_dst, v_srcL, v_srcR, v_ctl, 42 );
+ goto done;
+ }
+
+ case Pin_AvShlDbl: { // vsldoi
+ UInt shift =3D i->Pin.AvShlDbl.shift;
+ UInt v_dst =3D vregNo(i->Pin.AvShlDbl.dst);
+ UInt v_srcL =3D vregNo(i->Pin.AvShlDbl.srcL);
+ UInt v_srcR =3D vregNo(i->Pin.AvShlDbl.srcR);
+ vassert(shift <=3D 0xF);
+ p =3D mkFormVA( p, 4, v_dst, v_srcL, v_srcR, shift, 44 );
+ goto done;
+ }
+
+ case Pin_AvSplat: { // vsplt(is)(b,h,w)
+ UInt v_dst =3D vregNo(i->Pin.AvShlDbl.dst);
+ UChar sz =3D i->Pin.AvSplat.sz;
+ UInt v_src, simm_src, opc2;
+ vassert(sz =3D=3D 8 || sz =3D=3D 16 || sz =3D=3D 32);
+
+ if (i->Pin.AvSplat.src->tag =3D=3D Pri_Imm) {
+ opc2 =3D (sz =3D=3D 8) ? 780 : (sz =3D=3D 16) ? 844 : 908; // 8,16,32
+ simm_src =3D i->Pin.AvSplat.src->Pri.Imm.imm32;
+ p =3D mkFormVX( p, 4, v_dst, simm_src, 0, opc2 );
+ } else { // Pri_Reg
+ opc2 =3D (sz =3D=3D 8) ? 524 : (sz =3D=3D 16) ? 588 : 652; // =
8,16,32
+ v_src =3D iregNo(i->Pin.AvSplat.src->Pri.Reg.reg);
+ p =3D mkFormVX( p, 4, v_dst, 0, v_src, opc2 );
+ }
+ goto done;
+ }
+
+ case Pin_AvLdVSCR: { // mtvscr
+ UInt v_src =3D vregNo(i->Pin.AvLdVSCR.src);
+ p =3D mkFormVX( p, 4, 0, 0, v_src, 1604 );
+ goto done;
+ }
+
default:=20
goto bad;
}
Modified: trunk/priv/host-ppc32/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.h 2005-06-28 17:30:56 UTC (rev 1225)
+++ trunk/priv/host-ppc32/hdefs.h 2005-06-28 18:06:23 UTC (rev 1226)
@@ -114,6 +114,38 @@
extern HReg hregPPC32_FPR30 ( void );
extern HReg hregPPC32_FPR31 ( void );
=20
+extern HReg hregPPC32_VR0 ( void );
+extern HReg hregPPC32_VR1 ( void );
+extern HReg hregPPC32_VR2 ( void );
+extern HReg hregPPC32_VR3 ( void );
+extern HReg hregPPC32_VR4 ( void );
+extern HReg hregPPC32_VR5 ( void );
+extern HReg hregPPC32_VR6 ( void );
+extern HReg hregPPC32_VR7 ( void );
+extern HReg hregPPC32_VR8 ( void );
+extern HReg hregPPC32_VR9 ( void );
+extern HReg hregPPC32_VR10 ( void );
+extern HReg hregPPC32_VR11 ( void );
+extern HReg hregPPC32_VR12 ( void );
+extern HReg hregPPC32_VR13 ( void );
+extern HReg hregPPC32_VR14 ( void );
+extern HReg hregPPC32_VR15 ( void );
+extern HReg hregPPC32_VR16 ( void );
+extern HReg hregPPC32_VR17 ( void );
+extern HReg hregPPC32_VR18 ( void );
+extern HReg hregPPC32_VR19 ( void );
+extern HReg hregPPC32_VR20 ( void );
+extern HReg hregPPC32_VR21 ( void );
+extern HReg hregPPC32_VR22 ( void );
+extern HReg hregPPC32_VR23 ( void );
+extern HReg hregPPC32_VR24 ( void );
+extern HReg hregPPC32_VR25 ( void );
+extern HReg hregPPC32_VR26 ( void );
+extern HReg hregPPC32_VR27 ( void );
+extern HReg hregPPC32_VR28 ( void );
+extern HReg hregPPC32_VR29 ( void );
+extern HReg hregPPC32_VR30 ( void );
+extern HReg hregPPC32_VR31 ( void );
=20
#define StackFramePtr hregPPC32_GPR1()
#define GuestStatePtr hregPPC32_GPR31()
@@ -296,6 +328,75 @@
/* --------- */
typedef
enum {
+ Pav_INVALID,
+
+ /* Integer Unary */
+ Pav_MOV, /* Mov */
+ Pav_NOT, /* Bitwise */
+ Pav_UNPCKH8S, Pav_UNPCKH16S, /* Unpack */
+ Pav_UNPCKL8S, Pav_UNPCKL16S,
+ Pav_UNPCKHPIX, Pav_UNPCKLPIX,
+
+ /* Integer Binary */
+ Pav_AND, Pav_OR, Pav_XOR, /* Bitwise */
+
+ Pav_ADD8UM, Pav_ADD16UM, Pav_ADD32UM,
+ Pav_ADD8US, Pav_ADD16US, Pav_ADD32US,
+ Pav_ADD8SS, Pav_ADD16SS, Pav_ADD32SS,
+
+ Pav_SUB8UM, Pav_SUB16UM, Pav_SUB32UM,
+ Pav_SUB8US, Pav_SUB16US, Pav_SUB32US,
+ Pav_SUB8SS, Pav_SUB16SS, Pav_SUB32SS,
+
+ Pav_OMUL8U, Pav_OMUL16U,
+ Pav_OMUL8S, Pav_OMUL16S,
+ Pav_EMUL8U, Pav_EMUL16U,
+ Pav_EMUL8S, Pav_EMUL16S,
+
+ Pav_AVG8U, Pav_AVG16U, Pav_AVG32U,
+ Pav_AVG8S, Pav_AVG16S, Pav_AVG32S,
+ Pav_MAX8U, Pav_MAX16U, Pav_MAX32U,
+ Pav_MAX8S, Pav_MAX16S, Pav_MAX32S,
+ Pav_MIN8U, Pav_MIN16U, Pav_MIN32U,
+ Pav_MIN8S, Pav_MIN16S, Pav_MIN32S,
+
+ /* Compare (always affects CR field 6) */
+ Pav_CMPEQ8U, Pav_CMPEQ16U, Pav_CMPEQ32U,
+ Pav_CMPGT8U, Pav_CMPGT16U, Pav_CMPGT32U,
+ Pav_CMPGT8S, Pav_CMPGT16S, Pav_CMPGT32S,
+
+ /* Shift */
+ Pav_SHL8, Pav_SHL16, Pav_SHL32, Pav_SHL128,
+ Pav_SHR8, Pav_SHR16, Pav_SHR32, Pav_SHR128,
+ Pav_SAR8, Pav_SAR16, Pav_SAR32,
+ Pav_ROTL8, Pav_ROTL16, Pav_ROTL32,
+
+ /* Pack */
+ Pav_PACKU16UM, Pav_PACKU32UM,
+ Pav_PACKU16US, Pav_PACKU32US,
+ Pav_PACKS16US, Pav_PACKS32US,
+ Pav_PACKS16SS, Pav_PACKS32SS, Pav_PACKPXL,
+
+ /* Merge */
+ Pav_MRG8HI, Pav_MRG16HI, Pav_MRG32HI,
+ Pav_MRG8LO, Pav_MRG16LO, Pav_MRG32LO,
+
+//.. /* Floating point binary */
+//.. Xsse_ADDF, Xsse_SUBF, Xsse_MULF, Xsse_DIVF,
+//.. Xsse_MAXF, Xsse_MINF,
+//.. Xsse_CMPEQF, Xsse_CMPLTF, Xsse_CMPLEF, Xsse_CMPUNF,
+//..=20
+//.. /* Floating point unary */
+//.. Xsse_RCPF, Xsse_RSQRTF, Xsse_SQRTF,
+ }
+ PPC32AvOp;
+
+extern HChar* showPPC32AvOp ( PPC32AvOp );
+
+
+/* --------- */
+typedef
+ enum {
Pin_Alu32, /* 32-bit mov/arith/logical */
Pin_Sub32, /* 32-bit mov/arith/logical */
Pin_Sh32, /* 32-bit shift/rotate */
@@ -310,6 +411,7 @@
Pin_Store, /* store a 8|16|32 bit value to mem */
Pin_Set32, /* convert condition code to 32-bit value */
Pin_MFence, /* mem fence (not just sse2, but sse0 and 1 too) *=
/
+
Pin_FpUnary, /* FP unary op */
Pin_FpBinary, /* FP binary op */
Pin_FpLdSt, /* FP load/store */
@@ -318,7 +420,25 @@
Pin_FpCMov, /* FP floating point conditional move */
Pin_FpLdFPSCR, /* mtfsf */
Pin_FpCmp, /* FP compare, generating value into int reg */
- Pin_RdWrLR /* Read/Write Link Register */
+ Pin_RdWrLR, /* Read/Write Link Register */
+
+// Pin_AvConst, /* Generate restricted AV literal */
+ Pin_AvLdSt, /* AV load/store (kludging for AMode_IR) */
+ Pin_AvUnary, /* AV unary general reg=3D>reg */
+ Pin_AvBinary, /* AV binary general reg,reg=3D>reg */
+
+ Pin_AvPerm, /* AV permute (shuffle) */
+ Pin_AvSel, /* AV select */
+ Pin_AvShlDbl, /* AV shift-left double by imm */
+ Pin_AvSplat, /* One elem repeated throughout dst */
+ Pin_AvLdVSCR /* mtvscr */
+
+//.. Xin_SseLdzLO, /* SSE load low 32/64 bits, zero remainder of =
reg */
+//.. Xin_Sse32Fx4, /* SSE binary, 32Fx4 */
+//.. Xin_Sse32FLo, /* SSE binary, 32F in lowest lane only */
+//.. Xin_Sse64Fx2, /* SSE binary, 64Fx2 */
+//.. Xin_Sse64FLo, /* SSE binary, 64F in lowest lane only */
+//.. Xin_SseCMov, /* SSE conditional move */
}
PPC32InstrTag;
=20
@@ -473,6 +593,53 @@
Bool wrLR;
HReg gpr;
} RdWrLR;
+
+ /* Simplistic AltiVec */
+ struct {
+ Bool isLoad;
+ UChar sz; /* 8|16|32|128 */
+ HReg reg;
+ PPC32AMode* addr;
+ } AvLdSt;
+ struct {
+ PPC32AvOp op;
+ HReg dst;
+ HReg src;
+ } AvUnary;
+ struct {
+ PPC32AvOp op;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ } AvBinary;
+ /* Perm,Sel,SlDbl,Splat are all weird AV permutations */
+ struct {
+ HReg ctl;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ } AvPerm;
+ struct {
+ HReg ctl;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ } AvSel;
+ struct {
+ UChar shift;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ } AvShlDbl;
+ struct {
+ UChar sz; /* 8,16,32 */
+ HReg dst;
+ PPC32RI* src;
+ } AvSplat;
+ /* Load AlitVec Status & Control Register */
+ struct {
+ HReg src;
+ } AvLdVSCR;
} Pin;
}
PPC32Instr;
@@ -505,6 +672,14 @@
=20
extern PPC32Instr* PPC32Instr_RdWrLR ( Bool wrLR, HReg gpr );
=20
+extern PPC32Instr* PPC32Instr_AvLdSt ( Bool isLoad, UChar sz, HReg, =
PPC32AMode* );
+extern PPC32Instr* PPC32Instr_AvUnary ( PPC32FpOp op, HReg dst, HReg =
src );
+extern PPC32Instr* PPC32Instr_AvBinary ( PPC32FpOp op, HReg dst, HReg =
srcL, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvPerm ( HReg ctl, HReg dst, HReg srcL=
, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvSel ( HReg ctl, HReg dst, HReg srcL=
, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvShlDbl ( UChar shift, HReg dst, HReg s=
rcL, HReg srcR );
+extern PPC32Instr* PPC32Instr_AvSplat ( UChar sz, HReg dst, PPC32RI* =
src );
+extern PPC32Instr* PPC32Instr_AvLdVSCR ( HReg src );
=20
extern void ppPPC32Instr ( PPC32Instr* );
=20
@@ -514,8 +689,8 @@
extern void mapRegs_PPC32Instr ( HRegRemap*, PPC32Instr* );
extern Bool isMove_PPC32Instr ( PPC32Instr*, HReg*, HReg* )=
;
extern Int emit_PPC32Instr ( UChar* buf, Int nbuf, PPC32=
Instr* );
-extern PPC32Instr* genSpill_PPC32 ( HReg rreg, Int offset );
-extern PPC32Instr* genReload_PPC32 ( HReg rreg, Int offset );
+extern PPC32Instr* genSpill_PPC32 ( HReg rreg, UShort offsetB )=
;
+extern PPC32Instr* genReload_PPC32 ( HReg rreg, UShort offsetB )=
;
extern void getAllocableRegs_PPC32 ( Int*, HReg** );
extern HInstrArray* iselBB_PPC32 ( IRBB*, VexSubArch );
=20
|
|
From: <sv...@va...> - 2005-06-28 17:30:59
|
Author: cerion
Date: 2005-06-28 18:30:56 +0100 (Tue, 28 Jun 2005)
New Revision: 1225
Log:
PPC32 AltiVec reg offsets
Modified:
trunk/pub/libvex_guest_ppc32.h
Modified: trunk/pub/libvex_guest_ppc32.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/pub/libvex_guest_ppc32.h 2005-06-28 17:23:09 UTC (rev 1224)
+++ trunk/pub/libvex_guest_ppc32.h 2005-06-28 17:30:56 UTC (rev 1225)
@@ -114,29 +114,69 @@
/* 368 */ ULong guest_FPR30;
/* 376 */ ULong guest_FPR31;
=20
- /* 384 */ UInt guest_CIA; // IP (no arch visible register)
- /* 388 */ UInt guest_LR; // Link Register
- /* 392 */ UInt guest_CTR; // Count Register
+ // Vector Registers
+ /* 392 */ U128 guest_VR0;
+ /* 408 */ U128 guest_VR1;
+ /* 424 */ U128 guest_VR2;
+ /* 440 */ U128 guest_VR3;
+ /* 456 */ U128 guest_VR4;
+ /* 472 */ U128 guest_VR5;
+ /* 488 */ U128 guest_VR6;
+ /* 504 */ U128 guest_VR7;
+ /* 520 */ U128 guest_VR8;
+ /* 536 */ U128 guest_VR9;
+ /* 552 */ U128 guest_VR10;
+ /* 568 */ U128 guest_VR11;
+ /* 584 */ U128 guest_VR12;
+ /* 600 */ U128 guest_VR13;
+ /* 616 */ U128 guest_VR14;
+ /* 632 */ U128 guest_VR15;
+ /* 648 */ U128 guest_VR16;
+ /* 664 */ U128 guest_VR17;
+ /* 680 */ U128 guest_VR18;
+ /* 696 */ U128 guest_VR19;
+ /* 712 */ U128 guest_VR20;
+ /* 728 */ U128 guest_VR21;
+ /* 744 */ U128 guest_VR22;
+ /* 760 */ U128 guest_VR23;
+ /* 776 */ U128 guest_VR24;
+ /* 792 */ U128 guest_VR25;
+ /* 808 */ U128 guest_VR26;
+ /* 824 */ U128 guest_VR27;
+ /* 840 */ U128 guest_VR28;
+ /* 856 */ U128 guest_VR29;
+ /* 872 */ U128 guest_VR30;
+ /* 888 */ U128 guest_VR31;
=20
+ /* 904 */ UInt guest_CIA; // IP (no arch visible register)
+ /* 908 */ UInt guest_LR; // Link Register
+ /* 912 */ UInt guest_CTR; // Count Register
+
/* CR[7]: thunk used to calculate these flags. */
- /* 396 */ UInt guest_CC_OP;
- /* 400 */ UInt guest_CC_DEP1;
- /* 404 */ UInt guest_CC_DEP2;
+ /* 916 */ UInt guest_CC_OP;
+ /* 920 */ UInt guest_CC_DEP1;
+ /* 924 */ UInt guest_CC_DEP2;
=20
// CR[0:6]: Used for 'compare' ops
- /* 408 */ UInt guest_CR0to6;
+ /* 928 */ UInt guest_CR0to6;
=20
/* FP Status & Control Register fields */
- /* 412 */ UInt guest_FPROUND; // FP Rounding Mode
+ /* 932 */ UInt guest_FPROUND; // FP Rounding Mode
=20
- /* 416 */ UInt guest_XER; // XER Register
+ /* 936 */ UInt guest_XER; // XER Register
=20
+ /* Vector Save/Restore Register */
+ /* 940 */ UInt guest_VRSAVE;
+
+ /* Vector Status and Control Register */
+ /* 944 */ UInt guest_VSCR;
+
/* Emulation warnings */
- /* 420 */ UInt guest_EMWARN;
+ /* 948 */ UInt guest_EMWARN;
=20
/* For icbi: record start and length of area to invalidate */
- /* 424 */ UInt guest_TISTART;
- /* 428 */ UInt guest_TILEN;
+ /* 952 */ UInt guest_TISTART;
+ /* 956 */ UInt guest_TILEN;
=20
/* Padding to make it have an 8-aligned size */
/* UInt padding; */
|
|
From: <sv...@va...> - 2005-06-28 17:24:03
|
Author: cerion
Date: 2005-06-28 18:23:09 +0100 (Tue, 28 Jun 2005)
New Revision: 1224
Log:
AltiVec insn parsing for guest end.
Modified:
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-06-24 11:25:46 UTC (rev 1223)
+++ trunk/priv/guest-ppc32/toIR.c 2005-06-28 17:23:09 UTC (rev 1224)
@@ -36,12 +36,19 @@
/* Translates PPC32 code to IR. */
=20
/* References
- All page references, unless otherwise indicated, refer to IBM's
+
+#define PPC32
"PowerPC Microprocessor Family:
The Programming Environments for 32-Bit Microprocessors"
02/21/2000
http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/852569B20050=
FF778525699600719DF2
=20
+#define AV
+ "PowerPC Microprocessor Family:
+ AltiVec(TM) Technology Programming Environments Manual"
+ 07/10/2003
+ http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/FBFA164F82437=
0F987256D6A006F424D
+
Other refs:
"PowerPC Microprocessor Family:
Programming Environments Manual for 64 and 32-Bit Microprocessors
@@ -109,39 +116,6 @@
/*--- Offsets of various parts of the ppc32 guest state. ---*/
/*------------------------------------------------------------*/
=20
-#define OFFB_GPR0 offsetof(VexGuestPPC32State,guest_GPR0)
-#define OFFB_GPR1 offsetof(VexGuestPPC32State,guest_GPR1)
-#define OFFB_GPR2 offsetof(VexGuestPPC32State,guest_GPR2)
-#define OFFB_GPR3 offsetof(VexGuestPPC32State,guest_GPR3)
-#define OFFB_GPR4 offsetof(VexGuestPPC32State,guest_GPR4)
-#define OFFB_GPR5 offsetof(VexGuestPPC32State,guest_GPR5)
-#define OFFB_GPR6 offsetof(VexGuestPPC32State,guest_GPR6)
-#define OFFB_GPR7 offsetof(VexGuestPPC32State,guest_GPR7)
-#define OFFB_GPR8 offsetof(VexGuestPPC32State,guest_GPR8)
-#define OFFB_GPR9 offsetof(VexGuestPPC32State,guest_GPR9)
-#define OFFB_GPR10 offsetof(VexGuestPPC32State,guest_GPR10)
-#define OFFB_GPR11 offsetof(VexGuestPPC32State,guest_GPR11)
-#define OFFB_GPR12 offsetof(VexGuestPPC32State,guest_GPR12)
-#define OFFB_GPR13 offsetof(VexGuestPPC32State,guest_GPR13)
-#define OFFB_GPR14 offsetof(VexGuestPPC32State,guest_GPR14)
-#define OFFB_GPR15 offsetof(VexGuestPPC32State,guest_GPR15)
-#define OFFB_GPR16 offsetof(VexGuestPPC32State,guest_GPR16)
-#define OFFB_GPR17 offsetof(VexGuestPPC32State,guest_GPR17)
-#define OFFB_GPR18 offsetof(VexGuestPPC32State,guest_GPR18)
-#define OFFB_GPR19 offsetof(VexGuestPPC32State,guest_GPR19)
-#define OFFB_GPR20 offsetof(VexGuestPPC32State,guest_GPR20)
-#define OFFB_GPR21 offsetof(VexGuestPPC32State,guest_GPR21)
-#define OFFB_GPR22 offsetof(VexGuestPPC32State,guest_GPR22)
-#define OFFB_GPR23 offsetof(VexGuestPPC32State,guest_GPR23)
-#define OFFB_GPR24 offsetof(VexGuestPPC32State,guest_GPR24)
-#define OFFB_GPR25 offsetof(VexGuestPPC32State,guest_GPR25)
-#define OFFB_GPR26 offsetof(VexGuestPPC32State,guest_GPR26)
-#define OFFB_GPR27 offsetof(VexGuestPPC32State,guest_GPR27)
-#define OFFB_GPR28 offsetof(VexGuestPPC32State,guest_GPR28)
-#define OFFB_GPR29 offsetof(VexGuestPPC32State,guest_GPR29)
-#define OFFB_GPR30 offsetof(VexGuestPPC32State,guest_GPR30)
-#define OFFB_GPR31 offsetof(VexGuestPPC32State,guest_GPR31)
-
#define OFFB_CIA offsetof(VexGuestPPC32State,guest_CIA)
#define OFFB_LR offsetof(VexGuestPPC32State,guest_LR)
#define OFFB_CTR offsetof(VexGuestPPC32State,guest_CTR)
@@ -156,6 +130,9 @@
=20
#define OFFB_XER offsetof(VexGuestPPC32State,guest_XER)
=20
+#define OFFB_VRSAVE offsetof(VexGuestPPC32State,guest_VRSAVE)
+#define OFFB_VSCR offsetof(VexGuestPPC32State,guest_VSCR)
+
#define OFFB_EMWARN offsetof(VexGuestPPC32State,guest_EMWARN)
=20
#define OFFB_TISTART offsetof(VexGuestPPC32State,guest_TISTART)
@@ -170,7 +147,7 @@
#define SHIFT_XER_SO 31
#define SHIFT_XER_OV 30
#define SHIFT_XER_CA 29
-#define SHIFT_XER_BC 0
+#define SHIFT_XER_BC 0
=20
#define SHIFT_CR_LT 8
#define SHIFT_CR_GT 4
@@ -180,7 +157,10 @@
#define SHIFT_FPSCR_RN 0
#define MASK_FPSCR_RN (3 << SHIFT_FPSCR_RN)
=20
+#define SHIFT_VSCR_NJ 16
+#define SHIFT_VSCR_SAT 0
=20
+
// Special purpose (i.e. non-gpr/fpr) registers
typedef enum {
PPC32_SPR_CIA, // Current Instruction Address
@@ -189,6 +169,8 @@
PPC32_SPR_XER, // Summary Overflow
PPC32_SPR_CR, // Condition Register
PPC32_SPR_FPSCR, // Floating Point Status/Control Register
+ PPC32_SPR_VRSAVE, // Vector Save/Restore Register
+ PPC32_SPR_VSCR, // Vector Status and Control Register
PPC32_SPR_MAX
} PPC32SPR;
=20
@@ -465,6 +447,11 @@
=20
/* Various simple conversions */
=20
+static UChar extend_s_5to8 ( UChar x )
+{
+ return (UChar)((((Int)x) << 27) >> 27);
+}
+
#if 0
static UInt extend_s_8to32( UInt x )
{
@@ -617,6 +604,63 @@
}
=20
=20
+static Int vectorGuestRegOffset ( UInt archreg )
+{
+ vassert(archreg < 32);
+ =20
+ switch (archreg) {
+ case 0: return offsetof(VexGuestPPC32State, guest_VR0);
+ case 1: return offsetof(VexGuestPPC32State, guest_VR1);
+ case 2: return offsetof(VexGuestPPC32State, guest_VR2);
+ case 3: return offsetof(VexGuestPPC32State, guest_VR3);
+ case 4: return offsetof(VexGuestPPC32State, guest_VR4);
+ case 5: return offsetof(VexGuestPPC32State, guest_VR5);
+ case 6: return offsetof(VexGuestPPC32State, guest_VR6);
+ case 7: return offsetof(VexGuestPPC32State, guest_VR7);
+ case 8: return offsetof(VexGuestPPC32State, guest_VR8);
+ case 9: return offsetof(VexGuestPPC32State, guest_VR9);
+ case 10: return offsetof(VexGuestPPC32State, guest_VR10);
+ case 11: return offsetof(VexGuestPPC32State, guest_VR11);
+ case 12: return offsetof(VexGuestPPC32State, guest_VR12);
+ case 13: return offsetof(VexGuestPPC32State, guest_VR13);
+ case 14: return offsetof(VexGuestPPC32State, guest_VR14);
+ case 15: return offsetof(VexGuestPPC32State, guest_VR15);
+ case 16: return offsetof(VexGuestPPC32State, guest_VR16);
+ case 17: return offsetof(VexGuestPPC32State, guest_VR17);
+ case 18: return offsetof(VexGuestPPC32State, guest_VR18);
+ case 19: return offsetof(VexGuestPPC32State, guest_VR19);
+ case 20: return offsetof(VexGuestPPC32State, guest_VR20);
+ case 21: return offsetof(VexGuestPPC32State, guest_VR21);
+ case 22: return offsetof(VexGuestPPC32State, guest_VR22);
+ case 23: return offsetof(VexGuestPPC32State, guest_VR23);
+ case 24: return offsetof(VexGuestPPC32State, guest_VR24);
+ case 25: return offsetof(VexGuestPPC32State, guest_VR25);
+ case 26: return offsetof(VexGuestPPC32State, guest_VR26);
+ case 27: return offsetof(VexGuestPPC32State, guest_VR27);
+ case 28: return offsetof(VexGuestPPC32State, guest_VR28);
+ case 29: return offsetof(VexGuestPPC32State, guest_VR29);
+ case 30: return offsetof(VexGuestPPC32State, guest_VR30);
+ case 31: return offsetof(VexGuestPPC32State, guest_VR31);
+ }
+
+ vpanic("vextorGuestRegOffset(ppc32)"); /*notreached*/
+}
+
+static IRExpr* getVReg ( UInt archreg )
+{
+ vassert(archreg < 32);
+ return IRExpr_Get( vectorGuestRegOffset(archreg), Ity_V128 );
+}
+
+/* Ditto, but write to a reg instead. */
+static void putVReg ( UInt archreg, IRExpr* e )
+{
+ vassert(archreg < 32);
+ vassert(typeOfIRExpr(irbb->tyenv, e) =3D=3D Ity_V128);
+ stmt( IRStmt_Put(vectorGuestRegOffset(archreg), e) );
+}
+
+
static void assign ( IRTemp dst, IRExpr* e )
{
stmt( IRStmt_Tmp(dst, e) );
@@ -896,6 +940,17 @@
break; =20
}
=20
+ case PPC32_SPR_VRSAVE:
+ assign( val, IRExpr_Get(OFFB_VRSAVE, Ity_I32) );
+ break;
+
+ case PPC32_SPR_VSCR:
+ // All other bits are 'Reserved'. Returning zero for these bits.
+ mask =3D mask & 0x00010001;
+ assign( val, IRExpr_Get(OFFB_VSCR, Ity_I32) );
+ break;
+ break;
+
default:
vpanic("getReg(ppc32)");
}
@@ -1040,6 +1095,20 @@
);
}
=20
+ case PPC32_SPR_VRSAVE:
+ stmt( IRStmt_Put( OFFB_VRSAVE, src ) );
+ break;
+
+ case PPC32_SPR_VSCR:
+//CAB: There are only 2 valid bits in VSCR - maybe split into two vars..=
.
+
+ // All other bits are 'Reserved'. Ignoring writes to these bits.
+ assign( src_mskd, binop(Iop_And32, src, mkU32(mask & 0x00010001)) =
);
+ assign( reg_old, getReg_masked( PPC32_SPR_XER, (~mask & 0x00010001=
) ) );
+ stmt( IRStmt_Put( OFFB_VSCR,
+ binop(Iop_Or32, mkexpr(src_mskd), mkexpr(reg_old=
)) ));
+ break;
+
/*
Ignore all other writes
*/
@@ -3136,10 +3205,11 @@
DIP("mfspr r%d,0x%x\n", Rd_addr, SPR_flipped);
=20
switch (SPR_flipped) { // Choose a register...
- case 0x1: putIReg( Rd_addr, getReg( PPC32_SPR_XER ) ); break;
- case 0x8: putIReg( Rd_addr, getReg( PPC32_SPR_LR ) ); break;
- case 0x9: putIReg( Rd_addr, getReg( PPC32_SPR_CTR ) ); break;
- =20
+ case 0x1: putIReg( Rd_addr, getReg( PPC32_SPR_XER ) ); break;
+ case 0x8: putIReg( Rd_addr, getReg( PPC32_SPR_LR ) ); break;
+ case 0x9: putIReg( Rd_addr, getReg( PPC32_SPR_CTR ) ); break;
+ case 0x100: putIReg( Rd_addr, getReg( PPC32_SPR_VRSAVE ) ); break;
+
case 0x012: case 0x013: case 0x016:
case 0x019: case 0x01A: case 0x01B:
case 0x110: case 0x111: case 0x112: case 0x113:
@@ -3185,9 +3255,10 @@
DIP("mtspr 0x%x,r%d\n", SPR_flipped, Rs_addr);
=20
switch (SPR_flipped) { // Choose a register...
- case 0x1: putReg( PPC32_SPR_XER, mkexpr(Rs) ); break;
- case 0x8: putReg( PPC32_SPR_LR, mkexpr(Rs) ); break;
- case 0x9: putReg( PPC32_SPR_CTR, mkexpr(Rs) ); break;
+ case 0x1: putReg( PPC32_SPR_XER, mkexpr(Rs) ); break;
+ case 0x8: putReg( PPC32_SPR_LR, mkexpr(Rs) ); break;
+ case 0x9: putReg( PPC32_SPR_CTR, mkexpr(Rs) ); break;
+ case 0x100: putReg( PPC32_SPR_VRSAVE, mkexpr(Rs) ); break;
=20
case 0x012: case 0x013: case 0x016:
case 0x019: case 0x01A: case 0x01B:
@@ -4280,13 +4351,1290 @@
=20
=20
=20
+/*------------------------------------------------------------*/
+/*--- AltiVec Instruction Translation ---*/
+/*------------------------------------------------------------*/
=20
+/*
+ Altivec Cache Control Instructions (Data Streams)
+*/
+static Bool dis_av_datastream ( UInt theInstr )
+{
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
+ UChar flag_T =3D toUChar((theInstr >> 25) & 0x1); /* theInstr[25] =
*/
+ UChar flag_A =3D toUChar((theInstr >> 25) & 0x1); /* theInstr[25] =
*/
+ UChar b23to24 =3D toUChar((theInstr >> 23) & 0x3); /* theInstr[23:2=
4] */
+ UChar STRM =3D toUChar((theInstr >> 21) & 0x3); /* theInstr[21:2=
2] */
+ UChar rA_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:2=
0] */
+ UChar rB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
+ UInt opc2 =3D (theInstr >> 1) & 0x3FF; /* theInstr[1:10=
] */
+ UChar b0 =3D toUChar((theInstr >> 0) & 1); /* theInstr[0] =
*/
=20
+ if (opc1 !=3D 0x1F || b23to24 !=3D 0 || b0 !=3D 0) {
+ vex_printf("dis_av_datastream(PPC32)(instr)\n");
+ return False;
+ }
=20
+ switch (opc2) {
+ case 0x156: // dst (Data Stream Touch, AV p115)
+ DIP("dst%s r%d,r%d,%d\n", flag_T ? "t" : "", rA_addr, rB_addr, STR=
M);
+ DIP(" =3D> not implemented\n");
+ return False;
=20
+ case 0x176: // dstst (Data Stream Touch for Store, AV p117)
+ DIP("dstst%s r%d,r%d,%d\n", flag_T ? "t" : "", rA_addr, rB_addr, S=
TRM);
+ DIP(" =3D> not implemented\n");
+ return False;
=20
+ case 0x336: // dss (Data Stream Stop, AV p114)
+ if (rA_addr !=3D 0 || rB_addr !=3D 0) {
+ vex_printf("dis_av_datastream(PPC32)(opc2,dst)\n");
+ return False;
+ }
+ if (flag_A =3D=3D 0) {
+ DIP("dss %d\n", STRM);
+ DIP(" =3D> not implemented\n");
+ } else {
+ DIP("dssall\n");
+ DIP(" =3D> not implemented\n");
+ }
+ return False;
=20
+ default:
+ vex_printf("dis_av_datastream(PPC32)(opc2)\n");
+ return False;
+ }
+ return True;
+}
=20
+/*
+ AltiVec Processor Control Instructions
+*/
+static Bool dis_av_procctl ( UInt theInstr )
+{
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
+ UChar vD_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:25=
] */
+ UChar vA_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:20=
] */
+ UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:15=
] */
+ UInt opc2 =3D (theInstr >> 0) & 0x7FF; /* theInstr[0:10=
] */
+
+ if (opc1 !=3D 0x4) {
+ vex_printf("dis_av_procctl(PPC32)(instr)\n");
+ return False;
+ }
+
+ switch (opc2) {
+ case 0x604: // mfvscr (Move from VSCR, AV p129)
+ if (vA_addr !=3D 0 || vB_addr !=3D 0) {
+ vex_printf("dis_av_procctl(PPC32)(opc2,dst)\n");
+ return False;
+ }
+ DIP("mfvscr v%d\n", vD_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x644: // mtvscr (Move to VSCR, AV p130)
+ if (vD_addr !=3D 0 || vA_addr !=3D 0) {
+ vex_printf("dis_av_procctl(PPC32)(opc2,dst)\n");
+ return False;
+ }
+ DIP("mtvscr v%d\n", vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ vex_printf("dis_av_procctl(PPC32)(opc2)\n");
+ return False;
+ }
+ return True;
+}
+
+/*
+ AltiVec Load Instructions
+*/
+static Bool dis_av_load ( UInt theInstr )
+{
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
+ UChar vD_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
+ UChar rA_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:2=
0] */
+ UChar rB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
+ UInt opc2 =3D (theInstr >> 1) & 0x3FF; /* theInstr[1:10=
] */
+ UChar b0 =3D toUChar((theInstr >> 0) & 1); /* theInstr[0] =
*/
+
+ if (opc1 !=3D 0x1F || b0 !=3D 0) {
+ vex_printf("dis_av_load(PPC32)(instr)\n");
+ return False;
+ }
+
+ switch (opc2) {
+
+ case 0x006: // lvsl (Load Vector for Shift Left, AV p123)
+ DIP("lvsl v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x026: // lvsr (Load Vector for Shift Right, AV p125)
+ DIP("lvsr v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x007: // lvebx (Load Vector Element Byte Indexed, AV p119)
+ DIP("lvebx v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x027: // lvehx (Load Vector Element Half Word Indexed, AV p121)
+ DIP("lvehx v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x047: // lvewx (Load Vector Element Word Indexed, AV p122)
+ DIP("lvewx v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x067: // lvx (Load Vector Indexed, AV p127)
+ DIP("lvx v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x167: // lvxl (Load Vector Indexed LRU, AV p128)
+ // XXX: lvxl gives explicit control over cache block replacement
+ DIP("lvxl v%d,r%d,r%d\n", vD_addr, rA_addr, rB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ vex_printf("dis_av_load(PPC32)(opc2)\n");
+ return False;
+ }
+ return True;
+}
+
+/*
+ AltiVec Store Instructions
+*/
+static Bool dis_av_store ( UInt theInstr )
+{
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
+ UChar vS_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
+ UChar rA_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:2=
0] */
+ UChar rB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
+ UInt opc2 =3D (theInstr >> 1) & 0x3FF; /* theInstr[1:10=
] */
+ UChar b0 =3D toUChar((theInstr >> 0) & 1); /* theInstr[0] =
*/
+
+ IRTemp rA =3D newTemp(Ity_I32);
+ IRTemp rB =3D newTemp(Ity_I32);
+ IRTemp vS =3D newTemp(Ity_V128);
+ IRTemp EA =3D newTemp(Ity_I32);
+ IRTemp EA_aligned =3D newTemp(Ity_I32);
+
+ assign( rA, getIReg(rA_addr));
+ assign( rB, getIReg(rB_addr));
+ assign( vS, getVReg(vS_addr));
+
+ if (rA_addr =3D=3D 0) {
+ assign( EA, mkexpr(rB) );
+ } else {
+ assign( EA, binop(Iop_Add32, mkexpr(rA), mkexpr(rB)) );
+ }
+
+ if (opc1 !=3D 0x1F || b0 !=3D 0) {
+ vex_printf("dis_av_store(PPC32)(instr)\n");
+ return False;
+ }
+
+ switch (opc2) {
+ case 0x087: // stvebx (Store Vector Byte Indexed, AV p131)
+ DIP("stvebx v%d,r%d,r%d\n", vS_addr, rA_addr, rB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+// eb =3D EA & 0xF;
+// STORE(vS[eb*8:eb*8+7], 1, EA);
+// storeBE( mkexpr(EA), mkexpr(vS) );
+
+ case 0x0A7: // stvehx (Store Vector Half Word Indexed, AV p132)
+ DIP("stvehx v%d,r%d,r%d\n", vS_addr, rA_addr, rB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+// EA_aligned =3D EA & 0xFFFF_FFFE
+// eb =3D EA_aligned & 0xF;
+// STORE(vS[eb*8:eb*8+15], 2, EA_aligned);
+
+ case 0x0C7: // stvewx (Store Vector Word Indexed, AV p133)
+ DIP("stvewx v%d,r%d,r%d\n", vS_addr, rA_addr, rB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+// EA_aligned =3D EA & 0xFFFF_FFFC
+// eb =3D EA_aligned & 0xF;
+// STORE(vS[eb*8:eb*8+31], 4, EA_aligned);
+
+ case 0x0E7: // stvx (Store Vector Indexed, AV p134)
+ DIP("stvx v%d,r%d,r%d\n", vS_addr, rA_addr, rB_addr);
+ assign( EA_aligned, binop( Iop_And32, mkexpr(EA), mkU32(0xFFFFFFF0=
) ));
+ storeBE( mkexpr(EA_aligned), mkexpr(vS) );
+ break;
+
+ case 0x1E7: // stvxl (Store Vector Indexed LRU, AV p135)
+ // XXX: stvxl can give explicit control over cache block replacemen=
t
+ DIP("stvxl v%d,r%d,r%d\n", vS_addr, rA_addr, rB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+// EA_aligned =3D EA & 0xFFFF_FFF0;
+// STORE(vS, 16, EA);
+
+ default:
+ vex_printf("dis_av_store(PPC32)(opc2)\n");
+ return False;
+ }
+ return True;
+}
+
+/*
+ AltiVec Arithmetic Instructions
+*/
+static Bool dis_av_arith ( UInt theInstr )
+{
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
+ UChar vD_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
+ UChar vA_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:2=
0] */
+ UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
+ UInt opc2 =3D (theInstr >> 0) & 0x7FF; /* theInstr[0:10=
] */
+
+ if (opc1 !=3D 0x4) {
+ vex_printf("dis_av_arith(PPC32)(opc1 !=3D 0x4)\n");
+ return False;
+ }
+
+ switch (opc2) {
+ /* Add */
+ case 0x180: // vaddcuw (Add Carryout Unsigned Word, AV p136)
+ DIP("vaddcuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x000: // vaddubm (Add Unsigned Byte Modulo, AV p141)
+ DIP("vaddubm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x040: // vadduhm (Add Unsigned Half Word Modulo, AV p143)
+ DIP("vadduhm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x080: // vadduwm (Add Unsigned Word Modulo, AV p145)
+ DIP("vadduwm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x200: // vaddubs (Add Unsigned Byte Saturate, AV p142)
+ DIP("vaddubs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x240: // vadduhs (Add Unsigned Half Word Saturate, AV p144)
+ DIP("vadduhs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x280: // vadduws (Add Unsigned Word Saturate, AV p146)
+ DIP("vadduws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x300: // vaddsbs (Add Signed Byte Saturate, AV p138)
+ DIP("vaddsbs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x340: // vaddshs (Add Signed Half Word Saturate, AV p139)
+ DIP("vaddshs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x380: // vaddsws (Add Signed Word Saturate, AV p140)
+ DIP("vaddsws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ /* Subtract */
+ case 0x580: // vsubcuw (Subtract Carryout Unsigned Word, AV p260)
+ DIP("vsubcuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x400: // vsububm (Subtract Unsigned Byte Modulo, AV p265)
+ DIP("vsububm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x440: // vsubuhm (Subtract Unsigned Half Word Modulo, AV p267)
+ DIP("vsubuhm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x480: // vsubuwm (Subtract Unsigned Word Modulo, AV p269)
+ DIP("vsubuwm v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x600: // vsububs (Subtract Unsigned Byte Saturate, AV p266)
+ DIP("vsububs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x640: // vsubuhs (Subtract Unsigned Half Word Saturate, AV p268=
)
+ DIP("vsubuhs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x680: // vsubuws (Subtract Unsigned Word Saturate, AV p270)
+ DIP("vsubuws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x700: // vsubsbs (Subtract Signed Byte Saturate, AV p262)
+ DIP("vsubsbs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x740: // vsubshs (Subtract Signed Half Word Saturate, AV p263)
+ DIP("vsubshs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x780: // vsubsws (Subtract Signed Word Saturate, AV p264)
+ DIP("vsubsws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+
+ /* Maximum */
+ case 0x002: // vmaxub (Maximum Unsigned Byte, AV p182)
+ DIP("vmaxub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x042: // vmaxuh (Maximum Unsigned Half Word, AV p183)
+ DIP("vmaxuh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x082: // vmaxuw (Maximum Unsigned Word, AV p184)
+ DIP("vmaxuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x102: // vmaxsb (Maximum Signed Byte, AV p179)
+ DIP("vmaxsb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x142: // vmaxsh (Maximum Signed Half Word, AV p180)
+ DIP("vmaxsh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x182: // vmaxsw (Maximum Signed Word, AV p181)
+ DIP("vmaxsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+
+ /* Minimum */
+ case 0x202: // vminub (Minimum Unsigned Byte, AV p191)
+ DIP("vminub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x242: // vminuh (Minimum Unsigned Half Word, AV p192)
+ DIP("vminuh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x282: // vminuw (Minimum Unsigned Word, AV p193)
+ DIP("vminuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x302: // vminsb (Minimum Signed Byte, AV p188)
+ DIP("vminsb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x342: // vminsh (Minimum Signed Half Word, AV p189)
+ DIP("vminsh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x382: // vminsw (Minimum Signed Word, AV p190)
+ DIP("vminsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+
+ /* Average */
+ case 0x402: // vavgub (Average Unsigned Byte, AV p152)
+ DIP("vavgub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x442: // vavguh (Average Unsigned Half Word, AV p153)
+ DIP("vavguh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x482: // vavguw (Average Unsigned Word, AV p154)
+ DIP("vavguw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x502: // vavgsb (Average Signed Byte, AV p149)
+ DIP("vavgsb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x542: // vavgsh (Average Signed Half Word, AV p150)
+ DIP("vavgsh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x582: // vavgsw (Average Signed Word, AV p151)
+ DIP("vavgsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+
+ /* Multiply */
+ case 0x008: // vmuloub (Multiply Odd Unsigned Byte, AV p213)
+ DIP("vmuloub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x048: // vmulouh (Multiply Odd Unsigned Half Word, AV p214)
+ DIP("vmulouh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x108: // vmulosb (Multiply Odd Signed Byte, AV p211)
+ DIP("vmulosb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x148: // vmulosh (Multiply Odd Signed Half Word, AV p212)
+ DIP("vmulosh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x208: // vmuleub (Multiply Even Unsigned Byte, AV p209)
+ DIP("vmuleub v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x248: // vmuleuh (Multiply Even Unsigned Half Word, AV p210)
+ DIP("vmuleuh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x308: // vmulesb (Multiply Even Signed Byte, AV p207)
+ DIP("vmulesb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x348: // vmulesh (Multiply Even Signed Half Word, AV p208)
+ DIP("vmulesh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+
+ /* Sum Across Partial */
+ case 0x608: // vsum4ubs (Sum Partial (1/4) UB Saturate, AV p275)
+ DIP("vsum4ubs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x708: // vsum4sbs (Sum Partial (1/4) SB Saturate, AV p273)
+ DIP("vsum4sbs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x648: // vsum4shs (Sum Partial (1/4) SHW Saturate, AV p274)
+ DIP("vsum4shs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x688: // vsum2sws (Sum Partial (1/2) SW Saturate, AV p272)
+ DIP("vsum2sws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x788: // vsumsws (Sum SW Saturate, AV p271)
+ DIP("vsumsws v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ vex_printf("dis_av_arith(PPC32)(opc2=3D0x%x)\n", opc2);
+ return False;
+ }
+ return True;
+}
+
+/*
+ AltiVec Logic Instructions
+*/
+static Bool dis_av_logic ( UInt theInstr )
+{
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
+ UChar vD_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
+ UChar vA_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:2=
0] */
+ UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
+ UInt opc2 =3D (theInstr >> 0) & 0x7FF; /* theInstr[0:10=
] */
+
+ if (opc1 !=3D 0x4) {
+ vex_printf("dis_av_logic(PPC32)(opc1 !=3D 0x4)\n");
+ return False;
+ }
+
+ switch (opc2) {
+ case 0x404: // vand (And, AV p147)
+ DIP("vand v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x444: // vandc (And, AV p148)
+ DIP("vandc v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x484: // vor (Or, AV p217)
+ DIP("vor v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x4C4: // vxor (Xor, AV p282)
+ DIP("vxor v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x504: // vnor (Nor, AV p216)
+ DIP("vnor v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ vex_printf("dis_av_logic(PPC32)(opc2=3D0x%x)\n", opc2);
+ return False;
+ }
+ return True;
+}
+
+/*
+ AltiVec Compare Instructions
+*/
+static Bool dis_av_cmp ( UInt theInstr )
+{
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
+ UChar vD_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
+ UChar vA_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:2=
0] */
+ UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
+ UChar flag_Rc =3D toUChar((theInstr >> 10) & 0x1); /* theInstr[10] =
*/
+ UInt opc2 =3D (theInstr >> 0) & 0x3FF; /* theInstr[0:9]=
*/
+
+ if (opc1 !=3D 0x4) {
+ vex_printf("dis_av_cmp(PPC32)(instr)\n");
+ return False;
+ }
+
+ switch (opc2) {
+ case 0x006: // vcmpequb (Compare Equal-to Unsigned B, AV p160)
+ DIP("vcmpequb%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x046: // vcmpequh (Compare Equal-to Unsigned HW, AV p161)
+ DIP("vcmpequh%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x086: // vcmpequw (Compare Equal-to Unsigned W, AV p162)
+ DIP("vcmpequw%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x206: // vcmpgtub (Compare Greater-than Unsigned B, AV p168)
+ DIP("vcmpgtub%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x246: // vcmpgtuh (Compare Greater-than Unsigned HW, AV p169)
+ DIP("vcmpgtuh%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x286: // vcmpgtuw (Compare Greater-than Unsigned W, AV p170)
+ DIP("vcmpgtuw%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x306: // vcmpgtsb (Compare Greater-than Signed B, AV p165)
+ DIP("vcmpgtsb%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x346: // vcmpgtsh (Compare Greater-than Signed HW, AV p166)
+ DIP("vcmpgtsh%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x386: // vcmpgtsw (Compare Greater-than Signed W, AV p167)
+ DIP("vcmpgtsw%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ vex_printf("dis_av_cmp(PPC32)(opc2)\n");
+ return False;
+ }
+ return True;
+}
+
+/*
+ AltiVec Multiply-Sum Instructions
+*/
+static Bool dis_av_multarith ( UInt theInstr )
+{
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
+ UChar vD_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
+ UChar vA_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:2=
0] */
+ UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
+ UChar vC_addr =3D toUChar((theInstr >> 6) & 0x1F); /* theInstr[6:10=
] */
+ UChar opc2 =3D toUChar((theInstr >> 0) & 0x3F); /* theInstr[0:5]=
*/
+
+ if (opc1 !=3D 0x4) {
+ vex_printf("dis_av_multarith(PPC32)(instr)\n");
+ return False;
+ }
+
+ switch (opc2) {
+
+ /* Multiply-Add */
+ case 0x20: // vmhaddshs (Multiply High, Add Signed HW Saturate, AV p1=
85)
+ DIP("vmhaddshs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_a=
ddr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x21: // vmhraddshs (Multiply High Round, Add Signed HW Saturate=
, AV p186)
+ DIP("vmhraddshs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_=
addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x22: // vmladduhm (Multiply Low, Add Unsigned HW Modulo, AV p19=
4)
+ DIP("vmladduhm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_a=
ddr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+
+ /* Multiply-Sum */
+ case 0x24: // vmsumubm (Multiply Sum Unsigned B Modulo, AV p204)
+ DIP("vmsumubm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x25: // vmsummbm (Multiply Sum Mixed-Sign B Modulo, AV p201)
+ DIP("vmsummbm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x26: // vmsumuhm (Multiply Sum Unsigned HW Modulo, AV p205)
+ DIP("vmsumuhm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x27: // vmsumuhs (Multiply Sum Unsigned HW Saturate, AV p206)
+ DIP("vmsumuhs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x28: // vmsumshm (Multiply Sum Signed HW Modulo, AV p202)
+ DIP("vmsumshm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x29: // vmsumshs (Multiply Sum Signed HW Saturate, AV p203)
+ DIP("vmsumshs v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_ad=
dr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ vex_printf("dis_av_multarith(PPC32)(opc2)\n");
+ return False;
+ }
+ return True;
+}
+
+/*
+ AltiVec Shift/Rotate Instructions
+*/
+static Bool dis_av_shift ( UInt theInstr )
+{
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:31=
] */
+ UChar vD_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:25=
] */
+ UChar vA_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:20=
] */
+ UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:15=
] */
+ UInt opc2 =3D (theInstr >> 0) & 0x7FF; /* theInstr[0:10]=
*/
+
+ if (opc1 !=3D 0x4){
+ vex_printf("dis_av_shift(PPC32)(instr)\n");
+ return False;
+ }
+
+ switch (opc2) {
+ /* Rotate */
+ case 0x004: // vrlb (Rotate Left Integer B, AV p234)
+ DIP("vrlb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x044: // vrlh (Rotate Left Integer HW, AV p235)
+ DIP("vrlh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x084: // vrlw (Rotate Left Integer W, AV p236)
+ DIP("vrlw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+
+ /* Shift Left */
+ case 0x104: // vslb (Shift Left Integer B, AV p240)
+ DIP("vslb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x144: // vslh (Shift Left Integer HW, AV p242)
+ DIP("vslh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x184: // vslw (Shift Left Integer W, AV p244)
+ DIP("vslw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x1C4: // vsl (Shift Left, AV p239)
+ DIP("vsl v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x40C: // vslo (Shift Left by Octet, AV p243)
+ DIP("vslo v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ /* Shift Right */
+ case 0x204: // vsrb (Shift Right B, AV p256)
+ DIP("vsrb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x244: // vsrh (Shift Right HW, AV p257)
+ DIP("vsrh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x284: // vsrw (Shift Right W, AV p259)
+ DIP("vsrw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x2C4: // vsr (Shift Right, AV p252)
+ DIP("vsr v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x304: // vsrab (Shift Right Algebraic B, AV p253)
+ DIP("vsrab v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x344: // vsrah (Shift Right Algebraic HW, AV p254)
+ DIP("vsrah v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x384: // vsraw (Shift Right Algebraic W, AV p255)
+ DIP("vsraw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x44C: // vsro (Shift Right by Octet, AV p258)
+ DIP("vsro v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ vex_printf("dis_av_shift(PPC32)(opc2)\n");
+ return False;
+ }
+ return True;
+}
+
+/*
+ AltiVec Permute Instructions
+*/
+static Bool dis_av_permute ( UInt theInstr )
+{
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:=
31] */
+ UChar vD_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:=
25] */
+ UChar vA_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:=
20] */
+ UChar UIMM_5 =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:=
20] */
+ UChar SIMM_5 =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:=
20] */
+ UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:=
15] */
+ UChar vC_addr =3D toUChar((theInstr >> 6) & 0x1F); /* theInstr[6:1=
0] */
+ UChar b10 =3D toUChar((theInstr >> 10) & 0x1); /* theInstr[10]=
*/
+ UChar SHB_uimm4 =3D toUChar((theInstr >> 6) & 0xF); /* theInstr[6:9=
] */
+ UInt opc2 =3D (theInstr >> 0) & 0x3F; /* theInstr[0:5=
] */
+
+ UChar SIMM_8 =3D extend_s_5to8(SIMM_5);
+
+ if (opc1 !=3D 0x4) {
+ vex_printf("dis_av_permute(PPC32)(instr)\n");
+ return False;
+ }
+
+ switch (opc2) {
+ case 0x2A: // vsel (Conditional Select, AV p238)
+ DIP("vsel v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+ =20
+ case 0x2B: // vperm (Permute, AV p218)
+ DIP("vperm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr)=
;
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x2C: // vsldoi (Shift Left Double by Octet Imm, AV p241)
+ if (b10 !=3D 0) {
+ vex_printf("dis_av_permute(PPC32)(vsldoi)\n");
+ return False;
+ }
+ DIP("vsldoi v%d,v%d,v%d,%u\n", vD_addr, vA_addr, vB_addr, SHB_uimm=
4);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ break; // Fall through...
+ }
+
+ opc2 =3D (theInstr) & 0x7FF; /* theInstr[0:10] */
+ switch (opc2) {
+
+ /* Merge */
+ case 0x00C: // vmrghb (Merge High B, AV p195)
+ DIP("vmrghb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x04C: // vmrghh (Merge High HW, AV p196)
+ DIP("vmrghh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x08C: // vmrghw (Merge High W, AV p197)
+ DIP("vmrghw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x10C: // vmrglb (Merge Low B, AV p198)
+ DIP("vmrglb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x14C: // vmrglh (Merge Low HW, AV p199)
+ DIP("vmrglh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x18C: // vmrglw (Merge Low W, AV p200)
+ DIP("vmrglw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ /* Splat */
+ case 0x20C: // vspltb (Splat Byte, AV p245)
+ DIP("vspltb v%d,v%d,%u\n", vD_addr, vB_addr, UIMM_5);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x24C: // vsplth (Splat Half Word, AV p246)
+ DIP("vsplth v%d,v%d,%u\n", vD_addr, vB_addr, UIMM_5);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x28C: // vspltw (Splat Word, AV p250)
+ DIP("vspltw v%d,v%d,%u\n", vD_addr, vB_addr, UIMM_5);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x30C: // vspltisb (Splat Immediate Signed B, AV p247)
+ DIP("vspltisb v%d,%d\n", vD_addr, (Char)SIMM_8);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x34C: // vspltish (Splat Immediate Signed HW, AV p248)
+ DIP("vspltish v%d,%d\n", vD_addr, (Char)SIMM_8);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x38C: // vspltisw (Splat Immediate Signed W, AV p249)
+ DIP("vspltisw v%d,%d\n", vD_addr, (Char)SIMM_8);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ vex_printf("dis_av_permute(PPC32)(opc2)\n");
+ return False;
+ }
+ return True;
+}
+
+/*
+ AltiVec Pack/Unpack Instructions
+*/
+static Bool dis_av_pack ( UInt theInstr )
+{
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
+ UChar vD_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
+ UChar vA_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:2=
0] */
+ UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
+ UInt opc2 =3D (theInstr >> 0) & 0x7FF; /* theInstr[0:10=
] */
+
+ if (opc1 !=3D 0x4) {
+ vex_printf("dis_av_pack(PPC32)(instr)\n");
+ return False;
+ }
+
+ switch (opc2) {
+ /* Packing */
+ case 0x00E: // vpkuhum (Pack Unsigned HW Unsigned Modulo, AV p224)
+ DIP("vpkuhum v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x04E: // vpkuwum (Pack Unsigned W Unsigned Modulo, AV p226)
+ DIP("vpkuwum v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x08E: // vpkuhus (Pack Unsigned HW Unsigned Saturate, AV p225)
+ DIP("vpkuhus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x0CE: // vpkuwus (Pack Unsigned W Unsigned Saturate, AV p227)
+ DIP("vpkuwus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x10E: // vpkshus (Pack Signed HW Unsigned Saturate, AV p221)
+ DIP("vpkshus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x14E: // vpkswus (Pack Signed W Unsigned Saturate, AV p223)
+ DIP("vpkswus v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x18E: // vpkshss (Pack Signed HW Signed Saturate, AV p220)
+ DIP("vpkshss v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x1CE: // vpkswss (Pack Signed W Signed Saturate, AV p222)
+ DIP("vpkswss v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x30E: // vpkpx (Pack Pixel, AV p219)
+ DIP("vpkpx v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ break; // Fall through...
+ }
+
+
+ if (vA_addr !=3D 0) {
+ vex_printf("dis_av_pack(PPC32)(vA_addr)\n");
+ return False;
+ }
+
+ switch (opc2) {
+ /* Unpacking */
+ case 0x20E: // vupkhsb (Unpack High Signed B, AV p277)
+ DIP("vupkhsb v%d,v%d\n", vD_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x24E: // vupkhsh (Unpack High Signed HW, AV p278)
+ DIP("vupkhsh v%d,v%d\n", vD_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x28E: // vupklsb (Unpack Low Signed B, AV p280)
+ DIP("vupklsb v%d,v%d\n", vD_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x2CE: // vupklsh (Unpack Low Signed HW, AV p281)
+ DIP("vupklsh v%d,v%d\n", vD_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x34E: // vupkhpx (Unpack High Pixel16, AV p276)
+ DIP("vupkhpx v%d,v%d\n", vD_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x3CE: // vupklpx (Unpack Low Pixel16, AV p279)
+ DIP("vupklpx v%d,v%d\n", vD_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ vex_printf("dis_av_pack(PPC32)(opc2)\n");
+ return False;
+ }
+ return True;
+}
+
+
+/*
+ AltiVec Floating Point Arithmetic Instructions
+*/
+static Bool dis_av_fp_arith ( UInt theInstr )
+{
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
+ UChar vD_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
+ UChar vA_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:2=
0] */
+ UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
+ UChar vC_addr =3D toUChar((theInstr >> 6) & 0x1F); /* theInstr[6:10=
] */
+ UInt opc2=3D0;
+
+ if (opc1 !=3D 0x4) {
+ vex_printf("dis_av_fp_arith(PPC32)(instr)\n");
+ return False;
+ }
+
+ opc2 =3D (theInstr) & 0x3F; /* theInstr[0:5] */
+ switch (opc2) {
+ case 0x2E: // vmaddfp (Multiply Add FP, AV p177)
+ DIP("vmaddfp v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vC_addr, vB_add=
r);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x2F: // vnmsubfp (Negative Multiply-Subtract FP, AV p215)
+ DIP("vnmsubfp v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vC_addr, vB_ad=
dr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ break; // Fall through...
+ }
+
+ opc2 =3D (theInstr) & 0x7FF; /* theInstr[0:10] */
+ switch (opc2) {
+ case 0x00A: // vaddfp (Add FP, AV p137)
+ DIP("vaddfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x04A: // vsubfp (Subtract FP, AV p261)
+ DIP("vsubfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x40A: // vmaxfp (Maximum FP, AV p178)
+ DIP("vmaxfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x44A: // vminfp (Minimum FP, AV p187)
+ DIP("vminfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ break; // Fall through...
+ }
+
+
+ if (vA_addr !=3D 0) {
+ vex_printf("dis_av_fp_arith(PPC32)(vA_addr)\n");
+ return False;
+ }
+
+ switch (opc2) {
+ case 0x10A: // vrefp (Reciprocal Esimate FP, AV p228)
+ DIP("vrefp v%d,v%d\n", vD_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x14A: // vrsqrtefp (Reciprocal Square Root Estimate FP, AV p237=
)
+ DIP("vrsqrtefp v%d,v%d\n", vD_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x18A: // vexptefp (2 Raised to the Exp Est FP, AV p173)
+ DIP("vexptefp v%d,v%d\n", vD_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x1CA: // vlogefp (Log2 Estimate FP, AV p175)
+ DIP("vlogefp v%d,v%d\n", vD_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ vex_printf("dis_av_fp_arith(PPC32)(opc2=3D0x%x)\n",opc2);
+ return False;
+ }
+ return True;
+}
+
+/*
+ AltiVec Floating Point Compare Instructions
+*/
+static Bool dis_av_fp_cmp ( UInt theInstr )
+{
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
+ UChar vD_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
+ UChar vA_addr =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:2=
0] */
+ UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
+ UChar flag_Rc =3D toUChar((theInstr >> 10) & 0x1); /* theInstr[10] =
*/
+ UInt opc2 =3D (theInstr >> 0) & 0x3FF; /* theInstr[0:9]=
*/
+
+ if (opc1 !=3D 0x4) {
+ vex_printf("dis_av_fp_cmp(PPC32)(instr)\n");
+ return False;
+ }
+
+ switch (opc2) {
+ case 0x0C6: // vcmpeqfp (Compare Equal-to FP, AV p159)
+ DIP("vcmpeqfp%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x1C6: // vcmpgefp (Compare Greater-than-or-Equal-to FP, AV p163=
)
+ DIP("vcmpgefp%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x2C6: // vcmpgtfp (Compare Greater-than FP, AV p164)
+ DIP("vcmpgtfp%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_ad=
dr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x3C6: // vcmpbfp (Compare Bounds FP, AV p157)
+ DIP("vcmpbfp%s v%d,v%d,v%d\n", (flag_Rc ? ".":""), vD_addr, vA_add=
r, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ vex_printf("dis_av_fp_cmp(PPC32)(opc2)\n");
+ return False;
+ }
+ return True;
+}
+
+/*
+ AltiVec Floating Point Convert/Round Instructions
+*/
+static Bool dis_av_fp_convert ( UInt theInstr )
+{
+ UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:3=
1] */
+ UChar vD_addr =3D toUChar((theInstr >> 21) & 0x1F); /* theInstr[21:2=
5] */
+ UChar UIMM_5 =3D toUChar((theInstr >> 16) & 0x1F); /* theInstr[16:2=
0] */
+ UChar vB_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:1=
5] */
+ UInt opc2 =3D (theInstr >> 0) & 0x7FF; /* theInstr[0:10=
] */
+
+ if (opc1 !=3D 0x4) {
+ vex_printf("dis_av_fp_convert(PPC32)(instr)\n");
+ return False;
+ }
+
+ switch (opc2) {
+ case 0x30A: // vcfux (Convert from Unsigned Fixed-Point W, AV p156)
+ DIP("vcfux v%d,v%d,%u\n", vD_addr, vB_addr, UIMM_5);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x34A: // vcfsx (Convert from Signed Fixed-Point W, AV p155)
+ DIP("vcfsx v%d,v%d,%u\n", vD_addr, vB_addr, UIMM_5);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x38A: // vctuxs (Convert to Unsigned Fixed-Point W Saturate, AV=
p172)
+ DIP("vctuxs v%d,v%d,%u\n", vD_addr, vB_addr, UIMM_5);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x3CA: // vctsxs (Convert to Signed Fixed-Point W Saturate, AV p=
171)
+ DIP("vctsxs v%d,v%d,%u\n", vD_addr, vB_addr, UIMM_5);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ break; // Fall through...
+ }
+
+ if (UIMM_5 !=3D 0) {
+ vex_printf("dis_av_fp_convert(PPC32)(UIMM_5)\n");
+ return False;
+ }
+
+ switch (opc2) {
+ case 0x20A: // vrfin (Round to FP Integer Nearest, AV p231)
+ DIP("vrfin v%d,v%d\n", vD_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x24A: // vrfiz (Round to FP Integer toward zero, AV p233)
+ DIP("vrfiz v%d,v%d\n", vD_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x28A: // vrfip (Round to FP Integer toward +inf, AV p232)
+ DIP("vrfip v%d,v%d\n", vD_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ case 0x2CA: // vrfim (Round to FP Integer toward -inf, AV p230)
+ DIP("vrfim v%d,v%d\n", vD_addr, vB_addr);
+ DIP(" =3D> not implemented\n");
+ return False;
+
+ default:
+ vex_printf("dis_av_fp_convert(PPC32)(opc2)\n");
+ return False;
+ }
+ return True;
+}
+
+
+
+
+
+
/*------------------------------------------------------------*/
/*--- Disassemble a single instruction ---*/
/*------------------------------------------------------------*/
@@ -4558,6 +5906,7 @@
case 0x0C8: // subfze
if (dis_int_arith( theInstr )) goto decode_success;
goto decode_failure;
+
default:
break; // Fall through...
}
@@ -4636,7 +5985,7 @@
goto decode_failure;
=20
/* Trap Instructions */
- case 0x004: // tw
+ case 0x004: // tw
DIP("trap op (tw) =3D> not implemented\n");
goto decode_failure;
=20
@@ -4652,16 +6001,172 @@
if (dis_fp_store( theInstr )) goto decode_success;
goto decode_failure;
=20
+
/* AltiVec instructions */
- case 0x0E7: // stvx
- DIP("Altivec op (stvx) =3D> not implemented\n");
+
+ /* AV Cache Control - Data streams */
+ case 0x156: case 0x176: case 0x336: // dst, dstst, dss
+ if (dis_av_datastream( theInstr )) goto decode_success;
goto decode_failure;
=20
+ /* AV Load */
+ case 0x006: case 0x026: // lvsl, lvsr
+ case 0x007: case 0x027: case 0x047: // lvebx, lvehx, lvewx
+ case 0x067: case 0x167: // lvx, lvxl
+ if (dis_av_load( theInstr )) goto decode_success;
+ goto decode_failure;
+
+ /* AV Store */
+ case 0x087: case 0x0A7: case 0x0C7: // stvebx, stvehx, stvewx
+ case 0x0E7: case 0x1E7: // stvx, stvxl
+ if (dis_av_store( theInstr )) goto decode_success;
+ goto decode_failure;
+
default:
goto decode_failure;
}
break;
=20
+
+ case 0x04:
+ /* AltiVec instructions */
+
+ opc2 =3D (theInstr) & 0x3F; /* theInstr[0:5] */
+ switch (opc2) {
+ /* AV Mult-Add, Mult-Sum */
+ case 0x20: case 0x21: case 0x22: // vmhaddshs, vmhraddshs, vmladdu=
hm
+ case 0x24: case 0x25: case 0x26: // vmsumubm, vmsummbm, vmsumuhm
+ case 0x27: case 0x28: case 0x29: // vmsumuhs, vmsumshm, vmsumshs
+ if (dis_av_multarith( theInstr )) goto decode_success;
+ goto decode_failure;
+
+ /* AV Permutations */
+ case 0x2A: // vsel
+ case 0x2B: // vperm
+ if (dis_av_permute( theInstr )) goto decode_success;
+ goto decode_failure;
+
+ /* AV Shift */
+ case 0x2C: // vsldoi
+ if (dis_av_shift( theInstr )) goto decode_success;
+ goto decode_failure;
+
+ /* AV Floating Point Mult-Add/Sub */
+ case 0x2E: case 0x2F: // vmaddfp, vnmsubfp
+ if (dis_av_fp_arith( theInstr )) goto decode_success;
+ goto decode_failure;
+
+ default:
+ break; // Fall through...
+ }
+
+ opc2 =3D (theInstr) & 0x7FF; /* theInstr[0:10] */
+ switch (opc2) {
+ /* AV Arithmetic */
+ case 0x180: // vaddcuw
+ case 0x000: case 0x040: case 0x080: // vaddubm, vadduhm, vadduwm
+ case 0x200: case 0x240: case 0x280: // vaddubs, vadduhs, vadduws
+ case 0x300: case 0x340: case 0x380: // vaddsbs, vaddshs, vaddsws
+ case 0x580: // vsubcuw
+ case 0x400: case 0x440: case 0x480: // vsububm, vsubuhm, vsubuwm
+ case 0x600: case 0x640: case 0x680: // vsububs, vsubuhs, vsubuws
+ case 0x700: case 0x740: case 0x780: // vsubsbs, vsubshs, vsubsws
+ case 0x402: case 0x442: case 0x482: // vavgub, vavguh, vavguw
+ case 0x502: case 0x542: case 0x582: // vavgsb, vavgsh, vavgsw
+ case 0x002: case 0x042: case 0x082: // vmaxub, vmaxuh, vmaxuw
+ case 0x102: case 0x142: case 0x182: // vmaxsb, vmaxsh, vmaxsw
+ case 0x202: case 0x242: case 0x282: // vminub, vminuh, vminuw
+ case 0x302: case 0x342: case 0x382: // vminsb, vminsh, vminsw
+ case 0x008: case 0x048: // vmuloub, vmulouh
+ case 0x108: case 0x148: // vmulosb, vmulosh
+ case 0x208: case 0x248: // vmuleub, vmuleuh
+ case 0x308: case 0x348: // vmulesb, vmulesh
+ case 0x608: case 0x708: case 0x648: // vsum4ubs, vsum4sbs, vsum4sh=
s
+ case 0x688: case 0x788: // vsum2sws, vsumsws
+ if (dis_av_arith( theInstr )) goto decode_success;
+ goto decode_failure;
+
+ /* AV Rotate, Shift */
+ case 0x004: case 0x044: case 0x084: // vrlb, vrlh, vrlw
+ case 0x104: case 0x144: case 0x184: // vslb, vslh, vslw
+ case 0x204: case 0x244: case 0x284: // vsrb, vsrh, vsrw
+ case 0x304: case 0x344: case 0x384: // vsrab, vsrah, vsraw
+ case 0x1C4: case 0x2C4: // vsl, vsr
+ case 0x40C: case 0x44C: // vslo, vsro
+ if (dis_av_shift( theInstr )) goto decode_success;
+ goto decode_failure;
+
+ /* AV Logic */
+ case 0x404: case 0x444: case 0x484: // vand, vandc, vor
+ case 0x4C4: case 0x504: // vxor, vnor
+ if (dis_av_logic( theInstr )) goto decode_success;
+ goto decode_failure;
+
+ /* AV Processor Control */
+ case 0x604: case 0x644: // mfvscr, mtvscr
+ if (dis_av_procctl( theInstr )) goto decode_success;
+ goto d...
[truncated message content] |
|
From: Nicholas N. <nj...@cs...> - 2005-06-28 13:48:58
|
On Tue, 28 Jun 2005, Julian Seward wrote: >> Segments are meant to be marked as SF_FIXED when they are mapped in with >> VKI_MAP_FIXED. Because of the above bug, all segments were being marked >> as SF_FIXED. I'm not aware of any problems this caused, but it didn't >> seem like a good idea to be mis-marking our segments. > > It could be a bug I introduced when messing with those wrappers > some time back. No, it's in 2.4 also. N |
|
From: Julian S. <js...@ac...> - 2005-06-28 13:16:01
|
> >> Don't mark segments as SF_FIXED when VKI_MAP_FIXED isn't specified. > > > > What problem does this solve? > > Are you just curious or do you see breakage? Really just curious. It seems to make no difference to regtests here; however the mmap stuff is fragile and so I wondered if you'd fallen over some bug to which this was the solution. Ah, I guess you've been looking at this because you were looking at Segments and SegInfos, yes? > Segments are meant to be marked as SF_FIXED when they are mapped in with > VKI_MAP_FIXED. Because of the above bug, all segments were being marked > as SF_FIXED. I'm not aware of any problems this caused, but it didn't > seem like a good idea to be mis-marking our segments. It could be a bug I introduced when messing with those wrappers some time back. > I'd be happy to get rid of this SF_FIXED flag altogether. It's never used > in a meaningful way (not surprising, given that it was being consistently > misapplied). A number of the SF_* flags fall into this category. GC on, dude .. J |
|
From: Nicholas N. <nj...@cs...> - 2005-06-28 13:14:44
|
Hi, I basically like this idea. The things I'm unsure about are below. > - External tools: installing eg Callgrind could be more complex as it > would have to be linked against libcoregrind.a at > installation time, even if installing from RPMs. This is important, lots of people use Callgrind so we want to make it possible to do this. > - PIE: this would make PIE'd valgrinds impossible. I'm not too > bothered since it seems like the main use for pie is to work > around the current address-space-layout inflexibilities, which > are up for review anyway. I'd be happier with ditching this once the address-space reworking has been done and shown to work. > - Need a replacement driver: since only one tool at a time is > linked into libcoregrind.a, the --tool= flag is ignored, and so > we'd need a new ultra-trivial driver which inspects that flag > and selects the right executable to start. > > Alternatively, adjust the core/tool interface so that multiple > tools can be linked into the core all at once. This sounds > attractive, and could save disk space. After recent changes to the 3.0 this is much closer to possible, since we're not using predefined names (eg. SK_(instrument)()) for everything. But it doesn't sound like it would play well with external tools. > Comments? In particular, are there other bad consequences I haven't > thought of? Also, [GregP] how would this play for making V work > for MacOS ? I assume the LD_PRELOAD modules (eg. vg_preload_core.so, vgpreload_memcheck.so) are still being used correctly? They must be if you say Memcheck is working properly. N |
|
From: Nicholas N. <nj...@cs...> - 2005-06-28 13:01:12
|
On Tue, 28 Jun 2005, Julian Seward wrote: >> Don't mark segments as SF_FIXED when VKI_MAP_FIXED isn't specified. > > What problem does this solve? Are you just curious or do you see breakage? Segments are meant to be marked as SF_FIXED when they are mapped in with VKI_MAP_FIXED. Because of the above bug, all segments were being marked as SF_FIXED. I'm not aware of any problems this caused, but it didn't seem like a good idea to be mis-marking our segments. I'd be happy to get rid of this SF_FIXED flag altogether. It's never used in a meaningful way (not surprising, given that it was being consistently misapplied). A number of the SF_* flags fall into this category. N |
|
From: Julian S. <js...@ac...> - 2005-06-28 10:11:55
|
Some time back in a thread "RFC: libc futures" (31 March 05) it
was suggested that statically linking the core to each tool would
possibly be beneficial. Recently I've been thinking a lot about
overhauling address space management, and as part of that I thought
I'd try the static linking game.
It's really not difficult. gcc needs -static, obviously, and
the magic incantations to set a non-default load address
(-Wl,-defsym,kickstart_base=0x70000000 -Wl,-T,../coregrind/stage2.lds),
load_tool() in m_main.c has to be turned into a no-op, more
or less, and the stuff in m_main that unmaps stage1's padding file
disappears. Once that's done I got a statically linked stage2+tool
combination that can be started directly; no need for stage1.
I checked that nulgrind and memcheck that work OK on both x86 and
amd64-linux.
So what are the advantages/disadvantages:
+ Simplicity: less code in m_main; stage1 disappears completely.
stage2 is started directly.
+ Independence: removes dependence on dlopen
+ Robustness: no need for huge mmaps, less likely to go wrong.
+ A big step towards build-time enforcement of no glibc use.
I've been experimenting with not only static linking but
also passing -nodefaultlibs -lgcc. This means glibc et al
are simply not linked in, and any use of a symbol not supplied
by V causes the link to fail. This doesn't work yet since we
make quite a lot of use of glibc, but I can see getting rid of
it is on the order of a day's work (apart from
localtime_r(), used for --time-stamp=yes).
- Disk space: usage increases since core is linked with every tool.
- External tools: installing eg Callgrind could be more complex as it
would have to be linked against libcoregrind.a at
installation time, even if installing from RPMs.
- PIE: this would make PIE'd valgrinds impossible. I'm not too
bothered since it seems like the main use for pie is to work
around the current address-space-layout inflexibilities, which
are up for review anyway.
- Need a replacement driver: since only one tool at a time is
linked into libcoregrind.a, the --tool= flag is ignored, and so
we'd need a new ultra-trivial driver which inspects that flag
and selects the right executable to start.
Alternatively, adjust the core/tool interface so that multiple
tools can be linked into the core all at once. This sounds
attractive, and could save disk space.
Comments? In particular, are there other bad consequences I haven't
thought of? Also, [GregP] how would this play for making V work
for MacOS ?
J
|
|
From: Julian S. <js...@ac...> - 2005-06-28 09:40:31
|
> Don't mark segments as SF_FIXED when VKI_MAP_FIXED isn't specified. What problem does this solve? J |
|
From: Tom H. <th...@cy...> - 2005-06-28 03:00:35
|
Nightly build on audi ( i686, Red Hat 9 ) started at 2005-06-28 03:25:02 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 177 tests, 11 stderr failures, 3 stdout failures ================= memcheck/tests/error_counts (stdout) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-tree (stderr) memcheck/tests/pointer-trace (stderr) memcheck/tests/sigaltstack (stderr) memcheck/tests/xml1 (stderr) corecheck/tests/fdleak_cmsg (stderr) corecheck/tests/pth_cancel1 (stdout) corecheck/tests/pth_cancel1 (stderr) corecheck/tests/pth_cancel2 (stderr) none/tests/faultstatus (stderr) none/tests/pth_blockedsig (stderr) none/tests/x86/int (stderr) none/tests/yield (stdout) |
|
From: <sv...@va...> - 2005-06-28 02:54:58
|
Author: njn
Date: 2005-06-28 03:54:52 +0100 (Tue, 28 Jun 2005)
New Revision: 4040
Log:
Fix comment.
Modified:
trunk/coregrind/m_main.c
Modified: trunk/coregrind/m_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_main.c 2005-06-28 02:45:29 UTC (rev 4039)
+++ trunk/coregrind/m_main.c 2005-06-28 02:54:52 UTC (rev 4040)
@@ -1966,8 +1966,8 @@
=20
if (VG_(clo_n_suppressions) < VG_CLO_MAX_SFILES-1 &&
(VG_(needs).core_errors || VG_(needs).tool_errors)) {
- /* If there are no suppression files specified and the tool
- needs one, load the default */
+ /* If we haven't reached the max number of suppressions, load
+ the default one. */
static const Char default_supp[] =3D "default.supp";
Int len =3D VG_(strlen)(VG_(libdir)) + 1 + sizeof(default_supp);
Char *buf =3D VG_(arena_malloc)(VG_AR_CORE, len);
|
|
From: <sv...@va...> - 2005-06-28 02:45:34
|
Author: njn
Date: 2005-06-28 03:45:29 +0100 (Tue, 28 Jun 2005)
New Revision: 4039
Log:
Don't mark segments as SF_FIXED when VKI_MAP_FIXED isn't specified.
Modified:
trunk/coregrind/m_libcmman.c
Modified: trunk/coregrind/m_libcmman.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_libcmman.c 2005-06-28 00:12:31 UTC (rev 4038)
+++ trunk/coregrind/m_libcmman.c 2005-06-28 02:45:29 UTC (rev 4039)
@@ -46,14 +46,12 @@
=20
if (!(flags & VKI_MAP_FIXED)) {
start =3D (void *)VG_(find_map_space)((Addr)start, length, !!(flag=
s & VKI_MAP_CLIENT));
-
- flags |=3D VKI_MAP_FIXED;
}
if (start =3D=3D 0)
return (void *)-1;
=20
res =3D VG_(mmap_native)(start, length, prot,=20
- flags & ~(VKI_MAP_NOSYMS | VKI_MAP_CLIENT),
+ (flags | VKI_MAP_FIXED) & ~(VKI_MAP_NOSYMS | V=
KI_MAP_CLIENT),
fd, offset);
=20
// Check it ended up in the right place.
|
|
From: <js...@ac...> - 2005-06-28 02:40:56
|
Nightly build on phoenix ( SuSE 9.1 ) started at 2005-06-28 03:30:00 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Regression test results follow == 175 tests, 4 stderr failures, 1 stdout failure ================= memcheck/tests/error_counts (stdout) memcheck/tests/leak-0 (stderr) memcheck/tests/leak-tree (stderr) none/tests/faultstatus (stderr) none/tests/x86/int (stderr) |
|
From: Tom H. <to...@co...> - 2005-06-28 02:32:48
|
Nightly build on dunsmere ( athlon, Fedora Core 4 ) started at 2005-06-28 03:30:03 BST Checking out vex source tree ... done Building vex ... done Checking out valgrind source tree ... done Configuring valgrind ... done Building valgrind ... done Running regression tests ... failed Last 20 lines of log.verbose follow insn_fpu.c: In function 'fsubrl_1': insn_fpu.c:16391: error: unknown register name 'mm6' in 'asm' insn_fpu.c: In function 'fsubrl_2': insn_fpu.c:16429: error: unknown register name 'mm6' in 'asm' insn_fpu.c: In function 'fsubrl_3': insn_fpu.c:16467: error: unknown register name 'mm6' in 'asm' insn_fpu.c: In function 'fsubrl_4': insn_fpu.c:16505: error: unknown register name 'mm6' in 'asm' make[5]: *** [insn_fpu.o] Error 1 rm insn_fpu.c insn_basic.c make[5]: Leaving directory `/tmp/valgrind.4224/valgrind/none/tests/x86' make[4]: *** [check-am] Error 2 make[4]: Leaving directory `/tmp/valgrind.4224/valgrind/none/tests/x86' make[3]: *** [check-recursive] Error 1 make[3]: Leaving directory `/tmp/valgrind.4224/valgrind/none/tests' make[2]: *** [check-recursive] Error 1 make[2]: Leaving directory `/tmp/valgrind.4224/valgrind/none' make[1]: *** [check-recursive] Error 1 make[1]: Leaving directory `/tmp/valgrind.4224/valgrind' make: *** [check] Error 2 |