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From: <sv...@va...> - 2005-06-30 23:40:06
|
Author: njn
Date: 2005-07-01 00:40:04 +0100 (Fri, 01 Jul 2005)
New Revision: 134
Log:
more wibbles
Modified:
trunk/gallery/survey_current/chunk-surveys
trunk/gallery/survey_current/survey.html
Modified: trunk/gallery/survey_current/chunk-surveys
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/gallery/survey_current/chunk-surveys 2005-06-30 23:30:05 UTC (r=
ev 133)
+++ trunk/gallery/survey_current/chunk-surveys 2005-06-30 23:40:04 UTC (r=
ev 134)
@@ -24,7 +24,7 @@
print("chunking file $f...\n");
my $currQ =3D -1;
while (my $line =3D <INPUTFILE>) {
- if ($line =3D~ /^q(\d+)/) {
+ if ($line =3D~ /^q(\d+)\./) {
# Onto next question...
($currQ + 1 =3D=3D $1) || die "next question ($1) not in ord=
er...";
$currQ =3D $1;
Modified: trunk/gallery/survey_current/survey.html
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/gallery/survey_current/survey.html 2005-06-30 23:30:05 UTC (rev=
133)
+++ trunk/gallery/survey_current/survey.html 2005-06-30 23:40:04 UTC (rev=
134)
@@ -124,7 +124,7 @@
<tr><td>
<input type=3D"hidden" name=3D"Q8[q]"=20
value=3D"q8. Which command-line options do you sometimes use"/>
- <b>8. </b>Which of Valgrind's command-line options you sometimes use?<=
br />
+ <b>8. </b>Which of Valgrind's command-line options do you sometimes us=
e?<br />
<textarea name=3D"Q8[txt]" rows=3D"2" cols=3D"56"></textarea>
</td></tr>
</table>
@@ -180,7 +180,7 @@
</td></tr>
<tr><td>
<input type=3D"hidden" name=3D"Q13[q]" value=3D"q13. Ideas for new tool=
s"/>
- <b>13. </b>Do you have ideas/wishes for new tools that could be built
+ <b>13. </b>Do you have suggestions for new tools that could be built
with Valgrind? Give as much detail as necessary.<br />
<textarea name=3D"Q13[txt]" rows=3D"3" cols=3D"56"></textarea>
</td></tr>
@@ -229,8 +229,7 @@
Language(s) : (estimate proportions if > 1, eg. 80% C, 20% Fortran 7=
7)
Number of programmers:=20
Size (lines of code) :=20
- Number of users :
- </textarea>
+ Number of users : </textarea>
</td></tr>
<tr><td>
<input type=3D"hidden" name=3D"Q16[q2]"=20
|
|
From: <sv...@va...> - 2005-06-30 23:33:40
|
Author: sewardj
Date: 2005-07-01 00:33:37 +0100 (Fri, 01 Jul 2005)
New Revision: 4072
Log:
Track Vex API change (r1239, introduction of endianness-indications in
IR loads and stores.)
Modified:
trunk/cachegrind/cg_main.c
trunk/memcheck/mc_include.h
trunk/memcheck/mc_main.c
trunk/memcheck/mc_translate.c
Modified: trunk/cachegrind/cg_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/cachegrind/cg_main.c 2005-06-30 23:32:30 UTC (rev 4071)
+++ trunk/cachegrind/cg_main.c 2005-06-30 23:33:37 UTC (rev 4072)
@@ -433,22 +433,23 @@
=20
case Ist_Tmp: {
IRExpr* data =3D st->Ist.Tmp.data;
- if (data->tag =3D=3D Iex_LDle) {
- IRExpr* aexpr =3D data->Iex.LDle.addr;
+ if (data->tag =3D=3D Iex_Load) {
+ IRExpr* aexpr =3D data->Iex.Load.addr;
tl_assert( isIRAtom(aexpr) );
-
+ // Note also, endianness info is ignored. I guess that's not
+ // interesting.
// XXX: repe cmpsb does two loads... the first one is ignored h=
ere!
//tl_assert( NULL =3D=3D *loadAddrExpr ); // XXX: ???
*loadAddrExpr =3D aexpr;
- *dataSize =3D sizeofIRType(data->Iex.LDle.ty);
+ *dataSize =3D sizeofIRType(data->Iex.Load.ty);
}
addStmtToIRBB( bbOut, st );
break;
}
=20
- case Ist_STle: {
- IRExpr* data =3D st->Ist.STle.data;
- IRExpr* aexpr =3D st->Ist.STle.addr;
+ case Ist_Store: {
+ IRExpr* data =3D st->Ist.Store.data;
+ IRExpr* aexpr =3D st->Ist.Store.addr;
tl_assert( isIRAtom(aexpr) );
tl_assert( NULL =3D=3D *storeAddrExpr ); // XXX: ???
*storeAddrExpr =3D aexpr;
Modified: trunk/memcheck/mc_include.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/mc_include.h 2005-06-30 23:32:30 UTC (rev 4071)
+++ trunk/memcheck/mc_include.h 2005-06-30 23:33:37 UTC (rev 4072)
@@ -60,15 +60,15 @@
extern void MC_(helperc_value_check1_fail) ( void );
extern void MC_(helperc_value_check0_fail) ( void );
=20
-extern VG_REGPARM(1) void MC_(helperc_STOREV8) ( Addr, ULong );
-extern VG_REGPARM(2) void MC_(helperc_STOREV4) ( Addr, UWord );
-extern VG_REGPARM(2) void MC_(helperc_STOREV2) ( Addr, UWord );
-extern VG_REGPARM(2) void MC_(helperc_STOREV1) ( Addr, UWord );
+extern VG_REGPARM(1) void MC_(helperc_STOREV8le) ( Addr, ULong );
+extern VG_REGPARM(2) void MC_(helperc_STOREV4le) ( Addr, UWord );
+extern VG_REGPARM(2) void MC_(helperc_STOREV2le) ( Addr, UWord );
+extern VG_REGPARM(2) void MC_(helperc_STOREV1le) ( Addr, UWord );
=20
-extern VG_REGPARM(1) UWord MC_(helperc_LOADV1) ( Addr );
-extern VG_REGPARM(1) UWord MC_(helperc_LOADV2) ( Addr );
-extern VG_REGPARM(1) UWord MC_(helperc_LOADV4) ( Addr );
-extern VG_REGPARM(1) ULong MC_(helperc_LOADV8) ( Addr );
+extern VG_REGPARM(1) UWord MC_(helperc_LOADV1le) ( Addr );
+extern VG_REGPARM(1) UWord MC_(helperc_LOADV2le) ( Addr );
+extern VG_REGPARM(1) UWord MC_(helperc_LOADV4le) ( Addr );
+extern VG_REGPARM(1) ULong MC_(helperc_LOADV8le) ( Addr );
=20
extern void MC_(helperc_MAKE_STACK_UNINIT) ( Addr base, UWord len );
=20
Modified: trunk/memcheck/mc_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/mc_main.c 2005-06-30 23:32:30 UTC (rev 4071)
+++ trunk/memcheck/mc_main.c 2005-06-30 23:33:37 UTC (rev 4072)
@@ -1473,9 +1473,9 @@
/* ------------------------ Size =3D 8 ------------------------ */
=20
VG_REGPARM(1)
-ULong MC_(helperc_LOADV8) ( Addr aA )
+ULong MC_(helperc_LOADV8le) ( Addr aA )
{
- PROF_EVENT(200, "helperc_LOADV8");
+ PROF_EVENT(200, "helperc_LOADV8le");
=20
# if VG_DEBUG_MEMORY >=3D 2
return mc_LOADVn_slow( aA, 8, False/*littleendian*/ );
@@ -1488,7 +1488,7 @@
naturally aligned, or 'a' exceeds the range covered by the
primary map. Either way we defer to the slow-path case. */
if (EXPECTED_NOT_TAKEN(a & mask)) {
- PROF_EVENT(201, "helperc_LOADV8-slow1");
+ PROF_EVENT(201, "helperc_LOADV8le-slow1");
return (UWord)mc_LOADVn_slow( aA, 8, False/*littleendian*/ );
}
=20
@@ -1509,7 +1509,7 @@
return ((ULong*)(sm->vbyte))[ v_off >> 3 ];
} else {
/* Slow but general case. */
- PROF_EVENT(202, "helperc_LOADV8-slow2");
+ PROF_EVENT(202, "helperc_LOADV8le-slow2");
return mc_LOADVn_slow( a, 8, False/*littleendian*/ );
}
=20
@@ -1517,9 +1517,9 @@
}
=20
VG_REGPARM(1)
-void MC_(helperc_STOREV8) ( Addr aA, ULong vbytes )
+void MC_(helperc_STOREV8le) ( Addr aA, ULong vbytes )
{
- PROF_EVENT(210, "helperc_STOREV8");
+ PROF_EVENT(210, "helperc_STOREV8le");
=20
# if VG_DEBUG_MEMORY >=3D 2
mc_STOREVn_slow( aA, 8, vbytes, False/*littleendian*/ );
@@ -1532,7 +1532,7 @@
naturally aligned, or 'a' exceeds the range covered by the
primary map. Either way we defer to the slow-path case. */
if (EXPECTED_NOT_TAKEN(a & mask)) {
- PROF_EVENT(211, "helperc_STOREV8-slow1");
+ PROF_EVENT(211, "helperc_STOREV8le-slow1");
mc_STOREVn_slow( aA, 8, vbytes, False/*littleendian*/ );
return;
}
@@ -1555,7 +1555,7 @@
((ULong*)(sm->vbyte))[ v_off >> 3 ] =3D vbytes;
} else {
/* Slow but general case. */
- PROF_EVENT(212, "helperc_STOREV8-slow2");
+ PROF_EVENT(212, "helperc_STOREV8le-slow2");
mc_STOREVn_slow( aA, 8, vbytes, False/*littleendian*/ );
}
# endif
@@ -1564,9 +1564,9 @@
/* ------------------------ Size =3D 4 ------------------------ */
=20
VG_REGPARM(1)
-UWord MC_(helperc_LOADV4) ( Addr aA )
+UWord MC_(helperc_LOADV4le) ( Addr aA )
{
- PROF_EVENT(220, "helperc_LOADV4");
+ PROF_EVENT(220, "helperc_LOADV4le");
=20
# if VG_DEBUG_MEMORY >=3D 2
return (UWord)mc_LOADVn_slow( aA, 4, False/*littleendian*/ );
@@ -1579,7 +1579,7 @@
naturally aligned, or 'a' exceeds the range covered by the
primary map. Either way we defer to the slow-path case. */
if (EXPECTED_NOT_TAKEN(a & mask)) {
- PROF_EVENT(221, "helperc_LOADV4-slow1");
+ PROF_EVENT(221, "helperc_LOADV4le-slow1");
return (UWord)mc_LOADVn_slow( aA, 4, False/*littleendian*/ );
}
=20
@@ -1607,7 +1607,7 @@
return ret;
} else {
/* Slow but general case. */
- PROF_EVENT(222, "helperc_LOADV4-slow2");
+ PROF_EVENT(222, "helperc_LOADV4le-slow2");
return (UWord)mc_LOADVn_slow( a, 4, False/*littleendian*/ );
}
=20
@@ -1615,9 +1615,9 @@
}
=20
VG_REGPARM(2)
-void MC_(helperc_STOREV4) ( Addr aA, UWord vbytes )
+void MC_(helperc_STOREV4le) ( Addr aA, UWord vbytes )
{
- PROF_EVENT(230, "helperc_STOREV4");
+ PROF_EVENT(230, "helperc_STOREV4le");
=20
# if VG_DEBUG_MEMORY >=3D 2
mc_STOREVn_slow( aA, 4, (ULong)vbytes, False/*littleendian*/ );
@@ -1630,7 +1630,7 @@
naturally aligned, or 'a' exceeds the range covered by the
primary map. Either way we defer to the slow-path case. */
if (EXPECTED_NOT_TAKEN(a & mask)) {
- PROF_EVENT(231, "helperc_STOREV4-slow1");
+ PROF_EVENT(231, "helperc_STOREV4le-slow1");
mc_STOREVn_slow( aA, 4, (ULong)vbytes, False/*littleendian*/ );
return;
}
@@ -1654,7 +1654,7 @@
((UInt*)(sm->vbyte))[ v_off >> 2 ] =3D (UInt)vbytes;
} else {
/* Slow but general case. */
- PROF_EVENT(232, "helperc_STOREV4-slow2");
+ PROF_EVENT(232, "helperc_STOREV4le-slow2");
mc_STOREVn_slow( aA, 4, (ULong)vbytes, False/*littleendian*/ );
}
# endif
@@ -1663,9 +1663,9 @@
/* ------------------------ Size =3D 2 ------------------------ */
=20
VG_REGPARM(1)
-UWord MC_(helperc_LOADV2) ( Addr aA )
+UWord MC_(helperc_LOADV2le) ( Addr aA )
{
- PROF_EVENT(240, "helperc_LOADV2");
+ PROF_EVENT(240, "helperc_LOADV2le");
=20
# if VG_DEBUG_MEMORY >=3D 2
return (UWord)mc_LOADVn_slow( aA, 2, False/*littleendian*/ );
@@ -1678,7 +1678,7 @@
naturally aligned, or 'a' exceeds the range covered by the
primary map. Either way we defer to the slow-path case. */
if (EXPECTED_NOT_TAKEN(a & mask)) {
- PROF_EVENT(241, "helperc_LOADV2-slow1");
+ PROF_EVENT(241, "helperc_LOADV2le-slow1");
return (UWord)mc_LOADVn_slow( aA, 2, False/*littleendian*/ );
}
=20
@@ -1703,7 +1703,7 @@
(UWord)( ((UShort*)(sm->vbyte))[ v_off >> 1 ] );
} else {
/* Slow but general case. */
- PROF_EVENT(242, "helperc_LOADV2-slow2");
+ PROF_EVENT(242, "helperc_LOADV2le-slow2");
return (UWord)mc_LOADVn_slow( aA, 2, False/*littleendian*/ );
}
=20
@@ -1711,9 +1711,9 @@
}
=20
VG_REGPARM(2)
-void MC_(helperc_STOREV2) ( Addr aA, UWord vbytes )
+void MC_(helperc_STOREV2le) ( Addr aA, UWord vbytes )
{
- PROF_EVENT(250, "helperc_STOREV2");
+ PROF_EVENT(250, "helperc_STOREV2le");
=20
# if VG_DEBUG_MEMORY >=3D 2
mc_STOREVn_slow( aA, 2, (ULong)vbytes, False/*littleendian*/ );
@@ -1726,7 +1726,7 @@
naturally aligned, or 'a' exceeds the range covered by the
primary map. Either way we defer to the slow-path case. */
if (EXPECTED_NOT_TAKEN(a & mask)) {
- PROF_EVENT(251, "helperc_STOREV2-slow1");
+ PROF_EVENT(251, "helperc_STOREV2le-slow1");
mc_STOREVn_slow( aA, 2, (ULong)vbytes, False/*littleendian*/ );
return;
}
@@ -1747,7 +1747,7 @@
((UShort*)(sm->vbyte))[ v_off >> 1 ] =3D (UShort)vbytes;
} else {
/* Slow but general case. */
- PROF_EVENT(252, "helperc_STOREV2-slow2");
+ PROF_EVENT(252, "helperc_STOREV2le-slow2");
mc_STOREVn_slow( aA, 2, (ULong)vbytes, False/*littleendian*/ );
}
# endif
@@ -1756,9 +1756,9 @@
/* ------------------------ Size =3D 1 ------------------------ */
=20
VG_REGPARM(1)
-UWord MC_(helperc_LOADV1) ( Addr aA )
+UWord MC_(helperc_LOADV1le) ( Addr aA )
{
- PROF_EVENT(260, "helperc_LOADV1");
+ PROF_EVENT(260, "helperc_LOADV1le");
=20
# if VG_DEBUG_MEMORY >=3D 2
return (UWord)mc_LOADVn_slow( aA, 1, False/*littleendian*/ );
@@ -1771,7 +1771,7 @@
exceeds the range covered by the primary map. In which case we
defer to the slow-path case. */
if (EXPECTED_NOT_TAKEN(a & mask)) {
- PROF_EVENT(261, "helperc_LOADV1-slow1");
+ PROF_EVENT(261, "helperc_LOADV1le-slow1");
return (UWord)mc_LOADVn_slow( aA, 1, False/*littleendian*/ );
}
=20
@@ -1796,7 +1796,7 @@
(UWord)( ((UChar*)(sm->vbyte))[ v_off ] );
} else {
/* Slow but general case. */
- PROF_EVENT(262, "helperc_LOADV1-slow2");
+ PROF_EVENT(262, "helperc_LOADV1le-slow2");
return (UWord)mc_LOADVn_slow( aA, 1, False/*littleendian*/ );
}
# endif
@@ -1804,9 +1804,9 @@
=20
=20
VG_REGPARM(2)
-void MC_(helperc_STOREV1) ( Addr aA, UWord vbyte )
+void MC_(helperc_STOREV1le) ( Addr aA, UWord vbyte )
{
- PROF_EVENT(270, "helperc_STOREV1");
+ PROF_EVENT(270, "helperc_STOREV1le");
=20
# if VG_DEBUG_MEMORY >=3D 2
mc_STOREVn_slow( aA, 1, (ULong)vbyte, False/*littleendian*/ );
@@ -1818,7 +1818,7 @@
exceeds the range covered by the primary map. In which case we
defer to the slow-path case. */
if (EXPECTED_NOT_TAKEN(a & mask)) {
- PROF_EVENT(271, "helperc_STOREV1-slow1");
+ PROF_EVENT(271, "helperc_STOREV1le-slow1");
mc_STOREVn_slow( aA, 1, (ULong)vbyte, False/*littleendian*/ );
return;
}
@@ -1839,7 +1839,7 @@
lives in is addressible. */
((UChar*)(sm->vbyte))[ v_off ] =3D (UChar)vbyte;
} else {
- PROF_EVENT(272, "helperc_STOREV1-slow2");
+ PROF_EVENT(272, "helperc_STOREV1le-slow2");
mc_STOREVn_slow( aA, 1, (ULong)vbyte, False/*littleendian*/ );
}
=20
Modified: trunk/memcheck/mc_translate.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/memcheck/mc_translate.c 2005-06-30 23:32:30 UTC (rev 4071)
+++ trunk/memcheck/mc_translate.c 2005-06-30 23:33:37 UTC (rev 4072)
@@ -1936,7 +1936,9 @@
=20
/* Worker function; do not call directly. */
static
-IRAtom* expr2vbits_LDle_WRK ( MCEnv* mce, IRType ty, IRAtom* addr, UInt =
bias )
+IRAtom* expr2vbits_Load_WRK ( MCEnv* mce,=20
+ IREndness end, IRType ty,=20
+ IRAtom* addr, UInt bias )
{
void* helper;
Char* hname;
@@ -1945,6 +1947,7 @@
IRAtom* addrAct;
=20
tl_assert(isOriginalAtom(mce,addr));
+ tl_assert(end =3D=3D Iend_LE || end =3D=3D Iend_BE);
=20
/* First, emit a definedness test for the address. This also sets
the address (shadow) to 'defined' following the test. */
@@ -1953,21 +1956,26 @@
/* Now cook up a call to the relevant helper function, to read the
data V bits from shadow memory. */
ty =3D shadowType(ty);
- switch (ty) {
- case Ity_I64: helper =3D &MC_(helperc_LOADV8);
- hname =3D "MC_(helperc_LOADV8)";
- break;
- case Ity_I32: helper =3D &MC_(helperc_LOADV4);
- hname =3D "MC_(helperc_LOADV4)";
- break;
- case Ity_I16: helper =3D &MC_(helperc_LOADV2);
- hname =3D "MC_(helperc_LOADV2)";
- break;
- case Ity_I8: helper =3D &MC_(helperc_LOADV1);
- hname =3D "MC_(helperc_LOADV1)";
- break;
- default: ppIRType(ty);
- VG_(tool_panic)("memcheck:do_shadow_LDle");
+
+ if (end =3D=3D Iend_LE) { =20
+ switch (ty) {
+ case Ity_I64: helper =3D &MC_(helperc_LOADV8le);
+ hname =3D "MC_(helperc_LOADV8le)";
+ break;
+ case Ity_I32: helper =3D &MC_(helperc_LOADV4le);
+ hname =3D "MC_(helperc_LOADV4le)";
+ break;
+ case Ity_I16: helper =3D &MC_(helperc_LOADV2le);
+ hname =3D "MC_(helperc_LOADV2le)";
+ break;
+ case Ity_I8: helper =3D &MC_(helperc_LOADV1le);
+ hname =3D "MC_(helperc_LOADV1le)";
+ break;
+ default: ppIRType(ty);
+ VG_(tool_panic)("memcheck:do_shadow_Load(LE)");
+ }
+ } else {
+ VG_(tool_panic)("memcheck:do_shadow_Load(BE):bigendian not impleme=
nted");
}
=20
/* Generate the actual address into addrAct. */
@@ -1997,23 +2005,32 @@
=20
=20
static
-IRAtom* expr2vbits_LDle ( MCEnv* mce, IRType ty, IRAtom* addr, UInt bias=
)
+IRAtom* expr2vbits_Load ( MCEnv* mce,=20
+ IREndness end, IRType ty,=20
+ IRAtom* addr, UInt bias )
{
IRAtom *v64hi, *v64lo;
+ tl_assert(end =3D=3D Iend_LE || end =3D=3D Iend_BE);
switch (shadowType(ty)) {
case Ity_I8:=20
case Ity_I16:=20
case Ity_I32:=20
case Ity_I64:
- return expr2vbits_LDle_WRK(mce, ty, addr, bias);
+ return expr2vbits_Load_WRK(mce, end, ty, addr, bias);
case Ity_V128:
- v64lo =3D expr2vbits_LDle_WRK(mce, Ity_I64, addr, bias);
- v64hi =3D expr2vbits_LDle_WRK(mce, Ity_I64, addr, bias+8);
+ if (end =3D=3D Iend_LE) {
+ v64lo =3D expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias)=
;
+ v64hi =3D expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+=
8);
+ } else {
+ tl_assert(0 /* awaiting test case */);
+ v64hi =3D expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias)=
;
+ v64lo =3D expr2vbits_Load_WRK(mce, end, Ity_I64, addr, bias+=
8);
+ }
return assignNew( mce,=20
Ity_V128,=20
binop(Iop_64HLtoV128, v64hi, v64lo));
default:
- VG_(tool_panic)("expr2vbits_LDle");
+ VG_(tool_panic)("expr2vbits_Load");
}
}
=20
@@ -2073,9 +2090,10 @@
case Iex_Unop:
return expr2vbits_Unop( mce, e->Iex.Unop.op, e->Iex.Unop.arg );
=20
- case Iex_LDle:
- return expr2vbits_LDle( mce, e->Iex.LDle.ty,=20
- e->Iex.LDle.addr, 0/*addr bias*/ )=
;
+ case Iex_Load:
+ return expr2vbits_Load( mce, e->Iex.Load.end,
+ e->Iex.Load.ty,=20
+ e->Iex.Load.addr, 0/*addr bias*/ )=
;
=20
case Iex_CCall:
return mkLazyN( mce, e->Iex.CCall.args,=20
@@ -2142,25 +2160,27 @@
obviously not both. */
=20
static=20
-void do_shadow_STle ( MCEnv* mce,=20
- IRAtom* addr, UInt bias,
- IRAtom* data, IRAtom* vdata )
+void do_shadow_Store ( MCEnv* mce,=20
+ IREndness end,
+ IRAtom* addr, UInt bias,
+ IRAtom* data, IRAtom* vdata )
{
IROp mkAdd;
IRType ty, tyAddr;
IRDirty *di, *diLo64, *diHi64;
IRAtom *addrAct, *addrLo64, *addrHi64;
IRAtom *vdataLo64, *vdataHi64;
- IRAtom *eBias, *eBias0, *eBias8;
+ IRAtom *eBias, *eBiasLo64, *eBiasHi64;
void* helper =3D NULL;
Char* hname =3D NULL;
=20
tyAddr =3D mce->hWordTy;
mkAdd =3D tyAddr=3D=3DIty_I32 ? Iop_Add32 : Iop_Add64;
tl_assert( tyAddr =3D=3D Ity_I32 || tyAddr =3D=3D Ity_I64 );
+ tl_assert( end =3D=3D Iend_LE || end =3D=3D Iend_BE );
=20
di =3D diLo64 =3D diHi64 =3D NULL;
- eBias =3D eBias0 =3D eBias8 =3D NULL;
+ eBias =3D eBiasLo64 =3D eBiasHi64 =3D NULL;
addrAct =3D addrLo64 =3D addrHi64 =3D NULL;
vdataLo64 =3D vdataHi64 =3D NULL;
=20
@@ -2184,36 +2204,52 @@
=20
/* Now decide which helper function to call to write the data V
bits into shadow memory. */
- switch (ty) {
- case Ity_V128: /* we'll use the helper twice */
- case Ity_I64: helper =3D &MC_(helperc_STOREV8);
- hname =3D "MC_(helperc_STOREV8)";
- break;
- case Ity_I32: helper =3D &MC_(helperc_STOREV4);
- hname =3D "MC_(helperc_STOREV4)";
- break;
- case Ity_I16: helper =3D &MC_(helperc_STOREV2);
- hname =3D "MC_(helperc_STOREV2)";
- break;
- case Ity_I8: helper =3D &MC_(helperc_STOREV1);
- hname =3D "MC_(helperc_STOREV1)";
- break;
- default: VG_(tool_panic)("memcheck:do_shadow_STle");
+ if (end =3D=3D Iend_LE) {
+ switch (ty) {
+ case Ity_V128: /* we'll use the helper twice */
+ case Ity_I64: helper =3D &MC_(helperc_STOREV8le);
+ hname =3D "MC_(helperc_STOREV8le)";
+ break;
+ case Ity_I32: helper =3D &MC_(helperc_STOREV4le);
+ hname =3D "MC_(helperc_STOREV4le)";
+ break;
+ case Ity_I16: helper =3D &MC_(helperc_STOREV2le);
+ hname =3D "MC_(helperc_STOREV2le)";
+ break;
+ case Ity_I8: helper =3D &MC_(helperc_STOREV1le);
+ hname =3D "MC_(helperc_STOREV1le)";
+ break;
+ default: VG_(tool_panic)("memcheck:do_shadow_Store(LE)");
+ }
+ } else {
+ VG_(tool_panic)("memcheck:do_shadow_Store(BE):bigendian not implem=
ented");
}
=20
if (ty =3D=3D Ity_V128) {
=20
/* V128-bit case */
/* See comment in next clause re 64-bit regparms */
- eBias0 =3D tyAddr=3D=3DIty_I32 ? mkU32(bias) : mkU64(bias);
- addrLo64 =3D assignNew(mce, tyAddr, binop(mkAdd, addr, eBias0) );
+ /* also, need to be careful about endianness */
+
+ Int offLo64, offHi64;
+ if (end =3D=3D Iend_LE) {
+ offLo64 =3D 0;
+ offHi64 =3D 8;
+ } else {
+ tl_assert(0 /* awaiting test case */);
+ offLo64 =3D 8;
+ offHi64 =3D 0;
+ }
+
+ eBiasLo64 =3D tyAddr=3D=3DIty_I32 ? mkU32(bias+offLo64) : mkU64(bi=
as+offLo64);
+ addrLo64 =3D assignNew(mce, tyAddr, binop(mkAdd, addr, eBiasLo64)=
);
vdataLo64 =3D assignNew(mce, Ity_I64, unop(Iop_V128to64, vdata));
diLo64 =3D unsafeIRDirty_0_N(=20
1/*regparms*/, hname, helper,=20
mkIRExprVec_2( addrLo64, vdataLo64 ));
=20
- eBias8 =3D tyAddr=3D=3DIty_I32 ? mkU32(bias+8) : mkU64(bias+8);
- addrHi64 =3D assignNew(mce, tyAddr, binop(mkAdd, addr, eBias8) );
+ eBiasHi64 =3D tyAddr=3D=3DIty_I32 ? mkU32(bias+offHi64) : mkU64(bi=
as+offHi64);
+ addrHi64 =3D assignNew(mce, tyAddr, binop(mkAdd, addr, eBiasHi64)=
);
vdataHi64 =3D assignNew(mce, Ity_I64, unop(Iop_V128HIto64, vdata))=
;
diHi64 =3D unsafeIRDirty_0_N(=20
1/*regparms*/, hname, helper,=20
@@ -2273,11 +2309,21 @@
static
void do_shadow_Dirty ( MCEnv* mce, IRDirty* d )
{
- Int i, n, offset, toDo, gSz, gOff;
- IRAtom *src, *here, *curr;
- IRType tyAddr, tySrc, tyDst;
- IRTemp dst;
+ Int i, n, offset, toDo, gSz, gOff;
+ IRAtom *src, *here, *curr;
+ IRType tyAddr, tySrc, tyDst;
+ IRTemp dst;
+ IREndness end;
=20
+ /* What's the native endianness? We need to know this. */
+# if defined(VKI_BIG_ENDIAN)
+ end =3D Iend_BE;
+# elif defined(VKI_LITTLE_ENDIAN)
+ end =3D Iend_LE;
+# else
+# error "Unknown endianness"
+# endif
+
/* First check the guard. */
complainIfUndefined(mce, d->guard);
=20
@@ -2351,11 +2397,14 @@
if (d->mFx =3D=3D Ifx_Read || d->mFx =3D=3D Ifx_Modify) {
offset =3D 0;
toDo =3D d->mSize;
- /* chew off 32-bit chunks */
+ /* chew off 32-bit chunks. We don't care about the endianness
+ since it's all going to be condensed down to a single bit,
+ but nevertheless choose an endianness which is hopefully
+ native to the platform. */
while (toDo >=3D 4) {
here =3D mkPCastTo(=20
mce, Ity_I32,
- expr2vbits_LDle ( mce, Ity_I32,=20
+ expr2vbits_Load ( mce, end, Ity_I32,=20
d->mAddr, d->mSize - toDo )
);
curr =3D mkUifU32(mce, here, curr);
@@ -2365,7 +2414,7 @@
while (toDo >=3D 2) {
here =3D mkPCastTo(=20
mce, Ity_I32,
- expr2vbits_LDle ( mce, Ity_I16,=20
+ expr2vbits_Load ( mce, end, Ity_I16,=20
d->mAddr, d->mSize - toDo )
);
curr =3D mkUifU32(mce, here, curr);
@@ -2413,22 +2462,23 @@
}
}
=20
- /* Outputs: memory that we write or modify. */
+ /* Outputs: memory that we write or modify. Same comments about
+ endianness as above apply. */
if (d->mFx =3D=3D Ifx_Write || d->mFx =3D=3D Ifx_Modify) {
offset =3D 0;
toDo =3D d->mSize;
/* chew off 32-bit chunks */
while (toDo >=3D 4) {
- do_shadow_STle( mce, d->mAddr, d->mSize - toDo,
- NULL, /* original data */
- mkPCastTo( mce, Ity_I32, curr ) );
+ do_shadow_Store( mce, end, d->mAddr, d->mSize - toDo,
+ NULL, /* original data */
+ mkPCastTo( mce, Ity_I32, curr ) );
toDo -=3D 4;
}
/* chew off 16-bit chunks */
while (toDo >=3D 2) {
- do_shadow_STle( mce, d->mAddr, d->mSize - toDo,
- NULL, /* original data */
- mkPCastTo( mce, Ity_I16, curr ) );
+ do_shadow_Store( mce, end, d->mAddr, d->mSize - toDo,
+ NULL, /* original data */
+ mkPCastTo( mce, Ity_I16, curr ) );
toDo -=3D 2;
}
tl_assert(toDo =3D=3D 0); /* also need to handle 1-byte excess */
@@ -2517,8 +2567,8 @@
return isBogusAtom(e->Iex.Mux0X.cond)
|| isBogusAtom(e->Iex.Mux0X.expr0)
|| isBogusAtom(e->Iex.Mux0X.exprX);
- case Iex_LDle:=20
- return isBogusAtom(e->Iex.LDle.addr);
+ case Iex_Load:=20
+ return isBogusAtom(e->Iex.Load.addr);
case Iex_CCall:
for (i =3D 0; e->Iex.CCall.args[i]; i++)
if (isBogusAtom(e->Iex.CCall.args[i]))
@@ -2542,9 +2592,9 @@
case Ist_PutI:
return isBogusAtom(st->Ist.PutI.ix)=20
|| isBogusAtom(st->Ist.PutI.data);
- case Ist_STle:
- return isBogusAtom(st->Ist.STle.addr)=20
- || isBogusAtom(st->Ist.STle.data);
+ case Ist_Store:
+ return isBogusAtom(st->Ist.Store.addr)=20
+ || isBogusAtom(st->Ist.Store.data);
case Ist_Exit:
return isBogusAtom(st->Ist.Exit.guard);
case Ist_AbiHint:
@@ -2649,10 +2699,11 @@
st->Ist.PutI.data );
break;
=20
- case Ist_STle:
- do_shadow_STle( &mce, st->Ist.STle.addr, 0/* addr bias */,
- st->Ist.STle.data,
- NULL /* shadow data */ );
+ case Ist_Store:
+ do_shadow_Store( &mce, st->Ist.Store.end,
+ st->Ist.Store.addr, 0/* addr bias */,
+ st->Ist.Store.data,
+ NULL /* shadow data */ );
break;
=20
case Ist_Exit:
|
|
From: <sv...@va...> - 2005-06-30 23:32:34
|
Author: sewardj Date: 2005-07-01 00:32:30 +0100 (Fri, 01 Jul 2005) New Revision: 4071 Log: Update expected output. Modified: trunk/memcheck/tests/xml1.stderr.exp64 Modified: trunk/memcheck/tests/xml1.stderr.exp64 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/memcheck/tests/xml1.stderr.exp64 2005-06-30 23:20:30 UTC (rev 4= 070) +++ trunk/memcheck/tests/xml1.stderr.exp64 2005-06-30 23:32:30 UTC (rev 4= 071) @@ -1,3 +1,4 @@ +<?xml version=3D"1.0"?> =20 <valgrindoutput> =20 @@ -3,10 +4,12 @@ <protocolversion>1</protocolversion> =20 -<preamble>...</preamble> -<preamble>...</preamble> -<preamble>...</preamble> -<preamble>...</preamble> -<preamble>...</preamble> -<preamble>...</preamble> +<preamble> + <line>...</line> + <line>...</line> + <line>...</line> + <line>...</line> + <line>...</line> + <line>...</line> +</preamble> =20 <pid>...</pid> @@ -15,7 +18,7 @@ <tool>memcheck</tool> =20 <argv> - <arg>./xml1</arg> + <exe>./xml1</exe> </argv> =20 <status>RUNNING</status> @@ -26,18 +29,81 @@ <kind>InvalidRead</kind> <what>Invalid read of size 4</what> <stack> - <frame><ip>0x........</ip><obj>...</obj><fn>frame3</fn><file>xml1.c<= /file><line>11</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame2</fn><file>xml1.c<= /file><line>39</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame1</fn><file>xml1.c<= /file><line>44</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>main</fn><file>xml1.c</f= ile><line>49</line></frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame3</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame2</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame1</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>main</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> </stack> <auxwhat>Address 0x........ is 0 bytes after a block of size 40 alloc'= d</auxwhat> <stack> - <frame><ip>0x........</ip><obj>...</obj><fn>malloc</fn><file>vg_repl= ace_malloc.c</file><line>220</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame3</fn><file>xml1.c<= /file><line>8</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame2</fn><file>xml1.c<= /file><line>39</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame1</fn><file>xml1.c<= /file><line>44</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>main</fn><file>xml1.c</f= ile><line>49</line></frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>malloc</fn> + <dir>...</dir> + <file>vg_replace_malloc.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame3</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame2</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame1</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>main</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> </stack> </error> =20 @@ -47,10 +113,38 @@ <kind>UninitCondition</kind> <what>Conditional jump or move depends on uninitialised value(s)</what= > <stack> - <frame><ip>0x........</ip><obj>...</obj><fn>frame3</fn><file>xml1.c<= /file><line>14</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame2</fn><file>xml1.c<= /file><line>39</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame1</fn><file>xml1.c<= /file><line>44</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>main</fn><file>xml1.c</f= ile><line>49</line></frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame3</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame2</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame1</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>main</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> </stack> </error> =20 @@ -60,10 +154,38 @@ <kind>UninitValue</kind> <what>Use of uninitialised value of size 8</what> <stack> - <frame><ip>0x........</ip><obj>...</obj><fn>frame3</fn><file>xml1.c<= /file><line>21</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame2</fn><file>xml1.c<= /file><line>39</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame1</fn><file>xml1.c<= /file><line>44</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>main</fn><file>xml1.c</f= ile><line>49</line></frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame3</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame2</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame1</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>main</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> </stack> </error> =20 @@ -73,19 +195,89 @@ <kind>InvalidFree</kind> <what>Invalid free() / delete / delete[]</what> <stack> - <frame><ip>0x........</ip><obj>...</obj><fn>free</fn><file>vg_replac= e_malloc.c</file><line>306</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame3</fn><file>xml1.c<= /file><line>25</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame2</fn><file>xml1.c<= /file><line>39</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame1</fn><file>xml1.c<= /file><line>44</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>main</fn><file>xml1.c</f= ile><line>49</line></frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>free</fn> + <dir>...</dir> + <file>vg_replace_malloc.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame3</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame2</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame1</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>main</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> </stack> <auxwhat>Address 0x........ is 0 bytes inside a block of size 40 free'= d</auxwhat> <stack> - <frame><ip>0x........</ip><obj>...</obj><fn>free</fn><file>vg_replac= e_malloc.c</file><line>306</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame3</fn><file>xml1.c<= /file><line>24</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame2</fn><file>xml1.c<= /file><line>39</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame1</fn><file>xml1.c<= /file><line>44</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>main</fn><file>xml1.c</f= ile><line>49</line></frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>free</fn> + <dir>...</dir> + <file>vg_replace_malloc.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame3</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame2</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame1</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>main</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> </stack> </error> =20 @@ -95,11 +287,46 @@ <kind>InvalidFree</kind> <what>Invalid free() / delete / delete[]</what> <stack> - <frame><ip>0x........</ip><obj>...</obj><fn>free</fn><file>vg_replac= e_malloc.c</file><line>306</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame3</fn><file>xml1.c<= /file><line>28</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame2</fn><file>xml1.c<= /file><line>39</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame1</fn><file>xml1.c<= /file><line>44</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>main</fn><file>xml1.c</f= ile><line>49</line></frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>free</fn> + <dir>...</dir> + <file>vg_replace_malloc.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame3</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame2</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame1</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>main</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> </stack> <auxwhat>Address 0x........ is on thread 1's stack</auxwhat> </error> @@ -110,31 +337,49 @@ <kind>SyscallParam</kind> <what>Syscall param exit_group(exit_code) contains uninitialised byte(= s)</what> <stack> - <frame><ip>0x........</ip><obj>...</obj><fn>_Exit</fn></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>exit</fn></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>__libc_start_main</fn></= frame> - <frame><ip>0x........</ip><obj>...</obj><file>start.S</file><line>11= 3</line></frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>_Exit</fn> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>exit</fn> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>__libc_start_main</fn> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <dir>...</dir> + <file>start.S</file> + <line>...</line> + </frame> </stack> </error> =20 <errorcounts> - <pair><count>1</count><unique>0x........</unique></pair> - <pair><count>1</count><unique>0x........</unique></pair> - <pair><count>1</count><unique>0x........</unique></pair> - <pair><count>1</count><unique>0x........</unique></pair> - <pair><count>1</count><unique>0x........</unique></pair> - <pair><count>1</count><unique>0x........</unique></pair> + <pair> <count>1</count> <unique>0x........</unique> </pair> + <pair> <count>1</count> <unique>0x........</unique> </pair> + <pair> <count>1</count> <unique>0x........</unique> </pair> + <pair> <count>1</count> <unique>0x........</unique> </pair> + <pair> <count>1</count> <unique>0x........</unique> </pair> + <pair> <count>1</count> <unique>0x........</unique> </pair> </errorcounts> =20 <status>FINISHED</status> =20 <suppcounts> - <pair><count>3</count><name>index-not-intercepted-early-enough-HACK-1<= /name></pair> - <pair><count>1</count><name>strlen-not-intercepted-early-enough-HACK-5= </name></pair> - <pair><count>1</count><name>strlen-not-intercepted-early-enough-HACK-4= </name></pair> - <pair><count>1</count><name>strlen-not-intercepted-early-enough-HACK-3= </name></pair> - <pair><count>2</count><name>dl_relocate_object</name></pair> -<suppcounts> + <pair> <count>3</count> <name>index-not-intercepted-early-enough-HACK-= 1</name> </pair> + <pair> <count>1</count> <name>strlen-not-intercepted-early-enough-HACK= -5</name> </pair> + <pair> <count>1</count> <name>strlen-not-intercepted-early-enough-HACK= -4</name> </pair> + <pair> <count>1</count> <name>strlen-not-intercepted-early-enough-HACK= -3</name> </pair> + <pair> <count>2</count> <name>dl_relocate_object</name> </pair> +</suppcounts> =20 <error> <unique>0x........</unique> @@ -144,11 +389,46 @@ <leakedbytes>396</leakedbytes> <leakedblocks>1</leakedblocks> <stack> - <frame><ip>0x........</ip><obj>...</obj><fn>malloc</fn><file>vg_repl= ace_malloc.c</file><line>220</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame3</fn><file>xml1.c<= /file><line>31</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame2</fn><file>xml1.c<= /file><line>39</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>frame1</fn><file>xml1.c<= /file><line>44</line></frame> - <frame><ip>0x........</ip><obj>...</obj><fn>main</fn><file>xml1.c</f= ile><line>49</line></frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>malloc</fn> + <dir>...</dir> + <file>vg_replace_malloc.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame3</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame2</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>frame1</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> + <frame> + <ip>0x........</ip> + <obj>...</obj> + <fn>main</fn> + <dir>...</dir> + <file>xml1.c</file> + <line>...</line> + </frame> </stack> </error> =20 |
Author: sewardj
Date: 2005-07-01 00:31:27 +0100 (Fri, 01 Jul 2005)
New Revision: 1239
Log:
Enhance IR so as to distinguish between little- and big-endian loads and
stores, so that PPC can be properly handled. Until now it's been hardwir=
ed
to assume little-endian.
As a result, IRStmt_STle is renamed IRStmt_Store and IRExpr_LDle is
renamed IRExpr_Load.
Modified:
trunk/priv/guest-amd64/toIR.c
trunk/priv/guest-arm/toIR.c
trunk/priv/guest-ppc32/toIR.c
trunk/priv/guest-x86/toIR.c
trunk/priv/host-amd64/isel.c
trunk/priv/host-arm/isel.c
trunk/priv/host-ppc32/isel.c
trunk/priv/host-x86/isel.c
trunk/priv/ir/irdefs.c
trunk/priv/ir/irmatch.c
trunk/priv/ir/iropt.c
trunk/pub/libvex_ir.h
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-06-30 13:38:38 UTC (rev 1238)
+++ trunk/priv/guest-amd64/toIR.c 2005-06-30 23:31:27 UTC (rev 1239)
@@ -221,12 +221,12 @@
=20
static void storeLE ( IRExpr* addr, IRExpr* data )
{
- stmt( IRStmt_STle(addr,data) );
+ stmt( IRStmt_Store(Iend_LE,addr,data) );
}
=20
static IRExpr* loadLE ( IRType ty, IRExpr* data )
{
- return IRExpr_LDle(ty,data);
+ return IRExpr_Load(Iend_LE,ty,data);
}
=20
static IROp mkSizedOp ( IRType ty, IROp op8 )
@@ -5420,7 +5420,7 @@
case 0: /* FLD double-real */
DIP("fldl %s\n", dis_buf);
fp_push();
- put_ST(0, IRExpr_LDle(Ity_F64, mkexpr(addr)));
+ put_ST(0, loadLE(Ity_F64, mkexpr(addr)));
break;
=20
case 2: /* FST double-real */
Modified: trunk/priv/guest-arm/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-arm/toIR.c 2005-06-30 13:38:38 UTC (rev 1238)
+++ trunk/priv/guest-arm/toIR.c 2005-06-30 23:31:27 UTC (rev 1239)
@@ -484,7 +484,7 @@
=20
static void storeLE ( IRExpr* addr, IRExpr* data )
{
- stmt( IRStmt_STle(addr,data) );
+ stmt( IRStmt_Store(Iend_LE,addr,data) );
}
=20
static IRExpr* unop ( IROp op, IRExpr* a )
@@ -534,7 +534,7 @@
=20
static IRExpr* loadLE ( IRType ty, IRExpr* data )
{
- return IRExpr_LDle(ty,data);
+ return IRExpr_Load(Iend_LE,ty,data);
}
=20
#if 0
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-06-30 13:38:38 UTC (rev 1238)
+++ trunk/priv/guest-ppc32/toIR.c 2005-06-30 23:31:27 UTC (rev 1239)
@@ -653,15 +653,17 @@
return IRExpr_Get( vectorGuestRegOffset(archreg), Ity_V128 );
}
=20
+#if 0
/* Ditto, but write to a reg instead. */
+/* apparently unused, jrs 2005-06-30 */
static void putVReg ( UInt archreg, IRExpr* e )
{
vassert(archreg < 32);
vassert(typeOfIRExpr(irbb->tyenv, e) =3D=3D Ity_V128);
stmt( IRStmt_Put(vectorGuestRegOffset(archreg), e) );
}
+#endif
=20
-
static void assign ( IRTemp dst, IRExpr* e )
{
stmt( IRStmt_Tmp(dst, e) );
@@ -669,7 +671,7 @@
=20
static void storeBE ( IRExpr* addr, IRExpr* data )
{
- stmt( IRStmt_STle(addr,data) );
+ stmt( IRStmt_Store(Iend_BE,addr,data) );
}
=20
static IRExpr* unop ( IROp op, IRExpr* a )
@@ -712,7 +714,7 @@
=20
static IRExpr* loadBE ( IRType ty, IRExpr* data )
{
- return IRExpr_LDle(ty,data);
+ return IRExpr_Load(Iend_BE,ty,data);
}
=20
// ROTL(src32, rot_amt5)
Modified: trunk/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-x86/toIR.c 2005-06-30 13:38:38 UTC (rev 1238)
+++ trunk/priv/guest-x86/toIR.c 2005-06-30 23:31:27 UTC (rev 1239)
@@ -777,7 +777,7 @@
=20
static void storeLE ( IRExpr* addr, IRExpr* data )
{
- stmt( IRStmt_STle(addr,data) );
+ stmt( IRStmt_Store(Iend_LE,addr,data) );
}
=20
static IRExpr* unop ( IROp op, IRExpr* a )
@@ -834,7 +834,7 @@
=20
static IRExpr* loadLE ( IRType ty, IRExpr* data )
{
- return IRExpr_LDle(ty,data);
+ return IRExpr_Load(Iend_LE,ty,data);
}
=20
static IROp mkSizedOp ( IRType ty, IROp op8 )
@@ -4551,7 +4551,7 @@
case 0: /* FLD double-real */
DIP("fldl %s\n", dis_buf);
fp_push();
- put_ST(0, IRExpr_LDle(Ity_F64, mkexpr(addr)));
+ put_ST(0, loadLE(Ity_F64, mkexpr(addr)));
break;
=20
case 2: /* FST double-real */
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-06-30 13:38:38 UTC (rev 1238)
+++ trunk/priv/host-amd64/isel.c 2005-06-30 23:31:27 UTC (rev 1239)
@@ -797,9 +797,13 @@
}
=20
/* --------- LOAD --------- */
- case Iex_LDle: {
+ case Iex_Load: {
HReg dst =3D newVRegI(env);
- AMD64AMode* amode =3D iselIntExpr_AMode ( env, e->Iex.LDle.addr );
+ AMD64AMode* amode =3D iselIntExpr_AMode ( env, e->Iex.Load.addr );
+
+ if (e->Iex.Load.end !=3D Iend_LE)
+ goto irreducible;
+
if (ty =3D=3D Ity_I64) {
addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,
AMD64RMI_Mem(amode), dst) );
@@ -1777,8 +1781,8 @@
}
=20
/* special case: 64-bit load from memory */
- if (e->tag =3D=3D Iex_LDle && ty =3D=3D Ity_I64) {
- AMD64AMode* am =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
+ if (e->tag =3D=3D Iex_Load && ty =3D=3D Ity_I64 && e->Iex.Load.end =3D=
=3D Iend_LE) {
+ AMD64AMode* am =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
return AMD64RMI_Mem(am);
}
=20
@@ -2629,11 +2633,11 @@
return lookupIRTemp(env, e->Iex.Tmp.tmp);
}
=20
- if (e->tag =3D=3D Iex_LDle) {
+ if (e->tag =3D=3D Iex_Load && e->Iex.Load.end =3D=3D Iend_LE) {
AMD64AMode* am;
HReg res =3D newVRegV(env);
- vassert(e->Iex.LDle.ty =3D=3D Ity_F32);
- am =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
+ vassert(e->Iex.Load.ty =3D=3D Ity_F32);
+ am =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 4, res, am));
return res;
}
@@ -2753,11 +2757,11 @@
return res;
}
=20
- if (e->tag =3D=3D Iex_LDle) {
+ if (e->tag =3D=3D Iex_Load && e->Iex.Load.end =3D=3D Iend_LE) {
AMD64AMode* am;
HReg res =3D newVRegV(env);
- vassert(e->Iex.LDle.ty =3D=3D Ity_F64);
- am =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
+ vassert(e->Iex.Load.ty =3D=3D Ity_F64);
+ am =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 8, res, am ));
return res;
}
@@ -3071,9 +3075,9 @@
return dst;
}
=20
- if (e->tag =3D=3D Iex_LDle) {
+ if (e->tag =3D=3D Iex_Load && e->Iex.Load.end =3D=3D Iend_LE) {
HReg dst =3D newVRegV(env);
- AMD64AMode* am =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
+ AMD64AMode* am =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 16, dst, am ));
return dst;
}
@@ -3488,38 +3492,42 @@
switch (stmt->tag) {
=20
/* --------- STORE --------- */
- case Ist_STle: {
+ case Ist_Store: {
AMD64AMode* am;
- IRType tya =3D typeOfIRExpr(env->type_env, stmt->Ist.STle.addr);
- IRType tyd =3D typeOfIRExpr(env->type_env, stmt->Ist.STle.data);
- vassert(tya =3D=3D Ity_I64);
- am =3D iselIntExpr_AMode(env, stmt->Ist.STle.addr);
+ IRType tya =3D typeOfIRExpr(env->type_env, stmt->Ist.Store.addr=
);
+ IRType tyd =3D typeOfIRExpr(env->type_env, stmt->Ist.Store.data=
);
+ IREndness end =3D stmt->Ist.Store.end;
+
+ if (tya !=3D Ity_I64 || end !=3D Iend_LE)=20
+ goto stmt_fail;
+
+ am =3D iselIntExpr_AMode(env, stmt->Ist.Store.addr);
if (tyd =3D=3D Ity_I64) {
- AMD64RI* ri =3D iselIntExpr_RI(env, stmt->Ist.STle.data);
+ AMD64RI* ri =3D iselIntExpr_RI(env, stmt->Ist.Store.data);
addInstr(env, AMD64Instr_Alu64M(Aalu_MOV,ri,am));
return;
}
if (tyd =3D=3D Ity_I8 || tyd =3D=3D Ity_I16 || tyd =3D=3D Ity_I32)=
{
- HReg r =3D iselIntExpr_R(env, stmt->Ist.STle.data);
+ HReg r =3D iselIntExpr_R(env, stmt->Ist.Store.data);
addInstr(env, AMD64Instr_Store(
toUChar(tyd=3D=3DIty_I8 ? 1 : (tyd=3D=3DIty_I1=
6 ? 2 : 4)),
r,am));
return;
}
if (tyd =3D=3D Ity_F64) {
- HReg r =3D iselDblExpr(env, stmt->Ist.STle.data);
+ HReg r =3D iselDblExpr(env, stmt->Ist.Store.data);
addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, r, am));
return;
}
if (tyd =3D=3D Ity_F32) {
- HReg r =3D iselFltExpr(env, stmt->Ist.STle.data);
+ HReg r =3D iselFltExpr(env, stmt->Ist.Store.data);
addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 4, r, am));
return;
}
//.. if (tyd =3D=3D Ity_I64) {
//.. HReg vHi, vLo, rA;
-//.. iselInt64Expr(&vHi, &vLo, env, stmt->Ist.STle.data);
-//.. rA =3D iselIntExpr_R(env, stmt->Ist.STle.addr);
+//.. iselInt64Expr(&vHi, &vLo, env, stmt->Ist.Store.data);
+//.. rA =3D iselIntExpr_R(env, stmt->Ist.Store.addr);
//.. addInstr(env, X86Instr_Alu32M(
//.. Xalu_MOV, X86RI_Reg(vLo), X86AMode_IR(0, =
rA)));
//.. addInstr(env, X86Instr_Alu32M(
@@ -3527,7 +3535,7 @@
//.. return;
//.. }
if (tyd =3D=3D Ity_V128) {
- HReg r =3D iselVecExpr(env, stmt->Ist.STle.data);
+ HReg r =3D iselVecExpr(env, stmt->Ist.Store.data);
addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, r, am));
return;
}
@@ -3720,6 +3728,7 @@
=20
default: break;
}
+ stmt_fail:
ppIRStmt(stmt);
vpanic("iselStmt(amd64)");
}
Modified: trunk/priv/host-arm/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-arm/isel.c 2005-06-30 13:38:38 UTC (rev 1238)
+++ trunk/priv/host-arm/isel.c 2005-06-30 23:31:27 UTC (rev 1239)
@@ -738,25 +738,29 @@
=20
/* --------- STORE --------- */
/* little-endian write to memory */
- case Ist_STle: {
+ case Ist_Store: {
HReg reg;
- IRType tya =3D typeOfIRExpr(env->type_env, stmt->Ist.STle.addr);
- IRType tyd =3D typeOfIRExpr(env->type_env, stmt->Ist.STle.data);
- vassert(tya =3D=3D Ity_I32);
- reg =3D iselIntExpr_R(env, stmt->Ist.STle.data);
+ IRType tya =3D typeOfIRExpr(env->type_env, stmt->Ist.Store.addr);
+ IRType tyd =3D typeOfIRExpr(env->type_env, stmt->Ist.Store.data);
+ IREndness end =3D stmt->Ist.Store.end;
=20
+ if (tya !=3D Ity_I32 || end !=3D Iend_LE)=20
+ goto stmt_fail;
+
+ reg =3D iselIntExpr_R(env, stmt->Ist.Store.data);
+
if (tyd =3D=3D Ity_I8) {
- ARMAMode2* am2 =3D iselIntExpr_AMode2(env, stmt->Ist.STle.addr);
+ ARMAMode2* am2 =3D iselIntExpr_AMode2(env, stmt->Ist.Store.addr);
addInstr(env, ARMInstr_StoreB(reg,am2));
return;
}
if (tyd =3D=3D Ity_I16) {
- ARMAMode3* am3 =3D iselIntExpr_AMode3(env, stmt->Ist.STle.addr);
+ ARMAMode3* am3 =3D iselIntExpr_AMode3(env, stmt->Ist.Store.addr);
addInstr(env, ARMInstr_StoreH(reg,am3));
return;
}
if (tyd =3D=3D Ity_I32) {
- ARMAMode2* am2 =3D iselIntExpr_AMode2(env, stmt->Ist.STle.addr);
+ ARMAMode2* am2 =3D iselIntExpr_AMode2(env, stmt->Ist.Store.addr);
addInstr(env, ARMInstr_StoreW(reg,am2));
return;
} =20
@@ -880,6 +884,7 @@
=20
default: break;
}
+ stmt_fail:
ppIRStmt(stmt);
vpanic("iselStmt");
}
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-06-30 13:38:38 UTC (rev 1238)
+++ trunk/priv/host-ppc32/isel.c 2005-06-30 23:31:27 UTC (rev 1239)
@@ -909,11 +909,14 @@
return lookupIRTemp(env, e->Iex.Tmp.tmp);
=20
/* --------- LOAD --------- */
- case Iex_LDle: {
- HReg r_dst =3D newVRegI(env);
- PPC32AMode* am_addr =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
+ case Iex_Load: {
+ HReg r_dst =3D newVRegI(env);
+ PPC32AMode* am_addr =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
+ if (e->Iex.Load.end !=3D Iend_BE)
+ goto irreducible;
if (ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 || ty =3D=3D Ity_I32) {
- addInstr(env, PPC32Instr_Load( sizeofIRType(ty), False, r_dst, =
am_addr ));
+ addInstr(env, PPC32Instr_Load(=20
+ sizeofIRType(ty), False, r_dst, am_addr ));
return r_dst;
}
break;
@@ -1216,12 +1219,13 @@
return r_dst;
}
=20
- /* 16Uto32(LDle(expr32)) */
+ /* 16Uto32(LDbe:I16(expr32)) */
{
- DECLARE_PATTERN(p_LDle16_then_16Uto32);
- DEFINE_PATTERN(p_LDle16_then_16Uto32,
- unop(Iop_16Uto32,IRExpr_LDle(Ity_I16,bind(0))) );
- if (matchIRExpr(&mi,p_LDle16_then_16Uto32,e)) {
+ DECLARE_PATTERN(p_LDbe16_then_16Uto32);
+ DEFINE_PATTERN(p_LDbe16_then_16Uto32,
+ unop(Iop_16Uto32,
+ IRExpr_Load(Iend_BE,Ity_I16,bind(0))) );
+ if (matchIRExpr(&mi,p_LDbe16_then_16Uto32,e)) {
HReg r_dst =3D newVRegI(env);
PPC32AMode* amode =3D iselIntExpr_AMode ( env, mi.bindee[0] =
);
addInstr(env, PPC32Instr_Load(2,False,r_dst,amode));
@@ -2489,11 +2493,11 @@
return lookupIRTemp(env, e->Iex.Tmp.tmp);
}
=20
- if (e->tag =3D=3D Iex_LDle) {
+ if (e->tag =3D=3D Iex_Load && e->Iex.Load.end =3D=3D Iend_BE) {
PPC32AMode* am_addr;
HReg r_dst =3D newVRegF(env);
- vassert(e->Iex.LDle.ty =3D=3D Ity_F32);
- am_addr =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
+ vassert(e->Iex.Load.ty =3D=3D Ity_F32);
+ am_addr =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
addInstr(env, PPC32Instr_FpLdSt(True/*load*/, 4, r_dst, am_addr));
return r_dst;
}
@@ -2612,11 +2616,11 @@
return mk_LoadRRtoFPR( env, r_srcHi, r_srcLo );
}
=20
- if (e->tag =3D=3D Iex_LDle) {
+ if (e->tag =3D=3D Iex_Load && e->Iex.Load.end =3D=3D Iend_BE) {
HReg r_dst =3D newVRegF(env);
PPC32AMode* am_addr;
- vassert(e->Iex.LDle.ty =3D=3D Ity_F64);
- am_addr =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
+ vassert(e->Iex.Load.ty =3D=3D Ity_F64);
+ am_addr =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
addInstr(env, PPC32Instr_FpLdSt(True/*load*/, 8, r_dst, am_addr));
return r_dst;
}
@@ -2795,7 +2799,7 @@
static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
{
//.. Bool arg1isEReg =3D False;
- PPC32AvOp op =3D Pav_INVALID;
+ // unused: PPC32AvOp op =3D Pav_INVALID;
IRType ty =3D typeOfIRExpr(env->type_env,e);
vassert(e);
vassert(ty =3D=3D Ity_V128);
@@ -3251,7 +3255,7 @@
//.. return dst;
//.. }
=20
- vec_fail:
+ // unused: vec_fail:
vex_printf("iselVecExpr(ppc32) (subarch =3D %s): can't reduce\n",
LibVEX_ppVexSubArch(env->subarch));
ppIRExpr(e);
@@ -3274,32 +3278,35 @@
switch (stmt->tag) {
=20
/* --------- STORE --------- */
- case Ist_STle: {
+ case Ist_Store: {
PPC32AMode* am_addr;
- IRType tya =3D typeOfIRExpr(env->type_env, stmt->Ist.STle.addr);
- IRType tyd =3D typeOfIRExpr(env->type_env, stmt->Ist.STle.data);
- vassert(tya =3D=3D Ity_I32);
+ IRType tya =3D typeOfIRExpr(env->type_env, stmt->Ist.Store.addr=
);
+ IRType tyd =3D typeOfIRExpr(env->type_env, stmt->Ist.Store.data=
);
+ IREndness end =3D stmt->Ist.Store.end;
=20
- am_addr =3D iselIntExpr_AMode(env, stmt->Ist.STle.addr);
+ if (tya !=3D Ity_I32 || end !=3D Iend_BE)=20
+ goto stmt_fail;
+
+ am_addr =3D iselIntExpr_AMode(env, stmt->Ist.Store.addr);
if (tyd =3D=3D Ity_I8 || tyd =3D=3D Ity_I16 || tyd =3D=3D Ity_I32)=
{
- HReg r_src =3D iselIntExpr_R(env, stmt->Ist.STle.data);
+ HReg r_src =3D iselIntExpr_R(env, stmt->Ist.Store.data);
addInstr(env, PPC32Instr_Store(sizeofIRType(tyd), am_addr, r_sr=
c));
return;
}
if (tyd =3D=3D Ity_F64) {
- HReg fr_src =3D iselDblExpr(env, stmt->Ist.STle.data);
+ HReg fr_src =3D iselDblExpr(env, stmt->Ist.Store.data);
addInstr(env, PPC32Instr_FpLdSt(False/*store*/, 8, fr_src, am_a=
ddr));
return;
}
if (tyd =3D=3D Ity_F32) {
- HReg fr_src =3D iselFltExpr(env, stmt->Ist.STle.data);
+ HReg fr_src =3D iselFltExpr(env, stmt->Ist.Store.data);
addInstr(env, PPC32Instr_FpLdSt(False/*store*/, 4, fr_src, am_a=
ddr));
return;
}
//.. if (tyd =3D=3D Ity_I64) {
//.. HReg vHi, vLo, rA;
-//.. iselInt64Expr(&vHi, &vLo, env, stmt->Ist.STle.data);
-//.. rA =3D iselIntExpr_R(env, stmt->Ist.STle.addr);
+//.. iselInt64Expr(&vHi, &vLo, env, stmt->Ist.Store.data);
+//.. rA =3D iselIntExpr_R(env, stmt->Ist.Store.addr);
//.. addInstr(env, X86Instr_Alu32M(
//.. Xalu_MOV, X86RI_Reg(vLo), X86AMode_IR(0, =
rA)));
//.. addInstr(env, X86Instr_Alu32M(
@@ -3307,7 +3314,7 @@
//.. return;
//.. }
if (tyd =3D=3D Ity_V128) {
- HReg v_src =3D iselVecExpr(env, stmt->Ist.STle.data);
+ HReg v_src =3D iselVecExpr(env, stmt->Ist.Store.data);
addInstr(env, PPC32Instr_AvLdSt(False/*store*/, 16, v_src, am_a=
ddr));
return;
}
@@ -3496,6 +3503,7 @@
=20
default: break;
}
+ stmt_fail:
ppIRStmt(stmt);
vpanic("iselStmt(ppc32)");
}
Modified: trunk/priv/host-x86/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-x86/isel.c 2005-06-30 13:38:38 UTC (rev 1238)
+++ trunk/priv/host-x86/isel.c 2005-06-30 23:31:27 UTC (rev 1239)
@@ -726,9 +726,13 @@
}
=20
/* --------- LOAD --------- */
- case Iex_LDle: {
+ case Iex_Load: {
HReg dst =3D newVRegI(env);
- X86AMode* amode =3D iselIntExpr_AMode ( env, e->Iex.LDle.addr );
+ X86AMode* amode =3D iselIntExpr_AMode ( env, e->Iex.Load.addr );
+
+ if (e->Iex.Load.end !=3D Iend_LE)
+ goto irreducible;
+
if (ty =3D=3D Ity_I32) {
addInstr(env, X86Instr_Alu32R(Xalu_MOV,
X86RMI_Mem(amode), dst) );
@@ -1000,7 +1004,8 @@
{
DECLARE_PATTERN(p_LDle16_then_16Uto32);
DEFINE_PATTERN(p_LDle16_then_16Uto32,
- unop(Iop_16Uto32,IRExpr_LDle(Ity_I16,bind(0))) );
+ unop(Iop_16Uto32,
+ IRExpr_Load(Iend_LE,Ity_I16,bind(0))) );
if (matchIRExpr(&mi,p_LDle16_then_16Uto32,e)) {
HReg dst =3D newVRegI(env);
X86AMode* amode =3D iselIntExpr_AMode ( env, mi.bindee[0] );
@@ -1351,8 +1356,8 @@
}
=20
/* special case: 32-bit load from memory */
- if (e->tag =3D=3D Iex_LDle && ty =3D=3D Ity_I32) {
- X86AMode* am =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
+ if (e->tag =3D=3D Iex_Load && ty =3D=3D Ity_I32 && e->Iex.Load.end =3D=
=3D Iend_LE) {
+ X86AMode* am =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
return X86RMI_Mem(am);
}
=20
@@ -1782,13 +1787,13 @@
}
=20
/* 64-bit load */
- if (e->tag =3D=3D Iex_LDle) {
+ if (e->tag =3D=3D Iex_Load && e->Iex.Load.end =3D=3D Iend_LE) {
HReg tLo, tHi;
X86AMode *am0, *am4;
- vassert(e->Iex.LDle.ty =3D=3D Ity_I64);
+ vassert(e->Iex.Load.ty =3D=3D Ity_I64);
tLo =3D newVRegI(env);
tHi =3D newVRegI(env);
- am0 =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
+ am0 =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
am4 =3D advance4(am0);
addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(am0), tLo ));
addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(am4), tHi ));
@@ -2433,11 +2438,11 @@
return lookupIRTemp(env, e->Iex.Tmp.tmp);
}
=20
- if (e->tag =3D=3D Iex_LDle) {
+ if (e->tag =3D=3D Iex_Load && e->Iex.Load.end =3D=3D Iend_LE) {
X86AMode* am;
HReg res =3D newVRegF(env);
- vassert(e->Iex.LDle.ty =3D=3D Ity_F32);
- am =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
+ vassert(e->Iex.Load.ty =3D=3D Ity_F32);
+ am =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
addInstr(env, X86Instr_FpLdSt(True/*load*/, 4, res, am));
return res;
}
@@ -2557,11 +2562,11 @@
return freg;
}
=20
- if (e->tag =3D=3D Iex_LDle) {
+ if (e->tag =3D=3D Iex_Load && e->Iex.Load.end =3D=3D Iend_LE) {
X86AMode* am;
HReg res =3D newVRegF(env);
- vassert(e->Iex.LDle.ty =3D=3D Ity_F64);
- am =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
+ vassert(e->Iex.Load.ty =3D=3D Ity_F64);
+ am =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
addInstr(env, X86Instr_FpLdSt(True/*load*/, 8, res, am));
return res;
}
@@ -2792,9 +2797,9 @@
return dst;
}
=20
- if (e->tag =3D=3D Iex_LDle) {
+ if (e->tag =3D=3D Iex_Load && e->Iex.Load.end =3D=3D Iend_LE) {
HReg dst =3D newVRegV(env);
- X86AMode* am =3D iselIntExpr_AMode(env, e->Iex.LDle.addr);
+ X86AMode* am =3D iselIntExpr_AMode(env, e->Iex.Load.addr);
addInstr(env, X86Instr_SseLdSt( True/*load*/, dst, am ));
return dst;
}
@@ -2812,7 +2817,8 @@
/* 64UtoV128(LDle:I64(addr)) */
DECLARE_PATTERN(p_zwiden_load64);
DEFINE_PATTERN(p_zwiden_load64,
- unop(Iop_64UtoV128, IRExpr_LDle(Ity_I64,bind(0))));
+ unop(Iop_64UtoV128,=20
+ IRExpr_Load(Iend_LE,Ity_I64,bind(0))));
if (matchIRExpr(&mi, p_zwiden_load64, e)) {
X86AMode* am =3D iselIntExpr_AMode(env, mi.bindee[0]);
HReg dst =3D newVRegV(env);
@@ -3272,37 +3278,41 @@
switch (stmt->tag) {
=20
/* --------- STORE --------- */
- case Ist_STle: {
+ case Ist_Store: {
X86AMode* am;
- IRType tya =3D typeOfIRExpr(env->type_env, stmt->Ist.STle.addr);
- IRType tyd =3D typeOfIRExpr(env->type_env, stmt->Ist.STle.data);
- vassert(tya =3D=3D Ity_I32);
- am =3D iselIntExpr_AMode(env, stmt->Ist.STle.addr);
+ IRType tya =3D typeOfIRExpr(env->type_env, stmt->Ist.Store.addr=
);
+ IRType tyd =3D typeOfIRExpr(env->type_env, stmt->Ist.Store.data=
);
+ IREndness end =3D stmt->Ist.Store.end;
+
+ if (tya !=3D Ity_I32 || end !=3D Iend_LE)=20
+ goto stmt_fail;
+
+ am =3D iselIntExpr_AMode(env, stmt->Ist.Store.addr);
if (tyd =3D=3D Ity_I32) {
- X86RI* ri =3D iselIntExpr_RI(env, stmt->Ist.STle.data);
+ X86RI* ri =3D iselIntExpr_RI(env, stmt->Ist.Store.data);
addInstr(env, X86Instr_Alu32M(Xalu_MOV,ri,am));
return;
}
if (tyd =3D=3D Ity_I8 || tyd =3D=3D Ity_I16) {
- HReg r =3D iselIntExpr_R(env, stmt->Ist.STle.data);
+ HReg r =3D iselIntExpr_R(env, stmt->Ist.Store.data);
addInstr(env, X86Instr_Store( toUChar(tyd=3D=3DIty_I8 ? 1 : 2),
r,am ));
return;
}
if (tyd =3D=3D Ity_F64) {
- HReg r =3D iselDblExpr(env, stmt->Ist.STle.data);
+ HReg r =3D iselDblExpr(env, stmt->Ist.Store.data);
addInstr(env, X86Instr_FpLdSt(False/*store*/, 8, r, am));
return;
}
if (tyd =3D=3D Ity_F32) {
- HReg r =3D iselFltExpr(env, stmt->Ist.STle.data);
+ HReg r =3D iselFltExpr(env, stmt->Ist.Store.data);
addInstr(env, X86Instr_FpLdSt(False/*store*/, 4, r, am));
return;
}
if (tyd =3D=3D Ity_I64) {
HReg vHi, vLo, rA;
- iselInt64Expr(&vHi, &vLo, env, stmt->Ist.STle.data);
- rA =3D iselIntExpr_R(env, stmt->Ist.STle.addr);
+ iselInt64Expr(&vHi, &vLo, env, stmt->Ist.Store.data);
+ rA =3D iselIntExpr_R(env, stmt->Ist.Store.addr);
addInstr(env, X86Instr_Alu32M(
Xalu_MOV, X86RI_Reg(vLo), X86AMode_IR(0, rA)))=
;
addInstr(env, X86Instr_Alu32M(
@@ -3310,7 +3320,7 @@
return;
}
if (tyd =3D=3D Ity_V128) {
- HReg r =3D iselVecExpr(env, stmt->Ist.STle.data);
+ HReg r =3D iselVecExpr(env, stmt->Ist.Store.data);
addInstr(env, X86Instr_SseLdSt(False/*store*/, r, am));
return;
}
@@ -3520,6 +3530,7 @@
=20
default: break;
}
+ stmt_fail:
ppIRStmt(stmt);
vpanic("iselStmt");
}
Modified: trunk/priv/ir/irdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/irdefs.c 2005-06-30 13:38:38 UTC (rev 1238)
+++ trunk/priv/ir/irdefs.c 2005-06-30 23:31:27 UTC (rev 1239)
@@ -501,11 +501,11 @@
ppIRExpr(e->Iex.Unop.arg);
vex_printf( ")" );
break;
- case Iex_LDle:
- vex_printf( "LDle:" );
- ppIRType(e->Iex.LDle.ty);
+ case Iex_Load:
+ vex_printf( "LD%s:", e->Iex.Load.end=3D=3DIend_LE ? "le" : "be" );
+ ppIRType(e->Iex.Load.ty);
vex_printf( "(" );
- ppIRExpr(e->Iex.LDle.addr);
+ ppIRExpr(e->Iex.Load.addr);
vex_printf( ")" );
break;
case Iex_Const:
@@ -635,11 +635,11 @@
vex_printf( " =3D " );
ppIRExpr(s->Ist.Tmp.data);
break;
- case Ist_STle:
- vex_printf( "STle(");
- ppIRExpr(s->Ist.STle.addr);
+ case Ist_Store:
+ vex_printf( "ST%s(", s->Ist.Store.end=3D=3DIend_LE ? "le" : "be=
" );
+ ppIRExpr(s->Ist.Store.addr);
vex_printf( ") =3D ");
- ppIRExpr(s->Ist.STle.data);
+ ppIRExpr(s->Ist.Store.data);
break;
case Ist_Dirty:
ppIRDirty(s->Ist.Dirty.details);
@@ -837,11 +837,13 @@
e->Iex.Unop.arg =3D arg;
return e;
}
-IRExpr* IRExpr_LDle ( IRType ty, IRExpr* addr ) {
+IRExpr* IRExpr_Load ( IREndness end, IRType ty, IRExpr* addr ) {
IRExpr* e =3D LibVEX_Alloc(sizeof(IRExpr));
- e->tag =3D Iex_LDle;
- e->Iex.LDle.ty =3D ty;
- e->Iex.LDle.addr =3D addr;
+ e->tag =3D Iex_Load;
+ e->Iex.Load.end =3D end;
+ e->Iex.Load.ty =3D ty;
+ e->Iex.Load.addr =3D addr;
+ vassert(end =3D=3D Iend_LE || end =3D=3D Iend_BE);
return e;
}
IRExpr* IRExpr_Const ( IRConst* con ) {
@@ -984,11 +986,13 @@
s->Ist.Tmp.data =3D data;
return s;
}
-IRStmt* IRStmt_STle ( IRExpr* addr, IRExpr* data ) {
- IRStmt* s =3D LibVEX_Alloc(sizeof(IRStmt));
- s->tag =3D Ist_STle;
- s->Ist.STle.addr =3D addr;
- s->Ist.STle.data =3D data;
+IRStmt* IRStmt_Store ( IREndness end, IRExpr* addr, IRExpr* data ) {
+ IRStmt* s =3D LibVEX_Alloc(sizeof(IRStmt));
+ s->tag =3D Ist_Store;
+ s->Ist.Store.end =3D end;
+ s->Ist.Store.addr =3D addr;
+ s->Ist.Store.data =3D data;
+ vassert(end =3D=3D Iend_LE || end =3D=3D Iend_BE);
return s;
}
IRStmt* IRStmt_Dirty ( IRDirty* d )
@@ -1123,9 +1127,10 @@
case Iex_Unop:=20
return IRExpr_Unop(e->Iex.Unop.op,
dopyIRExpr(e->Iex.Unop.arg));
- case Iex_LDle:=20
- return IRExpr_LDle(e->Iex.LDle.ty,
- dopyIRExpr(e->Iex.LDle.addr));
+ case Iex_Load:=20
+ return IRExpr_Load(e->Iex.Load.end,
+ e->Iex.Load.ty,
+ dopyIRExpr(e->Iex.Load.addr));
case Iex_Const:=20
return IRExpr_Const(dopyIRConst(e->Iex.Const.con));
case Iex_CCall:
@@ -1181,9 +1186,10 @@
case Ist_Tmp:
return IRStmt_Tmp(s->Ist.Tmp.tmp,
dopyIRExpr(s->Ist.Tmp.data));
- case Ist_STle:=20
- return IRStmt_STle(dopyIRExpr(s->Ist.STle.addr),
- dopyIRExpr(s->Ist.STle.data));
+ case Ist_Store:=20
+ return IRStmt_Store(s->Ist.Store.end,
+ dopyIRExpr(s->Ist.Store.addr),
+ dopyIRExpr(s->Ist.Store.data));
case Ist_Dirty:=20
return IRStmt_Dirty(dopyIRDirty(s->Ist.Dirty.details));
case Ist_MFence:
@@ -1596,8 +1602,8 @@
IRType t_dst, t_arg1, t_arg2;
start:
switch (e->tag) {
- case Iex_LDle:
- return e->Iex.LDle.ty;
+ case Iex_Load:
+ return e->Iex.Load.ty;
case Iex_Get:
return e->Iex.Get.ty;
case Iex_GetI:
@@ -1684,7 +1690,7 @@
isIRAtom(e->Iex.Binop.arg1)=20
&& isIRAtom(e->Iex.Binop.arg2));
case Iex_Unop: return isIRAtom(e->Iex.Unop.arg);
- case Iex_LDle: return isIRAtom(e->Iex.LDle.addr);
+ case Iex_Load: return isIRAtom(e->Iex.Load.addr);
case Iex_Const: return True;
case Iex_CCall: for (i =3D 0; e->Iex.CCall.args[i]; i++)
if (!isIRAtom(e->Iex.CCall.args[i]))=20
@@ -1698,9 +1704,9 @@
}
/*notreached*/
vassert(0);
- case Ist_STle:
- return toBool( isIRAtom(st->Ist.STle.addr)=20
- && isIRAtom(st->Ist.STle.data) );
+ case Ist_Store:
+ return toBool( isIRAtom(st->Ist.Store.addr)=20
+ && isIRAtom(st->Ist.Store.data) );
case Ist_Dirty:
di =3D st->Ist.Dirty.details;
if (!isIRAtom(di->guard))=20
@@ -1825,8 +1831,8 @@
case Iex_Unop:
useBeforeDef_Expr(bb,stmt,expr->Iex.Unop.arg,def_counts);
break;
- case Iex_LDle:
- useBeforeDef_Expr(bb,stmt,expr->Iex.LDle.addr,def_counts);
+ case Iex_Load:
+ useBeforeDef_Expr(bb,stmt,expr->Iex.Load.addr,def_counts);
break;
case Iex_Const:
break;
@@ -1865,9 +1871,9 @@
case Ist_Tmp:
useBeforeDef_Expr(bb,stmt,stmt->Ist.Tmp.data,def_counts);
break;
- case Ist_STle:
- useBeforeDef_Expr(bb,stmt,stmt->Ist.STle.addr,def_counts);
- useBeforeDef_Expr(bb,stmt,stmt->Ist.STle.data,def_counts);
+ case Ist_Store:
+ useBeforeDef_Expr(bb,stmt,stmt->Ist.Store.addr,def_counts);
+ useBeforeDef_Expr(bb,stmt,stmt->Ist.Store.data,def_counts);
break;
case Ist_Dirty:
d =3D stmt->Ist.Dirty.details;
@@ -1948,10 +1954,12 @@
if (t_arg1 !=3D typeOfIRExpr(tyenv, expr->Iex.Unop.arg))
sanityCheckFail(bb,stmt,"Iex.Unop: arg ty doesn't match op t=
y");
break;
- case Iex_LDle:
- tcExpr(bb,stmt, expr->Iex.LDle.addr, gWordTy);
- if (typeOfIRExpr(tyenv, expr->Iex.LDle.addr) !=3D gWordTy)
- sanityCheckFail(bb,stmt,"Iex.LDle.addr: not :: guest word ty=
pe");
+ case Iex_Load:
+ tcExpr(bb,stmt, expr->Iex.Load.addr, gWordTy);
+ if (typeOfIRExpr(tyenv, expr->Iex.Load.addr) !=3D gWordTy)
+ sanityCheckFail(bb,stmt,"Iex.Load.addr: not :: guest word ty=
pe");
+ if (expr->Iex.Load.end !=3D Iend_LE && expr->Iex.Load.end !=3D =
Iend_BE)
+ sanityCheckFail(bb,stmt,"Iex.Load.end: bogus endianness");
break;
case Iex_CCall:
if (!saneIRCallee(expr->Iex.CCall.cee))
@@ -2031,13 +2039,15 @@
!=3D typeOfIRExpr(tyenv, stmt->Ist.Tmp.data))
sanityCheckFail(bb,stmt,"IRStmt.Put.Tmp: tmp and expr do not=
match");
break;
- case Ist_STle:
- tcExpr( bb, stmt, stmt->Ist.STle.addr, gWordTy );
- tcExpr( bb, stmt, stmt->Ist.STle.data, gWordTy );
- if (typeOfIRExpr(tyenv, stmt->Ist.STle.addr) !=3D gWordTy)
- sanityCheckFail(bb,stmt,"IRStmt.STle.addr: not :: guest word=
type");
- if (typeOfIRExpr(tyenv, stmt->Ist.STle.data) =3D=3D Ity_I1)
- sanityCheckFail(bb,stmt,"IRStmt.STle.data: cannot STle :: It=
y_I1");
+ case Ist_Store:
+ tcExpr( bb, stmt, stmt->Ist.Store.addr, gWordTy );
+ tcExpr( bb, stmt, stmt->Ist.Store.data, gWordTy );
+ if (typeOfIRExpr(tyenv, stmt->Ist.Store.addr) !=3D gWordTy)
+ sanityCheckFail(bb,stmt,"IRStmt.Store.addr: not :: guest wor=
d type");
+ if (typeOfIRExpr(tyenv, stmt->Ist.Store.data) =3D=3D Ity_I1)
+ sanityCheckFail(bb,stmt,"IRStmt.Store.data: cannot Store :: =
Ity_I1");
+ if (stmt->Ist.Store.end !=3D Iend_LE && stmt->Ist.Store.end !=3D=
Iend_BE)
+ sanityCheckFail(bb,stmt,"Ist.Store.end: bogus endianness");
break;
case Ist_Dirty:
/* Mostly check for various kinds of ill-formed dirty calls. */
Modified: trunk/priv/ir/irmatch.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/irmatch.c 2005-06-30 13:38:38 UTC (rev 1238)
+++ trunk/priv/ir/irmatch.c 2005-06-30 23:31:27 UTC (rev 1239)
@@ -86,10 +86,11 @@
if (!matchWrk(mi, p->Iex.Binop.arg2, e->Iex.Binop.arg2))
return False;
return True;
- case Iex_LDle:
- if (e->tag !=3D Iex_LDle) return False;
- if (p->Iex.LDle.ty !=3D e->Iex.LDle.ty) return False;
- if (!matchWrk(mi, p->Iex.LDle.addr, e->Iex.LDle.addr))
+ case Iex_Load:
+ if (e->tag !=3D Iex_Load) return False;
+ if (p->Iex.Load.end !=3D e->Iex.Load.end) return False;
+ if (p->Iex.Load.ty !=3D e->Iex.Load.ty) return False;
+ if (!matchWrk(mi, p->Iex.Load.addr, e->Iex.Load.addr))
return False;
return True;
case Iex_Const:
Modified: trunk/priv/ir/iropt.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/iropt.c 2005-06-30 13:38:38 UTC (rev 1238)
+++ trunk/priv/ir/iropt.c 2005-06-30 23:31:27 UTC (rev 1239)
@@ -253,8 +253,8 @@
if (e->tag =3D=3D Iex_Binop)
return toBool( isIRAtom(e->Iex.Binop.arg1)=20
&& isIRAtom(e->Iex.Binop.arg2) );
- if (e->tag =3D=3D Iex_LDle)
- return isIRAtom(e->Iex.LDle.addr);
+ if (e->tag =3D=3D Iex_Load)
+ return isIRAtom(e->Iex.Load.addr);
return False;
}
=20
@@ -300,11 +300,12 @@
flatten_Expr(bb, ex->Iex.Unop.arg))));
return IRExpr_Tmp(t1);
=20
- case Iex_LDle:
+ case Iex_Load:
t1 =3D newIRTemp(bb->tyenv, ty);
addStmtToIRBB(bb, IRStmt_Tmp(t1,
- IRExpr_LDle(ex->Iex.LDle.ty,=20
- flatten_Expr(bb, ex->Iex.LDle.addr))));
+ IRExpr_Load(ex->Iex.Load.end,
+ ex->Iex.Load.ty,=20
+ flatten_Expr(bb, ex->Iex.Load.addr))));
return IRExpr_Tmp(t1);
=20
case Iex_CCall:
@@ -389,10 +390,10 @@
addStmtToIRBB(bb, IRStmt_Tmp(st->Ist.Tmp.tmp, e1));
}
break;
- case Ist_STle:
- e1 =3D flatten_Expr(bb, st->Ist.STle.addr);
- e2 =3D flatten_Expr(bb, st->Ist.STle.data);
- addStmtToIRBB(bb, IRStmt_STle(e1,e2));
+ case Ist_Store:
+ e1 =3D flatten_Expr(bb, st->Ist.Store.addr);
+ e2 =3D flatten_Expr(bb, st->Ist.Store.data);
+ addStmtToIRBB(bb, IRStmt_Store(st->Ist.Store.end, e1,e2));
break;
case Ist_Dirty:
d =3D st->Ist.Dirty.details;
@@ -652,7 +653,7 @@
isGet =3D True;
key =3D mk_key_GetIPutI ( e->Iex.GetI.descr );
break;
- case Iex_LDle:
+ case Iex_Load:
isGet =3D False;
memRW =3D True;
break;
@@ -686,9 +687,9 @@
break;
=20
/* all other cases are boring. */
- case Ist_STle:
- vassert(isIRAtom(st->Ist.STle.addr));
- vassert(isIRAtom(st->Ist.STle.data));
+ case Ist_Store:
+ vassert(isIRAtom(st->Ist.Store.addr));
+ vassert(isIRAtom(st->Ist.Store.data));
memRW =3D True;
break;
=20
@@ -1469,11 +1470,12 @@
subst_Expr(env, ex->Iex.Unop.arg)
);
=20
- case Iex_LDle:
- vassert(isIRAtom(ex->Iex.LDle.addr));
- return IRExpr_LDle(
- ex->Iex.LDle.ty,
- subst_Expr(env, ex->Iex.LDle.addr)
+ case Iex_Load:
+ vassert(isIRAtom(ex->Iex.Load.addr));
+ return IRExpr_Load(
+ ex->Iex.Load.end,
+ ex->Iex.Load.ty,
+ subst_Expr(env, ex->Iex.Load.addr)
);
=20
case Iex_CCall: {
@@ -1552,12 +1554,13 @@
fold_Expr(subst_Expr(env, st->Ist.Tmp.data))
);
=20
- case Ist_STle:
- vassert(isIRAtom(st->Ist.STle.addr));
- vassert(isIRAtom(st->Ist.STle.data));
- return IRStmt_STle(
- fold_Expr(subst_Expr(env, st->Ist.STle.addr)),
- fold_Expr(subst_Expr(env, st->Ist.STle.data))
+ case Ist_Store:
+ vassert(isIRAtom(st->Ist.Store.addr));
+ vassert(isIRAtom(st->Ist.Store.data));
+ return IRStmt_Store(
+ st->Ist.Store.end,
+ fold_Expr(subst_Expr(env, st->Ist.Store.addr)),
+ fold_Expr(subst_Expr(env, st->Ist.Store.data))
);
=20
case Ist_Dirty: {
@@ -1724,8 +1727,8 @@
for (i =3D 0; e->Iex.CCall.args[i]; i++)
addUses_Expr(set, e->Iex.CCall.args[i]);
return;
- case Iex_LDle:
- addUses_Expr(set, e->Iex.LDle.addr);
+ case Iex_Load:
+ addUses_Expr(set, e->Iex.Load.addr);
return;
case Iex_Binop:
addUses_Expr(set, e->Iex.Binop.arg1);
@@ -1765,9 +1768,9 @@
case Ist_Put:
addUses_Expr(set, st->Ist.Put.data);
return;
- case Ist_STle:
- addUses_Expr(set, st->Ist.STle.addr);
- addUses_Expr(set, st->Ist.STle.data);
+ case Ist_Store:
+ addUses_Expr(set, st->Ist.Store.addr);
+ addUses_Expr(set, st->Ist.Store.data);
return;
case Ist_Dirty:
d =3D st->Ist.Dirty.details;
@@ -2650,9 +2653,9 @@
}
return False;
=20
- case Ist_STle:
- vassert(isIRAtom(s2->Ist.STle.addr));
- vassert(isIRAtom(s2->Ist.STle.data));
+ case Ist_Store:
+ vassert(isIRAtom(s2->Ist.Store.addr));
+ vassert(isIRAtom(s2->Ist.Store.data));
return False;
=20
default:
@@ -2799,8 +2802,8 @@
case Iex_Unop:
deltaIRExpr(e->Iex.Unop.arg, delta);
break;
- case Iex_LDle:
- deltaIRExpr(e->Iex.LDle.addr, delta);
+ case Iex_Load:
+ deltaIRExpr(e->Iex.Load.addr, delta);
break;
case Iex_CCall:
for (i =3D 0; e->Iex.CCall.args[i]; i++)
@@ -2846,9 +2849,9 @@
case Ist_Exit:
deltaIRExpr(st->Ist.Exit.guard, delta);
break;
- case Ist_STle:
- deltaIRExpr(st->Ist.STle.addr, delta);
- deltaIRExpr(st->Ist.STle.data, delta);
+ case Ist_Store:
+ deltaIRExpr(st->Ist.Store.addr, delta);
+ deltaIRExpr(st->Ist.Store.data, delta);
break;
case Ist_Dirty:
d =3D st->Ist.Dirty.details;
@@ -3161,8 +3164,8 @@
occCount_Expr(env, e->Iex.Unop.arg);
return;
=20
- case Iex_LDle:=20
- occCount_Expr(env, e->Iex.LDle.addr);
+ case Iex_Load:
+ occCount_Expr(env, e->Iex.Load.addr);
return;
=20
case Iex_CCall:
@@ -3207,9 +3210,9 @@
occCount_Expr(env, st->Ist.PutI.ix);
occCount_Expr(env, st->Ist.PutI.data);
return;
- case Ist_STle:=20
- occCount_Expr(env, st->Ist.STle.addr);
- occCount_Expr(env, st->Ist.STle.data);
+ case Ist_Store:
+ occCount_Expr(env, st->Ist.Store.addr);
+ occCount_Expr(env, st->Ist.Store.data);
return;
case Ist_Dirty:
d =3D st->Ist.Dirty.details;
@@ -3296,10 +3299,11 @@
e->Iex.Unop.op,
tbSubst_Expr(env, e->Iex.Unop.arg)
);
- case Iex_LDle:
- return IRExpr_LDle(
- e->Iex.LDle.ty,
- tbSubst_Expr(env, e->Iex.LDle.addr)
+ case Iex_Load:
+ return IRExpr_Load(
+ e->Iex.Load.end,
+ e->Iex.Load.ty,
+ tbSubst_Expr(env, e->Iex.Load.addr)
);
case Iex_GetI:
return IRExpr_GetI(
@@ -3329,10 +3333,11 @@
tbSubst_Expr(env, st->Ist.AbiHint.base),
st->Ist.AbiHint.len
);
- case Ist_STle:
- return IRStmt_STle(
- tbSubst_Expr(env, st->Ist.STle.addr),
- tbSubst_Expr(env, st->Ist.STle.data)
+ case Ist_Store:
+ return IRStmt_Store(
+ st->Ist.Store.end,
+ tbSubst_Expr(env, st->Ist.Store.addr),
+ tbSubst_Expr(env, st->Ist.Store.data)
);
case Ist_Tmp:
return IRStmt_Tmp(
@@ -3405,9 +3410,9 @@
case Iex_Unop:
setHints_Expr(doesLoad, doesGet, e->Iex.Unop.arg);
return;
- case Iex_LDle:
+ case Iex_Load:
*doesLoad =3D True;
- setHints_Expr(doesLoad, doesGet, e->Iex.LDle.addr);
+ setHints_Expr(doesLoad, doesGet, e->Iex.Load.addr);
return;
case Iex_Get:
*doesGet =3D True;
@@ -3587,7 +3592,7 @@
|| st->tag =3D=3D Ist_PutI=20
|| st->tag =3D=3D Ist_Dirty);
=20
- invStore =3D toBool(st->tag =3D=3D Ist_STle
+ invStore =3D toBool(st->tag =3D=3D Ist_Store
|| st->tag =3D=3D Ist_Dirty);
=20
for (k =3D 0; k < n_tmps; k++) {
@@ -3741,9 +3746,9 @@
case Ist_Put:
vassert(isIRAtom(st->Ist.Put.data));
break;
- case Ist_STle:
- vassert(isIRAtom(st->Ist.STle.addr));
- vassert(isIRAtom(st->Ist.STle.data));
+ case Ist_Store:
+ vassert(isIRAtom(st->Ist.Store.addr));
+ vassert(isIRAtom(st->Ist.Store.data));
break;
case Ist_Dirty:
d =3D st->Ist.Dirty.details;
Modified: trunk/pub/libvex_ir.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/pub/libvex_ir.h 2005-06-30 13:38:38 UTC (rev 1238)
+++ trunk/pub/libvex_ir.h 2005-06-30 23:31:27 UTC (rev 1239)
@@ -87,6 +87,16 @@
extern Int sizeofIRType ( IRType );
=20
=20
+/* ------------------ Endianness ------------------ */
+
+typedef
+ enum {=20
+ Iend_LE=3D22, /* little endian */
+ Iend_BE=3D33 /* big endian */
+ }
+ IREndness;
+
+
/* ------------------ Constants ------------------ */
=20
typedef
@@ -655,7 +665,7 @@
Iex_Tmp, /* value of temporary */
Iex_Binop, /* binary operation */
Iex_Unop, /* unary operation */
- Iex_LDle, /* little-endian read from memory */=20
+ Iex_Load, /* read from memory */=20
Iex_Const, /* constant-valued expression */
Iex_Mux0X, /* ternary if-then-else operator (STRICT) */
Iex_CCall /* call to pure (side-effect-free) helper fn */
@@ -691,9 +701,10 @@
struct _IRExpr* arg;
} Unop;
struct {
+ IREndness end;
IRType ty;
struct _IRExpr* addr;
- } LDle;
+ } Load;
struct {
IRConst* con;
} Const;
@@ -717,7 +728,7 @@
extern IRExpr* IRExpr_Tmp ( IRTemp tmp );
extern IRExpr* IRExpr_Binop ( IROp op, IRExpr* arg1, IRExpr* arg2 );
extern IRExpr* IRExpr_Unop ( IROp op, IRExpr* arg );
-extern IRExpr* IRExpr_LDle ( IRType ty, IRExpr* addr );
+extern IRExpr* IRExpr_Load ( IREndness end, IRType ty, IRExpr* addr );
extern IRExpr* IRExpr_Const ( IRConst* con );
extern IRExpr* IRExpr_CCall ( IRCallee* cee, IRType retty, IRExpr** arg=
s );
extern IRExpr* IRExpr_Mux0X ( IRExpr* cond, IRExpr* expr0, IRExpr* expr=
X );
@@ -918,7 +929,7 @@
Ist_Put, /* write guest state, fixed offset */
Ist_PutI, /* write guest state, run-time offset */
Ist_Tmp, /* assign value to temporary */
- Ist_STle, /* little-endian write to memory */
+ Ist_Store, /* write to memory */
Ist_Dirty, /* call complex ("dirty") helper function */
Ist_MFence, /* memory fence */
Ist_Exit /* conditional exit from BB */
@@ -955,9 +966,10 @@
IRExpr* data;
} Tmp;
struct {
- IRExpr* addr;
- IRExpr* data;
- } STle;
+ IREndness end;
+ IRExpr* addr;
+ IRExpr* data;
+ } Store;
struct {
IRDirty* details;
} Dirty;
@@ -979,7 +991,7 @@
extern IRStmt* IRStmt_PutI ( IRArray* descr, IRExpr* ix, Int bias,=20
IRExpr* data );
extern IRStmt* IRStmt_Tmp ( IRTemp tmp, IRExpr* data );
-extern IRStmt* IRStmt_STle ( IRExpr* addr, IRExpr* data );
+extern IRStmt* IRStmt_Store ( IREndness end, IRExpr* addr, IRExpr* dat=
a );
extern IRStmt* IRStmt_Dirty ( IRDirty* details );
extern IRStmt* IRStmt_MFence ( void );
extern IRStmt* IRStmt_Exit ( IRExpr* guard, IRJumpKind jk, IRConst* d=
st );
|
|
From: <sv...@va...> - 2005-06-30 23:30:08
|
Author: njn
Date: 2005-07-01 00:30:05 +0100 (Fri, 01 Jul 2005)
New Revision: 133
Log:
bah
Modified:
trunk/gallery/survey_current/survey.html
Modified: trunk/gallery/survey_current/survey.html
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/gallery/survey_current/survey.html 2005-06-30 23:27:47 UTC (rev=
132)
+++ trunk/gallery/survey_current/survey.html 2005-06-30 23:30:05 UTC (rev=
133)
@@ -268,8 +268,7 @@
<tr><td>
<input type=3D"hidden" name=3D"Q0[q]" value=3D"q0. Contact details"/>
Please provide your contact details if you wish.<br />
-</td></tr>
- <table cellspacing=3D"2" cellpadding=3D"0" border=3D"0">
+ <table cellspacing=3D"2" cellpadding=3D"0" border=3D"0">
<tr>
<td>Name:</td>
<td><input name=3D"Q0[name]" size=3D"60" type=3D"text" value=3D""/></=
td>
@@ -282,8 +281,7 @@
<td>Country:</td>
<td><input name=3D"Q0[country]" size=3D"60" type=3D"text" value=3D""/=
></td>
</tr>
- </table>
-<tr><td>
+ </table>
Why are we asking for your name and email address? Partly because it
encourages more thoughtful responses if your name is attached. And pa=
rtly
because sometimes we respond to surveys -- for example, sometimes we c=
an
|
|
From: <sv...@va...> - 2005-06-30 23:28:38
|
Author: njn Date: 2005-07-01 00:27:47 +0100 (Fri, 01 Jul 2005) New Revision: 132 Log: wibbles Modified: trunk/gallery/survey_current/submitted.php trunk/gallery/survey_current/survey.html Modified: trunk/gallery/survey_current/submitted.php =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/gallery/survey_current/submitted.php 2005-06-30 23:19:32 UTC (r= ev 131) +++ trunk/gallery/survey_current/submitted.php 2005-06-30 23:27:47 UTC (r= ev 132) @@ -7,7 +7,8 @@ $post =3D $_POST['Q0']; $results .=3D $post['q']. "\n"; $results .=3D $post['name']. "\n"; -$results .=3D $post['email']. "\n\n"; +$results .=3D $post['email']. "\n"; +$results .=3D $post['country']. "\n\n"; =20 /*------ using valgrind ------*/ $post =3D $_POST['Q1']; Modified: trunk/gallery/survey_current/survey.html =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/gallery/survey_current/survey.html 2005-06-30 23:19:32 UTC (rev= 131) +++ trunk/gallery/survey_current/survey.html 2005-06-30 23:27:47 UTC (rev= 132) @@ -128,7 +128,6 @@ <textarea name=3D"Q8[txt]" rows=3D"2" cols=3D"56"></textarea> </td></tr> </table> -<p> </p> =20 <!-- valgrind on other platforms --> <table class=3D"form" width=3D"100%" cellspacing=3D"8" cellpadding=3D"0"= border=3D"0"> @@ -148,7 +147,6 @@ <textarea name=3D"Q9[txt]" rows=3D"10" cols=3D"56"></textarea> </td></tr> </table> -<p> </p> =20 <!-- software issues --> <table class=3D"form" width=3D"100%" cellspacing=3D"8" cellpadding=3D"0"= border=3D"0"> @@ -187,7 +185,6 @@ <textarea name=3D"Q13[txt]" rows=3D"3" cols=3D"56"></textarea> </td></tr> </table> -<p> </p> =20 <!-- non-software issues --> <table class=3D"form" width=3D"100%" cellspacing=3D"8" cellpadding=3D"0"= border=3D"0"> @@ -213,7 +210,6 @@ <textarea name=3D"Q15[txt]" rows=3D"3" cols=3D"56"></textarea> </td></tr> </table> -<p> </p> =20 <!-- project details --> <table class=3D"form" width=3D"100%" cellspacing=3D"8" cellpadding=3D"0"= border=3D"0"> @@ -226,7 +222,7 @@ information. (Omit any details you want to keep private. Please estimate for any answers you're unsure about. Take more than one line per answer if necessary.)<br/> - <textarea name=3D"Q16[txt]" rows=3D"14" cols=3D"56"> + <textarea name=3D"Q16[txt]" rows=3D"10" cols=3D"56"> Project name :=20 Website (if one exists) :=20 Brief description :=20 @@ -249,7 +245,6 @@ <input name=3D"Q16[rb]" type=3D"radio" value=3D"no"/> No<br/> </td></tr> </table> -<p> </p> =20 <!-- other comments --> <table class=3D"form" width=3D"100%" cellspacing=3D"8" cellpadding=3D"0"= border=3D"0"> @@ -274,29 +269,30 @@ <input type=3D"hidden" name=3D"Q0[q]" value=3D"q0. Contact details"/> Please provide your contact details if you wish.<br /> </td></tr> -<tr> - <td>Name:</td> - <td><input name=3D"Q0[name]" size=3D"60" type=3D"text" value=3D""/></t= d> -</tr> -<tr> - <td>Email:</td> - <td><input name=3D"Q0[email]" size=3D"60" type=3D"text" value=3D""/></= td> -</tr> -<tr> - <td>Country:</td> - <td><input name=3D"Q0[email]" size=3D"60" type=3D"text" value=3D""/></= td> -</tr> + <table cellspacing=3D"2" cellpadding=3D"0" border=3D"0"> + <tr> + <td>Name:</td> + <td><input name=3D"Q0[name]" size=3D"60" type=3D"text" value=3D""/></= td> + </tr> + <tr> + <td>Email:</td> + <td><input name=3D"Q0[email]" size=3D"60" type=3D"text" value=3D""/><= /td> + </tr> + <tr> + <td>Country:</td> + <td><input name=3D"Q0[country]" size=3D"60" type=3D"text" value=3D""/= ></td> + </tr> + </table> <tr><td> - Why are we asking your name and email? Partly because it encourages - more thoughtful responses if your name is attached. And partly becuas - sometimes we respond to surveys; for example point out that a feature - that a responder thought was missing is actually implemented. As for - the country, we're just curious to see how widely Valgrind is used! + Why are we asking for your name and email address? Partly because it + encourages more thoughtful responses if your name is attached. And pa= rtly + because sometimes we respond to surveys -- for example, sometimes we c= an + point out that a feature that a responder thought was missing is actua= lly + implemented. As for your country, we're just curious to see how widel= y + Valgrind is used! </td></tr> </table> -<p> </p> =20 - <p align=3D"center"> <input type=3D"submit" name=3D"send" value=3D"Submit" /><br /><br /> Thank you for your time and support. |
|
From: <sv...@va...> - 2005-06-30 23:20:34
|
Author: sewardj Date: 2005-07-01 00:20:30 +0100 (Fri, 01 Jul 2005) New Revision: 4070 Log: Add missing #include. Modified: trunk/cachegrind/cg-amd64.c Modified: trunk/cachegrind/cg-amd64.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/cachegrind/cg-amd64.c 2005-06-30 12:40:17 UTC (rev 4069) +++ trunk/cachegrind/cg-amd64.c 2005-06-30 23:20:30 UTC (rev 4070) @@ -29,6 +29,7 @@ */ =20 #include "pub_tool_basics.h" +#include "pub_tool_cpuid.h" #include "pub_tool_libcbase.h" #include "pub_tool_libcassert.h" #include "pub_tool_libcprint.h" |
|
From: <sv...@va...> - 2005-06-30 23:19:39
|
Author: njn
Date: 2005-07-01 00:19:32 +0100 (Fri, 01 Jul 2005)
New Revision: 131
Log:
Streamline survey.
Modified:
trunk/gallery/survey_current/submitted.php
trunk/gallery/survey_current/survey.html
Modified: trunk/gallery/survey_current/submitted.php
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/gallery/survey_current/submitted.php 2005-06-30 01:54:20 UTC (r=
ev 130)
+++ trunk/gallery/survey_current/submitted.php 2005-06-30 23:19:32 UTC (r=
ev 131)
@@ -9,43 +9,25 @@
$results .=3D $post['name']. "\n";
$results .=3D $post['email']. "\n\n";
=20
-/*------ learning about valgrind ------*/
+/*------ using valgrind ------*/
$post =3D $_POST['Q1'];
$results .=3D $post['q']. "\n";
-$results .=3D $post['rb']. "\n";
-if ( !empty( $post['txt'] ) ) {
- $results .=3D $post['cmt']. "\n";
- $results .=3D $post['txt']. "\n";
-}
-$results .=3D "\n";
+$results .=3D $post['txt']. "\n\n";
=20
$post =3D $_POST['Q2'];
$results .=3D $post['q']. "\n";
-$results .=3D $post['txt']. "\n\n";
+$results .=3D $post['rb']. "\n\n";
=20
$post =3D $_POST['Q3'];
$results .=3D $post['q']. "\n";
$results .=3D $post['txt']. "\n\n";
=20
-/*------ using valgrind ------*/
$post =3D $_POST['Q4'];
$results .=3D $post['q']. "\n";
$results .=3D $post['txt']. "\n\n";
=20
$post =3D $_POST['Q5'];
$results .=3D $post['q']. "\n";
-$results .=3D $post['rb']. "\n\n";
-
-$post =3D $_POST['Q6'];
-$results .=3D $post['q']. "\n";
-$results .=3D $post['txt']. "\n\n";
-
-$post =3D $_POST['Q7'];
-$results .=3D $post['q']. "\n";
-$results .=3D $post['txt']. "\n\n";
-
-$post =3D $_POST['Q8'];
-$results .=3D $post['q']. "\n";
if ( !empty( $post['cb1'] ) )
$results .=3D $post['cb1']. "\n";
if ( !empty( $post['cb2'] ) )
@@ -62,7 +44,7 @@
}
$results .=3D "\n";
=20
-$post =3D $_POST['Q9'];
+$post =3D $_POST['Q6'];
$results .=3D $post['q']. "\n";
if ( !empty( $post['txt0'] ) )
$results .=3D "memcheck ". $post['txt0']. "\n";
@@ -80,71 +62,54 @@
$results .=3D "other ". $post['txt6']. "\n";
$results .=3D "\n";
=20
-$post =3D $_POST['Q10'];
+$post =3D $_POST['Q7'];
$results .=3D $post['q']. "\n";
$results .=3D $post['txt']. "\n\n";
=20
-$post =3D $_POST['Q11'];
+$post =3D $_POST['Q8'];
$results .=3D $post['q']. "\n";
$results .=3D $post['txt']. "\n\n";
=20
-$post =3D $_POST['Q12'];
-$results .=3D $post['q']. "\n";
-$results .=3D $post['txt']. "\n\n";
-
/*------ valgrind on other platforms ------*/
-$post =3D $_POST['Q13'];
+$post =3D $_POST['Q9'];
$results .=3D $post['q']. "\n";
$results .=3D $post['txt']. "\n\n";
=20
/*------ software issues ------*/
-$post =3D $_POST['Q14'];
+$post =3D $_POST['Q10'];
$results .=3D $post['q']. "\n";
$results .=3D $post['txt']. "\n\n";
=20
-$post =3D $_POST['Q15'];
+$post =3D $_POST['Q11'];
$results .=3D $post['q']. "\n";
$results .=3D $post['txt']. "\n\n";
=20
-$post =3D $_POST['Q16'];
+$post =3D $_POST['Q12'];
$results .=3D $post['q']. "\n";
$results .=3D $post['txt']. "\n\n";
=20
-$post =3D $_POST['Q17'];
+$post =3D $_POST['Q13'];
$results .=3D $post['q']. "\n";
$results .=3D $post['txt']. "\n\n";
=20
-$post =3D $_POST['Q18'];
-$results .=3D $post['q']. "\n";
-$results .=3D $post['txt']. "\n\n";
-
/*------ non-software issues ------*/
-$post =3D $_POST['Q19'];
+$post =3D $_POST['Q14'];
$results .=3D $post['q']. "\n";
$results .=3D $post['txt']. "\n\n";
=20
-$post =3D $_POST['Q20'];
+$post =3D $_POST['Q15'];
$results .=3D $post['q']. "\n";
$results .=3D $post['txt']. "\n\n";
=20
-$post =3D $_POST['Q21'];
-$results .=3D $post['q']. "\n";
-$results .=3D $post['txt']. "\n\n";
-
/*------ project details ------*/
-$post =3D $_POST['Q22'];
+$post =3D $_POST['Q16'];
$txt =3D ' Project name :=20
Website (if one exists) :=20
Brief description :=20
- Public or private? :=20
- License : (eg. GNU GPL; BSD; proprietary)
Language(s) : (estimate proportions if > 1, eg. 80% C, 20% For=
tran)
- No of programmers in total :=20
- No of programmers using Valgrind :=20
+ Number of programmers:=20
Size (lines of code) :=20
- No. of users :=20
- Development location :=20
- Other comments : ';
+ Number of users : ';
$txt =3D ereg_replace( "\n", "", $txt );
$tmp =3D ereg_replace( "\n", "", $post['txt'] );
$tmp =3D ereg_replace( "\r", "", $tmp );
@@ -156,10 +121,14 @@
$results .=3D $post['rb']. "\n\n";
=20
/*------ surveys ------*/
-$post =3D $_POST['Q23'];
+$post =3D $_POST['Q17'];
$results .=3D $post['q']. "\n";
$results .=3D $post['txt']. "\n\n";
=20
+$post =3D $_POST['Q18'];
+$results .=3D $post['q']. "\n";
+$results .=3D $post['txt']. "\n\n";
+
/*
echo "<pre>\n";
print( $results );
Modified: trunk/gallery/survey_current/survey.html
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/gallery/survey_current/survey.html 2005-06-30 01:54:20 UTC (rev=
130)
+++ trunk/gallery/survey_current/survey.html 2005-06-30 23:19:32 UTC (rev=
131)
@@ -27,150 +27,106 @@
=20
<form method=3D"post" action=3D"<?php echo $_SERVER['SCRIPT_NAME']; ?>">
=20
-<!-- learning about valgrind -->
-<table class=3D"form" width=3D"100%" cellspacing=3D"8" cellpadding=3D"0"=
border=3D"0">
-<tr><th>Learning about Valgrind</th></tr>
-<tr><td>
- <input type=3D"hidden" name=3D"Q1[q]"=20
- value=3D"q1. How did you first learn about Valgrind"/>
- <b>1. </b>How did you first learn about Valgrind?<br />
- <input name=3D"Q1[rb]" type=3D"radio"=20
- value=3D"from a friend"/> from a friend<br/>
- <input name=3D"Q1[rb]" type=3D"radio"=20
- value=3D"from a workmate"/> from a workmate<br/>
- <input name=3D"Q1[rb]" type=3D"radio"=20
- value=3D"searching for tools"/> searching for tools<br/>
- <input name=3D"Q1[rb]" type=3D"radio"=20
- value=3D"from a publication"/> from a publication
- (please specify publication name below)<br/>
- <input name=3D"Q1[rb]" type=3D"radio" value=3D"other"/> other=20
- (please specify below)<br/>
- <p>
- <input type=3D"hidden" name=3D"Q1[cmt]" value=3D"Extra info:"/>
- <textarea name=3D"Q1[txt]" rows=3D"2" cols=3D"56"></textarea></p>
-</td></tr>
-<tr><td>
- <input type=3D"hidden" name=3D"Q2[q]"=20
- value=3D"q2. How many other programmers have you told about Valgrind"=
/>
- <b>2. </b>How many other programmers have you told about Valgrind?<br /=
>
- How many of them have used it as a consequence?<br />
- <textarea name=3D"Q2[txt]" rows=3D"2" cols=3D"56"></textarea>
-</td></tr>
-<tr><td>
- <b>3. </b>Any other comments about how you first learnt about Valgrind?=
<br />
- <input type=3D"hidden" name=3D"Q3[q]"=20
- value=3D"q3. Other comments about learning about Valgrind"/>
- <textarea name=3D"Q3[txt]" rows=3D"2" cols=3D"56"></textarea>
-</td></tr>
-</table>
-<p> </p>
-
<!-- using valgrind -->
<table class=3D"form" width=3D"100%" cellspacing=3D"8" cellpadding=3D"0"=
border=3D"0">
<tr><th>Using Valgrind</th></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q4[q]"=20
- value=3D"q4. How long (in months) have you been using Valgrind"/=
>
- <b>4. </b>Approximately how long (in months) have you been using Valgri=
nd?<br />
- <input name=3D"Q4[txt]" size=3D"60" type=3D"text" value=3D""/>
+ <input type=3D"hidden" name=3D"Q1[q]"=20
+ value=3D"q1. How long (in months) have you been using Valgrind"/=
>
+ <b>1. </b>Approximately how long (in months) have you been using Valgri=
nd?<br />
+ <input name=3D"Q1[txt]" size=3D"60" type=3D"text" value=3D""/>
</td></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q5[q]"=20
- value=3D"q5. On average how often do you use Valgrind"/>
- <b>5. </b>Which of the following best describes how often you use
+ <input type=3D"hidden" name=3D"Q2[q]"=20
+ value=3D"q2. On average how often do you use Valgrind"/>
+ <b>2. </b>Which of the following best describes how often you use
Valgrind?<br />
- <input name=3D"Q5[rb]" type=3D"radio" value=3D"hourly" /> hourly <br/>
- <input name=3D"Q5[rb]" type=3D"radio" value=3D"daily" /> daily <br/>
- <input name=3D"Q5[rb]" type=3D"radio" value=3D"weekly" /> weekly <br/>
- <input name=3D"Q5[rb]" type=3D"radio" value=3D"monthly"/> monthly<br/>
+ <input name=3D"Q2[rb]" type=3D"radio" value=3D"hourly" /> hourly <br/>
+ <input name=3D"Q2[rb]" type=3D"radio" value=3D"daily" /> daily <br/>
+ <input name=3D"Q2[rb]" type=3D"radio" value=3D"weekly" /> weekly <br/>
+ <input name=3D"Q2[rb]" type=3D"radio" value=3D"monthly"/> monthly<br/>
</td></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q6[q]"=20
- value=3D"q6. What hardware do you use Valgrind on"/>
- <b>6. </b>What hardware do you use Valgrind on?<br />
+ <input type=3D"hidden" name=3D"Q3[q]"=20
+ value=3D"q3. What hardware do you use Valgrind on"/>
+ <b>3. </b>What hardware do you use Valgrind on?<br />
Estimate the proportion of your Valgrind usage on different
machines. (Example: Pentium 4 70%, Athlon 30%)<br />
- <textarea name=3D"Q6[txt]" rows=3D"2" cols=3D"56"></textarea>
+ <textarea name=3D"Q3[txt]" rows=3D"2" cols=3D"56"></textarea>
</td></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q7[q]"=20
- value=3D"q7. What Linux distros do you use Valgrind on"/>
- <b>7. </b>What operating systems(s) do you use Valgrind on?<br />
+ <input type=3D"hidden" name=3D"Q4[q]"=20
+ value=3D"q4. What Linux distros do you use Valgrind on"/>
+ <b>4. </b>What operating systems(s) do you use Valgrind on?<br />
Estimate the proportion of your Valgrind usage on different
operating systems. Please give version numbers if
possible. (Example: Linux RedHat 9.0 90%, Linux SuSe 8.1 10%)<br />
- <textarea name=3D"Q7[txt]" rows=3D"2" cols=3D"56"></textarea>
+ <textarea name=3D"Q4[txt]" rows=3D"2" cols=3D"56"></textarea>
</td></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q8[q]"=20
- value=3D"q8. In what form did you/do you obtain Valgrind"/>
- <b>8. </b>In what form did you/do you obtain Valgrind?<br />
- <input name=3D"Q8[cb1]" type=3D"checkbox" value=3D"cvs"/> source, fro=
m CVS<br/>
- <input name=3D"Q8[cb2]" type=3D"checkbox" value=3D"www"/> source, from=
website<br/>
- <input name=3D"Q8[cb3]" type=3D"checkbox" value=3D"rpm"/> pre-built ve=
rsion (eg. RPM)<br/>
- <input name=3D"Q8[cb4]" type=3D"checkbox" value=3D"inst"/> already ins=
talled on system<br/>
- <input name=3D"Q8[cb5]" type=3D"checkbox" value=3D"other"/> other (ple=
ase specify below)<br/>
+ <input type=3D"hidden" name=3D"Q5[q]"=20
+ value=3D"q5. In what form did you/do you obtain Valgrind"/>
+ <b>5. </b>In what form did you/do you obtain Valgrind?<br />
+ <input name=3D"Q5[cb1]" type=3D"checkbox" value=3D"cvs"/> source, fro=
m CVS<br/>
+ <input name=3D"Q5[cb2]" type=3D"checkbox" value=3D"www"/> source, from=
website<br/>
+ <input name=3D"Q5[cb3]" type=3D"checkbox" value=3D"rpm"/> pre-built ve=
rsion (eg. RPM)<br/>
+ <input name=3D"Q5[cb4]" type=3D"checkbox" value=3D"inst"/> already ins=
talled on system<br/>
+ <input name=3D"Q5[cb5]" type=3D"checkbox" value=3D"other"/> other (ple=
ase specify below)<br/>
<p>
- <input type=3D"hidden" name=3D"Q8[cmt]" value=3D"Extra info:"/>
- <textarea name=3D"Q8[txt]" rows=3D"2" cols=3D"56"></textarea></p>
+ <input type=3D"hidden" name=3D"Q5[cmt]" value=3D"Extra info:"/>
+ <textarea name=3D"Q5[txt]" rows=3D"2" cols=3D"56"></textarea></p>
</td></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q9[q]"=20
- value=3D"q9. Which Valgrind tools do you use"/>
- <b>9. </b>Which Valgrind tools do you use?<br />
+ <input type=3D"hidden" name=3D"Q6[q]"=20
+ value=3D"q6. Which Valgrind tools do you use"/>
+ <b>6. </b>Which Valgrind tools do you use?<br />
Estimate the proportion of your Valgrind usage each tool
accounts for. (Example: Memcheck 80%, Addrcheck 10%,
Cachegrind 10%)<br />
<table cellspacing=3D"2" cellpadding=3D"0" border=3D"0">
<tr>
<td>Memcheck :</td>
- <td><input name=3D"Q9[txt0]" size=3D"30" type=3D"text" value=3D""/><=
/td>
+ <td><input name=3D"Q6[txt0]" size=3D"30" type=3D"text" value=3D""/><=
/td>
</tr>
<tr>
<td>Addrcheck :</td>
- <td><input name=3D"Q9[txt1]" size=3D"30" type=3D"text" value=3D""/><=
/td>
+ <td><input name=3D"Q6[txt1]" size=3D"30" type=3D"text" value=3D""/><=
/td>
</tr>
<tr>
<td>Cachegrind :</td>
- <td><input name=3D"Q9[txt2]" size=3D"30" type=3D"text" value=3D""/><=
/td>
+ <td><input name=3D"Q6[txt2]" size=3D"30" type=3D"text" value=3D""/><=
/td>
</tr>
<tr>
<td>Helgrind :</td>
- <td><input name=3D"Q9[txt3]" size=3D"30" type=3D"text" value=3D""/><=
/td>
+ <td><input name=3D"Q6[txt3]" size=3D"30" type=3D"text" value=3D""/><=
/td>
</tr>
<tr>
<td>Callgrind/KCachegrind : </td>
- <td><input name=3D"Q9[txt4]" size=3D"30" type=3D"text" value=3D""/><=
/td>
+ <td><input name=3D"Q6[txt4]" size=3D"30" type=3D"text" value=3D""/><=
/td>
</tr>
<tr>
<td>Massif :</td>
- <td><input name=3D"Q9[txt5]" size=3D"30" type=3D"text" value=3D""/><=
/td>
+ <td><input name=3D"Q6[txt5]" size=3D"30" type=3D"text" value=3D""/><=
/td>
</tr>
<tr>
<td>Other :</td>
- <td><input name=3D"Q9[txt6]" size=3D"30" type=3D"text" value=3D""/><=
/td>
+ <td><input name=3D"Q6[txt6]" size=3D"30" type=3D"text" value=3D""/><=
/td>
</tr>
</table>
</td></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q10[q]"=20
- value=3D"q10. Which command-line options do you (almost) always use=
"/>
- <b>10. </b>Which of Valgrind's command-line options do you always, or
+ <input type=3D"hidden" name=3D"Q7[q]"=20
+ value=3D"q7. Which command-line options do you (almost) always use"=
/>
+ <b>7. </b>Which of Valgrind's command-line options do you always, or
almost always, use?<br />
- <textarea name=3D"Q10[txt]" rows=3D"2" cols=3D"56"></textarea>
+ <textarea name=3D"Q7[txt]" rows=3D"2" cols=3D"56"></textarea>
</td></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q11[q]"=20
- value=3D"q11. Which command-line options do you sometimes use"/>
- <b>11. </b>Which of Valgrind's command-line options you sometimes use?=
<br />
- <textarea name=3D"Q11[txt]" rows=3D"2" cols=3D"56"></textarea>
+ <input type=3D"hidden" name=3D"Q8[q]"=20
+ value=3D"q8. Which command-line options do you sometimes use"/>
+ <b>8. </b>Which of Valgrind's command-line options you sometimes use?<=
br />
+ <textarea name=3D"Q8[txt]" rows=3D"2" cols=3D"56"></textarea>
</td></tr>
-<tr><td>
- <b>12. </b>Any other comments about how you use Valgrind?<br />
- <input type=3D"hidden" name=3D"Q12[q]"=20
- value=3D"q12. Other comments about using Valgrind:"/>
- <textarea name=3D"Q12[txt]" rows=3D"2" cols=3D"56"></textarea>
-</td></tr>
</table>
<p> </p>
=20
@@ -178,9 +134,9 @@
<table class=3D"form" width=3D"100%" cellspacing=3D"8" cellpadding=3D"0"=
border=3D"0">
<tr><th>Valgrind on Other Platforms</th></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q13[q]"=20
- value=3D"q13. Percentage of use on all platforms, if available"/>
- <b>13. </b>If Valgrind was available on all hardware/OS platforms,
+ <input type=3D"hidden" name=3D"Q9[q]"=20
+ value=3D"q9. Percentage of use on all platforms, if available"/>
+ <b>9. </b>If Valgrind was available on all hardware/OS platforms,
estimate what proportion of your usage would be on each
platform. Please describe each platform as precisely as
possible.<br />
@@ -189,7 +145,7 @@
- SPARC9/Solaris : 25%<br />
- x86/Linux : 20%<br />
- IA64/Linux : 5%<br />
- <textarea name=3D"Q13[txt]" rows=3D"10" cols=3D"56"></textarea>
+ <textarea name=3D"Q9[txt]" rows=3D"10" cols=3D"56"></textarea>
</td></tr>
</table>
<p> </p>
@@ -204,38 +160,32 @@
etc.<br />
</td></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q14[q]"=20
- value=3D"q14. List up to 3 existing good features"/>
- <b>14. </b>List up to 3 existing features of Valgrind that you think
+ <input type=3D"hidden" name=3D"Q10[q]"=20
+ value=3D"q10. List up to 3 existing good features"/>
+ <b>10. </b>List up to 3 existing features of Valgrind that you think
are good. Give as much detail as necessary.<br />
- <textarea name=3D"Q14[txt]" rows=3D"3" cols=3D"56"></textarea>
+ <textarea name=3D"Q10[txt]" rows=3D"3" cols=3D"56"></textarea>
</td></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q15[q]"=20
- value=3D"q15. List up to 3 existing improvable features"/>
- <b>15. </b>List up to 3 existing features of Valgrind that you think
+ <input type=3D"hidden" name=3D"Q11[q]"=20
+ value=3D"q11. List up to 3 existing improvable features"/>
+ <b>11. </b>List up to 3 existing features of Valgrind that you think
need improvement. Give as much detail as necessary.<br />
- <textarea name=3D"Q15[txt]" rows=3D"3" cols=3D"56"></textarea>
+ <textarea name=3D"Q11[txt]" rows=3D"3" cols=3D"56"></textarea>
</td></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q16[q]"=20
- value=3D"q16. List up to 3 missing features"/>
- <b>16. </b>List up to 3 missing features you would like added to
+ <input type=3D"hidden" name=3D"Q12[q]"=20
+ value=3D"q12. List up to 3 missing features"/>
+ <b>12. </b>List up to 3 missing features you would like added to
Valgrind. <br />
- <textarea name=3D"Q16[txt]" rows=3D"3" cols=3D"56"></textarea>
+ <textarea name=3D"Q12[txt]" rows=3D"3" cols=3D"56"></textarea>
</td></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q17[q]" value=3D"q17. Ideas for new tool=
s"/>
- <b>17. </b>Do you have ideas/wishes for new tools that could be built
+ <input type=3D"hidden" name=3D"Q13[q]" value=3D"q13. Ideas for new tool=
s"/>
+ <b>13. </b>Do you have ideas/wishes for new tools that could be built
with Valgrind? Give as much detail as necessary.<br />
- <textarea name=3D"Q17[txt]" rows=3D"3" cols=3D"56"></textarea>
+ <textarea name=3D"Q13[txt]" rows=3D"3" cols=3D"56"></textarea>
</td></tr>
-<tr><td>
- <b>18. </b>Any other comments about software issues?<br />
- <input type=3D"hidden" name=3D"Q18[q]"
- value=3D"q18. Other comments about software issues"/>
- <textarea name=3D"Q18[txt]" rows=3D"2" cols=3D"56"></textarea>
-</td></tr>
</table>
<p> </p>
=20
@@ -248,26 +198,20 @@
publicity, etc.
</td></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q19[q]"=20
- value=3D"q19. List up to 3 good development aspects"/>
- <b>19. </b>List up to 3 aspects of Valgrind's development that you
+ <input type=3D"hidden" name=3D"Q14[q]"=20
+ value=3D"q14. List up to 3 good development aspects"/>
+ <b>14. </b>List up to 3 aspects of Valgrind's development that you
think are good. Give as much detail as necessary.<br />
- <textarea name=3D"Q19[txt]" rows=3D"3" cols=3D"56"></textarea>
+ <textarea name=3D"Q14[txt]" rows=3D"3" cols=3D"56"></textarea>
</td></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q20[q]"=20
- value=3D"q20. List up to 3 improvable development aspects"/>
- <b>20. </b>List up to 3 aspects of Valgrind's development
+ <input type=3D"hidden" name=3D"Q15[q]"=20
+ value=3D"q15. List up to 3 improvable development aspects"/>
+ <b>15. </b>List up to 3 aspects of Valgrind's development
that you think need improvement.<br />
Give as much detail as necessary.<br />
- <textarea name=3D"Q20[txt]" rows=3D"3" cols=3D"56"></textarea>
+ <textarea name=3D"Q15[txt]" rows=3D"3" cols=3D"56"></textarea>
</td></tr>
-<tr><td>
- <b>21. </b>Any other comments about non-software issues?<br />
- <input type=3D"hidden" name=3D"Q21[q]"=20
- value=3D"q21. Other comments about non-software issues"/>
- <textarea name=3D"Q21[txt]" rows=3D"2" cols=3D"56"></textarea>
-</td></tr>
</table>
<p> </p>
=20
@@ -275,29 +219,25 @@
<table class=3D"form" width=3D"100%" cellspacing=3D"8" cellpadding=3D"0"=
border=3D"0">
<tr><th>Project Details</th></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q22[q]"=20
- value=3D"q22. Project use information"/>
- <b>22. </b>For <b>each project</b> on which you have used
+ <input type=3D"hidden" name=3D"Q16[q]"=20
+ value=3D"q16. Project use information"/>
+ <b>16. </b>For <b>each project</b> on which you have used
Valgrind, we would be interested to know the following
information. (Omit any details you want to keep private.
Please estimate for any answers you're unsure about. Take more
than one line per answer if necessary.)<br/>
- <textarea name=3D"Q22[txt]" rows=3D"14" cols=3D"56">
+ <textarea name=3D"Q16[txt]" rows=3D"14" cols=3D"56">
Project name :=20
Website (if one exists) :=20
Brief description :=20
- Public or private? :=20
- License : (eg. GNU GPL; BSD; proprietary)
Language(s) : (estimate proportions if > 1, eg. 80% C, 20% Fortran 7=
7)
- No of programmers in total :=20
- No of programmers using Valgrind :=20
+ Number of programmers:=20
Size (lines of code) :=20
- No. of users :=20
- Development location :=20
- Other comments : </textarea>
+ Number of users :
+ </textarea>
</td></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q22[q2]"=20
+ <input type=3D"hidden" name=3D"Q16[q2]"=20
value=3D"Do you want project mentioned on valgrind.org"/>
Would you be willing to have your project
mentioned on the Valgrind website as one that uses Valgrind?
@@ -305,21 +245,26 @@
within your project to do so, or you have asked someone with
the appropriate authority.) We will only mention the project name,
website, and a brief description.<br />
- <input name=3D"Q22[rb]" type=3D"radio" value=3D"yes"/> Yes<br/>
- <input name=3D"Q22[rb]" type=3D"radio" value=3D"no"/> No<br/>
+ <input name=3D"Q16[rb]" type=3D"radio" value=3D"yes"/> Yes<br/>
+ <input name=3D"Q16[rb]" type=3D"radio" value=3D"no"/> No<br/>
</td></tr>
</table>
<p> </p>
=20
-<!-- valgrind surveys -->
+<!-- other comments -->
<table class=3D"form" width=3D"100%" cellspacing=3D"8" cellpadding=3D"0"=
border=3D"0">
-<tr><th>Surveys</th></tr>
+<tr><th>Other comments</th></tr>
<tr><td>
- <input type=3D"hidden" name=3D"Q23[q]" value=3D"q23. Survey comments:"=
/>
- <b>23. </b>Any comments about the content or structure of
+ <input type=3D"hidden" name=3D"Q17[q]" value=3D"q17. Survey comments:"=
/>
+ <b>17. </b>Any comments about the content or structure of
this survey?<br/>
- <textarea name=3D"Q23[txt]" rows=3D"3" cols=3D"56"></textarea>
+ <textarea name=3D"Q17[txt]" rows=3D"3" cols=3D"56"></textarea>
</td></tr>
+<tr><td>
+ <input type=3D"hidden" name=3D"Q18[q]" value=3D"q18. Survey comments:"=
/>
+ <b>18. </b>Any other comments about Valgrind?<br/>
+ <textarea name=3D"Q18[txt]" rows=3D"3" cols=3D"56"></textarea>
+</td></tr>
</table>
=20
<!-- contact details -->
@@ -337,6 +282,17 @@
<td>Email:</td>
<td><input name=3D"Q0[email]" size=3D"60" type=3D"text" value=3D""/></=
td>
</tr>
+<tr>
+ <td>Country:</td>
+ <td><input name=3D"Q0[email]" size=3D"60" type=3D"text" value=3D""/></=
td>
+</tr>
+<tr><td>
+ Why are we asking your name and email? Partly because it encourages
+ more thoughtful responses if your name is attached. And partly becuas
+ sometimes we respond to surveys; for example point out that a feature
+ that a responder thought was missing is actually implemented. As for
+ the country, we're just curious to see how widely Valgrind is used!
+</td></tr>
</table>
<p> </p>
=20
|
|
From: Jeremy F. <je...@go...> - 2005-06-30 20:07:15
|
Julian Seward wrote:
>Suppose stage2 is statically linked, including the relevant tool,
>and is linked to load at some non-standard address, the latter as
>at present. Then there would be no need for stage1 at all, and no
>need for address space padding/unpadding. Is that correct?
>
>
Pretty much. For usability you'd have a simple program to select the
right backend binary for a particular tool, and maybe for the
appropriate CPU type (so it can handle x86 and x86-64 in a
user-transparent way).
J
|
|
From: <sv...@va...> - 2005-06-30 13:39:37
|
Author: sewardj
Date: 2005-06-30 14:38:38 +0100 (Thu, 30 Jun 2005)
New Revision: 1238
Log:
deltaIRStmt: handle IRStmt_MFence.
Modified:
trunk/priv/ir/iropt.c
Modified: trunk/priv/ir/iropt.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/ir/iropt.c 2005-06-30 12:50:50 UTC (rev 1237)
+++ trunk/priv/ir/iropt.c 2005-06-30 13:38:38 UTC (rev 1238)
@@ -2827,6 +2827,7 @@
switch (st->tag) {
case Ist_NoOp:
case Ist_IMark:
+ case Ist_MFence:
break;
case Ist_AbiHint:
deltaIRExpr(st->Ist.AbiHint.base, delta);
|
|
From: Julian S. <js...@ac...> - 2005-06-30 13:37:52
|
> This test always fails for me, and it fails on some/all of the nightly > test machines. [..] Yes, I was just thinking that improved filtering on the output wouldn't hurt. I'll make it so. > Julian, there's a xml1.stderr.exp64, but it looks like the XML output > format has changed since it was written. Can you take a look? Thanks. Will do. J |
|
From: Nicholas N. <nj...@cs...> - 2005-06-30 13:03:29
|
On Thu, 30 Jun 2005, sv...@va... wrote: > Log: > Update expected output. > > Modified: > trunk/memcheck/tests/xml1.stderr.exp This test always fails for me, and it fails on some/all of the nightly test machines. A large part of the problem is that with XML output details of the suppressed errors are printed, and they depend greatly on which glibc you are running. Eg. the expected output gets one suppressed "Ugly strchr" error, whereas on my machine I see suppressed two _dl_start errors and and index error. Filtering out the content between the <suppcounts> tags would solve that part of the problem. Julian, there's a xml1.stderr.exp64, but it looks like the XML output format has changed since it was written. Can you take a look? Thanks. N |
|
From: <sv...@va...> - 2005-06-30 12:50:55
|
Author: sewardj
Date: 2005-06-30 13:50:50 +0100 (Thu, 30 Jun 2005)
New Revision: 1237
Log:
Fix pointer-type mismatches.
Modified:
trunk/priv/guest-arm/gdefs.h
trunk/priv/guest-arm/toIR.c
trunk/test_main.c
Modified: trunk/priv/guest-arm/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-arm/gdefs.h 2005-06-30 12:26:18 UTC (rev 1236)
+++ trunk/priv/guest-arm/gdefs.h 2005-06-30 12:50:50 UTC (rev 1237)
@@ -51,7 +51,7 @@
Bool (*byte_accessible)(Addr64),
Bool (*resteerOkFn)(Addr64),
Bool host_bigendian,
- VexSubArch subarch_guest );
+ VexArchInfo* archinfo_guest );
=20
/* Used by the optimiser to specialise calls to helpers. */
extern
Modified: trunk/priv/guest-arm/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-arm/toIR.c 2005-06-30 12:26:18 UTC (rev 1236)
+++ trunk/priv/guest-arm/toIR.c 2005-06-30 12:50:50 UTC (rev 1237)
@@ -167,7 +167,7 @@
Bool (*byte_accessible)(Addr64),
Bool (*chase_into_ok)(Addr64),
Bool host_bigendian,
- VexSubArch subarch_guest )
+ VexArchInfo* archinfo_guest )
{
Long delta;
Int i, n_instrs, size, first_stmt_idx;
@@ -183,7 +183,7 @@
vassert(vex_control.guest_chase_thresh >=3D 0);
vassert(vex_control.guest_chase_thresh < vex_control.guest_max_insns)=
;
=20
- vassert(subarch_guest =3D=3D VexSubArchARM_v4);
+ vassert(archinfo_guest->subarch =3D=3D VexSubArchARM_v4);
=20
/* Start a new, empty extent. */
vge->n_used =3D 1;
Modified: trunk/test_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/test_main.c 2005-06-30 12:26:18 UTC (rev 1236)
+++ trunk/test_main.c 2005-06-30 12:50:50 UTC (rev 1237)
@@ -66,6 +66,7 @@
VexTranslateResult tres;
VexControl vcon;
VexGuestExtents vge;
+ VexArchInfo vai;
=20
if (argc !=3D 2) {
fprintf(stderr, "usage: vex file.org\n");
@@ -122,6 +123,9 @@
origbuf[i] =3D (UChar)u;
}
=20
+ LibVEX_default_VexArchInfo(&vai);
+ vai.subarch =3D VexSubArchX86_sse1;
+
for (i =3D 0; i < TEST_N_ITERS; i++)
tres
=3D LibVEX_Translate (=20
@@ -138,8 +142,8 @@
VexArchAMD64, VexSubArch_NONE,=20
#endif
#if 1 /* x86 -> x86 */
- VexArchX86, VexSubArchX86_sse1,=20
- VexArchX86, VexSubArchX86_sse1,=20
+ VexArchX86, &vai,=20
+ VexArchX86, &vai,=20
#endif
=20
origbuf, (Addr64)orig_addr, chase_into_not_ok,
|
|
From: <sv...@va...> - 2005-06-30 12:40:21
|
Author: sewardj Date: 2005-06-30 13:40:17 +0100 (Thu, 30 Jun 2005) New Revision: 4069 Log: Update expected output. Modified: trunk/memcheck/tests/xml1.stderr.exp Modified: trunk/memcheck/tests/xml1.stderr.exp =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- trunk/memcheck/tests/xml1.stderr.exp 2005-06-30 12:11:19 UTC (rev 406= 8) +++ trunk/memcheck/tests/xml1.stderr.exp 2005-06-30 12:40:17 UTC (rev 406= 9) @@ -369,10 +369,7 @@ <status>FINISHED</status> =20 <suppcounts> - <pair> - <count>16</count> - <name>Ugly strchr error in /lib/ld-2.3.3.so</name> - </pair> + <pair> <count>18</count> <name>Ugly strchr error in /lib/ld-2.3.3.so</= name> </pair> </suppcounts> =20 <error> |
|
From: <sv...@va...> - 2005-06-30 12:26:43
|
Author: sewardj
Date: 2005-06-30 13:26:18 +0100 (Thu, 30 Jun 2005)
New Revision: 1236
Log:
Comment wibble
Modified:
trunk/pub/libvex_basictypes.h
Modified: trunk/pub/libvex_basictypes.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/pub/libvex_basictypes.h 2005-06-30 12:21:04 UTC (rev 1235)
+++ trunk/pub/libvex_basictypes.h 2005-06-30 12:26:18 UTC (rev 1236)
@@ -118,7 +118,7 @@
=20
/* We need to know the host word size in order to write Ptr_to_ULong
and ULong_to_Ptr in a way that doesn't cause compilers to complain.
- These functions allow us to case pointers to and from 64-bit
+ These functions allow us to cast pointers to and from 64-bit
integers without complaints from compilers, regardless of the host
word size. */
=20
|
|
From: <sv...@va...> - 2005-06-30 12:21:14
|
Author: sewardj
Date: 2005-06-30 13:21:04 +0100 (Thu, 30 Jun 2005)
New Revision: 1235
Log:
Fill in guest_ppc32_state_requires_precise_mem_exns() properly, so Vex
has a bit more of a chance of optimising the IR.
Modified:
trunk/priv/guest-ppc32/ghelpers.c
Modified: trunk/priv/guest-ppc32/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/ghelpers.c 2005-06-30 12:08:48 UTC (rev 1234)
+++ trunk/priv/guest-ppc32/ghelpers.c 2005-06-30 12:21:04 UTC (rev 1235)
@@ -274,16 +274,46 @@
/* Figure out if any part of the guest state contained in minoff
.. maxoff requires precise memory exceptions. If in doubt return
True (but this is generates significantly slower code). =20
+
+ By default we enforce precise exns for guest R1 (stack pointer),
+ CIA (current insn address) and LR (link register). These are the
+ minimum needed to extract correct stack backtraces from ppc32
+ code. [[NB: not sure if keeping LR up to date is actually
+ necessary.]]
*/
Bool guest_ppc32_state_requires_precise_mem_exns ( Int minoff,=20
- Int maxoff)
+ Int maxoff )
{
- return True; // FIXME (also comment above)
+ Int lr_min =3D offsetof(VexGuestPPC32State, guest_LR);
+ Int lr_max =3D lr_min + 4 - 1;
+ Int r1_min =3D offsetof(VexGuestPPC32State, guest_GPR1);
+ Int r1_max =3D r1_min + 4 - 1;
+ Int cia_min =3D offsetof(VexGuestPPC32State, guest_CIA);
+ Int cia_max =3D cia_min + 4 - 1;
+
+ if (maxoff < lr_min || minoff > lr_max) {
+ /* no overlap with LR */
+ } else {
+ return True;
+ }
+
+ if (maxoff < r1_min || minoff > r1_max) {
+ /* no overlap with R1 */
+ } else {
+ return True;
+ }
+
+ if (maxoff < cia_min || minoff > cia_max) {
+ /* no overlap with CIA */
+ } else {
+ return True;
+ }
+
+ return False;
}
=20
=20
-
-#define ALWAYSDEFD(field) \
+#define ALWAYSDEFD(field) \
{ offsetof(VexGuestPPC32State, field), \
(sizeof ((VexGuestPPC32State*)0)->field) }
=20
|
|
From: <sv...@va...> - 2005-06-30 12:11:25
|
Author: sewardj
Date: 2005-06-30 13:11:19 +0100 (Thu, 30 Jun 2005)
New Revision: 4068
Log:
Restrict assertion to cache lines we know we need.
Modified:
trunk/coregrind/m_transtab.c
Modified: trunk/coregrind/m_transtab.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_transtab.c 2005-06-30 12:10:45 UTC (rev 4067)
+++ trunk/coregrind/m_transtab.c 2005-06-30 12:11:19 UTC (rev 4068)
@@ -333,8 +333,8 @@
Addr cls =3D VG_(cache_line_size_ppc32);
Addr addr;
=20
- /* Surely no real cache would have a different line size? */
- vg_assert(cls =3D=3D 16 || cls =3D=3D 32 || cls =3D=3D 64 || cls =3D=3D=
128);
+ /* Stay sane .. */
+ vg_assert(cls =3D=3D 32 || cls =3D=3D 128);
=20
startaddr &=3D ~(cls - 1);
for (addr =3D startaddr; addr < endaddr; addr +=3D cls)
|
|
From: <sv...@va...> - 2005-06-30 12:10:48
|
Author: sewardj
Date: 2005-06-30 13:10:45 +0100 (Thu, 30 Jun 2005)
New Revision: 4067
Log:
ppc32-linux: Vex implements dcbz correctly now. No need to mess with
the auxv to fool glibc into not using it.
Modified:
trunk/coregrind/m_main.c
Modified: trunk/coregrind/m_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_main.c 2005-06-30 11:50:11 UTC (rev 4066)
+++ trunk/coregrind/m_main.c 2005-06-30 12:10:45 UTC (rev 4067)
@@ -177,9 +177,6 @@
"PPC32 cache line size %u (type %u)\n",=20
(UInt)auxv->u.a_val, (UInt)auxv->a_type );
}
- /* HACK: Tell glibc we don't know what the line size is.
- This stops it using dcbz. */
- auxv->u.a_val =3D 0;
break;
# endif
=20
|
|
From: <sv...@va...> - 2005-06-30 12:08:50
|
Author: sewardj
Date: 2005-06-30 13:08:48 +0100 (Thu, 30 Jun 2005)
New Revision: 1234
Log:
Connect up the plumbing which allows the ppc32 front end to know the
cache line size it is supposed to simulate. Use this in
dis_cache_manage(). Finally reinstate 'dcbz'.
Modified:
trunk/priv/guest-ppc32/toIR.c
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-06-30 11:49:14 UTC (rev 1233)
+++ trunk/priv/guest-ppc32/toIR.c 2005-06-30 12:08:48 UTC (rev 1234)
@@ -282,6 +282,7 @@
static DisResult disInstr ( /*IN*/ Bool resteerOK,
/*IN*/ Bool (*resteerOkFn) ( Addr64 ),
/*IN*/ UInt delta,=20
+ /*IN*/ VexArchInfo* archinfo,
/*OUT*/ Int* size,
/*OUT*/ Addr64* whereNext );
=20
@@ -351,7 +352,7 @@
}
=20
dres =3D disInstr( resteerOK, chase_into_ok,=20
- delta, &size, &guest_next );
+ delta, archinfo_guest, &size, &guest_next );
=20
/* Print the resulting IR, if needed. */
if (vex_traceflags & VEX_TRACE_FE) {
@@ -3290,7 +3291,9 @@
/*
Cache Management Instructions
*/
-static Bool dis_cache_manage ( UInt theInstr, DisResult* whatNext )
+static Bool dis_cache_manage ( UInt theInstr,=20
+ DisResult* whatNext,
+ VexArchInfo* guest_archinfo )
{
/* X-Form */
UChar opc1 =3D toUChar((theInstr >> 26) & 0x3F); /* theInstr[26:31=
] */
@@ -3299,11 +3302,15 @@
UChar Rb_addr =3D toUChar((theInstr >> 11) & 0x1F); /* theInstr[11:15=
] */
UInt opc2 =3D (theInstr >> 1) & 0x3FF; /* theInstr[1:10]=
*/
UChar b0 =3D toUChar((theInstr >> 0) & 1); /* theInstr[0] =
*/
+ Int lineszB =3D guest_archinfo-> ppc32_cache_line_szB;
=20
if (opc1 !=3D 0x1F || b21to25 !=3D 0 || b0 !=3D 0) {
vex_printf("dis_cache_manage(PPC32)(opc1|b21to25|b0)\n");
return False;
}
+
+ /* stay sane .. */
+ vassert(lineszB =3D=3D 32 || lineszB =3D=3D 128);
=20
switch (opc2) {
case 0x2F6: // dcba (Data Cache Block Allocate, PPC32 p380)
@@ -3333,14 +3340,10 @@
case 0x3F6: { // dcbz (Data Cache Block Clear to Zero, PPC32 p387)
/* This needs to be fixed. We absolutely have to know the=20
correct cache line size to implement it right. */
- vassert(0);
- /* Clear all bytes in cache block at (rA|0) + rB.
- Since we don't know the cache line size, let's assume 256
- - safe, as no I1 cache would have a line size that large. */
+ /* Clear all bytes in cache block at (rA|0) + rB. */
IRTemp EA =3D newTemp(Ity_I32);
IRTemp addr =3D newTemp(Ity_I32);
IRExpr* irx_addr;
- UInt assumed_line_size =3D 32;
UInt i;
DIP("dcbz r%d,r%d\n", Ra_addr, Rb_addr);
assign( EA,
@@ -3352,11 +3355,11 @@
assign( addr,
binop( Iop_And32,
mkexpr(EA),
- mkU32( ~(assumed_line_size-1) )) );
+ mkU32( ~(lineszB-1) )) );
=20
- for (i =3D 0; i < (assumed_line_size / 4); i++) {
- irx_addr =3D binop( Iop_Add32, mkexpr(addr), mkU32(i*4) );
- storeBE( irx_addr, mkU32(0) );
+ for (i =3D 0; i < lineszB / 4; i++) {
+ irx_addr =3D binop( Iop_Add32, mkexpr(addr), mkU32(i*4) );
+ storeBE( irx_addr, mkU32(0) );
}
break;
}
@@ -3364,11 +3367,8 @@
case 0x3D6: {=20
// icbi (Instruction Cache Block Invalidate, PPC32 p431)
/* Invalidate all translations containing code from the cache
- block at (rA|0) + rB. Since we don't know what the cache
- line size is, let's assume 256 -- no real I1 cache would ever
- have a line size that large, so that's safe. */
+ block at (rA|0) + rB. */
IRTemp addr =3D newTemp(Ity_I32);
- UInt assumed_line_size =3D 256;
DIP("icbi r%d,r%d\n", Ra_addr, Rb_addr);
=20
assign( addr,
@@ -3381,9 +3381,9 @@
OFFB_TISTART,
binop( Iop_And32,=20
mkexpr(addr),=20
- mkU32( ~(assumed_line_size-1) ))) );
+ mkU32( ~(lineszB-1) ))) );
=20
- stmt( IRStmt_Put(OFFB_TILEN, mkU32(assumed_line_size) ) );
+ stmt( IRStmt_Put(OFFB_TILEN, mkU32(lineszB) ) );
=20
/* be paranoid ... */
stmt( IRStmt_MFence() );
@@ -5649,6 +5649,7 @@
static DisResult disInstr ( /*IN*/ Bool resteerOK,
/*IN*/ Bool (*resteerOkFn) ( Addr64 ),
/*IN*/ UInt delta,=20
+ /*IN*/ VexArchInfo* archinfo,
/*OUT*/ Int* size,
/*OUT*/ Addr64* whereNext )
{
@@ -5976,7 +5977,8 @@
case 0x2F6: case 0x056: case 0x036: // dcba, dcbf, dcbst
case 0x116: case 0x0F6: case 0x3F6: // dcbt, dcbtst, dcbz
case 0x3D6: // icbi
- if (dis_cache_manage( theInstr, &whatNext )) goto decode_succes=
s;
+ if (dis_cache_manage( theInstr, &whatNext, archinfo ))=20
+ goto decode_success;
goto decode_failure;
=20
/* External Control Instructions */
|
|
From: Josef W. <Jos...@gm...> - 2005-06-30 11:59:12
|
On Thursday 30 June 2005 05:54, Nicholas Nethercote wrote: > On Thu, 30 Jun 2005, Josef Weidendorfer wrote: > > Linking with valgrind at build time would make RPMs independent, i.e. a > > callgrind installation could exist without valgrind at all or with > > another valgrind release. Similar, currently I am forced to install into > > the same prefix, as valgrind has to find the tool. > > That's a good point. I was assuming that Callgrind would have to link > with the already installed Valgrind, but it can have its own copy in the > RPM. I thought the idea was to statically link the tool with valgrind at build time. What else would a RPM have to provide from core valgrind other than the built executable? In this sense, there is no own copy in the RPM. Am I missing something here? Configuration files are tool dependent (suppressions etc.), and help files in tool RPMs would be only for the tool. > This would give you more independence from the main Valgrind releases, > because you don't necessarily have to update Callgrind when a new Valgrind > is released It was always possible to install a second Valgrind release in some private path, and adjust the callgrind wrapper (which is in $PATH) to use this second version. > -- there's no danger of someone having a new Valgrind which > doesn't match an old Callgrind. Given that the tool API version checking is working correctly -- which AFAIK always was the case for stable releases -- this was prevented successfully. > (Although if the new Valgrind had a new > feature that you wanted, you'd have to rebuild and release a new Callgrind > to take advantage of it.) Exactly this is the main point: People want to have callgrind working with the newest valgrind: if I didn't provide a matching callgrind release a few days after a stable valgrind release, I got an increased number of mails asking for when the new callgrind release would happen. But releasing a new callgrind version is of course only needed if the major version of the tool API is increased in a new valgrind release. Unfortunately, this was almost always the case, and required me to release the updated tool. AFAIK there was only one time where the major version was kept - and it was indeed working without me doing anything. So the main problem with the version check was that the tool API simply was not stable at all. Regarding maintenance effort, my wrapper script simply could have checked the exact valgrind version requirement instead - without introducing tool API versions at all. > We also wouldn't have to worry about having a version number for the > core/tool interface any more, which is nice -- one fewer thing to get > wrong. Why? You do not need to do any check at runtime, but a check for the tool API version at build time is still better than relying an exact valgrind release numbers. The API still would exist - and major versions still make sense. > It would be more consistent to build every tool into a separate > executable, so that internal tools and external tools can be treated the > same way. I do not understand this. What is the difference between one executable for multiple tools and a separate for each? You could have one executable and hardlinks to this one, and run the tool depending on argv[0]. > It would make sense to have a minimal "stage1" which just looks for the > --tool option and invokes the appropriate executable. This could even > work for external tools if they were installed in the same place. The issue here is that you again introduce some kind of dependency of a "standalone" callgrind installation to an installed valgrind: the minimal stage1. So why such a minimal stage1 at all? Josef |
|
From: <sv...@va...> - 2005-06-30 11:50:25
|
Author: sewardj
Date: 2005-06-30 12:50:11 +0100 (Thu, 30 Jun 2005)
New Revision: 4066
Log:
Track Vex API change in r1233 (VexSubArch -> VexArchInfo).
Modified:
trunk/coregrind/m_translate.c
Modified: trunk/coregrind/m_translate.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/coregrind/m_translate.c 2005-06-30 04:41:56 UTC (rev 4065)
+++ trunk/coregrind/m_translate.c 2005-06-30 11:50:11 UTC (rev 4066)
@@ -33,6 +33,7 @@
#include "pub_core_debuginfo.h" // Needed for pub_core_aspacemgr :(
#include "pub_core_aspacemgr.h"
#include "pub_core_cpuid.h"
+#include "pub_core_machine.h" // For VG_(cache_line_size_ppc32)
#include "pub_core_libcbase.h"
#include "pub_core_libcassert.h"
#include "pub_core_libcprint.h"
@@ -49,12 +50,17 @@
/*--- Determining arch/subarch. ---*/
/*------------------------------------------------------------*/
=20
-// Returns the architecture and subarchitecture, or indicates
-// that this subarchitecture is unable to run Valgrind
-// Returns False to indicate we cannot proceed further.
-static Bool getArchAndSubArch( /*OUT*/VexArch* vex_arch,=20
- /*OUT*/VexSubArch* vex_subarch )
+// Returns the architecture and auxiliary information, or indicates
+// that this subarchitecture is unable to run Valgrind Returns False
+// to indicate we cannot proceed further.
+
+static Bool getArchAndArchInfo( /*OUT*/VexArch* vex_arch,=20
+ /*OUT*/VexArchInfo* vai )
{
+ // Whack default settings into vai, so that we only need to fill in
+ // any interesting bits.
+ LibVEX_default_VexArchInfo(vai);
+
#if defined(VGA_x86)
Bool have_sse0, have_sse1, have_sse2;
UInt eax, ebx, ecx, edx;
@@ -77,19 +83,19 @@
=20
if (have_sse2 && have_sse1 && have_sse0) {
*vex_arch =3D VexArchX86;
- *vex_subarch =3D VexSubArchX86_sse2;
+ vai->subarch =3D VexSubArchX86_sse2;
return True;
}
=20
if (have_sse1 && have_sse0) {
*vex_arch =3D VexArchX86;
- *vex_subarch =3D VexSubArchX86_sse1;
+ vai->subarch =3D VexSubArchX86_sse1;
return True;
}
=20
if (have_sse0) {
*vex_arch =3D VexArchX86;
- *vex_subarch =3D VexSubArchX86_sse0;
+ vai->subarch =3D VexSubArchX86_sse0;
return True;
}
=20
@@ -98,13 +104,14 @@
=20
#elif defined(VGA_amd64)
vg_assert(VG_(has_cpuid)());
- *vex_arch =3D VexArchAMD64;
- *vex_subarch =3D VexSubArch_NONE;
+ *vex_arch =3D VexArchAMD64;
+ vai->subarch =3D VexSubArch_NONE;
return True;
=20
#elif defined(VGA_ppc32)
*vex_arch =3D VexArchPPC32;
- *vex_subarch =3D VexSubArchPPC32_noAV;
+ vai->subarch =3D VexSubArchPPC32_noAV;
+ vai->ppc32_cache_line_szB =3D VG_(cache_line_size_ppc32);
return True;
=20
#else
@@ -434,16 +441,17 @@
Segment* seg;
VexGuestExtents vge;
=20
- /* Indicates what arch and subarch we are running on. */
- static VexArch vex_arch =3D VexArch_INVALID;
- static VexSubArch vex_subarch =3D VexSubArch_INVALID;
+ /* Indicates what arch we are running on, and other important info
+ (subarch variant, cache line size). */
+ static VexArchInfo vex_archinfo;
+ static VexArch vex_arch =3D VexArch_INVALID;
=20
/* Make sure Vex is initialised right. */
VexTranslateResult tres;
static Bool vex_init_done =3D False;
=20
if (!vex_init_done) {
- Bool ok =3D getArchAndSubArch( &vex_arch, &vex_subarch );
+ Bool ok =3D getArchAndArchInfo( &vex_arch, &vex_archinfo );
if (!ok) {
VG_(printf)("\n");
VG_(printf)("valgrind: fatal error: unsupported CPU.\n");
@@ -457,7 +465,7 @@
VG_(message)(Vg_DebugMsg,=20
"Host CPU: arch =3D %s, subarch =3D %s",
LibVEX_ppVexArch ( vex_arch ),
- LibVEX_ppVexSubArch( vex_subarch ) );
+ LibVEX_ppVexSubArch( vex_archinfo.subarch ) );
}
=20
LibVEX_Init ( &failure_exit, &log_bytes,=20
@@ -548,8 +556,8 @@
tl_assert2(VG_(tdict).tool_instrument,
"you forgot to set VgToolInterface function 'tool_instrume=
nt'");
tres =3D LibVEX_Translate (=20
- vex_arch, vex_subarch,
- vex_arch, vex_subarch,
+ vex_arch, &vex_archinfo,
+ vex_arch, &vex_archinfo,
(UChar*)ULong_to_Ptr(orig_addr),=20
(Addr64)orig_addr,=20
chase_into_ok,
|
|
From: <sv...@va...> - 2005-06-30 11:49:38
|
Author: sewardj
Date: 2005-06-30 12:49:14 +0100 (Thu, 30 Jun 2005)
New Revision: 1233
Log:
(API-visible change): generalise the VexSubArch idea. Everywhere
where a VexSubArch was previously passed around, a VexArchInfo is now
passed around. This is a struct which carries more details about any
given architecture and in particular gives a clean way to pass around
info about PPC cache line sizes, which is needed for guest-side PPC.
Modified:
trunk/priv/guest-amd64/gdefs.h
trunk/priv/guest-amd64/toIR.c
trunk/priv/guest-ppc32/gdefs.h
trunk/priv/guest-ppc32/toIR.c
trunk/priv/guest-x86/gdefs.h
trunk/priv/guest-x86/toIR.c
trunk/priv/host-amd64/hdefs.h
trunk/priv/host-amd64/isel.c
trunk/priv/host-ppc32/hdefs.h
trunk/priv/host-ppc32/isel.c
trunk/priv/host-x86/hdefs.h
trunk/priv/host-x86/isel.c
trunk/priv/main/vex_main.c
trunk/pub/libvex.h
Modified: trunk/priv/guest-amd64/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/gdefs.h 2005-06-29 19:05:08 UTC (rev 1232)
+++ trunk/priv/guest-amd64/gdefs.h 2005-06-30 11:49:14 UTC (rev 1233)
@@ -50,7 +50,7 @@
Bool (*byte_accessible)(Addr64),
Bool (*resteerOkFn)(Addr64),
Bool host_bigendian,
- VexSubArch subarch_guest );
+ VexArchInfo* archinfo_guest );
=20
/* Used by the optimiser to specialise calls to helpers. */
extern
Modified: trunk/priv/guest-amd64/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-amd64/toIR.c 2005-06-29 19:05:08 UTC (rev 1232)
+++ trunk/priv/guest-amd64/toIR.c 2005-06-30 11:49:14 UTC (rev 1233)
@@ -398,12 +398,12 @@
resteer into, returns False. */
=20
static=20
-DisResult disInstr ( /*IN*/ Bool resteerOK,
- /*IN*/ Bool (*resteerOkFn) ( Addr64 ),
- /*IN*/ ULong delta,=20
- /*IN*/ VexSubArch subarch,
- /*OUT*/ Long* size,
- /*OUT*/ Addr64* whereNext );
+DisResult disInstr ( /*IN*/ Bool resteerOK,
+ /*IN*/ Bool (*resteerOkFn) ( Addr64 ),
+ /*IN*/ ULong delta,=20
+ /*IN*/ VexArchInfo* archinfo,
+ /*OUT*/ Long* size,
+ /*OUT*/ Addr64* whereNext );
=20
=20
/* This is the main (only, in fact) entry point for this module. */
@@ -417,7 +417,7 @@
Bool (*byte_accessible)(Addr64),
Bool (*chase_into_ok)(Addr64),
Bool host_bigendian,
- VexSubArch subarch_guest )
+ VexArchInfo* archinfo_guest )
{
Long delta, size;
Int i, n_instrs, first_stmt_idx;
@@ -434,7 +434,7 @@
vassert(vex_control.guest_chase_thresh >=3D 0);
vassert(vex_control.guest_chase_thresh < vex_control.guest_max_insns)=
;
=20
- vassert(subarch_guest =3D=3D VexSubArch_NONE);
+ vassert(archinfo_guest->subarch =3D=3D VexSubArch_NONE);
=20
/* Start a new, empty extent. */
vge->n_used =3D 1;
@@ -491,7 +491,7 @@
guest_rip_next_assumed =3D 0;
guest_rip_next_mustcheck =3D False;
dres =3D disInstr( resteerOK, chase_into_ok,=20
- delta, subarch_guest, &size, &guest_next );
+ delta, archinfo_guest, &size, &guest_next );
insn_verbose =3D False;
=20
/* stay sane ... */
@@ -7927,12 +7927,12 @@
is False, disInstr may not return Dis_Resteer. */
=20
static=20
-DisResult disInstr ( /*IN*/ Bool resteerOK,
- /*IN*/ Bool (*resteerOkFn) ( Addr64 ),
- /*IN*/ ULong delta,=20
- /*IN*/ VexSubArch subarch,
- /*OUT*/ Long* size,
- /*OUT*/ Addr64* whereNext )
+DisResult disInstr ( /*IN*/ Bool resteerOK,
+ /*IN*/ Bool (*resteerOkFn) ( Addr64 ),
+ /*IN*/ ULong delta,=20
+ /*IN*/ VexArchInfo* archinfo,
+ /*OUT*/ Long* size,
+ /*OUT*/ Addr64* whereNext )
{
IRType ty;
IRTemp addr, t0, t1, t2, t3, t4, t5, t6;
@@ -13115,7 +13115,7 @@
HChar* fName =3D NULL;
void* fAddr =3D NULL;
if (haveF2orF3(pfx)) goto decode_failure;
- switch (subarch) {
+ switch (archinfo->subarch) {
case VexSubArch_NONE:
fName =3D "amd64g_dirtyhelper_CPUID";
fAddr =3D &amd64g_dirtyhelper_CPUID;=20
Modified: trunk/priv/guest-ppc32/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/gdefs.h 2005-06-29 19:05:08 UTC (rev 1232)
+++ trunk/priv/guest-ppc32/gdefs.h 2005-06-30 11:49:14 UTC (rev 1233)
@@ -69,7 +69,7 @@
Bool (*byte_accessible)(Addr64),
Bool (*resteerOkFn)(Addr64),
Bool host_bigendian,
- VexSubArch subarch_guest );
+ VexArchInfo* archinfo_guest );
=20
/* Used by the optimiser to specialise calls to helpers. */
extern
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-06-29 19:05:08 UTC (rev 1232)
+++ trunk/priv/guest-ppc32/toIR.c 2005-06-30 11:49:14 UTC (rev 1233)
@@ -298,7 +298,7 @@
Bool (*byte_accessible)(Addr64),
Bool (*chase_into_ok)(Addr64),
Bool host_bigendian,
- VexSubArch subarch_guest )
+ VexArchInfo* archinfo_guest )
{
UInt delta;
Int i, n_instrs, size, first_stmt_idx;
@@ -314,8 +314,8 @@
vassert(vex_control.guest_chase_thresh >=3D 0);
vassert(vex_control.guest_chase_thresh < vex_control.guest_max_insns)=
;
=20
- vassert(subarch_guest =3D=3D VexSubArchPPC32_noAV
- || subarch_guest =3D=3D VexSubArchPPC32_AV);
+ vassert(archinfo_guest->subarch =3D=3D VexSubArchPPC32_noAV
+ || archinfo_guest->subarch =3D=3D VexSubArchPPC32_AV);
=20
/* Start a new, empty extent. */
vge->n_used =3D 1;
Modified: trunk/priv/guest-x86/gdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-x86/gdefs.h 2005-06-29 19:05:08 UTC (rev 1232)
+++ trunk/priv/guest-x86/gdefs.h 2005-06-30 11:49:14 UTC (rev 1233)
@@ -50,7 +50,7 @@
Bool (*byte_accessible)(Addr64),
Bool (*resteerOkFn)(Addr64),
Bool host_bigendian,
- VexSubArch subarch_guest );
+ VexArchInfo* archinfo_guest );
=20
/* Used by the optimiser to specialise calls to helpers. */
extern
Modified: trunk/priv/guest-x86/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-x86/toIR.c 2005-06-29 19:05:08 UTC (rev 1232)
+++ trunk/priv/guest-x86/toIR.c 2005-06-30 11:49:14 UTC (rev 1233)
@@ -233,12 +233,12 @@
resteer into, returns False. */
=20
static=20
-DisResult disInstr ( /*IN*/ Bool resteerOK,
- /*IN*/ Bool (*resteerOkFn) ( Addr64 ),
- /*IN*/ UInt delta,=20
- /*IN*/ VexSubArch subarch,
- /*OUT*/ Int* size,
- /*OUT*/ Addr64* whereNext );
+DisResult disInstr ( /*IN*/ Bool resteerOK,
+ /*IN*/ Bool (*resteerOkFn) ( Addr64 ),
+ /*IN*/ UInt delta,=20
+ /*IN*/ VexArchInfo* archinfo,
+ /*OUT*/ Int* size,
+ /*OUT*/ Addr64* whereNext );
=20
=20
/* This is the main (only, in fact) entry point for this module. */
@@ -252,7 +252,7 @@
Bool (*byte_accessible)(Addr64),
Bool (*chase_into_ok)(Addr64),
Bool host_bigendian,
- VexSubArch subarch_guest )
+ VexArchInfo* archinfo_guest )
{
UInt delta;
Int i, n_instrs, size, first_stmt_idx;
@@ -269,9 +269,9 @@
vassert(vex_control.guest_chase_thresh >=3D 0);
vassert(vex_control.guest_chase_thresh < vex_control.guest_max_insns)=
;
=20
- vassert(subarch_guest =3D=3D VexSubArchX86_sse0
- || subarch_guest =3D=3D VexSubArchX86_sse1
- || subarch_guest =3D=3D VexSubArchX86_sse2);
+ vassert(archinfo_guest->subarch =3D=3D VexSubArchX86_sse0
+ || archinfo_guest->subarch =3D=3D VexSubArchX86_sse1
+ || archinfo_guest->subarch =3D=3D VexSubArchX86_sse2);
=20
vassert((guest_eip_start >> 32) =3D=3D 0);
=20
@@ -328,7 +328,7 @@
needs to be annulled. */
size =3D 0; /* just in case disInstr doesn't set it */
dres =3D disInstr( resteerOK, chase_into_ok,=20
- delta, subarch_guest, &size, &guest_next );
+ delta, archinfo_guest, &size, &guest_next );
insn_verbose =3D False;
=20
/* stay sane ... */
@@ -6997,12 +6997,12 @@
is False, disInstr may not return Dis_Resteer. */
=20
static=20
-DisResult disInstr ( /*IN*/ Bool resteerOK,
- /*IN*/ Bool (*resteerOkFn) ( Addr64 ),
- /*IN*/ UInt delta,=20
- /*IN*/ VexSubArch subarch,
- /*OUT*/ Int* size,
- /*OUT*/ Addr64* whereNext )
+DisResult disInstr ( /*IN*/ Bool resteerOK,
+ /*IN*/ Bool (*resteerOkFn) ( Addr64 ),
+ /*IN*/ UInt delta,=20
+ /*IN*/ VexArchInfo* archinfo,
+ /*OUT*/ Int* size,
+ /*OUT*/ Addr64* whereNext )
{
IRType ty;
IRTemp addr, t0, t1, t2, t3, t4, t5, t6;
@@ -7222,7 +7222,7 @@
=20
/* Skip parts of the decoder which don't apply given the stated
guest subarchitecture. */
- if (subarch =3D=3D VexSubArchX86_sse0)
+ if (archinfo->subarch =3D=3D VexSubArchX86_sse0)
goto after_sse_decoders;
=20
/* Otherwise we must be doing sse1 or sse2, so we can at least try
@@ -8242,7 +8242,8 @@
=20
/* Skip parts of the decoder which don't apply given the stated
guest subarchitecture. */
- if (subarch =3D=3D VexSubArchX86_sse0 || subarch =3D=3D VexSubArchX86=
_sse1)
+ if (archinfo->subarch =3D=3D VexSubArchX86_sse0=20
+ || archinfo->subarch =3D=3D VexSubArchX86_sse1)
goto after_sse_decoders;
=20
insn =3D (UChar*)&guest_code[delta];
@@ -11766,7 +11767,7 @@
IRDirty* d =3D NULL;
HChar* fName =3D NULL;
void* fAddr =3D NULL;
- switch (subarch) {
+ switch (archinfo->subarch) {
case VexSubArchX86_sse0:
fName =3D "x86g_dirtyhelper_CPUID_sse0";
fAddr =3D &x86g_dirtyhelper_CPUID_sse0;=20
Modified: trunk/priv/host-amd64/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/hdefs.h 2005-06-29 19:05:08 UTC (rev 1232)
+++ trunk/priv/host-amd64/hdefs.h 2005-06-30 11:49:14 UTC (rev 1233)
@@ -708,7 +708,7 @@
extern AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offset );
extern AMD64Instr* genReload_AMD64 ( HReg rreg, Int offset );
extern void getAllocableRegs_AMD64 ( Int*, HReg** );
-extern HInstrArray* iselBB_AMD64 ( IRBB*, VexSubArch );
+extern HInstrArray* iselBB_AMD64 ( IRBB*, VexArchInfo* );
=20
#endif /* ndef __LIBVEX_HOST_AMD64_HDEFS_H */
=20
Modified: trunk/priv/host-amd64/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-amd64/isel.c 2005-06-29 19:05:08 UTC (rev 1232)
+++ trunk/priv/host-amd64/isel.c 2005-06-30 11:49:14 UTC (rev 1233)
@@ -3750,11 +3750,12 @@
=20
/* Translate an entire BB to amd64 code. */
=20
-HInstrArray* iselBB_AMD64 ( IRBB* bb, VexSubArch subarch_host )
+HInstrArray* iselBB_AMD64 ( IRBB* bb, VexArchInfo* archinfo_host )
{
- Int i, j;
- HReg hreg, hregHI;
- ISelEnv* env;
+ Int i, j;
+ HReg hreg, hregHI;
+ ISelEnv* env;
+ VexSubArch subarch_host =3D archinfo_host->subarch;
=20
/* sanity ... */
vassert(subarch_host =3D=3D VexSubArch_NONE);
Modified: trunk/priv/host-ppc32/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.h 2005-06-29 19:05:08 UTC (rev 1232)
+++ trunk/priv/host-ppc32/hdefs.h 2005-06-30 11:49:14 UTC (rev 1233)
@@ -710,7 +710,7 @@
extern PPC32Instr* genSpill_PPC32 ( HReg rreg, UShort offsetB )=
;
extern PPC32Instr* genReload_PPC32 ( HReg rreg, UShort offsetB )=
;
extern void getAllocableRegs_PPC32 ( Int*, HReg** );
-extern HInstrArray* iselBB_PPC32 ( IRBB*, VexSubArch );
+extern HInstrArray* iselBB_PPC32 ( IRBB*, VexArchInfo* );
=20
#endif /* ndef __LIBVEX_HOST_PPC32_HDEFS_H */
=20
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-06-29 19:05:08 UTC (rev 1232)
+++ trunk/priv/host-ppc32/isel.c 2005-06-30 11:49:14 UTC (rev 1233)
@@ -3529,11 +3529,12 @@
=20
/* Translate an entire BB to ppc32 code. */
=20
-HInstrArray* iselBB_PPC32 ( IRBB* bb, VexSubArch subarch_host )
+HInstrArray* iselBB_PPC32 ( IRBB* bb, VexArchInfo* archinfo_host )
{
- Int i, j;
- HReg hreg, hregHI;
- ISelEnv* env;
+ Int i, j;
+ HReg hreg, hregHI;
+ ISelEnv* env;
+ VexSubArch subarch_host =3D archinfo_host->subarch;
=20
/* sanity ... */
vassert(subarch_host =3D=3D VexSubArchPPC32_noAV
Modified: trunk/priv/host-x86/hdefs.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-x86/hdefs.h 2005-06-29 19:05:08 UTC (rev 1232)
+++ trunk/priv/host-x86/hdefs.h 2005-06-30 11:49:14 UTC (rev 1233)
@@ -653,7 +653,7 @@
extern X86Instr* genSpill_X86 ( HReg rreg, Int offset );
extern X86Instr* genReload_X86 ( HReg rreg, Int offset );
extern void getAllocableRegs_X86 ( Int*, HReg** );
-extern HInstrArray* iselBB_X86 ( IRBB*, VexSubArch );
+extern HInstrArray* iselBB_X86 ( IRBB*, VexArchInfo* );
=20
#endif /* ndef __LIBVEX_HOST_X86_HDEFS_H */
=20
Modified: trunk/priv/host-x86/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-x86/isel.c 2005-06-29 19:05:08 UTC (rev 1232)
+++ trunk/priv/host-x86/isel.c 2005-06-30 11:49:14 UTC (rev 1233)
@@ -3550,11 +3550,12 @@
=20
/* Translate an entire BB to x86 code. */
=20
-HInstrArray* iselBB_X86 ( IRBB* bb, VexSubArch subarch_host )
+HInstrArray* iselBB_X86 ( IRBB* bb, VexArchInfo* archinfo_host )
{
- Int i, j;
- HReg hreg, hregHI;
- ISelEnv* env;
+ Int i, j;
+ HReg hreg, hregHI;
+ ISelEnv* env;
+ VexSubArch subarch_host =3D archinfo_host->subarch;
=20
/* sanity ... */
vassert(subarch_host =3D=3D VexSubArchX86_sse0
Modified: trunk/priv/main/vex_main.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/main/vex_main.c 2005-06-29 19:05:08 UTC (rev 1232)
+++ trunk/priv/main/vex_main.c 2005-06-30 11:49:14 UTC (rev 1233)
@@ -168,10 +168,10 @@
=20
VexTranslateResult LibVEX_Translate (
/* The instruction sets we are translating from and to. */
- VexArch arch_guest,
- VexSubArch subarch_guest,
- VexArch arch_host,
- VexSubArch subarch_host,
+ VexArch arch_guest,
+ VexArchInfo* archinfo_guest,
+ VexArch arch_host,
+ VexArchInfo* archinfo_host,
/* IN: the block to translate, and its guest address. */
UChar* guest_bytes,
Addr64 guest_bytes_addr,
@@ -207,12 +207,12 @@
HInstr* (*genReload) ( HReg, Int );
void (*ppInstr) ( HInstr* );
void (*ppReg) ( HReg );
- HInstrArray* (*iselBB) ( IRBB*, VexSubArch );
+ HInstrArray* (*iselBB) ( IRBB*, VexArchInfo* );
IRBB* (*bbToIR) ( UChar*, Addr64,=20
VexGuestExtents*,=20
Bool(*)(Addr64),=20
Bool(*)(Addr64),=20
- Bool, VexSubArch );
+ Bool, VexArchInfo* );
Int (*emit) ( UChar*, Int, HInstr* );
IRExpr* (*specHelper) ( HChar*, IRExpr** );
Bool (*preciseMemExnsFn) ( Int, Int );
@@ -270,9 +270,9 @@
emit =3D (Int(*)(UChar*,Int,HInstr*)) emit_X86Instr;
host_is_bigendian =3D False;
host_word_type =3D Ity_I32;
- vassert(subarch_host =3D=3D VexSubArchX86_sse0
- || subarch_host =3D=3D VexSubArchX86_sse1
- || subarch_host =3D=3D VexSubArchX86_sse2);
+ vassert(archinfo_host->subarch =3D=3D VexSubArchX86_sse0
+ || archinfo_host->subarch =3D=3D VexSubArchX86_sse1
+ || archinfo_host->subarch =3D=3D VexSubArchX86_sse2);
break;
=20
case VexArchAMD64:
@@ -289,7 +289,7 @@
emit =3D (Int(*)(UChar*,Int,HInstr*)) emit_AMD64Instr;
host_is_bigendian =3D False;
host_word_type =3D Ity_I64;
- vassert(subarch_host =3D=3D VexSubArch_NONE);
+ vassert(archinfo_host->subarch =3D=3D VexSubArch_NONE);
break;
=20
case VexArchPPC32:
@@ -306,8 +306,8 @@
emit =3D (Int(*)(UChar*,Int,HInstr*)) emit_PPC32Instr;
host_is_bigendian =3D True;
host_word_type =3D Ity_I32;
- vassert(subarch_guest =3D=3D VexSubArchPPC32_noAV
- || subarch_guest =3D=3D VexSubArchPPC32_AV);
+ vassert(archinfo_guest->subarch =3D=3D VexSubArchPPC32_noAV
+ || archinfo_guest->subarch =3D=3D VexSubArchPPC32_AV);
break;
=20
default:
@@ -324,9 +324,9 @@
guest_sizeB =3D sizeof(VexGuestX86State);
guest_word_type =3D Ity_I32;
guest_layout =3D &x86guest_layout;
- vassert(subarch_guest =3D=3D VexSubArchX86_sse0
- || subarch_guest =3D=3D VexSubArchX86_sse1
- || subarch_guest =3D=3D VexSubArchX86_sse2);
+ vassert(archinfo_guest->subarch =3D=3D VexSubArchX86_sse0
+ || archinfo_guest->subarch =3D=3D VexSubArchX86_sse1
+ || archinfo_guest->subarch =3D=3D VexSubArchX86_sse2);
break;
=20
case VexArchAMD64:
@@ -336,7 +336,7 @@
guest_sizeB =3D sizeof(VexGuestAMD64State);
guest_word_type =3D Ity_I64;
guest_layout =3D &amd64guest_layout;
- vassert(subarch_guest =3D=3D VexSubArch_NONE);
+ vassert(archinfo_guest->subarch =3D=3D VexSubArch_NONE);
break;
=20
case VexArchARM:
@@ -346,7 +346,7 @@
guest_sizeB =3D sizeof(VexGuestARMState);
guest_word_type =3D Ity_I32;
guest_layout =3D &armGuest_layout;
- vassert(subarch_guest =3D=3D VexSubArchARM_v4);
+ vassert(archinfo_guest->subarch =3D=3D VexSubArchARM_v4);
break;
=20
case VexArchPPC32:
@@ -356,8 +356,8 @@
guest_sizeB =3D sizeof(VexGuestPPC32State);
guest_word_type =3D Ity_I32;
guest_layout =3D &ppc32Guest_layout;
- vassert(subarch_guest =3D=3D VexSubArchPPC32_noAV
- || subarch_guest =3D=3D VexSubArchPPC32_AV);
+ vassert(archinfo_guest->subarch =3D=3D VexSubArchPPC32_noAV
+ || archinfo_guest->subarch =3D=3D VexSubArchPPC32_AV);
break;
=20
default:
@@ -369,7 +369,7 @@
/* doesn't necessarily have to be true, but if it isn't it means
we are simulating one flavour of an architecture a different
flavour of the same architecture, which is pretty strange. */
- vassert(subarch_guest =3D=3D subarch_host);
+ vassert(archinfo_guest->subarch =3D=3D archinfo_host->subarch);
}
=20
if (vex_traceflags & VEX_TRACE_FE)
@@ -383,7 +383,7 @@
byte_accessible,
chase_into_ok,
host_is_bigendian,
- subarch_guest );
+ archinfo_guest );
=20
if (irbb =3D=3D NULL) {
/* Access failure. */
@@ -489,7 +489,7 @@
" Instruction selection "
"------------------------\n");
=20
- vcode =3D iselBB ( irbb, subarch_host );
+ vcode =3D iselBB ( irbb, archinfo_host );
=20
if (vex_traceflags & VEX_TRACE_VCODE)
vex_printf("\n");
@@ -592,7 +592,7 @@
}
}
=20
-/* --------- Arch/Subarch names. --------- */
+/* --------- Arch/Subarch stuff. --------- */
=20
const HChar* LibVEX_ppVexArch ( VexArch arch )
{
@@ -621,6 +621,14 @@
}
}
=20
+/* Write default settings info *vai. */
+void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai )
+{
+ vai->subarch =3D VexSubArch_INVALID;
+ vai->ppc32_cache_line_szB =3D 0;
+}
+
+
/*---------------------------------------------------------------*/
/*--- end main/vex_main.c ---*/
/*---------------------------------------------------------------*/
Modified: trunk/pub/libvex.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/pub/libvex.h 2005-06-29 19:05:08 UTC (rev 1232)
+++ trunk/pub/libvex.h 2005-06-30 11:49:14 UTC (rev 1233)
@@ -46,7 +46,7 @@
/*---------------------------------------------------------------*/
=20
/*-------------------------------------------------------*/
-/*--- Architectures and architecture variants ---*/
+/*--- Architectures, variants, and other arch info ---*/
/*-------------------------------------------------------*/
=20
typedef=20
@@ -78,6 +78,24 @@
extern const HChar* LibVEX_ppVexSubArch ( VexSubArch );
=20
=20
+/* This struct is a bit of a hack, but is needed to carry misc
+ important bits of info about an arch. Fields which are optional or
+ ignored on some arch should be set to zero. */
+
+typedef
+ struct {
+ /* This is the only mandatory field. */
+ VexSubArch subarch;
+ /* PPC32 only: size of cache line */
+ Int ppc32_cache_line_szB;
+ }
+ VexArchInfo;
+
+/* Write default settings info *vai. */
+extern=20
+void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai );
+
+
/*-------------------------------------------------------*/
/*--- Control of Vex's optimiser (iropt). ---*/
/*-------------------------------------------------------*/
@@ -247,10 +265,10 @@
extern=20
VexTranslateResult LibVEX_Translate (
/* The instruction sets we are translating from and to. */
- VexArch arch_guest,
- VexSubArch subarch_guest,
- VexArch arch_host,
- VexSubArch subarch_host,
+ VexArch arch_guest,
+ VexArchInfo* archinfo_guest,
+ VexArch arch_host,
+ VexArchInfo* archinfo_host,
/* IN: the block to translate, and its guest address. */
UChar* guest_bytes,
Addr64 guest_bytes_addr,
|
|
From: <sv...@va...> - 2005-06-30 04:42:27
|
Author: njn
Date: 2005-06-30 05:41:56 +0100 (Thu, 30 Jun 2005)
New Revision: 4065
Log:
Move some more Corecheck tests into none/tests.
Added:
trunk/none/tests/res_search.c
trunk/none/tests/res_search.stderr.exp
trunk/none/tests/res_search.stdout.exp
trunk/none/tests/res_search.vgtest
trunk/none/tests/threadederrno.c
trunk/none/tests/threadederrno.stderr.exp
trunk/none/tests/threadederrno.stdout.exp
trunk/none/tests/threadederrno.vgtest
Removed:
trunk/corecheck/tests/res_search.c
trunk/corecheck/tests/res_search.stderr.exp
trunk/corecheck/tests/res_search.stdout.exp
trunk/corecheck/tests/res_search.vgtest
trunk/corecheck/tests/threadederrno.c
trunk/corecheck/tests/threadederrno.stderr.exp
trunk/corecheck/tests/threadederrno.stdout.exp
trunk/corecheck/tests/threadederrno.vgtest
Modified:
trunk/corecheck/tests/Makefile.am
trunk/none/tests/Makefile.am
Modified: trunk/corecheck/tests/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/corecheck/tests/Makefile.am 2005-06-30 04:09:11 UTC (rev 4064)
+++ trunk/corecheck/tests/Makefile.am 2005-06-30 04:41:56 UTC (rev 4065)
@@ -9,16 +9,10 @@
EXTRA_DIST =3D $(noinst_SCRIPTS) \
erringfds.stderr.exp erringfds.stdout.exp erringfds.vgtest \
sigkill.stderr.exp sigkill.stderr.exp2 sigkill.vgtest \
- stack_changes.vgtest \
- res_search.stderr.exp res_search.stdout.exp res_search.vgtest \
- threadederrno.stderr.exp threadederrno.stdout.exp \
- threadederrno.vgtest
+ stack_changes.vgtest
=20
check_PROGRAMS =3D \
- erringfds \
- sigkill res_search \
- threadederrno \
- stack_changes
+ erringfds sigkill stack_changes
=20
AM_CFLAGS =3D $(WERROR) -Winline -Wall -Wshadow -g -O0
AM_CPPFLAGS =3D -I$(top_srcdir)/include
@@ -26,10 +20,5 @@
=20
sigkill_SOURCES =3D sigkill.c
=20
-res_search_SOURCES =3D res_search.c
-res_search_LDADD =3D -lresolv -lpthread
-threadederrno_SOURCES =3D threadederrno.c
-threadederrno_LDADD =3D -lpthread
-
# Stack tests
stack_changes_SOURCES =3D stack_changes.c
Deleted: trunk/corecheck/tests/res_search.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/corecheck/tests/res_search.c 2005-06-30 04:09:11 UTC (rev 4064)
+++ trunk/corecheck/tests/res_search.c 2005-06-30 04:41:56 UTC (rev 4065)
@@ -1,66 +0,0 @@
-#include <stdio.h>
-#include <string.h>
-#include <netinet/in.h>
-#include <arpa/nameser.h>
-#include <resolv.h>
-#include <pthread.h>
-
-void* fn(void* arg)
-{
- char* dn =3D (char*)arg;
-
- unsigned char buff[8000];
-
- if(-1 =3D=3D res_search(dn, 1, 1, buff, 8000))
- {
- printf("Error: res_search()\n");
- }
- else
- {
- printf("Success!\n");
- }
- return 0;
-}
-
-int main(int argc, char** argv)
-{
- pthread_t pid;
- if(2 !=3D argc)
- {
- printf("Usage: %s <domain>\n", argv[0]);
- return 1;
- }
-
- _res.options |=3D RES_DEBUG;
- if(0 !=3D res_init())
- {
- printf("Error: res_init()\n");
- return(1);
- }
-#if 1
- /* Test it in a different thread -- the failure case */
- if(0 !=3D pthread_create(&pid, 0, fn, (void*)argv[1]))
- {
- printf("Failed to create thread.\n");
- return 1;
- }
-
- pthread_join(pid, 0);
-#else
- {
- unsigned char buff[8000];
-
- if(-1 =3D=3D res_search(argv[1], 1, 1, buff, 8000))
- {
- printf("Error: res_search()\n");
- }
- else
- {
- printf("Success!\n");
- }
- }
-#endif
- return 0;
-}
-
-
Deleted: trunk/corecheck/tests/res_search.stderr.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Deleted: trunk/corecheck/tests/res_search.stdout.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/corecheck/tests/res_search.stdout.exp 2005-06-30 04:09:11 UTC (=
rev 4064)
+++ trunk/corecheck/tests/res_search.stdout.exp 2005-06-30 04:41:56 UTC (=
rev 4065)
@@ -1 +0,0 @@
-Success!
Deleted: trunk/corecheck/tests/res_search.vgtest
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/corecheck/tests/res_search.vgtest 2005-06-30 04:09:11 UTC (rev =
4064)
+++ trunk/corecheck/tests/res_search.vgtest 2005-06-30 04:41:56 UTC (rev =
4065)
@@ -1,3 +0,0 @@
-prog: res_search
-args: www.yahoo.com
-vgopts: -q
Deleted: trunk/corecheck/tests/threadederrno.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/corecheck/tests/threadederrno.c 2005-06-30 04:09:11 UTC (rev 40=
64)
+++ trunk/corecheck/tests/threadederrno.c 2005-06-30 04:41:56 UTC (rev 40=
65)
@@ -1,35 +0,0 @@
-
-#include <pthread.h>
-#include <stdio.h>
-#include <errno.h>
-#include <string.h>
-
-
-void* thr2 ( void* v )
-{
- FILE* f =3D fopen("bogus2", "r");
- printf("f =3D %p, errno =3D %d (%s)\n", f, errno, strerror(errno));
- return NULL;
-}
-
-void* thr3 ( void* v )
-{
- FILE* f =3D fopen("bogus3", "r");
- printf("f =3D %p, errno =3D %d (%s)\n", f, errno, strerror(errno));
- return NULL;
-}
-
-
-int main ( void )
-{
- FILE* f;
- pthread_t tid2, tid3;
- pthread_create(&tid2, NULL, &thr2, NULL);
- pthread_create(&tid3, NULL, &thr3, NULL);
- f =3D fopen("bogus", "r");
- printf("f =3D %p, errno =3D %d (%s)\n", f, errno, strerror(errno));
- pthread_join(tid2, NULL);
- pthread_join(tid3, NULL);
- return 0;
-}
-
Deleted: trunk/corecheck/tests/threadederrno.stderr.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Deleted: trunk/corecheck/tests/threadederrno.stdout.exp
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/corecheck/tests/threadederrno.stdout.exp 2005-06-30 04:09:11 UT=
C (rev 4064)
+++ trunk/corecheck/tests/threadederrno.stdout.exp 2005-06-30 04:41:56 UT=
C (rev 4065)
@@ -1,3 +0,0 @@
-f =3D (nil), errno =3D 2 (No such file or directory)
-f =3D (nil), errno =3D 2 (No such file or directory)
-f =3D (nil), errno =3D 2 (No such file or directory)
Deleted: trunk/corecheck/tests/threadederrno.vgtest
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/corecheck/tests/threadederrno.vgtest 2005-06-30 04:09:11 UTC (r=
ev 4064)
+++ trunk/corecheck/tests/threadederrno.vgtest 2005-06-30 04:41:56 UTC (r=
ev 4065)
@@ -1,2 +0,0 @@
-prog: threadederrno
-vgopts: -q
Modified: trunk/none/tests/Makefile.am
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/none/tests/Makefile.am 2005-06-30 04:09:11 UTC (rev 4064)
+++ trunk/none/tests/Makefile.am 2005-06-30 04:41:56 UTC (rev 4065)
@@ -76,6 +76,7 @@
rcrl.stderr.exp rcrl.stdout.exp rcrl.vgtest \
readline1.stderr.exp readline1.stdout.exp \
readline1.vgtest \
+ res_search.stderr.exp res_search.stdout.exp res_search.vgtest \
resolv.stderr.exp resolv.stdout.exp resolv.vgtest \
rlimit_nofile.stderr.exp rlimit_nofile.stdout.exp rlimit_nofile.vgtest =
\
selfrun.stderr.exp selfrun.stdout.exp selfrun.vgtest \
@@ -93,6 +94,8 @@
system.stderr.exp system.vgtest \
thread-exits.stderr.exp thread-exits.stdout.exp thread-exits.vgtest \
threaded-fork.stderr.exp threaded-fork.stdout.exp threaded-fork.vgtest =
\
+ threadederrno.stderr.exp threadederrno.stdout.exp \
+ threadederrno.vgtest \
tls.stderr.exp tls.stdout.exp \
vgprintf.stderr.exp vgprintf.stdout.exp vgprintf.vgtest \
yield.stderr.exp yield.stdout.exp yield.vgtest
@@ -110,10 +113,11 @@
pth_atfork1 pth_blockedsig pth_cancel1 pth_cancel2 pth_cvsimple \
pth_empty pth_exit pth_exit2 pth_mutexspeed pth_once pth_rwlock \
pth_stackalign \
- rcrl readline1 resolv rlimit_nofile selfrun sem semlimit sha1_test \
+ rcrl readline1 res_search resolv \
+ rlimit_nofile selfrun sem semlimit sha1_test \
shortpush shorts stackgrowth sigstackgrowth smc1 susphello \
syscall-restart1 syscall-restart2 system \
- thread-exits threaded-fork \
+ thread-exits threaded-fork threadederrno \
tls tls.so tls2.so yield vgprintf \
coolo_sigaction gxx304
=20
@@ -185,6 +189,8 @@
pth_stackalign_LDADD =3D -lpthread
rcrl_SOURCES =3D rcrl.c
readline1_SOURCES =3D readline1.c
+res_search_SOURCES =3D res_search.c
+res_search_LDADD =3D -lresolv -lpthread
resolv_SOURCES =3D resolv.c
rlimit_nofile_SOURCES =3D rlimit_nofile.c
selfrun_SOURCES =3D selfrun.c
@@ -206,6 +212,8 @@
thread_exits_LDADD =3D -lpthread
threaded_fork_SOURCES =3D threaded-fork.c
threaded_fork_LDADD =3D -lpthread
+threadederrno_SOURCES =3D threadederrno.c
+threadederrno_LDADD =3D -lpthread
tls_SOURCES =3D tls.c tls2.c
tls_DEPENDENCIES =3D tls.so
tls_LDFLAGS =3D -Wl,-rpath,$(top_builddir)/none/tests
Copied: trunk/none/tests/res_search.c (from rev 4052, trunk/corecheck/tes=
ts/res_search.c)
Copied: trunk/none/tests/res_search.stderr.exp (from rev 4052, trunk/core=
check/tests/res_search.stderr.exp)
Copied: trunk/none/tests/res_search.stdout.exp (from rev 4052, trunk/core=
check/tests/res_search.stdout.exp)
Copied: trunk/none/tests/res_search.vgtest (from rev 4052, trunk/corechec=
k/tests/res_search.vgtest)
Copied: trunk/none/tests/threadederrno.c (from rev 4052, trunk/corecheck/=
tests/threadederrno.c)
Copied: trunk/none/tests/threadederrno.stderr.exp (from rev 4052, trunk/c=
orecheck/tests/threadederrno.stderr.exp)
Copied: trunk/none/tests/threadederrno.stdout.exp (from rev 4052, trunk/c=
orecheck/tests/threadederrno.stdout.exp)
Copied: trunk/none/tests/threadederrno.vgtest (from rev 4052, trunk/corec=
heck/tests/threadederrno.vgtest)
|
|
From: Nicholas N. <nj...@cs...> - 2005-06-30 04:40:51
|
On Sun, 26 Jun 2005, Nicholas Nethercote wrote: >> valgrind.vs is used for linking "stage2", which versions the exported >> ... >> So, can I just remove that? > > I'd be fine with it going. It's been a couple of days and no-one's objected -- I say do it! :) Thanks, Dirk. N |
|
From: Nicholas N. <nj...@cs...> - 2005-06-30 04:35:24
|
On Fri, 24 Jun 2005, Craig Chaney wrote: > As I've been looking into the last few remaining regression test > failures for Paul's ppc port of Valgrind 2.4, I came across a couple of > issues that I can't see an easy resolution for. The issues are minor > and are not likely to have a very big impact on real-life valgrind use. > But it would be nice to find a simple way to fix them. > > Issue 1: > Sometimes, when the client program calls VALGRIND_DO_LEAK_CHECK, > valgrind can miss some leaked memory blocks. This will happen when > "dead" registers (i.e. registers that will never be read before being > overwritten) still contain memory addresses of the blocks that are > leaked. I found this with the leak-cycle and leak-tree regression > tests. Since the memory walking algorithm includes all of the gprs in > its root set, valgrind believes that there are live pointers to these > blocks. > > Issue 2: > The code that handles the cache for the dynamic loader (i.e. the code > that mmap's /etc/ld.so.cache) frees the cache memory shortly before the > client program's main() begins. The algorithm that operates on that > cache utilizes a global pointer variable which points to addresses in > the cache. That variable is left dangling when the cache is freed. Not > really a bug, since it's never referenced again. But, the pointer > happens to point to a memory area that gets reused later for mallocs (at > least on ppc). > > This leads to minor inaccuracies when looking for leaked blocks. If > you're really unlucky, the dangling ld pointer will point to the > beginning of a leaked malloc block, causing the leak to go undetected. > If you're only slightly unlucky, it will point to somewhere in the > middle of a leaked memory block, causing valgrind to report the block as > "possibly leaked" rather than "definitely leaked". Both these sound tricky; I can't see any obvious ways around them. N |