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From: Jeremy F. <je...@go...> - 2004-01-25 02:39:04
|
CVS commit by fitzhardinge:
Virtualize CPUID. Rather than just using the host CPU's CPUID,
we now completely virtualize it. The feature flags returned are the
intersection of the set the CPU supports, and the set of flags Valgrind
supports. This turns out to be a small number of features, like FPU,
TSC, MMX, SSE, SSE2, FXSR. All mention of things which are only useful
to kernel-mode code are also suppressed. This CPUID doesn't support
any extended feature flags, or extended CPUID operations. It returns a
vendor string of "ValgrindVCPU".
If the host CPU doesn't support CPUID, then we make sure we treat it as
an illegal instruction (I'm not sure if we handle the eflags bit toggle
test right). This is because the CPUID helper doesn't actually use the
cpuid instruction in all cases, so it may succeed where the host CPU
wouldn't (other instructions which depend on feature flags will end up
generating those instructions, so they'll endup generating a SIGILL if
client code uses them on a CPU which doesn't support them).
M +47 -0 vg_constants.h 1.16
M +38 -14 vg_helpers.S 1.29
M +0 -33 vg_include.h 1.173
M +6 -1 vg_to_ucode.c 1.126
--- valgrind/coregrind/vg_constants.h #1.15:1.16
@@ -95,4 +95,51 @@
#define VG_USERREQ__SIGNAL_RETURNS 0x4001
+/* CPU features */
+#define VG_X86_FEAT_FPU (0*32 + 0)
+#define VG_X86_FEAT_VME (0*32 + 1)
+#define VG_X86_FEAT_DE (0*32 + 2)
+#define VG_X86_FEAT_PSE (0*32 + 3)
+#define VG_X86_FEAT_TSC (0*32 + 4)
+#define VG_X86_FEAT_MSR (0*32 + 5)
+#define VG_X86_FEAT_PAE (0*32 + 6)
+#define VG_X86_FEAT_MCE (0*32 + 7)
+#define VG_X86_FEAT_CX8 (0*32 + 8)
+#define VG_X86_FEAT_APIC (0*32 + 9)
+#define VG_X86_FEAT_SEP (0*32 + 11)
+#define VG_X86_FEAT_MTRR (0*32 + 12)
+#define VG_X86_FEAT_PGE (0*32 + 13)
+#define VG_X86_FEAT_MCA (0*32 + 14)
+#define VG_X86_FEAT_CMOV (0*32 + 15)
+#define VG_X86_FEAT_PAT (0*32 + 16)
+#define VG_X86_FEAT_PSE36 (0*32 + 17)
+#define VG_X86_FEAT_CLFSH (0*32 + 19)
+#define VG_X86_FEAT_DS (0*32 + 21)
+#define VG_X86_FEAT_ACPI (0*32 + 22)
+#define VG_X86_FEAT_MMX (0*32 + 23)
+#define VG_X86_FEAT_FXSR (0*32 + 24)
+#define VG_X86_FEAT_SSE (0*32 + 25)
+#define VG_X86_FEAT_SSE2 (0*32 + 26)
+#define VG_X86_FEAT_SS (0*32 + 27)
+#define VG_X86_FEAT_HT (0*32 + 28)
+#define VG_X86_FEAT_TM (0*32 + 29)
+#define VG_X86_FEAT_PBE (0*32 + 31)
+
+#define VG_X86_FEAT_EST (1*32 + 7)
+#define VG_X86_FEAT_TM2 (1*32 + 8)
+#define VG_X86_FEAT_CNXTID (1*32 + 10)
+
+/* Used internally to mark whether CPUID is even implemented */
+#define VG_X86_FEAT_CPUID (2*32 + 0)
+
+/* The set of features we're willing to support for the client */
+#define VG_SUPPORTED_FEATURES \
+ ((1 << VG_X86_FEAT_FPU) | \
+ (1 << VG_X86_FEAT_TSC) | \
+ (1 << VG_X86_FEAT_CMOV) | \
+ (1 << VG_X86_FEAT_MMX) | \
+ (1 << VG_X86_FEAT_FXSR) | \
+ (1 << VG_X86_FEAT_SSE) | \
+ (1 << VG_X86_FEAT_SSE2))
+
/* Various environment variables we pay attention to */
--- valgrind/coregrind/vg_helpers.S #1.28:1.29
@@ -194,5 +194,6 @@
issue a "real" cpuid instruction and then mask out
the bits of the features we do not support currently (3dnow mostly).
-
+ We also claim to not support most CPUID operations.
+
Dirk Mueller <mu...@kd...>
@@ -214,17 +215,37 @@
movl 32(%esp), %eax
- cmpl $0x80000001, %eax
- je cpuid_no3dnow
-
- cpuid
- jmp cpuid__99
-
-cpuid_no3dnow:
- cpuid
+ /* eax==0 - max valid request+processor vendor */
+ cmpl $0, %eax
+ jne 1f
+
+ movl $1, %eax /* only support request 1 */
+ movl valgrind_brand+0, %ebx
+ movl valgrind_brand+4, %edx
+ movl valgrind_brand+8, %ecx
+ jmp 99f
+
+ /* eax==1 - CPU features and model ID */
+1: cmpl $1, %eax
+ jne 2f
+
+ cpuid /* get host CPU's capabilities */
+
+ movl $0111, %eax
+ movl $0, %ebx /* clear APIC id, CLFLUSH size, Brand ID */
+ movl $0, %ecx /* clear extended feature bits */
+ andl $VG_SUPPORTED_FEATURES, %edx /* mask off feature bits we don't support */
+ jmp 99f
+
+ /* eax=0x80000000 - extended cpuid functions */
+2: cmpl $0x80000000, %eax
+ jne 99f
+
+ /* leave eax==0x80000000 - we don't support any other extended operations */
+ movl valgrind_brand+0, %ebx /* AMD load the brand string again - */
+ movl valgrind_brand+4, %edx /* Intel leaves them "reserved" */
+ movl valgrind_brand+8, %ecx
- andl $0x3fffffff, %edx
-
-cpuid__99:
- movl %edx, 20(%esp)
+
+99: movl %edx, 20(%esp)
movl %ecx, 24(%esp)
movl %ebx, 28(%esp)
@@ -236,5 +257,8 @@
popl %eax
ret
-
+.data
+valgrind_brand:
+ .ascii "ValgrindVCPU"
+.text
/* Fetch the FPU status register.
--- valgrind/coregrind/vg_include.h #1.172:1.173
@@ -1137,37 +1137,4 @@ extern Bool VG_(is_chained_jumpsite)
------------------------------------------------------------------ */
-#define VG_X86_FEAT_FPU (0*32 + 0)
-#define VG_X86_FEAT_VME (0*32 + 1)
-#define VG_X86_FEAT_DE (0*32 + 2)
-#define VG_X86_FEAT_PSE (0*32 + 3)
-#define VG_X86_FEAT_TSC (0*32 + 4)
-#define VG_X86_FEAT_MSR (0*32 + 5)
-#define VG_X86_FEAT_PAE (0*32 + 6)
-#define VG_X86_FEAT_MCE (0*32 + 7)
-#define VG_X86_FEAT_CX8 (0*32 + 8)
-#define VG_X86_FEAT_APIC (0*32 + 9)
-#define VG_X86_FEAT_SEP (0*32 + 11)
-#define VG_X86_FEAT_MTRR (0*32 + 12)
-#define VG_X86_FEAT_PGE (0*32 + 13)
-#define VG_X86_FEAT_MCA (0*32 + 14)
-#define VG_X86_FEAT_CMOV (0*32 + 15)
-#define VG_X86_FEAT_PAT (0*32 + 16)
-#define VG_X86_FEAT_PSE36 (0*32 + 17)
-#define VG_X86_FEAT_CLFSH (0*32 + 19)
-#define VG_X86_FEAT_DS (0*32 + 21)
-#define VG_X86_FEAT_ACPI (0*32 + 22)
-#define VG_X86_FEAT_MMX (0*32 + 23)
-#define VG_X86_FEAT_FXSR (0*32 + 24)
-#define VG_X86_FEAT_SSE (0*32 + 25)
-#define VG_X86_FEAT_SSE2 (0*32 + 26)
-#define VG_X86_FEAT_SS (0*32 + 27)
-#define VG_X86_FEAT_HT (0*32 + 28)
-#define VG_X86_FEAT_TM (0*32 + 29)
-#define VG_X86_FEAT_PBE (0*32 + 31)
-
-#define VG_X86_FEAT_EST (1*32 + 7)
-#define VG_X86_FEAT_TM2 (1*32 + 8)
-#define VG_X86_FEAT_CNXTID (1*32 + 10)
-
Bool VG_(cpu_has_feature)(UInt feat);
--- valgrind/coregrind/vg_to_ucode.c #1.125:1.126
@@ -46,5 +46,5 @@
/*------------------------------------------------------------*/
-#define VG_N_FEATURE_WORDS 2
+#define VG_N_FEATURE_WORDS 3
static Int cpuid_level = -2; /* -2 -> not initialized */
@@ -109,4 +109,6 @@ static void get_cpu_features(void)
}
+ cpu_features[2] |= (1 << (VG_X86_FEAT_CPUID%32));
+
cpuid_level = cpuid_eax(0);
@@ -6504,4 +6506,7 @@ static Addr disInstr ( UCodeBlock* cb, A
case 0xA2: /* CPUID */
+ if (!VG_(cpu_has_feature)(VG_X86_FEAT_CPUID))
+ goto decode_failure;
+
t1 = newTemp(cb);
t2 = newTemp(cb);
|
|
From: Jeremy F. <je...@go...> - 2004-01-25 02:28:05
|
On Sat, 2004-01-24 at 10:18, Nicholas Nethercote wrote: > Moved stage2.c into vg_main.c. Merged main() and VG_(main)(); VG_(main)() > no longer exists. One advantage of this is that global > variables/structures needed for communicating between the two can be made > local. Also, the order in which things happen has been simplified. > > This is mostly just a big refactoring. Startup is now a fair bit easier to > understand. Dependencies between the various startup stages are fairly well > documented in comments. Also, --help and --version now work properly -- > eg. --help gives tool-specific help if --tool was specified. There is still > some parts where things could be reordered and/or simplified, and where the > dependencies aren't clear. These are marked with 'XXX'. This looks pretty good. All the dependencies on having to read /proc/self/maps before/after allocating various pieces of memory should be obsolete now. This is because 1) the client hasn't run at all at this early stage, so there are no dynamically generated mappings, and 2) anyway, all client mappings are in the client address space, and all Valgrind mappings are above, so there's no likelihood of confusing the two. I don't know if this actually makes any difference, but it seemed like a couple of things were initialized in somewhat unnatural places because of this old constraint. Also, I think read and parse of /proc/self/maps were separated because it was quite common to read /proc/self/maps once, then parse it multiple times for various reasons (in fact, main() does this now). I think this is still a useful thing to have, though reading /proc/self/maps should now only be necessary during startup, since after that the Segment list will tell you everything you need to know about the layout of the address space. J |