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From: Mark W. <ma...@kl...> - 2022-11-26 21:36:20
|
Hi Eyal, On Sat, Nov 26, 2022 at 01:22:51PM -0700, Eyal Soha wrote: > I found a false positive in amd64 conditional move. I'm comfortable fixing > it if I can just find how the cmov gets translated into IR for memcheck. > I've done work on other IR before but I'm having the hardest time just > finding where this code is generated! > > The issue is that the sign flag is depending upon all bits being defined > where actually it only needs the highest bit. > > Where can I find how cmovnz translates to the valid bit checking IR? If > there are docs that will help me, I'm happy to read them. And if not, I'll > make docs to describe whatever I'm taught. The amd64 code is transformed into VEX IR in VEX/priv/guest_amd64_toIR.c. Look for "cmov not zero" to find cmovnz. Which will call dis_cmov_E_G which uses mk_amd64g_calculate_condition. The actual IR created is described in VEX/pub/libvex_ir.h. The code that instruments this IR for memcheck definedness checking is in memcheck/mc_translate.c. README_DEVELOPERS has some hints at the end about Printing out problematic blocks. valgrind can print out various stages of the IR, which is really helpful tracking down where which transformation occurs. Cheers, Mark |
|
From: Eyal S. <eya...@gm...> - 2022-11-26 20:23:13
|
I found a false positive in amd64 conditional move. I'm comfortable fixing it if I can just find how the cmov gets translated into IR for memcheck. I've done work on other IR before but I'm having the hardest time just finding where this code is generated! The issue is that the sign flag is depending upon all bits being defined where actually it only needs the highest bit. Where can I find how cmovnz translates to the valid bit checking IR? If there are docs that will help me, I'm happy to read them. And if not, I'll make docs to describe whatever I'm taught. Thanks! Eyal |