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From: Julian S. <se...@so...> - 2021-11-13 19:00:41
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=595341b150312d2407bd43304449bf39ec3e1fa8 commit 595341b150312d2407bd43304449bf39ec3e1fa8 Author: Julian Seward <js...@ac...> Date: Sat Nov 13 19:59:07 2021 +0100 amd64 front end: add more spec rules: S after SHRQ Z after SHLQ NZ after SHLQ Z after SHLL S after SHLL The lack of at least one of these was observed to cause occasional false positives in Memcheck. Plus add commented-out cases so as to complete the set of 12 rules {Z,NZ,S,NS} after {SHRQ,SHLQ,SHLL}. The commented-out ones are commented out because I so far didn't find any use cases for them. Diff: --- VEX/priv/guest_amd64_helpers.c | 60 ++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 58 insertions(+), 2 deletions(-) diff --git a/VEX/priv/guest_amd64_helpers.c b/VEX/priv/guest_amd64_helpers.c index 9d61e7a0fd..ba71c1b62f 100644 --- a/VEX/priv/guest_amd64_helpers.c +++ b/VEX/priv/guest_amd64_helpers.c @@ -1823,16 +1823,26 @@ IRExpr* guest_amd64_spechelper ( const HChar* function_name, /*---------------- SHRQ ----------------*/ if (isU64(cc_op, AMD64G_CC_OP_SHRQ) && isU64(cond, AMD64CondZ)) { - /* SHRQ, then Z --> test dep1 == 0 */ + /* SHRQ, then Z --> test result[63:0] == 0 */ return unop(Iop_1Uto64, binop(Iop_CmpEQ64, cc_dep1, mkU64(0))); } if (isU64(cc_op, AMD64G_CC_OP_SHRQ) && isU64(cond, AMD64CondNZ)) { - /* SHRQ, then NZ --> test dep1 != 0 */ + /* SHRQ, then NZ --> test result[63:0] != 0 */ return unop(Iop_1Uto64, binop(Iop_CmpNE64, cc_dep1, mkU64(0))); } + if (isU64(cc_op, AMD64G_CC_OP_SHRQ) && isU64(cond, AMD64CondS)) { + /* SHRQ, then S --> (ULong)result[63] (result is in dep1) */ + return binop(Iop_Shr64, cc_dep1, mkU8(63)); + } + // No known test case for this, hence disabled: + //if (isU64(cc_op, AMD64G_CC_OP_SHRQ) && isU64(cond, AMD64CondNS)) { + // /* SHRQ, then NS --> (ULong) ~ result[63] */ + // vassert(0); + //} + /*---------------- SHRL ----------------*/ if (isU64(cc_op, AMD64G_CC_OP_SHRL) && isU64(cond, AMD64CondZ)) { @@ -1881,6 +1891,52 @@ IRExpr* guest_amd64_spechelper ( const HChar* function_name, // mkU32(0))); //} + /*---------------- SHLQ ----------------*/ + + if (isU64(cc_op, AMD64G_CC_OP_SHLQ) && isU64(cond, AMD64CondZ)) { + /* SHLQ, then Z --> test dep1 == 0 */ + return unop(Iop_1Uto64, + binop(Iop_CmpEQ64, cc_dep1, mkU64(0))); + } + if (isU64(cc_op, AMD64G_CC_OP_SHLQ) && isU64(cond, AMD64CondNZ)) { + /* SHLQ, then NZ --> test dep1 != 0 */ + return unop(Iop_1Uto64, + binop(Iop_CmpNE64, cc_dep1, mkU64(0))); + } + + //if (isU64(cc_op, AMD64G_CC_OP_SHLQ) && isU64(cond, AMD64CondS)) { + // /* SHLQ, then S --> (ULong)result[63] */ + // vassert(0); + //} + //if (isU64(cc_op, AMD64G_CC_OP_SHLQ) && isU64(cond, AMD64CondNS)) { + // /* SHLQ, then NS --> (ULong) ~ result[63] */ + // vassert(0); + //} + + /*---------------- SHLL ----------------*/ + + if (isU64(cc_op, AMD64G_CC_OP_SHLL) && isU64(cond, AMD64CondZ)) { + /* SHLL, then Z --> test result[31:0] == 0 */ + return unop(Iop_1Uto64, + binop(Iop_CmpEQ32, unop(Iop_64to32, cc_dep1), + mkU32(0))); + } + //if (isU64(cc_op, AMD64G_CC_OP_SHLL) && isU64(cond, AMD64CondNZ)) { + // /* SHLL, then NZ --> test dep1 != 0 */ + // vassert(0); + //} + + if (isU64(cc_op, AMD64G_CC_OP_SHLL) && isU64(cond, AMD64CondS)) { + /* SHLL, then S --> (ULong)result[31] */ + return binop(Iop_And64, + binop(Iop_Shr64, cc_dep1, mkU8(31)), + mkU64(1)); + } + //if (isU64(cc_op, AMD64G_CC_OP_SHLL) && isU64(cond, AMD64CondNS)) { + // /* SHLL, then NS --> (ULong) ~ result[31] */ + // vassert(0); + //} + /*---------------- COPY ----------------*/ /* This can happen, as a result of amd64 FP compares: "comisd ... ; jbe" for example. */ |
|
From: Paul F. <pa...@so...> - 2021-11-13 17:11:00
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=4fd9bd3ed02db5a837fe734e1d525ab222053d9f commit 4fd9bd3ed02db5a837fe734e1d525ab222053d9f Author: Paul Floyd <pj...@wa...> Date: Sat Nov 13 18:09:20 2021 +0100 Remove a default suppession for GCC/libstdc++ This is covered by cxx-freeres Diff: --- freebsd.supp | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/freebsd.supp b/freebsd.supp index 7f9b22bb30..b86b800d80 100644 --- a/freebsd.supp +++ b/freebsd.supp @@ -17,17 +17,6 @@ obj:/libexec/ld-elf32.so.1 obj:/libexec/ld-elf32.so.1 } - -{ - MEMCHECK-LIBSTDC++-REACHABLE - Memcheck:Leak - match-leak-kinds: reachable - fun:malloc - obj:/usr/local/lib*/gcc*/libstdc++.so.* - obj:/libexec/ld-elf*.so.1 - obj:/libexec/ld-elf*.so.1 - obj:/libexec/ld-elf*.so.1 -} { MEMCHECK-LIBC-REACHABLE-1 Memcheck:Leak |
|
From: Paul F. <pa...@so...> - 2021-11-13 11:33:26
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=39b4bbe3a1e48f9363351bc76f787b2c82a566b4 commit 39b4bbe3a1e48f9363351bc76f787b2c82a566b4 Author: Paul Floyd <pj...@wa...> Date: Sat Nov 13 12:31:41 2021 +0100 Bugs 435732 and 403802 again This time with debuginfo removed. Also update the vgtest files for a couple of massif tests (and also the expected because of the commmand line change). Not yet tested these two with debuginfo installed. Diff: --- massif/tests/new-cpp.post.exp | 2 +- massif/tests/new-cpp.vgtest | 1 + massif/tests/overloaded-new.post.exp | 2 +- massif/tests/overloaded-new.vgtest | 1 + memcheck/tests/libstdc++.supp | 23 +++++++++-------------- 5 files changed, 13 insertions(+), 16 deletions(-) diff --git a/massif/tests/new-cpp.post.exp b/massif/tests/new-cpp.post.exp index 9d90cf6c22..5935771617 100644 --- a/massif/tests/new-cpp.post.exp +++ b/massif/tests/new-cpp.post.exp @@ -1,6 +1,6 @@ -------------------------------------------------------------------------------- Command: ./new-cpp -Massif arguments: --stacks=no --time-unit=B --massif-out-file=massif.out --ignore-fn=__part_load_locale --ignore-fn=__time_load_locale --ignore-fn=dwarf2_unwind_dyld_add_image_hook --ignore-fn=get_or_create_key_element --ignore-fn=_GLOBAL__sub_I_eh_alloc.cc --ignore-fn=call_init.part.0 +Massif arguments: --stacks=no --time-unit=B --massif-out-file=massif.out --ignore-fn=__part_load_locale --ignore-fn=__time_load_locale --ignore-fn=dwarf2_unwind_dyld_add_image_hook --ignore-fn=get_or_create_key_element --ignore-fn=_GLOBAL__sub_I_eh_alloc.cc --ignore-fn=call_init.part.0 --ignore-fn=call_init ms_print arguments: massif.out -------------------------------------------------------------------------------- diff --git a/massif/tests/new-cpp.vgtest b/massif/tests/new-cpp.vgtest index 88bdf939b9..ebcef897a0 100644 --- a/massif/tests/new-cpp.vgtest +++ b/massif/tests/new-cpp.vgtest @@ -2,5 +2,6 @@ prog: new-cpp vgopts: --stacks=no --time-unit=B --massif-out-file=massif.out vgopts: --ignore-fn=__part_load_locale --ignore-fn=__time_load_locale --ignore-fn=dwarf2_unwind_dyld_add_image_hook vgopts: --ignore-fn=get_or_create_key_element --ignore-fn=_GLOBAL__sub_I_eh_alloc.cc --ignore-fn=call_init.part.0 +vgopts: --ignore-fn=call_init post: perl ../../massif/ms_print massif.out | ../../tests/filter_addresses cleanup: rm massif.out diff --git a/massif/tests/overloaded-new.post.exp b/massif/tests/overloaded-new.post.exp index e55885fc57..ae112710b7 100644 --- a/massif/tests/overloaded-new.post.exp +++ b/massif/tests/overloaded-new.post.exp @@ -1,6 +1,6 @@ -------------------------------------------------------------------------------- Command: ./overloaded-new -Massif arguments: --stacks=no --time-unit=B --massif-out-file=massif.out --ignore-fn=__part_load_locale --ignore-fn=__time_load_locale --ignore-fn=dwarf2_unwind_dyld_add_image_hook --ignore-fn=get_or_create_key_element --ignore-fn=_GLOBAL__sub_I_eh_alloc.cc --ignore-fn=call_init.part.0 +Massif arguments: --stacks=no --time-unit=B --massif-out-file=massif.out --ignore-fn=__part_load_locale --ignore-fn=__time_load_locale --ignore-fn=dwarf2_unwind_dyld_add_image_hook --ignore-fn=get_or_create_key_element --ignore-fn=_GLOBAL__sub_I_eh_alloc.cc --ignore-fn=call_init.part.0 --ignore-fn=call_init ms_print arguments: massif.out -------------------------------------------------------------------------------- diff --git a/massif/tests/overloaded-new.vgtest b/massif/tests/overloaded-new.vgtest index 20bcd97e62..fc95acc2f3 100644 --- a/massif/tests/overloaded-new.vgtest +++ b/massif/tests/overloaded-new.vgtest @@ -2,5 +2,6 @@ prog: overloaded-new vgopts: --stacks=no --time-unit=B --massif-out-file=massif.out vgopts: --ignore-fn=__part_load_locale --ignore-fn=__time_load_locale --ignore-fn=dwarf2_unwind_dyld_add_image_hook vgopts: --ignore-fn=get_or_create_key_element --ignore-fn=_GLOBAL__sub_I_eh_alloc.cc --ignore-fn=call_init.part.0 +vgopts: --ignore-fn=call_init post: perl ../../massif/ms_print massif.out | ../../tests/filter_addresses cleanup: rm massif.out diff --git a/memcheck/tests/libstdc++.supp b/memcheck/tests/libstdc++.supp index 3cd2e628da..852d8ab0b6 100644 --- a/memcheck/tests/libstdc++.supp +++ b/memcheck/tests/libstdc++.supp @@ -52,26 +52,21 @@ # All the following suppressions are variants of # _dl_init -> call_init which calls the DT_INIT_ARRAY functions +# These suppressions are sensitive to changes to GCC and libstdc++ +# in order to generate a suppression stanza run +# +# /vg-in-place --gen-suppressions=all --show-reachable=yes --leak-check=full --run-cxx-freeres=no memcheck/tests/leak_cpp_interior +# +# since leaks are ordered by increasing size the stanza to look for is the last one + + { malloc-leaks-cxx-stl-string-classes Memcheck:Leak match-leak-kinds: reachable fun:malloc obj:*lib*/libstdc++.so* - fun:call_init.part.0 - fun:call_init - fun:_dl_init - obj:*lib*/ld-2.*.so -} -{ - malloc-leaks-cxx-stl-string-classes-2 - Memcheck:Leak - match-leak-kinds: reachable - fun:malloc - obj:*lib*/libstdc++.so* - fun:call_init.part.0 - fun:_dl_init - obj:*lib*/ld-2.*.so + fun:call_init* } { malloc-leaks-cxx-stl-string-classes-debug |
|
From: Julian S. <se...@so...> - 2021-11-13 08:28:39
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=2be719921e700a9ac9b85f470ed87cb8adf8151b commit 2be719921e700a9ac9b85f470ed87cb8adf8151b Author: Julian Seward <js...@ac...> Date: Sat Nov 13 09:27:01 2021 +0100 Bug 445415 - arm64 front end: alignment checks missing for atomic instructions. For the arm64 front end, none of the atomic instructions have address alignment checks included in their IR. They all should. The effect of missing alignment checks in the IR is that, since this IR will in most cases be translated back to atomic instructions in the back end, we will get alignment traps (SIGBUS) on the host side and not on the guest side, which is (very) incorrect behaviour of the simulation. Diff: --- NEWS | 2 ++ VEX/priv/guest_arm64_toIR.c | 47 ++++++++++++++++++++++++++++++++++++++++----- VEX/priv/host_arm64_defs.c | 1 + VEX/priv/host_arm64_isel.c | 5 +++-- 4 files changed, 48 insertions(+), 7 deletions(-) diff --git a/NEWS b/NEWS index 1fafeeef9e..708c6e1df7 100644 --- a/NEWS +++ b/NEWS @@ -51,12 +51,14 @@ are not entered into bugzilla tend to get forgotten about or ignored. 445032 valgrind/memcheck crash with SIGSEGV when SIGVTALRM timer used and libthr.so associated 445354 arm64 backend: incorrect code emitted for doubleword CAS +445415 arm64 front end: alignment checks missing for atomic instructions To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX where XXXXXX is the bug number as listed below. + Release 3.18.0 (15 Oct 2021) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c index ee018c6a9f..16a7e075f0 100644 --- a/VEX/priv/guest_arm64_toIR.c +++ b/VEX/priv/guest_arm64_toIR.c @@ -4833,6 +4833,34 @@ static IRTemp gen_zwidening_load ( UInt szB, IRTemp addr ) } +/* Generate a SIGBUS followed by a restart of the current instruction if + `effective_addr` is `align`-aligned. This is required behaviour for atomic + instructions. This assumes that guest_RIP_curr_instr is set correctly! + + This is hardwired to generate SIGBUS because so far the only supported arm64 + (arm64-linux) does that. Should we need to later extend it to generate some + other signal, use the same scheme as with gen_SIGNAL_if_not_XX_aligned in + guest_amd64_toIR.c. */ +static +void gen_SIGBUS_if_not_XX_aligned ( IRTemp effective_addr, ULong align ) +{ + if (align == 1) { + return; + } + vassert(align == 16 || align == 8 || align == 4 || align == 2); + stmt( + IRStmt_Exit( + binop(Iop_CmpNE64, + binop(Iop_And64,mkexpr(effective_addr),mkU64(align-1)), + mkU64(0)), + Ijk_SigBUS, + IRConst_U64(guest_PC_curr_instr), + OFFB_PC + ) + ); +} + + /* Generate a "standard 7" name, from bitQ and size. But also allow ".1d" since that's occasionally useful. */ static @@ -6670,7 +6698,7 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, IRTemp ea = newTemp(Ity_I64); assign(ea, getIReg64orSP(nn)); - /* FIXME generate check that ea is szB-aligned */ + gen_SIGBUS_if_not_XX_aligned(ea, szB); if (isLD && ss == BITS5(1,1,1,1,1)) { IRTemp res = newTemp(ty); @@ -6803,7 +6831,7 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, IRTemp ea = newTemp(Ity_I64); assign(ea, getIReg64orSP(nn)); - /* FIXME generate check that ea is 2*elemSzB-aligned */ + gen_SIGBUS_if_not_XX_aligned(ea, fullSzB); if (isLD && ss == BITS5(1,1,1,1,1)) { if (abiinfo->guest__use_fallback_LLSC) { @@ -7044,7 +7072,7 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, IRTemp ea = newTemp(Ity_I64); assign(ea, getIReg64orSP(nn)); - /* FIXME generate check that ea is szB-aligned */ + gen_SIGBUS_if_not_XX_aligned(ea, szB); if (isLD) { IRTemp res = newTemp(ty); @@ -7159,6 +7187,7 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, IRTemp ea = newTemp(Ity_I64); assign(ea, getIReg64orSP(nn)); + gen_SIGBUS_if_not_XX_aligned(ea, szB); // Insert barrier before loading for acquire and acquire-release variants: // A and AL. @@ -7266,6 +7295,10 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, IRType ty = integerIRTypeOfSize(szB); Bool is64 = szB == 8; + IRTemp ea = newTemp(Ity_I64); + assign(ea, getIReg64orSP(nn)); + gen_SIGBUS_if_not_XX_aligned(ea, szB); + IRExpr *exp = narrowFrom64(ty, getIReg64orZR(ss)); IRExpr *new = narrowFrom64(ty, getIReg64orZR(tt)); @@ -7275,7 +7308,7 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, // Store the result back if LHS remains unchanged in memory. IRTemp old = newTemp(ty); stmt( IRStmt_CAS(mkIRCAS(/*oldHi*/IRTemp_INVALID, old, - Iend_LE, getIReg64orSP(nn), + Iend_LE, mkexpr(ea), /*expdHi*/NULL, exp, /*dataHi*/NULL, new)) ); @@ -7307,6 +7340,10 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, if ((ss & 0x1) || (tt & 0x1)) { /* undefined; fall through */ } else { + IRTemp ea = newTemp(Ity_I64); + assign(ea, getIReg64orSP(nn)); + gen_SIGBUS_if_not_XX_aligned(ea, is64 ? 16 : 8); + IRExpr *expLo = getIRegOrZR(is64, ss); IRExpr *expHi = getIRegOrZR(is64, ss + 1); IRExpr *newLo = getIRegOrZR(is64, tt); @@ -7318,7 +7355,7 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, stmt(IRStmt_MBE(Imbe_Fence)); stmt( IRStmt_CAS(mkIRCAS(oldHi, oldLo, - Iend_LE, getIReg64orSP(nn), + Iend_LE, mkexpr(ea), expHi, expLo, newHi, newLo)) ); diff --git a/VEX/priv/host_arm64_defs.c b/VEX/priv/host_arm64_defs.c index b65e27db4d..39c6aaa46b 100644 --- a/VEX/priv/host_arm64_defs.c +++ b/VEX/priv/host_arm64_defs.c @@ -4033,6 +4033,7 @@ Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc, case Ijk_FlushDCache: trcval = VEX_TRC_JMP_FLUSHDCACHE; break; case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break; case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break; + case Ijk_SigBUS: trcval = VEX_TRC_JMP_SIGBUS; break; //case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break; case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break; /* We don't expect to see the following being assisted. */ diff --git a/VEX/priv/host_arm64_isel.c b/VEX/priv/host_arm64_isel.c index 094e7e74b4..82cb2d78c6 100644 --- a/VEX/priv/host_arm64_isel.c +++ b/VEX/priv/host_arm64_isel.c @@ -4483,6 +4483,7 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt ) case Ijk_InvalICache: case Ijk_FlushDCache: case Ijk_SigTRAP: + case Ijk_SigBUS: case Ijk_Yield: { HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst)); addInstr(env, ARM64Instr_XAssisted(r, amPC, cc, @@ -4576,8 +4577,8 @@ static void iselNext ( ISelEnv* env, case Ijk_InvalICache: case Ijk_FlushDCache: case Ijk_SigTRAP: - case Ijk_Yield: - { + case Ijk_SigBUS: + case Ijk_Yield: { HReg r = iselIntExpr_R(env, next); ARM64AMode* amPC = mk_baseblock_64bit_access_amode(offsIP); addInstr(env, ARM64Instr_XAssisted(r, amPC, ARM64cc_AL, jk)); |
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From: Julian S. <se...@so...> - 2021-11-13 08:08:59
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=92e56be59b3f32e7c749bfabcd6d775b779001ab commit 92e56be59b3f32e7c749bfabcd6d775b779001ab Author: Julian Seward <js...@ac...> Date: Sat Nov 13 09:08:27 2021 +0100 Add missing NEWS entry for bug 444399 (== 434283). Diff: --- NEWS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/NEWS b/NEWS index 55ad93c4cb..1fafeeef9e 100644 --- a/NEWS +++ b/NEWS @@ -42,6 +42,8 @@ than mailing the developers (or mailing lists) directly -- bugs that are not entered into bugzilla tend to get forgotten about or ignored. 444242 s390x: Valgrind crashes on EXRL with negative offset +444399 arm64: unhandled instruction 0xC87F2D89 (LD{,A}XP and ST{,L}XP). + == 434283 444495 dhat/tests/copy fails on s390x 444571 PPC, fix the lxsibzx and lxsihzx so they only load their respective sized data. |