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From: Carl L. <ca...@so...> - 2021-03-30 16:13:35
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=4bcc6c8a97c10c4dd41b35bd3b3035ec4037d524 commit 4bcc6c8a97c10c4dd41b35bd3b3035ec4037d524 Author: Carl Love <ce...@us...> Date: Mon Nov 16 19:09:47 2020 -0600 VSX Permute Control Vector Generate Operation tests. Diff: --- NEWS | 1 + none/tests/ppc64/test_isa_3_1_XT.c | 64 ++++++++ none/tests/ppc64/test_isa_3_1_XT.stdout.exp | 226 +++++++++++++++++++++++++++- 3 files changed, 290 insertions(+), 1 deletion(-) diff --git a/NEWS b/NEWS index aa398cf54b..2e42e74b2e 100644 --- a/NEWS +++ b/NEWS @@ -154,6 +154,7 @@ where XXXXXX is the bug number as listed below. 428909 helgrind: need to intercept duplicate libc definitions for Fedora 33 429352 PPC ISA 3.1 support is missing, part 7 429354 PPC ISA 3.1 support is missing, part 8 +429375 PPC ISA 3.1 support is missing, part 9 429692 unhandled ppc64le-linux syscall: 147 (getsid) 429864 s390x: C++ atomic test_and_set yields false-positive memcheck diagnostics diff --git a/none/tests/ppc64/test_isa_3_1_XT.c b/none/tests/ppc64/test_isa_3_1_XT.c index c16ddedac3..a54e8763a7 100644 --- a/none/tests/ppc64/test_isa_3_1_XT.c +++ b/none/tests/ppc64/test_isa_3_1_XT.c @@ -491,6 +491,54 @@ static void test_pstxv_4 (void) { static void test_pstxv_0 (void) { __asm__ __volatile__ ("pstxv %x0, 0(%1), 0" :: "wa" (vec_xs), "r" (ra) ); } +static void test_xxgenpcvbm_imm0 (void) { + __asm__ __volatile__ ("xxgenpcvbm %x0, %1, 0" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvbm_imm1 (void) { + __asm__ __volatile__ ("xxgenpcvbm %x0, %1, 1" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvbm_imm2 (void) { + __asm__ __volatile__ ("xxgenpcvbm %x0, %1, 2" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvbm_imm3 (void) { + __asm__ __volatile__ ("xxgenpcvbm %x0, %1, 3" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvhm_imm0 (void) { + __asm__ __volatile__ ("xxgenpcvhm %x0, %1, 0" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvhm_imm1 (void) { + __asm__ __volatile__ ("xxgenpcvhm %x0, %1, 1" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvhm_imm2 (void) { + __asm__ __volatile__ ("xxgenpcvhm %x0, %1, 2" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvhm_imm3 (void) { + __asm__ __volatile__ ("xxgenpcvhm %x0, %1, 3" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvwm_imm0 (void) { + __asm__ __volatile__ ("xxgenpcvwm %x0, %1, 0" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvwm_imm1 (void) { + __asm__ __volatile__ ("xxgenpcvwm %x0, %1, 1" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvwm_imm2 (void) { + __asm__ __volatile__ ("xxgenpcvwm %x0, %1, 2" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvwm_imm3 (void) { + __asm__ __volatile__ ("xxgenpcvwm %x0, %1, 3" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvdm_imm0 (void) { + __asm__ __volatile__ ("xxgenpcvdm %x0, %1, 0" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvdm_imm1 (void) { + __asm__ __volatile__ ("xxgenpcvdm %x0, %1, 1" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvdm_imm2 (void) { + __asm__ __volatile__ ("xxgenpcvdm %x0, %1, 2" : "=wa" (vec_xt) : "v" (vrb) ); +} +static void test_xxgenpcvdm_imm3 (void) { + __asm__ __volatile__ ("xxgenpcvdm %x0, %1, 3" : "=wa" (vec_xt) : "v" (vrb) ); +} static test_list_t testgroup_generic[] = { { &test_lxvkq_imm1, "lxvkq imm1", "XT,UIM"}, /* bcwp */ @@ -592,6 +640,22 @@ static test_list_t testgroup_generic[] = { { &test_xxblendvw, "xxblendvw", "XT,XA,XB,XC"}, /* bcs */ { &test_xxeval_imm0, "xxeval imm0", "XT,XA,XB,XC,IMM"}, /* bcwp */ { &test_xxeval_imm3, "xxeval imm3", "XT,XA,XB,XC,IMM"}, /* bcwp */ + { &test_xxgenpcvbm_imm0, "xxgenpcvbm imm0", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvbm_imm1, "xxgenpcvbm imm1", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvbm_imm2, "xxgenpcvbm imm2", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvbm_imm3, "xxgenpcvbm imm3", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvdm_imm0, "xxgenpcvdm imm0", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvdm_imm1, "xxgenpcvdm imm1", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvdm_imm2, "xxgenpcvdm imm2", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvdm_imm3, "xxgenpcvdm imm3", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvhm_imm0, "xxgenpcvhm imm0", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvhm_imm1, "xxgenpcvhm imm1", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvhm_imm2, "xxgenpcvhm imm2", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvhm_imm3, "xxgenpcvhm imm3", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvwm_imm0, "xxgenpcvwm imm0", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvwm_imm1, "xxgenpcvwm imm1", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvwm_imm2, "xxgenpcvwm imm2", "XT,VRB,IMM"}, /* bcwp */ + { &test_xxgenpcvwm_imm3, "xxgenpcvwm imm3", "XT,VRB,IMM"}, /* bcwp */ { &test_xxpermx_imm0, "xxpermx imm0", "XT,XA,XB,XC,UIM"}, /* bcwp */ { &test_xxpermx_imm3, "xxpermx imm3", "XT,XA,XB,XC,UIM"}, /* bcwp */ { &test_xxsplti32dx_ix0_imm0xa5a5a5a5, "xxsplti32dx ix0_imm0xa5a5a5a5", "XT,IX,IMM32"}, /* bcwp */ diff --git a/none/tests/ppc64/test_isa_3_1_XT.stdout.exp b/none/tests/ppc64/test_isa_3_1_XT.stdout.exp index efa95884e9..8b5f1d1a36 100644 --- a/none/tests/ppc64/test_isa_3_1_XT.stdout.exp +++ b/none/tests/ppc64/test_isa_3_1_XT.stdout.exp @@ -4644,6 +4644,230 @@ xxeval imm3 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 xxeval imm3 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => 8000000000000000 7f800000ff800000 xxeval imm3 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => 8000000000000000 7f800000ff800000 +xxgenpcvbm imm0 7f800000ff800000,ff8000007f800000 => 18031a1b04051e1f 1121314021617 +xxgenpcvbm imm0 ff8000007f800000,ff7ffffe7f7ffffe => 5061a1b1c071e1f 11010214150304 +xxgenpcvbm imm0 ff7ffffe7f7ffffe,0080000e8080000e => 31904051c1d0607 1000121301021617 +xxgenpcvbm imm0 0080000e8080000e,0180055e0180077e => 18021a1b03041e1f 1000121314011617 +xxgenpcvbm imm0 0180055e0180077e,0000111e8000222e => 18011a1b1c021e1f 1011121300151617 +xxgenpcvbm imm0 0000111e8000222e,7ff0000000000000 => 18191a1b011d1e1f 1000121314151617 +xxgenpcvbm imm0 7ff0000000000000,fff0000000000000 => 18021a1b1c1d1e1f 1121314151617 +xxgenpcvbm imm0 fff0000000000000,2208400000000000 => 11a1b1c1d1e1f 1011121314151617 +xxgenpcvbm imm0 2208400000000000,0000000000000009 => 18191a1b1c1d1e1f 1011121314151617 +xxgenpcvbm imm0 0000000000000009,ffff000180000001 => 18191a1b1c1d1e1f 1121302151617 +xxgenpcvbm imm0 ffff000180000001,0000000000000000 => 11a1b021d1e1f 1011121314151617 +xxgenpcvbm imm0 0000000000000000,8000000000000000 => 18191a1b1c1d1e1f 11121314151617 +xxgenpcvbm imm0 8000000000000000,7f800000ff800000 => 3191a1b1c1d1e1f 1000121301021617 + +xxgenpcvbm imm1 7f800000ff800000,ff8000007f800000 => 0 105090c0d0000 +xxgenpcvbm imm1 ff8000007f800000,ff7ffffe7f7ffffe => 0 203060708090d +xxgenpcvbm imm1 ff7ffffe7f7ffffe,0080000e8080000e => 0 10405080a0b0e0f +xxgenpcvbm imm1 0080000e8080000e,0180055e0180077e => 0 105090c0d000000 +xxgenpcvbm imm1 0180055e0180077e,0000111e8000222e => 0 4090d0000000000 +xxgenpcvbm imm1 0000111e8000222e,7ff0000000000000 => 0 10c000000000000 +xxgenpcvbm imm1 7ff0000000000000,fff0000000000000 => 0 1090000000000 +xxgenpcvbm imm1 fff0000000000000,2208400000000000 => 0 809000000000000 +xxgenpcvbm imm1 2208400000000000,0000000000000009 => 0 0 +xxgenpcvbm imm1 0000000000000009,ffff000180000001 => 0 1040000000000 +xxgenpcvbm imm1 ffff000180000001,0000000000000000 => 0 8090c0000000000 +xxgenpcvbm imm1 0000000000000000,8000000000000000 => 0 0 +xxgenpcvbm imm1 8000000000000000,7f800000ff800000 => 0 104050800000000 + +xxgenpcvbm imm2 7f800000ff800000,ff8000007f800000 => 1702151401001110 5041d1c1b031918 +xxgenpcvbm imm2 ff8000007f800000,ff7ffffe7f7ffffe => 201151413001110 71e06051b1a0403 +xxgenpcvbm imm2 ff7ffffe7f7ffffe,0080000e8080000e => 416030213120100 1f071d1c06051918 +xxgenpcvbm imm2 0080000e8080000e,0180055e0180077e => 1702151401001110 1f041d1c1b031918 +xxgenpcvbm imm2 0180055e0180077e,0000111e8000222e => 1701151413001110 1f1e1d1c021a1918 +xxgenpcvbm imm2 0000111e8000222e,7ff0000000000000 => 1716151400121110 1f011d1c1b1a1918 +xxgenpcvbm imm2 7ff0000000000000,fff0000000000000 => 1700151413121110 2011d1c1b1a1918 +xxgenpcvbm imm2 fff0000000000000,2208400000000000 => 100151413121110 1f1e1d1c1b1a1918 +xxgenpcvbm imm2 2208400000000000,0000000000000009 => 1716151413121110 1f1e1d1c1b1a1918 +xxgenpcvbm imm2 0000000000000009,ffff000180000001 => 1716151413121110 2011d1c001a1918 +xxgenpcvbm imm2 ffff000180000001,0000000000000000 => 201151400121110 1f1e1d1c1b1a1918 +xxgenpcvbm imm2 0000000000000000,8000000000000000 => 1716151413121110 1e1d1c1b1a1918 +xxgenpcvbm imm2 8000000000000000,7f800000ff800000 => 16151413121110 1f031d1c02011918 + +xxgenpcvbm imm3 7f800000ff800000,ff8000007f800000 => f0e0a060302 0 +xxgenpcvbm imm3 ff8000007f800000,ff7ffffe7f7ffffe => f0d0c0908070602 0 +xxgenpcvbm imm3 ff7ffffe7f7ffffe,0080000e8080000e => e0b0a0705040100 0 +xxgenpcvbm imm3 0080000e8080000e,0180055e0180077e => e0a060302 0 +xxgenpcvbm imm3 0180055e0180077e,0000111e8000222e => b0602 0 +xxgenpcvbm imm3 0000111e8000222e,7ff0000000000000 => e03 0 +xxgenpcvbm imm3 7ff0000000000000,fff0000000000000 => f0e06 0 +xxgenpcvbm imm3 fff0000000000000,2208400000000000 => 706 0 +xxgenpcvbm imm3 2208400000000000,0000000000000009 => 0 0 +xxgenpcvbm imm3 0000000000000009,ffff000180000001 => f0e0b 0 +xxgenpcvbm imm3 ffff000180000001,0000000000000000 => 70603 0 +xxgenpcvbm imm3 0000000000000000,8000000000000000 => f 0 +xxgenpcvbm imm3 8000000000000000,7f800000ff800000 => e0b0a07 0 + +xxgenpcvdm imm0 7f800000ff800000,ff8000007f800000 => 18191a1b1c1d1e1f 1020304050607 +xxgenpcvdm imm0 ff8000007f800000,ff7ffffe7f7ffffe => 8090a0b0c0d0e0f 1020304050607 +xxgenpcvdm imm0 ff7ffffe7f7ffffe,0080000e8080000e => 1020304050607 1011121314151617 +xxgenpcvdm imm0 0080000e8080000e,0180055e0180077e => 18191a1b1c1d1e1f 1011121314151617 +xxgenpcvdm imm0 0180055e0180077e,0000111e8000222e => 18191a1b1c1d1e1f 1011121314151617 +xxgenpcvdm imm0 0000111e8000222e,7ff0000000000000 => 18191a1b1c1d1e1f 1011121314151617 +xxgenpcvdm imm0 7ff0000000000000,fff0000000000000 => 18191a1b1c1d1e1f 1020304050607 +xxgenpcvdm imm0 fff0000000000000,2208400000000000 => 1020304050607 1011121314151617 +xxgenpcvdm imm0 2208400000000000,0000000000000009 => 18191a1b1c1d1e1f 1011121314151617 +xxgenpcvdm imm0 0000000000000009,ffff000180000001 => 18191a1b1c1d1e1f 1020304050607 +xxgenpcvdm imm0 ffff000180000001,0000000000000000 => 1020304050607 1011121314151617 +xxgenpcvdm imm0 0000000000000000,8000000000000000 => 18191a1b1c1d1e1f 1020304050607 +xxgenpcvdm imm0 8000000000000000,7f800000ff800000 => 1020304050607 1011121314151617 + +xxgenpcvdm imm1 7f800000ff800000,ff8000007f800000 => 0 1020304050607 +xxgenpcvdm imm1 ff8000007f800000,ff7ffffe7f7ffffe => 8090a0b0c0d0e0f 1020304050607 +xxgenpcvdm imm1 ff7ffffe7f7ffffe,0080000e8080000e => 0 8090a0b0c0d0e0f +xxgenpcvdm imm1 0080000e8080000e,0180055e0180077e => 0 0 +xxgenpcvdm imm1 0180055e0180077e,0000111e8000222e => 0 0 +xxgenpcvdm imm1 0000111e8000222e,7ff0000000000000 => 0 0 +xxgenpcvdm imm1 7ff0000000000000,fff0000000000000 => 0 1020304050607 +xxgenpcvdm imm1 fff0000000000000,2208400000000000 => 0 8090a0b0c0d0e0f +xxgenpcvdm imm1 2208400000000000,0000000000000009 => 0 0 +xxgenpcvdm imm1 0000000000000009,ffff000180000001 => 0 1020304050607 +xxgenpcvdm imm1 ffff000180000001,0000000000000000 => 0 8090a0b0c0d0e0f +xxgenpcvdm imm1 0000000000000000,8000000000000000 => 0 1020304050607 +xxgenpcvdm imm1 8000000000000000,7f800000ff800000 => 0 8090a0b0c0d0e0f + +xxgenpcvdm imm2 7f800000ff800000,ff8000007f800000 => 1716151413121110 706050403020100 +xxgenpcvdm imm2 ff8000007f800000,ff7ffffe7f7ffffe => 706050403020100 f0e0d0c0b0a0908 +xxgenpcvdm imm2 ff7ffffe7f7ffffe,0080000e8080000e => 706050403020100 1f1e1d1c1b1a1918 +xxgenpcvdm imm2 0080000e8080000e,0180055e0180077e => 1716151413121110 1f1e1d1c1b1a1918 +xxgenpcvdm imm2 0180055e0180077e,0000111e8000222e => 1716151413121110 1f1e1d1c1b1a1918 +xxgenpcvdm imm2 0000111e8000222e,7ff0000000000000 => 1716151413121110 1f1e1d1c1b1a1918 +xxgenpcvdm imm2 7ff0000000000000,fff0000000000000 => 1716151413121110 706050403020100 +xxgenpcvdm imm2 fff0000000000000,2208400000000000 => 706050403020100 1f1e1d1c1b1a1918 +xxgenpcvdm imm2 2208400000000000,0000000000000009 => 1716151413121110 1f1e1d1c1b1a1918 +xxgenpcvdm imm2 0000000000000009,ffff000180000001 => 1716151413121110 706050403020100 +xxgenpcvdm imm2 ffff000180000001,0000000000000000 => 706050403020100 1f1e1d1c1b1a1918 +xxgenpcvdm imm2 0000000000000000,8000000000000000 => 1716151413121110 706050403020100 +xxgenpcvdm imm2 8000000000000000,7f800000ff800000 => 706050403020100 1f1e1d1c1b1a1918 + +xxgenpcvdm imm3 7f800000ff800000,ff8000007f800000 => f0e0d0c0b0a0908 0 +xxgenpcvdm imm3 ff8000007f800000,ff7ffffe7f7ffffe => 706050403020100 f0e0d0c0b0a0908 +xxgenpcvdm imm3 ff7ffffe7f7ffffe,0080000e8080000e => 706050403020100 0 +xxgenpcvdm imm3 0080000e8080000e,0180055e0180077e => 0 0 +xxgenpcvdm imm3 0180055e0180077e,0000111e8000222e => 0 0 +xxgenpcvdm imm3 0000111e8000222e,7ff0000000000000 => 0 0 +xxgenpcvdm imm3 7ff0000000000000,fff0000000000000 => f0e0d0c0b0a0908 0 +xxgenpcvdm imm3 fff0000000000000,2208400000000000 => 706050403020100 0 +xxgenpcvdm imm3 2208400000000000,0000000000000009 => 0 0 +xxgenpcvdm imm3 0000000000000009,ffff000180000001 => f0e0d0c0b0a0908 0 +xxgenpcvdm imm3 ffff000180000001,0000000000000000 => 706050403020100 0 +xxgenpcvdm imm3 0000000000000000,8000000000000000 => f0e0d0c0b0a0908 0 +xxgenpcvdm imm3 8000000000000000,7f800000ff800000 => 706050403020100 0 + +xxgenpcvhm imm0 7f800000ff800000,ff8000007f800000 => 18191a1b02031e1f 1121314151617 +xxgenpcvhm imm0 ff8000007f800000,ff7ffffe7f7ffffe => 6071a1b1c1d1e1f 1020314150405 +xxgenpcvhm imm0 ff7ffffe7f7ffffe,0080000e8080000e => 20304051c1d0607 1011121300011617 +xxgenpcvhm imm0 0080000e8080000e,0180055e0180077e => 18191a1b00011e1f 1011121314151617 +xxgenpcvhm imm0 0180055e0180077e,0000111e8000222e => 18191a1b1c1d1e1f 1011121300011617 +xxgenpcvhm imm0 0000111e8000222e,7ff0000000000000 => 18191a1b00011e1f 1011121314151617 +xxgenpcvhm imm0 7ff0000000000000,fff0000000000000 => 18191a1b1c1d1e1f 1121314151617 +xxgenpcvhm imm0 fff0000000000000,2208400000000000 => 11a1b1c1d1e1f 1011121314151617 +xxgenpcvhm imm0 2208400000000000,0000000000000009 => 18191a1b1c1d1e1f 1011121314151617 +xxgenpcvhm imm0 0000000000000009,ffff000180000001 => 18191a1b1c1d1e1f 1121302031617 +xxgenpcvhm imm0 ffff000180000001,0000000000000000 => 11a1b02031e1f 1011121314151617 +xxgenpcvhm imm0 0000000000000000,8000000000000000 => 18191a1b1c1d1e1f 1121314151617 +xxgenpcvhm imm0 8000000000000000,7f800000ff800000 => 2031a1b1c1d1e1f 1011121300011617 + +xxgenpcvhm imm1 7f800000ff800000,ff8000007f800000 => 0 10c0d00000000 +xxgenpcvhm imm1 ff8000007f800000,ff7ffffe7f7ffffe => 0 1020306070809 +xxgenpcvhm imm1 ff7ffffe7f7ffffe,0080000e8080000e => 0 40508090a0b0e0f +xxgenpcvhm imm1 0080000e8080000e,0180055e0180077e => 0 c0d000000000000 +xxgenpcvhm imm1 0180055e0180077e,0000111e8000222e => 0 405000000000000 +xxgenpcvhm imm1 0000111e8000222e,7ff0000000000000 => 0 c0d000000000000 +xxgenpcvhm imm1 7ff0000000000000,fff0000000000000 => 0 1000000000000 +xxgenpcvhm imm1 fff0000000000000,2208400000000000 => 0 809000000000000 +xxgenpcvhm imm1 2208400000000000,0000000000000009 => 0 0 +xxgenpcvhm imm1 0000000000000009,ffff000180000001 => 0 1040500000000 +xxgenpcvhm imm1 ffff000180000001,0000000000000000 => 0 8090c0d00000000 +xxgenpcvhm imm1 0000000000000000,8000000000000000 => 0 1000000000000 +xxgenpcvhm imm1 8000000000000000,7f800000ff800000 => 0 405080900000000 + +xxgenpcvhm imm2 7f800000ff800000,ff8000007f800000 => 1716151401001110 3021d1c1b1a1918 +xxgenpcvhm imm2 ff8000007f800000,ff7ffffe7f7ffffe => 100151413121110 70605041b1a0302 +xxgenpcvhm imm2 ff7ffffe7f7ffffe,0080000e8080000e => 504030213120100 1f1e1d1c07061918 +xxgenpcvhm imm2 0080000e8080000e,0180055e0180077e => 1716151401001110 1f1e1d1c1b1a1918 +xxgenpcvhm imm2 0180055e0180077e,0000111e8000222e => 1716151413121110 1f1e1d1c01001918 +xxgenpcvhm imm2 0000111e8000222e,7ff0000000000000 => 1716151401001110 1f1e1d1c1b1a1918 +xxgenpcvhm imm2 7ff0000000000000,fff0000000000000 => 1716151413121110 1001d1c1b1a1918 +xxgenpcvhm imm2 fff0000000000000,2208400000000000 => 100151413121110 1f1e1d1c1b1a1918 +xxgenpcvhm imm2 2208400000000000,0000000000000009 => 1716151413121110 1f1e1d1c1b1a1918 +xxgenpcvhm imm2 0000000000000009,ffff000180000001 => 1716151413121110 3021d1c01001918 +xxgenpcvhm imm2 ffff000180000001,0000000000000000 => 302151401001110 1f1e1d1c1b1a1918 +xxgenpcvhm imm2 0000000000000000,8000000000000000 => 1716151413121110 1001d1c1b1a1918 +xxgenpcvhm imm2 8000000000000000,7f800000ff800000 => 100151413121110 1f1e1d1c03021918 + +xxgenpcvhm imm3 7f800000ff800000,ff8000007f800000 => f0e0302 0 +xxgenpcvhm imm3 ff8000007f800000,ff7ffffe7f7ffffe => f0e0d0c09080706 0 +xxgenpcvhm imm3 ff7ffffe7f7ffffe,0080000e8080000e => b0a070605040100 0 +xxgenpcvhm imm3 0080000e8080000e,0180055e0180077e => 302 0 +xxgenpcvhm imm3 0180055e0180077e,0000111e8000222e => b0a 0 +xxgenpcvhm imm3 0000111e8000222e,7ff0000000000000 => 302 0 +xxgenpcvhm imm3 7ff0000000000000,fff0000000000000 => f0e 0 +xxgenpcvhm imm3 fff0000000000000,2208400000000000 => 706 0 +xxgenpcvhm imm3 2208400000000000,0000000000000009 => 0 0 +xxgenpcvhm imm3 0000000000000009,ffff000180000001 => f0e0b0a 0 +xxgenpcvhm imm3 ffff000180000001,0000000000000000 => 7060302 0 +xxgenpcvhm imm3 0000000000000000,8000000000000000 => f0e 0 +xxgenpcvhm imm3 8000000000000000,7f800000ff800000 => b0a0706 0 + +xxgenpcvwm imm0 7f800000ff800000,ff8000007f800000 => 18191a1b04050607 1020314151617 +xxgenpcvwm imm0 ff8000007f800000,ff7ffffe7f7ffffe => 40506071c1d1e1f 1020314151617 +xxgenpcvwm imm0 ff7ffffe7f7ffffe,0080000e8080000e => 40506071c1d1e1f 1011121300010203 +xxgenpcvwm imm0 0080000e8080000e,0180055e0180077e => 18191a1b00010203 1011121314151617 +xxgenpcvwm imm0 0180055e0180077e,0000111e8000222e => 18191a1b1c1d1e1f 1011121300010203 +xxgenpcvwm imm0 0000111e8000222e,7ff0000000000000 => 18191a1b00010203 1011121314151617 +xxgenpcvwm imm0 7ff0000000000000,fff0000000000000 => 18191a1b1c1d1e1f 1020314151617 +xxgenpcvwm imm0 fff0000000000000,2208400000000000 => 102031c1d1e1f 1011121314151617 +xxgenpcvwm imm0 2208400000000000,0000000000000009 => 18191a1b1c1d1e1f 1011121314151617 +xxgenpcvwm imm0 0000000000000009,ffff000180000001 => 18191a1b1c1d1e1f 1020304050607 +xxgenpcvwm imm0 ffff000180000001,0000000000000000 => 1020304050607 1011121314151617 +xxgenpcvwm imm0 0000000000000000,8000000000000000 => 18191a1b1c1d1e1f 1020314151617 +xxgenpcvwm imm0 8000000000000000,7f800000ff800000 => 40506071c1d1e1f 1011121300010203 + +xxgenpcvwm imm1 7f800000ff800000,ff8000007f800000 => 0 102030c0d0e0f +xxgenpcvwm imm1 ff8000007f800000,ff7ffffe7f7ffffe => 0 1020308090a0b +xxgenpcvwm imm1 ff7ffffe7f7ffffe,0080000e8080000e => 0 405060708090a0b +xxgenpcvwm imm1 0080000e8080000e,0180055e0180077e => 0 c0d0e0f00000000 +xxgenpcvwm imm1 0180055e0180077e,0000111e8000222e => 0 405060700000000 +xxgenpcvwm imm1 0000111e8000222e,7ff0000000000000 => 0 c0d0e0f00000000 +xxgenpcvwm imm1 7ff0000000000000,fff0000000000000 => 0 1020300000000 +xxgenpcvwm imm1 fff0000000000000,2208400000000000 => 0 8090a0b00000000 +xxgenpcvwm imm1 2208400000000000,0000000000000009 => 0 0 +xxgenpcvwm imm1 0000000000000009,ffff000180000001 => 0 1020304050607 +xxgenpcvwm imm1 ffff000180000001,0000000000000000 => 0 8090a0b0c0d0e0f +xxgenpcvwm imm1 0000000000000000,8000000000000000 => 0 1020300000000 +xxgenpcvwm imm1 8000000000000000,7f800000ff800000 => 0 405060708090a0b + +xxgenpcvwm imm2 7f800000ff800000,ff8000007f800000 => 1716151403020100 70605041b1a1918 +xxgenpcvwm imm2 ff8000007f800000,ff7ffffe7f7ffffe => 302010013121110 70605041b1a1918 +xxgenpcvwm imm2 ff7ffffe7f7ffffe,0080000e8080000e => 302010013121110 1f1e1d1c07060504 +xxgenpcvwm imm2 0080000e8080000e,0180055e0180077e => 1716151403020100 1f1e1d1c1b1a1918 +xxgenpcvwm imm2 0180055e0180077e,0000111e8000222e => 1716151413121110 1f1e1d1c03020100 +xxgenpcvwm imm2 0000111e8000222e,7ff0000000000000 => 1716151403020100 1f1e1d1c1b1a1918 +xxgenpcvwm imm2 7ff0000000000000,fff0000000000000 => 1716151413121110 30201001b1a1918 +xxgenpcvwm imm2 fff0000000000000,2208400000000000 => 302010013121110 1f1e1d1c1b1a1918 +xxgenpcvwm imm2 2208400000000000,0000000000000009 => 1716151413121110 1f1e1d1c1b1a1918 +xxgenpcvwm imm2 0000000000000009,ffff000180000001 => 1716151413121110 706050403020100 +xxgenpcvwm imm2 ffff000180000001,0000000000000000 => 706050403020100 1f1e1d1c1b1a1918 +xxgenpcvwm imm2 0000000000000000,8000000000000000 => 1716151413121110 30201001b1a1918 +xxgenpcvwm imm2 8000000000000000,7f800000ff800000 => 302010013121110 1f1e1d1c07060504 + +xxgenpcvwm imm3 7f800000ff800000,ff8000007f800000 => f0e0d0c03020100 0 +xxgenpcvwm imm3 ff8000007f800000,ff7ffffe7f7ffffe => f0e0d0c07060504 0 +xxgenpcvwm imm3 ff7ffffe7f7ffffe,0080000e8080000e => b0a090807060504 0 +xxgenpcvwm imm3 0080000e8080000e,0180055e0180077e => 3020100 0 +xxgenpcvwm imm3 0180055e0180077e,0000111e8000222e => b0a0908 0 +xxgenpcvwm imm3 0000111e8000222e,7ff0000000000000 => 3020100 0 +xxgenpcvwm imm3 7ff0000000000000,fff0000000000000 => f0e0d0c 0 +xxgenpcvwm imm3 fff0000000000000,2208400000000000 => 7060504 0 +xxgenpcvwm imm3 2208400000000000,0000000000000009 => 0 0 +xxgenpcvwm imm3 0000000000000009,ffff000180000001 => f0e0d0c0b0a0908 0 +xxgenpcvwm imm3 ffff000180000001,0000000000000000 => 706050403020100 0 +xxgenpcvwm imm3 0000000000000000,8000000000000000 => f0e0d0c 0 +xxgenpcvwm imm3 8000000000000000,7f800000ff800000 => b0a090807060504 0 + xxpermx imm0 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ffff0000ffff ffff0000ffff xxpermx imm0 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ffff0000ffff ffff0000ffff xxpermx imm0 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ffff0000ffff ffff0000ffff @@ -7094,4 +7318,4 @@ xxspltiw imm3 => 300000003 300000003 xxspltiw imm8 => 800000008 800000008 -All done. Tested 142 different instruction groups +All done. Tested 158 different instruction groups |
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From: Carl L. <ca...@so...> - 2021-03-30 16:13:19
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3cc0232c46a5905b4a6c2fbd302b58bf5f90b3d5 commit 3cc0232c46a5905b4a6c2fbd302b58bf5f90b3d5 Author: Carl Love <ce...@us...> Date: Mon Jan 11 16:00:57 2021 -0600 PPC64: ISA 3.1 VSX PCV Generate Operations xgenpcvbm VSX Vector Generate PCV from Byte Mask xxgenpcvdmVSX Vector Generate PCV from Doubleword Mask xxgenpcvhmVSX Vector Generate PCV from Halfword Mask xxgenpcvwmVSX Vector Generate PCV from Word Mask Diff: --- VEX/priv/guest_ppc_defs.h | 17 + VEX/priv/guest_ppc_helpers.c | 732 +++++++++++++++++++++++++++++++++++++++++++ VEX/priv/guest_ppc_toIR.c | 163 +++++++++- 3 files changed, 898 insertions(+), 14 deletions(-) diff --git a/VEX/priv/guest_ppc_defs.h b/VEX/priv/guest_ppc_defs.h index deda4dfcee..54ce923a9b 100644 --- a/VEX/priv/guest_ppc_defs.h +++ b/VEX/priv/guest_ppc_defs.h @@ -169,6 +169,23 @@ void write_ACC_entry (VexGuestPPC64State* gst, UInt offset, UInt acc, void get_ACC_entry (VexGuestPPC64State* gst, UInt offset, UInt acc, UInt reg, UInt *result); +extern void vector_gen_pvc_byte_mask_dirty_helper( VexGuestPPC64State* gst, + ULong src_hi, + ULong src_lo, + UInt rtn_val, UInt IMM ); +extern void vector_gen_pvc_hword_mask_dirty_helper( VexGuestPPC64State* gst, + ULong src_hi, + ULong src_lo, + UInt rtn_val, UInt IMM ); +extern void vector_gen_pvc_word_mask_dirty_helper( VexGuestPPC64State* gst, + ULong src_hi, + ULong src_lo, + UInt rtn_val, UInt IMM ); +extern void vector_gen_pvc_dword_mask_dirty_helper( VexGuestPPC64State* gst, + ULong src_hi, + ULong src_lo, + UInt rtn_val, UInt IMM ); + /* 8-bit XO value from instruction description */ #define XVI4GER8 0b00100011 #define XVI4GER8PP 0b00100010 diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c index c24191ef3c..75497abb96 100644 --- a/VEX/priv/guest_ppc_helpers.c +++ b/VEX/priv/guest_ppc_helpers.c @@ -701,6 +701,738 @@ ULong vector_evaluate64_helper( ULong srcA, ULong srcB, ULong srcC, #undef MAX_IMM_BITS } +/*--------------------------------------------------*/ +/*---- VSX Vector Generate PCV from Mask helpers ---*/ +/*--------------------------------------------------*/ +static void write_VSX_entry (VexGuestPPC64State* gst, UInt reg_offset, + ULong *vsx_entry) +{ + U128* pU128_dst; + pU128_dst = (U128*) (((UChar*) gst) + reg_offset); + + /* The U128 type is defined as an array of unsigned intetgers. */ + /* Writing in LE order */ + (*pU128_dst)[0] = (UInt)(vsx_entry[1] & 0xFFFFFFFF); + (*pU128_dst)[1] = (UInt)(vsx_entry[1] >> 32); + (*pU128_dst)[2] = (UInt)(vsx_entry[0] & 0xFFFFFFFF); + (*pU128_dst)[3] = (UInt)(vsx_entry[0] >> 32); + return; +} + +/* CALLED FROM GENERATED CODE */ +void vector_gen_pvc_byte_mask_dirty_helper( VexGuestPPC64State* gst, + ULong src_hi, ULong src_lo, + UInt reg_offset, UInt imm ) { + /* The function computes the 128-bit result then writes it directly + into the guest state VSX register. */ + + UInt i, shift_by, sel_shift_by, half_sel; + ULong index, src, result[2]; + ULong j; + + result[0] = 0; + result[1] = 0; + j = 0; + + /* The algorithm in the ISA is written with IBM numbering zero on left and + N-1 on right. The loop index is converted to "i" to match the algorithm + for claritiy of matching the C code to the algorithm in the ISA. */ + + if (imm == 0b00) { // big endian expansion + for( index = 0; index < 16; index++) { + i = 15 - index; + + shift_by = i*8; + + if ( i >= 8) { + src = src_hi; + shift_by = shift_by - 64; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = shift_by + 7; + + if ( ((src >> sel_shift_by) & 0x1) == 1) { + result[half_sel] |= j << shift_by; + j++; + } else { + result[half_sel] |= (index + (unsigned long long)0x10) << shift_by; + } + } + + + } else if (imm == 0b01) { // big endian compression + /* If IMM=0b00001, let pcv be the permute control vector required to + enable a left-indexed permute (vperm or xxperm) to implement a + compression of the sparse byte elements in a source vector specified + by the byte-element mask in VSR[VRB+32] into the leftmost byte + elements of a result vector. + */ + for( index = 0; index < 16; index++) { + i = 15 - index; + shift_by = i*8; + + if ( i >= 8) { + src = src_hi; + shift_by = shift_by - 64; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = shift_by + 7; + + if ( ((src >> sel_shift_by) & 0x1) == 1) { + if (j >= 8) + result[1] |= (index) << (15 - j)*8; + else + result[0] |= (index) << (7 - j)*8; + j++; + } + } + /* The algorithim says set to undefined, leave as 0 + for( index = 3 - j; index < 4; index++) { + result |= (0 << (index*8)); + } + */ + + } else if (imm == 0b10) { //little-endian expansion + /* If IMM=0b00010, let pcv be the permute control vector required to + enable a right-indexed permute (vpermr or xxpermr) to implement an + expansion of the rightmost byte elements of a source vector into the + byte elements of a result vector specified by the byte-element mask + in VSR[VRB+32]. */ + for( index = 0; index < 16; index++) { + i = index; + + shift_by = i*8; + + if ( i >= 8) { + src = src_hi; + shift_by = shift_by - 64; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = shift_by + 7; + + /* mod shift amount by 8 since src is either the upper or lower + 64-bits. */ + if ( ((src >> sel_shift_by) & 0x1) == 1) { + result[half_sel] |= j << shift_by; + j++; + } else { + result[half_sel] |= (index + (unsigned long long)0x10) << shift_by; + } + } + + } else if (imm == 0b11) { //little-endian compression + /* If IMM=0b00011, let pcv be the permute control vector required to + enable a right-indexed permute (vpermr or xxpermr) to implement a + compression of the sparse byte elements in a source vector specified + by the byte-element mask in VSR[VRB+32] into the rightmost byte + elements of a result vector. */ + + for( index = 0; index < 16; index++) { + i = index; + + shift_by = i*8; + + if ( i >= 8) { + src = src_hi; + shift_by = shift_by - 64; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = shift_by + 7; + + if ( ((src >> sel_shift_by) & 0x1) == 1) { + if (j >= 8) + result[0] |= (index) << (j-8)*8; + else + result[1] |= (index) << j*8; + j++; + } + } + + /* The algorithim says set to undefined, leave as 0 + for( index = 3 - j; index < 4; index++) { + result |= (0 << (index*8)); + } + */ + + } else { + vex_printf("ERROR, vector_gen_pvc_byte_mask_dirty_helper, imm value %u not supported.\n", + imm); + vassert(0); + } + write_VSX_entry( gst, reg_offset, result); +} + +/* CALLED FROM GENERATED CODE */ +void vector_gen_pvc_hword_mask_dirty_helper( VexGuestPPC64State* gst, + ULong src_hi, ULong src_lo, + UInt reg_offset, + UInt imm ) { + /* The function computes the 128-bit result then writes it directly + into the guest state VSX register. */ + UInt i, shift_by, sel_shift_by, half_sel; + ULong index, src, result[2]; + ULong j; + + result[0] = 0; + result[1] = 0; + j = 0; + + /* The algorithm in the ISA is written with IBM numbering zero on left and + N-1 on right. The loop index is converted to "i" to match the algorithm + for claritiy of matching the C code to the algorithm in the ISA. */ + + if (imm == 0b00) { // big endian expansion + /* If IMM=0b00000, let pcv be the permute control vector required to + enable a left-indexed permute (vperm or xxperm) to implement an + expansion of the leftmost halfword elements of a source vector into + the halfword elements of a result vector specified by the halfword- + element mask in VSR[VRB+32]. + */ + for( index = 0; index < 8; index++) { + i = 7 - index; + + shift_by = i*16; + + if ( i >= 4) { + src = src_hi; + shift_by = shift_by - 64; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = shift_by + 15; + + if ( ((src >> sel_shift_by) & 0x1) == 1) { + // half-word i, byte 0 + result[half_sel] |= (2*j + 0x0) << (shift_by+8); + // half-word i, byte 1 + result[half_sel] |= (2*j + 0x1) << shift_by; + j++; + } else { + result[half_sel] |= (2*index + 0x10) << (shift_by+8); + result[half_sel] |= (2*index + 0x11) << shift_by; + } + } + + } else if (imm == 0b01) { // big endian expansion + /* If IMM=0b00001,let pcv be the permute control vector required to + enable a left-indexed permute (vperm or xxperm) to implement a + compression of the sparse halfword elements in a source vector + specified by the halfword-element mask in VSR[VRB+32] into the + leftmost halfword elements of a result vector. + */ + for( index = 0; index < 8; index++) { + i = 7 - index; + + shift_by = i*16; + + if ( i >= 4) { + src = src_hi; + shift_by = shift_by - 64; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = shift_by + 15; + + if ( ((src >> sel_shift_by) & 0x1) == 1) { + if (j >= 4) { + // half-word i, byte 0 + result[1] |= (2*index + 0x0) << ((7 - j)*16 + 8); + // half-word i, byte 1 + result[1] |= (2*index + 0x1) << ((7 - j)*16); + } else { + // half-word i, byte 0 + result[0] |= (2*index + 0x0) << ((3 - j)*16 + 8); + // half-word i, byte 1 + result[0] |= (2*index + 0x1) << ((3 - j)*16); + } + j++; + } + } + + } else if (imm == 0b10) { //little-endian expansion + /* If IMM=0b00010, let pcv be the permute control vector required to + enable a right-indexed permute (vpermr or xxpermr) to implement an + expansion of the rightmost halfword elements of a source vector into + the halfword elements of a result vector specified by the halfword- + element mask in VSR[VRB+32]. + */ + for( index = 0; index < 8; index++) { + i = index; + shift_by = i*16; + + if ( i >= 4) { + src = src_hi; + shift_by = shift_by - 64; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = shift_by + 15; + + if ( ((src >> sel_shift_by) & 0x1) == 1) { + // half-word i, byte 0 + result[half_sel] |= (2*j + 0x00) << shift_by; + // half-word i, byte 1 + result[half_sel] |= (2*j + 0x01) << (shift_by+8); + j++; + + } else { + // half-word i, byte 0 + result[half_sel] |= (2*index + 0x10) << shift_by; + // half-word i, byte 1 + result[half_sel] |= (2*index + 0x11) << (shift_by+8); + } + } + + } else if (imm == 0b11) { //little-endian compression + /* If IMM=0b00011, let pcv be the permute control vector required to + enable a right-indexed permute (vpermr or xxpermr) to implement a + compression of the sparse halfword elements in a source vector + specified by the halfword-element mask in VSR[VRB+32] into the + rightmost halfword elements of a result vector. */ + for( index = 0; index < 8; index++) { + i = index; + shift_by = i*16; + + if ( i >= 4) { + src = src_hi; + shift_by = shift_by - 64; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = shift_by + 15; + + if ( ((src >> sel_shift_by) & 0x1) == 1) { + if (j >= 4) { + // half-word j, byte 0 + result[0] |= (2*index + 0x0) << ((j-4)*16); + // half-word j, byte 1 + result[0] |= (2*index + 0x1) << ((j-4)*16+8); + } else { + // half-word j, byte 0 + result[1] |= (2*index + 0x0) << (j*16); + // half-word j, byte 1 + result[1] |= (2*index + 0x1) << ((j*16)+8); + } + j++; + } + } + + } else { + vex_printf("ERROR, vector_gen_pvc_hword_dirty_mask_helper, imm value %u not supported.\n", + imm); + vassert(0); + } + write_VSX_entry( gst, reg_offset, result); +} + +/* CALLED FROM GENERATED CODE */ +void vector_gen_pvc_word_mask_dirty_helper( VexGuestPPC64State* gst, + ULong src_hi, ULong src_lo, + UInt reg_offset, UInt imm ) { + /* The function computes the 128-bit result then writes it directly + into the guest state VSX register. */ + UInt i, shift_by, sel_shift_by, half_sel; + ULong index, src, result[2]; + ULong j; + + result[0] = 0; + result[1] = 0; + j = 0; + + /* The algorithm in the ISA is written with IBM numbering zero on left and + N-1 on right. The loop index is converted to "i" to match the algorithm + for claritiy of matching the C code to the algorithm in the ISA. */ + + if (imm == 0b00) { // big endian expansion + /* If IMM=0b00000, let pcv be the permute control vector required to + enable a left-indexed permute (vperm or xxperm) to implement an + expansion of the leftmost word elements of a source vector into the + word elements of a result vector specified by the word-element mask + in VSR[VRB+32]. + */ + for( index = 0; index < 4; index++) { + i = 3 - index; + + shift_by = i*32; + + if ( i >= 2) { + src = src_hi; + shift_by = shift_by - 64; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = shift_by + 31; + + if ( ((src >> sel_shift_by) & 0x1) == 1) { + result[half_sel] |= (4*j+0) << (shift_by+24); // word i, byte 0 + result[half_sel] |= (4*j+1) << (shift_by+16); // word i, byte 1 + result[half_sel] |= (4*j+2) << (shift_by+8); // word i, byte 2 + result[half_sel] |= (4*j+3) << shift_by; // word i, byte 3 + j++; + } else { + result[half_sel] |= (4*index + 0x10) << (shift_by+24); + result[half_sel] |= (4*index + 0x11) << (shift_by+16); + result[half_sel] |= (4*index + 0x12) << (shift_by+8); + result[half_sel] |= (4*index + 0x13) << shift_by; + } + } + + } else if (imm == 0b01) { // big endian compression + /* If IMM=0b00001, let pcv be the permute control vector required to + enable a left-indexed permute (vperm or xxperm) to implement a + compression of the sparse word elements in a source vector specified + by the word-element mask in VSR[VRB+32] into the leftmost word + elements of a result vector. + */ + for( index = 0; index < 4; index++) { + i = 3 - index; + + shift_by = i*32; + + if ( i >= 2) { + src = src_hi; + shift_by = shift_by - 64; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = shift_by + 31; + + if (((src >> sel_shift_by) & 0x1) == 1) { + if (j >= 2) { + // word j, byte 0 + result[1] |= (4*index+0) << ((3 - j)*32 + 24); + // word j, byte 1 + result[1] |= (4*index+1) << ((3 - j)*32 + 16); + // word j, byte 2 + result[1] |= (4*index+2) << ((3 - j)*32 + 8); + // word j, byte 3 + result[1] |= (4*index+3) << ((3 - j)*32 + 0); + } else { + result[0] |= (4*index+0) << ((1 - j)*32 + 24); + result[0] |= (4*index+1) << ((1 - j)*32 + 16); + result[0] |= (4*index+2) << ((1 - j)*32 + 8); + result[0] |= (4*index+3) << ((1 - j)*32 + 0); + } + j++; + } + } + + } else if (imm == 0b10) { //little-endian expansion + /* If IMM=0b00010, let pcv be the permute control vector required to + enable a right-indexed permute (vpermr or xxpermr) to implement an + expansion of the rightmost word elements of a source vector into the + word elements of a result vector specified by the word-element mask + in VSR[VRB+32]. + */ + for( index = 0; index < 4; index++) { + i = index; + + shift_by = i*32; + + if ( i >= 2) { + src = src_hi; + shift_by = shift_by - 64; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = shift_by + 31; + + if (((src >> sel_shift_by) & 0x1) == 1) { + result[half_sel] |= (4*j+0) << (shift_by + 0); // word j, byte 0 + result[half_sel] |= (4*j+1) << (shift_by + 8); // word j, byte 1 + result[half_sel] |= (4*j+2) << (shift_by + 16); // word j, byte 2 + result[half_sel] |= (4*j+3) << (shift_by + 24); // word j, byte 3 + j++; + } else { + result[half_sel] |= (4*index + 0x10) << (shift_by + 0); + result[half_sel] |= (4*index + 0x11) << (shift_by + 8); + result[half_sel] |= (4*index + 0x12) << (shift_by + 16); + result[half_sel] |= (4*index + 0x13) << (shift_by + 24); + } + } + + } else if (imm == 0b11) { //little-endian compression + /* If IMM=0b00011, let pcv be the permute control vector required to + enable a right-indexed permute (vpermr or xxpermr) to implement a + compression of the sparse word elements in a source vector specified + by the word-element mask in VSR[VRB+32] into the rightmost word + elements of a result vector. */ + for( index = 0; index < 4; index++) { + i =index; + + shift_by = i*32; + + if ( i >= 2) { + src = src_hi; + shift_by = shift_by - 64; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = shift_by + 31; + + if (((src >> sel_shift_by) & 0x1) == 1) { + if (j >= 2){ + // word j, byte 0 + result[0] |= (4*index + 0x0) << ((j-2)*32+0); + // word j, byte 1 + result[0] |= (4*index + 0x1) << ((j-2)*32+8); + // word j, byte 2 + result[0] |= (4*index + 0x2) << ((j-2)*32+16); + // word j, byte 3 + result[0] |= (4*index + 0x3) << ((j-2)*32+24); + } else { + result[1] |= (4*index + 0x0) << (j*32+0); + result[1] |= (4*index + 0x1) << (j*32+8); + result[1] |= (4*index + 0x2) << (j*32+16); + result[1] |= (4*index + 0x3) << (j*32+24); + } + j++; + } + } + } else { + vex_printf("ERROR, vector_gen_pvc_word_mask_dirty_helper, imm value %u not supported.\n", + imm); + vassert(0); + } + + write_VSX_entry( gst, reg_offset, result); +} + +/* CALLED FROM GENERATED CODE */ +void vector_gen_pvc_dword_mask_dirty_helper( VexGuestPPC64State* gst, + ULong src_hi, ULong src_lo, + UInt reg_offset, UInt imm ) { + /* The function computes the 128-bit result then writes it directly + into the guest state VSX register. */ + UInt sel_shift_by, half_sel; + ULong index, src, result[2]; + ULong j, i; + + result[0] = 0; + result[1] = 0; + j = 0; + + /* The algorithm in the ISA is written with IBM numbering zero on left and + N-1 on right. The loop index is converted to "i" to match the algorithm + for claritiy of matching the C code to the algorithm in the ISA. */ + + if (imm == 0b00) { // big endian expansion + /* If IMM=0b00000, let pcv be the permute control vector required to + enable a left-indexed permute (vperm or xxperm) to implement an + expansion of the leftmost doubleword elements of a source vector into + the doubleword elements of a result vector specified by the + doubleword-element mask in VSR[VRB+32]. + */ + for( index = 0; index < 2; index++) { + i = 1 - index; + + if ( i == 1) { + src = src_hi; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = 63; + + if ( ((src >> sel_shift_by) & 0x1) == 1) { + result[half_sel] |= (8*j + 0x0) << 56; // dword i, byte 0 + result[half_sel] |= (8*j + 0x1) << 48; // dword i, byte 1 + result[half_sel] |= (8*j + 0x2) << 40; // dword i, byte 2 + result[half_sel] |= (8*j + 0x3) << 32; // dword i, byte 3 + result[half_sel] |= (8*j + 0x4) << 24; // dword i, byte 4 + result[half_sel] |= (8*j + 0x5) << 16; // dword i, byte 5 + result[half_sel] |= (8*j + 0x6) << 8; // dword i, byte 6 + result[half_sel] |= (8*j + 0x7) << 0; // dword i, byte 7 + j++; + } else { + result[half_sel] |= (8*index + 0x10) << 56; + result[half_sel] |= (8*index + 0x11) << 48; + result[half_sel] |= (8*index + 0x12) << 40; + result[half_sel] |= (8*index + 0x13) << 32; + result[half_sel] |= (8*index + 0x14) << 24; + result[half_sel] |= (8*index + 0x15) << 16; + result[half_sel] |= (8*index + 0x16) << 8; + result[half_sel] |= (8*index + 0x17) << 0; + } + } + } else if (imm == 0b01) { // big endian compression + /* If IMM=0b00001, let pcv be the the permute control vector required to + enable a left-indexed permute (vperm or xxperm) to implement a + compression of the sparse doubleword elements in a source vector + specified by the doubleword-element mask in VSR[VRB+32] into the + leftmost doubleword elements of a result vector. + */ + for( index = 0; index < 2; index++) { + i = 1 - index; + + if ( i == 1) { + src = src_hi; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = 63; + + if ( ((src >> sel_shift_by) & 0x1) == 1) { + if (j == 1) { + result[1] |= (8*index + 0x0) << 56; // double-word j, byte 0 + result[1] |= (8*index + 0x1) << 48; // double-word j, byte 1 + result[1] |= (8*index + 0x2) << 40; // double-word j, byte 2 + result[1] |= (8*index + 0x3) << 32; // double-word j, byte 3 + result[1] |= (8*index + 0x4) << 24; // double-word j, byte 4 + result[1] |= (8*index + 0x5) << 16; // double-word j, byte 5 + result[1] |= (8*index + 0x6) << 8; // double-word j, byte 6 + result[1] |= (8*index + 0x7) << 0; // double-word j, byte 7 + } else { + result[0] |= (8*index + 0x0) << 56; // double-word j, byte 0 + result[0] |= (8*index + 0x1) << 48; // double-word j, byte 1 + result[0] |= (8*index + 0x2) << 40; // double-word j, byte 2 + result[0] |= (8*index + 0x3) << 32; // double-word j, byte 3 + result[0] |= (8*index + 0x4) << 24; // double-word j, byte 4 + result[0] |= (8*index + 0x5) << 16; // double-word j, byte 5 + result[0] |= (8*index + 0x6) << 8; // double-word j, byte 6 + result[0] |= (8*index + 0x7) << 0; // double-word j, byte 7 + } + j++; + } + } + } else if (imm == 0b10) { //little-endian expansion + /* If IMM=0b00010, let pcv be the permute control vector required to + enable a right-indexed permute (vpermr or xxpermr) to implement an + expansion of the rightmost doubleword elements of a source vector + into the doubleword elements of a result vector specified by the + doubleword-element mask in VSR[VRB+32]. + */ + + for( index = 0; index < 2; index++) { + i = index; + + if ( i == 1) { + src = src_hi; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = 63; + + if ( ((src >> sel_shift_by) & 0x1) == 1) { + result[half_sel] |= (8*j+0) << 0; // double-word i, byte 0 + result[half_sel] |= (8*j+1) << 8; // double-word i, byte 1 + result[half_sel] |= (8*j+2) << 16; // double-word i, byte 2 + result[half_sel] |= (8*j+3) << 24; // double-word i, byte 3 + result[half_sel] |= (8*j+4) << 32; // double-word i, byte 4 + result[half_sel] |= (8*j+5) << 40; // double-word i, byte 5 + result[half_sel] |= (8*j+6) << 48; // double-word i, byte 6 + result[half_sel] |= (8*j+7) << 56; // double-word i, byte 7 + j++; + } else { + result[half_sel] |= (8*index + 0x10) << 0; + result[half_sel] |= (8*index + 0x11) << 8; + result[half_sel] |= (8*index + 0x12) << 16; + result[half_sel] |= (8*index + 0x13) << 24; + result[half_sel] |= (8*index + 0x14) << 32; + result[half_sel] |= (8*index + 0x15) << 40; + result[half_sel] |= (8*index + 0x16) << 48; + result[half_sel] |= (8*index + 0x17) << 56; + } + } + + } else if (imm == 0b11) { //little-endian compression + /* If IMM=0b00011, let pcv be the permute control vector required to + enable a right-indexed permute (vpermr or xxpermr) to implement a + compression of the sparse doubleword elements in a source vector + specified by the doubleword-element mask in VSR[VRB+32] into the + rightmost doubleword elements of a result vector. */ + for( index = 0; index < 2; index++) { + i = index; + + if ( i == 1) { + src = src_hi; + half_sel = 0; + } else { + src = src_lo; + half_sel = 1; + } + + sel_shift_by = 63; + + if (((src >> sel_shift_by) & 0x1) == 1) { + if (j == 1) { + result[0] |= (8*index + 0x0) << 0; // double-word j, byte 0 + result[0] |= (8*index + 0x1) << 8; // double-word j, byte 1 + result[0] |= (8*index + 0x2) << 16; // double-word j, byte 2 + result[0] |= (8*index + 0x3) << 24; // double-word j, byte 3 + result[0] |= (8*index + 0x4) << 32; // double-word j, byte 4 + result[0] |= (8*index + 0x5) << 40; // double-word j, byte 5 + result[0] |= (8*index + 0x6) << 48; // double-word j, byte 6 + result[0] |= (8*index + 0x7) << 56; // double-word j, byte 7 + } else { + result[1] |= (8*index + 0x0) << 0; + result[1] |= (8*index + 0x1) << 8; + result[1] |= (8*index + 0x2) << 16; + result[1] |= (8*index + 0x3) << 24; + result[1] |= (8*index + 0x4) << 32; + result[1] |= (8*index + 0x5) << 40; + result[1] |= (8*index + 0x6) << 48; + result[1] |= (8*index + 0x7) << 56; + } + j++; + } + } + } else { + vex_printf("ERROR, vector_gen_pvc_dword_mask_helper, imm value %u not supported.\n", + imm); + vassert(0); + } + + write_VSX_entry( gst, reg_offset, result); +} /*------------------------------------------------*/ /*---- VSX Matrix signed integer GER functions ---*/ diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index bcabf69dd7..354be6b53d 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -3322,6 +3322,7 @@ static IRExpr * locate_vector_ele_eq ( IRTemp src, IRExpr *value, #define DFORM_IMMASK 0xffffffff #define DSFORM_IMMASK 0xfffffffc #define DQFORM_IMMASK 0xfffffff0 +#define DA8LSFORM_IMMASK 0x3fffffff // Algebraic 8LS Dform #define ISA_3_1_PREFIX_CHECK if (prefix) {if (!allow_isa_3_1) goto decode_noIsa3_1;} @@ -6109,6 +6110,87 @@ static void vsx_matrix_64bit_float_ger ( const VexAbiInfo* vbi, stmt( IRStmt_Dirty(d) ); } +static void vector_gen_pvc_mask ( const VexAbiInfo* vbi, + IRExpr *src, UInt IMM, + UInt opc2, UInt VSX_addr ) { + /* The function takes a 64-bit source and an immediate value. The function + calls a helper to execute the xxgenpcvbm, xxgenpcvhm, xxgenpcvwm, + xxgenpcvdm instruction. The instructions are not practical to do with + Iops. The instruction is implemented with a dirty helper that + calculates the 128-bit result and writes it directly into the guest + state VSX register. + */ + IRTemp src_hi = newTemp( Ity_I64); + IRTemp src_lo = newTemp( Ity_I64); + + IRDirty* d; + + vassert( (VSX_addr >= 0) && (VSX_addr < 64) ); + UInt reg_offset = offsetofPPCGuestState( guest_VSR0 ) + + sizeof(U128) * VSX_addr; + + assign( src_hi, unop( Iop_V128HIto64, src ) ); + assign( src_lo, unop( Iop_V128to64, src ) ); + + IRExpr** args = mkIRExprVec_5( + IRExpr_GSPTR(), + mkexpr( src_hi ), + mkexpr( src_lo ), + mkU32( reg_offset ), + mkU64( IMM ) ); + + switch( opc2 ) { + case 0x394: // xxgenpcvbm + d = unsafeIRDirty_0_N ( + 0 /*regparms*/, + "vector_gen_pvc_byte_mask_dirty_helper", + fnptr_to_fnentry( vbi, + &vector_gen_pvc_byte_mask_dirty_helper ), + args); + break; + + case 0x395: // xxgenpcvhm + d = unsafeIRDirty_0_N ( + 0 /*regparms*/, + "vector_gen_pvc_hword_mask_dirty_helper", + fnptr_to_fnentry( vbi, + &vector_gen_pvc_hword_mask_dirty_helper ), + args); + break; + + case 0x3B4: // xxgenpcvwm + d = unsafeIRDirty_0_N ( + 0 /*regparms*/, + "vector_gen_pvc_word_mask_dirty_helper", + fnptr_to_fnentry( vbi, + &vector_gen_pvc_word_mask_dirty_helper ), + args); + break; + + case 0x3B5: // xxgenpcvdm + d = unsafeIRDirty_0_N ( + 0 /*regparms*/, + "vector_gen_pvc_dword_mask_dirty_helper", + fnptr_to_fnentry( vbi, + &vector_gen_pvc_dword_mask_dirty_helper ), + args); + break; + default: + vex_printf("ERROR: Unkown instruction = %u in vector_gen_pvc_mask()\n", + opc2); + return; + } + + d->nFxState = 1; + vex_bzero(&d->fxState, sizeof(d->fxState)); + d->fxState[0].fx = Ifx_Modify; + d->fxState[0].size = sizeof(U128); + d->fxState[0].offset = reg_offset; + + /* execute the dirty call, side-effecting guest state */ + stmt( IRStmt_Dirty(d) ); +} + static IRExpr * UNSIGNED_CMP_GT_V128 ( IRExpr *vA, IRExpr *vB ) { /* This function does an unsigned compare of two V128 values. The * function is for use in 32-bit mode only as it is expensive. The @@ -35227,6 +35309,54 @@ static Bool dis_vsx_accumulator_prefix ( UInt prefix, UInt theInstr, return True; } +static Bool dis_vector_generate_pvc_from_mask ( UInt prefix, + UInt theInstr, + const VexAbiInfo* vbi ) +{ + UChar XT_addr = ifieldRegXT(theInstr); + UChar vB_addr = ifieldRegB(theInstr); + IRTemp vB = newTemp( Ity_V128 ); + UInt opc2 = ifieldOPClo10(theInstr); + UInt IMM = IFIELD(theInstr, (31-15), 5); // bits[11:15] + + assign( vB, getVReg( vB_addr ) ); + + switch( opc2 ) { + case 0x394: + DIP("xxgenpcvbm v%u,v%u,%u\n", XT_addr, vB_addr, IMM); + /* vector_gen_pvc_mask uses a dirty helper to calculate the result and + write it to the VSX result register. */ + vector_gen_pvc_mask( vbi, mkexpr( vB ), IMM, opc2, XT_addr ); + break; + + case 0x395: + DIP("xxgenpcvhm v%u,v%u,%u\n", XT_addr, vB_addr, IMM); + /* vector_gen_pvc_mask uses a dirty helper to calculate the result and + write it to the VSX result register. */ + vector_gen_pvc_mask( vbi, mkexpr( vB ), IMM, opc2, XT_addr ); + break; + + case 0x3B4: + DIP("xxgenpcvwm v%u,v%u,%u\n", XT_addr, vB_addr, IMM); + /* vector_gen_pvc_mask uses a dirty helper to calculate the result and + write it to the VSX result register. */ + vector_gen_pvc_mask( vbi, mkexpr( vB ), IMM, opc2, XT_addr ); + break; + + case 0x3B5: + DIP("xxgenpcvdm v%u,v%u,%u\n", XT_addr, vB_addr, IMM); + /* vector_gen_pvc_mask uses a dirty helper to calculate the result and + write it to the VSX result register. */ + vector_gen_pvc_mask( vbi, mkexpr( vB ), IMM, opc2, XT_addr ); + break; + + default: + return False; + } + + return True; +} + static Int dis_nop_prefix ( UInt prefix, UInt theInstr ) { Bool is_prefix = prefix_instruction( prefix ); @@ -35748,14 +35878,9 @@ DisResult disInstr_PPC_WRK ( } goto decode_failure; - case 0x31: // lfsu, stxv + case 0x31: // lfsu if (!allow_F) goto decode_noF; - if (prefix_instruction( prefix )) { // stxv - if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; - if (dis_fp_pair_prefix( prefix, theInstr )) goto decode_success; - } else { // lfsu - if (dis_fp_load( prefix, theInstr )) goto decode_success; - } + if (dis_fp_load( prefix, theInstr )) goto decode_success; goto decode_failure; case 0x32: @@ -35842,7 +35967,6 @@ DisResult disInstr_PPC_WRK ( case 0x39: // pld, lxsd, lxssp, lfdp { UInt opc2tmp = ifieldOPC0o2(theInstr); - if (!allow_F) goto decode_noF; if (prefix_instruction( prefix )) { // pld if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; @@ -36125,12 +36249,6 @@ DisResult disInstr_PPC_WRK ( goto decode_failure; } - /* The vsxOpc2 returned is the "normalized" value, representing the - * instructions secondary opcode as taken from the standard secondary - * opcode field [21:30] (IBM notatition), even if the actual field - * is non-standard. These normalized values are given in the opcode - * appendices of the ISA 2.06 document. - */ if ( ( opc2 == 0x168 ) && ( IFIELD( theInstr, 19, 2 ) == 0 ) )// xxspltib { /* This is a special case of the XX1 form where the RA, RB @@ -36153,6 +36271,23 @@ DisResult disInstr_PPC_WRK ( goto decode_failure; } + if ( ( opc2 == 0x394 ) || // xxgenpcvbm + ( opc2 == 0x395 ) || // xxgenpcvwm + ( opc2 == 0x3B4 ) || // xxgenpcvhm + ( opc2 == 0x3B5 ) ) { // xxgenpcvdm + if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; + if (dis_vector_generate_pvc_from_mask( prefix, theInstr, + abiinfo )) + goto decode_success; + goto decode_failure; + } + + /* The vsxOpc2 returned is the "normalized" value, representing the + * instructions secondary opcode as taken from the standard secondary + * opcode field [21:30] (IBM notatition), even if the actual field + * is non-standard. These normalized values are given in the opcode + * appendices of the ISA 2.06 document. + */ vsxOpc2 = get_VSX60_opc2(opc2, theInstr); switch (vsxOpc2) { |