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From: Mark W. <ma...@so...> - 2021-02-12 19:47:29
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e2e830f61271c28dddfa6b478044870d2188cf57 commit e2e830f61271c28dddfa6b478044870d2188cf57 Author: Mark Wielaard <ma...@kl...> Date: Fri Feb 12 20:42:00 2021 +0100 PR432809 VEX should support REX.W + POPF It seems a REX.W prefix simply explicitly sets the operant size to 8, and so can/must be ignored as redundant. This is what we already do for PUSH, POP and PUSHF. All instructions are described as "When in 64-bit mode, instruction defaults to 64-bit operand size and cannot encode 32-bit operand size." in the instruction manual. Original patch and analysis by Mike Dalessio <mik...@gm...> https://bugs.kde.org/show_bug.cgi?id=432809 Diff: --- NEWS | 1 + VEX/priv/guest_amd64_toIR.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/NEWS b/NEWS index dbe029ecea..eafe0cb009 100644 --- a/NEWS +++ b/NEWS @@ -88,6 +88,7 @@ n-i-bz helgrind: If hg_cli__realloc fails, return NULL. 430354 ppc stxsibx and stxsihx instructions write too much data 430485 expr_is_guardable doesn't handle Iex_Qop 432672 vg_regtest: test-specific environment variables not reset between tests +432809 VEX should support REX.W + POPF 432861 PPC modsw and modsd give incorrect results for 1 mod 12 Release 3.16.1 (?? June 2020) diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c index 2faca7d03f..30487065d7 100644 --- a/VEX/priv/guest_amd64_toIR.c +++ b/VEX/priv/guest_amd64_toIR.c @@ -20586,7 +20586,7 @@ Long dis_ESC_NONE ( /* Note. There is no encoding for a 32-bit popf in 64-bit mode. So sz==4 actually means sz==8. */ if (haveF2orF3(pfx)) goto decode_failure; - vassert(sz == 2 || sz == 4); + vassert(sz == 2 || sz == 4 || sz == 8); if (sz == 4) sz = 8; if (sz != 8) goto decode_failure; // until we know a sz==2 test case exists t1 = newTemp(Ity_I64); t2 = newTemp(Ity_I64); |
|
From: Carl L. <ca...@so...> - 2021-02-12 17:02:30
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=b4eff82004077b5628e9c0958121fe6156c29664 commit b4eff82004077b5628e9c0958121fe6156c29664 Author: Carl Love <ce...@us...> Date: Wed Feb 10 21:04:22 2021 -0600 PPC, modsw and modsd instruction fix Diff: --- NEWS | 1 + VEX/priv/guest_ppc_toIR.c | 144 ++-- none/tests/ppc64/Makefile.am | 4 +- none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE | 2 +- none/tests/ppc64/test_mod_instructions.c | 251 +++++++ none/tests/ppc64/test_mod_instructions.stderr.exp | 2 + none/tests/ppc64/test_mod_instructions.stdout.exp | 824 ++++++++++++++++++++++ none/tests/ppc64/test_mod_instructions.vgtest | 2 + 8 files changed, 1162 insertions(+), 68 deletions(-) diff --git a/NEWS b/NEWS index 3e0f5a0bd3..dbe029ecea 100644 --- a/NEWS +++ b/NEWS @@ -88,6 +88,7 @@ n-i-bz helgrind: If hg_cli__realloc fails, return NULL. 430354 ppc stxsibx and stxsihx instructions write too much data 430485 expr_is_guardable doesn't handle Iex_Qop 432672 vg_regtest: test-specific environment variables not reset between tests +432861 PPC modsw and modsd give incorrect results for 1 mod 12 Release 3.16.1 (?? June 2020) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 3d4833d96a..880a47ebb2 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -7453,14 +7453,13 @@ static Bool dis_modulo_int ( UInt prefix, UInt theInstr ) IRTemp rB = newTemp( Ity_I64 ); IRTemp rA2_63 = newTemp( Ity_I64 ); /* all 1's if rA != -2^63 */ IRTemp rB_0 = newTemp( Ity_I1 ); /* 1 if rB = 0 */ - IRTemp rB_1 = newTemp( Ity_I1 ); /* 1 if rB = -1 */ - IRTemp rA_1 = newTemp( Ity_I1 ); /* 1 if rA = -1 */ + IRTemp rB_1 = newTemp( Ity_I1 ); /* 1 if rB = 1 */ + IRTemp rB_m1 = newTemp( Ity_I1 ); /* 1 if rB = -1 */ + IRTemp rA_m1 = newTemp( Ity_I1 ); /* 1 if rA = -1 */ IRTemp resultis0 = newTemp( Ity_I64 ); - IRTemp resultisF = newTemp( Ity_I64 ); IRTemp quotient = newTemp( Ity_I64 ); IRTemp quotientTimesDivisor = newTemp( Ity_I64 ); IRTemp remainder = newTemp( Ity_I64 ); - IRTemp tmp = newTemp( Ity_I64 ); DIP("modsd r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); @@ -7477,30 +7476,46 @@ static Bool dis_modulo_int ( UInt prefix, UInt theInstr ) assign( rB_1, binop( Iop_CmpEQ64, mkexpr( rB ), - mkU64( 0xFFFFFFFFFFFFFFFF ) ) ); + mkU64( 0x1 ) ) ); + + assign( rB_m1, binop( Iop_CmpEQ64, + mkexpr( rB ), + mkU64( 0xFFFFFFFFFFFFFFFF ) ) ); - assign( rA_1, binop( Iop_CmpEQ64, + assign( rA_m1, binop( Iop_CmpEQ64, mkexpr( rA ), mkU64( 0xFFFFFFFFFFFFFFFF ) ) ); /* Need to match the HW for these special cases - * rA = -2^31 and rB = -1 result all zeros - * rA = -1 and rB = -1 result all zeros - * rA = -1 and (rB != -1 AND rB != 0) result all 1's - */ + rA = -2^31 and rB = -1 result all zeros + rA = -1 and rB = -1 result all zeros + + if an attempt is made to perform any of the divisions: + 0x80000000 % -1 + <anything> % 0 + result is undefined. Force result to zero to match the + HW behaviour. */ + assign( resultis0, binop( Iop_Or64, - mkexpr( rA2_63 ), - unop ( Iop_1Sto64, mkexpr( rB_1 ) ) ) ); - assign( resultisF, - binop( Iop_And64, - unop( Iop_1Sto64, mkexpr( rA_1 ) ), - binop( Iop_And64, - unop( Iop_Not64, - unop( Iop_1Sto64, mkexpr( rB_0 ) ) ), - unop( Iop_Not64, - unop( Iop_1Sto64, mkexpr( rB_1 ) ) ) - ) ) ); + binop( Iop_Or64, + /* -1 % 1 */ + binop( Iop_And64, + unop( Iop_1Sto64, mkexpr( rA_m1 ) ), + unop( Iop_1Sto64, mkexpr( rB_1 ) ) ), + /* rA % 0 (division by zero) */ + unop( Iop_1Sto64, mkexpr( rB_0 ) ) ), + binop( Iop_Or64, + binop( Iop_And64, + unop( Iop_Not64, + mkexpr( rA2_63 ) ), + unop ( Iop_1Sto64, + mkexpr( rB_m1 ) ) ), + /* -1 % -1 */ + binop( Iop_And64, + unop( Iop_1Sto64, mkexpr( rA_m1 ) ), + unop( Iop_1Sto64, mkexpr( rB_m1 ) ) + ) ) ) ); /* The following remainder computation works as long as * rA != -2^63 and rB != -1. @@ -7518,33 +7533,25 @@ static Bool dis_modulo_int ( UInt prefix, UInt theInstr ) mkexpr( rA ), mkexpr( quotientTimesDivisor ) ) ); - assign( tmp, binop( Iop_And64, + assign( rD, binop( Iop_And64, mkexpr( remainder ), unop( Iop_Not64, mkexpr( resultis0 ) ) ) ); - - assign( rD, binop( Iop_Or64, - binop( Iop_And64, - unop (Iop_Not64, - mkexpr( resultisF ) ), - mkexpr( tmp ) ), - mkexpr( resultisF ) ) ); break; } case 0x30B: // modsw Modulo Signed Word { IRTemp rA = newTemp( Ity_I32 ); IRTemp rB = newTemp( Ity_I32 ); - IRTemp rA2_32 = newTemp( Ity_I32 ); /* all 1's if rA = -2^32 */ - IRTemp rB_0 = newTemp( Ity_I1 ); /* 1 if rB = 0 */ - IRTemp rB_1 = newTemp( Ity_I1 ); /* 1 if rB = -1 */ - IRTemp rA_1 = newTemp( Ity_I1 ); /* 1 if rA = -1 */ + IRTemp rA2_32 = newTemp( Ity_I32 ); /* all 1's if rA = -2^32 */ + IRTemp rB_0 = newTemp( Ity_I1 ); /* 1 if rB = 0 */ + IRTemp rB_1 = newTemp( Ity_I1 ); /* 1 if rB = 1 */ + IRTemp rB_m1 = newTemp( Ity_I1 ); /* 1 if rB = -1, 0xFFFFFFFF */ + IRTemp rA_m1 = newTemp( Ity_I1 ); /* 1 if rA = -1, 0xFFFFFFFF */ IRTemp resultis0 = newTemp( Ity_I32 ); - IRTemp resultisF = newTemp( Ity_I64 ); IRTemp quotient = newTemp( Ity_I32 ); IRTemp quotientTimesDivisor = newTemp( Ity_I32 ); IRTemp remainder = newTemp( Ity_I32 ); - IRTemp tmp = newTemp( Ity_I64 ); DIP("modsw r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr); @@ -7574,36 +7581,48 @@ static Bool dis_modulo_int ( UInt prefix, UInt theInstr ) assign( rB_1, binop( Iop_CmpEQ32, mkexpr( rB ), - mkU32( 0xFFFFFFFF ) ) ); + mkU32( 0x00000001 ) ) ); - assign( rA_1, binop( Iop_CmpEQ32, + assign( rB_m1, binop( Iop_CmpEQ32, + mkexpr( rB ), + mkU32( 0xFFFFFFFF ) ) ); + + assign( rA_m1, binop( Iop_CmpEQ32, mkexpr( rA ), mkU32( 0xFFFFFFFF ) ) ); /* Need to match the HW for these special cases - * rA = -2^31 and rB = -1 result all zeros - * rA = -1 and rB = -1 result all zeros - * rA = -1 and (rB != -1 AND rB != 0) result all 1's - */ + rA = -2^31 and rB = -1 result all zeros + rA = -1 and rB = -1 result all zeros + rA = -1 and rB = 1 result all zeros + + if an attempt is made to perform any of the divisions: + 0x80000000 % -1 + <anything> % 0 + result is undefined. Force result to zero to match the + HW beaviour. */ + assign( resultis0, binop( Iop_Or32, - unop( Iop_Not32, - binop( Iop_And32, - mkexpr( rA2_32 ), - unop( Iop_1Sto32, - mkexpr( rB_1 ) ) ) ), - binop( Iop_And32, - unop( Iop_1Sto32, mkexpr( rA_1 ) ), - unop( Iop_1Sto32, mkexpr( rB_1 ) ) ) ) ); - assign( resultisF, - binop( Iop_And64, - unop( Iop_1Sto64, mkexpr( rA_1 ) ), - binop( Iop_And64, - unop( Iop_Not64, - unop( Iop_1Sto64, mkexpr( rB_0 ) ) ), - unop( Iop_Not64, - unop( Iop_1Sto64, mkexpr( rB_1 ) ) ) - ) ) ); + binop( Iop_Or32, + /* -1 % 1 */ + binop( Iop_And32, + unop( Iop_1Sto32, mkexpr( rA_m1 ) ), + unop( Iop_1Sto32, mkexpr( rB_1 ) ) ), + /* rA % 0 (division by zero) */ + unop( Iop_1Sto32, mkexpr( rB_0 ) ) ), + + binop( Iop_Or32, + /* 0x8000000 % -1 */ + binop( Iop_And32, + mkexpr( rA2_32 ), + unop( Iop_1Sto32, + mkexpr( rB_m1 ) ) ), + /* -1 % -1 */ + binop( Iop_And32, + unop( Iop_1Sto32, mkexpr( rA_m1 ) ), + unop( Iop_1Sto32, mkexpr( rB_m1 ) ) + ) ) ) ); /* The following remainder computation works as long as * rA != -2^31 and rB != -1. @@ -7622,19 +7641,12 @@ static Bool dis_modulo_int ( UInt prefix, UInt theInstr ) mkexpr( rA ), mkexpr( quotientTimesDivisor ) ) ); - assign( tmp, binop( Iop_32HLto64, + assign( rD, binop( Iop_32HLto64, mkU32( 0 ), binop( Iop_And32, mkexpr( remainder ), unop( Iop_Not32, mkexpr( resultis0 ) ) ) ) ); - - assign( rD, binop( Iop_Or64, - binop( Iop_And64, - unop ( Iop_Not64, - mkexpr( resultisF ) ), - mkexpr( tmp ) ), - mkexpr( resultisF ) ) ); break; } diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index cd5dc91a46..23a22d922b 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -49,6 +49,8 @@ EXTRA_DIST = \ test_isa_3_0_altivec.stdout.exp-LE test_isa_3_0_altivec.vgtest \ test_isa_3_0_other.stderr.exp \ test_isa_3_0_other.stdout.exp-LE test_isa_3_0_other.vgtest \ + test_mod_instructions.stderr.exp test_mod_instructions.stdout.exp \ + test_mod_instructions.vgtest \ test_isa_3_1_RT.vgtest test_isa_3_1_RT.stderr.exp test_isa_3_1_RT.stdout.exp \ test_isa_3_1_XT.vgtest test_isa_3_1_XT.stderr.exp test_isa_3_1_XT.stdout.exp \ test_isa_3_1_VRT.vgtest test_isa_3_1_VRT.stderr.exp test_isa_3_1_VRT.stdout.exp \ @@ -63,7 +65,7 @@ check_PROGRAMS = \ test_isa_2_06_part1 test_isa_2_06_part2 test_isa_2_06_part3 \ test_dfp1 test_dfp2 test_dfp3 test_dfp4 test_dfp5 \ test_isa_2_07_part1 test_isa_2_07_part2 \ - test_isa_3_0 \ + test_isa_3_0 test_mod_instructions \ test_isa_3_1_RT test_isa_3_1_XT test_isa_3_1_VRT \ test_isa_3_1_Misc test_isa_3_1_AT \ subnormal_test \ diff --git a/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE index cc0e88e9a3..4d6da7999f 100644 --- a/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE +++ b/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE @@ -7,7 +7,7 @@ modsw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000) modsw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000) modsw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000) modsw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000) -modsw ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000) +modsw ffffffffffffffff, 0000001cbe991def => 00000000ffffffff (00000000) modsw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000) moduw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000) diff --git a/none/tests/ppc64/test_mod_instructions.c b/none/tests/ppc64/test_mod_instructions.c new file mode 100644 index 0000000000..07e1cd2881 --- /dev/null +++ b/none/tests/ppc64/test_mod_instructions.c @@ -0,0 +1,251 @@ +#include <stdio.h> + +long test_modsd( long srcA, long srcB) +{ + long dst; + __asm__ __volatile__ ("modsd %0,%1,%2" : "=r" (dst): "r" (srcA), "r" (srcB)); + + return dst; +} + +unsigned long test_modud( unsigned long srcA, unsigned long srcB) +{ + unsigned long dst; + __asm__ __volatile__ ("modud %0,%1,%2" : "=r" (dst): "r" (srcA), "r" (srcB)); + + return dst; +} + +int test_modsw( int srcA, int srcB) +{ + int dst; + __asm__ __volatile__ ("modsw %0,%1,%2" : "=r" (dst): "r" (srcA), "r" (srcB)); + + return dst; +} + +unsigned test_moduw( unsigned srcA, unsigned srcB) +{ + unsigned dst; + __asm__ __volatile__ ("moduw %0,%1,%2" : "=r" (dst): "r" (srcA), "r" (srcB)); + + return dst; +} + +int main() +{ + int srcA_si, srcB_si, dst_si; + unsigned int srcA_ui, srcB_ui, dst_ui; + long srcA_sl, srcB_sl, dst_sl; + unsigned long srcA_ul, srcB_ul, dst_ul; + int i_si, j_si; + long int i_sl, j_sl; + int i_ui, j_ui; + long int i_ul, j_ul; + +#define SI_NEGATIVE_START 0x80000000 +#define SI_NEGATIVE_STOP 0x80000008 +#define SI_POSITIVE_START 0x7FFFFFF8 +#define SI_POSITIVE_STOP 0x7FFFFFFF +#define SI_ZERO_START -5 +#define SI_ZERO_STOP 5 + +#define DI_NEGATIVE_START 0x8000000000000000LL +#define DI_NEGATIVE_STOP 0x8000000000000008LL +#define DI_POSITIVE_START 0x7FFFFFFFFFFFFFF8LL +#define DI_POSITIVE_STOP 0x7FFFFFFFFFFFFFFFLL +#define DI_ZERO_START -5 +#define DI_ZERO_STOP 5 + +#define UI_START 0xFFFFFFF8 +#define UI_STOP 0xFFFFFFFF +#define UI_ZERO_START 0 +#define UI_ZERO_STOP 10 + +#define UL_START 0xFFFFFFFFFFFFFFF8ULL +#define UL_STOP 0xFFFFFFFFFFFFFFFFULL +#define UL_ZERO_START 0 +#define UL_ZERO_STOP 10 + + /* Signed tests need to check the most negative values, + the most positive values and values around zero. */ + + /* Signed integer tests */ + for (i_si = SI_NEGATIVE_START; i_si < SI_NEGATIVE_STOP; i_si++) + for (j_si = SI_NEGATIVE_START; j_si < SI_NEGATIVE_STOP; j_si++) + { + srcA_si = i_si; + srcB_si = j_si; + + dst_si = test_modsw( srcA_si, srcB_si); +#ifdef debug + printf("srcA_si = %d \n", srcA_si); + printf("srcB_si = %d \n", srcB_si); + printf ("modsw result = %d\n\n", dst_si); +#else + printf ("modsw result = %d\n", dst_si); +#endif + } + + for (i_si = SI_ZERO_START; i_si < SI_ZERO_STOP; i_si++) + for (j_si = SI_ZERO_START; j_si < SI_ZERO_STOP; j_si++) + { + srcA_si = i_si; + srcB_si = j_si; + + dst_si = test_modsw( srcA_si, srcB_si); + +#ifdef debug + printf("srcA_si = %d \n", srcA_si); + printf("srcB_si = %d \n", srcB_si); + printf ("modsw result = %d\n\n", dst_si); +#else + printf ("modsw result = %d\n", dst_si); +#endif + } + + for (i_si = SI_POSITIVE_START; i_si < SI_POSITIVE_STOP; i_si++) + for (j_si = SI_POSITIVE_START; j_si < SI_POSITIVE_STOP; j_si++) + { + srcA_si = i_si; + srcB_si = j_si; + + dst_si = test_modsw( srcA_si, srcB_si); + +#ifdef debug + printf("srcA_si = %d \n", srcA_si); + printf("srcB_si = %d \n", srcB_si); + printf ("modsw result = %d\n\n", dst_si); +#else + printf ("modsw result = %d\n", dst_si); +#endif + } + + /* Signed long integer tests */ + for (i_sl = DI_NEGATIVE_START; i_sl < DI_NEGATIVE_STOP; i_sl++) + for (j_sl = DI_NEGATIVE_START; j_sl < DI_NEGATIVE_STOP; j_sl++) + { + srcA_sl = i_sl; + srcB_sl = j_sl; + + dst_sl = test_modsd( srcA_sl, srcB_sl); + +#ifdef debug + printf("srcA_sl = %ld \n", srcA_sl); + printf("srcB_sl = %ld \n", srcB_sl); + printf ("modsd result = %ld\n\n", dst_sl); +#else + printf ("modsd result = %ld\n", dst_sl); +#endif + } + + for (i_sl = DI_ZERO_START; i_sl < DI_ZERO_STOP; i_sl++) + for (j_sl = DI_ZERO_START; j_sl < DI_ZERO_STOP; j_sl++) + { + srcA_sl = i_sl; + srcB_sl = j_sl; + + dst_sl = test_modsd( srcA_sl, srcB_sl); + +#ifdef debug + printf("srcA_sl = %ld \n", srcA_sl); + printf("srcB_sl = %ld \n", srcB_sl); + printf ("modsd result = %ld\n\n", dst_sl); +#else + printf ("modsd result = %ld\n", dst_sl); +#endif + } + + for (i_sl = DI_POSITIVE_START; i_sl < DI_POSITIVE_STOP; i_sl++) + for (j_sl = DI_POSITIVE_START; j_sl < DI_POSITIVE_STOP; j_sl++) + { + srcA_sl = i_sl; + srcB_sl = j_sl; + + dst_sl = test_modsd( srcA_sl, srcB_sl); + +#ifdef debug + printf("srcA_sl = %ld \n", srcA_sl); + printf("srcB_sl = %ld \n", srcB_sl); + printf ("modsd result = %ld\n\n", dst_sl); +#else + printf ("modsd result = %ld\n", dst_sl); +#endif + } + + /* Unsigned tests need to check the most positive values + and the values around zero. */ + + /* Unsigned integer tests */ + for (i_ui = UI_START; i_ui < UI_STOP; i_ui++) + for (j_ui = UI_START; j_ui < UI_STOP; j_ui++) + { + srcA_ui = i_ui; + srcB_ui = j_ui; + + dst_ui = test_moduw( srcA_ui, srcB_ui); + +#ifdef debug + printf("srcA_ui = %u \n", srcA_ui); + printf("srcB_ui = %u \n", srcB_ui); + printf ("moduw result = %u\n\n", dst_ui); +#else + printf ("moduw result = %u\n", dst_ui); +#endif + } + + for (i_ui = SI_ZERO_START; i_ui < SI_ZERO_STOP; i_ui++) + for (j_ui = SI_ZERO_START; j_ui < SI_ZERO_STOP; j_ui++) + { + srcA_ui = i_ui; + srcB_ui = j_ui; + + dst_ui = test_moduw( srcA_ui, srcB_ui); + +#ifdef debug + printf("srcA_ui = %u \n", srcA_ui); + printf("srcB_ui = %u \n", srcB_ui); + printf ("moduw result = %u\n", dst_ui); +#else + printf ("moduw result = %u\n\n", dst_ui); +#endif + } + + /* Unsigned long integer tests */ + for (i_ul = UL_START; i_ul < UL_STOP; i_ul++) + for (j_ul = UL_START; j_ul < UL_STOP; j_ul++) + { + srcA_ul = i_ul; + srcB_ul = j_ul; + + dst_ul = test_modud( srcA_ul, srcB_ul); + +#ifdef debug + printf("srcA_ul = %lu \n", srcA_ul); + printf("srcB_ul = %lu \n", srcB_ul); + printf ("modud result = %lu\n\n", dst_ul); +#else + printf ("modud result = %lu\n", dst_ul); +#endif + } + + for (i_ul = UL_ZERO_START; i_ul < UL_ZERO_STOP; i_ul++) + for (j_ul = UL_ZERO_START; j_ul < UL_ZERO_STOP; j_ul++) + { + srcA_ul = i_ul; + srcB_ul = j_ul; + + dst_ul = test_modud( srcA_ul, srcB_ul); + +#ifdef debug + printf("srcA_ul = %lu \n", srcA_ul); + printf("srcB_ul = %lu \n", srcB_ul); + printf ("modud result = %lu\n\n", dst_ul); +#else + printf ("modud result = %lu\n", dst_ul); +#endif + } + + return 0; +} + diff --git a/none/tests/ppc64/test_mod_instructions.stderr.exp b/none/tests/ppc64/test_mod_instructions.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc64/test_mod_instructions.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/test_mod_instructions.stdout.exp b/none/tests/ppc64/test_mod_instructions.stdout.exp new file mode 100644 index 0000000000..b53f97e546 --- /dev/null +++ b/none/tests/ppc64/test_mod_instructions.stdout.exp @@ -0,0 +1,824 @@ +modsw result = 0 +modsw result = -1 +modsw result = -2 +modsw result = -3 +modsw result = -4 +modsw result = -5 +modsw result = -6 +modsw result = -7 +modsw result = -2147483647 +modsw result = 0 +modsw result = -1 +modsw result = -2 +modsw result = -3 +modsw result = -4 +modsw result = -5 +modsw result = -6 +modsw result = -2147483646 +modsw result = -2147483646 +modsw result = 0 +modsw result = -1 +modsw result = -2 +modsw result = -3 +modsw result = -4 +modsw result = -5 +modsw result = -2147483645 +modsw result = -2147483645 +modsw result = -2147483645 +modsw result = 0 +modsw result = -1 +modsw result = -2 +modsw result = -3 +modsw result = -4 +modsw result = -2147483644 +modsw result = -2147483644 +modsw result = -2147483644 +modsw result = -2147483644 +modsw result = 0 +modsw result = -1 +modsw result = -2 +modsw result = -3 +modsw result = -2147483643 +modsw result = -2147483643 +modsw result = -2147483643 +modsw result = -2147483643 +modsw result = -2147483643 +modsw result = 0 +modsw result = -1 +modsw result = -2 +modsw result = -2147483642 +modsw result = -2147483642 +modsw result = -2147483642 +modsw result = -2147483642 +modsw result = -2147483642 +modsw result = -2147483642 +modsw result = 0 +modsw result = -1 +modsw result = -2147483641 +modsw result = -2147483641 +modsw result = -2147483641 +modsw result = -2147483641 +modsw result = -2147483641 +modsw result = -2147483641 +modsw result = -2147483641 +modsw result = 0 +modsw result = 0 +modsw result = -1 +modsw result = -2 +modsw result = -1 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = -1 +modsw result = -2 +modsw result = -1 +modsw result = -4 +modsw result = 0 +modsw result = -1 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = -1 +modsw result = 0 +modsw result = -3 +modsw result = -3 +modsw result = 0 +modsw result = -1 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = -1 +modsw result = 0 +modsw result = -3 +modsw result = -2 +modsw result = -2 +modsw result = -2 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = -2 +modsw result = -2 +modsw result = -1 +modsw result = -1 +modsw result = -1 +modsw result = -1 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = -1 +modsw result = -1 +modsw result = -1 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 1 +modsw result = 1 +modsw result = 1 +modsw result = 1 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 1 +modsw result = 1 +modsw result = 1 +modsw result = 2 +modsw result = 2 +modsw result = 2 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 2 +modsw result = 2 +modsw result = 3 +modsw result = 3 +modsw result = 0 +modsw result = 1 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 1 +modsw result = 0 +modsw result = 3 +modsw result = 4 +modsw result = 0 +modsw result = 1 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 0 +modsw result = 1 +modsw result = 0 +modsw result = 0 +modsw result = 2147483640 +modsw result = 2147483640 +modsw result = 2147483640 +modsw result = 2147483640 +modsw result = 2147483640 +modsw result = 2147483640 +modsw result = 1 +modsw result = 0 +modsw result = 2147483641 +modsw result = 2147483641 +modsw result = 2147483641 +modsw result = 2147483641 +modsw result = 2147483641 +modsw result = 2 +modsw result = 1 +modsw result = 0 +modsw result = 2147483642 +modsw result = 2147483642 +modsw result = 2147483642 +modsw result = 2147483642 +modsw result = 3 +modsw result = 2 +modsw result = 1 +modsw result = 0 +modsw result = 2147483643 +modsw result = 2147483643 +modsw result = 2147483643 +modsw result = 4 +modsw result = 3 +modsw result = 2 +modsw result = 1 +modsw result = 0 +modsw result = 2147483644 +modsw result = 2147483644 +modsw result = 5 +modsw result = 4 +modsw result = 3 +modsw result = 2 +modsw result = 1 +modsw result = 0 +modsw result = 2147483645 +modsw result = 6 +modsw result = 5 +modsw result = 4 +modsw result = 3 +modsw result = 2 +modsw result = 1 +modsw result = 0 +modsd result = 0 +modsd result = -1 +modsd result = -2 +modsd result = -3 +modsd result = -4 +modsd result = -5 +modsd result = -6 +modsd result = -7 +modsd result = -9223372036854775807 +modsd result = 0 +modsd result = -1 +modsd result = -2 +modsd result = -3 +modsd result = -4 +modsd result = -5 +modsd result = -6 +modsd result = -9223372036854775806 +modsd result = -9223372036854775806 +modsd result = 0 +modsd result = -1 +modsd result = -2 +modsd result = -3 +modsd result = -4 +modsd result = -5 +modsd result = -9223372036854775805 +modsd result = -9223372036854775805 +modsd result = -9223372036854775805 +modsd result = 0 +modsd result = -1 +modsd result = -2 +modsd result = -3 +modsd result = -4 +modsd result = -9223372036854775804 +modsd result = -9223372036854775804 +modsd result = -9223372036854775804 +modsd result = -9223372036854775804 +modsd result = 0 +modsd result = -1 +modsd result = -2 +modsd result = -3 +modsd result = -9223372036854775803 +modsd result = -9223372036854775803 +modsd result = -9223372036854775803 +modsd result = -9223372036854775803 +modsd result = -9223372036854775803 +modsd result = 0 +modsd result = -1 +modsd result = -2 +modsd result = -9223372036854775802 +modsd result = -9223372036854775802 +modsd result = -9223372036854775802 +modsd result = -9223372036854775802 +modsd result = -9223372036854775802 +modsd result = -9223372036854775802 +modsd result = 0 +modsd result = -1 +modsd result = -9223372036854775801 +modsd result = -9223372036854775801 +modsd result = -9223372036854775801 +modsd result = -9223372036854775801 +modsd result = -9223372036854775801 +modsd result = -9223372036854775801 +modsd result = -9223372036854775801 +modsd result = 0 +modsd result = 0 +modsd result = -1 +modsd result = -2 +modsd result = -1 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = -1 +modsd result = -2 +modsd result = -1 +modsd result = -4 +modsd result = 0 +modsd result = -1 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = -1 +modsd result = 0 +modsd result = -3 +modsd result = -3 +modsd result = 0 +modsd result = -1 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = -1 +modsd result = 0 +modsd result = -3 +modsd result = -2 +modsd result = -2 +modsd result = -2 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = -2 +modsd result = -2 +modsd result = -1 +modsd result = -1 +modsd result = -1 +modsd result = -1 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = -1 +modsd result = -1 +modsd result = -1 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 1 +modsd result = 1 +modsd result = 1 +modsd result = 1 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 1 +modsd result = 1 +modsd result = 1 +modsd result = 2 +modsd result = 2 +modsd result = 2 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 2 +modsd result = 2 +modsd result = 3 +modsd result = 3 +modsd result = 0 +modsd result = 1 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 1 +modsd result = 0 +modsd result = 3 +modsd result = 4 +modsd result = 0 +modsd result = 1 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 0 +modsd result = 1 +modsd result = 0 +modsd result = 0 +modsd result = 9223372036854775800 +modsd result = 9223372036854775800 +modsd result = 9223372036854775800 +modsd result = 9223372036854775800 +modsd result = 9223372036854775800 +modsd result = 9223372036854775800 +modsd result = 1 +modsd result = 0 +modsd result = 9223372036854775801 +modsd result = 9223372036854775801 +modsd result = 9223372036854775801 +modsd result = 9223372036854775801 +modsd result = 9223372036854775801 +modsd result = 2 +modsd result = 1 +modsd result = 0 +modsd result = 9223372036854775802 +modsd result = 9223372036854775802 +modsd result = 9223372036854775802 +modsd result = 9223372036854775802 +modsd result = 3 +modsd result = 2 +modsd result = 1 +modsd result = 0 +modsd result = 9223372036854775803 +modsd result = 9223372036854775803 +modsd result = 9223372036854775803 +modsd result = 4 +modsd result = 3 +modsd result = 2 +modsd result = 1 +modsd result = 0 +modsd result = 9223372036854775804 +modsd result = 9223372036854775804 +modsd result = 5 +modsd result = 4 +modsd result = 3 +modsd result = 2 +modsd result = 1 +modsd result = 0 +modsd result = 9223372036854775805 +modsd result = 6 +modsd result = 5 +modsd result = 4 +modsd result = 3 +modsd result = 2 +modsd result = 1 +modsd result = 0 +moduw result = 0 +moduw result = 4294967288 +moduw result = 4294967288 +moduw result = 4294967288 +moduw result = 4294967288 +moduw result = 4294967288 +moduw result = 4294967288 +moduw result = 1 +moduw result = 0 +moduw result = 4294967289 +moduw result = 4294967289 +moduw result = 4294967289 +moduw result = 4294967289 +moduw result = 4294967289 +moduw result = 2 +moduw result = 1 +moduw result = 0 +moduw result = 4294967290 +moduw result = 4294967290 +moduw result = 4294967290 +moduw result = 4294967290 +moduw result = 3 +moduw result = 2 +moduw result = 1 +moduw result = 0 +moduw result = 4294967291 +moduw result = 4294967291 +moduw result = 4294967291 +moduw result = 4 +moduw result = 3 +moduw result = 2 +moduw result = 1 +moduw result = 0 +moduw result = 4294967292 +moduw result = 4294967292 +moduw result = 5 +moduw result = 4 +moduw result = 3 +moduw result = 2 +moduw result = 1 +moduw result = 0 +moduw result = 4294967293 +moduw result = 6 +moduw result = 5 +moduw result = 4 +moduw result = 3 +moduw result = 2 +moduw result = 1 +moduw result = 0 +moduw result = 0 + +moduw result = 4294967291 + +moduw result = 4294967291 + +moduw result = 4294967291 + +moduw result = 4294967291 + +moduw result = 0 + +moduw result = 0 + +moduw result = 1 + +moduw result = 2 + +moduw result = 3 + +moduw result = 1 + +moduw result = 0 + +moduw result = 4294967292 + +moduw result = 4294967292 + +moduw result = 4294967292 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 2 + +moduw result = 1 + +moduw result = 0 + +moduw result = 4294967293 + +moduw result = 4294967293 + +moduw result = 0 + +moduw result = 0 + +moduw result = 1 + +moduw result = 1 + +moduw result = 1 + +moduw result = 3 + +moduw result = 2 + +moduw result = 1 + +moduw result = 0 + +moduw result = 4294967294 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 2 + +moduw result = 2 + +moduw result = 4 + +moduw result = 3 + +moduw result = 2 + +moduw result = 1 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 1 + +moduw result = 0 + +moduw result = 3 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 1 + +moduw result = 1 + +moduw result = 1 + +moduw result = 1 + +moduw result = 1 + +moduw result = 0 + +moduw result = 0 + +moduw result = 1 + +moduw result = 1 + +moduw result = 1 + +moduw result = 2 + +moduw result = 2 + +moduw result = 2 + +moduw result = 2 + +moduw result = 2 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 2 + +moduw result = 2 + +moduw result = 3 + +moduw result = 3 + +moduw result = 3 + +moduw result = 3 + +moduw result = 3 + +moduw result = 0 + +moduw result = 0 + +moduw result = 1 + +moduw result = 0 + +moduw result = 3 + +moduw result = 4 + +moduw result = 4 + +moduw result = 4 + +moduw result = 4 + +moduw result = 4 + +moduw result = 0 + +moduw result = 0 + +moduw result = 0 + +moduw result = 1 + +moduw result = 0 + +modud result = 0 +modud result = 18446744073709551608 +modud result = 18446744073709551608 +modud result = 18446744073709551608 +modud result = 18446744073709551608 +modud result = 18446744073709551608 +modud result = 18446744073709551608 +modud result = 1 +modud result = 0 +modud result = 18446744073709551609 +modud result = 18446744073709551609 +modud result = 18446744073709551609 +modud result = 18446744073709551609 +modud result = 18446744073709551609 +modud result = 2 +modud result = 1 +modud result = 0 +modud result = 18446744073709551610 +modud result = 18446744073709551610 +modud result = 18446744073709551610 +modud result = 18446744073709551610 +modud result = 3 +modud result = 2 +modud result = 1 +modud result = 0 +modud result = 18446744073709551611 +modud result = 18446744073709551611 +modud result = 18446744073709551611 +modud result = 4 +modud result = 3 +modud result = 2 +modud result = 1 +modud result = 0 +modud result = 18446744073709551612 +modud result = 18446744073709551612 +modud result = 5 +modud result = 4 +modud result = 3 +modud result = 2 +modud result = 1 +modud result = 0 +modud result = 18446744073709551613 +modud result = 6 +modud result = 5 +modud result = 4 +modud result = 3 +modud result = 2 +modud result = 1 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 1 +modud result = 1 +modud result = 1 +modud result = 1 +modud result = 1 +modud result = 1 +modud result = 1 +modud result = 1 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 2 +modud result = 2 +modud result = 2 +modud result = 2 +modud result = 2 +modud result = 2 +modud result = 2 +modud result = 0 +modud result = 0 +modud result = 1 +modud result = 0 +modud result = 3 +modud result = 3 +modud result = 3 +modud result = 3 +modud result = 3 +modud result = 3 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 1 +modud result = 0 +modud result = 4 +modud result = 4 +modud result = 4 +modud result = 4 +modud result = 4 +modud result = 0 +modud result = 0 +modud result = 1 +modud result = 2 +modud result = 1 +modud result = 0 +modud result = 5 +modud result = 5 +modud result = 5 +modud result = 5 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 2 +modud result = 1 +modud result = 0 +modud result = 6 +modud result = 6 +modud result = 6 +modud result = 0 +modud result = 0 +modud result = 1 +modud result = 1 +modud result = 3 +modud result = 2 +modud result = 1 +modud result = 0 +modud result = 7 +modud result = 7 +modud result = 0 +modud result = 0 +modud result = 0 +modud result = 2 +modud result = 0 +modud result = 3 +modud result = 2 +modud result = 1 +modud result = 0 +modud result = 8 +modud result = 0 +modud result = 0 +modud result = 1 +modud result = 0 +modud result = 1 +modud result = 4 +modud result = 3 +modud result = 2 +modud result = 1 +modud result = 0 diff --git a/none/tests/ppc64/test_mod_instructions.vgtest b/none/tests/ppc64/test_mod_instructions.vgtest new file mode 100644 index 0000000000..d281fcc60b --- /dev/null +++ b/none/tests/ppc64/test_mod_instructions.vgtest @@ -0,0 +1,2 @@ +prereq: ../../../tests/check_ppc64_auxv_cap arch_3_00 +prog: test_mod_instructions |