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From: Carl L. <ca...@so...> - 2020-11-09 23:47:37
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=cd01d5eb0c4f1d7440c45ed9595fc1ab99165910 commit cd01d5eb0c4f1d7440c45ed9595fc1ab99165910 Author: Carl Love <ce...@us...> Date: Tue Oct 6 12:01:35 2020 -0500 Bit Manipulation Operation tests Diff: --- NEWS | 1 + none/tests/ppc64/test_isa_3_1_RT.c | 44 + none/tests/ppc64/test_isa_3_1_RT.stdout.exp | 271 ++- none/tests/ppc64/test_isa_3_1_VRT.c | 25 + none/tests/ppc64/test_isa_3_1_VRT.stdout.exp | 852 ++++++++- none/tests/ppc64/test_isa_3_1_XT.c | 10 + none/tests/ppc64/test_isa_3_1_XT.stdout.exp | 2370 +++++++++++++++++++++++++- 7 files changed, 3570 insertions(+), 3 deletions(-) diff --git a/NEWS b/NEWS index 7b9142fc4a..7b4cea04a0 100644 --- a/NEWS +++ b/NEWS @@ -55,6 +55,7 @@ n-i-bz helgrind: If hg_cli__realloc fails, return NULL. 427787 Support new faccessat2 linux syscall (439) 428035 drd: Unbreak the musl build 428648 s390_emit_load_mem panics due to 20-bit offset for vector load +427400 PPC ISA 3.1 support is missing, part 4 Release 3.16.1 (?? June 2020) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/none/tests/ppc64/test_isa_3_1_RT.c b/none/tests/ppc64/test_isa_3_1_RT.c index c6f8422ab3..ce70c7ac0f 100644 --- a/none/tests/ppc64/test_isa_3_1_RT.c +++ b/none/tests/ppc64/test_isa_3_1_RT.c @@ -73,6 +73,39 @@ static void test_plxvp_off24 (void) { static void test_plxvp_off32 (void) { __asm__ __volatile__ ("plxvp 20, 32(%0), 0" :: "r" (ra) ); } +static void test_cfuged (void) { + __asm__ __volatile__ ("cfuged %0, %1, %2" : "=r" (ra) : "r" (rs), "r" (rb) ); +} +static void test_cntlzdm (void) { + __asm__ __volatile__ ("cntlzdm %0, %1, %2" : "=r" (ra) : "r" (rs), "r" (rb) ); +} +static void test_cnttzdm (void) { + __asm__ __volatile__ ("cnttzdm %0, %1, %2" : "=r" (ra) : "r" (rs), "r" (rb) ); +} +static void test_pdepd (void) { + __asm__ __volatile__ ("pdepd %0, %1, %2" : "=r" (ra) : "r" (rs), "r" (rb) ); +} +static void test_pextd (void) { + __asm__ __volatile__ ("pextd %0, %1, %2" : "=r" (ra) : "r" (rs), "r" (rb) ); +} +static void test_vgnb_2 (void) { + __asm__ __volatile__ ("vgnb %0, %1, 2" : "=r" (rt) : "v" (vrb) ); +} +static void test_vgnb_3 (void) { + __asm__ __volatile__ ("vgnb %0, %1, 3" : "=r" (rt) : "v" (vrb) ); +} +static void test_vgnb_4 (void) { + __asm__ __volatile__ ("vgnb %0, %1, 4" : "=r" (rt) : "v" (vrb) ); +} +static void test_vgnb_5 (void) { + __asm__ __volatile__ ("vgnb %0, %1, 5" : "=r" (rt) : "v" (vrb) ); +} +static void test_vgnb_6 (void) { + __asm__ __volatile__ ("vgnb %0, %1, 6" : "=r" (rt) : "v" (vrb) ); +} +static void test_vgnb_7 (void) { + __asm__ __volatile__ ("vgnb %0, %1, 7" : "=r" (rt) : "v" (vrb) ); +} static void test_setbc_0_cr0s (void) { SET_CR(0x00000000); __asm__ __volatile__ ("setbc 26, 0"); @@ -661,10 +694,15 @@ static test_list_t testgroup_generic[] = { { &test_brd, "brd", "RA,RS"}, /* bcs */ { &test_brh, "brh", "RA,RS"}, /* bcs */ { &test_brw, "brw", "RA,RS"}, /* bcs */ + { &test_cfuged, "cfuged", "RA,RS,RB"}, /* bcs */ + { &test_cntlzdm, "cntlzdm", "RA,RS,RB"}, /* bcs */ + { &test_cnttzdm, "cnttzdm", "RA,RS,RB"}, /* bcs */ { &test_paddi_0, "paddi 0", "RT,RA,SI,R"}, /* bcwp */ { &test_paddi_12, "paddi 12", "RT,RA,SI,R"}, /* bcwp */ { &test_paddi_48, "paddi 48", "RT,RA,SI,R"}, /* bcwp */ { &test_paddi_98, "paddi 98", "RT,RA,SI,R"}, /* bcwp */ + { &test_pdepd, "pdepd", "RA,RS,RB"}, /* bcs */ + { &test_pextd, "pextd", "RA,RS,RB"}, /* bcs */ { &test_plbz_off0, "plbz off0", "RT,D(RA),R"}, /* bcwp */ { &test_plbz_off8, "plbz off8", "RT,D(RA),R"}, /* bcwp */ { &test_plbz_off16, "plbz off16", "RT,D(RA),R"}, /* bcwp */ @@ -807,6 +845,12 @@ static test_list_t testgroup_generic[] = { { &test_setnbc_31_cr1s, "setnbc 31_cr1s", "RT,BI"}, /* bcwp */ { &test_setnbc_31_creb, "setnbc 31_creb", "RT,BI"}, /* bcwp */ { &test_setnbc_31_crob, "setnbc 31_crob", "RT,BI"}, /* bcwp */ + { &test_vgnb_2, "vgnb 2", "RT,VRB,N"}, /* bcwp */ + { &test_vgnb_3, "vgnb 3", "RT,VRB,N"}, /* bcwp */ + { &test_vgnb_4, "vgnb 4", "RT,VRB,N"}, /* bcwp */ + { &test_vgnb_5, "vgnb 5", "RT,VRB,N"}, /* bcwp */ + { &test_vgnb_6, "vgnb 6", "RT,VRB,N"}, /* bcwp */ + { &test_vgnb_7, "vgnb 7", "RT,VRB,N"}, /* bcwp */ { NULL, NULL }, }; diff --git a/none/tests/ppc64/test_isa_3_1_RT.stdout.exp b/none/tests/ppc64/test_isa_3_1_RT.stdout.exp index 2cfd5cd66a..7cacb36440 100644 --- a/none/tests/ppc64/test_isa_3_1_RT.stdout.exp +++ b/none/tests/ppc64/test_isa_3_1_RT.stdout.exp @@ -19,6 +19,117 @@ brw 7ff7000100030005 => 100f77f05000300 brw ffe7111022203330 => 1011e7ff30332022 brw 0 => 0 +cfuged 102030405060708 102030405060708 => 1fff +cfuged 102030405060708 a5b4c3d2e1f00918 => a56b0d5c78111643 +cfuged 102030405060708 fff7fffafff3fff1 => ffefffdffbff3ede +cfuged 102030405060708 7ff7000100030005 => 7fec00200200b810 +cfuged 102030405060708 ffe7111022203330 => ffcc410490631a06 +cfuged 102030405060708 0 => 0 +cfuged a5b4c3d2e1f00918 102030405060708 => 202260c01030105 +cfuged a5b4c3d2e1f00918 a5b4c3d2e1f00918 => fffffff +cfuged a5b4c3d2e1f00918 fff7fffafff3fff1 => fbfcf3ff9ffffffe +cfuged a5b4c3d2e1f00918 7ff7000100030005 => fb01030057f00000 +cfuged a5b4c3d2e1f00918 ffe7111022203330 => fb4010348fd12226 +cfuged a5b4c3d2e1f00918 0 => 0 +cfuged fff7fffafff3fff1 102030405060708 => 4c010406002840e0 +cfuged fff7fffafff3fff1 a5b4c3d2e1f00918 => 4a5b987af0f8122 +cfuged fff7fffafff3fff1 fff7fffafff3fff1 => ffffffffffffff +cfuged fff7fffafff3fff1 7ff7000100030005 => 227ffe0000006001 +cfuged fff7fffafff3fff1 ffe7111022203330 => ffee2221110666 +cfuged fff7fffafff3fff1 0 => 0 +cfuged 7ff7000100030005 102030405060708 => c102820e101048 +cfuged 7ff7000100030005 a5b4c3d2e1f00918 => b0f4f0f812325b80 +cfuged 7ff7000100030005 fff7fffafff3fff1 => bffefff9ffe7ffed +cfuged 7ff7000100030005 7ff7000100030005 => 7ffff +cfuged 7ff7000100030005 ffe7111022203330 => 844411106667fee0 +cfuged 7ff7000100030005 0 => 0 +cfuged ffe7111022203330 102030405060708 => 10818612004240c +cfuged ffe7111022203330 a5b4c3d2e1f00918 => b1c58f022296c745 +cfuged ffe7111022203330 fff7fffafff3fff1 => bff5ff3fc7ffffff +cfuged ffe7111022203330 7ff7000100030005 => 8002003015fff000 +cfuged ffe7111022203330 ffe7111022203330 => 3ffffff +cfuged ffe7111022203330 0 => 0 +cfuged 0 102030405060708 => 102030405060708 +cfuged 0 a5b4c3d2e1f00918 => a5b4c3d2e1f00918 +cfuged 0 fff7fffafff3fff1 => fff7fffafff3fff1 +cfuged 0 7ff7000100030005 => 7ff7000100030005 +cfuged 0 ffe7111022203330 => ffe7111022203330 +cfuged 0 0 => 0 + +cntlzdm 102030405060708 102030405060708 => 0 +cntlzdm 102030405060708 a5b4c3d2e1f00918 => 0 +cntlzdm 102030405060708 fff7fffafff3fff1 => 0 +cntlzdm 102030405060708 7ff7000100030005 => 0 +cntlzdm 102030405060708 ffe7111022203330 => 0 +cntlzdm 102030405060708 0 => d +cntlzdm a5b4c3d2e1f00918 102030405060708 => 3 +cntlzdm a5b4c3d2e1f00918 a5b4c3d2e1f00918 => 0 +cntlzdm a5b4c3d2e1f00918 fff7fffafff3fff1 => 0 +cntlzdm a5b4c3d2e1f00918 7ff7000100030005 => 1 +cntlzdm a5b4c3d2e1f00918 ffe7111022203330 => 0 +cntlzdm a5b4c3d2e1f00918 0 => 1c +cntlzdm fff7fffafff3fff1 102030405060708 => 7 +cntlzdm fff7fffafff3fff1 a5b4c3d2e1f00918 => 0 +cntlzdm fff7fffafff3fff1 fff7fffafff3fff1 => 0 +cntlzdm fff7fffafff3fff1 7ff7000100030005 => 1 +cntlzdm fff7fffafff3fff1 ffe7111022203330 => 0 +cntlzdm fff7fffafff3fff1 0 => 38 +cntlzdm 7ff7000100030005 102030405060708 => 6 +cntlzdm 7ff7000100030005 a5b4c3d2e1f00918 => 1 +cntlzdm 7ff7000100030005 fff7fffafff3fff1 => 0 +cntlzdm 7ff7000100030005 7ff7000100030005 => 0 +cntlzdm 7ff7000100030005 ffe7111022203330 => 0 +cntlzdm 7ff7000100030005 0 => 13 +cntlzdm ffe7111022203330 102030405060708 => 7 +cntlzdm ffe7111022203330 a5b4c3d2e1f00918 => 0 +cntlzdm ffe7111022203330 fff7fffafff3fff1 => 0 +cntlzdm ffe7111022203330 7ff7000100030005 => 1 +cntlzdm ffe7111022203330 ffe7111022203330 => 0 +cntlzdm ffe7111022203330 0 => 1a +cntlzdm 0 102030405060708 => 0 +cntlzdm 0 a5b4c3d2e1f00918 => 0 +cntlzdm 0 fff7fffafff3fff1 => 0 +cntlzdm 0 7ff7000100030005 => 0 +cntlzdm 0 ffe7111022203330 => 0 +cntlzdm 0 0 => 0 + +cnttzdm 102030405060708 102030405060708 => 0 +cnttzdm 102030405060708 a5b4c3d2e1f00918 => 0 +cnttzdm 102030405060708 fff7fffafff3fff1 => 1 +cnttzdm 102030405060708 7ff7000100030005 => 4 +cnttzdm 102030405060708 ffe7111022203330 => 1 +cnttzdm 102030405060708 0 => d +cnttzdm a5b4c3d2e1f00918 102030405060708 => 0 +cnttzdm a5b4c3d2e1f00918 a5b4c3d2e1f00918 => 0 +cnttzdm a5b4c3d2e1f00918 fff7fffafff3fff1 => 1 +cnttzdm a5b4c3d2e1f00918 7ff7000100030005 => 14 +cnttzdm a5b4c3d2e1f00918 ffe7111022203330 => 1 +cnttzdm a5b4c3d2e1f00918 0 => 1c +cnttzdm fff7fffafff3fff1 102030405060708 => 5 +cnttzdm fff7fffafff3fff1 a5b4c3d2e1f00918 => 1 +cnttzdm fff7fffafff3fff1 fff7fffafff3fff1 => 0 +cnttzdm fff7fffafff3fff1 7ff7000100030005 => 0 +cnttzdm fff7fffafff3fff1 ffe7111022203330 => 1 +cnttzdm fff7fffafff3fff1 0 => 38 +cnttzdm 7ff7000100030005 102030405060708 => 3 +cnttzdm 7ff7000100030005 a5b4c3d2e1f00918 => 7 +cnttzdm 7ff7000100030005 fff7fffafff3fff1 => 0 +cnttzdm 7ff7000100030005 7ff7000100030005 => 0 +cnttzdm 7ff7000100030005 ffe7111022203330 => 5 +cnttzdm 7ff7000100030005 0 => 13 +cnttzdm ffe7111022203330 102030405060708 => 2 +cnttzdm ffe7111022203330 a5b4c3d2e1f00918 => 0 +cnttzdm ffe7111022203330 fff7fffafff3fff1 => 0 +cnttzdm ffe7111022203330 7ff7000100030005 => c +cnttzdm ffe7111022203330 ffe7111022203330 => 0 +cnttzdm ffe7111022203330 0 => 1a +cnttzdm 0 102030405060708 => 0 +cnttzdm 0 a5b4c3d2e1f00918 => 0 +cnttzdm 0 fff7fffafff3fff1 => 0 +cnttzdm 0 7ff7000100030005 => 0 +cnttzdm 0 ffe7111022203330 => 0 +cnttzdm 0 0 => 0 + paddi 0 102030405060708 => 102030405060708 paddi 0 a5b4c3d2e1f00918 => a5b4c3d2e1f00918 paddi 0 fff7fffafff3fff1 => fff7fffafff3fff1 @@ -47,6 +158,80 @@ paddi 98 7ff7000100030005 => 7ff7000100030067 paddi 98 ffe7111022203330 => ffe7111022203392 paddi 98 0 => 62 +pdepd 102030405060708 102030405060708 => 30400000400 +pdepd 102030405060708 a5b4c3d2e1f00918 => 2000400020400 +pdepd 102030405060708 fff7fffafff3fff1 => 102030405060008 +pdepd 102030405060708 7ff7000100030005 => 208 +pdepd 102030405060708 ffe7111022203330 => 100010400060000 +pdepd 102030405060708 0 => 0 +pdepd a5b4c3d2e1f00918 102030405060708 => 2100420061000800 +pdepd a5b4c3d2e1f00918 a5b4c3d2e1f00918 => 1b4000081100800 +pdepd a5b4c3d2e1f00918 fff7fffafff3fff1 => a5b403d2e1f00008 +pdepd a5b4c3d2e1f00918 7ff7000100030005 => 30000000108 +pdepd a5b4c3d2e1f00918 ffe7111022203330 => 410001221300000 +pdepd a5b4c3d2e1f00918 0 => 0 +pdepd fff7fffafff3fff1 102030405060708 => 2018200a0c03840 +pdepd fff7fffafff3fff1 a5b4c3d2e1f00918 => b4c1e9703e0048c0 +pdepd fff7fffafff3fff1 fff7fffafff3fff1 => f7f7fd7afe73ff81 +pdepd fff7fffafff3fff1 7ff7000100030005 => f700008000600021 +pdepd fff7fffafff3fff1 ffe7111022203330 => e710881044019980 +pdepd fff7fffafff3fff1 0 => 0 +pdepd 7ff7000100030005 102030405060708 => 6070000000020000 +pdepd 7ff7000100030005 a5b4c3d2e1f00918 => 90000100020000 +pdepd 7ff7000100030005 fff7fffafff3fff1 => 3ff7000100000001 +pdepd 7ff7000100030005 7ff7000100030005 => 3000000000010001 +pdepd 7ff7000100030005 ffe7111022203330 => 331000100000000 +pdepd 7ff7000100030005 0 => 0 +pdepd ffe7111022203330 102030405060708 => 4180011020000200 +pdepd ffe7111022203330 a5b4c3d2e1f00918 => 7c00100020001200 +pdepd ffe7111022203330 fff7fffafff3fff1 => fce7111022203010 +pdepd ffe7111022203330 7ff7000100030005 => c0000000000110 +pdepd ffe7111022203330 ffe7111022203330 => 8803001020003000 +pdepd ffe7111022203330 0 => 0 +pdepd 0 102030405060708 => 0 +pdepd 0 a5b4c3d2e1f00918 => 0 +pdepd 0 fff7fffafff3fff1 => 0 +pdepd 0 7ff7000100030005 => 0 +pdepd 0 ffe7111022203330 => 0 +pdepd 0 0 => 0 + +pextd 102030405060708 102030405060708 => 1fff +pextd 102030405060708 a5b4c3d2e1f00918 => 1643 +pextd 102030405060708 fff7fffafff3fff1 => 1ede +pextd 102030405060708 7ff7000100030005 => 1810 +pextd 102030405060708 ffe7111022203330 => 1a06 +pextd 102030405060708 0 => 0 +pextd a5b4c3d2e1f00918 102030405060708 => 1030105 +pextd a5b4c3d2e1f00918 a5b4c3d2e1f00918 => fffffff +pextd a5b4c3d2e1f00918 fff7fffafff3fff1 => ffffffe +pextd a5b4c3d2e1f00918 7ff7000100030005 => 7f00000 +pextd a5b4c3d2e1f00918 ffe7111022203330 => fd12226 +pextd a5b4c3d2e1f00918 0 => 0 +pextd fff7fffafff3fff1 102030405060708 => 10406002840e0 +pextd fff7fffafff3fff1 a5b4c3d2e1f00918 => a5b987af0f8122 +pextd fff7fffafff3fff1 fff7fffafff3fff1 => ffffffffffffff +pextd fff7fffafff3fff1 7ff7000100030005 => 7ffe0000006001 +pextd fff7fffafff3fff1 ffe7111022203330 => ffee2221110666 +pextd fff7fffafff3fff1 0 => 0 +pextd 7ff7000100030005 102030405060708 => 1048 +pextd 7ff7000100030005 a5b4c3d2e1f00918 => 25b80 +pextd 7ff7000100030005 fff7fffafff3fff1 => 7ffed +pextd 7ff7000100030005 7ff7000100030005 => 7ffff +pextd 7ff7000100030005 ffe7111022203330 => 7fee0 +pextd 7ff7000100030005 0 => 0 +pextd ffe7111022203330 102030405060708 => 4240c +pextd ffe7111022203330 a5b4c3d2e1f00918 => 296c745 +pextd ffe7111022203330 fff7fffafff3fff1 => 3ffffff +pextd ffe7111022203330 7ff7000100030005 => 1fff000 +pextd ffe7111022203330 ffe7111022203330 => 3ffffff +pextd ffe7111022203330 0 => 0 +pextd 0 102030405060708 => 0 +pextd 0 a5b4c3d2e1f00918 => 0 +pextd 0 fff7fffafff3fff1 => 0 +pextd 0 7ff7000100030005 => 0 +pextd 0 ffe7111022203330 => 0 +pextd 0 0 => 0 + plbz off0 (&buffer) => 59 plbz off8 (&buffer) => 7 @@ -336,4 +521,88 @@ setnbc 31_creb => [aaaaaaaa] 0 setnbc 31_crob => [55555555] ffffffffffffffff -All done. Tested 149 different instruction groups +vgnb 2 7f800000ff800000,ff8000007f800000 => f80078007800f800 +vgnb 2 ff8000007f800000,ff7ffffe7f7ffffe => f7ff77fff8007800 +vgnb 2 ff7ffffe7f7ffffe,0080000e8080000e => 8038803f7ff77ff +vgnb 2 0080000e8080000e,0180055e0180077e => 803081708038803 +vgnb 2 0180055e0180077e,0000111e8000222e => 3805708030817 +vgnb 2 0000111e8000222e,7ff0000000000000 => 7c00000000038057 +vgnb 2 7ff0000000000000,fff0000000000000 => fc0000007c000000 +vgnb 2 fff0000000000000,2208400000000000 => 52000000fc000000 +vgnb 2 2208400000000000,0000000000000009 => 252000000 +vgnb 2 0000000000000009,ffff000180000001 => ff00800000000002 +vgnb 2 ffff000180000001,0000000000000000 => ff008000 +vgnb 2 0000000000000000,8000000000000000 => 8000000000000000 +vgnb 2 8000000000000000,7f800000ff800000 => 7800f80080000000 + +vgnb 3 7f800000ff800000,ff8000007f800000 => e01c0380e0000000 +vgnb 3 ff8000007f800000,ff7ffffe7f7ffffe => fffffb8060000000 +vgnb 3 ff7ffffe7f7ffffe,0080000e8080000e => 200b7f7fe00000 +vgnb 3 0080000e8080000e,0180055e0180077e => 164388180200000 +vgnb 3 0180055e0180077e,0000111e8000222e => 60288501600000 +vgnb 3 0000111e8000222e,7ff0000000000000 => 7000000582200000 +vgnb 3 7ff0000000000000,fff0000000000000 => f00003c000000000 +vgnb 3 fff0000000000000,2208400000000000 => 280003c000000000 +vgnb 3 2208400000000000,0000000000000009 => e1000000000 +vgnb 3 0000000000000009,ffff000180000001 => fc00040000000000 +vgnb 3 ffff000180000001,0000000000000000 => 3e080000000 +vgnb 3 0000000000000000,8000000000000000 => 8000000000000000 +vgnb 3 8000000000000000,7f800000ff800000 => 601c000000000000 + +vgnb 4 7f800000ff800000,ff8000007f800000 => e06060e000000000 +vgnb 4 ff8000007f800000,ff7ffffe7f7ffffe => df5fe06000000000 +vgnb 4 ff7ffffe7f7ffffe,0080000e8080000e => 21a1df5f00000000 +vgnb 4 0080000e8080000e,0180055e0180077e => 212121a100000000 +vgnb 4 0180055e0180077e,0000111e8000222e => 181212100000000 +vgnb 4 0000111e8000222e,7ff0000000000000 => 6000018100000000 +vgnb 4 7ff0000000000000,fff0000000000000 => e000600000000000 +vgnb 4 fff0000000000000,2208400000000000 => 1000e00000000000 +vgnb 4 2208400000000000,0000000000000009 => 1100000000000 +vgnb 4 0000000000000009,ffff000180000001 => f080000100000000 +vgnb 4 ffff000180000001,0000000000000000 => f08000000000 +vgnb 4 0000000000000000,8000000000000000 => 8000000000000000 +vgnb 4 8000000000000000,7f800000ff800000 => 60e0800000000000 + +vgnb 5 7f800000ff800000,ff8000007f800000 => c186080000000000 +vgnb 5 ff8000007f800000,ff7ffffe7f7ffffe => ff7e080000000000 +vgnb 5 ff7ffffe7f7ffffe,0080000e8080000e => 28fefc000000000 +vgnb 5 0080000e8080000e,0180055e0180077e => 698004000000000 +vgnb 5 0180055e0180077e,0000111e8000222e => 228404000000000 +vgnb 5 0000111e8000222e,7ff0000000000000 => 6000004000000000 +vgnb 5 7ff0000000000000,fff0000000000000 => e007000000000000 +vgnb 5 fff0000000000000,2208400000000000 => 7000000000000 +vgnb 5 2208400000000000,0000000000000009 => a000000000000 +vgnb 5 0000000000000009,ffff000180000001 => f000000000000000 +vgnb 5 ffff000180000001,0000000000000000 => 7100000000000 +vgnb 5 0000000000000000,8000000000000000 => 8000000000000000 +vgnb 5 8000000000000000,7f800000ff800000 => 4180000000000000 + +vgnb 6 7f800000ff800000,ff8000007f800000 => c218c00000000000 +vgnb 6 ff8000007f800000,ff7ffffe7f7ffffe => fff8400000000000 +vgnb 6 ff7ffffe7f7ffffe,0080000e8080000e => 4377c0000000000 +vgnb 6 0080000e8080000e,0180055e0180077e => 468840000000000 +vgnb 6 0180055e0180077e,0000111e8000222e => 468040000000000 +vgnb 6 0000111e8000222e,7ff0000000000000 => 4000940000000000 +vgnb 6 7ff0000000000000,fff0000000000000 => c018000000000000 +vgnb 6 fff0000000000000,2208400000000000 => 6018000000000000 +vgnb 6 2208400000000000,0000000000000009 => 30000000000000 +vgnb 6 0000000000000009,ffff000180000001 => e000000000000000 +vgnb 6 ffff000180000001,0000000000000000 => 1c800000000000 +vgnb 6 0000000000000000,8000000000000000 => 8000000000000000 +vgnb 6 8000000000000000,7f800000ff800000 => 4200000000000000 + +vgnb 7 7f800000ff800000,ff8000007f800000 => c422000000000000 +vgnb 7 ff8000007f800000,ff7ffffe7f7ffffe => ffa2000000000000 +vgnb 7 ff7ffffe7f7ffffe,0080000e8080000e => 83fe00000000000 +vgnb 7 0080000e8080000e,0180055e0180077e => 5800200000000000 +vgnb 7 0180055e0180077e,0000111e8000222e => 804600000000000 +vgnb 7 0000111e8000222e,7ff0000000000000 => 4004200000000000 +vgnb 7 7ff0000000000000,fff0000000000000 => c020000000000000 +vgnb 7 fff0000000000000,2208400000000000 => 20000000000000 +vgnb 7 2208400000000000,0000000000000009 => 60000000000000 +vgnb 7 0000000000000009,ffff000180000001 => e040000000000000 +vgnb 7 ffff000180000001,0000000000000000 => 30000000000000 +vgnb 7 0000000000000000,8000000000000000 => 8000000000000000 +vgnb 7 8000000000000000,7f800000ff800000 => 4400000000000000 + +All done. Tested 160 different instruction groups diff --git a/none/tests/ppc64/test_isa_3_1_VRT.c b/none/tests/ppc64/test_isa_3_1_VRT.c index 70838887ab..955ddd18cd 100644 --- a/none/tests/ppc64/test_isa_3_1_VRT.c +++ b/none/tests/ppc64/test_isa_3_1_VRT.c @@ -303,6 +303,26 @@ static void test_vsrdbi_4 (void) { __asm__ __volatile__ ("vsrdbi %0, %1, %2, 4" : "=v" (vrt) : "v" (vra), "v" (vrb) ); } +static void test_vcfuged (void) { + __asm__ __volatile__ ("vcfuged %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vclzdm (void) { + __asm__ __volatile__ ("vclzdm %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vctzdm (void) { + __asm__ __volatile__ ("vctzdm %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vpdepd (void) { + __asm__ __volatile__ ("vpdepd %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vpextd (void) { + __asm__ __volatile__ ("vpextd %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} static void test_xscmpeqqp (void) { __asm__ __volatile__ ("xscmpeqqp %0, %1, %2" : "=v" (vrt) : "v" (vra), "v" (vrb) ); @@ -328,9 +348,12 @@ static test_list_t testgroup_generic[] = { { &test_dotted_vcmpequq, "vcmpequq.", "VRT,VRA,VRB"}, /* bcs */ { &test_dotted_vcmpgtsq, "vcmpgtsq.", "VRT,VRA,VRB"}, /* bcs */ { &test_dotted_vcmpgtuq, "vcmpgtuq.", "VRT,VRA,VRB"}, /* bcs */ + { &test_vcfuged, "vcfuged", "VRT,VRA,VRB"}, /* bcs */ + { &test_vclzdm, "vclzdm", "VRT,VRA,VRB"}, /* bcs */ { &test_vcmpequq, "vcmpequq", "VRT,VRA,VRB"}, /* bcs */ { &test_vcmpgtsq, "vcmpgtsq", "VRT,VRA,VRB"}, /* bcs */ { &test_vcmpgtuq, "vcmpgtuq", "VRT,VRA,VRB"}, /* bcs */ + { &test_vctzdm, "vctzdm", "VRT,VRA,VRB"}, /* bcs */ { &test_vdivesd, "vdivesd", "VRT,VRA,VRB"}, /* bcs */ { &test_vdivesw, "vdivesw", "VRT,VRA,VRB"}, /* bcs */ { &test_vdiveud, "vdiveud", "VRT,VRA,VRB"}, /* bcs */ @@ -379,6 +402,8 @@ static test_list_t testgroup_generic[] = { { &test_vmulld, "vmulld", "VRT,VRA,VRB"}, /* bcs */ { &test_vmulosd, "vmulosd", "VRT,VRA,VRB"}, /* bcs */ { &test_vmuloud, "vmuloud", "VRT,VRA,VRB"}, /* bcs */ + { &test_vpdepd, "vpdepd", "VRT,VRA,VRB"}, /* bcs */ + { &test_vpextd, "vpextd", "VRT,VRA,VRB"}, /* bcs */ { &test_vrlqmi, "vrlqmi", "VRT,VRA,VRB"}, /* bcs */ { &test_vrlqnm, "vrlqnm", "VRT,VRA,VRB"}, /* bcs */ { &test_vrlq, "vrlq", "VRT,VRA,VRB"}, /* bcs */ diff --git a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp index 560d7eae00..7890dc28ac 100644 --- a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp +++ b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp @@ -508,6 +508,346 @@ vcmpgtuq. 8000000000000000,7f800000ff800000 ffff000180000001,0000000000000000 => vcmpgtuq. 8000000000000000,7f800000ff800000 0000000000000000,8000000000000000 => [00000000]6:[0000] 0,0000000000000000 vcmpgtuq. 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => [00000000]6:[0000] 0,0000000000000000 +vcfuged 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 1ffff,000000000001ffff +vcfuged 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 97f800001fc00000,000001000000ffff +vcfuged 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => ff00000fe0000108,b3f800001fc00000 +vcfuged 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => fe0000fc000c0600,7f00000fe0000118 +vcfuged 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => ff80003fc0000000,7e0001fc000c0600 +vcfuged 7f800000ff800000,ff8000007f800000 0000111e8000222e,7ff0000000000000 => 800003fc000007f8,7f80003fc0000040 +vcfuged 7f800000ff800000,ff8000007f800000 7ff0000000000000,fff0000000000000 => 7f800000ff8,000007fc000007f8 +vcfuged 7f800000ff800000,ff8000007f800000 fff0000000000000,2208400000000000 => fe000007f800000c,00000ff8000007f8 +vcfuged 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => ff8000007f800000,7e00000ff800000c +vcfuged 7f800000ff800000,ff8000007f800000 0000000000000009,ffff000180000001 => 1fe000007fc00,7f800000ff800000 +vcfuged 7f800000ff800000,ff8000007f800000 ffff000180000001,0000000000000000 => ff8000007f800000,0001fe000003fc02 +vcfuged 7f800000ff800000,ff8000007f800000 0000000000000000,8000000000000000 => ff000000ff000001,7f800000ff800000 +vcfuged 7f800000ff800000,ff8000007f800000 8000000000000000,7f800000ff800000 => 800000000001feff,ff000001ff000000 +vcfuged ff8000007f800000,ff7ffffe7f7ffffe 7f800000ff800000,ff8000007f800000 => fffffcfffffdfefe,800000000001feff +vcfuged ff8000007f800000,ff7ffffe7f7ffffe ff8000007f800000,ff7ffffe7f7ffffe => 7ffffffffffffff,000000000001ffff +vcfuged ff8000007f800000,ff7ffffe7f7ffffe ff7ffffe7f7ffffe,0080000e8080000e => ffffffeffffffce7,97f800001fc00000 +vcfuged ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => fffffcffffebfdff,ff00000fe0000108 +vcfuged ff8000007f800000,ff7ffffe7f7ffffe 0180055e0180077e,0000111e8000222e => ff7fffbfbfffdfbf,fe0000fc000c0600 +vcfuged ff8000007f800000,ff7ffffe7f7ffffe 0000111e8000222e,7ff0000000000000 => fffff3fbfffff7f7,ff80003fc0000000 +vcfuged ff8000007f800000,ff7ffffe7f7ffffe 7ff0000000000000,fff0000000000000 => ffffe7f7ffffeff7,800003fc000007f8 +vcfuged ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => fdffffe7f7ffffef,000007f800000ff8 +vcfuged ff8000007f800000,ff7ffffe7f7ffffe 2208400000000000,0000000000000009 => ff7ffffe7f7ffffe,fe000007f800000c +vcfuged ff8000007f800000,ff7ffffe7f7ffffe 0000000000000009,ffff000180000001 => fffffdfffffffbf8,ff8000007f800000 +vcfuged ff8000007f800000,ff7ffffe7f7ffffe ffff000180000001,0000000000000000 => ff7ffffe7f7ffffe,0001fe000007fc00 +vcfuged ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => fefffffcfefffffd,ff8000007f800000 +vcfuged ff8000007f800000,ff7ffffe7f7ffffe 8000000000000000,7f800000ff800000 => fffffefffffdfcfe,ff000000ff000001 +vcfuged ff7ffffe7f7ffffe,0080000e8080000e 7f800000ff800000,ff8000007f800000 => 1d00001c0101,fffffefffffdfcfe +vcfuged ff7ffffe7f7ffffe,0080000e8080000e ff8000007f800000,ff7ffffe7f7ffffe => b0000000e0000007,fffffcfffffdfefe +vcfuged ff7ffffe7f7ffffe,0080000e8080000e ff7ffffe7f7ffffe,0080000e8080000e => 1ff,07ffffffffffffff +vcfuged ff7ffffe7f7ffffe,0080000e8080000e 0080000e8080000e,0180055e0180077e => 10000043a07,ffffffeffffffce7 +vcfuged ff7ffffe7f7ffffe,0080000e8080000e 0180055e0180077e,0000111e8000222e => 800000400003c7,fffffcffffebfdff +vcfuged ff7ffffe7f7ffffe,0080000e8080000e 0000111e8000222e,7ff0000000000000 => 740400007008,ff7fffbfbfffdfbf +vcfuged ff7ffffe7f7ffffe,0080000e8080000e 7ff0000000000000,fff0000000000000 => e8080000e008,fffff3fbfffff7f7 +vcfuged ff7ffffe7f7ffffe,0080000e8080000e fff0000000000000,2208400000000000 => 20000e8080000e0,ffffe7f7ffffeff7 +vcfuged ff7ffffe7f7ffffe,0080000e8080000e 2208400000000000,0000000000000009 => 80000e8080000e,fdffffe7f7ffffef +vcfuged ff7ffffe7f7ffffe,0080000e8080000e 0000000000000009,ffff000180000001 => e020000380402,ff7ffffe7f7ffffe +vcfuged ff7ffffe7f7ffffe,0080000e8080000e ffff000180000001,0000000000000000 => 80000e8080000e,fffffdfffffffbf8 +vcfuged ff7ffffe7f7ffffe,0080000e8080000e 0000000000000000,8000000000000000 => 100001d0100001c,ff7ffffe7f7ffffe +vcfuged ff7ffffe7f7ffffe,0080000e8080000e 8000000000000000,7f800000ff800000 => e00001c0301,fefffffcfefffffd +vcfuged 0080000e8080000e,0180055e0180077e 7f800000ff800000,ff8000007f800000 => abc000efc0303,00000e00001c0301 +vcfuged 0080000e8080000e,0180055e0180077e ff8000007f800000,ff7ffffe7f7ffffe => 90080055e04003bf,00001d00001c0101 +vcfuged 0080000e8080000e,0180055e0180077e ff7ffffe7f7ffffe,0080000e8080000e => 1000aa02001ddef,b0000000e0000007 +vcfuged 0080000e8080000e,0180055e0180077e 0080000e8080000e,0180055e0180077e => fffff,00000000000001ff +vcfuged 0080000e8080000e,0180055e0180077e 0180055e0180077e,0000111e8000222e => 1800900c006cf9f,0000010000043a07 +vcfuged 0080000e8080000e,0180055e0180077e 0000111e8000222e,7ff0000000000000 => 2af00c003bf018,00800000400003c7 +vcfuged 0080000e8080000e,0180055e0180077e 7ff0000000000000,fff0000000000000 => 55e0180077e018,0000740400007008 +vcfuged 0080000e8080000e,0180055e0180077e fff0000000000000,2208400000000000 => 60055e0180077e0,0000e8080000e008 +vcfuged 0080000e8080000e,0180055e0180077e 2208400000000000,0000000000000009 => 180055e0180077e,020000e8080000e0 +vcfuged 0080000e8080000e,0180055e0180077e 0000000000000009,ffff000180000001 => 55e06001df80c00,0080000e8080000e +vcfuged 0080000e8080000e,0180055e0180077e ffff000180000001,0000000000000000 => 180055e0180077e,000e020000380402 +vcfuged 0080000e8080000e,0180055e0180077e 0000000000000000,8000000000000000 => 3000abc03000efc,0080000e8080000e +vcfuged 0080000e8080000e,0180055e0180077e 8000000000000000,7f800000ff800000 => 55e000efc0603,0100001d0100001c +vcfuged 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => 223d00445c0000,00055e000efc0603 +vcfuged 0180055e0180077e,0000111e8000222e ff8000007f800000,ff7ffffe7f7ffffe => 20000111e0001117,000abc000efc0303 +vcfuged 0180055e0180077e,0000111e8000222e ff7ffffe7f7ffffe,0080000e8080000e => 2220000888f7,90080055e04003bf +vcfuged 0180055e0180077e,0000111e8000222e 0080000e8080000e,0180055e0180077e => 410001017897,01000aa02001ddef +vcfuged 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => 1fff,00000000000fffff +vcfuged 0180055e0180077e,0000111e8000222e 0000111e8000222e,7ff0000000000000 => 88f40001117000,01800900c006cf9f +vcfuged 0180055e0180077e,0000111e8000222e 7ff0000000000000,fff0000000000000 => 111e8000222e000,002af00c003bf018 +vcfuged 0180055e0180077e,0000111e8000222e fff0000000000000,2208400000000000 => 111e8000222e0,0055e0180077e018 +vcfuged 0180055e0180077e,0000111e8000222e 2208400000000000,0000000000000009 => 111e8000222e,060055e0180077e0 +vcfuged 0180055e0180077e,0000111e8000222e 0000000000000009,ffff000180000001 => 111e000088b80002,0180055e0180077e +vcfuged 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fff0000000000000,2208400000000000 0000000000000000,8000000000000000 => 1,0000000000000000 +vclzdm fff0000000000000,2208400000000000 8000000000000000,7f800000ff800000 => 1,0000000000000000 +vclzdm 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => 11,0000000000000001 +vclzdm 2208400000000000,0000000000000009 ff8000007f800000,ff7ffffe7f7ffffe => 38,0000000000000002 +vclzdm 2208400000000000,0000000000000009 ff7ffffe7f7ffffe,0080000e8080000e => 6,0000000000000002 +vclzdm 2208400000000000,0000000000000009 0080000e8080000e,0180055e0180077e => 11,0000000000000009 +vclzdm 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => a,0000000000000014 +vclzdm 2208400000000000,0000000000000009 0000111e8000222e,7ff0000000000000 => b,000000000000000d +vclzdm 2208400000000000,0000000000000009 7ff0000000000000,fff0000000000000 => c,0000000000000001 +vclzdm 2208400000000000,0000000000000009 fff0000000000000,2208400000000000 => 4,0000000000000002 +vclzdm 2208400000000000,0000000000000009 2208400000000000,0000000000000009 => 0,0000000000000000 +vclzdm 2208400000000000,0000000000000009 0000000000000009,ffff000180000001 => 12,0000000000000002 +vclzdm 2208400000000000,0000000000000009 ffff000180000001,0000000000000000 => 0,0000000000000002 +vclzdm 2208400000000000,0000000000000009 0000000000000000,8000000000000000 => 1,0000000000000000 +vclzdm 2208400000000000,0000000000000009 8000000000000000,7f800000ff800000 => 11,0000000000000001 +vclzdm 0000000000000009,ffff000180000001 7f800000ff800000,ff8000007f800000 => 0,0000000000000011 +vclzdm 0000000000000009,ffff000180000001 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000011 +vclzdm 0000000000000009,ffff000180000001 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000038 +vclzdm 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => 0,0000000000000006 +vclzdm 0000000000000009,ffff000180000001 0180055e0180077e,0000111e8000222e => 6,0000000000000011 +vclzdm 0000000000000009,ffff000180000001 0000111e8000222e,7ff0000000000000 => 0,000000000000000a +vclzdm 0000000000000009,ffff000180000001 7ff0000000000000,fff0000000000000 => 0,000000000000000b +vclzdm 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => 0,000000000000000c +vclzdm 0000000000000009,ffff000180000001 2208400000000000,0000000000000009 => 1,0000000000000004 +vclzdm 0000000000000009,ffff000180000001 0000000000000009,ffff000180000001 => 0,0000000000000000 +vclzdm 0000000000000009,ffff000180000001 ffff000180000001,0000000000000000 => 0,0000000000000012 +vclzdm 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => 0,0000000000000000 +vclzdm 0000000000000009,ffff000180000001 8000000000000000,7f800000ff800000 => 0,0000000000000001 +vclzdm ffff000180000001,0000000000000000 7f800000ff800000,ff8000007f800000 => 11,0000000000000000 +vclzdm ffff000180000001,0000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 3b,0000000000000000 +vclzdm ffff000180000001,0000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 9,0000000000000000 +vclzdm ffff000180000001,0000000000000000 0080000e8080000e,0180055e0180077e => 14,0000000000000000 +vclzdm ffff000180000001,0000000000000000 0180055e0180077e,0000111e8000222e => d,0000000000000000 +vclzdm ffff000180000001,0000000000000000 0000111e8000222e,7ff0000000000000 => b,0000000000000006 +vclzdm ffff000180000001,0000000000000000 7ff0000000000000,fff0000000000000 => c,0000000000000000 +vclzdm ffff000180000001,0000000000000000 fff0000000000000,2208400000000000 => 4,0000000000000000 +vclzdm ffff000180000001,0000000000000000 2208400000000000,0000000000000009 => 2,0000000000000000 +vclzdm ffff000180000001,0000000000000000 0000000000000009,ffff000180000001 => 13,0000000000000001 +vclzdm ffff000180000001,0000000000000000 ffff000180000001,0000000000000000 => 0,0000000000000000 +vclzdm ffff000180000001,0000000000000000 0000000000000000,8000000000000000 => 1,0000000000000000 +vclzdm ffff000180000001,0000000000000000 8000000000000000,7f800000ff800000 => 11,0000000000000000 +vclzdm 0000000000000000,8000000000000000 7f800000ff800000,ff8000007f800000 => 0,0000000000000011 +vclzdm 0000000000000000,8000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000011 +vclzdm 0000000000000000,8000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 9,000000000000003b +vclzdm 0000000000000000,8000000000000000 0080000e8080000e,0180055e0180077e => 14,0000000000000009 +vclzdm 0000000000000000,8000000000000000 0180055e0180077e,0000111e8000222e => d,0000000000000014 +vclzdm 0000000000000000,8000000000000000 0000111e8000222e,7ff0000000000000 => b,000000000000000d +vclzdm 0000000000000000,8000000000000000 7ff0000000000000,fff0000000000000 => 0,000000000000000b +vclzdm 0000000000000000,8000000000000000 fff0000000000000,2208400000000000 => 4,000000000000000c +vclzdm 0000000000000000,8000000000000000 2208400000000000,0000000000000009 => 2,0000000000000004 +vclzdm 0000000000000000,8000000000000000 0000000000000009,ffff000180000001 => 0,0000000000000002 +vclzdm 0000000000000000,8000000000000000 ffff000180000001,0000000000000000 => 0,0000000000000013 +vclzdm 0000000000000000,8000000000000000 0000000000000000,8000000000000000 => 0,0000000000000000 +vclzdm 0000000000000000,8000000000000000 8000000000000000,7f800000ff800000 => 11,0000000000000001 +vclzdm 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => 1,0000000000000011 +vclzdm 8000000000000000,7f800000ff800000 ff8000007f800000,ff7ffffe7f7ffffe => 1,0000000000000000 +vclzdm 8000000000000000,7f800000ff800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vclzdm 8000000000000000,7f800000ff800000 0080000e8080000e,0180055e0180077e => 0,0000000000000009 +vclzdm 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => 6,0000000000000014 +vclzdm 8000000000000000,7f800000ff800000 0000111e8000222e,7ff0000000000000 => 0,000000000000000d +vclzdm 8000000000000000,7f800000ff800000 7ff0000000000000,fff0000000000000 => 1,000000000000000b +vclzdm 8000000000000000,7f800000ff800000 fff0000000000000,2208400000000000 => 0,0000000000000000 +vclzdm 8000000000000000,7f800000ff800000 2208400000000000,0000000000000009 => 2,0000000000000004 +vclzdm 8000000000000000,7f800000ff800000 0000000000000009,ffff000180000001 => 1,0000000000000002 +vclzdm 8000000000000000,7f800000ff800000 ffff000180000001,0000000000000000 => 0,0000000000000000 +vclzdm 8000000000000000,7f800000ff800000 0000000000000000,8000000000000000 => 1,0000000000000000 +vclzdm 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => 0,0000000000000000 + vcmpequq 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ffffffffffffffff,ffffffffffffffff vcmpequq 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 vcmpequq 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 @@ -1018,6 +1358,176 @@ vcmpgtuq 8000000000000000,7f800000ff800000 ffff000180000001,0000000000000000 => vcmpgtuq 8000000000000000,7f800000ff800000 0000000000000000,8000000000000000 => 0,0000000000000000 vcmpgtuq 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => 0,0000000000000000 +vctzdm 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000... [truncated message content] |
|
From: Carl L. <ca...@so...> - 2020-11-09 23:47:24
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=62f62b7ce64cf7f29df9ecb5607ec3a47b38722f commit 62f62b7ce64cf7f29df9ecb5607ec3a47b38722f Author: Carl Love <ce...@us...> Date: Tue Oct 6 12:00:07 2020 -0500 128-bit Binary Integer Operation tests Diff: --- none/tests/ppc64/Makefile.am | 9 +- none/tests/ppc64/test_isa_3_1_Misc.c | 273 +++ none/tests/ppc64/test_isa_3_1_Misc.stderr.exp | 2 + none/tests/ppc64/test_isa_3_1_Misc.stdout.exp | 341 +++ none/tests/ppc64/test_isa_3_1_VRT.c | 87 + none/tests/ppc64/test_isa_3_1_VRT.stdout.exp | 2736 ++++++++++++++++++++++++- 6 files changed, 3443 insertions(+), 5 deletions(-) diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index 3490c5eb60..0a7fa77002 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -52,11 +52,10 @@ EXTRA_DIST = \ test_isa_3_1_RT.vgtest test_isa_3_1_RT.stderr.exp test_isa_3_1_RT.stdout.exp \ test_isa_3_1_XT.vgtest test_isa_3_1_XT.stderr.exp test_isa_3_1_XT.stdout.exp \ test_isa_3_1_VRT.vgtest test_isa_3_1_VRT.stderr.exp test_isa_3_1_VRT.stdout.exp \ - test_isa_3_1_Misc.vgtest \ + test_isa_3_1_Misc.vgtest test_isa_3_1_Misc.stderr.exp test_isa_3_1_Misc.stdout.exp \ test_isa_3_1_AT.vgtest \ subnormal_test.stderr.exp subnormal_test.stdout.exp \ subnormal_test.vgtest -# test_isa_3_1_Misc.vgtest test_isa_3_1_Misc.stderr.exp test_isa_3_1_Misc.stdout.exp # test_isa_3_1_AT.vgtest test_isa_3_1_AT.stderr.exp test_isa_3_1_AT.stdout.exp check_PROGRAMS = \ @@ -67,11 +66,12 @@ check_PROGRAMS = \ test_isa_2_07_part1 test_isa_2_07_part2 \ test_isa_3_0 \ test_isa_3_1_RT test_isa_3_1_XT test_isa_3_1_VRT \ + test_isa_3_1_Misc \ subnormal_test \ test_tm test_touch_tm ldst_multiple data-cache-instructions \ power6_mf_gpr std_reg_imm \ twi_tdi tw_td power6_bcmp -# test_isa_3_1_Misc test_isa_3_1_AT +# test_isa_3_1_AT AM_CFLAGS += @FLAG_M64@ AM_CXXFLAGS += @FLAG_M64@ @@ -82,9 +82,9 @@ allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@ test_isa_3_1_XT_SOURCES = test_isa_3_1_XT.c test_isa_3_1_common.c test_isa_3_1_RT_SOURCES = test_isa_3_1_RT.c test_isa_3_1_common.c test_isa_3_1_VRT_SOURCES = test_isa_3_1_VRT.c test_isa_3_1_common.c +test_isa_3_1_Misc_SOURCES = test_isa_3_1_Misc.c test_isa_3_1_common.c #test_isa_3_1_AT_SOURCES = test_isa_3_1_AT.c test_isa_3_1_common.c -#test_isa_3_1_Misc_SOURCES = test_isa_3_1_Misc.c test_isa_3_1_common.c if HAS_ALTIVEC BUILD_FLAG_ALTIVEC = -maltivec @@ -189,6 +189,7 @@ test_isa_3_1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_3_1_FL test_isa_3_1_RT_CFLAGS = $(test_isa_3_1_CFLAGS) test_isa_3_1_XT_CFLAGS = $(test_isa_3_1_CFLAGS) test_isa_3_1_VRT_CFLAGS = $(test_isa_3_1_CFLAGS) +test_isa_3_1_Misc_CFLAGS = $(test_isa_3_1_CFLAGS) subnormal_test_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) $(ISA_2_06_FLAG) \ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX) $(BUILD_FLAGS_ISA_2_06) diff --git a/none/tests/ppc64/test_isa_3_1_Misc.c b/none/tests/ppc64/test_isa_3_1_Misc.c new file mode 100644 index 0000000000..54db7e21be --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_Misc.c @@ -0,0 +1,273 @@ +/* + * Valgrind testcase for PowerPC ISA 3.1 + * + * Copyright (C) 2019-2020 Will Schmidt <wil...@vn...> + * + * 64bit build: + * gcc -Winline -Wall -g -O -mregnames -maltivec -m64 + */ + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <stdio.h> +#ifdef HAS_ISA_3_1 +#include <stdint.h> +#include <assert.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <altivec.h> +#include <malloc.h> + +#include <string.h> +#include <signal.h> +#include <setjmp.h> + +/* Condition Register fields. + These are used to capture the condition register values immediately after + the instruction under test is executed. This is done to help prevent other + test overhead (switch statements, result compares, etc) from disturbing + the test case results. */ +unsigned long current_cr; +unsigned long current_fpscr; + +struct test_list_t current_test; + +#include "isa_3_1_helpers.h" + +static void test_vcmpsq (void) { + SET_CR_ZERO; + __asm__ __volatile__ ("vcmpsq 3, %0, %1" :: "v" (vra), "v" (vrb) ); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_vcmpuq (void) { + SET_CR_ZERO; + __asm__ __volatile__ ("vcmpuq 3, %0, %1" :: "v" (vra), "v" (vrb) ); + GET_CR(current_cr); SET_CR_ZERO; +} + +static test_list_t testgroup_generic[] = { + { &test_vcmpsq, "vcmpsq", "BF,VRA,VRB"}, /* bcs */ + { &test_vcmpuq, "vcmpuq", "BF,VRA,VRB"}, /* bcs */ + { NULL, NULL }, +}; + +/* Allow skipping of tests. */ +unsigned long test_count=0xffff; +unsigned long skip_count=0; +unsigned long setup_only=0; + +/* Set up a setjmp/longjmp to gently handle our SIGILLs and SIGSEGVs. */ +static jmp_buf mybuf; + +/* This (testfunction_generic) is meant to handle all of the instruction + variations. The helpers set up the register and iterator values + as is appropriate for the instruction being tested. */ +static void testfunction_generic (const char* instruction_name, + test_func_t test_function, + unsigned int ignore_flags, + char * cur_form) { + + identify_form_components (instruction_name , cur_form); + debug_show_form (instruction_name, cur_form); + set_up_iterators (); + debug_show_iter_ranges (); + initialize_buffer (0); + debug_dump_buffer (); + + for (vrai = a_start; vrai < a_iters ; vrai+=a_inc) { + for (vrbi = b_start; vrbi < b_iters ; vrbi+=b_inc) { + for (vrci = c_start; vrci < c_iters ; vrci+=c_inc) { + for (vrmi = m_start; (vrmi < m_iters) ; vrmi+=m_inc) { + CHECK_OVERRIDES + debug_show_current_iteration (); + // Be sure to initialize the target registers first. + initialize_target_registers (); + initialize_source_registers (); + printf ("%s", instruction_name); + print_register_header (); + printf( " =>"); fflush (stdout); + if (!setup_only) { + if (enable_setjmp) { + if ( setjmp ( mybuf ) ) { + printf("signal tripped. (FIXME)\n"); + continue; + } + } + (*test_function) (); + } + print_register_footer (); + print_result_buffer (); + printf ("\n"); + } + } + } + } +} + +void mykillhandler ( int x ) { longjmp (mybuf, 1); } +void mysegvhandler ( int x ) { longjmp (mybuf, 1); } + +static void do_tests ( void ) +{ + int groupcount; + char * cur_form; + test_group_t group_function = &testfunction_generic; + test_list_t *tests = testgroup_generic; + + struct sigaction kill_action, segv_action; + struct sigaction old_kill_action, old_segv_action; + if (enable_setjmp) { + kill_action.sa_handler = mykillhandler; + segv_action.sa_handler = mysegvhandler; + sigemptyset ( &kill_action.sa_mask ); + sigemptyset ( &segv_action.sa_mask ); + kill_action.sa_flags = SA_NODEFER; + segv_action.sa_flags = SA_NODEFER; + sigaction ( SIGILL, &kill_action, &old_kill_action); + sigaction ( SIGSEGV, &segv_action, &old_segv_action); + } + + for (groupcount = 0; tests[groupcount].name != NULL; groupcount++) { + cur_form = strdup(tests[groupcount].form); + current_test = tests[groupcount]; + if (groupcount < skip_count) continue; + if (verbose) printf("Test #%d ,", groupcount); + if (verbose > 1) printf(" instruction %s (v=%d)", current_test.name, verbose); + (*group_function) (current_test.name, current_test.func, 0, cur_form ); + printf ("\n"); + if (groupcount >= (skip_count+test_count)) break; + } + if (debug_show_labels) printf("\n"); + printf ("All done. Tested %d different instruction groups\n", groupcount); +} + +static void usage (void) +{ + fprintf(stderr, + "Usage: test_isa_XXX [OPTIONS]\n" + "\t-h: display this help and exit\n" + "\t-v: increase verbosity\n" + "\t-a <foo> : limit number of a-iterations to <foo>\n" + "\t-b <foo> : limit number of b-iterations to <foo>\n" + "\t-c <foo> : limit number of c-iterations to <foo>\n" + "\t-n <foo> : limit to this number of tests.\n" + "\t-r <foo>: run only test # <foo> \n" + "\t\n" + "\t-j :enable setjmp to recover from illegal insns. \n" + "\t-m :(dev only?) lock VRM value to zero.\n" + "\t-z :(dev only?) lock MC value to zero.\n" + "\t-p :(dev only?) disable prefix instructions\n" + "\t-s <foo>: skip <foo> tests \n" + "\t-c <foo>: stop after running <foo> # of tests \n" + "\t-f : Do the test setup but do not actually execute the test instruction. \n" + ); +} + +int main (int argc, char **argv) +{ + int c; + while ((c = getopt(argc, argv, "dhjvmpfzs:a:b:c:n:r:")) != -1) { + switch (c) { + case 'h': + usage(); + return 0; + + case 'v': + verbose++; + break; + + /* Options related to limiting the test iterations. */ + case 'a': + a_limit=atoi (optarg); + printf ("limiting a-iters to %ld.\n", a_limit); + break; + case 'b': + b_limit=atoi (optarg); + printf ("limiting b-iters to %ld.\n", b_limit); + break; + case 'c': + c_limit=atoi (optarg); + printf ("limiting c-iters to %ld.\n", c_limit); + break; + case 'n': // run this number of tests. + test_count=atoi (optarg); + printf ("limiting to %ld tests\n", test_count); + break; + case 'r': // run just test #<foo>. + skip_count=atoi (optarg); + test_count=0; + if (verbose) printf("Running only test number %ld\n", skip_count); + break; + case 's': // skip this number of tests. + skip_count=atoi (optarg); + printf ("skipping %ld tests\n", skip_count); + break; + + /* debug options. */ + case 'd': + dump_tables=1; + printf("DEBUG:dump_tables.\n"); + break; + case 'f': + setup_only=1; + printf("DEBUG:setup_only.\n"); + break; + case 'j': + enable_setjmp=1; + printf ("DEBUG:setjmp enabled.\n"); + break; + case 'm': + vrm_override=1; + printf ("DEBUG:vrm override enabled.\n"); + break; + case 'p': + prefix_override=1; + printf ("DEBUG:prefix override enabled.\n"); + break; + case 'z': + mc_override=1; + printf ("DEBUG:MC override enabled.\n"); + break; + default: + usage(); + fprintf(stderr, "Unknown argument: '%c'\n", c); + } + } + + generic_prologue (); + build_vsx_table (); + build_args_table (); + build_float_vsx_tables (); + + if (dump_tables) { + dump_float_vsx_tables (); + dump_vsxargs (); + } + + do_tests (); + + return 0; +} + +#else // HAS_ISA_3_1 +int main (int argc, char **argv) +{ + printf("NO ISA 3.1 SUPPORT\n"); + return 0; +} +#endif diff --git a/none/tests/ppc64/test_isa_3_1_Misc.stderr.exp b/none/tests/ppc64/test_isa_3_1_Misc.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_Misc.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/test_isa_3_1_Misc.stdout.exp b/none/tests/ppc64/test_isa_3_1_Misc.stdout.exp new file mode 100644 index 0000000000..47b396aba5 --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_Misc.stdout.exp @@ -0,0 +1,341 @@ +vcmpsq 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => [00020000] +vcmpsq 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => [00040000] +vcmpsq 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => [00080000] +vcmpsq 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => [00080000] +vcmpsq 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => [00080000] +vcmpsq 7f800000ff800000,ff8000007f800000 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpsq 7f800000ff800000,ff8000007f800000 7ff0000000000000,fff0000000000000 => [00080000] +vcmpsq 7f800000ff800000,ff8000007f800000 fff0000000000000,2208400000000000 => [00080000] +vcmpsq 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => [00080000] +vcmpsq 7f800000ff800000,ff8000007f800000 0000000000000009,ffff000180000001 => [00080000] +vcmpsq 7f800000ff800000,ff8000007f800000 ffff000180000001,0000000000000000 => [00080000] +vcmpsq 7f800000ff800000,ff8000007f800000 0000000000000000,8000000000000000 => [00040000] +vcmpsq 7f800000ff800000,ff8000007f800000 8000000000000000,7f800000ff800000 => [00080000] +vcmpsq ff8000007f800000,ff7ffffe7f7ffffe 7f800000ff800000,ff8000007f800000 => [00080000] +vcmpsq ff8000007f800000,ff7ffffe7f7ffffe ff8000007f800000,ff7ffffe7f7ffffe => [00020000] +vcmpsq ff8000007f800000,ff7ffffe7f7ffffe ff7ffffe7f7ffffe,0080000e8080000e => [00080000] +vcmpsq ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [00080000] +vcmpsq ff8000007f800000,ff7ffffe7f7ffffe 0180055e0180077e,0000111e8000222e => [00080000] +vcmpsq ff8000007f800000,ff7ffffe7f7ffffe 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpsq ff8000007f800000,ff7ffffe7f7ffffe 7ff0000000000000,fff0000000000000 => [00080000] +vcmpsq ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [00080000] +vcmpsq ff8000007f800000,ff7ffffe7f7ffffe 2208400000000000,0000000000000009 => [00080000] +vcmpsq ff8000007f800000,ff7ffffe7f7ffffe 0000000000000009,ffff000180000001 => [00080000] +vcmpsq ff8000007f800000,ff7ffffe7f7ffffe ffff000180000001,0000000000000000 => [00080000] +vcmpsq ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [00040000] +vcmpsq ff8000007f800000,ff7ffffe7f7ffffe 8000000000000000,7f800000ff800000 => [00080000] +vcmpsq ff7ffffe7f7ffffe,0080000e8080000e 7f800000ff800000,ff8000007f800000 => [00040000] +vcmpsq ff7ffffe7f7ffffe,0080000e8080000e ff8000007f800000,ff7ffffe7f7ffffe => [00040000] +vcmpsq ff7ffffe7f7ffffe,0080000e8080000e ff7ffffe7f7ffffe,0080000e8080000e => [00020000] +vcmpsq ff7ffffe7f7ffffe,0080000e8080000e 0080000e8080000e,0180055e0180077e => [00080000] +vcmpsq ff7ffffe7f7ffffe,0080000e8080000e 0180055e0180077e,0000111e8000222e => [00040000] +vcmpsq ff7ffffe7f7ffffe,0080000e8080000e 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpsq ff7ffffe7f7ffffe,0080000e8080000e 7ff0000000000000,fff0000000000000 => [00040000] +vcmpsq ff7ffffe7f7ffffe,0080000e8080000e fff0000000000000,2208400000000000 => [00080000] +vcmpsq ff7ffffe7f7ffffe,0080000e8080000e 2208400000000000,0000000000000009 => [00040000] +vcmpsq ff7ffffe7f7ffffe,0080000e8080000e 0000000000000009,ffff000180000001 => [00040000] +vcmpsq ff7ffffe7f7ffffe,0080000e8080000e ffff000180000001,0000000000000000 => [00040000] +vcmpsq ff7ffffe7f7ffffe,0080000e8080000e 0000000000000000,8000000000000000 => [00040000] +vcmpsq ff7ffffe7f7ffffe,0080000e8080000e 8000000000000000,7f800000ff800000 => [00080000] +vcmpsq 0080000e8080000e,0180055e0180077e 7f800000ff800000,ff8000007f800000 => [00040000] +vcmpsq 0080000e8080000e,0180055e0180077e ff8000007f800000,ff7ffffe7f7ffffe => [00040000] +vcmpsq 0080000e8080000e,0180055e0180077e ff7ffffe7f7ffffe,0080000e8080000e => [00040000] +vcmpsq 0080000e8080000e,0180055e0180077e 0080000e8080000e,0180055e0180077e => [00020000] +vcmpsq 0080000e8080000e,0180055e0180077e 0180055e0180077e,0000111e8000222e => [00040000] +vcmpsq 0080000e8080000e,0180055e0180077e 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpsq 0080000e8080000e,0180055e0180077e 7ff0000000000000,fff0000000000000 => [00040000] +vcmpsq 0080000e8080000e,0180055e0180077e fff0000000000000,2208400000000000 => [00080000] +vcmpsq 0080000e8080000e,0180055e0180077e 2208400000000000,0000000000000009 => [00040000] +vcmpsq 0080000e8080000e,0180055e0180077e 0000000000000009,ffff000180000001 => [00040000] +vcmpsq 0080000e8080000e,0180055e0180077e ffff000180000001,0000000000000000 => [00040000] +vcmpsq 0080000e8080000e,0180055e0180077e 0000000000000000,8000000000000000 => [00040000] +vcmpsq 0080000e8080000e,0180055e0180077e 8000000000000000,7f800000ff800000 => [00080000] +vcmpsq 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => [00040000] +vcmpsq 0180055e0180077e,0000111e8000222e ff8000007f800000,ff7ffffe7f7ffffe => [00040000] +vcmpsq 0180055e0180077e,0000111e8000222e ff7ffffe7f7ffffe,0080000e8080000e => [00080000] +vcmpsq 0180055e0180077e,0000111e8000222e 0080000e8080000e,0180055e0180077e => [00080000] +vcmpsq 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => [00020000] +vcmpsq 0180055e0180077e,0000111e8000222e 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpsq 0180055e0180077e,0000111e8000222e 7ff0000000000000,fff0000000000000 => [00040000] +vcmpsq 0180055e0180077e,0000111e8000222e fff0000000000000,2208400000000000 => [00080000] +vcmpsq 0180055e0180077e,0000111e8000222e 2208400000000000,0000000000000009 => [00040000] +vcmpsq 0180055e0180077e,0000111e8000222e 0000000000000009,ffff000180000001 => [00040000] +vcmpsq 0180055e0180077e,0000111e8000222e ffff000180000001,0000000000000000 => [00040000] +vcmpsq 0180055e0180077e,0000111e8000222e 0000000000000000,8000000000000000 => [00040000] +vcmpsq 0180055e0180077e,0000111e8000222e 8000000000000000,7f800000ff800000 => [00080000] +vcmpsq 0000111e8000222e,7ff0000000000000 7f800000ff800000,ff8000007f800000 => [00040000] +vcmpsq 0000111e8000222e,7ff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00040000] +vcmpsq 0000111e8000222e,7ff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00040000] +vcmpsq 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [00040000] +vcmpsq 0000111e8000222e,7ff0000000000000 0180055e0180077e,0000111e8000222e => [00040000] +vcmpsq 0000111e8000222e,7ff0000000000000 0000111e8000222e,7ff0000000000000 => [00020000] +vcmpsq 0000111e8000222e,7ff0000000000000 7ff0000000000000,fff0000000000000 => [00040000] +vcmpsq 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [00040000] +vcmpsq 0000111e8000222e,7ff0000000000000 2208400000000000,0000000000000009 => [00040000] +vcmpsq 0000111e8000222e,7ff0000000000000 0000000000000009,ffff000180000001 => [00040000] +vcmpsq 0000111e8000222e,7ff0000000000000 ffff000180000001,0000000000000000 => [00040000] +vcmpsq 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [00040000] +vcmpsq 0000111e8000222e,7ff0000000000000 8000000000000000,7f800000ff800000 => [00040000] +vcmpsq 7ff0000000000000,fff0000000000000 7f800000ff800000,ff8000007f800000 => [00040000] +vcmpsq 7ff0000000000000,fff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00040000] +vcmpsq 7ff0000000000000,fff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00080000] +vcmpsq 7ff0000000000000,fff0000000000000 0080000e8080000e,0180055e0180077e => [00080000] +vcmpsq 7ff0000000000000,fff0000000000000 0180055e0180077e,0000111e8000222e => [00080000] +vcmpsq 7ff0000000000000,fff0000000000000 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpsq 7ff0000000000000,fff0000000000000 7ff0000000000000,fff0000000000000 => [00020000] +vcmpsq 7ff0000000000000,fff0000000000000 fff0000000000000,2208400000000000 => [00080000] +vcmpsq 7ff0000000000000,fff0000000000000 2208400000000000,0000000000000009 => [00080000] +vcmpsq 7ff0000000000000,fff0000000000000 0000000000000009,ffff000180000001 => [00080000] +vcmpsq 7ff0000000000000,fff0000000000000 ffff000180000001,0000000000000000 => [00080000] +vcmpsq 7ff0000000000000,fff0000000000000 0000000000000000,8000000000000000 => [00040000] +vcmpsq 7ff0000000000000,fff0000000000000 8000000000000000,7f800000ff800000 => [00080000] +vcmpsq fff0000000000000,2208400000000000 7f800000ff800000,ff8000007f800000 => [00040000] +vcmpsq fff0000000000000,2208400000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00040000] +vcmpsq fff0000000000000,2208400000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00040000] +vcmpsq fff0000000000000,2208400000000000 0080000e8080000e,0180055e0180077e => [00040000] +vcmpsq fff0000000000000,2208400000000000 0180055e0180077e,0000111e8000222e => [00040000] +vcmpsq fff0000000000000,2208400000000000 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpsq fff0000000000000,2208400000000000 7ff0000000000000,fff0000000000000 => [00040000] +vcmpsq fff0000000000000,2208400000000000 fff0000000000000,2208400000000000 => [00020000] +vcmpsq fff0000000000000,2208400000000000 2208400000000000,0000000000000009 => [00040000] +vcmpsq fff0000000000000,2208400000000000 0000000000000009,ffff000180000001 => [00040000] +vcmpsq fff0000000000000,2208400000000000 ffff000180000001,0000000000000000 => [00040000] +vcmpsq fff0000000000000,2208400000000000 0000000000000000,8000000000000000 => [00040000] +vcmpsq fff0000000000000,2208400000000000 8000000000000000,7f800000ff800000 => [00080000] +vcmpsq 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => [00040000] +vcmpsq 2208400000000000,0000000000000009 ff8000007f800000,ff7ffffe7f7ffffe => [00040000] +vcmpsq 2208400000000000,0000000000000009 ff7ffffe7f7ffffe,0080000e8080000e => [00080000] +vcmpsq 2208400000000000,0000000000000009 0080000e8080000e,0180055e0180077e => [00080000] +vcmpsq 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => [00080000] +vcmpsq 2208400000000000,0000000000000009 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpsq 2208400000000000,0000000000000009 7ff0000000000000,fff0000000000000 => [00040000] +vcmpsq 2208400000000000,0000000000000009 fff0000000000000,2208400000000000 => [00080000] +vcmpsq 2208400000000000,0000000000000009 2208400000000000,0000000000000009 => [00020000] +vcmpsq 2208400000000000,0000000000000009 0000000000000009,ffff000180000001 => [00040000] +vcmpsq 2208400000000000,0000000000000009 ffff000180000001,0000000000000000 => [00040000] +vcmpsq 2208400000000000,0000000000000009 0000000000000000,8000000000000000 => [00040000] +vcmpsq 2208400000000000,0000000000000009 8000000000000000,7f800000ff800000 => [00080000] +vcmpsq 0000000000000009,ffff000180000001 7f800000ff800000,ff8000007f800000 => [00040000] +vcmpsq 0000000000000009,ffff000180000001 ff8000007f800000,ff7ffffe7f7ffffe => [00040000] +vcmpsq 0000000000000009,ffff000180000001 ff7ffffe7f7ffffe,0080000e8080000e => [00080000] +vcmpsq 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [00080000] +vcmpsq 0000000000000009,ffff000180000001 0180055e0180077e,0000111e8000222e => [00080000] +vcmpsq 0000000000000009,ffff000180000001 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpsq 0000000000000009,ffff000180000001 7ff0000000000000,fff0000000000000 => [00040000] +vcmpsq 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [00080000] +vcmpsq 0000000000000009,ffff000180000001 2208400000000000,0000000000000009 => [00080000] +vcmpsq 0000000000000009,ffff000180000001 0000000000000009,ffff000180000001 => [00020000] +vcmpsq 0000000000000009,ffff000180000001 ffff000180000001,0000000000000000 => [00080000] +vcmpsq 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [00040000] +vcmpsq 0000000000000009,ffff000180000001 8000000000000000,7f800000ff800000 => [00080000] +vcmpsq ffff000180000001,0000000000000000 7f800000ff800000,ff8000007f800000 => [00040000] +vcmpsq ffff000180000001,0000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00040000] +vcmpsq ffff000180000001,0000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00080000] +vcmpsq ffff000180000001,0000000000000000 0080000e8080000e,0180055e0180077e => [00080000] +vcmpsq ffff000180000001,0000000000000000 0180055e0180077e,0000111e8000222e => [00080000] +vcmpsq ffff000180000001,0000000000000000 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpsq ffff000180000001,0000000000000000 7ff0000000000000,fff0000000000000 => [00040000] +vcmpsq ffff000180000001,0000000000000000 fff0000000000000,2208400000000000 => [00080000] +vcmpsq ffff000180000001,0000000000000000 2208400000000000,0000000000000009 => [00080000] +vcmpsq ffff000180000001,0000000000000000 0000000000000009,ffff000180000001 => [00040000] +vcmpsq ffff000180000001,0000000000000000 ffff000180000001,0000000000000000 => [00020000] +vcmpsq ffff000180000001,0000000000000000 0000000000000000,8000000000000000 => [00040000] +vcmpsq ffff000180000001,0000000000000000 8000000000000000,7f800000ff800000 => [00080000] +vcmpsq 0000000000000000,8000000000000000 7f800000ff800000,ff8000007f800000 => [00080000] +vcmpsq 0000000000000000,8000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00080000] +vcmpsq 0000000000000000,8000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00080000] +vcmpsq 0000000000000000,8000000000000000 0080000e8080000e,0180055e0180077e => [00080000] +vcmpsq 0000000000000000,8000000000000000 0180055e0180077e,0000111e8000222e => [00080000] +vcmpsq 0000000000000000,8000000000000000 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpsq 0000000000000000,8000000000000000 7ff0000000000000,fff0000000000000 => [00080000] +vcmpsq 0000000000000000,8000000000000000 fff0000000000000,2208400000000000 => [00080000] +vcmpsq 0000000000000000,8000000000000000 2208400000000000,0000000000000009 => [00080000] +vcmpsq 0000000000000000,8000000000000000 0000000000000009,ffff000180000001 => [00080000] +vcmpsq 0000000000000000,8000000000000000 ffff000180000001,0000000000000000 => [00080000] +vcmpsq 0000000000000000,8000000000000000 0000000000000000,8000000000000000 => [00020000] +vcmpsq 0000000000000000,8000000000000000 8000000000000000,7f800000ff800000 => [00080000] +vcmpsq 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => [00040000] +vcmpsq 8000000000000000,7f800000ff800000 ff8000007f800000,ff7ffffe7f7ffffe => [00040000] +vcmpsq 8000000000000000,7f800000ff800000 ff7ffffe7f7ffffe,0080000e8080000e => [00040000] +vcmpsq 8000000000000000,7f800000ff800000 0080000e8080000e,0180055e0180077e => [00040000] +vcmpsq 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => [00040000] +vcmpsq 8000000000000000,7f800000ff800000 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpsq 8000000000000000,7f800000ff800000 7ff0000000000000,fff0000000000000 => [00040000] +vcmpsq 8000000000000000,7f800000ff800000 fff0000000000000,2208400000000000 => [00040000] +vcmpsq 8000000000000000,7f800000ff800000 2208400000000000,0000000000000009 => [00040000] +vcmpsq 8000000000000000,7f800000ff800000 0000000000000009,ffff000180000001 => [00040000] +vcmpsq 8000000000000000,7f800000ff800000 ffff000180000001,0000000000000000 => [00040000] +vcmpsq 8000000000000000,7f800000ff800000 0000000000000000,8000000000000000 => [00040000] +vcmpsq 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => [00020000] + +vcmpuq 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => [00020000] +vcmpuq 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => [00040000] +vcmpuq 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => [00040000] +vcmpuq 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => [00040000] +vcmpuq 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => [00040000] +vcmpuq 7f800000ff800000,ff8000007f800000 0000111e8000222e,7ff0000000000000 => [00040000] +vcmpuq 7f800000ff800000,ff8000007f800000 7ff0000000000000,fff0000000000000 => [00080000] +vcmpuq 7f800000ff800000,ff8000007f800000 fff0000000000000,2208400000000000 => [00040000] +vcmpuq 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => [00040000] +vcmpuq 7f800000ff800000,ff8000007f800000 0000000000000009,ffff000180000001 => [00080000] +vcmpuq 7f800000ff800000,ff8000007f800000 ffff000180000001,0000000000000000 => [00040000] +vcmpuq 7f800000ff800000,ff8000007f800000 0000000000000000,8000000000000000 => [00040000] +vcmpuq 7f800000ff800000,ff8000007f800000 8000000000000000,7f800000ff800000 => [00040000] +vcmpuq ff8000007f800000,ff7ffffe7f7ffffe 7f800000ff800000,ff8000007f800000 => [00080000] +vcmpuq ff8000007f800000,ff7ffffe7f7ffffe ff8000007f800000,ff7ffffe7f7ffffe => [00020000] +vcmpuq ff8000007f800000,ff7ffffe7f7ffffe ff7ffffe7f7ffffe,0080000e8080000e => [00040000] +vcmpuq ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [00040000] +vcmpuq ff8000007f800000,ff7ffffe7f7ffffe 0180055e0180077e,0000111e8000222e => [00040000] +vcmpuq ff8000007f800000,ff7ffffe7f7ffffe 0000111e8000222e,7ff0000000000000 => [00040000] +vcmpuq ff8000007f800000,ff7ffffe7f7ffffe 7ff0000000000000,fff0000000000000 => [00080000] +vcmpuq ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [00040000] +vcmpuq ff8000007f800000,ff7ffffe7f7ffffe 2208400000000000,0000000000000009 => [00040000] +vcmpuq ff8000007f800000,ff7ffffe7f7ffffe 0000000000000009,ffff000180000001 => [00080000] +vcmpuq ff8000007f800000,ff7ffffe7f7ffffe ffff000180000001,0000000000000000 => [00040000] +vcmpuq ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [00040000] +vcmpuq ff8000007f800000,ff7ffffe7f7ffffe 8000000000000000,7f800000ff800000 => [00040000] +vcmpuq ff7ffffe7f7ffffe,0080000e8080000e 7f800000ff800000,ff8000007f800000 => [00080000] +vcmpuq ff7ffffe7f7ffffe,0080000e8080000e ff8000007f800000,ff7ffffe7f7ffffe => [00080000] +vcmpuq ff7ffffe7f7ffffe,0080000e8080000e ff7ffffe7f7ffffe,0080000e8080000e => [00020000] +vcmpuq ff7ffffe7f7ffffe,0080000e8080000e 0080000e8080000e,0180055e0180077e => [00080000] +vcmpuq ff7ffffe7f7ffffe,0080000e8080000e 0180055e0180077e,0000111e8000222e => [00040000] +vcmpuq ff7ffffe7f7ffffe,0080000e8080000e 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpuq ff7ffffe7f7ffffe,0080000e8080000e 7ff0000000000000,fff0000000000000 => [00080000] +vcmpuq ff7ffffe7f7ffffe,0080000e8080000e fff0000000000000,2208400000000000 => [00080000] +vcmpuq ff7ffffe7f7ffffe,0080000e8080000e 2208400000000000,0000000000000009 => [00040000] +vcmpuq ff7ffffe7f7ffffe,0080000e8080000e 0000000000000009,ffff000180000001 => [00080000] +vcmpuq ff7ffffe7f7ffffe,0080000e8080000e ffff000180000001,0000000000000000 => [00040000] +vcmpuq ff7ffffe7f7ffffe,0080000e8080000e 0000000000000000,8000000000000000 => [00080000] +vcmpuq ff7ffffe7f7ffffe,0080000e8080000e 8000000000000000,7f800000ff800000 => [00080000] +vcmpuq 0080000e8080000e,0180055e0180077e 7f800000ff800000,ff8000007f800000 => [00080000] +vcmpuq 0080000e8080000e,0180055e0180077e ff8000007f800000,ff7ffffe7f7ffffe => [00080000] +vcmpuq 0080000e8080000e,0180055e0180077e ff7ffffe7f7ffffe,0080000e8080000e => [00040000] +vcmpuq 0080000e8080000e,0180055e0180077e 0080000e8080000e,0180055e0180077e => [00020000] +vcmpuq 0080000e8080000e,0180055e0180077e 0180055e0180077e,0000111e8000222e => [00040000] +vcmpuq 0080000e8080000e,0180055e0180077e 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpuq 0080000e8080000e,0180055e0180077e 7ff0000000000000,fff0000000000000 => [00080000] +vcmpuq 0080000e8080000e,0180055e0180077e fff0000000000000,2208400000000000 => [00080000] +vcmpuq 0080000e8080000e,0180055e0180077e 2208400000000000,0000000000000009 => [00040000] +vcmpuq 0080000e8080000e,0180055e0180077e 0000000000000009,ffff000180000001 => [00080000] +vcmpuq 0080000e8080000e,0180055e0180077e ffff000180000001,0000000000000000 => [00040000] +vcmpuq 0080000e8080000e,0180055e0180077e 0000000000000000,8000000000000000 => [00080000] +vcmpuq 0080000e8080000e,0180055e0180077e 8000000000000000,7f800000ff800000 => [00080000] +vcmpuq 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => [00080000] +vcmpuq 0180055e0180077e,0000111e8000222e ff8000007f800000,ff7ffffe7f7ffffe => [00080000] +vcmpuq 0180055e0180077e,0000111e8000222e ff7ffffe7f7ffffe,0080000e8080000e => [00080000] +vcmpuq 0180055e0180077e,0000111e8000222e 0080000e8080000e,0180055e0180077e => [00080000] +vcmpuq 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => [00020000] +vcmpuq 0180055e0180077e,0000111e8000222e 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpuq 0180055e0180077e,0000111e8000222e 7ff0000000000000,fff0000000000000 => [00080000] +vcmpuq 0180055e0180077e,0000111e8000222e fff0000000000000,2208400000000000 => [00080000] +vcmpuq 0180055e0180077e,0000111e8000222e 2208400000000000,0000000000000009 => [00040000] +vcmpuq 0180055e0180077e,0000111e8000222e 0000000000000009,ffff000180000001 => [00080000] +vcmpuq 0180055e0180077e,0000111e8000222e ffff000180000001,0000000000000000 => [00040000] +vcmpuq 0180055e0180077e,0000111e8000222e 0000000000000000,8000000000000000 => [00080000] +vcmpuq 0180055e0180077e,0000111e8000222e 8000000000000000,7f800000ff800000 => [00080000] +vcmpuq 0000111e8000222e,7ff0000000000000 7f800000ff800000,ff8000007f800000 => [00080000] +vcmpuq 0000111e8000222e,7ff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00080000] +vcmpuq 0000111e8000222e,7ff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00040000] +vcmpuq 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [00040000] +vcmpuq 0000111e8000222e,7ff0000000000000 0180055e0180077e,0000111e8000222e => [00040000] +vcmpuq 0000111e8000222e,7ff0000000000000 0000111e8000222e,7ff0000000000000 => [00020000] +vcmpuq 0000111e8000222e,7ff0000000000000 7ff0000000000000,fff0000000000000 => [00080000] +vcmpuq 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [00040000] +vcmpuq 0000111e8000222e,7ff0000000000000 2208400000000000,0000000000000009 => [00040000] +vcmpuq 0000111e8000222e,7ff0000000000000 0000000000000009,ffff000180000001 => [00080000] +vcmpuq 0000111e8000222e,7ff0000000000000 ffff000180000001,0000000000000000 => [00040000] +vcmpuq 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [00080000] +vcmpuq 0000111e8000222e,7ff0000000000000 8000000000000000,7f800000ff800000 => [00040000] +vcmpuq 7ff0000000000000,fff0000000000000 7f800000ff800000,ff8000007f800000 => [00040000] +vcmpuq 7ff0000000000000,fff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00040000] +vcmpuq 7ff0000000000000,fff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00040000] +vcmpuq 7ff0000000000000,fff0000000000000 0080000e8080000e,0180055e0180077e => [00040000] +vcmpuq 7ff0000000000000,fff0000000000000 0180055e0180077e,0000111e8000222e => [00040000] +vcmpuq 7ff0000000000000,fff0000000000000 0000111e8000222e,7ff0000000000000 => [00040000] +vcmpuq 7ff0000000000000,fff0000000000000 7ff0000000000000,fff0000000000000 => [00020000] +vcmpuq 7ff0000000000000,fff0000000000000 fff0000000000000,2208400000000000 => [00040000] +vcmpuq 7ff0000000000000,fff0000000000000 2208400000000000,0000000000000009 => [00040000] +vcmpuq 7ff0000000000000,fff0000000000000 0000000000000009,ffff000180000001 => [00080000] +vcmpuq 7ff0000000000000,fff0000000000000 ffff000180000001,0000000000000000 => [00040000] +vcmpuq 7ff0000000000000,fff0000000000000 0000000000000000,8000000000000000 => [00040000] +vcmpuq 7ff0000000000000,fff0000000000000 8000000000000000,7f800000ff800000 => [00040000] +vcmpuq fff0000000000000,2208400000000000 7f800000ff800000,ff8000007f800000 => [00080000] +vcmpuq fff0000000000000,2208400000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00080000] +vcmpuq fff0000000000000,2208400000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00040000] +vcmpuq fff0000000000000,2208400000000000 0080000e8080000e,0180055e0180077e => [00040000] +vcmpuq fff0000000000000,2208400000000000 0180055e0180077e,0000111e8000222e => [00040000] +vcmpuq fff0000000000000,2208400000000000 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpuq fff0000000000000,2208400000000000 7ff0000000000000,fff0000000000000 => [00080000] +vcmpuq fff0000000000000,2208400000000000 fff0000000000000,2208400000000000 => [00020000] +vcmpuq fff0000000000000,2208400000000000 2208400000000000,0000000000000009 => [00040000] +vcmpuq fff0000000000000,2208400000000000 0000000000000009,ffff000180000001 => [00080000] +vcmpuq fff0000000000000,2208400000000000 ffff000180000001,0000000000000000 => [00040000] +vcmpuq fff0000000000000,2208400000000000 0000000000000000,8000000000000000 => [00080000] +vcmpuq fff0000000000000,2208400000000000 8000000000000000,7f800000ff800000 => [00080000] +vcmpuq 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => [00080000] +vcmpuq 2208400000000000,0000000000000009 ff8000007f800000,ff7ffffe7f7ffffe => [00080000] +vcmpuq 2208400000000000,0000000000000009 ff7ffffe7f7ffffe,0080000e8080000e => [00080000] +vcmpuq 2208400000000000,0000000000000009 0080000e8080000e,0180055e0180077e => [00080000] +vcmpuq 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => [00080000] +vcmpuq 2208400000000000,0000000000000009 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpuq 2208400000000000,0000000000000009 7ff0000000000000,fff0000000000000 => [00080000] +vcmpuq 2208400000000000,0000000000000009 fff0000000000000,2208400000000000 => [00080000] +vcmpuq 2208400000000000,0000000000000009 2208400000000000,0000000000000009 => [00020000] +vcmpuq 2208400000000000,0000000000000009 0000000000000009,ffff000180000001 => [00080000] +vcmpuq 2208400000000000,0000000000000009 ffff000180000001,0000000000000000 => [00040000] +vcmpuq 2208400000000000,0000000000000009 0000000000000000,8000000000000000 => [00080000] +vcmpuq 2208400000000000,0000000000000009 8000000000000000,7f800000ff800000 => [00080000] +vcmpuq 0000000000000009,ffff000180000001 7f800000ff800000,ff8000007f800000 => [00040000] +vcmpuq 0000000000000009,ffff000180000001 ff8000007f800000,ff7ffffe7f7ffffe => [00040000] +vcmpuq 0000000000000009,ffff000180000001 ff7ffffe7f7ffffe,0080000e8080000e => [00040000] +vcmpuq 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => [00040000] +vcmpuq 0000000000000009,ffff000180000001 0180055e0180077e,0000111e8000222e => [00040000] +vcmpuq 0000000000000009,ffff000180000001 0000111e8000222e,7ff0000000000000 => [00040000] +vcmpuq 0000000000000009,ffff000180000001 7ff0000000000000,fff0000000000000 => [00040000] +vcmpuq 0000000000000009,ffff000180000001 fff0000000000000,2208400000000000 => [00040000] +vcmpuq 0000000000000009,ffff000180000001 2208400000000000,0000000000000009 => [00040000] +vcmpuq 0000000000000009,ffff000180000001 0000000000000009,ffff000180000001 => [00020000] +vcmpuq 0000000000000009,ffff000180000001 ffff000180000001,0000000000000000 => [00040000] +vcmpuq 0000000000000009,ffff000180000001 0000000000000000,8000000000000000 => [00040000] +vcmpuq 0000000000000009,ffff000180000001 8000000000000000,7f800000ff800000 => [00040000] +vcmpuq ffff000180000001,0000000000000000 7f800000ff800000,ff8000007f800000 => [00080000] +vcmpuq ffff000180000001,0000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00080000] +vcmpuq ffff000180000001,0000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00080000] +vcmpuq ffff000180000001,0000000000000000 0080000e8080000e,0180055e0180077e => [00080000] +vcmpuq ffff000180000001,0000000000000000 0180055e0180077e,0000111e8000222e => [00080000] +vcmpuq ffff000180000001,0000000000000000 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpuq ffff000180000001,0000000000000000 7ff0000000000000,fff0000000000000 => [00080000] +vcmpuq ffff000180000001,0000000000000000 fff0000000000000,2208400000000000 => [00080000] +vcmpuq ffff000180000001,0000000000000000 2208400000000000,0000000000000009 => [00080000] +vcmpuq ffff000180000001,0000000000000000 0000000000000009,ffff000180000001 => [00080000] +vcmpuq ffff000180000001,0000000000000000 ffff000180000001,0000000000000000 => [00020000] +vcmpuq ffff000180000001,0000000000000000 0000000000000000,8000000000000000 => [00080000] +vcmpuq ffff000180000001,0000000000000000 8000000000000000,7f800000ff800000 => [00080000] +vcmpuq 0000000000000000,8000000000000000 7f800000ff800000,ff8000007f800000 => [00080000] +vcmpuq 0000000000000000,8000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00080000] +vcmpuq 0000000000000000,8000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00040000] +vcmpuq 0000000000000000,8000000000000000 0080000e8080000e,0180055e0180077e => [00040000] +vcmpuq 0000000000000000,8000000000000000 0180055e0180077e,0000111e8000222e => [00040000] +vcmpuq 0000000000000000,8000000000000000 0000111e8000222e,7ff0000000000000 => [00040000] +vcmpuq 0000000000000000,8000000000000000 7ff0000000000000,fff0000000000000 => [00080000] +vcmpuq 0000000000000000,8000000000000000 fff0000000000000,2208400000000000 => [00040000] +vcmpuq 0000000000000000,8000000000000000 2208400000000000,0000000000000009 => [00040000] +vcmpuq 0000000000000000,8000000000000000 0000000000000009,ffff000180000001 => [00080000] +vcmpuq 0000000000000000,8000000000000000 ffff000180000001,0000000000000000 => [00040000] +vcmpuq 0000000000000000,8000000000000000 0000000000000000,8000000000000000 => [00020000] +vcmpuq 0000000000000000,8000000000000000 8000000000000000,7f800000ff800000 => [00040000] +vcmpuq 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => [00080000] +vcmpuq 8000000000000000,7f800000ff800000 ff8000007f800000,ff7ffffe7f7ffffe => [00080000] +vcmpuq 8000000000000000,7f800000ff800000 ff7ffffe7f7ffffe,0080000e8080000e => [00040000] +vcmpuq 8000000000000000,7f800000ff800000 0080000e8080000e,0180055e0180077e => [00040000] +vcmpuq 8000000000000000,7f800000ff800000 0180055e0180077e,0000111e8000222e => [00040000] +vcmpuq 8000000000000000,7f800000ff800000 0000111e8000222e,7ff0000000000000 => [00080000] +vcmpuq 8000000000000000,7f800000ff800000 7ff0000000000000,fff0000000000000 => [00080000] +vcmpuq 8000000000000000,7f800000ff800000 fff0000000000000,2208400000000000 => [00040000] +vcmpuq 8000000000000000,7f800000ff800000 2208400000000000,0000000000000009 => [00040000] +vcmpuq 8000000000000000,7f800000ff800000 0000000000000009,ffff000180000001 => [00080000] +vcmpuq 8000000000000000,7f800000ff800000 ffff000180000001,0000000000000000 => [00040000] +vcmpuq 8000000000000000,7f800000ff800000 0000000000000000,8000000000000000 => [00080000] +vcmpuq 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => [00020000] + +All done. Tested 2 different instruction groups diff --git a/none/tests/ppc64/test_isa_3_1_VRT.c b/none/tests/ppc64/test_isa_3_1_VRT.c index a801d403cb..70838887ab 100644 --- a/none/tests/ppc64/test_isa_3_1_VRT.c +++ b/none/tests/ppc64/test_isa_3_1_VRT.c @@ -117,6 +117,76 @@ static void test_vmodud (void) { __asm__ __volatile__ ("vmodud %0, %1, %2" : "=v" (vrt) : "v" (vra), "v" (vrb) ); } +static void test_vmulesd (void) { + __asm__ __volatile__ ("vmulesd %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vmuleud (void) { + __asm__ __volatile__ ("vmuleud %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vmulosd (void) { + __asm__ __volatile__ ("vmulosd %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vmuloud (void) { + __asm__ __volatile__ ("vmuloud %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vextsd2q (void) { + __asm__ __volatile__ ("vextsd2q %0, %1 " : "=v" (vrt) : "v" (vrb) ); +} +static void test_vcmpequq (void) { + __asm__ __volatile__ ("vcmpequq %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_dotted_vcmpequq (void) { + SET_CR_ZERO; + __asm__ __volatile__ ("vcmpequq %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_vcmpgtsq (void) { + __asm__ __volatile__ ("vcmpgtsq %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_dotted_vcmpgtsq (void) { + SET_CR_ZERO; + __asm__ __volatile__ ("vcmpgtsq %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_vcmpgtuq (void) { + __asm__ __volatile__ ("vcmpgtuq %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_dotted_vcmpgtuq (void) { + SET_CR_ZERO; + __asm__ __volatile__ ("vcmpgtuq %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_vrlq (void) { + __asm__ __volatile__ ("vrlq %0, %1, %2" : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vrlqmi (void) { + __asm__ __volatile__ ("vrlqmi %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vrlqnm (void) { + __asm__ __volatile__ ("vrlqnm %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vslq (void) { + __asm__ __volatile__ ("vslq %0, %1, %2" : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vsraq (void) { + __asm__ __volatile__ ("vsraq %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vsrq (void) { + __asm__ __volatile__ ("vsrq %0, %1, %2" : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} static void test_vextdubvlx (void) { __asm__ __volatile__ ("vextdubvlx %0, %1, %2, %3" : "=v" (vrt) : "v" (vra), "v" (vrb), "r" (rc) ); @@ -255,6 +325,12 @@ static void test_xsmincqp (void) { } static test_list_t testgroup_generic[] = { + { &test_dotted_vcmpequq, "vcmpequq.", "VRT,VRA,VRB"}, /* bcs */ + { &test_dotted_vcmpgtsq, "vcmpgtsq.", "VRT,VRA,VRB"}, /* bcs */ + { &test_dotted_vcmpgtuq, "vcmpgtuq.", "VRT,VRA,VRB"}, /* bcs */ + { &test_vcmpequq, "vcmpequq", "VRT,VRA,VRB"}, /* bcs */ + { &test_vcmpgtsq, "vcmpgtsq", "VRT,VRA,VRB"}, /* bcs */ + { &test_vcmpgtuq, "vcmpgtuq", "VRT,VRA,VRB"}, /* bcs */ { &test_vdivesd, "vdivesd", "VRT,VRA,VRB"}, /* bcs */ { &test_vdivesw, "vdivesw", "VRT,VRA,VRB"}, /* bcs */ { &test_vdiveud, "vdiveud", "VRT,VRA,VRB"}, /* bcs */ @@ -271,6 +347,7 @@ static test_list_t testgroup_generic[] = { { &test_vextduhvrx, "vextduhvrx", "VRT,VRA,VRB,RC"}, /* bcs */ { &test_vextduwvlx, "vextduwvlx", "VRT,VRA,VRB,RC"}, /* bcs */ { &test_vextduwvrx, "vextduwvrx", "VRT,VRA,VRB,RC"}, /* bcs */ + { &test_vextsd2q, "vextsd2q", "VRT,VRB"}, /* bcs */ { &test_vinsblx, "vinsblx", "VRT,RA,RB"}, /* bcs */ { &test_vinsbrx, "vinsbrx", "VRT,RA,RB"}, /* bcs */ { &test_vinsbvlx, "vinsbvlx", "VRT,RA,VRB"}, /* bcs */ @@ -293,15 +370,25 @@ static test_list_t testgroup_generic[] = { { &test_vmodsw, "vmodsw", "VRT,VRA,VRB"}, /* bcs */ { &test_vmodud, "vmodud", "VRT,VRA,VRB"}, /* bcs */ { &test_vmoduw, "vmoduw", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmulesd, "vmulesd", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmuleud, "vmuleud", "VRT,VRA,VRB"}, /* bcs */ { &test_vmulhsd, "vmulhsd", "VRT,VRA,VRB"}, /* bcs */ { &test_vmulhsw, "vmulhsw", "VRT,VRA,VRB"}, /* bcs */ { &test_vmulhud, "vmulhud", "VRT,VRA,VRB"}, /* bcs */ { &test_vmulhuw, "vmulhuw", "VRT,VRA,VRB"}, /* bcs */ { &test_vmulld, "vmulld", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmulosd, "vmulosd", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmuloud, "vmuloud", "VRT,VRA,VRB"}, /* bcs */ + { &test_vrlqmi, "vrlqmi", "VRT,VRA,VRB"}, /* bcs */ + { &test_vrlqnm, "vrlqnm", "VRT,VRA,VRB"}, /* bcs */ + { &test_vrlq, "vrlq", "VRT,VRA,VRB"}, /* bcs */ { &test_vsldbi_0, "vsldbi 0", "VRT,VRA,VRB,SH"}, /* bcwp */ { &test_vsldbi_4, "vsldbi 4", "VRT,VRA,VRB,SH"}, /* bcwp */ + { &test_vslq, "vslq", "VRT,VRA,VRB"}, /* bcs */ + { &test_vsraq, "vsraq", "VRT,VRA,VRB"}, /* bcs */ { &test_vsrdbi_0, "vsrdbi 0", "VRT,VRA,VRB,SH"}, /* bcwp */ { &test_vsrdbi_4, "vsrdbi 4", "VRT,VRA,VRB,SH"}, /* bcwp */ + { &test_vsrq, "vsrq", "VRT,VRA,VRB"}, /* bcs */ { &test_xscmpeqqp, "xscmpeqqp", "VRT,VRA,VRB"}, /* bcs */ { &test_xscmpgeqp, "xscmpgeqp", "VRT,VRA,VRB"}, /* bcs */ { &test_xscmpgtqp, "xscmpgtqp", "VRT,VRA,VRB"}, /* bcs */ diff --git a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp index 579dcdcc09..560d7eae00 100644 --- a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp +++ b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp @@ -1,3 +1,1023 @@ +vcmpequq. 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff +vcmpequq. 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7f800000ff800000,ff8000007f800000 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7f800000ff800000,ff8000007f800000 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7f800000ff800000,ff8000007f800000 fff0000000000000,2208400000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7f800000ff800000,ff8000007f800000 0000000000000009,ffff000180000001 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7f800000ff800000,ff8000007f800000 ffff000180000001,0000000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7f800000ff800000,ff8000007f800000 0000000000000000,8000000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7f800000ff800000,ff8000007f800000 8000000000000000,7f800000ff800000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff +vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 0180055e0180077e,0000111e8000222e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 2208400000000000,0000000000000009 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 0000000000000009,ffff000180000001 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe ffff000180000001,0000000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff8000007f800000,ff7ffffe7f7ffffe 8000000000000000,7f800000ff800000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff +vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e 0080000e8080000e,0180055e0180077e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e 0180055e0180077e,0000111e8000222e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e fff0000000000000,2208400000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e 2208400000000000,0000000000000009 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e 0000000000000009,ffff000180000001 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e ffff000180000001,0000000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e 0000000000000000,8000000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. ff7ffffe7f7ffffe,0080000e8080000e 8000000000000000,7f800000ff800000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0080000e8080000e,0180055e0180077e 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0080000e8080000e,0180055e0180077e ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0080000e8080000e,0180055e0180077e ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0080000e8080000e,0180055e0180077e 0080000e8080000e,0180055e0180077e => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff +vcmpequq. 0080000e8080000e,0180055e0180077e 0180055e0180077e,0000111e8000222e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0080000e8080000e,0180055e0180077e 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0080000e8080000e,0180055e0180077e 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0080000e8080000e,0180055e0180077e fff0000000000000,2208400000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0080000e8080000e,0180055e0180077e 2208400000000000,0000000000000009 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0080000e8080000e,0180055e0180077e 0000000000000009,ffff000180000001 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0080000e8080000e,0180055e0180077e ffff000180000001,0000000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0080000e8080000e,0180055e0180077e 0000000000000000,8000000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0080000e8080000e,0180055e0180077e 8000000000000000,7f800000ff800000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0180055e0180077e,0000111e8000222e ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0180055e0180077e,0000111e8000222e ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0180055e0180077e,0000111e8000222e 0080000e8080000e,0180055e0180077e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff +vcmpequq. 0180055e0180077e,0000111e8000222e 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0180055e0180077e,0000111e8000222e 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0180055e0180077e,0000111e8000222e fff0000000000000,2208400000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0180055e0180077e,0000111e8000222e 2208400000000000,0000000000000009 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0180055e0180077e,0000111e8000222e 0000000000000009,ffff000180000001 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0180055e0180077e,0000111e8000222e ffff000180000001,0000000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0180055e0180077e,0000111e8000222e 0000000000000000,8000000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0180055e0180077e,0000111e8000222e 8000000000000000,7f800000ff800000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0000111e8000222e,7ff0000000000000 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0000111e8000222e,7ff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0000111e8000222e,7ff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0000111e8000222e,7ff0000000000000 0180055e0180077e,0000111e8000222e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0000111e8000222e,7ff0000000000000 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff +vcmpequq. 0000111e8000222e,7ff0000000000000 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0000111e8000222e,7ff0000000000000 fff0000000000000,2208400000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0000111e8000222e,7ff0000000000000 2208400000000000,0000000000000009 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0000111e8000222e,7ff0000000000000 0000000000000009,ffff000180000001 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0000111e8000222e,7ff0000000000000 ffff000180000001,0000000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0000111e8000222e,7ff0000000000000 0000000000000000,8000000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 0000111e8000222e,7ff0000000000000 8000000000000000,7f800000ff800000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7ff0000000000000,fff0000000000000 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7ff0000000000000,fff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7ff0000000000000,fff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7ff0000000000000,fff0000000000000 0080000e8080000e,0180055e0180077e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7ff0000000000000,fff0000000000000 0180055e0180077e,0000111e8000222e => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7ff0000000000000,fff0000000000000 0000111e8000222e,7ff0000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7ff0000000000000,fff0000000000000 7ff0000000000000,fff0000000000000 => [00000000]6:[0000] ffffffffffffffff,ffffffffffffffff +vcmpequq. 7ff0000000000000,fff0000000000000 fff0000000000000,2208400000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7ff0000000000000,fff0000000000000 2208400000000000,0000000000000009 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7ff0000000000000,fff0000000000000 0000000000000009,ffff000180000001 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7ff0000000000000,fff0000000000000 ffff000180000001,0000000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7ff0000000000000,fff0000000000000 0000000000000000,8000000000000000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. 7ff0000000000000,fff0000000000000 8000000000000000,7f800000ff800000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. fff0000000000000,2208400000000000 7f800000ff800000,ff8000007f800000 => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. fff0000000000000,2208400000000000 ff8000007f800000,ff7ffffe7f7ffffe => [00000000]6:[0000] 0,0000000000000000 +vcmpequq. fff0000000000000,2208400000000000 ff7ffffe7f7ffffe,0080000e8080000e => [00000000]6:[0000] 0,0000000000000000 +vcm... [truncated message content] |
|
From: Carl L. <ca...@so...> - 2020-11-09 23:47:05
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=7a52b46d1a5c306ed16acc5c006969fce5144683 commit 7a52b46d1a5c306ed16acc5c006969fce5144683 Author: Carl Love <ce...@us...> Date: Tue Oct 6 11:58:44 2020 -0500 VSX Scalar Min/Max/Compare Quad-Precision operation tests Diff: --- none/tests/ppc64/test_isa_3_1_VRT.c | 25 + none/tests/ppc64/test_isa_3_1_VRT.stdout.exp | 852 ++++++++++++++++++++++++++- 2 files changed, 876 insertions(+), 1 deletion(-) diff --git a/none/tests/ppc64/test_isa_3_1_VRT.c b/none/tests/ppc64/test_isa_3_1_VRT.c index a72ea26263..a801d403cb 100644 --- a/none/tests/ppc64/test_isa_3_1_VRT.c +++ b/none/tests/ppc64/test_isa_3_1_VRT.c @@ -233,6 +233,26 @@ static void test_vsrdbi_4 (void) { __asm__ __volatile__ ("vsrdbi %0, %1, %2, 4" : "=v" (vrt) : "v" (vra), "v" (vrb) ); } +static void test_xscmpeqqp (void) { + __asm__ __volatile__ ("xscmpeqqp %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_xscmpgeqp (void) { + __asm__ __volatile__ ("xscmpgeqp %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_xscmpgtqp (void) { + __asm__ __volatile__ ("xscmpgtqp %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_xsmaxcqp (void) { + __asm__ __volatile__ ("xsmaxcqp %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_xsmincqp (void) { + __asm__ __volatile__ ("xsmincqp %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} static test_list_t testgroup_generic[] = { { &test_vdivesd, "vdivesd", "VRT,VRA,VRB"}, /* bcs */ @@ -282,6 +302,11 @@ static test_list_t testgroup_generic[] = { { &test_vsldbi_4, "vsldbi 4", "VRT,VRA,VRB,SH"}, /* bcwp */ { &test_vsrdbi_0, "vsrdbi 0", "VRT,VRA,VRB,SH"}, /* bcwp */ { &test_vsrdbi_4, "vsrdbi 4", "VRT,VRA,VRB,SH"}, /* bcwp */ + { &test_xscmpeqqp, "xscmpeqqp", "VRT,VRA,VRB"}, /* bcs */ + { &test_xscmpgeqp, "xscmpgeqp", "VRT,VRA,VRB"}, /* bcs */ + { &test_xscmpgtqp, "xscmpgtqp", "VRT,VRA,VRB"}, /* bcs */ + { &test_xsmaxcqp, "xsmaxcqp", "VRT,VRA,VRB"}, /* bcs */ + { &test_xsmincqp, "xsmincqp", "VRT,VRA,VRB"}, /* bcs */ { NULL, NULL }, }; diff --git a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp index 5b2e41b01d..579dcdcc09 100644 --- a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp +++ b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp @@ -6894,4 +6894,854 @@ vsrdbi 4 8000000000000000,7f800000ff800000 ffff000180000001,0000000000000000 => vsrdbi 4 8000000000000000,7f800000ff800000 0000000000000000,8000000000000000 => 800000000000000,0000000000000000 vsrdbi 4 8000000000000000,7f800000ff800000 8000000000000000,7f800000ff800000 => 7f800000ff80000,0800000000000000 -All done. Tested 47 different instruction groups +xscmpeqqp 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ffffffffffffffff,ffffffffffffffff +xscmpeqqp 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +xscmpeqqp 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +xscmpeqqp 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +xscmpeqqp 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +xscmpeqqp 7f800000ff800000,ff8000007f800000 0000111e8000222e,7ff0000000000000 => 0,0000000000000000 +xscmpeqqp 7f800000ff800000,ff8000007f800000 7ff0000000000000,fff0000000000000 => 0,0000000000000000 +xscmpeqqp 7f800000ff800000,ff8000007f800000 fff0000000000000,2208400000000000 => 0,0000000000000000 +xscmpeqqp 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => 0,0000000000000000 +xscmpeqqp 7f800000ff800000,ff8000007f800000 0000000000000009,ffff000180000001 => 0,0000000000000000 +xscmpeqqp 7f800000ff800000,ff8000007f800000 ffff000180000001,0000000000000000 => 0,0000000000000000 +xscmpeqqp 7f800000ff800000,ff8000007f800000 0000000000000000,8000000000000000 => 0,0000000000000000 +xscmpeqqp 7f800000ff800000,ff8000007f800000 8000000000000000,7f800000ff800000 => 0,0000000000000000 +xscmpeqqp ff8000007f800000,ff7ffffe7f7ffffe 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +xscmpeqqp ff8000007f800000,ff7ffffe7f7ffffe ff8000007f800000,ff7ffffe7f7ffffe => ffffffffffffffff,ffffffffffffffff +xscmpeqqp ff8000007f800000,ff7ffffe7f7ffffe ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +xscmpeqqp ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +xscmpeqqp ff8000007f800000,ff7ffffe7f7ffffe 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +xscmpeqqp ff8000007f800000,ff7ffffe7f7ffffe 0000111e8000222e,7ff0000000000000 => 0,0000000000000000 +xscmpeqqp ff8000007f800000,ff7ffffe7f7ffffe 7ff0000000000000,fff0000000000000 => 0,0000000000000000 +xscmpeqqp ff8000007f800000,ff7ffffe7f7ffffe fff0000000000000,2208400000000000 => 0,0000000000000000 +xscmpeqqp ff8000007f800000,ff7ffffe7f7ffffe 2208400000000000,0000000000000009 => 0,0000000000000000 +xscmpeqqp ff8000007f800000,ff7ffffe7f7ffffe 0000000000000009,ffff000180000001 => 0,0000000000000000 +xscmpeqqp ff8000007f800000,ff7ffffe7f7ffffe ffff000180000001,0000000000000000 => 0,0000000000000000 +xscmpeqqp ff8000007f800000,ff7ffffe7f7ffffe 0000000000000000,8000000000000000 => 0,0000000000000000 +xscmpeqqp ff8000007f800000,ff7ffffe7f7ffffe 8000000000000000,7f800000ff800000 => 0,0000000000000000 +xscmpeqqp ff7ffffe7f7ffffe,0080000e8080000e 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +xscmpeqqp ff7ffffe7f7ffffe,0080000e8080000e ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +xscmpeqqp ff7ffffe7f7ffffe,0080000e8080000e ff7ffffe7f7ffffe,0080000e8080000e => ffffffffffffffff,ffffffffffffffff +xscmpeqqp ff7ffffe7f7ffffe,0080000e8080000e 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +xscmpeqqp ff7ffffe7f7ffffe,0080000e8080000e 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +xscmpeqqp ff7ffffe7f7ffffe,0080000e8080000e 0000111e8000222e,7ff0000000000000 => 0,0000000000000000 +xscmpeqqp ff7ffffe7f7ffffe,0080000e8080000e 7ff0000000000000,fff0000000000000 => 0,0000000000000000 +xscmpeqqp ff7ffffe7f7ffffe,0080000e8080000e fff0000000000000,2208400000000000 => 0,0000000000000000 +xscmpeqqp ff7ffffe7f7ffffe,0080000e8080000e 2208400000000000,0000000000000009 => 0,0000000000000000 +xscmpeqqp ff7ffffe7f7ffffe,0080000e8080000e 0000000000000009,ffff000180000001 => 0,0000000000000000 +xscmpeqqp ff7ffffe7f7ffffe,0080000e8080000e ffff000180000001,0000000000000000 => 0,0000000000000000 +xscmpeqqp ff7ffffe7f7ffffe,0080000e8080000e 0000000000000000,8000000000000000 => 0,0000000000000000 +xscmpeqqp ff7ffffe7f7ffffe,0080000e8080000e 8000000000000000,7f800000ff800000 => 0,0000000000000000 +xscmpeqqp 0080000e8080000e,0180055e0180077e 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +xscmpeqqp 0080000e8080000e,0180055e0180077e ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +xscmpeqqp 0080000e8080000e,0180055e0180077e ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +xscmpeqqp 0080000e8080000e,0180055e0180077e 0080000e8080000e,0180055e0180077e => ffffffffffffffff,ffffffffffffffff +xscmpeqqp 0080000e8080000e,0180055e0180077e 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +xscmpeqqp 0080000e8080000e,0180055e0180077e 0000111e8000222e,7ff0000000000000 => 0,0000000000000000 +xscmpeqqp 0080000e8080000e,0180055e0180077e 7ff0000000000000,fff0000000000000 => 0,0000000000000000 +xscmpeqqp 0080000e8080000e,0180055e0180077e fff0000000000000,2208400000000000 => 0,0000000000000000 +xscmpeqqp 0080000e8080000e,0180055e0180077e 2208400000000000,0000000000000009 => 0,0000000000000000 +xscmpeqqp 0080000e8080000e,0180055e0180077e 0000000000000009,ffff000180000001 => 0,0000000000000000 +xscmpeqqp 0080000e8080000e,0180055e0180077e ffff000180000001,0000000000000000 => 0,0000000000000000 +xscmpeqqp 0080000e8080000e,0180055e0180077e 0000000000000000,8000000000000000 => 0,0000000000000000 +xscmpeqqp 0080000e8080000e,0180055e0180077e 8000000000000000,7f800000ff800000 => 0,0000000000000000 +xscmpeqqp 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +xscmpeqqp 0180055e0180077e,0000111e8000222e ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +xscmpeqqp 0180055e0180077e,0000111e8000222e ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +xscmpeqqp 0180055e0180077e,0000111e8000222e 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +xscmpeqqp 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => ffffffffffffffff,ffffffffffffffff +xscmpeqqp 0180055e0180077e,0000111e8000222e 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[truncated message content] |
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From: Carl L. <ca...@so...> - 2020-11-09 23:46:53
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ea228057d07056b1ce817baa51b6346ad6738e4b commit ea228057d07056b1ce817baa51b6346ad6738e4b Author: Carl Love <ce...@us...> Date: Wed May 6 20:09:38 2020 -0500 ISA 3.1 Bit-Manipulation Operations Add support for: cfuged Centrifuge Doubleword cntlzdm Count Leading Zeros Doubleword under bit Mask cnttzdm Count Trailing Zeros Doubleword under bit Mask pdepd Parallel Bits Deposit Doubleword pextd Parallel Bits Extract Doubleword vcfuged Vector Centrifuge Doubleword vclzdm Vector Count Leading Zeros Doubleword under bit Mask vctzdm Vector Count Trailing Zeros Doubleword under bit Mask vgnb Vector Gather every Nth Bit vpdepd Vector Parallel Bits Deposit Doubleword vpextd Vector Parallel Bits Extract Doubleword xxeval VSX Vector Evaluate dependent on RFC2609 patch being applied first. Diff: --- VEX/priv/guest_ppc_defs.h | 3 + VEX/priv/guest_ppc_helpers.c | 44 +++ VEX/priv/guest_ppc_toIR.c | 825 +++++++++++++++++++++++++++++++++++++++---- 3 files changed, 808 insertions(+), 64 deletions(-) diff --git a/VEX/priv/guest_ppc_defs.h b/VEX/priv/guest_ppc_defs.h index aea5ef7005..2efa89e102 100644 --- a/VEX/priv/guest_ppc_defs.h +++ b/VEX/priv/guest_ppc_defs.h @@ -154,6 +154,9 @@ extern ULong convert_from_national_helper( ULong src_hi, ULong src_low ); extern ULong generate_C_FPCC_helper( ULong size, ULong src_hi, ULong src ); extern ULong extract_bits_under_mask_helper( ULong src, ULong mask, UInt flag ); +extern UInt count_bits_under_mask_helper( ULong src, ULong mask, + UInt flag ); +extern ULong deposit_bits_under_mask_helper( ULong src, ULong mask ); extern ULong population_count64_helper( ULong src ); extern ULong vector_evaluate64_helper( ULong srcA, ULong srcB, ULong srcC, ULong IMM ); diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c index a5cf9b4c26..3bea3f9928 100644 --- a/VEX/priv/guest_ppc_helpers.c +++ b/VEX/priv/guest_ppc_helpers.c @@ -576,6 +576,49 @@ ULong extract_bits_under_mask_helper( ULong src, ULong mask, UInt flag ) { return zeros; } +UInt count_bits_under_mask_helper( ULong src, ULong mask, UInt flag ) { + + UInt i, count_extracted_1, count_extracted_0;; + ULong mask_bit; + + count_extracted_1 = 0; + count_extracted_0 = 0; + + for (i=0; i<64; i++){ + mask_bit = 0x1 & (mask >> (63-i)); + + if (mask_bit == 1) + count_extracted_1++; + + if ((1^mask_bit) == 1) + count_extracted_0++; + } + + if (flag == 1) + return count_extracted_1; + else + return count_extracted_0; +} + +ULong deposit_bits_under_mask_helper( ULong src, ULong mask ) { + + UInt i, src_bit_pos; + ULong result, mask_bit, bit_src; + + result = 0; + src_bit_pos = 0; + + for (i=0; i<64; i++){ + mask_bit = 0x1 & (mask >> i); + + if (mask_bit == 1) { + bit_src = 0x1 & (src >> src_bit_pos); + result = result | (bit_src << i); + src_bit_pos++; + } + } + return result; +} /*----------------------------------------------*/ /*--- Vector Evaluate Inst helper --------------*/ @@ -599,6 +642,7 @@ ULong vector_evaluate64_helper( ULong srcA, ULong srcB, ULong srcC, bitB = 0x1 & (srcB >> i); bitC = 0x1 & (srcC >> i); + /* The value of select is IBM numbering based, i.e. MSB is bit 0 */ select = (bitA << 2) | (bitB << 1) | bitC; bitIMM = (IMM >> (MAX_IMM_BITS - 1 - select)) & 0x1; result = result | (bitIMM << i); diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 213f6d4c6a..62eeade57a 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -5286,6 +5286,151 @@ static IRExpr * convert_from_national ( const VexAbiInfo* vbi, IRExpr *src ) { return mkexpr( result ); } +static IRExpr * popcnt64 ( const VexAbiInfo* vbi, + IRExpr *src ){ + /* The function takes a 64-bit source and counts the number of bits in the + source that are 1's. */ + IRTemp result = newTemp( Ity_I64); + + assign( result, + mkIRExprCCall( Ity_I64, 0 /*regparms*/, + "population_count64_helper", + fnptr_to_fnentry( vbi, + &population_count64_helper ), + mkIRExprVec_1( src ) ) ); + + return mkexpr( result ); +} + +static IRExpr * extract_bits_under_mask ( const VexAbiInfo* vbi, + IRExpr *src, IRExpr *mask, + IRExpr *flag ) { + + /* The function takes a 64-bit value and a 64-bit mask. It will extract the + * bits from the source that align with 1's in the mask or it will extract + * the bits from the source that align with 0's in the mask. + */ + IRTemp result = newTemp( Ity_I64); + + assign( result, + mkIRExprCCall( Ity_I64, 0 /*regparms*/, + "extract_bits_under_mask_helper", + fnptr_to_fnentry( vbi, + &extract_bits_under_mask_helper ), + mkIRExprVec_3( src, mask, flag ) ) ); + + return mkexpr( result ); +} + +static IRExpr * count_bits_under_mask ( const VexAbiInfo* vbi, + IRExpr *src , IRExpr *mask, + IRExpr *flag ) { + + /* The function takes a 64-bit value and a 64-bit mask. It will count the + * bits from the source that align with 1's in the mask or it will count + * the bits from the source that align with 0's in the mask. + */ + IRTemp result = newTemp( Ity_I32); + + assign( result, + mkIRExprCCall( Ity_I32, 0 /*regparms*/, + "count_bits_under_mask_helper", + fnptr_to_fnentry( vbi, + &count_bits_under_mask_helper ), + mkIRExprVec_3( src, mask, flag ) ) ); + + return mkexpr( result ); +} + +static IRExpr * deposit_bits_under_mask ( const VexAbiInfo* vbi, + IRExpr *src , IRExpr *mask ) { + + /* The contents of the rightmost n bits of src are placed into bits_rtn + * under the control of the mask. The LSB (bit 63) of src is placed into + * the bit of bits_rtn corresponding to the right most bit of mask that is + * a 1. The LSB+1 (bit 62) of src is placed into the bit of bits_rtn + * corresponding to the second right most bit of mask that is a 1, etc. + */ + + IRTemp result = newTemp( Ity_I64); + + assign( result, + mkIRExprCCall( Ity_I64, 0 /*regparms*/, + "deposit_bits_under_mask_helper", + fnptr_to_fnentry( vbi, + &deposit_bits_under_mask_helper ), + mkIRExprVec_2( src, mask) ) ); + + return mkexpr( result ); +} + +static IRExpr * vector_evaluate_inst ( const VexAbiInfo* vbi, + IRExpr *srcA, IRExpr *srcB, + IRExpr *srcC, IRExpr *IMM ){ + /* This function implements the ISA 3.1 instruction xxeval. The + instruction is too complex to do with Iops. An Iop implementation is + expected to exhaust memory and be really complex to write, debug and + understand. The second option would be to just map it to a new Iop. + Unfortunately, I doubt any other architecture will implement it making + the Iop PPC specific which isn't really attractive. It would need + extensive documenation for the Iop definition for anyone else to + understand what it does. That leaves doing it as a clean helper. This + is not the ideal option, but was chosen for now to help document what + the instruction does. Discuss this with Julian before committing to + decide if we really want to use this approach or map the instructioin + to a new IOP. */ + /* FIX ME, CARLL 11/8/2018*/ + + /* The instruction description, note the IBM bit numbering is left to right: + + For each integer value i, 0 to 127, do the following. + + Let j be the value of the concatenation of the contents of bit i of + srcA, bit i of srcB, bit i of srcC. (j = srcA[i] | srcB[i] | srcC[i]) + + The value of bit IMM[j] is placed into bit result[i]. + + Basically the instruction lets you set each of the 128 bits in the result + by selecting one of the eight bits in the IMM value. */ + + /* Calling clean helpers with 128-bit args is currently not supported. It + isn't worth adding the support. We will simply call a 64-bit helper to + do the upper 64-bits of the result and the lower 64-bits of the result. + */ + + IRTemp result_hi = newTemp( Ity_I64 ); + IRTemp result_lo = newTemp( Ity_I64 ); + IRExpr *srcA_hi; + IRExpr *srcB_hi; + IRExpr *srcC_hi; + IRExpr *srcA_lo; + IRExpr *srcB_lo; + IRExpr *srcC_lo; + + srcA_hi = unop( Iop_V128HIto64, srcA ); + srcA_lo = unop( Iop_V128to64, srcA ); + srcB_hi = unop( Iop_V128HIto64, srcB ); + srcB_lo = unop( Iop_V128to64, srcB ); + srcC_hi = unop( Iop_V128HIto64, srcC ); + srcC_lo = unop( Iop_V128to64, srcC ); + + assign( result_hi, + mkIRExprCCall( Ity_I64, 0 /*regparms*/, + "vector_evaluate64_helper", + fnptr_to_fnentry( vbi, + &vector_evaluate64_helper ), + mkIRExprVec_4( srcA_hi, srcB_hi, srcC_hi, IMM ) ) ); + + assign( result_lo, + mkIRExprCCall( Ity_I64, 0 /*regparms*/, + "vector_evaluate64_helper", + fnptr_to_fnentry( vbi, + &vector_evaluate64_helper ), + mkIRExprVec_4( srcA_lo, srcB_lo, srcC_lo, IMM ) ) ); + + return binop( Iop_64HLtoV128, mkexpr( result_hi ), mkexpr( result_lo ) ); +} + static IRExpr * UNSIGNED_CMP_GT_V128 ( IRExpr *vA, IRExpr *vB ) { /* This function does an unsigned compare of two V128 values. The * function is for use in 32-bit mode only as it is expensive. The @@ -8470,7 +8615,8 @@ static Bool dis_vector_splat_imm_prefix ( UInt prefix, UInt theInstr ) /* VSX Vector Permute Extended 8RR:D-form */ -static Bool dis_vector_permute_prefix ( UInt prefix, UInt theInstr ) +static Bool dis_vector_permute_prefix ( UInt prefix, UInt theInstr, + const VexAbiInfo* vbi ) { #define MAX_ELE 16 UChar opc1 = ifieldOPC(theInstr); @@ -8479,7 +8625,6 @@ static Bool dis_vector_permute_prefix ( UInt prefix, UInt theInstr ) UChar rXA_addr = ifieldRegXA_8RR_XX4( theInstr ); UChar rXB_addr = ifieldRegXB_8RR_XX4( theInstr ); UChar rXC_addr = ifieldRegXC_8RR_XX4( theInstr ); - UInt UIM = IFIELD(prefix, 0, 3); // bit [29:31] of the prefix Int i; IRTemp rXA = newTemp(Ity_V128); @@ -8495,77 +8640,104 @@ static Bool dis_vector_permute_prefix ( UInt prefix, UInt theInstr ) /* These are prefix instructions, no equivalent word instruction. */ if ((opc1 != 0x22) && (opc2 != 0)) return False; - DIP("xxpermx v%u,v%u,v%u,v%u,%u\n", - rXT_addr, rXA_addr, rXB_addr, rXC_addr, UIM); - assign( rXA, getVSReg( rXA_addr ) ); assign( rXB, getVSReg( rXB_addr ) ); assign( rXC, getVSReg( rXC_addr ) ); - result[MAX_ELE] = newTemp(Ity_V128); - assign( eidx_mask, mkU64( 0x1F ) ); - assign( cmp_mask, mkU64( 0x7 ) ); - assign( result[MAX_ELE], binop( Iop_64HLtoV128, mkU64( 0 ), mkU64( 0 ) ) ); + switch(opc2) { + case 0: + { + UInt UIM = IFIELD(prefix, 0, 3); // bit [29:31] of the prefix - for (i = MAX_ELE-1; i >= 0; i--) { + DIP("xxpermx v%u,v%u,v%u,v%u,%u\n", + rXT_addr, rXA_addr, rXB_addr, rXC_addr, UIM); - eidx[i] = newTemp( Ity_I64 ); - byte[i] = newTemp( Ity_I64 ); - result[i] = newTemp( Ity_V128 ); - result_mask[i] = newTemp( Ity_I64 ); + result[MAX_ELE] = newTemp(Ity_V128); + assign( eidx_mask, mkU64( 0x1F ) ); + assign( cmp_mask, mkU64( 0x7 ) ); + assign( result[MAX_ELE], binop( Iop_64HLtoV128, mkU64( 0 ), + mkU64( 0 ) ) ); - /* the eidx is left based, make index right based for - extractBytefromV256(). */ - if ( i >= 8) { - assign( eidx[i], - binop( Iop_Sub64, - mkU64( 31 ), - binop( Iop_And64, - mkexpr( eidx_mask ), - binop( Iop_Shr64, - unop( Iop_V128HIto64, mkexpr( rXC ) ), - mkU8( (i - 8)*8 ) ) ) ) ); - assign( result_mask[i], - unop( Iop_1Sto64, - binop( Iop_CmpEQ64, - mkU64( UIM ), - binop( Iop_And64, - mkexpr ( cmp_mask ), - binop( Iop_Shr64, // bits 0:2 of ith byte - unop( Iop_V128HIto64, - mkexpr( rXC ) ), - mkU8( (i - 8)*8 + 5 ) ) ) ) ) ); - } else { - assign( eidx[i], - binop( Iop_Sub64, - mkU64( 31 ), - binop( Iop_And64, - mkexpr( eidx_mask ), - binop( Iop_Shr64, - unop( Iop_V128to64, mkexpr( rXC ) ), - mkU8( i*8 ) ) ) ) ); - assign( result_mask[i], - unop( Iop_1Sto64, - binop( Iop_CmpEQ64, - mkU64( UIM ), - binop( Iop_And64, - mkexpr ( cmp_mask ), - binop( Iop_Shr64, // bits 0:2 of ith byte - unop( Iop_V128to64, - mkexpr( rXC ) ), - mkU8( i*8 + 5 ) ) ) ) ) ); + for (i = MAX_ELE-1; i >= 0; i--) { + eidx[i] = newTemp( Ity_I64 ); + byte[i] = newTemp( Ity_I64 ); + result[i] = newTemp( Ity_V128 ); + result_mask[i] = newTemp( Ity_I64 ); + + /* The eidx is left based, make index right based for + extractBytefromV256(). */ + if ( i >= 8) { + assign( eidx[i], + binop( Iop_Sub64, + mkU64( 31 ), + binop( Iop_And64, + mkexpr( eidx_mask ), + binop( Iop_Shr64, + unop( Iop_V128HIto64, mkexpr( rXC ) ), + mkU8( (i - 8)*8 ) ) ) ) ); + assign( result_mask[i], + unop( Iop_1Sto64, + binop( Iop_CmpEQ64, + mkU64( UIM ), + binop( Iop_And64, + mkexpr ( cmp_mask ), + // bits 0:2 of ith byte + binop( Iop_Shr64, + unop( Iop_V128HIto64, + mkexpr( rXC ) ), + mkU8( (i - 8)*8 + 5 ) ) ) + ) ) ); + } else { + assign( eidx[i], + binop( Iop_Sub64, + mkU64( 31 ), + binop( Iop_And64, + mkexpr( eidx_mask ), + binop( Iop_Shr64, + unop( Iop_V128to64, mkexpr( rXC ) ), + mkU8( i*8 ) ) ) ) ); + assign( result_mask[i], + unop( Iop_1Sto64, + binop( Iop_CmpEQ64, + mkU64( UIM ), + binop( Iop_And64, + mkexpr ( cmp_mask ), + // bits 0:2 of ith byte + binop( Iop_Shr64, + unop( Iop_V128to64, + mkexpr( rXC ) ), + mkU8( i*8 + 5 ) ) ) ) ) ); + } + + assign( byte[i], + binop( Iop_And64, + mkexpr( result_mask[i] ), + extractBytefromV256( rXA, rXB, eidx[i] ) ) ); + + assign( result[i], insert_field_into_vector( result[i+1], + mkU64( i ), + mkexpr( byte[i] ), + mkU64( 0xFF ) ) ); } + putVSReg( rXT_addr, mkexpr( result[0] ) ); + } + break; - assign( byte[i], - binop( Iop_And64, - mkexpr( result_mask[i] ), - extractBytefromV256( rXA, rXB, eidx[i] ) ) ); + case 1: + { + UInt IMM = IFIELD(prefix, 0, 8); // bit [24:31] of the prefix + DIP("xxeval v%u,v%u,v%u,v%u,%u\n", + rXT_addr, rXA_addr, rXB_addr, rXC_addr, IMM); + putVSReg( rXT_addr, + vector_evaluate_inst ( vbi, mkexpr( rXA ), mkexpr( rXB ), + mkexpr( rXC ), mkU64( IMM ) ) ); + } + break; - assign( result[i], insert_field_into_vector( result[i+1], mkU64( i ), - mkexpr( byte[i] ), - mkU64( 0xFF ) ) ); + default: + vex_printf("dis_vector_permute_prefix(ppc)(opc2)\n"); + return False; } - putVSReg( rXT_addr, mkexpr( result[0] ) ); return True; #undef MAX_ELE @@ -19742,6 +19914,508 @@ dis_av_count_bitTranspose ( UInt prefix, UInt theInstr, UInt opc2 ) return True; } +/* + * Scalar / Vector Population Count/bit matrix transpose + */ +static Bool dis_logical_mask_bits ( UInt prefix, UInt theInstr, + const VexAbiInfo* vbi ) +{ + UChar opc1 = ifieldOPC(theInstr); + UInt opc2 = ifieldOPClo10(theInstr); + UChar rS_addr = ifieldRegDS(theInstr); + UChar rA_addr = ifieldRegA(theInstr); + UChar rB_addr = ifieldRegB(theInstr); + + IRTemp rS = newTemp( Ity_I64 ); + IRTemp rA = newTemp( Ity_I64 ); + IRTemp rB = newTemp( Ity_I64 ); + + /* There are no prefixed version of these instructions. */ + vassert( !prefix_instruction( prefix ) ); + + assign( rS, getIReg(rS_addr) ); + assign( rB, getIReg(rB_addr) ); + + if (opc1 != 0x1F) { + vex_printf( "dis_logical_mask_bits(ppc)(instr)\n" ); + return False; + } + + switch (opc2) { + + /* X-form instructions */ + case 0x03B: // cntlzdm, Count Leading Zeros Doubleword Under bitmask + case 0x0BC: // pextd, Parallel Bits Extract Doubleword + case 0x0DC: // cfuged, Centrifuge Doubleword + case 0x23B: // cnttzdm, Count Trailing Zeros Doubleword Under bit mask + { + UInt max_bits = mode64 ? 64 : 32; + IRTemp ones = newTemp( Ity_I64 ); + IRTemp all_ones = newTemp( Ity_I64 ); + + /* Get the bits corresponding to 1's in the mask */ + assign( ones, extract_bits_under_mask ( vbi, + mkexpr( rS ), + mkexpr( rB ), + mkU64( 1 ) ) ); + + if ( opc2 == 0x03b ) { // cntlzdm + IRTemp cnt = newTemp( Ity_I64 ); + + DIP("cntlzdm r%u,r%u,r%u\n", rA_addr, rS_addr, rB_addr); + assign( cnt, popcnt64( vbi, mkexpr( rB ) ) ); + + assign( all_ones, binop( Iop_Shr64, + mkU64( 0xFFFFFFFFFFFFFFFF ), + unop( Iop_64to8, mkexpr( cnt ) ) ) ); + + assign( rA, + unop( Iop_ClzNat64, + binop( Iop_Or64, + binop( Iop_Shl64, + mkexpr( ones ), + binop( Iop_Sub8, + mkU8( max_bits ), + unop( Iop_64to8, + mkexpr( cnt ) ) ) ), + mkexpr( all_ones ) ) ) ); + + } else if ( opc2 == 0x0BC ) { // pextd + DIP("pextd r%u,r%u,r%u\n", rA_addr, rS_addr, rB_addr); + assign( rA, mkexpr( ones ) ); + + } else if ( opc2 == 0x0DC ) { // cfuged + IRTemp zeros = newTemp( Ity_I64 ); + IRTemp cnt = newTemp( Ity_I64 ); + + DIP("cfuged r%u,r%u,r%u\n", rA_addr, rS_addr, rB_addr); + assign( cnt, popcnt64( vbi, mkexpr( rB ) ) ); + + /* Get the bits corresponding to 0's in the mask */ + assign( zeros, extract_bits_under_mask ( vbi, + mkexpr( rS ), + mkexpr( rB ), + mkU64( 0 ) ) ); + + assign( rA, + binop( Iop_Or64, + binop( Iop_Shl64, + mkexpr( zeros ), + unop( Iop_64to8, + mkexpr( cnt ) ) ), + mkexpr( ones ) ) ); + + } else if ( opc2 == 0x23B ) { //cnttzdm + DIP("cnttzdm r%u,r%u,r%u\n", rA_addr, rS_addr, rB_addr); + assign( all_ones, binop( Iop_Shl64, + mkU64( 0xFFFFFFFFFFFFFFFF ), + unop( Iop_64to8, + popcnt64( vbi, + mkexpr( rB ) ) ) ) ); + + assign( rA, + unop( Iop_CtzNat64, + binop( Iop_Or64, + mkexpr( all_ones ), mkexpr( ones ) ) ) ); + + } else { //pexld + DIP("pexld r%u,r%u,r%u\n", rA_addr, rS_addr, rB_addr); + assign( rA, mkexpr( ones ) ); + } + break; + } + + case 0x09C: // pdepd, Parallel Bits Deposit Doubleword X-form + { + IRTemp ones = newTemp( Ity_I64 ); + + DIP("pdepd r%u,r%u,r%u\n", rA_addr, rS_addr, rB_addr); + assign( ones, deposit_bits_under_mask ( vbi, mkexpr( rS ), + mkexpr( rB ) ) ); + assign( rA, mkexpr( ones ) ); + break; + } + + default: + vex_printf("dis_logical_mask_bits)(ppc)\n"); + return False; + } + + putIReg( rA_addr, mkexpr( rA ) ); + return True; +} + +static Bool +dis_vector_logical_mask_bits ( UInt prefix, UInt theInstr, UInt opc2, + const VexAbiInfo* vbi ) +{ + UChar vRA_addr = ifieldRegA(theInstr); + UChar vRB_addr = ifieldRegB(theInstr); + UChar vRT_addr = ifieldRegDS(theInstr); + UChar opc1 = ifieldOPC( theInstr ); + IRTemp vA = newTemp(Ity_V128); + IRTemp vB = newTemp(Ity_V128); + + /* There are no prefixed version of these instructions. */ + vassert( !prefix_instruction( prefix ) ); + + if (opc1 != 4) { + vex_printf( "dis_vector_logical_mask_bits(ppc)(instr)\n" ); + return False; + } + + assign( vA, getVReg(vRA_addr)); + assign( vB, getVReg(vRB_addr)); + + switch (opc2) { + case 0x4CC: // vgnb, Vector Gather every Nth Bit VX-form + { + IRTemp vB_hi = newTemp( Ity_I64 ); + IRTemp vB_lo = newTemp( Ity_I64 ); + IRTemp ones_hi, ones_lo; + UChar N = toUChar( IFIELD( theInstr, 16, 3 ) ); + ULong extract_mask_hi, extract_mask_lo, byte_mask; + UInt i, num_bits_hi, num_bits_lo; + + /* Note, the return register number is actually for a GPR not a + vector register. */ + DIP("vgnb %u,v%u,%u\n", vRT_addr, vRB_addr, N); + + if ((N < 2) || (N>7)) { + /* The value of N can be any value between 2 and 7, inclusive. */ + vex_printf("\nERROR: vgnb RT,VRB,N; N is out of range.\n\n"); + return False; + } + + /* Create 32-bit extract mask, starting with bit 0 (IBM numbering), + every Nth bit going right will be a 1. */ + extract_mask_hi = 0; + extract_mask_lo = 0; + + byte_mask = 1; + + i = 0; + num_bits_hi = 0; + while( i < 64) { + extract_mask_hi = extract_mask_hi | (byte_mask << (63 - i)); + i = i + N; + num_bits_hi++; + } + + num_bits_lo = 0; + while( i < 128) { + extract_mask_lo = extract_mask_lo | (byte_mask << (127 - i)); + i = i + N; + num_bits_lo++; + } + + ones_hi = newTemp( Ity_I64 ); + ones_lo = newTemp( Ity_I64 ); + + assign( vB_hi, unop( Iop_V128HIto64, mkexpr( vB ) ) ); + assign( vB_lo, unop( Iop_V128to64, mkexpr( vB ) ) ); + + assign( ones_hi, extract_bits_under_mask ( vbi, mkexpr( vB_hi ), + mkU64( extract_mask_hi ), + mkU64( 1 ) ) ); + assign( ones_lo, extract_bits_under_mask ( vbi, mkexpr( vB_lo ), + mkU64( extract_mask_lo ), + mkU64( 1 ) ) ); + + /* Concatenate the extracted bits from ones_hi and ones_lo and + store in GPR. Make sure the hi and low bits are left aligned per + IBM numbering */ + putIReg( vRT_addr, binop( Iop_Or64, + binop( Iop_Shl64, + mkexpr( ones_hi ), + mkU8( 64 - num_bits_hi ) ), + binop( Iop_Shl64, + mkexpr( ones_lo ), + mkU8( 64 - num_bits_hi + - num_bits_lo ) ) ) ); + } + return True; + + case 0x54D: // vcfuged, Centrifuge Doubleword VX-form + { + IRTemp vA_hi = newTemp( Ity_I64 ); + IRTemp vA_lo = newTemp( Ity_I64 ); + IRTemp vB_hi = newTemp( Ity_I64 ); + IRTemp vB_lo = newTemp( Ity_I64 ); + IRTemp zeros[2]; + IRTemp ones[2]; + IRTemp count[2]; + + DIP("vcfuged v%u,v%u,v%u\n", vRT_addr, vRA_addr, vRB_addr); + + zeros[0] = newTemp( Ity_I64 ); + zeros[1] = newTemp( Ity_I64 ); + ones[0] = newTemp( Ity_I64 ); + ones[1] = newTemp( Ity_I64 ); + count[0] = newTemp( Ity_I64 ); + count[1] = newTemp( Ity_I64 ); + + assign( vA_hi, unop( Iop_V128HIto64, mkexpr( vA ) ) ); + assign( vB_hi, unop( Iop_V128HIto64, mkexpr( vB ) ) ); + assign( vA_lo, unop( Iop_V128to64, mkexpr( vA ) ) ); + assign( vB_lo, unop( Iop_V128to64, mkexpr( vB ) ) ); + + assign( count[0], popcnt64( vbi, mkexpr( vB_hi ) ) ); + assign( count[1], popcnt64( vbi, mkexpr( vB_lo ) ) ); + + assign( ones[0], extract_bits_under_mask ( vbi, mkexpr( vA_hi ), + mkexpr( vB_hi ), + mkU64( 1 ) ) ); + assign( ones[1], extract_bits_under_mask ( vbi, mkexpr( vA_lo ), + mkexpr( vB_lo ), + mkU64( 1 ) ) ); + assign( zeros[0], extract_bits_under_mask ( vbi, mkexpr( vA_hi ), + mkexpr( vB_hi ), + mkU64( 0 ) ) ); + assign( zeros[1], extract_bits_under_mask ( vbi, mkexpr( vA_lo ), + mkexpr( vB_lo ), + mkU64( 0 ) ) ); + + /* Put the bits corresponding to zero mask bits to the left of the + bits corresponding to one mask bits for the upper and lower 64-bit + words. */ + putVReg( vRT_addr, binop( Iop_64HLtoV128, + binop( Iop_Or64, + binop( Iop_Shl64, + mkexpr( zeros[0] ), + unop( Iop_64to8, + mkexpr( count[0] ) ) ), + mkexpr( ones[0] ) ), + binop( Iop_Or64, + binop( Iop_Shl64, + mkexpr( zeros[1] ), + unop( Iop_64to8, + mkexpr( count[1] ) ) ), + mkexpr( ones[1] ) ) ) ); + } + break; + + case 0x58D: // vpextd, Vector Parallel Bits Extract Doubleword VX-form + { + IRTemp vA_hi = newTemp( Ity_I64 ); + IRTemp vA_lo = newTemp( Ity_I64 ); + IRTemp vB_hi = newTemp( Ity_I64 ); + IRTemp vB_lo = newTemp( Ity_I64 ); + IRTemp ones[2]; + + DIP("vpextd v%u,v%u,v%u\n", vRT_addr, vRA_addr, vRB_addr); + + ones[0] = newTemp( Ity_I64 ); + ones[1] = newTemp( Ity_I64 ); + + assign( vA_hi, unop( Iop_V128HIto64, mkexpr( vA ) ) ); + assign( vB_hi, unop( Iop_V128HIto64, mkexpr( vB ) ) ); + assign( vA_lo, unop( Iop_V128to64, mkexpr( vA ) ) ); + assign( vB_lo, unop( Iop_V128to64, mkexpr( vB ) ) ); + + assign( ones[0], extract_bits_under_mask ( vbi, mkexpr( vA_hi ), + mkexpr( vB_hi ), + mkU64( 1 ) ) ); + assign( ones[1], extract_bits_under_mask ( vbi, mkexpr( vA_lo ), + mkexpr( vB_lo ), + mkU64( 1 ) ) ); + putVReg( vRT_addr, binop( Iop_64HLtoV128, + mkexpr( ones[0] ), mkexpr( ones[1] ) ) ); + } + break; + + case 0x5CD: // vpdepd, Vector Parallel Bits Deposit Doubleword VX-form + { + IRTemp vA_hi = newTemp( Ity_I64 ); + IRTemp vA_lo = newTemp( Ity_I64 ); + IRTemp vB_hi = newTemp( Ity_I64 ); + IRTemp vB_lo = newTemp( Ity_I64 ); + IRTemp ones[2]; + + DIP("vpdepd v%u,v%u,v%u\n", vRT_addr, vRA_addr, vRB_addr); + + ones[0] = newTemp( Ity_I64 ); + ones[1] = newTemp( Ity_I64 ); + + assign( vA_hi, unop( Iop_V128HIto64, mkexpr( vA ) ) ); + assign( vB_hi, unop( Iop_V128HIto64, mkexpr( vB ) ) ); + assign( vA_lo, unop( Iop_V128to64, mkexpr( vA ) ) ); + assign( vB_lo, unop( Iop_V128to64, mkexpr( vB ) ) ); + + assign( ones[0], deposit_bits_under_mask ( vbi, mkexpr( vA_hi ), + mkexpr( vB_hi ) ) ); + assign( ones[1], deposit_bits_under_mask ( vbi, mkexpr( vA_lo ), + mkexpr( vB_lo ) ) ); + putVReg( vRT_addr, binop( Iop_64HLtoV128, + mkexpr( ones[0] ), mkexpr( ones[1] ) ) ); + } + break; + + case 0x784: // vclzdm, + { + /* Vector Count Leading Zeros Doubleword under bit mask */ + + IRTemp extracted_bits[2]; + IRTemp clz[2]; + IRTemp ones[2]; + IRTemp cnt_extract_bits[2]; + UInt max_bits = 64; + IRTemp vA_hi = newTemp( Ity_I64 ); + IRTemp vA_lo = newTemp( Ity_I64 ); + IRTemp vB_hi = newTemp( Ity_I64 ); + IRTemp vB_lo = newTemp( Ity_I64 ); + + DIP("vclzdm v%u,v%u,v%u\n", vRT_addr, vRA_addr, vRB_addr); + + ones[0] = newTemp( Ity_I64 ); + ones[1] = newTemp( Ity_I64 ); + clz[0] = newTemp( Ity_I64 ); + clz[1] = newTemp( Ity_I64 ); + extracted_bits[0] = newTemp( Ity_I64 ); + extracted_bits[1] = newTemp( Ity_I64 ); + cnt_extract_bits[0] = newTemp( Ity_I8 ); + cnt_extract_bits[1] = newTemp( Ity_I8 ); + + /* Gather bits in each vector element, then count leading zeros. */ + assign( vA_hi, unop( Iop_V128HIto64, mkexpr( vA ) ) ); + assign( vB_hi, unop( Iop_V128HIto64, mkexpr( vB ) ) ); + assign( vA_lo, unop( Iop_V128to64, mkexpr( vA ) ) ); + assign( vB_lo, unop( Iop_V128to64, mkexpr( vB ) ) ); + + assign( ones[0], extract_bits_under_mask ( vbi, + mkexpr( vA_hi ), + mkexpr( vB_hi ), + mkU64( 1 ) ) ); + + assign( ones[1], extract_bits_under_mask ( vbi, + mkexpr( vA_lo ), + mkexpr( vB_lo ), + mkU64( 1 ) ) ); + + assign( cnt_extract_bits[0], + unop( Iop_16to8, + unop( Iop_32to16, + count_bits_under_mask ( vbi, + mkexpr( vA_hi ), + mkexpr( vB_hi ), + mkU64( 1 ) ) ) ) ); + + assign( cnt_extract_bits[1], + unop( Iop_16to8, + unop( Iop_32to16, + count_bits_under_mask ( vbi, + mkexpr( vA_lo ), + mkexpr( vB_lo ), + mkU64( 1 ) ) ) ) ); + + /* Shift extracted bits to High order bits, filling lower order bits + with 1's so we only count zeros in extracted bits. */ + assign( extracted_bits[0], + binop( Iop_Or64, + binop( Iop_Shr64, + mkU64( 0xFFFFFFFFFFFFFFFF ), + mkexpr( cnt_extract_bits[0] ) ), + binop( Iop_Shl64, + mkexpr( ones[0] ), + binop( Iop_Sub8, + mkU8( max_bits ), + mkexpr( cnt_extract_bits[0] ) + ) ) ) ); + + assign( clz[0], + unop( Iop_Clz64, + mkexpr( extracted_bits[0] ) ) ); + + assign( extracted_bits[1], + binop( Iop_Or64, + binop( Iop_Shr64, + mkU64( 0xFFFFFFFFFFFFFFFF ), + mkexpr( cnt_extract_bits[1] ) ), + binop( Iop_Shl64, + mkexpr( ones[1] ), + binop( Iop_Sub8, + mkU8( max_bits ), + mkexpr( cnt_extract_bits[1] ) + ) ) ) ); + assign( clz[1], + unop( Iop_Clz64, + mkexpr( extracted_bits[1] ) ) ); + + putVReg( vRT_addr, binop( Iop_64HLtoV128, + mkexpr( clz[0] ), mkexpr( clz[1] ) ) ); + break; + } + + case 0x7C4: // vctzdm + { + /* Vector Count Trailing Zeros Doubleword under bit mask */ + IRTemp ctz[2]; + IRTemp ones[2]; + IRTemp all_ones_hi = newTemp( Ity_I64 ); + IRTemp all_ones_lo = newTemp( Ity_I64 ); + IRTemp vA_hi = newTemp( Ity_I64 ); + IRTemp vA_lo = newTemp( Ity_I64 ); + IRTemp vB_hi = newTemp( Ity_I64 ); + IRTemp vB_lo = newTemp( Ity_I64 ); + + DIP("vctzdm v%u,v%u,v%u\n", vRT_addr, vRA_addr, vRB_addr); + + ones[0] = newTemp( Ity_I64 ); + ones[1] = newTemp( Ity_I64 ); + ctz[0] = newTemp( Ity_I64 ); + ctz[1] = newTemp( Ity_I64 ); + + /* Gather bits in each vector element, then count trailing zeros. */ + assign( vA_hi, unop( Iop_V128HIto64, mkexpr( vA ) ) ); + assign( vB_hi, unop( Iop_V128HIto64, mkexpr( vB ) ) ); + assign( vA_lo, unop( Iop_V128to64, mkexpr( vA ) ) ); + assign( vB_lo, unop( Iop_V128to64, mkexpr( vB ) ) ); + + /* Shift all 1's value left by the count of the number of bits in the + mask. OR this with the extracted bits so the trailing zero count + will only count zeros in extracted field. */ + assign( all_ones_hi, + binop( Iop_Shl64, + mkU64( 0xFFFFFFFFFFFFFFFF ), + unop( Iop_64to8, + popcnt64( vbi, mkexpr( vB_hi ) ) ) ) ); + assign( all_ones_lo, + binop( Iop_Shl64, + mkU64( 0xFFFFFFFFFFFFFFFF ), + unop( Iop_64to8, + popcnt64( vbi, mkexpr( vB_lo ) ) ) ) ); + + assign( ones[0], + binop( Iop_Or64, + mkexpr( all_ones_hi ), + extract_bits_under_mask ( vbi, + mkexpr( vA_hi ), + mkexpr( vB_hi ), + mkU64( 1 ) ) ) ); + + assign( ones[1], + binop( Iop_Or64, + mkexpr( all_ones_lo ), + extract_bits_under_mask ( vbi, + mkexpr( vA_lo ), + mkexpr( vB_lo ), + mkU64( 1 ) ) ) ); + + assign( ctz[0], unop( Iop_CtzNat64, mkexpr( ones[0] ) ) ); + assign( ctz[1], unop( Iop_CtzNat64, mkexpr( ones[1] ) ) ); + + putVReg( vRT_addr, binop( Iop_64HLtoV128, + mkexpr( ctz[0] ), mkexpr( ctz[1] ) ) ); + break; + } + + default: + vex_printf("dis_vector_logical_mask_bits(ppc)(opc2)\n"); + return False; + } + return True; +} + typedef enum { PPC_CMP_EQ = 2, PPC_CMP_GT = 4, @@ -32317,7 +32991,7 @@ DisResult disInstr_PPC_WRK ( if (prefix_instruction( prefix) && ( ptype == pType1 ) ) { if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; // splat instructions: xxpermx - if (dis_vector_permute_prefix( prefix, theInstr )) + if (dis_vector_permute_prefix( prefix, theInstr, abiinfo )) goto decode_success; } else { // lbz: load instruction if (dis_int_load_prefix( prefix, theInstr )) @@ -33342,6 +34016,17 @@ DisResult disInstr_PPC_WRK ( if (dis_byte_reverse( prefix, theInstr )) goto decode_success; goto decode_failure; + /* X-form instructions */ + case 0x03B: // cntlzdm, Count Leading Zeros Doubleword under bit Mask + case 0x0BC: // pextd, Parallel Bits Extract Doubleword + case 0x09C: // pdepd, Parallel Bits Deposit Doubleword + case 0x23B: // cnttzdm, Count Trailing Zeros Doubleword under bit Mask + case 0x0DC: // cfuged, Centrifuge Doubleword + if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; + if (dis_logical_mask_bits( prefix, theInstr, abiinfo ) ) + goto decode_success; + goto decode_failure; + /* Integer miscellaneous instructions */ case 0x01E: // wait RFC 2500 if (dis_int_misc( prefix, theInstr )) goto decode_success; @@ -33359,6 +34044,9 @@ DisResult disInstr_PPC_WRK ( case 0x10B: case 0x30B: // moduw, modsw case 0x109: case 0x309: // modsd, modud + if (dis_modulo_int( prefix, theInstr )) goto decode_success; + goto decode_failure; + case 0x21A: case 0x23A: // cnttzw, cnttzd if (dis_modulo_int( prefix, theInstr )) goto decode_success; goto decode_failure; @@ -34021,7 +34709,16 @@ DisResult disInstr_PPC_WRK ( case 0x782: case 0x7c2: // vclzw, vclzd if (!allow_isa_2_07) goto decode_noP8; if (dis_av_count_bitTranspose( prefix, theInstr, opc2 )) - goto decode_success; + goto decode_success; + goto decode_failure; + + case 0x4CC: case 0x54D: // vgnb, vcfuged + case 0x58D: case 0x5CD: // vpextd, vpdepd + case 0x784: case 0x7C4: // vclzdm, vctzdm + if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; + if (dis_vector_logical_mask_bits( prefix, theInstr, opc2, + abiinfo )) + goto decode_success; goto decode_failure; case 0x703: case 0x743: // vpopcntb, vpopcnth |
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From: Carl L. <ca...@so...> - 2020-11-09 23:46:43
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=42321f97e81af24e5112d72c16d9b2523182b04d commit 42321f97e81af24e5112d72c16d9b2523182b04d Author: Carl Love <ce...@us...> Date: Thu Sep 24 10:29:56 2020 -0500 ISA 3.1 128-bit Binary Integer Operations Add support for: vmuleud, vmuloud, vmulesd, vmulosd vextsd2q, vcmpuq, vcmpsq vcmpequq, vcmpequq., vcmpgtuq, vcmpgtuq., vcmpgtsq, vcmpgtsq. vrlq, vrlqnm, vlqmi, vslq, vsrq, vsraq Diff: --- VEX/priv/guest_ppc_defs.h | 5 + VEX/priv/guest_ppc_helpers.c | 76 ++++++ VEX/priv/guest_ppc_toIR.c | 555 ++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 627 insertions(+), 9 deletions(-) diff --git a/VEX/priv/guest_ppc_defs.h b/VEX/priv/guest_ppc_defs.h index 802e75a328..aea5ef7005 100644 --- a/VEX/priv/guest_ppc_defs.h +++ b/VEX/priv/guest_ppc_defs.h @@ -152,6 +152,11 @@ extern ULong convert_to_national_helper( ULong src, ULong return_upper ); extern ULong convert_from_zoned_helper( ULong src_hi, ULong src_low ); extern ULong convert_from_national_helper( ULong src_hi, ULong src_low ); extern ULong generate_C_FPCC_helper( ULong size, ULong src_hi, ULong src ); +extern ULong extract_bits_under_mask_helper( ULong src, ULong mask, + UInt flag ); +extern ULong population_count64_helper( ULong src ); +extern ULong vector_evaluate64_helper( ULong srcA, ULong srcB, ULong srcC, + ULong IMM ); /* --- DIRTY HELPERS --- */ diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c index 80c7965556..a5cf9b4c26 100644 --- a/VEX/priv/guest_ppc_helpers.c +++ b/VEX/priv/guest_ppc_helpers.c @@ -533,6 +533,82 @@ ULong convert_from_national_helper( ULong src_hi, ULong src_low ) { return tmp; } +/*------------------------------------------------*/ +/*--- Population count ---------------------------*/ +/*------------------------------------------------*/ +ULong population_count64_helper( ULong src ) { + /* Fast population count based on algorithm in the "Hacker's Delight" by + Henery S. Warren. */ + src = (src & 0x5555555555555555) + ((src >> 1) & 0x5555555555555555); + src = (src & 0x3333333333333333) + ((src >> 2) & 0x3333333333333333); + src = (src & 0x0F0F0F0F0F0F0F0F) + ((src >> 4) & 0x0F0F0F0F0F0F0F0F); + src = (src & 0x00FF00FF00FF00FF) + ((src >> 8) & 0x00FF00FF00FF00FF); + src = (src & 0x0000FFFF0000FFFF) + ((src >> 16) & 0x0000FFFF0000FFFF); + src = (src & 0x00000000FFFFFFFF) + ((src >> 32) & 0x00000000FFFFFFFF); + return src & 0x3F; +} + +/*------------------------------------------------*/ +/*---- Extract/Deposit bits under mask helpers ---*/ +/*------------------------------------------------*/ +ULong extract_bits_under_mask_helper( ULong src, ULong mask, UInt flag ) { + + UInt i; + ULong ones, zeros, mask_bit, bit_src; + + zeros = 0; + ones = 0; + + for (i=0; i<64; i++){ + mask_bit = 0x1 & (mask >> (63-i)); + bit_src = 0x1 & (src >> (63-i)); + + ones = ones << mask_bit; + ones = ones | (mask_bit & bit_src); + + zeros = zeros << (1^mask_bit); + zeros = zeros | ((1^mask_bit) & bit_src); + } + + if (flag == 1) + return ones; + else + return zeros; +} + + +/*----------------------------------------------*/ +/*--- Vector Evaluate Inst helper --------------*/ +/*----------------------------------------------*/ + /* This is a 64-bit version of the VXS Vector Evaluate + instruction xxeval. */ + +ULong vector_evaluate64_helper( ULong srcA, ULong srcB, ULong srcC, + ULong IMM ) { +#define MAX_BITS 64 +#define MAX_IMM_BITS 8 + + UInt i, select; + ULong bitA, bitB, bitC, result; + ULong bitIMM; + + result = 0; + + for (i=0; i<MAX_BITS; i++){ + bitA = 0x1 & (srcA >> i); + bitB = 0x1 & (srcB >> i); + bitC = 0x1 & (srcC >> i); + + select = (bitA << 2) | (bitB << 1) | bitC; + bitIMM = (IMM >> (MAX_IMM_BITS - 1 - select)) & 0x1; + result = result | (bitIMM << i); + } + return result; +#undef MAX_BITS +#undef MAX_IMM_BITS +} + + /*----------------------------------------------*/ /*--- The exported fns .. ---*/ /*----------------------------------------------*/ diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index a652e4d16c..213f6d4c6a 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -357,6 +357,11 @@ static UChar ifieldOPC( UInt instr ) { return toUChar( IFIELD( instr, 26, 6 ) ); } +/* Extract 11-bit secondary opcode, instr[10:0] */ +static UInt ifieldOPClo11 ( UInt instr) { + return IFIELD( instr, 0, 11 ); +} + /* Extract 10-bit secondary opcode, instr[10:1] */ static UInt ifieldOPClo10 ( UInt instr) { return IFIELD( instr, 1, 10 ); @@ -4638,6 +4643,72 @@ static IRExpr* negate_Vector ( IRType element_size, IRExpr* value ) value ); } +/* This function takes two quad_precision unsigned/signed integers of type + V128 and return 1 (Ity_Bit) if src_A = src_B, 0 otherwise. */ +static IRExpr * Quad_precision_int_eq ( IRTemp src_A, IRTemp src_B ) +{ + return mkAND1( binop( Iop_CmpEQ64, + unop( Iop_V128HIto64, mkexpr( src_A ) ), + unop( Iop_V128HIto64, mkexpr( src_B ) ) ), + binop( Iop_CmpEQ64, + unop( Iop_V128to64, mkexpr( src_A ) ), + unop( Iop_V128to64, mkexpr( src_B ) ) ) ); +} + +/* This function takes two quad_precision unsigned integers of type + V128 and return 1 if src_A > src_B, 0 otherwise. */ +static IRExpr * Quad_precision_uint_gt ( IRTemp src_A, IRTemp src_B ) +{ + IRExpr * hi_eq = binop( Iop_CmpEQ64, + unop( Iop_V128HIto64, mkexpr( src_A ) ), + unop( Iop_V128HIto64, mkexpr( src_B ) ) ); + + IRExpr * hi_gt = binop( Iop_CmpLT64U, + unop( Iop_V128HIto64, mkexpr( src_B ) ), + unop( Iop_V128HIto64, mkexpr( src_A ) ) ); + + IRExpr * lo_gt = binop( Iop_CmpLT64U, + unop( Iop_V128to64, mkexpr( src_B ) ), + unop( Iop_V128to64, mkexpr( src_A ) ) ); + + return mkOR1( hi_gt, mkAND1( hi_eq, lo_gt ) ); +} + +/* This function takes two quad_precision signed integers of type + V128 and return 1 if src_A > src_B, 0 otherwise. */ +static IRExpr * Quad_precision_sint_gt ( IRTemp src_A, IRTemp src_B ) +{ + + IRExpr * hi_eq = binop( Iop_CmpEQ64, + unop( Iop_V128HIto64, mkexpr( src_A ) ), + unop( Iop_V128HIto64, mkexpr( src_B ) ) ); + + IRExpr * lo_eq = binop( Iop_CmpEQ64, + unop( Iop_V128to64, mkexpr( src_A ) ), + unop( Iop_V128to64, mkexpr( src_B ) ) ); + + IRExpr * hi_gt = binop( Iop_CmpLT64S, + unop( Iop_V128HIto64, mkexpr( src_B ) ), + unop( Iop_V128HIto64, mkexpr( src_A ) ) ); + +/* If srcA and srcB are positive and srcA > srcB then lo_gteq = 1. + If srcA and srcB are negative and srcA > srcB, then the unsigned value + of the lower 64-bits are 2's complemented values means lower bits of srcB + must be less then the lower bits of srcA. + + srcA = 8000012380000123 7000000080000000 => (smaller/less negative) + - 7FFFFEDC7FFFFEDD 8FFFFFFF7FFFFFFF + srcB = 8000012380000123 8000012380000123 => + - 7FFFFEDC7FFFFEDD 7FFFFEDC7FFFFEDD +*/ + IRExpr * lo_gteq = binop( Iop_CmpLT64U, + unop( Iop_V128to64, mkexpr( src_B ) ), + unop( Iop_V128to64, mkexpr( src_A ) ) ); + + /* If hi is eq, then lower must be GT and not equal. */ + return mkOR1( hi_gt, mkAND1( hi_eq, mkAND1( lo_gteq, mkNOT1 ( lo_eq ) ) ) ); +} + /* This function takes two quad_precision floating point numbers of type V128 and return 1 if src_A > src_B, 0 otherwise. */ static IRExpr * Quad_precision_gt ( IRTemp src_A, IRTemp src_B ) @@ -17212,14 +17283,14 @@ static Bool dis_av_extend_sign_count_zero ( UInt prefix, UInt theInstr, } case 6: // vnegw, Vector Negate Word - DIP("vnegw v%d,%d,v%d", rT_addr, rA_addr, vB_addr); + DIP("vnegw v%u,v%u", rT_addr, vB_addr); /* multiply each word by -1 */ assign( vT, binop( Iop_Mul32x4, mkexpr( vB ), mkV128( 0xFFFF ) ) ); break; case 7: // vnegd, Vector Negate Doubleword - DIP("vnegd v%d,%d,v%d", rT_addr, rA_addr, vB_addr); + DIP("vnegd v%u,v%u", rT_addr, vB_addr); /* multiply each word by -1 */ assign( vT, binop( Iop_64HLtoV128, @@ -17299,7 +17370,7 @@ static Bool dis_av_extend_sign_count_zero ( UInt prefix, UInt theInstr, break; case 16: // vextsb2w, Vector Extend Sign Byte to Word - DIP("vextsb2w v%d,%d,v%d", rT_addr, rA_addr, vB_addr); + DIP("vextsb2w v%u,v%u", rT_addr, vB_addr); /* Iop_MullEven8Sx16 does a signed widening multiplication of byte to * two byte sign extended result. Then do a two byte to four byte sign @@ -17318,7 +17389,7 @@ static Bool dis_av_extend_sign_count_zero ( UInt prefix, UInt theInstr, break; case 17: // vextsh2w, Vector Extend Sign Halfword to Word - DIP("vextsh2w v%d,%d,v%d", rT_addr, rA_addr, vB_addr); + DIP("vextsh2w v%u,v%u", rT_addr, vB_addr); /* Iop_MullEven16Sx8 does a signed widening multiply of four byte * 8 bytes. Note contents of upper two bytes in word are @@ -17333,7 +17404,7 @@ static Bool dis_av_extend_sign_count_zero ( UInt prefix, UInt theInstr, break; case 24: // vextsb2d, Vector Extend Sign Byte to Doubleword - DIP("vextsb2d v%d,%d,v%d", rT_addr, rA_addr, vB_addr); + DIP("vextsb2d v%u,v%u", rT_addr, vB_addr); /* Iop_MullEven8Sx16 does a signed widening multiplication of byte to * two byte sign extended result. Then do a two byte to four byte sign @@ -17355,7 +17426,7 @@ static Bool dis_av_extend_sign_count_zero ( UInt prefix, UInt theInstr, break; case 25: // vextsh2d, Vector Extend Sign Halfword to Doubleword - DIP("vextsh2d v%d,%d,v%d", rT_addr, rA_addr, vB_addr); + DIP("vextsh2d v%u,v%u", rT_addr, vB_addr); assign( vT, binop( Iop_MullEven32Sx4, binop( Iop_64HLtoV128, @@ -17369,7 +17440,7 @@ static Bool dis_av_extend_sign_count_zero ( UInt prefix, UInt theInstr, break; case 26: // vextsw2d, Vector Extend Sign Word to Doubleword - DIP("vextsw2d v%d,%d,v%d", rT_addr, rA_addr, vB_addr); + DIP("vextsw2d v%u,v%u", rT_addr, vB_addr); assign( vT, binop( Iop_MullEven32Sx4, binop( Iop_64HLtoV128, @@ -17377,6 +17448,23 @@ static Bool dis_av_extend_sign_count_zero ( UInt prefix, UInt theInstr, mkU64( 0x0000000000000001 ) ), mkexpr( vB ) ) ); break; + case 27: // vextsd2q Vector Extend Sign Doubleword to Quadword + { + IRTemp sb = newTemp(Ity_I64); // sign bit extended + IRTemp tmp = newTemp(Ity_I64); + + DIP("vextsd2q v%u,v%u\n", rT_addr, vB_addr); + assign( tmp, unop( Iop_V128to64, mkexpr( vB ) ) ); + assign( sb, unop( Iop_1Sto64, + unop( Iop_64to1, + binop( Iop_Shr64, + mkexpr( tmp ), + mkU8( 63 ) ) ) ) ); + + assign( vT, binop( Iop_64HLtoV128, mkexpr( sb ), mkexpr( tmp ) ) ); + } + break; + case 28: // vctzb, Vector Count Trailing Zeros Byte { @@ -25857,6 +25945,54 @@ static Bool dis_av_arith ( UInt prefix, UInt theInstr ) // TODO: set VSCR[SAT] break; + case 0x0C8: // vmuloud (Vector multiply Odd Unsigned Doubleword VX-form) + case 0x1C8: // vmulosd (Vector multiply Odd Signed Doubleword VX-form) + case 0x2C8: // vmuleud (Vector multiply Even Unsigned Doubleword VX-form) + case 0x3C8: // vmulesd (Vector multiply Even Signed Doubleword VX-form) + { + IRTemp hi = newTemp(Ity_I64); + IRTemp lo = newTemp(Ity_I64); + IRTemp tmp128 = newTemp(Ity_I128); + + if ( opc2 == 0x0C8) { + DIP("vwuloud v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); + /* multiply lower D-words together, upper D-words not used. */ + assign( tmp128, binop( Iop_MullU64, + unop( Iop_V128to64, mkexpr( vA ) ), + unop( Iop_V128to64, mkexpr( vB ) ) ) ); + + } else if ( opc2 == 0x1C8) { + DIP("vwulosd v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); + /* multiply lower D-words together, upper D-words not used. */ + assign( tmp128, binop( Iop_MullS64, + unop( Iop_V128to64, mkexpr( vA ) ), + unop( Iop_V128to64, mkexpr( vB ) ) ) ); + + } else if ( opc2 == 0x2C8) { + DIP("vwuleud v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); + /* multiply upper D-words together, lower D-words not used. */ + assign( tmp128, binop( Iop_MullU64, + unop( Iop_V128HIto64, mkexpr( vA ) ), + unop( Iop_V128HIto64, mkexpr( vB ) ) ) ); + + } else { + DIP("vwulesd v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); + /* multiply upper D-words together, lower D-words not used. */ + assign( tmp128, binop( Iop_MullS64, + unop( Iop_V128HIto64, mkexpr( vA ) ), + unop( Iop_V128HIto64, mkexpr( vB ) ) ) ); + } + + /* Need to convert from I128 to V128. Don't have a direct + conversion. */ + assign( hi, unop( Iop_128HIto64, mkexpr( tmp128 ) ) ); + assign( lo, unop( Iop_128to64, mkexpr( tmp128 ) ) ); + + putVReg( vD_addr, + binop( Iop_64HLtoV128, mkexpr( hi ), mkexpr( lo ) ) ); + } + break; + case 0x300: // vaddsbs (Add Signed Byte Saturate, AV p138) DIP("vaddsbs v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_QAdd8Sx16, mkexpr(vA), mkexpr(vB)) ); @@ -26619,6 +26755,376 @@ static Bool dis_av_arith ( UInt prefix, UInt theInstr ) return True; } +static Bool dis_vx_quadword_arith ( UInt prefix, UInt theInstr ) +{ + /* Quad word operations, VX-Form */ + UChar vT_addr = ifieldRegDS(theInstr); + UChar vA_addr = ifieldRegA(theInstr); + UChar vB_addr = ifieldRegB(theInstr); + UChar opc1 = ifieldOPC(theInstr); + UInt opc2 = ifieldOPClo11( theInstr ); + IRTemp vA = newTemp(Ity_V128); + IRTemp vB = newTemp(Ity_V128); + + if (opc1 != 0x4) { + vex_printf("ERROR: dis_vx_quadword_arith(ppc)\n"); + return False; + } + + assign( vA, getVReg( vA_addr ) ); + assign( vB, getVReg( vB_addr ) ); + + switch (opc2) { + case 0x005: //vrlq Vector Rotate Left Quadword + { + IRTemp sh = newTemp(Ity_I8); /* shift amout is vB[57:63] */ + IRTemp shr = newTemp(Ity_I8); + IRTemp vA_shl = newTemp(Ity_V128); + IRTemp vA_shr = newTemp(Ity_V128); + + DIP("vrlq v%u,v%u,v%u\n", vT_addr, vA_addr, vB_addr); + + assign( sh, + binop( Iop_And8, + mkU8( 0x7F ), + unop( Iop_16to8, + unop( Iop_32to16, + unop( Iop_64to32, + unop( Iop_V128HIto64, + mkexpr( vB ) ) ) ) ) ) ); + + assign( shr, binop( Iop_Sub8, mkU8( 128 ), mkexpr( sh ) ) ); + assign( vA_shl, binop( Iop_ShlV128, mkexpr( vA ), mkexpr( sh ) ) ); + assign( vA_shr, binop( Iop_ShrV128, mkexpr( vA ), mkexpr( shr ) ) ); + putVReg( vT_addr, + binop( Iop_OrV128, mkexpr( vA_shl ), mkexpr( vA_shr ) ) ); + } + break; + + case 0x00B: //vdivuq Vector Divide Unsigned Quadword + vex_printf("WARNING: instruction vdivuq not currently supported. dis_vx_quadword_arith(ppc)\n"); + break; + + case 0x101: //vcmpuq Vector Compare Unsigned Quadword + { + IRTemp lt = newTemp(Ity_I32); + IRTemp gt = newTemp(Ity_I32); + IRTemp eq = newTemp(Ity_I32); + IRTemp cc = newTemp(Ity_I32); + UInt BF = IFIELD( theInstr, (31-8), 3 ); + + DIP("vcmpuq %u,v%u,v%u\n", BF, vA_addr, vB_addr); + + assign ( lt, unop( Iop_1Uto32, Quad_precision_uint_gt( vB, vA ) ) ); + assign ( gt, unop( Iop_1Uto32, Quad_precision_uint_gt( vA, vB ) ) ); + assign ( eq, unop( Iop_1Uto32, Quad_precision_int_eq( vA, vB ) ) ); + + assign( cc, binop( Iop_Or32, + binop( Iop_Shl32, mkexpr( lt ), mkU8( 3 ) ), + binop( Iop_Or32, + binop( Iop_Shl32, + mkexpr( gt ), mkU8( 2 ) ), + binop( Iop_Shl32, + mkexpr( eq ), mkU8( 1 ) ) ) ) ); + + putGST_field( PPC_GST_CR, mkexpr( cc ), BF ); + } + break; + + case 0x105: //vslq Vector Shift Left Quadword + case 0x205: //vsrq Vector Shift Right Quadword + { + IRTemp sh = newTemp(Ity_I8); /* shift amout is vB[57:63] */ + + assign( sh, + binop( Iop_And8, + mkU8( 0x7F ), + unop( Iop_16to8, + unop( Iop_32to16, + unop( Iop_64to32, + unop( Iop_V128HIto64, + mkexpr( vB ) ) ) ) ) ) ); + + if (opc2 == 0x105) { + DIP("vslq v%u,v%u,v%u\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, + binop( Iop_ShlV128, mkexpr( vA ), mkexpr( sh ) ) ); + + } else { + DIP("vsrq v%u,v%u,v%u\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, + binop( Iop_ShrV128, mkexpr( vA ), mkexpr( sh ) ) ); + } + } + break; + + case 0x10B: //vdivsq Vector Divide Signed Quadword + vex_printf("WARNING: instruction vdivsq not currently supported. dis_vx_quadword_arith(ppc)\n"); + break; + + case 0x141: //vcmpsq Vector Compare Signed Quadword + { + IRTemp lt = newTemp(Ity_I32); + IRTemp gt = newTemp(Ity_I32); + IRTemp eq = newTemp(Ity_I32); + IRTemp cc = newTemp(Ity_I32); + UInt BF = IFIELD( theInstr, (31-8), 3 ); + + DIP("vcmpsq %u,v%u,v%u\n", BF, vA_addr, vB_addr); + + assign ( lt, unop( Iop_1Uto32, Quad_precision_sint_gt( vB, vA ) ) ); + assign ( gt, unop( Iop_1Uto32, Quad_precision_sint_gt( vA, vB ) ) ); + assign ( eq, unop( Iop_1Uto32, Quad_precision_int_eq( vA, vB ) ) ); + + assign( cc, binop( Iop_Or32, + binop( Iop_Shl32, mkexpr( lt ), mkU8( 3 ) ), + binop( Iop_Or32, + binop( Iop_Shl32, + mkexpr( gt ), mkU8( 2 ) ), + binop( Iop_Shl32, + mkexpr( eq ), mkU8( 1 ) ) ) ) ); + + putGST_field( PPC_GST_CR, mkexpr( cc ), BF ); + } + break; + + case 0x045: //vrlqmi Vector Rotate Left Quadword then Mask Insert + case 0x145: //vrlqnm Vector Rotate Left Quadword then AND with Mask + { + IRTemp sh = newTemp(Ity_I8); + IRTemp shr = newTemp(Ity_I8); + IRTemp vA_shl = newTemp(Ity_V128); + IRTemp vA_shr = newTemp(Ity_V128); + IRTemp mask = newTemp(Ity_V128); + IRTemp mb = newTemp(Ity_I8); /* mask begin */ + IRTemp me = newTemp(Ity_I8); /* mask end */ + IRTemp tmp = newTemp(Ity_I8); /* mask end tmp */ + + /* rotate value in bits vB[57:63] */ + assign( sh, + binop( Iop_And8, + mkU8( 0x7F ), + unop ( Iop_16to8, + unop ( Iop_32to16, + unop ( Iop_64to32, + unop( Iop_V128HIto64, + mkexpr( vB ) ) ) ) ) ) ); + + /* mask begin in bits vB[41:47] */ + assign( mb, + binop( Iop_And8, + mkU8( 0x7F ), + unop ( Iop_16to8, + unop ( Iop_32to16, + binop( Iop_Shr32, + unop ( Iop_64to32, + unop( Iop_V128HIto64, + mkexpr( vB ) ) ), + mkU8 ( 16 ) ) ) ) ) ); + + /* mask end in bits vB[49:55] */ + assign( tmp, + unop ( Iop_16to8, + unop ( Iop_32to16, + binop( Iop_Shr32, + unop ( Iop_64to32, + unop( Iop_V128HIto64, + mkexpr( vB ) ) ), + mkU8 ( 8 ) ) ) ) ); + + assign( me, + binop( Iop_Sub8, + mkU8( 127 ), + binop( Iop_And8, + mkU8( 0x7F ), + mkexpr( tmp ) ) ) ); + + /* Create mask, Start with all 1's, shift right and then left by + (127-me) to clear the lower me bits. Similarly, shift left then + right by mb to clear upper bits. */ + + assign( mask, + binop( Iop_ShrV128, + binop( Iop_ShlV128, + binop( Iop_ShlV128, + binop( Iop_ShrV128, + binop( Iop_64HLtoV128, + mkU64( 0xFFFFFFFFFFFFFFFF ), + mkU64( 0xFFFFFFFFFFFFFFFF ) ), + mkexpr( me ) ), + mkexpr( me ) ), + mkexpr( mb ) ), + mkexpr( mb ) ) ); + + assign( shr, binop( Iop_Sub8, mkU8( 128 ), mkexpr( sh ) ) ); + assign( vA_shl, binop( Iop_ShlV128, mkexpr( vA ), mkexpr( sh ) ) ); + assign( vA_shr, binop( Iop_ShrV128, mkexpr( vA ), mkexpr( shr ) ) ); + + if (opc2 == 0x045) { + IRTemp vT_initial = newTemp(Ity_V128); + + DIP("vrlqmi v%u,v%u,v%u\n", vT_addr, vA_addr, vB_addr); + + assign( vT_initial, getVReg( vT_addr ) ); + + /* Mask rotated value from vA and insert into vT */ + putVReg( vT_addr, + binop( Iop_OrV128, + binop( Iop_AndV128, + unop( Iop_NotV128, mkexpr( mask ) ), + mkexpr( vT_initial ) ), + binop( Iop_AndV128, + binop( Iop_OrV128, + mkexpr( vA_shl ), + mkexpr( vA_shr ) ), + mkexpr( mask ) ) ) ); + + } else { + DIP("vrlqnm v%u,v%u\n", vA_addr, vB_addr); + + putVReg( vT_addr, + binop( Iop_AndV128, + binop( Iop_OrV128, + mkexpr( vA_shl ), + mkexpr( vA_shr ) ), + mkexpr( mask ) ) ); + } + } + break; + + case 0x1C7: //vcmpequq Vector Compare Equal Quadword + case 0x5C7: //vcmpequq. + { + IRTemp eq = newTemp(Ity_I1); + IRTemp cc = newTemp(Ity_I32); + UInt Rc = IFIELD( theInstr, (31-21), 1 ); + UInt cc_field = 6; + + DIP("vcmpequq%s v%u,v%u,v%u\n", + Rc ? ".":"", vT_addr, vA_addr, vB_addr); + + assign ( eq, Quad_precision_int_eq( vA, vB ) ); + + assign( cc, binop( Iop_Shl32, + unop( Iop_1Uto32, mkexpr( eq ) ), + mkU8( 1 ) ) ); + + if (Rc) putGST_field( PPC_GST_CR, mkexpr( cc ), cc_field ); + + putVReg( vT_addr, binop( Iop_64HLtoV128, + unop( Iop_1Sto64, mkexpr( eq ) ), + unop( Iop_1Sto64, mkexpr( eq ) ) ) ); + } + break; + + case 0x287: //vcmpgtuq Vector Compare Greater Than Unsigned Quadword + case 0x687: //vcmpgtuq. + case 0x387: //vcmpgtsq Vector Compare Greater Than Signed Quadword + case 0x787: //vcmpgtsq. + { + IRTemp gt = newTemp(Ity_I1); + IRTemp cc = newTemp(Ity_I32); + UInt Rc = IFIELD( theInstr, (31-21), 1 ); + UInt cc_field = 6; + + if ((opc2 == 0x287) || (opc2 == 0x687)) { + DIP("vcmpgtuq%s v%u,v%u,v%u\n", + Rc ? ".":"", vT_addr, vA_addr, vB_addr); + + assign ( gt, Quad_precision_uint_gt( vA, vB ) ); + + } else { + DIP("vcmpgtsq%s v%u,v%u,v%u\n", + Rc ? ".":"", vT_addr, vA_addr, vB_addr); + + assign ( gt, Quad_precision_sint_gt( vA, vB ) ); + } + + assign( cc, binop( Iop_Shl32, + unop( Iop_1Uto32, mkexpr( gt ) ), + mkU8( 2 ) ) ); + + if (Rc) putGST_field( PPC_GST_CR, mkexpr( cc ), cc_field ); + + putVReg( vT_addr, binop( Iop_64HLtoV128, + unop( Iop_1Sto64, mkexpr( gt ) ), + unop( Iop_1Sto64, mkexpr( gt ) ) ) ); + } + break; + + case 0x20B: //vdiveuq Vector Divide Extended Unsigned Quadword + vex_printf("WARNING: instruction vdiveuq not currently supported. dis_vx_quadword_arith(ppc)\n"); + break; + + case 0x305: //vsraq Vector Shift Right Algebraic Quadword + { + IRTemp sh = newTemp(Ity_I8); /* shift amout is vB[57:63] */ + IRTemp shr = newTemp(Ity_I8); + IRTemp tmp = newTemp(Ity_I64); + IRTemp vA_sign = newTemp(Ity_V128); /* sign bit of vA replicated */ + + DIP("vsraq v%u,v%u,v%u\n", vT_addr, vA_addr, vB_addr); + + assign( sh, + binop( Iop_And8, + mkU8( 0x7F ), + unop( Iop_16to8, + unop( Iop_32to16, + unop( Iop_64to32, + unop( Iop_V128HIto64, + mkexpr( vB ) ) ) ) ) ) ); + assign( shr, binop( Iop_Sub8, mkU8( 128 ), mkexpr( sh ) ) ); + + /* Replicate the sign bit in all bit positions if sh is not zero. Clear the lower bits + from [sh:127] by shifting right, then left by (127-sh). + */ + assign( tmp, + binop( Iop_And64, + unop( Iop_1Sto64, + binop( Iop_CmpNE8, mkexpr( sh ), mkU8( 0 ) ) ), + unop( Iop_1Sto64, + unop( Iop_64to1, + binop( Iop_Shr64, + unop( Iop_V128HIto64, + mkexpr( vA ) ), + mkU8( 63 ) ) ) ) ) ); + assign( vA_sign, + binop( Iop_ShlV128, + binop( Iop_ShrV128, + binop( Iop_64HLtoV128, + mkexpr( tmp ), + mkexpr( tmp ) ), + mkexpr( shr ) ), + mkexpr( shr ) ) ); + + putVReg( vT_addr, + binop( Iop_OrV128, + binop( Iop_ShrV128, mkexpr( vA ), mkexpr( sh ) ), + mkexpr( vA_sign ) ) ); + } + break; + + case 0x30B: //vdivesq Vector Divide Extended Signed Quadword + vex_printf("WARNING: instruction vdivesq not currently supported. dis_vx_quadword_arith(ppc)\n"); + break; + + case 0x60B: //vmoduq Vector Modulo Unsigned Quadword + vex_printf("WARNING: instruction vmoduq not currently supported. dis_vx_quadword_arith(ppc)\n"); + break; + + case 0x70B: //vmodsq Vector Modulo Signed Quadword + vex_printf("WARNING: instruction vmodsq not currently supported. dis_vx_quadword_arith(ppc)\n"); + break; + + default: + vex_printf("dis_av_arith(ppc)(opc2=0x%x)\n", opc2); + return False; + } /* switch (opc2) */ + + return True; +} + + /* AltiVec Logic Instructions */ @@ -28994,7 +29500,7 @@ static IRExpr * bcd_sign_code_adjust( UInt ps, IRExpr * tmp) * because passing a constant via triop() breaks the vbit-test test. The * vbit-tester assumes it can set non-zero shadow bits for the triop() * arguments. Thus they have to be expressions not a constant. - * Use 32-bit compare instructiions as 64-bit compares are not supported + * Use 32-bit compare instructions as 64-bit compares are not supported * in 32-bit mode. */ IRTemp mask = newTemp(Ity_I64); @@ -33292,6 +33798,13 @@ DisResult disInstr_PPC_WRK ( if (dis_av_arith( prefix, theInstr )) goto decode_success; goto decode_failure; + case 0x0C8: case 0x1C8: case 0x2C8: // vmuloud, vmulosd, vmuleud + case 0x3C8: // vmulesd + if (!allow_V) goto decode_noV; + if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; + if (dis_av_arith( prefix, theInstr )) goto decode_success; + goto decode_failure; + case 0x08B: case 0x18B: // vdivuw, vdivsw case 0x289: case 0x389: // vmulhuw, vmulhsw case 0x28B: case 0x38B: // vdiveuw, vdivesw @@ -33305,6 +33818,24 @@ DisResult disInstr_PPC_WRK ( if (dis_av_arith( prefix, theInstr )) goto decode_success; goto decode_failure; + case 0x005: // vrlq + case 0x00B: case 0x10B: // vdivuq, vdivsq + case 0x045: // vrlqmi + case 0x101: case 0x141: // vcmpuq, vcmpsq + case 0x105: case 0x145: // vslq, vrlqnm + case 0x1C7: case 0x5C7: // vcmpequq, vcmpequq. + case 0x205: // vsrq + case 0x20B: case 0x30B: // vdivueq, vdivesq + case 0x287: case 0x687: // vcmpgtuq, vcmpgtuq. + case 0x305: // vsraq + case 0x387: case 0x787: // vcmpgtsq, vcmpgtsq. + case 0x60B: case 0x70B: // vmoduq, vmodsq + if (!allow_V) goto decode_noV; + if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; + if (dis_vx_quadword_arith( prefix, theInstr )) + goto decode_success; + goto decode_failure; + case 0x088: case 0x089: // vmulouw, vmuluwm case 0x0C0: case 0x0C2: // vaddudm, vmaxud case 0x1C2: case 0x2C2: case 0x3C2: // vmaxsd, vminud, vminsd @@ -33470,8 +34001,14 @@ DisResult disInstr_PPC_WRK ( // vnegw, vnegd // vprtybw, vprtybd, vprtybq // vctzb, vctzh, vctzw, vctzd + // vextsd2q if (!allow_V) goto decode_noV; - if (dis_av_extend_sign_count_zero( prefix, theInstr, allow_isa_3_0 )) + if ( !(allow_isa_3_1) + && (ifieldRegA( theInstr ) == 27) ) // vextsd2q + goto decode_noIsa3_1; + if (dis_av_extend_sign_count_zero( prefix, theInstr, + allow_isa_3_0 )) + goto decode_success; goto decode_failure; |
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From: Carl L. <ca...@so...> - 2020-11-09 23:46:32
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3ec034d7465fcddecc323a7012038f6b6987a264 commit 3ec034d7465fcddecc323a7012038f6b6987a264 Author: Carl Love <ce...@us...> Date: Thu Apr 30 10:37:07 2020 -0500 ISA 3.1 VSX Scalar Minimum/Maximum/Compare Quad-Precision Operations Add support for: xscmpeqqp VSX Scalar Compare Equal Quad-Precision xscmpgeqp VSX Scalar Compare Greater Than or Equal Quad-Precision xscmpgtqp VSX Scalar Compare Greater Than Quad-Precision xsmaxcqp VSX Scalar Maximum Type-C Quad-Precision xsmincqp VSX Scalar Minimum Type-C Quad-Precision Diff: --- VEX/priv/guest_ppc_toIR.c | 200 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 185 insertions(+), 15 deletions(-) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 602831e91a..a652e4d16c 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -22500,7 +22500,7 @@ dis_vx_misc ( UInt prefix, UInt theInstr, UInt opc2 ) case 0x4C: //xscmpgedp { - DIP("xscmpeqdp v%d,v%d,v%d\n", XT, XA, XB); + DIP("xscmpgedp v%u,v%u,v%u\n", XT, XA, XB); /* compare src 1 >= src 2 */ /* result of Iop_CmpF64 is 0x40 if operands are equal, mask is all 1's if equal. */ @@ -24759,9 +24759,12 @@ dis_vx_scalar_quad_precision ( UInt prefix, UInt theInstr ) /* XX1-Form */ UChar opc1 = ifieldOPC( theInstr ); UInt opc2 = ifieldOPClo10( theInstr ); - UChar vT_addr = ifieldRegDS( theInstr ) + 32; - UChar vA_addr = ifieldRegA( theInstr ) + 32; - UChar vB_addr = ifieldRegB( theInstr ) + 32; + UChar VRT = ifieldRegDS( theInstr ); + UChar VRA = ifieldRegA( theInstr ); + UChar VRB = ifieldRegB( theInstr ); + UChar vT_addr = VRT + 32; + UChar vA_addr = VRA + 32; + UChar vB_addr = VRB + 32; IRTemp vA = newTemp( Ity_V128 ); IRTemp vB = newTemp( Ity_V128 ); IRTemp vT = newTemp( Ity_V128 ); @@ -24778,12 +24781,55 @@ dis_vx_scalar_quad_precision ( UInt prefix, UInt theInstr ) switch (opc2) { + case 0x044: // xscmpeqqp (VSX Scalar Compare Equal Quad-Precision X-form) + { + IRTemp vA_hi = newTemp( Ity_I64 ); + IRTemp vA_lo = newTemp( Ity_I64 ); + IRTemp vB_hi = newTemp( Ity_I64 ); + IRTemp vB_lo = newTemp( Ity_I64 ); + IRTemp tmp = newTemp( Ity_I64 ); + IRTemp src_not_NaN = newTemp( Ity_I64 ); + + /* NOTE: exceptions are not implemented, will not set VXSNAN, VXVC or + FX registers. */ + DIP("xscmpeqqp v%u,v%u,v%u\n", VRT, VRA, VRB); + + assign( vA, getVSReg( vA_addr ) ); + + /* neither vA or vB is NaN */ + assign( src_not_NaN, + unop(Iop_Not64, + unop(Iop_1Sto64, + mkOR1( is_NaN( Ity_V128, vA ), + is_NaN( Ity_V128, vB ) ) ) ) ); + + assign( vA_hi, unop( Iop_V128HIto64, mkexpr( vA ) ) ); + assign( vA_lo, unop( Iop_V128to64, mkexpr( vA ) ) ); + assign( vB_hi, unop( Iop_V128HIto64, mkexpr( vB ) ) ); + assign( vB_lo, unop( Iop_V128to64, mkexpr( vB ) ) ); + + assign( tmp, + binop( Iop_And64, + mkexpr( src_not_NaN ), + binop( Iop_And64, + unop( Iop_1Sto64, + binop( Iop_CmpEQ64, + mkexpr( vA_hi ), + mkexpr( vB_hi ) ) ), + unop( Iop_1Sto64, + binop( Iop_CmpEQ64, + mkexpr( vA_lo ), + mkexpr( vB_lo ) ) ) ) ) ); + assign( vT, binop( Iop_64HLtoV128, mkexpr( tmp ), mkexpr( tmp ) ) ); + } + break; + case 0x064: // xscpsgnqp (VSX Scalar Copy Sign Quad-Precision) { IRTemp sign_vA = newTemp( Ity_I64 ); IRTemp vB_hi = newTemp( Ity_I64 ); - DIP("xscpsgnqp v%d,v%d,v%d\n", vT_addr, vA_addr, vB_addr); + DIP("xscpsgnqp v%u,v%u,v%u\n", VRT, VRA, VRB); assign( vA, getVSReg(vA_addr) ); @@ -24803,6 +24849,64 @@ dis_vx_scalar_quad_precision ( UInt prefix, UInt theInstr ) break; } + case 0x0C4: // xscmpgeqp (VSX Scalar Compare Greater Than or + // Equal Quad-Precision X-form) + { + IRTemp tmp = newTemp( Ity_I64 ); + IRTemp src_not_NaN = newTemp( Ity_I64 ); + + /* NOTE: exceptions are not implemented, will not set VXSNAN, VXVC or + FX registers. */ + DIP("xscmpgeqp v%u,v%u,v%u\n", VRT, VRA, VRB); + + assign( vA, getVSReg( vA_addr ) ); + + /* neither vA or vB is NaN */ + assign( src_not_NaN, + unop(Iop_Not64, + unop(Iop_1Sto64, + mkOR1( is_NaN( Ity_V128, vA ), + is_NaN( Ity_V128, vB ) ) ) ) ); + + /* vA >= vB is Not( vB > vA) */ + assign( tmp, + binop( Iop_And64, + mkexpr( src_not_NaN ), + unop( Iop_Not64, + unop( Iop_1Sto64, + Quad_precision_gt( vB, vA ) ) ) ) ) ; + assign( vT, binop( Iop_64HLtoV128, mkexpr( tmp ), mkexpr( tmp ) ) ); + } + break; + + case 0x0E4: // xscmpgtqp (VSX Scalar Compare Greater Than + // Quad-Precision X-form) + { + IRTemp tmp = newTemp( Ity_I64 ); + IRTemp src_not_NaN = newTemp( Ity_I64 ); + + /* NOTE: exceptions are not implemented, will not set VXSNAN, VXVC or + FX registers. */ + DIP("xscmpgtqp v%u,v%u,v%u\n", VRT, VRA, VRB); + + assign( vA, getVSReg( vA_addr ) ); + + /* neither vA or vB is NaN */ + assign( src_not_NaN, + unop(Iop_Not64, + unop(Iop_1Sto64, + mkOR1( is_NaN( Ity_V128, vA ), + is_NaN( Ity_V128, vB ) ) ) ) ); + + assign( tmp, + binop( Iop_And64, + mkexpr( src_not_NaN ), + unop( Iop_1Sto64, Quad_precision_gt( vA, vB ) ) ) ); + + assign( vT, binop( Iop_64HLtoV128, mkexpr( tmp ), mkexpr( tmp ) ) ); + } + break; + case 0x084: // xscmpoqp (VSX Scalar Compare Ordered Quad-Precision) case 0x284: // xscmpuqp (VSX Scalar Compare Unrdered Quad-Precision) { @@ -24815,9 +24919,9 @@ dis_vx_scalar_quad_precision ( UInt prefix, UInt theInstr ) IRTemp CC = newTemp( Ity_I32 ); if (opc2 == 0x084) { - DIP("xscmpoqp %u,v%d,v%u\n", BF, vA_addr, vB_addr); + DIP("xscmpoqp %u,v%d,v%u\n", BF, VRA, VRB); } else { - DIP("xscmpuqp %u,v%d,v%u\n", BF, vA_addr, vB_addr); + DIP("xscmpuqp %u,v%d,v%u\n", BF, VRA, VRB); } assign( vA, getVSReg(vA_addr)); @@ -24916,7 +25020,7 @@ dis_vx_scalar_quad_precision ( UInt prefix, UInt theInstr ) IRTemp eq_lt_gt = newTemp( Ity_I32 ); IRTemp CC = newTemp( Ity_I32 ); - DIP("xscmpexpqp %u,v%d,v%u\n", BF, vA_addr, vB_addr); + DIP("xscmpexpqp %u,v%u,v%u\n", BF, VRA, VRB); assign( vA, getVSReg(vA_addr)); @@ -24981,6 +25085,62 @@ dis_vx_scalar_quad_precision ( UInt prefix, UInt theInstr ) } break; + case 0x2A4: // xsmaxcqp (VSX Scalar Maximum Type-C Quad Precision) + case 0x2E4: // xsmincqp (VSX Scalar Minimum Type-C Quad Precision) + { + IRTemp tmp_cmp = newTemp( Ity_I64 ); + IRTemp cmp_mask = newTemp( Ity_V128 ); + IRTemp result = newTemp( Ity_V128 ); + IRTemp src_not_NaN = newTemp( Ity_V128 ); + IRTemp tmp_src_not_NaN = newTemp( Ity_I64 ); + + /* NOTE: exceptions are not implemented, will not set VXSNAN, VXVC or + FX registers. */ + assign( vA, getVSReg( vA_addr ) ); + + if (opc2 == 0x2A4) { + DIP("xsmaxcqp v%u,v%u,v%u\n", VRT, VRA, VRB); + assign( tmp_cmp, unop( Iop_1Sto64, Quad_precision_gt( vA, vB ) ) ); + + } else { + DIP("xsmincqp v%u,v%u,v%u\n", VRT, VRA, VRB); + assign( tmp_cmp, unop( Iop_1Sto64, Quad_precision_gt( vB, vA ) ) ); + } + + /* if either vA or vB is NaN, result is vB */ + assign( tmp_src_not_NaN, + unop( Iop_Not64, + unop( Iop_1Sto64, + mkOR1( is_NaN( Ity_V128, vA ), + is_NaN( Ity_V128, vB ) ) ) ) ); + + assign( src_not_NaN, binop( Iop_64HLtoV128, + mkexpr( tmp_src_not_NaN ), + mkexpr( tmp_src_not_NaN ) ) ); + + assign( cmp_mask, binop( Iop_64HLtoV128, + mkexpr( tmp_cmp ), mkexpr( tmp_cmp ) ) ); + + /* comparison is True, then result = vA, otherwise result = vB */ + assign( result, binop( Iop_OrV128, + binop( Iop_AndV128, + mkexpr( cmp_mask ), + mkexpr( vA ) ), + binop( Iop_AndV128, + unop( Iop_NotV128, mkexpr( cmp_mask ) ), + mkexpr( vB ) ) ) ); + + assign( vT, + binop( Iop_OrV128, + binop( Iop_AndV128, + mkexpr( src_not_NaN ), + mkexpr( result ) ), + binop( Iop_AndV128, + unop( Iop_NotV128, mkexpr( src_not_NaN ) ), + mkexpr( vB ) ) ) ); + } + break; + case 0x2C4: // xststdcqp (VSX Scalar Quad-Precision Test Data Class) { UInt BF = IFIELD( theInstr, 23, 3 ); @@ -24993,7 +25153,7 @@ dis_vx_scalar_quad_precision ( UInt prefix, UInt theInstr ) IRTemp zero = newTemp( Ity_I64 ); IRTemp dnorm = newTemp( Ity_I64 ); - DIP("xststdcqp %u,v%d,%u\n", BF, vB_addr, DCMX_mask); + DIP("xststdcqp %u,v%u,%u\n", BF, VRB, DCMX_mask); assign( zero, unop( Iop_1Uto64, is_Zero( Ity_V128, vB ) ) ); assign( pos, unop( Iop_1Uto64, @@ -25040,7 +25200,7 @@ dis_vx_scalar_quad_precision ( UInt prefix, UInt theInstr ) switch (inst_select) { case 0: - DIP("xsabsqp v%d,v%d\n", vT_addr, vB_addr); + DIP("xsabsqp v%u,v%u\n", VRT, VRB); assign( vT, binop( Iop_AndV128, mkexpr( vB ), binop( Iop_64HLtoV128, mkU64( 0x7FFFFFFFFFFFFFFF ), @@ -25048,7 +25208,7 @@ dis_vx_scalar_quad_precision ( UInt prefix, UInt theInstr ) break; case 2: - DIP("xsxexpqp v%d,v%d\n", vT_addr, vB_addr); + DIP("xsxexpqp v%u,v%u\n", VRT, VRB); assign( vT, binop( Iop_ShrV128, binop( Iop_AndV128, mkexpr( vB ), binop( Iop_64HLtoV128, @@ -25058,7 +25218,7 @@ dis_vx_scalar_quad_precision ( UInt prefix, UInt theInstr ) break; case 8: - DIP("xsnabsqp v%d,v%d\n", vT_addr, vB_addr); + DIP("xsnabsqp v%u,v%u\n", VRT, VRB); assign( vT, binop( Iop_OrV128, mkexpr( vB ), binop( Iop_64HLtoV128, mkU64( 0x8000000000000000 ), @@ -25066,7 +25226,7 @@ dis_vx_scalar_quad_precision ( UInt prefix, UInt theInstr ) break; case 16: - DIP("xsnegqp v%d,v%d\n", vT_addr, vB_addr); + DIP("xsnegqp v%u,v%u\n", VRT, VRB); assign( vT, binop( Iop_XorV128, mkexpr( vB ), binop( Iop_64HLtoV128, mkU64( 0x8000000000000000 ), @@ -25078,7 +25238,7 @@ dis_vx_scalar_quad_precision ( UInt prefix, UInt theInstr ) IRTemp expZero = newTemp( Ity_I64 ); IRTemp expInfinity = newTemp( Ity_I64 ); - DIP("xsxsigqp v%d,v%d\n", vT_addr, vB_addr); + DIP("xsxsigqp v%u,v%u\n", VRT, VRB); assign( expZero, unop( Iop_1Uto64, binop( Iop_CmpNE64, @@ -25127,7 +25287,7 @@ dis_vx_scalar_quad_precision ( UInt prefix, UInt theInstr ) { IRTemp exp = newTemp( Ity_I64 ); - DIP("xsiexpqp v%d,v%d,v%d\n", vT_addr, vA_addr, vB_addr); + DIP("xsiexpqp v%d,v%d,v%d\n", VRT, VRA, VRB); assign( vA, getVSReg( vA_addr ) ); assign( exp, binop( Iop_And64, @@ -32484,6 +32644,16 @@ DisResult disInstr_PPC_WRK ( goto decode_success; goto decode_failure; + case 0x044: // xscmpeqqp + case 0x0C4: // xscmpgeqp + case 0x0E4: // xscmpgtqp + case 0x2A4: // xsmaxcqp + case 0x2E4: // xsmincqp + if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; + if (dis_vx_scalar_quad_precision( prefix, theInstr )) + goto decode_success; + goto decode_failure; + /* Instructions implemented using ISA 3.0 instructions */ // xsaddqpo (VSX Scalar Add Quad-Precision [using round to ODD] case 0x004: // xsaddqp (VSX Scalar Add Quad-Precision [using RN mode] |
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From: Paul F. <pa...@so...> - 2020-11-09 15:32:38
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=35c9c33897ef89b08e1518ed16244e70bc6996da commit 35c9c33897ef89b08e1518ed16244e70bc6996da Author: Paul Floyd <pj...@wa...> Date: Mon Nov 9 16:31:40 2020 +0100 Bug 384729 - __libc_freeres inhibits cross-platform valgrind Diff: --- coregrind/vg_preloaded.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/coregrind/vg_preloaded.c b/coregrind/vg_preloaded.c index 3ea3761f97..39d82c7c23 100644 --- a/coregrind/vg_preloaded.c +++ b/coregrind/vg_preloaded.c @@ -68,13 +68,12 @@ void VG_NOTIFY_ON_LOAD(freeres)(Vg_FreeresToRun to_run) _ZN9__gnu_cxx9__freeresEv(); } -# if defined(VGO_linux) - /* __libc_freeres() not yet available on Solaris. */ - extern void __libc_freeres(void); - if ((to_run & VG_RUN__LIBC_FREERES) != 0) { + extern void __libc_freeres(void) __attribute__((weak)); + if (((to_run & VG_RUN__LIBC_FREERES) != 0) && + (__libc_freeres != NULL)) { __libc_freeres(); } -# endif + # endif VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__FREERES_DONE, 0, 0, 0, 0, 0); |
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From: Paul F. <pa...@so...> - 2020-11-09 15:12:04
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e300cb0d8d36dd8a7c3be7b8d0796a3d2cfa98c1 commit e300cb0d8d36dd8a7c3be7b8d0796a3d2cfa98c1 Author: Paul Floyd <pj...@wa...> Date: Mon Nov 9 16:10:52 2020 +0100 Pushed binary by mistake Diff: --- memcheck/tests/sized_delete | Bin 20736 -> 0 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/memcheck/tests/sized_delete b/memcheck/tests/sized_delete deleted file mode 100755 index a9f716d73e..0000000000 Binary files a/memcheck/tests/sized_delete and /dev/null differ |
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From: Paul F. <pa...@so...> - 2020-11-09 08:37:46
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=6faec425f13025084076e6fd2e1399a1834a3782 commit 6faec425f13025084076e6fd2e1399a1834a3782 Author: Paul Floyd <pj...@wa...> Date: Mon Nov 9 09:37:17 2020 +0100 Add testcase for C++14 sized delete Diff: --- .gitignore | 1 + memcheck/tests/Makefile.am | 8 +++++++- memcheck/tests/filter_sized_delete | 4 ++++ memcheck/tests/sized_delete | Bin 0 -> 20736 bytes memcheck/tests/sized_delete.cpp | 12 ++++++++++++ memcheck/tests/sized_delete.stderr.exp | 4 ++++ memcheck/tests/sized_delete.stderr.exp-x86 | 4 ++++ memcheck/tests/sized_delete.vgtest | 4 ++++ 8 files changed, 36 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 18067259c1..47e53a9542 100644 --- a/.gitignore +++ b/.gitignore @@ -901,6 +901,7 @@ /memcheck/tests/sigkill /memcheck/tests/signal2 /memcheck/tests/sigprocmask +/memcheck/tests/sized_delete /memcheck/tests/stack_changes /memcheck/tests/stack_switch /memcheck/tests/static_malloc diff --git a/memcheck/tests/Makefile.am b/memcheck/tests/Makefile.am index 84b2a81cea..28f26bbebe 100644 --- a/memcheck/tests/Makefile.am +++ b/memcheck/tests/Makefile.am @@ -69,7 +69,8 @@ dist_noinst_SCRIPTS = \ filter_strchr \ filter_varinfo3 \ filter_memcheck \ - filter_overlaperror + filter_overlaperror \ + filter_sized_delete noinst_HEADERS = leak.h @@ -267,6 +268,7 @@ EXTRA_DIST = \ sigkill.stderr.exp-glibc-2.28 sigkill.vgtest \ signal2.stderr.exp signal2.stdout.exp signal2.vgtest \ sigprocmask.stderr.exp sigprocmask.stderr.exp2 sigprocmask.vgtest \ + sized_delete.stderr.exp sized_delete.stderr.exp-x86 sized_delete.vgtest \ static_malloc.stderr.exp static_malloc.vgtest \ stpncpy.vgtest stpncpy.stderr.exp stpncpy.stdout.exp \ strchr.stderr.exp strchr.stderr.exp2 strchr.stderr.exp3 strchr.vgtest \ @@ -397,6 +399,7 @@ check_PROGRAMS = \ sendmsg \ sh-mem sh-mem-random \ sigaltstack signal2 sigprocmask static_malloc sigkill \ + sized_delete \ strchr \ str_tester \ supp_unknown supp1 supp2 suppfree \ @@ -549,6 +552,9 @@ sendmsg_CFLAGS += -D_XOPEN_SOURCE=600 sendmsg_LDADD = -lsocket -lnsl endif +sized_delete_SOURCES = sized_delete.cpp +sized_delete_CXXFLAGS = $(AM_CXXFLAGS) -fsized-deallocation + str_tester_CFLAGS = $(AM_CFLAGS) -Wno-shadow \ @FLAG_W_NO_MEMSET_TRANSPOSED_ARGS@ diff --git a/memcheck/tests/filter_sized_delete b/memcheck/tests/filter_sized_delete new file mode 100755 index 0000000000..54dea76b5d --- /dev/null +++ b/memcheck/tests/filter_sized_delete @@ -0,0 +1,4 @@ +#! /bin/sh + +./filter_stderr "$@" | +grep -v free | grep -v malloc diff --git a/memcheck/tests/sized_delete b/memcheck/tests/sized_delete new file mode 100755 index 0000000000..a9f716d73e Binary files /dev/null and b/memcheck/tests/sized_delete differ diff --git a/memcheck/tests/sized_delete.cpp b/memcheck/tests/sized_delete.cpp new file mode 100644 index 0000000000..24379d1a7e --- /dev/null +++ b/memcheck/tests/sized_delete.cpp @@ -0,0 +1,12 @@ +class MyClass { + int i; + +}; + +int main() { + MyClass* myClass = new MyClass(); + delete myClass; + MyClass* myClass5 = new MyClass[5]; + operator delete[](myClass5, 5U*sizeof(MyClass)); + //delete [] myClass5; +} diff --git a/memcheck/tests/sized_delete.stderr.exp b/memcheck/tests/sized_delete.stderr.exp new file mode 100644 index 0000000000..91bd71c388 --- /dev/null +++ b/memcheck/tests/sized_delete.stderr.exp @@ -0,0 +1,4 @@ +_Znwm(4) = 0x........ +_ZdlPvm(0x........) +_Znam(20) = 0x........ +_ZdaPvm(0x........) diff --git a/memcheck/tests/sized_delete.stderr.exp-x86 b/memcheck/tests/sized_delete.stderr.exp-x86 new file mode 100644 index 0000000000..1f6e9f9155 --- /dev/null +++ b/memcheck/tests/sized_delete.stderr.exp-x86 @@ -0,0 +1,4 @@ +_Znwj(4) = 0x........ +_ZdlPvj(0x........) +_Znaj(20) = 0x........ +_ZdaPvj(0x........) diff --git a/memcheck/tests/sized_delete.vgtest b/memcheck/tests/sized_delete.vgtest new file mode 100644 index 0000000000..9f483e01c4 --- /dev/null +++ b/memcheck/tests/sized_delete.vgtest @@ -0,0 +1,4 @@ +prog: sized_delete +prereq: test -e sized_delete +vgopts: -q "--trace-malloc=yes" --show-mismatched-frees=yes +stderr_filter: filter_sized_delete |
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From: Paul F. <pa...@so...> - 2020-11-09 08:33:54
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3aa3482774cf99ba23b7a6eac97d17cf143af5aa commit 3aa3482774cf99ba23b7a6eac97d17cf143af5aa Author: Paul Floyd <pj...@wa...> Date: Mon Nov 9 09:30:31 2020 +0100 Bug 424012 - fix crash if readv/writev have invalid but not NULL arg2 iovec pointer Diff: --- coregrind/m_syswrap/syswrap-generic.c | 7 +++---- memcheck/tests/writev1.c | 20 ++++++++++++++++++++ memcheck/tests/writev1.stderr.exp | 12 ++++++++++++ 3 files changed, 35 insertions(+), 4 deletions(-) diff --git a/coregrind/m_syswrap/syswrap-generic.c b/coregrind/m_syswrap/syswrap-generic.c index 864bda76c5..badb8c778d 100644 --- a/coregrind/m_syswrap/syswrap-generic.c +++ b/coregrind/m_syswrap/syswrap-generic.c @@ -4291,8 +4291,7 @@ PRE(sys_readv) if ((Int)ARG3 >= 0) PRE_MEM_READ( "readv(vector)", ARG2, ARG3 * sizeof(struct vki_iovec) ); - if (ARG2 != 0) { - /* ToDo: don't do any of the following if the vector is invalid */ + if (ML_(safe_to_deref)((const void*)ARG2, ARG3*sizeof(struct vki_iovec *))) { vec = (struct vki_iovec *)(Addr)ARG2; for (i = 0; i < (Int)ARG3; i++) PRE_MEM_WRITE( "readv(vector[...])", @@ -4644,8 +4643,8 @@ PRE(sys_writev) if ((Int)ARG3 >= 0) PRE_MEM_READ( "writev(vector)", ARG2, ARG3 * sizeof(struct vki_iovec) ); - if (ARG2 != 0) { - /* ToDo: don't do any of the following if the vector is invalid */ + + if (ML_(safe_to_deref)((const void*)ARG2, ARG3*sizeof(struct vki_iovec *))) { vec = (struct vki_iovec *)(Addr)ARG2; for (i = 0; i < (Int)ARG3; i++) PRE_MEM_READ( "writev(vector[...])", diff --git a/memcheck/tests/writev1.c b/memcheck/tests/writev1.c index 6a8c281c89..f537058e91 100644 --- a/memcheck/tests/writev1.c +++ b/memcheck/tests/writev1.c @@ -82,6 +82,26 @@ int main(void) else fprintf(stderr, "Error readv returned a positive value\n"); + // test with totally bogus iovec pointer + // see bugz 424012 + if (writev(fd, (const struct iovec *)1, 1) < 0) { + if (errno == EFAULT) + fprintf(stderr, "Received EFAULT as expected\n"); + else + fprintf(stderr, "Expected EFAULT, got %d\n", errno); + } + else + fprintf(stderr, "Error writev returned a positive value\n"); + + if (readv(fd, (const struct iovec *)1, 1) < 0) { + if (errno == EFAULT) + fprintf(stderr, "Received EFAULT as expected\n"); + else + fprintf(stderr, "Expected EFAULT, got %d\n", errno); + } + else + fprintf(stderr, "Error readv returned a positive value\n"); + unlink(f_name); return 0; diff --git a/memcheck/tests/writev1.stderr.exp b/memcheck/tests/writev1.stderr.exp index 0fe62eecb7..aea8390c74 100644 --- a/memcheck/tests/writev1.stderr.exp +++ b/memcheck/tests/writev1.stderr.exp @@ -7,3 +7,15 @@ Syscall param writev(vector[...]) points to unaddressable byte(s) Received EFAULT as expected Received EINVAL as expected Received EINVAL as expected +Syscall param writev(vector) points to unaddressable byte(s) + ... + by 0x........: main (writev1.c:87) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Received EFAULT as expected +Syscall param readv(vector) points to unaddressable byte(s) + ... + by 0x........: main (writev1.c:96) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Received EFAULT as expected |