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From: Carl L. <ca...@so...> - 2020-10-07 17:18:31
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ef76075436a539cc5e71e0113858f2b7849b9ffc commit ef76075436a539cc5e71e0113858f2b7849b9ffc Author: Carl Love <ce...@us...> Date: Tue Oct 6 11:57:00 2020 -0500 SIMD Permute-Class operations powerpc tests Diff: --- NEWS | 1 + none/tests/ppc64/test_isa_3_1_VRT.c | 146 + none/tests/ppc64/test_isa_3_1_VRT.stdout.exp | 5196 +++++++++++++++++++++++++- none/tests/ppc64/test_isa_3_1_XT.c | 266 ++ none/tests/ppc64/test_isa_3_1_XT.stdout.exp | 4520 +++++++++++++++++++++- 5 files changed, 10127 insertions(+), 2 deletions(-) diff --git a/NEWS b/NEWS index 780f2f3243..460eea232d 100644 --- a/NEWS +++ b/NEWS @@ -51,6 +51,7 @@ n-i-bz helgrind: If hg_cli__realloc fails, return NULL. 426144 Fix "condition variable has not been initialized" on Fedora 33. 423195 PPC ISA 3.1 support is missing, part 1 425232 PPC ISA 3.1 support is missing, part 2 +426123 PPC ISA 3.1 support is missing, part 3 Release 3.16.1 (?? June 2020) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/none/tests/ppc64/test_isa_3_1_VRT.c b/none/tests/ppc64/test_isa_3_1_VRT.c index 72025b9bf2..a72ea26263 100644 --- a/none/tests/ppc64/test_isa_3_1_VRT.c +++ b/none/tests/ppc64/test_isa_3_1_VRT.c @@ -117,6 +117,122 @@ static void test_vmodud (void) { __asm__ __volatile__ ("vmodud %0, %1, %2" : "=v" (vrt) : "v" (vra), "v" (vrb) ); } +static void test_vextdubvlx (void) { + __asm__ __volatile__ ("vextdubvlx %0, %1, %2, %3" + : "=v" (vrt) : "v" (vra), "v" (vrb), "r" (rc) ); +} +static void test_vextdubvrx (void) { + __asm__ __volatile__ ("vextdubvrx %0, %1, %2, %3" + : "=v" (vrt) : "v" (vra), "v" (vrb), "r" (rc) ); +} +static void test_vextduhvlx (void) { + __asm__ __volatile__ ("vextduhvlx %0, %1, %2, %3" + : "=v" (vrt) : "v" (vra), "v" (vrb), "r" (rc) ); +} +static void test_vextduhvrx (void) { + __asm__ __volatile__ ("vextduhvrx %0, %1, %2, %3" + : "=v" (vrt) : "v" (vra), "v" (vrb), "r" (rc) ); +} +static void test_vextduwvlx (void) { + __asm__ __volatile__ ("vextduwvlx %0, %1, %2, %3" + : "=v" (vrt) : "v" (vra), "v" (vrb), "r" (rc) ); +} +static void test_vextduwvrx (void) { + __asm__ __volatile__ ("vextduwvrx %0, %1, %2, %3" + : "=v" (vrt) : "v" (vra), "v" (vrb), "r" (rc) ); +} +static void test_vextddvlx (void) { + __asm__ __volatile__ ("vextddvlx %0, %1, %2, %3" + : "=v" (vrt) : "v" (vra), "v" (vrb), "r" (rc) ); +} +static void test_vextddvrx (void) { + __asm__ __volatile__ ("vextddvrx %0, %1, %2, %3" + : "=v" (vrt) : "v" (vra), "v" (vrb), "r" (rc) ); +} +static void test_vinsblx (void) { + __asm__ __volatile__ ("vinsblx %0, %1, %2" + : "+v" (vrt) : "r" (ra), "r" (rb) ); +} +static void test_vinsbrx (void) { + __asm__ __volatile__ ("vinsbrx %0, %1, %2" + : "+v" (vrt) : "r" (ra), "r" (rb) ); +} +static void test_vinshlx (void) { + __asm__ __volatile__ ("vinshlx %0, %1, %2" + : "+v" (vrt) : "r" (ra), "r" (rb) ); +} +static void test_vinshrx (void) { + __asm__ __volatile__ ("vinshrx %0, %1, %2" + : "+v" (vrt) : "r" (ra), "r" (rb) ); +} +static void test_vinswlx (void) { + __asm__ __volatile__ ("vinswlx %0, %1, %2" + : "+v" (vrt) : "r" (ra), "r" (rb) ); +} +static void test_vinswrx (void) { + __asm__ __volatile__ ("vinswrx %0, %1, %2" + : "+v" (vrt) : "r" (ra), "r" (rb) ); +} +static void test_vinsdlx (void) { + __asm__ __volatile__ ("vinsdlx %0, %1, %2" + : "+v" (vrt) : "r" (ra), "r" (rb) ); +} +static void test_vinsdrx (void) { + __asm__ __volatile__ ("vinsdrx %0, %1, %2" + : "+v" (vrt) : "r" (ra), "r" (rb) ); +} +static void test_vinsbvlx (void) { + __asm__ __volatile__ ("vinsbvlx %0, %1, %2" + : "+v" (vrt) : "r" (ra), "v" (vrb) ); +} +static void test_vinshvlx (void) { + __asm__ __volatile__ ("vinshvlx %0, %1, %2" + : "+v" (vrt) : "r" (ra), "v" (vrb) ); +} +static void test_vinsbvrx (void) { + __asm__ __volatile__ ("vinsbvrx %0, %1, %2" + : "+v" (vrt) : "r" (ra), "v" (vrb) ); +} +static void test_vinshvrx (void) { + __asm__ __volatile__ ("vinshvrx %0, %1, %2" + : "+v" (vrt) : "r" (ra), "v" (vrb) ); +} +static void test_vinswvlx (void) { + __asm__ __volatile__ ("vinswvlx %0, %1, %2" + : "+v" (vrt) : "r" (ra), "v" (vrb) ); +} +static void test_vinswvrx (void) { + __asm__ __volatile__ ("vinswvrx %0, %1, %2" + : "+v" (vrt) : "r" (ra), "v" (vrb) ); +} +static void test_vinsw_3 (void) { + __asm__ __volatile__ ("vinsw %0, %1, 3" : "+v" (vrt) : "r" (rb) ); +} +static void test_vinsw_7 (void) { + __asm__ __volatile__ ("vinsw %0, %1, 7" : "+v" (vrt) : "r" (rb) ); +} +static void test_vinsd_3 (void) { + __asm__ __volatile__ ("vinsd %0, %1, 3" : "+v" (vrt) : "r" (rb) ); +} +static void test_vinsd_7 (void) { + __asm__ __volatile__ ("vinsd %0, %1, 7" : "+v" (vrt) : "r" (rb) ); +} +static void test_vsldbi_0 (void) { + __asm__ __volatile__ ("vsldbi %0, %1, %2, 0" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vsldbi_4 (void) { + __asm__ __volatile__ ("vsldbi %0, %1, %2, 4" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vsrdbi_0 (void) { + __asm__ __volatile__ ("vsrdbi %0, %1, %2, 0" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vsrdbi_4 (void) { + __asm__ __volatile__ ("vsrdbi %0, %1, %2, 4" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} static test_list_t testgroup_generic[] = { { &test_vdivesd, "vdivesd", "VRT,VRA,VRB"}, /* bcs */ @@ -127,6 +243,32 @@ static test_list_t testgroup_generic[] = { { &test_vdivsw, "vdivsw", "VRT,VRA,VRB"}, /* bcs */ { &test_vdivud, "vdivud", "VRT,VRA,VRB"}, /* bcs */ { &test_vdivuw, "vdivuw", "VRT,VRA,VRB"}, /* bcs */ + { &test_vextddvlx, "vextddvlx", "VRT,VRA,VRB,RC"}, /* bcs */ + { &test_vextddvrx, "vextddvrx", "VRT,VRA,VRB,RC"}, /* bcs */ + { &test_vextdubvlx, "vextdubvlx", "VRT,VRA,VRB,RC"}, /* bcs */ + { &test_vextdubvrx, "vextdubvrx", "VRT,VRA,VRB,RC"}, /* bcs */ + { &test_vextduhvlx, "vextduhvlx", "VRT,VRA,VRB,RC"}, /* bcs */ + { &test_vextduhvrx, "vextduhvrx", "VRT,VRA,VRB,RC"}, /* bcs */ + { &test_vextduwvlx, "vextduwvlx", "VRT,VRA,VRB,RC"}, /* bcs */ + { &test_vextduwvrx, "vextduwvrx", "VRT,VRA,VRB,RC"}, /* bcs */ + { &test_vinsblx, "vinsblx", "VRT,RA,RB"}, /* bcs */ + { &test_vinsbrx, "vinsbrx", "VRT,RA,RB"}, /* bcs */ + { &test_vinsbvlx, "vinsbvlx", "VRT,RA,VRB"}, /* bcs */ + { &test_vinsbvrx, "vinsbvrx", "VRT,RA,VRB"}, /* bcs */ + { &test_vinsdlx, "vinsdlx", "VRT,RA,RB"}, /* bcs */ + { &test_vinsdrx, "vinsdrx", "VRT,RA,RB"}, /* bcs */ + { &test_vinsd_3, "vinsd 3", "VRT,RB,UIM"}, /* bcwp */ + { &test_vinsd_7, "vinsd 7", "VRT,RB,UIM"}, /* bcwp */ + { &test_vinshlx, "vinshlx", "VRT,RA,RB"}, /* bcs */ + { &test_vinshrx, "vinshrx", "VRT,RA,RB"}, /* bcs */ + { &test_vinshvlx, "vinshvlx", "VRT,RA,VRB"}, /* bcs */ + { &test_vinshvrx, "vinshvrx", "VRT,RA,VRB"}, /* bcs */ + { &test_vinswlx, "vinswlx", "VRT,RA,RB"}, /* bcs */ + { &test_vinswrx, "vinswrx", "VRT,RA,RB"}, /* bcs */ + { &test_vinswvlx, "vinswvlx", "VRT,RA,VRB"}, /* bcs */ + { &test_vinswvrx, "vinswvrx", "VRT,RA,VRB"}, /* bcs */ + { &test_vinsw_3, "vinsw 3", "VRT,RB,UIM"}, /* bcwp */ + { &test_vinsw_7, "vinsw 7", "VRT,RB,UIM"}, /* bcwp */ { &test_vmodsd, "vmodsd", "VRT,VRA,VRB"}, /* bcs */ { &test_vmodsw, "vmodsw", "VRT,VRA,VRB"}, /* bcs */ { &test_vmodud, "vmodud", "VRT,VRA,VRB"}, /* bcs */ @@ -136,6 +278,10 @@ static test_list_t testgroup_generic[] = { { &test_vmulhud, "vmulhud", "VRT,VRA,VRB"}, /* bcs */ { &test_vmulhuw, "vmulhuw", "VRT,VRA,VRB"}, /* bcs */ { &test_vmulld, "vmulld", "VRT,VRA,VRB"}, /* bcs */ + { &test_vsldbi_0, "vsldbi 0", "VRT,VRA,VRB,SH"}, /* bcwp */ + { &test_vsldbi_4, "vsldbi 4", "VRT,VRA,VRB,SH"}, /* bcwp */ + { &test_vsrdbi_0, "vsrdbi 0", "VRT,VRA,VRB,SH"}, /* bcwp */ + { &test_vsrdbi_4, "vsrdbi 4", "VRT,VRA,VRB,SH"}, /* bcwp */ { NULL, NULL }, }; diff --git a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp index 5b35d4f9ba..5b2e41b01d 100644 --- a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp +++ b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp @@ -566,6 +566,4520 @@ vdivuw 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => vdivuw 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => aa00000054,000000fe00000001 vdivuw 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => eed3000000000,00000054000000aa +vextddvlx 0 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => ff8000007f800000,0000000000000000 +vextddvlx 4 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 7f8000007f800000,0000000000000000 +vextddvlx 8 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 7f800000ff800000,0000000000000000 +vextddvlx 0 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => ff8000007f800000,0000000000000000 +vextddvlx 4 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 7f8000007f800000,0000000000000000 +vextddvlx 8 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 7f800000ff800000,0000000000000000 +vextddvlx 0 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => ff8000007f800000,0000000000000000 +vextddvlx 4 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 7f8000007f800000,0000000000000000 +vextddvlx 8 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 7f800000ff800000,0000000000000000 +vextddvlx 0 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => ff8000007f800000,0000000000000000 +vextddvlx 4 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 7f8000007f800000,0000000000000000 +vextddvlx 8 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 7f800000ff800000,0000000000000000 +vextddvlx 0 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => ff8000007f800000,0000000000000000 +vextddvlx 4 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => 7f8000007f800000,0000000000000000 +vextddvlx 8 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => 7f800000ff800000,0000000000000000 +vextddvlx 0 7f800000ff800000,ff8000007f800000 0000111e8000222e,7ff0000000000000 => ff8000007f800000,0000000000000000 +vextddvlx 4 7f800000ff800000,ff8000007f800000 0000111e8000222e,7ff0000000000000 => 7f8000007f800000,0000000000000000 +vextddvlx 8 7f800000ff800000,ff8000007f800000 0000111e8000222e,7ff0000000000000 => 7f800000ff800000,0000000000000000 +vextddvlx 0 7f800000ff800000,ff8000007f800000 7ff0000000000000,fff0000000000000 => ff8000007f800000,0000000000000000 +vextddvlx 4 7f800000ff800000,ff8000007f800000 7ff0000000000000,fff0000000000000 => 7f8000007f800000,0000000000000000 +vextddvlx 8 7f800000ff800000,ff8000007f800000 7ff0000000000000,fff0000000000000 => 7f800000ff800000,0000000000000000 +vextddvlx 0 7f800000ff800000,ff8000007f800000 fff0000000000000,2208400000000000 => ff8000007f800000,0000000000000000 +vextddvlx 4 7f800000ff800000,ff8000007f800000 fff0000000000000,2208400000000000 => 7f8000007f800000,0000000000000000 +vextddvlx 8 7f800000ff800000,ff8000007f800000 fff0000000000000,2208400000000000 => 7f800000ff800000,0000000000000000 +vextddvlx 0 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => ff8000007f800000,0000000000000000 +vextddvlx 4 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => 7f8000007f800000,0000000000000000 +vextddvlx 8 7f800000ff800000,ff8000007f800000 2208400000000000,0000000000000009 => 7f800000ff800000,0000000000000000 +vextddvlx 0 7f800000ff800000,ff8000007f800000 0000000000000009,ffff000180000001 => ff8000007f800000,0000000000000000 +vextddvlx 4 7f800000ff800000,ff8000007f800000 0000000000000009,ffff000180000001 => 7f8000007f800000,0000000000000000 +vextddvlx 8 7f800000ff800000,ff8000007f800000 0000000000000009,ffff000180000001 => 7f800000ff800000,0000000000000000 +vextddvlx 0 7f800000ff800000,ff8000007f800000 ffff000180000001,0000000000000000 => ff8000007f800000,0000000000000000 +vextddvlx 4 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ffff000180000001,0000000000000000 0000000000000009,ffff000180000001 => ffff0001,0000000000000000 +vextddvlx 8 ffff000180000001,0000000000000000 0000000000000009,ffff000180000001 => ffff000180000001,0000000000000000 +vextddvlx 0 ffff000180000001,0000000000000000 ffff000180000001,0000000000000000 => 0,0000000000000000 +vextddvlx 4 ffff000180000001,0000000000000000 ffff000180000001,0000000000000000 => ffff0001,0000000000000000 +vextddvlx 8 ffff000180000001,0000000000000000 ffff000180000001,0000000000000000 => ffff000180000001,0000000000000000 +vextddvlx 0 ffff000180000001,0000000000000000 0000000000000000,8000000000000000 => 0,0000000000000000 +vextddvlx 4 ffff000180000001,0000000000000000 0000000000000000,8000000000000000 => ffff0001,0000000000000000 +vextddvlx 8 ffff000180000001,0000000000000000 0000000000000000,8000000000000000 => ffff000180000001,0000000000000000 +vextddvlx 0 ffff000180000001,0000000000000000 8000000000000000,7f800000ff800000 => 0,0000000000000000 +vextddvlx 4 ffff000180000001,0000000000000000 8000000000000000,7f800000ff800000 => ffff0001,0000000000000000 +vextddvlx 8 ffff000180000001,0000000000000000 8000000000000000,7f800000ff800000 => ffff000180000001,0000000000000000 +vextddvlx 0 0000000000000000,8000000000000000 7f800000ff800000,ff8000007f800000 => 8000000000000000,0000000000000000 +vextddvlx 4 0000000000000000,8000000000000000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vextddvlx 8 0000000000000000,8000000000000000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vextddvlx 0 0000000000000000,8000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 8000000000000000,0000000000000000 +vextddvlx 4 0000000000000000,8000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vextddvlx 8 0000000000000000,8000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vextddvlx 0 0000000000000000,8000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 8000000000000000,0000000000000000 +vextddvlx 4 0000000000000000,8000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vextddvlx 8 0000000000000000,8000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vextddvlx 0 0000000000000000,8000000000000000 0080000e8080000e,0180055e0180077e => 8000000000000000,0000000000000000 +vextddvlx 4 0000000000000000,8000000000000000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vextddvlx 8 0000000000000000,8000000000000000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vextddvlx 0 0000000000000000,8000000000000000 0180055e0180077e,0000111e8000222e => 8000000000000000,0000000000000000 +vextddvlx 4 0000000000000000,8000000000000000 0180055e0180077e,0000111e8000222e =>... [truncated message content] |
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From: Carl L. <ca...@so...> - 2020-10-07 17:18:17
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=349102dcc790ac2adc88a6b23ee6b371187a2cf0 commit 349102dcc790ac2adc88a6b23ee6b371187a2cf0 Author: Carl Love <ce...@us...> Date: Wed May 13 15:29:51 2020 -0500 ISA 3.1 SIMD Permute-Class Operations Add support for: vxvkq Load VSX Vector Special Value Quadword vextddvlx Vector Extract Double Dword to VSR Left-Indexed vextddvrx Vector Extract Double Dword to VSR Right-Indexed vextdubvlx Vector Extract Double Unsigned Byte to VR Left-Indexed vextdubvrx Vector Extract Double Unsigned Byte to VR Right-Indexed vextduhvlx Vector Extract Double Unsigned Hword to VR Left-Indexed vextduhvrx Vector Extract Double Unsigned Hword to VR Right-Indexed vextduwvlx Vector Extract Double Unsigned Word to VR Left-Indexed vextduwvrx Vector Extract Double Unsigned Word to VR Right-Indexed vinsblx Vector Insert Byte from GPR Left-Indexed vinsbrx Vector Insert Byte from GPR Right-Indexed vinsbvlx Vector Insert Byte from VSR Left-Indexed vinsbvrx Vector Insert Byte from VSR Right-Indexed vinsd Vector Insert Dword from GPR vinsdlx Vector Insert Dword from GPR Left-Indexed vinsdrx Vector Insert Dword from GPR Right-Indexed vinshlx Vector Insert Hword from GPR Left-Indexed vinshrx Vector Insert Hword from GPR Right-Indexed vinshvlx Vector Insert Hword from VSR Left-Indexed vinshvrx Vector Insert Hword from VSR Right-Indexed vinsw Vector Insert Word from GPR vinswlx Vector Insert Word from GPR Left-Indexed vinswrx Vector Insert Word from GPR Right-Indexed vinswvlx Vector Insert Word from VSR Left-Indexed vinswvrx Vector Insert Word from VSR Right-Indexed vsldbi Vector Shift Left Double by Bit Immediate vsrdbi Vector Shift Right Double by Bit Immediate xxblendvb VSX Vector Blend Variable Byte xxblendvd VSX Vector Blend Variable Dword xxblendvh VSX Vector Blend Variable Hword xxblendvw VSX Vector Blend Variable Word xxpermx VSX Vector Permute Extended xxsplti32dx VSX Vector Splat Immediate32 Dword Indexed xxspltidp VSX Vector Splat Immediate DP xxspltiw VSX Vector Splat Immediate Word Diff: --- VEX/priv/guest_ppc_toIR.c | 1427 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 1379 insertions(+), 48 deletions(-) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 5d139d0741..602831e91a 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -1005,6 +1005,91 @@ static IRExpr* extract_field_from_vector( IRTemp vB, IRExpr* index, UInt mask) mkU64( mask ) ) ) ); } +static IRExpr* insert_field_into_vector( IRTemp vSrc, IRExpr* index, + IRExpr* bits, IRExpr* mask) +{ + /* vSrc is a vector v128, index is I64 between 0 and 15 bytes, bits is I64, + mask is I64. Indexing is based on the least significant byte being + index 0. Insert bits starting at index to size of mask */ + IRTemp shift = newTemp(Ity_I8); + IRTemp tmp_mask = newTemp(Ity_V128); + IRTemp tmp_not_mask = newTemp(Ity_V128); + UInt index_mask = 0xF; //Index is only 4-bits wide + + assign( shift, unop( Iop_64to8, + binop( Iop_Mul64, + binop( Iop_And64, + index, + mkU64( index_mask ) ), + mkU64( 8 ) ) ) ); + assign( tmp_mask, binop( Iop_ShlV128, + binop( Iop_64HLtoV128, + mkU64( 0x0 ), + mask ), + mkexpr( shift) ) ); + assign( tmp_not_mask, unop( Iop_NotV128, mkexpr( tmp_mask ) ) ); + return binop( Iop_OrV128, + binop( Iop_AndV128, + mkexpr( vSrc ), + mkexpr( tmp_not_mask ) ), + binop( Iop_AndV128, + binop( Iop_ShlV128, + binop( Iop_64HLtoV128, + mkU64( 0x0 ), + bits ), + mkexpr( shift) ), + mkexpr( tmp_mask ) ) ); +} + +static IRExpr* extractBytefromV256( IRTemp vA, IRTemp vB, UInt byte_index) +{ + UInt byte_mask = 0xFF; + UInt byte_size = 8; // size in bits + IRTemp shift = newTemp(Ity_I8); + IRTemp select_tmp = newTemp(Ity_I64); + IRTemp reg_select = newTemp(Ity_V128); + IRTemp src_tmp = newTemp(Ity_V128); + + /* The byte numbering is right to left: byte_n-1, byte_n-2, ...., byte0. + The byte-index is between 0 and 31. */ + assign( shift, unop( Iop_64to8, + binop( Iop_Mul64, + binop( Iop_And64, + mkU64( 0xF ), + mkexpr( byte_index ) ), + mkU64( byte_size ) ) ) ); + + /* Create mask to select byte from srcA if byte_index > 16 or + from srcB. Use byte_index[4] to select srcA or srcB. */ + assign( select_tmp, unop( Iop_1Sto64, + unop( Iop_64to1, + binop( Iop_Shr64, + mkexpr( byte_index ), + mkU8( 4 ) ) ) ) ); + + assign( reg_select, binop( Iop_64HLtoV128, + mkexpr( select_tmp ), + mkexpr( select_tmp ) ) ); + + assign( src_tmp, + binop( Iop_OrV128, + binop( Iop_AndV128, + mkexpr( reg_select ), + binop( Iop_ShrV128, + mkexpr( vA ), + mkexpr( shift ) ) ), + binop( Iop_AndV128, + unop( Iop_NotV128, mkexpr( reg_select ) ), + binop( Iop_ShrV128, + mkexpr( vB ), + mkexpr( shift ) ) ) ) ); + + /* Mask off element */ + return binop( Iop_And64, + unop( Iop_V128to64, mkexpr( src_tmp ) ), + mkU64( byte_mask ) ); +} + /* Signed saturating narrow 64S to 32 */ static IRExpr* mkQNarrow64Sto32 ( IRExpr* t64 ) { @@ -3131,6 +3216,20 @@ static UChar PrefixType( UInt instr ) { return toUChar( IFIELD( instr, 24, 2 ) ); } +/* Extract XT 8RR D-form (destination register) field, instr[38:42] | [47] */ +static UChar ifieldRegXT_8RR_D ( UInt instr ) +{ + UChar TX = toUChar (IFIELD (instr, (63 - 47), 1)); + UChar T = toUChar (IFIELD (instr, (63 - 42), 4)); + return (TX << 5) | T; +} + +/* Extract immediate 8RR D-form prefix[16:31] or inst[48:63] */ +static UInt ifield_imm_8RR_D ( UInt instr ) +{ + return IFIELD( instr, 0, 16 ); +} + static UChar ifieldR( UInt instr ) { return toUChar( IFIELD( instr, 20, 1 ) ); } @@ -3211,6 +3310,27 @@ static IRExpr* calculate_prefix_EA ( UInt prefix, UInt suffixInstr, mkU64( guest_CIA_curr_instr ) ); } +/* Extract prefix intruction register fields 8RR:XX4-form */ +static UChar ifieldRegXT_8RR_XX4 ( UInt instr ) { + return toUChar( ( IFIELD( instr, (63-63), 1) << 5) + | ( IFIELD( instr, (63-42), 5 ) ) ); // instr[38:42] | [63] +} + +static UChar ifieldRegXA_8RR_XX4 ( UInt instr ) { + return toUChar( ( IFIELD( instr, (63-61), 1) << 5) + | ( IFIELD( instr, (63-47), 5 ) ) ); // instr[43:47] | [61] +} + +static UChar ifieldRegXB_8RR_XX4 ( UInt instr ) { + return toUChar( ( IFIELD( instr, (63-62), 1) << 5) + | ( IFIELD( instr, (63-52), 5 ) ) ); // instr[48:52] | [62] +} + +static UChar ifieldRegXC_8RR_XX4 ( UInt instr ) { + return toUChar( ( IFIELD( instr, (63-60), 1) << 5) + | ( IFIELD( instr, (63-57), 5 ) ) ); // instr[53:57] | [60] +} + /*------------------------------------------------------------*/ /*--- Read/write to guest-state --- */ /*------------------------------------------------------------*/ @@ -5157,6 +5277,8 @@ static IRExpr * UNSIGNED_CMP_GT_V128 ( IRExpr *vA, IRExpr *vB ) { /*--- FP Helpers ---*/ /*------------------------------------------------------------*/ +static IRExpr* /* :: Ity_I32 */ get_IR_roundingmode ( void ); // prototype + /* Produce the 32-bit pattern corresponding to the supplied float. */ static UInt float_to_bits ( Float f ) @@ -8177,6 +8299,361 @@ static Bool dis_int_load ( UInt prefix, UInt theInstr ) return True; } +/* + VSX Vector Splat Immediate Word 8RR:D-form +*/ +static Bool dis_vector_splat_imm_prefix ( UInt prefix, UInt theInstr ) +{ + UChar opc1 = ifieldOPC(theInstr); + UChar opc2 = IFIELD(theInstr, (31-(46-32)), 4); // bits[43:46] + + UInt imm0 = ifield_imm_8RR_D(prefix); + UInt imm1 = ifield_imm_8RR_D(theInstr); + UInt IMM32 = (imm0 << 16) | imm1; + + UInt XT_addr = ifieldRegXT_8RR_D(theInstr); + + if (opc1 != 0x20) return False; + + /* These are prefix instructions, no equivalent word instruction. */ + switch(opc2) { + case 0x0: + case 0x1: + { + /* VSX Vector Splat Immediate32 Doubleword Indexed 8RR:D-form */ + UInt IX = IFIELD(theInstr, (31-(46-32)), 1); // bit[46] + IRTemp tmp = newTemp(Ity_V128); + IRTemp mask = newTemp(Ity_V128); + IRTemp new_elements = newTemp(Ity_V128); + + DIP("xxsplti32dx %u,%u,%u\n", XT_addr, IX, IMM32); + + assign( tmp, getVSReg( XT_addr ) ); + + if (IX == 0) { + assign( mask, binop( Iop_64HLtoV128, + binop( Iop_32HLto64, + mkU32( 0 ), mkU32( 0xFFFFFFFF ) ), + binop( Iop_32HLto64, + mkU32( 0 ), mkU32( 0xFFFFFFFF ) ) ) ); + assign( new_elements, binop( Iop_64HLtoV128, + binop( Iop_32HLto64, + mkU32( IMM32 ), mkU32( 0 ) ), + binop( Iop_32HLto64, + mkU32( IMM32 ), mkU32( 0 ) ) ) ); + } else { + assign( mask, binop( Iop_64HLtoV128, + binop( Iop_32HLto64, + mkU32( 0xFFFFFFFF ), mkU32( 0 ) ), + binop( Iop_32HLto64, + mkU32( 0xFFFFFFFF ), mkU32( 0 ) ) ) ); + assign( new_elements, binop( Iop_64HLtoV128, + binop( Iop_32HLto64, + mkU32( 0 ), mkU32( IMM32 ) ), + binop( Iop_32HLto64, + mkU32( 0 ), mkU32( IMM32 ) ) ) ); + } + + putVSReg( XT_addr, + binop( Iop_OrV128, + binop( Iop_AndV128, mkexpr( tmp ), mkexpr( mask) ), + mkexpr( new_elements ) ) ); + break; + } + case 0x2: + { + IRTemp result = newTemp(Ity_I64); + + /* VSX Vector Splat Immediate Double-precision 8RR:D-form */ + DIP("xxspltidp %u,%u\n", XT_addr, IMM32); + + assign( result, + unop( Iop_ReinterpF64asI64, + unop( Iop_F32toF64, + unop( Iop_ReinterpI32asF32, + mkU32( IMM32 ) ) ) ) ); + putVSReg( XT_addr, binop( Iop_64HLtoV128, + mkexpr( result ), mkexpr( result ) ) ); + } + break; + + case 0x3: + /* VSX Vector Splat Immediate Word 8RR:D-form */ + DIP("xxspltiw %u,%u\n", XT_addr, IMM32); + + putVSReg( XT_addr, + binop( Iop_64HLtoV128, + binop( Iop_32HLto64, + mkU32( IMM32 ), mkU32( IMM32 ) ), + binop( Iop_32HLto64, + mkU32( IMM32 ), mkU32( IMM32 ) ) ) ); + break; + default: + vex_printf("dis_vector_splat_imm_prefix (opc2)\n"); + return False; + } + + return True; +} + + /* + VSX Vector Permute Extended 8RR:D-form + */ +static Bool dis_vector_permute_prefix ( UInt prefix, UInt theInstr ) +{ + #define MAX_ELE 16 + UChar opc1 = ifieldOPC(theInstr); + UChar opc2 = IFIELD(theInstr, (63-59), 2); // bits[58:59] + UChar rXT_addr = ifieldRegXT_8RR_XX4( theInstr ); + UChar rXA_addr = ifieldRegXA_8RR_XX4( theInstr ); + UChar rXB_addr = ifieldRegXB_8RR_XX4( theInstr ); + UChar rXC_addr = ifieldRegXC_8RR_XX4( theInstr ); + UInt UIM = IFIELD(prefix, 0, 3); // bit [29:31] of the prefix + + Int i; + IRTemp rXA = newTemp(Ity_V128); + IRTemp rXB = newTemp(Ity_V128); + IRTemp rXC = newTemp(Ity_V128); + IRTemp cmp_mask = newTemp(Ity_I64); + IRTemp eidx_mask = newTemp(Ity_I64); + IRTemp result[MAX_ELE+1]; + IRTemp result_mask[MAX_ELE]; + IRTemp byte[MAX_ELE]; + IRTemp eidx[MAX_ELE]; + + /* These are prefix instructions, no equivalent word instruction. */ + if ((opc1 != 0x22) && (opc2 != 0)) return False; + + DIP("xxpermx v%u,v%u,v%u,v%u,%u\n", + rXT_addr, rXA_addr, rXB_addr, rXC_addr, UIM); + + assign( rXA, getVSReg( rXA_addr ) ); + assign( rXB, getVSReg( rXB_addr ) ); + assign( rXC, getVSReg( rXC_addr ) ); + + result[MAX_ELE] = newTemp(Ity_V128); + assign( eidx_mask, mkU64( 0x1F ) ); + assign( cmp_mask, mkU64( 0x7 ) ); + assign( result[MAX_ELE], binop( Iop_64HLtoV128, mkU64( 0 ), mkU64( 0 ) ) ); + + for (i = MAX_ELE-1; i >= 0; i--) { + + eidx[i] = newTemp( Ity_I64 ); + byte[i] = newTemp( Ity_I64 ); + result[i] = newTemp( Ity_V128 ); + result_mask[i] = newTemp( Ity_I64 ); + + /* the eidx is left based, make index right based for + extractBytefromV256(). */ + if ( i >= 8) { + assign( eidx[i], + binop( Iop_Sub64, + mkU64( 31 ), + binop( Iop_And64, + mkexpr( eidx_mask ), + binop( Iop_Shr64, + unop( Iop_V128HIto64, mkexpr( rXC ) ), + mkU8( (i - 8)*8 ) ) ) ) ); + assign( result_mask[i], + unop( Iop_1Sto64, + binop( Iop_CmpEQ64, + mkU64( UIM ), + binop( Iop_And64, + mkexpr ( cmp_mask ), + binop( Iop_Shr64, // bits 0:2 of ith byte + unop( Iop_V128HIto64, + mkexpr( rXC ) ), + mkU8( (i - 8)*8 + 5 ) ) ) ) ) ); + } else { + assign( eidx[i], + binop( Iop_Sub64, + mkU64( 31 ), + binop( Iop_And64, + mkexpr( eidx_mask ), + binop( Iop_Shr64, + unop( Iop_V128to64, mkexpr( rXC ) ), + mkU8( i*8 ) ) ) ) ); + assign( result_mask[i], + unop( Iop_1Sto64, + binop( Iop_CmpEQ64, + mkU64( UIM ), + binop( Iop_And64, + mkexpr ( cmp_mask ), + binop( Iop_Shr64, // bits 0:2 of ith byte + unop( Iop_V128to64, + mkexpr( rXC ) ), + mkU8( i*8 + 5 ) ) ) ) ) ); + } + + assign( byte[i], + binop( Iop_And64, + mkexpr( result_mask[i] ), + extractBytefromV256( rXA, rXB, eidx[i] ) ) ); + + assign( result[i], insert_field_into_vector( result[i+1], mkU64( i ), + mkexpr( byte[i] ), + mkU64( 0xFF ) ) ); + } + putVSReg( rXT_addr, mkexpr( result[0] ) ); + + return True; +#undef MAX_ELE +} + +/* + VSX Vector Splat Immediate Word 8RR:D-form +*/ +static Bool dis_vector_blend_prefix ( UInt prefix, UInt theInstr ) +{ + UChar opc1 = ifieldOPC(theInstr); + UChar opc2 = IFIELD(theInstr, (63-59), 2); // bits[58:59] + UChar rXT_addr = ifieldRegXT_8RR_XX4( theInstr ); + UChar rXA_addr = ifieldRegXA_8RR_XX4( theInstr ); + UChar rXB_addr = ifieldRegXB_8RR_XX4( theInstr ); + UChar rXC_addr = ifieldRegXC_8RR_XX4( theInstr ); + + IRTemp rXA = newTemp(Ity_V128); + IRTemp rXB = newTemp(Ity_V128); + IRTemp rXC = newTemp(Ity_V128); + IRTemp bit_mask = newTemp(Ity_V128); + IRTemp mask_gen = newTemp(Ity_V128); + IRTemp mask = newTemp(Ity_V128); + + /* These are prefix instructions, no equivalent word instruction. */ + if (opc1 != 0x21) return False; + + /* Generate the mask to select the elements from rXA or rXB. Use a vector + multiply to generate the mask to select the elments. Take the selctor + bit for the element (rXC & bit_mask) and multiply it by all 1's + (mask_gen). If the selector bit was 0, then we get zero bits for that + element entry, otherwise we get 1's. + + Unfortunately, we don't have an integer vector multipy have to do it as + an even and odd multiply for byt, halfword and word elements. Note, the + MK_Iop_MullOddXUxY shifts the operands right and uses the MullEven + operator, so we have to move the result back to its correct lane + position. */ + + assign( rXA, getVSReg( rXA_addr ) ); + assign( rXB, getVSReg( rXB_addr ) ); + assign( rXC, getVSReg( rXC_addr ) ); + + assign( mask_gen, + binop( Iop_64HLtoV128, + mkU64( 0xFFFFFFFFFFFFFFFFULL), + mkU64( 0xFFFFFFFFFFFFFFFFULL) ) ); + + switch(opc2) { + case 0: + /* VSX Vector Blend Variable Byte 8RR:XX4-Form */ + DIP("xxblendvb v%u,v%u,v%u,v%u\n", + rXT_addr, rXA_addr, rXB_addr, rXC_addr); + + assign( bit_mask, + binop( Iop_ShrV128, + binop( Iop_AndV128, + mkexpr( rXC ), + binop( Iop_64HLtoV128, + mkU64( 0x8080808080808080ULL ), + mkU64( 0x8080808080808080ULL ) ) ), + mkU8 ( 7 ) ) ); + assign( mask, + binop( Iop_OrV128, + binop( Iop_MullEven8Ux16, + mkexpr( mask_gen ), + mkexpr( bit_mask ) ), + binop( Iop_ShlV128, + MK_Iop_MullOdd8Ux16( + mkexpr( mask_gen ), + mkexpr( bit_mask ) ), + mkU8( 8 ) ) ) ); + break; + + case 1: + /* VSX Vector Blend Variable Halfword 8RR:XX4-Form */ + DIP("xxblendvh v%u,v%u,v%u,v%u\n", + rXT_addr, rXA_addr, rXB_addr, rXC_addr); + + assign( bit_mask, + binop( Iop_ShrV128, + binop( Iop_AndV128, + mkexpr( rXC ), + binop( Iop_64HLtoV128, + mkU64( 0x8000800080008000ULL ), + mkU64( 0x8000800080008000ULL ) ) ), + mkU8 ( 15 ) ) ); + assign( mask, + binop( Iop_OrV128, + binop( Iop_MullEven16Ux8, + mkexpr( mask_gen ), + mkexpr( bit_mask ) ), + binop( Iop_ShlV128, + MK_Iop_MullOdd16Ux8( + mkexpr( mask_gen ), + mkexpr( bit_mask ) ), + mkU8( 16 ) ) ) ); + break; + + case 2: + /* VSX Vector Blend Variable Word 8RR:XX4-Form */ + DIP("xxblendvw v%u,v%u,v%u,v%u\n", + rXT_addr, rXA_addr, rXB_addr, rXC_addr); + + assign( bit_mask, + binop( Iop_ShrV128, + binop( Iop_AndV128, + mkexpr( rXC ), + binop( Iop_64HLtoV128, + mkU64( 0x8000000080000000ULL ), + mkU64( 0x8000000080000000ULL ) ) ), + mkU8 ( 31 ) ) ); + assign( mask, + binop( Iop_OrV128, + binop( Iop_MullEven32Ux4, + mkexpr( mask_gen ), + mkexpr( bit_mask ) ), + binop( Iop_ShlV128, + MK_Iop_MullOdd32Ux4( + mkexpr( mask_gen ), + mkexpr( bit_mask ) ), + mkU8( 32 ) ) ) ); + break; + + case 3: + /* VSX Vector Blend Variable Double 8RR:XX4-Form */ + DIP("xxblendvd v%u,v%u,v%u,v%u\n", + rXT_addr, rXA_addr, rXB_addr, rXC_addr); + + /* Have to use a different trick here */ + assign( mask, + binop( Iop_64HLtoV128, + unop( Iop_1Sto64, + unop( Iop_64to1, + binop( Iop_Shr64, + unop( Iop_V128HIto64, + mkexpr( rXC ) ), + mkU8( 63) ) ) ), + unop( Iop_1Sto64, + unop( Iop_64to1, + binop( Iop_Shr64, + unop( Iop_V128to64, + mkexpr( rXC ) ), + mkU8( 63) ) ) ) ) ); + break; + + default: + vex_printf("dis_vector_blend_prefix (opc2)\n"); + return False; + } + putVSReg( rXT_addr, binop( Iop_OrV128, + binop( Iop_AndV128, + unop( Iop_NotV128, mkexpr( mask ) ), + mkexpr( rXA ) ), + binop( Iop_AndV128, + mkexpr( mask ), + mkexpr( rXB ) ) ) ); + return True; +} /* @@ -17230,6 +17707,343 @@ static Bool dis_av_rotate ( UInt prefix, UInt theInstr ) return True; } +/* + AltiVec Vector Extract Element Instructions +*/ +static Bool dis_av_insert_element ( UInt prefix, UInt theInstr ) +{ + /* VX-Form, + * Source, index and value are GPR, destination is a vector register. + */ + UChar opc1 = ifieldOPC( theInstr ); + UChar VRT = ifieldRegDS( theInstr ); + UChar rA_addr = ifieldRegA( theInstr ); + UChar VRB = ifieldRegB( theInstr ); + UInt opc2 = IFIELD( theInstr, 0, 11 ); + UChar rVT_addr = VRT; + UChar rVB_addr = VRB; + + IRTemp rA = newTemp( Ity_I64 ); + IRTemp vTmp = newTemp( Ity_V128 ); + IRTemp index = newTemp( Ity_I64 ); + UInt max_index_in_src = 15; + + /* There is no prefixed version of these instructions. */ + vassert( !prefix_instruction( prefix ) ); + + assign( vTmp, getVReg( rVT_addr ) ); + assign( rA, getIReg( rA_addr ) ); + assign ( index, binop( Iop_Sub64, + mkU64( 15 ), + mkexpr( rA ) ) ); + + if ( opc1 != 0x4 ) { + vex_printf("dis_av_insert_element(ppc)(instr)\n"); + return False; + } + + switch ( opc2 ) { + case 0x00F: // vinsbvlx, vector insert Byte from VSR Left-indexed VX form + { + IRTemp src = newTemp( Ity_I64 ); + IRTemp adj_index = newTemp( Ity_I64 ); + IRTemp rVB = newTemp( Ity_V128 ); + + DIP("vinsbvlx v%d,%d,v%d", VRT, rA_addr, VRB); + + assign( rVB, getVReg( rVB_addr ) ); + assign( adj_index, binop( Iop_Sub64, + mkU64( max_index_in_src ), + binop( Iop_And64, + mkU64( 0xF), + mkexpr( rA ) ) ) ); + + /* Extract byte in rVB[56:63], that is byte 8 counting from the right */ + assign( src, extract_field_from_vector( rVB, mkU64( 8 ), 0xFF ) ); + putVReg( rVT_addr, + insert_field_into_vector( vTmp, mkexpr( adj_index ), + mkexpr( src), mkU64( 0xFF ) ) ); + } + break; + + case 0x10F: // vinsbvrx, vector insert Byte from VSR Right-indexed VX form + { + IRTemp src = newTemp( Ity_I64 ); + IRTemp rVB = newTemp( Ity_V128 ); + IRTemp adj_index = newTemp( Ity_I64 ); + + DIP("vinsbvrx v%d,%d,v%d", VRT, rA_addr, VRB); + + assign( rVB, getVReg( rVB_addr ) ); + + assign( adj_index, binop( Iop_And64, mkexpr( rA ), mkU64( 0xF ) ) ); + /* Extract byte in rVB[56:63], that is byte 8 counting from the right */ + assign( src, extract_field_from_vector( rVB, mkU64( 8 ), 0xFF ) ); + putVReg( rVT_addr, + insert_field_into_vector( vTmp, mkexpr( rA ), + mkexpr( src), mkU64( 0xFF ) ) ); + } + break; + + case 0x04F: + // vinshvlx, vector insert Halfword from VSR Left-indexed VX form + { + IRTemp src = newTemp( Ity_I64 ); + IRTemp adj_index = newTemp( Ity_I64 ); + IRTemp rVB = newTemp( Ity_V128 ); + + DIP("vinshvlx v%d,%d,v%d", VRT, rA_addr, VRB); + + assign( rVB, getVReg( rVB_addr ) ); + assign( adj_index, binop( Iop_Sub64, + mkU64( max_index_in_src - 1 ), + binop( Iop_And64, + mkexpr( rA ), + mkU64( 0xF ) ) ) ); + + /* Extract half word rVB[48:63], bytes [9:8] counting from the right */ + assign( src, extract_field_from_vector( rVB, mkU64( 8 ), 0xFFFF ) ); + putVReg( rVT_addr, + insert_field_into_vector( vTmp, mkexpr( adj_index ), + mkexpr( src), mkU64( 0xFFFF ) ) ); + } + break; + + case 0x14F: + // vinshvrx, vector insert Halfword from VSR Right-indexed VX form + { + IRTemp src = newTemp( Ity_I64 ); + IRTemp rVB = newTemp( Ity_V128 ); + IRTemp adj_index = newTemp( Ity_I64 ); + + DIP("vinshvrx v%d,%d,v%d", VRT, rA_addr, VRB); + + assign( rVB, getVReg( rVB_addr ) ); + + assign( adj_index, binop( Iop_And64, mkexpr( rA ), mkU64( 0xF ) ) ); + + /* Extract half word rVB[48:63], bytes [9:8] counting from the right */ + assign( src, extract_field_from_vector( rVB, mkU64( 8 ), 0xFFFF ) ); + putVReg( rVT_addr, + insert_field_into_vector( vTmp, mkexpr( rA ), mkexpr( src), + mkU64( 0xFFFF ) ) ); + } + break; + + case 0x08F: + // vinswvlx, vector insert Word from VSR Left-indexed VX form + { + IRTemp src = newTemp( Ity_I64 ); + IRTemp adj_index = newTemp( Ity_I64 ); + IRTemp rVB = newTemp( Ity_V128 ); + + DIP("vinswvlx v%u,%u,v%u", VRT, rA_addr, VRB); + + assign( rVB, getVReg( rVB_addr ) ); + assign( adj_index, binop( Iop_Sub64, + mkU64( max_index_in_src - 3 ), + binop( Iop_And64, + mkU64( 0xF ), + mkexpr( rA ) ) ) ); + + /* Extract word rVB[32:63], bytes [15:8] counting from the right */ + assign( src, extract_field_from_vector( rVB, mkU64( 8 ), 0xFFFFFFFF ) ); + putVReg( rVT_addr, + insert_field_into_vector( vTmp, mkexpr( adj_index ), + mkexpr( src), mkU64( 0xFFFFFFFF ) ) ); + } + break; + + case 0x18F: + // vinswvrx, vector insert Word from VSR Right-indexed VX form + { + IRTemp src = newTemp( Ity_I64 ); + IRTemp rVB = newTemp( Ity_V128 ); + IRTemp adj_index = newTemp( Ity_I64 ); + + DIP("vinswvrx v%u,%u,v%u", VRT, rA_addr, VRB); + + assign( rVB, getVReg( rVB_addr ) ); + + assign( adj_index, binop( Iop_And64, mkexpr( rA ), mkU64( 0xF ) ) ); + /* Extract word in rVB[32:63], bytes [15:8] counting from the right */ + assign( src, extract_field_from_vector( rVB, mkU64( 8 ), 0xFFFFFFFF ) ); + + putVReg( rVT_addr, + insert_field_into_vector( vTmp, mkexpr( rA ), + mkexpr( src), mkU64( 0xFFFFFFFF ) ) ); + } + break; + + case 0x0CF: + // vinsw, vector insert Word from GPR VX form + { + IRTemp rB = newTemp( Ity_I64 ); + UChar rB_addr = ifieldRegB( theInstr ); + UInt UIM = IFIELD( theInstr, 16, 4 ); + UInt max_bytes_in_src = 15; + + DIP("vinsw v%u,%u,%u", VRT, rB_addr, UIM); + + assign( rB, getIReg( rB_addr ) ); + + putVReg( rVT_addr, + insert_field_into_vector( vTmp, + mkU64( max_bytes_in_src - 3 - UIM ), + mkexpr( rB), mkU64( 0xFFFFFFFF ) ) ); + } + break; + + case 0x1CF: + // vinsd, vector insert Doubleword from GPR VX form + { + IRTemp rB = newTemp( Ity_I64 ); + UChar rB_addr = ifieldRegB( theInstr ); + UInt UIM = IFIELD( theInstr, 16, 4 ); + UInt max_bytes_in_src = 15; + + DIP("vinsd v%u,%u,%u", VRT, rB_addr, UIM); + + assign( rB, getIReg( rB_addr ) ); + + putVReg( rVT_addr, + insert_field_into_vector( vTmp, + mkU64( max_bytes_in_src - 7 - UIM ), + mkexpr( rB ), + mkU64( 0xFFFFFFFFFFFFFFFFULL ) ) ); + } + break; + + case 0x20F: // vinsblx, vector insert Byte from GPR Left-indexed VX form + { + IRTemp rB = newTemp( Ity_I64 ); + UChar rB_addr = ifieldRegB( theInstr ); + + DIP("vinsblx v%u,%u,%u", VRT, rA_addr, rB_addr); + + assign( rB, getIReg( rB_addr ) ); + putVReg( rVT_addr, + insert_field_into_vector( vTmp, + binop( Iop_Sub64, + mkU64( max_index_in_src ), + mkexpr( rA ) ), + mkexpr( rB ), mkU64( 0xFF ) ) ); + break; + } + case 0x30F: // vinsbrx, vector insert Byte from GPR Right-indexed VX form + { + IRTemp rB = newTemp( Ity_I64 ); + UChar rB_addr = ifieldRegB( theInstr ); + + DIP("vinsbrx v%u,%u,%u", VRT, rA_addr, rB_addr); + + assign( rB, getIReg( rB_addr ) ); + putVReg( rVT_addr, + insert_field_into_vector( vTmp, mkexpr( rA ), + mkexpr( rB ), mkU64( 0xFF ) ) ); + break; + } + case 0x24F: // vinshlx, vector insert Halfword from GPR Left-indexed VX form + { + IRTemp rB = newTemp( Ity_I64 ); + UChar rB_addr = ifieldRegB( theInstr ); + + DIP("vinshlx v%u,%u,%u", VRT, rA_addr, rB_addr); + + /* insert_field_into_vector assumes right-indexed, convert argument */ + assign( rB, getIReg( rB_addr ) ); + putVReg( rVT_addr, + insert_field_into_vector( vTmp, + binop( Iop_Sub64, + mkU64( max_index_in_src-1 ), + mkexpr( rA ) ), + mkexpr( rB ), mkU64( 0xFFFF ) ) ); + break; + } + case 0x34F:// vinshrx, vector insert Halfword from GPR Right-indexed VX form + { + IRTemp rB = newTemp( Ity_I64 ); + UChar rB_addr = ifieldRegB( theInstr ); + + DIP("vinshrx v%u,%u,%u", VRT, rA_addr, rB_addr); + + assign( rB, getIReg( rB_addr ) ); + putVReg( rVT_addr, + insert_field_into_vector( vTmp, mkexpr( rA ), + mkexpr( rB ), mkU64( 0xFFFF ) ) ); + break; + } + case 0x28F: // vinswlx, vector insert Word from GPR Left-indexed VX form + { + IRTemp rB = newTemp( Ity_I64 ); + UChar rB_addr = ifieldRegB( theInstr ); + + DIP("vinswlx v%u,%u,%u", VRT, rA_addr, rB_addr); + + /* insert_field_into_vector assumes right-indexed, convert argument */ + assign( rB, getIReg( rB_addr ) ); + putVReg( rVT_addr, + insert_field_into_vector( vTmp, + binop( Iop_Sub64, + mkU64( max_index_in_src-3 ), + mkexpr( rA ) ), + mkexpr( rB ), mkU64( 0xFFFFFFFF ) ) ); + break; + } + case 0x38F:// vinswrx, vector insert Word from GPR Right-indexed VX form + { + IRTemp rB = newTemp( Ity_I64 ); + UChar rB_addr = ifieldRegB( theInstr ); + + DIP("vinswrx v%u,%u,%u", VRT, rA_addr, rB_addr); + + assign( rB, getIReg( rB_addr ) ); + putVReg( rVT_addr, + insert_field_into_vector( vTmp, mkexpr( rA ), + mkexpr( rB ), mkU64( 0xFFFFFFFF ) ) ); + break; + } + case 0x2CF: + { + // vinsdlx, vector insert Doubleword from GPR Left-indexed VX form + IRTemp rB = newTemp( Ity_I64 ); + UChar rB_addr = ifieldRegB( theInstr ); + + DIP("vinsdlx v%u,%u,%u", VRT, rA_addr, rB_addr); + + /* insert_field_into_vector assumes right-indexed, convert argument */ + assign( rB, getIReg( rB_addr ) ); + putVReg( rVT_addr, + insert_field_into_vector( vTmp, + binop( Iop_Sub64, + mkU64( max_index_in_src-7 ), + mkexpr( rA ) ), + mkexpr( rB ), + mkU64( 0xFFFFFFFFFFFFFFFFULL ) ) ); + break; + } + case 0x3CF: + { + // vinsdrx, vector insert Doubleword from GPR Right-indexed VX form + IRTemp rB = newTemp( Ity_I64 ); + UChar rB_addr = ifieldRegB( theInstr ); + + DIP("vinsdrx v%u,%u,%u", VRT, rA_addr, rB_addr); + + assign( rB, getIReg( rB_addr ) ); + putVReg( rVT_addr, + insert_field_into_vector( vTmp, mkexpr( rA ), + mkexpr( rB ), + mkU64( 0xFFFFFFFFFFFFFFFFULL ) ) ); + break; + } + default: + vex_printf("dis_av_extract_element(ppc)(opc2)\n"); + return False; + } + return True; +} + /* AltiVec Vector Extract Element Instructions */ @@ -20209,6 +21023,103 @@ dis_vvec_cmp( UInt prefix, UInt theInstr, UInt opc2 ) /* * Miscellaneous VSX Scalar Instructions */ +static Bool +dis_load_vector_special( UInt prefix, UInt theInstr, + const VexAbiInfo* vbi, UInt opc2, int allow_isa_3_0 ) +{ + UChar opc1 = ifieldOPC( theInstr ); + UChar XT = ifieldRegXT ( theInstr ); + UInt uim = IFIELD( theInstr, 11, 5 ); // inst[16:20] + + if (opc1 != 0x3C) { + vex_printf( "dis_load_special(ppc)(instr)\n" ); + return False; + } + + DIP("lxvkq v%u,%u\n", (UInt)XT, uim); + + switch( uim ) { + case 0b00001: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0x3FFF000000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b00010: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0x4000000000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b00011: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0x4000800000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b00100: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0x4001000000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b00101: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0x4001400000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b00110: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0x4001800000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b00111: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0x4001C00000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b01000: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0x7FFF000000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b01001: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0x7FFF800000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b10000: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0x8000000000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b10001: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0xBFFF000000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b10010: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0xC000000000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b10011: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0xC000800000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b10100: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0xC001000000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b10101: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0xC001400000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b10110: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0xC001800000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b10111: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0xC001C00000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + case 0b11000: putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0xFFFF000000000000 ), + mkU64( 0x0000000000000000 ) ) ); + break; + default: vex_printf( "dis_load_special(ppc)(lxvkq XT, UIM not valid)\n" ); + putVSReg( XT, binop( Iop_64HLtoV128, + mkU64( 0x0000000000000000 ), + mkU64( 0x0000000000000000 ) ) ); + return True; /* print message, continue */ + } + return True; +} + static Bool dis_vxs_misc( UInt prefix, UInt theInstr, const VexAbiInfo* vbi, UInt opc2, int allow_isa_3_0 ) @@ -25012,7 +25923,6 @@ static Bool dis_av_arith ( UInt prefix, UInt theInstr ) UInt i; IRType size_op = Ity_I64, size_res = Ity_I64; - if (opc2 == 0x1C9) { DIP("vmulld v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); operation = Iop_MullS64; @@ -25556,7 +26466,7 @@ static Bool dis_av_logic ( UInt prefix, UInt theInstr ) { /* VX-Form */ UChar opc1 = ifieldOPC(theInstr); - UChar vD_addr = ifieldRegDS(theInstr); + UChar vT_addr = ifieldRegDS(theInstr); UChar vA_addr = ifieldRegA(theInstr); UChar vB_addr = ifieldRegB(theInstr); UInt opc2 = IFIELD( theInstr, 0, 11 ); @@ -25576,49 +26486,49 @@ static Bool dis_av_logic ( UInt prefix, UInt theInstr ) switch (opc2) { case 0x404: // vand (And, AV p147) - DIP("vand v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); - putVReg( vD_addr, binop(Iop_AndV128, mkexpr(vA), mkexpr(vB)) ); + DIP("vand v%d,v%d,v%d\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, binop(Iop_AndV128, mkexpr(vA), mkexpr(vB)) ); break; case 0x444: // vandc (And, AV p148) - DIP("vandc v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); - putVReg( vD_addr, binop(Iop_AndV128, mkexpr(vA), + DIP("vandc v%d,v%d,v%d\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, binop(Iop_AndV128, mkexpr(vA), unop(Iop_NotV128, mkexpr(vB))) ); break; case 0x484: // vor (Or, AV p217) - DIP("vor v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); - putVReg( vD_addr, binop(Iop_OrV128, mkexpr(vA), mkexpr(vB)) ); + DIP("vor v%d,v%d,v%d\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, binop(Iop_OrV128, mkexpr(vA), mkexpr(vB)) ); break; case 0x4C4: // vxor (Xor, AV p282) - DIP("vxor v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); - putVReg( vD_addr, binop(Iop_XorV128, mkexpr(vA), mkexpr(vB)) ); + DIP("vxor v%d,v%d,v%d\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, binop(Iop_XorV128, mkexpr(vA), mkexpr(vB)) ); break; case 0x504: // vnor (Nor, AV p216) - DIP("vnor v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); - putVReg( vD_addr, + DIP("vnor v%d,v%d,v%d\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, unop(Iop_NotV128, binop(Iop_OrV128, mkexpr(vA), mkexpr(vB))) ); break; case 0x544: // vorc (vA Or'd with complement of vb) - DIP("vorc v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); - putVReg( vD_addr, binop( Iop_OrV128, + DIP("vorc v%d,v%d,v%d\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, binop( Iop_OrV128, mkexpr( vA ), unop( Iop_NotV128, mkexpr( vB ) ) ) ); break; case 0x584: // vnand (Nand) - DIP("vnand v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); - putVReg( vD_addr, unop( Iop_NotV128, + DIP("vnand v%d,v%d,v%d\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, unop( Iop_NotV128, binop(Iop_AndV128, mkexpr( vA ), mkexpr( vB ) ) ) ); break; case 0x684: // veqv (complemented XOr) - DIP("veqv v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); - putVReg( vD_addr, unop( Iop_NotV128, + DIP("veqv v%d,v%d,v%d\n", vT_addr, vA_addr, vB_addr); + putVReg( vT_addr, unop( Iop_NotV128, binop( Iop_XorV128, mkexpr( vA ), mkexpr( vB ) ) ) ); break; @@ -26299,7 +27209,8 @@ static Bool dis_av_shift ( UInt prefix, UInt theInstr ) UChar vD_addr = ifieldRegDS(theInstr); UChar vA_addr = ifieldRegA(theInstr); UChar vB_addr = ifieldRegB(theInstr); - UInt opc2 = IFIELD( theInstr, 0, 11 ); + UInt opc2_vx_form = IFIELD( theInstr, 0, 11 ); + UInt opc2_vn_form = IFIELD( theInstr, 0, 6 ); IRTemp vA = newTemp(Ity_V128); IRTemp vB = newTemp(Ity_V128); @@ -26314,54 +27225,102 @@ static Bool dis_av_shift ( UInt prefix, UInt theInstr ) vex_printf("dis_av_shift(ppc)(instr)\n"); return False; } + if (opc2_vn_form == 0x16) { + UInt SH = IFIELD( theInstr, 6, 3 ); + UInt bit21_22 = IFIELD( theInstr, 9, 2 ); + IRTemp Middle_128 = newTemp(Ity_V128); + IRTemp tmpLo_64 = newTemp(Ity_I64); + IRTemp tmpHi_64 = newTemp(Ity_I64); + IRTemp result = newTemp(Ity_V128); - switch (opc2) { + assign( Middle_128, binop( Iop_64HLtoV128, + unop( Iop_V128to64, mkexpr( vA ) ), + unop( Iop_V128HIto64, mkexpr( vB ) ) ) ); + + if (bit21_22 == 0) { + // Vector Shift Left Double by Bit Immediate VN-form + DIP("vsldbi v%u,v%u,v%u,%u\n", vD_addr, vA_addr, vB_addr, SH); + + assign( tmpHi_64, + unop( Iop_V128HIto64, + binop( Iop_ShlV128, + mkexpr( vA ), + mkU8( SH ) ) ) ); + assign( result, + binop( Iop_64HLtoV128, + mkexpr( tmpHi_64 ), + unop( Iop_V128HIto64, + binop( Iop_ShlV128, + mkexpr( Middle_128 ), + mkU8( SH ) ) ) ) ); + } else { + // Vector Shift right Double by Bit Immediate VN-form + DIP("vsrdbi v%u,v%u,v%u,%u\n", vD_addr, vA_addr, vB_addr, SH); + + assign( tmpLo_64, + unop( Iop_V128to64, + binop( Iop_ShrV128, + mkexpr( vB ), + mkU8( SH ) ) ) ); + assign( result, + binop( Iop_64HLtoV128, + unop( Iop_V128to64, + binop( Iop_ShrV128, + mkexpr( Middle_128 ), + mkU8( SH ) ) ), + mkexpr( tmpLo_64 ) ) ); + } + putVReg( vD_addr, mkexpr( result ) ); + return True; + } + + switch (opc2_vx_form) { /* Rotate */ case 0x004: // vrlb (Rotate Left Integer B, AV p234) - DIP("vrlb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vrlb v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Rol8x16, mkexpr(vA), mkexpr(vB)) ); break; case 0x044: // vrlh (Rotate Left Integer HW, AV p235) - DIP("vrlh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vrlh v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Rol16x8, mkexpr(vA), mkexpr(vB)) ); break; case 0x084: // vrlw (Rotate Left Integer W, AV p236) - DIP("vrlw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vrlw v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Rol32x4, mkexpr(vA), mkexpr(vB)) ); break; case 0x0C4: // vrld (Rotate Left Integer Double Word) - DIP("vrld v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vrld v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Rol64x2, mkexpr(vA), mkexpr(vB)) ); break; /* Shift Left */ case 0x104: // vslb (Shift Left Integer B, AV p240) - DIP("vslb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vslb v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Shl8x16, mkexpr(vA), mkexpr(vB)) ); break; case 0x144: // vslh (Shift Left Integer HW, AV p242) - DIP("vslh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vslh v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Shl16x8, mkexpr(vA), mkexpr(vB)) ); break; case 0x184: // vslw (Shift Left Integer W, AV p244) - DIP("vslw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vslw v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Shl32x4, mkexpr(vA), mkexpr(vB)) ); break; case 0x5C4: // vsld (Shift Left Integer Double Word) - DIP("vsld v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vsld v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Shl64x2, mkexpr(vA), mkexpr(vB)) ); break; case 0x1C4: { // vsl (Shift Left, AV p239) IRTemp sh = newTemp(Ity_I8); - DIP("vsl v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vsl v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); assign( sh, binop(Iop_And8, mkU8(0x7), unop(Iop_32to8, unop(Iop_V128to32, mkexpr(vB)))) ); @@ -26371,7 +27330,7 @@ static Bool dis_av_shift ( UInt prefix, UInt theInstr ) } case 0x40C: { // vslo (Shift Left by Octet, AV p243) IRTemp sh = newTemp(Ity_I8); - DIP("vslo v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vslo v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); assign( sh, binop(Iop_And8, mkU8(0x78), unop(Iop_32to8, unop(Iop_V128to32, mkexpr(vB)))) ); @@ -26383,23 +27342,23 @@ static Bool dis_av_shift ( UInt prefix, UInt theInstr ) /* Shift Right */ case 0x204: // vsrb (Shift Right B, AV p256) - DIP("vsrb v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vsrb v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Shr8x16, mkexpr(vA), mkexpr(vB)) ); break; case 0x244: // vsrh (Shift Right HW, AV p257) - DIP("vsrh v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vsrh v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Shr16x8, mkexpr(vA), mkexpr(vB)) ); break; case 0x284: // vsrw (Shift Right W, AV p259) - DIP("vsrw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vsrw v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Shr32x4, mkexpr(vA), mkexpr(vB)) ); break; case 0x2C4: { // vsr (Shift Right, AV p251) IRTemp sh = newTemp(Ity_I8); - DIP("vsr v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vsr v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); assign( sh, binop(Iop_And8, mkU8(0x7), unop(Iop_32to8, unop(Iop_V128to32, mkexpr(vB)))) ); @@ -26408,28 +27367,28 @@ static Bool dis_av_shift ( UInt prefix, UInt theInstr ) break; } case 0x304: // vsrab (Shift Right Alg B, AV p253) - DIP("vsrab v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vsrab v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Sar8x16, mkexpr(vA), mkexpr(vB)) ); break; case 0x344: // vsrah (Shift Right Alg HW, AV p254) - DIP("vsrah v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vsrah v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Sar16x8, mkexpr(vA), mkexpr(vB)) ); break; case 0x384: // vsraw (Shift Right Alg W, AV p255) - DIP("vsraw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vsraw v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Sar32x4, mkexpr(vA), mkexpr(vB)) ); break; case 0x3C4: // vsrad (Shift Right Alg Double Word) - DIP("vsrad v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vsrad v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Sar64x2, mkexpr(vA), mkexpr(vB)) ); break; case 0x44C: { // vsro (Shift Right by Octet, AV p258) IRTemp sh = newTemp(Ity_I8); - DIP("vsro v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vsro v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); assign( sh, binop(Iop_And8, mkU8(0x78), unop(Iop_32to8, unop(Iop_V128to32, mkexpr(vB)))) ); @@ -26439,7 +27398,7 @@ static Bool dis_av_shift ( UInt prefix, UInt theInstr ) } case 0x6C4: // vsrd (Shift Right Double Word) - DIP("vsrd v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + DIP("vsrd v%u,v%u,v%u\n", vD_addr, vA_addr, vB_addr); putVReg( vD_addr, binop(Iop_Shr64x2, mkexpr(vA), mkexpr(vB)) ); break; @@ -30063,6 +31022,300 @@ static UInt get_VSX60_opc2(UInt opc2_full, UInt theInstr) return 0; } +static Bool dis_vec_extract_insert ( UInt prefix, UInt theInstr ) +{ + /* VA-Form */ + UChar VRT = ifieldRegDS(theInstr); + UChar VRA = ifieldRegA(theInstr); + UChar VRB = ifieldRegB(theInstr); + UChar rC_addr = ifieldRegC(theInstr); + UChar opc2 = toUChar( IFIELD( theInstr, 0, 6 ) ); + UChar vT_addr = VRT + 32; + UChar vA_addr = VRA + 32; + UChar vB_addr = VRB + 32; + + IRTemp vA = newTemp(Ity_V128); + IRTemp vB = newTemp(Ity_V128); + IRTemp rC = newTemp(Ity_I64); + IRTemp res_tmp = newTemp(Ity_I64); + IRTemp byte_index = newTemp(Ity_I64); + IRTemp index0 = newTemp(Ity_I64); + + UInt index_mask = 0x1F; + UInt max_index_in_src = 31; /* src is vrA | vrB which is 32-bytes */ + + assign( vA, getVSReg( vA_addr ) ); + assign( vB, getVSReg( vB_addr ) ); + assign( rC, getIReg( rC_addr ) ); + + /* Get index of the element to extract */ + assign( byte_index, binop( Iop_And64, + getIReg(rC_addr), + mkU64( index_mask ) ) ); + switch (opc2) { + + case 0x18: + // vextdubvlx, Vector Extract Double Unsigned Byte Left-indexed + DIP("vextdubvlx v%u,v%u,v%u,%u\n", VRT, VRA, VRB, rC_addr); + + /* extractBytefromV256() assumes Right-index ordering */ + assign( index0, + binop( Iop_Sub64, + mkU64( max_index_in_src ), mkexpr( byte_index ) ) ); + assign( res_tmp, extractBytefromV256( vA, vB, index0 ) ); + break; + + case 0x19: + // vextdubvrx, Vector Extract Double Unsigned Byte Right-indexed + DIP("vextdubvrx v%u,v%u,v%u,%u\n", vT_addr, vA_addr, vB_addr, rC_addr); + + assign( res_tmp, extractBytefromV256( vA, vB, byte_index ) ); + break; + + case 0x1A: + { + IRTemp index1 = newTemp(Ity_I64); + + // vextduhvlx, Vector Extract Double Unsigned Half-word Left-indexed + DIP("vextduhvlx v%u,v%u,v%u,%u\n", + vT_addr, vA_addr, vB_addr, rC_addr); + + /* extractBytefromV256() assumes Right-index ordering */ + assign( index0, + binop( Iop_Sub64, + mkU64( max_index_in_src ), mkexpr( byte_index ) ) ); + assign( index1, binop( Iop_Sub64, mkexpr( index0 ), mkU64( 1 ) ) ); + assign( res_tmp, + binop( Iop_Or64, + extractBytefromV256( vA, vB, index1 ), + binop( Iop_Shl64, + extractBytefromV256( vA, vB, index0 ), + mkU8( 8 ) ) ) ); + } + break; + + case 0x1B: + { + IRTemp index1 = newTemp(Ity_I64); + + // vextduhvrx, Vector Extract Double Unsigned Half-word Right-indexed + DIP("vextduhvrx v%u,v%u,v%u,%u\n", + vT_addr, vA_addr, vB_addr, rC_addr); + + assign( index0, mkexpr( byte_index ) ); + assign( index1, binop( Iop_Add64, mkU64( 1 ), mkexpr( index0 ) ) ); + assign( res_tmp, + binop( Iop_Or64, + extractBytefromV256( vA, vB, index0 ), + binop( Iop_Shl64, + extractBytefromV256( vA, vB, index1 ), + mkU8( 8 ) ) ) ); + } + break; + + case 0x1C: + { + IRTemp index1 = newTemp(Ity_I64); + IRTemp index2 = newTemp(Ity_I64); + IRTemp index3 = newTemp(Ity_I64); + + // vextduwvlx, Vector Extract Double Unsigned Word Left-indexed + DIP("vextduwvlx v%u,v%u,v%u,%u\n", + vT_addr, vA_addr, vB_addr, rC_addr); + + /* extractBytefromV256() assumes Right-index ordering */ + assign( index0, + binop( Iop_Sub64, + mkU64( max_index_in_src ), mkexpr( byte_index ) ) ); + assign( index1, binop( Iop_Sub64, mkexpr( index0 ), mkU64( 1 ) ) ); + assign( index2, binop( Iop_Sub64, mkexpr( index1 ), mkU64( 1 ) ) ); + assign( index3, binop( Iop_Sub64, mkexpr( index2 ), mkU64( 1 ) ) ); + assign( res_tmp, + binop( Iop_Or64, + binop( Iop_Or64, + extractBytefromV256( vA, vB, index3 ), + binop( Iop_Shl64, + extractBytefromV256( vA, vB, index2 ), + mkU8( 8 ) ) ), + binop( Iop_Or64, + binop( Iop_Shl64, + extractBytefromV256( vA, vB, index1 ), + mkU8( 16 ) ), + binop( Iop_Shl64, + extractBytefromV256( vA, vB, index0 ), + mkU8( 24 ) ) ) ) ); + } + break; + + case 0x1D: + { + IRTemp index1 = newTemp(Ity_I64); + IRTemp index2 = newTemp(Ity_I64); + IRTemp index3 = newTemp(Ity_I64); + + // vextduwvrx, Vector Extract Double Unsigned Word Right-indexed + DIP("vextduwvrx v%u,v%u,v%u,%u\n", + vT_addr, vA_addr, vB_addr, rC_addr); + + assign( index0, mkexpr( byte_index ) ); + assign( index1, binop( Iop_Add64, mkexpr( index0 ), mkU64( 1 ) ) ); + assign( index2, binop( Iop_Add64, mkexpr( index1 ), mkU64( 1 ) ) ); + assign( index3, binop( Iop_Add64, mkexpr( index2 ), mkU64( 1 ) ) ); + assign( res_tmp, + binop( Iop_Or64, + binop( Iop_Or64, + extractBytefromV256( vA, vB, index0 ), + binop( Iop_Shl64, + extractBytefromV256( vA, vB, index1 ), + mkU8( 8 ) ) ), + binop( Iop_Or64, + binop( Iop_Shl64, + extractBytefromV256( vA, vB, index2 ), + mkU8( 16 ) ), + binop( Iop_Shl64, + extractBytefromV256( vA, vB, index3 ), + mkU8( 24 ) ) ) ) ); + } + break; + case 0x1E: + { + IRTemp index1 = newTemp(Ity_I64); + IRTemp index2 = newTemp(Ity_I64); + IRTemp index3 = newTemp(Ity_I64); + IRTemp index4 = newTemp(Ity_I64); + IRTemp index5 = newTemp(Ity_I64); + IRTemp index6 = newTemp(Ity_I64); + IRTemp index7 = newTemp(Ity_I64); + + // vextddvlx, Vector Extract Double Double-Word Left-indexed + DIP("vextddvlx v%u,v%u,v%u,%u\n", + vT_addr, vA_addr, vB_addr, rC_addr); + + /* extractBytefromV256() assumes Right-index ordering */ + assign( index0, + binop( Iop_Sub64, + mkU64( max_index_in_src ), mkexpr( byte_index ) ) ); + assign( index1, binop( Iop_Sub64, mkexpr( index0 ), mkU64( 1 ) ) ); + assign( index2, binop( Iop_Sub64, mkexpr( index1 ), mkU64( 1 ) ) ); + assign( index3, binop( Iop_Sub64, mkexpr( index2 ), mkU64( 1 ) ) ); + assign( index4, binop( Iop_Sub64, mkexpr( index3 ), mkU64( 1 ) ) ); + assign( index5, binop( Iop_Sub64, mkexpr( index4 ), mkU64( 1 ) ) ); + assign( index6, binop( Iop_Sub64, mkexpr( index5 ), mkU64( 1 ) ) ); + assign( index7, binop( Iop_Sub64, mkexpr( index6 ), mkU64( 1 ) ) ); + assign( res_tmp, + binop( Iop_Or64, + binop( Iop_Or64, + binop( Iop_Or64, + extractBytefromV256( vA, vB, index7 ), + binop( Iop_Shl64, + extractBytefromV256( vA, vB, + index6 ), + mkU8( 8 ) ) ), + binop( Iop_Or64, + binop( Iop_Shl64, + extractBytefromV256( vA, vB, + index5 ), + mkU8( 16 ) )... [truncated message content] |
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From: Carl L. <ca...@so...> - 2020-10-07 16:36:00
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e3d32554219b53481fe91c68a756e63e62925e92 commit e3d32554219b53481fe91c68a756e63e62925e92 Author: Carl Love <ce...@us...> Date: Tue Oct 6 11:52:34 2020 -0500 Vector Integer Multiply/Divide/Modulo Instruction tests Diff: --- NEWS | 3 +- none/tests/ppc64/Makefile.am | 10 +- none/tests/ppc64/test_isa_3_1_VRT.c | 346 ++++++ none/tests/ppc64/test_isa_3_1_VRT.stderr.exp | 2 + none/tests/ppc64/test_isa_3_1_VRT.stdout.exp | 1703 ++++++++++++++++++++++++++ 5 files changed, 2058 insertions(+), 6 deletions(-) diff --git a/NEWS b/NEWS index 13bfe4fa1e..780f2f3243 100644 --- a/NEWS +++ b/NEWS @@ -49,7 +49,8 @@ n-i-bz helgrind: If hg_cli__realloc fails, return NULL. 423021 PPC: Add missing ISA 3.0 documentation link and HWCAPS test. 424298 amd64: Implement RDSEED 426144 Fix "condition variable has not been initialized" on Fedora 33. - +423195 PPC ISA 3.1 support is missing, part 1 +425232 PPC ISA 3.1 support is missing, part 2 Release 3.16.1 (?? June 2020) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index 4ca4ffc86c..3490c5eb60 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -51,12 +51,11 @@ EXTRA_DIST = \ test_isa_3_0_other.stdout.exp-LE test_isa_3_0_other.vgtest \ test_isa_3_1_RT.vgtest test_isa_3_1_RT.stderr.exp test_isa_3_1_RT.stdout.exp \ test_isa_3_1_XT.vgtest test_isa_3_1_XT.stderr.exp test_isa_3_1_XT.stdout.exp \ - test_isa_3_1_VRT.vgtest \ + test_isa_3_1_VRT.vgtest test_isa_3_1_VRT.stderr.exp test_isa_3_1_VRT.stdout.exp \ test_isa_3_1_Misc.vgtest \ test_isa_3_1_AT.vgtest \ subnormal_test.stderr.exp subnormal_test.stdout.exp \ subnormal_test.vgtest -# test_isa_3_1_VRT.vgtest test_isa_3_1_VRT.stderr.exp test_isa_3_1_VRT.stdout.exp # test_isa_3_1_Misc.vgtest test_isa_3_1_Misc.stderr.exp test_isa_3_1_Misc.stdout.exp # test_isa_3_1_AT.vgtest test_isa_3_1_AT.stderr.exp test_isa_3_1_AT.stdout.exp @@ -67,12 +66,12 @@ check_PROGRAMS = \ test_dfp1 test_dfp2 test_dfp3 test_dfp4 test_dfp5 \ test_isa_2_07_part1 test_isa_2_07_part2 \ test_isa_3_0 \ - test_isa_3_1_RT test_isa_3_1_XT \ + test_isa_3_1_RT test_isa_3_1_XT test_isa_3_1_VRT \ subnormal_test \ test_tm test_touch_tm ldst_multiple data-cache-instructions \ power6_mf_gpr std_reg_imm \ twi_tdi tw_td power6_bcmp -# test_isa_3_1_Misc test_isa_3_1_VRT test_isa_3_1_AT +# test_isa_3_1_Misc test_isa_3_1_AT AM_CFLAGS += @FLAG_M64@ AM_CXXFLAGS += @FLAG_M64@ @@ -82,8 +81,8 @@ allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@ test_isa_3_1_XT_SOURCES = test_isa_3_1_XT.c test_isa_3_1_common.c test_isa_3_1_RT_SOURCES = test_isa_3_1_RT.c test_isa_3_1_common.c +test_isa_3_1_VRT_SOURCES = test_isa_3_1_VRT.c test_isa_3_1_common.c -#test_isa_3_1_VRT_SOURCES = test_isa_3_1_VRT.c test_isa_3_1_common.c #test_isa_3_1_AT_SOURCES = test_isa_3_1_AT.c test_isa_3_1_common.c #test_isa_3_1_Misc_SOURCES = test_isa_3_1_Misc.c test_isa_3_1_common.c @@ -189,6 +188,7 @@ test_isa_3_1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_3_1_FL @FLAG_M64@ $(BUILD_FLAGS_ISA_3_1) test_isa_3_1_RT_CFLAGS = $(test_isa_3_1_CFLAGS) test_isa_3_1_XT_CFLAGS = $(test_isa_3_1_CFLAGS) +test_isa_3_1_VRT_CFLAGS = $(test_isa_3_1_CFLAGS) subnormal_test_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) $(ISA_2_06_FLAG) \ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX) $(BUILD_FLAGS_ISA_2_06) diff --git a/none/tests/ppc64/test_isa_3_1_VRT.c b/none/tests/ppc64/test_isa_3_1_VRT.c new file mode 100644 index 0000000000..72025b9bf2 --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_VRT.c @@ -0,0 +1,346 @@ +/* + * Valgrind testcase for PowerPC ISA 3.1 + * + * Copyright (C) 2019-2020 Will Schmidt <wil...@vn...> + * + * 64bit build: + * gcc -Winline -Wall -g -O -mregnames -maltivec -m64 + */ + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <stdio.h> +#ifdef HAS_ISA_3_1 +#include <stdint.h> +#include <assert.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#include <altivec.h> +#include <malloc.h> + +#include <string.h> +#include <signal.h> +#include <setjmp.h> + +/* Condition Register fields. + These are used to capture the condition register values immediately after + the instruction under test is executed. This is done to help prevent other + test overhead (switch statements, result compares, etc) from disturbing + the test case results. */ +unsigned long current_cr; +unsigned long current_fpscr; + +struct test_list_t current_test; + +#include "isa_3_1_helpers.h" + +static void test_vmulhsw (void) { + __asm__ __volatile__ ("vmulhsw %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vmulhuw (void) { + __asm__ __volatile__ ("vmulhuw %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vmulhsd (void) { + __asm__ __volatile__ ("vmulhsd %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vmulhud (void) { + __asm__ __volatile__ ("vmulhud %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vmulld (void) { + __asm__ __volatile__ ("vmulld %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vdivsw (void) { + __asm__ __volatile__ ("vdivsw %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vdivuw (void) { + __asm__ __volatile__ ("vdivuw %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vdivesw (void) { + __asm__ __volatile__ ("vdivesw %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vdiveuw (void) { + __asm__ __volatile__ ("vdiveuw %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vdivsd (void) { + __asm__ __volatile__ ("vdivsd %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vdivud (void) { + __asm__ __volatile__ ("vdivud %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vdivesd (void) { + __asm__ __volatile__ ("vdivesd %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vdiveud (void) { + __asm__ __volatile__ ("vdiveud %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vmodsw (void) { + __asm__ __volatile__ ("vmodsw %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vmoduw (void) { + __asm__ __volatile__ ("vmoduw %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vmodsd (void) { + __asm__ __volatile__ ("vmodsd %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} +static void test_vmodud (void) { + __asm__ __volatile__ ("vmodud %0, %1, %2" + : "=v" (vrt) : "v" (vra), "v" (vrb) ); +} + +static test_list_t testgroup_generic[] = { + { &test_vdivesd, "vdivesd", "VRT,VRA,VRB"}, /* bcs */ + { &test_vdivesw, "vdivesw", "VRT,VRA,VRB"}, /* bcs */ + { &test_vdiveud, "vdiveud", "VRT,VRA,VRB"}, /* bcs */ + { &test_vdiveuw, "vdiveuw", "VRT,VRA,VRB"}, /* bcs */ + { &test_vdivsd, "vdivsd", "VRT,VRA,VRB"}, /* bcs */ + { &test_vdivsw, "vdivsw", "VRT,VRA,VRB"}, /* bcs */ + { &test_vdivud, "vdivud", "VRT,VRA,VRB"}, /* bcs */ + { &test_vdivuw, "vdivuw", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmodsd, "vmodsd", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmodsw, "vmodsw", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmodud, "vmodud", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmoduw, "vmoduw", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmulhsd, "vmulhsd", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmulhsw, "vmulhsw", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmulhud, "vmulhud", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmulhuw, "vmulhuw", "VRT,VRA,VRB"}, /* bcs */ + { &test_vmulld, "vmulld", "VRT,VRA,VRB"}, /* bcs */ + { NULL, NULL }, +}; + +/* Allow skipping of tests. */ +unsigned long test_count=0xffff; +unsigned long skip_count=0; +unsigned long setup_only=0; + +/* Set up a setjmp/longjmp to gently handle our SIGILLs and SIGSEGVs. */ +static jmp_buf mybuf; + +/* This (testfunction_generic) is meant to handle all of the instruction + variations. The helpers set up the register and iterator values + as is appropriate for the instruction being tested. */ +static void testfunction_generic (const char* instruction_name, + test_func_t test_function, + unsigned int ignore_flags, + char * cur_form) { + + identify_form_components (instruction_name , cur_form); + debug_show_form (instruction_name, cur_form); + set_up_iterators (); + debug_show_iter_ranges (); + initialize_buffer (0); + debug_dump_buffer (); + + for (vrai = a_start; vrai < a_iters ; vrai+=a_inc) { + for (vrbi = b_start; vrbi < b_iters ; vrbi+=b_inc) { + for (vrci = c_start; vrci < c_iters ; vrci+=c_inc) { + for (vrmi = m_start; (vrmi < m_iters) ; vrmi+=m_inc) { + CHECK_OVERRIDES + debug_show_current_iteration (); + // Be sure to initialize the target registers first. + initialize_target_registers (); + initialize_source_registers (); + printf ("%s", instruction_name); + print_register_header (); + printf( " =>"); fflush (stdout); + if (!setup_only) { + if (enable_setjmp) { + if ( setjmp ( mybuf ) ) { + printf("signal tripped. (FIXME)\n"); + continue; + } + } + (*test_function) (); + } + print_register_footer (); + print_result_buffer (); + printf ("\n"); + } + } + } + } +} + +void mykillhandler ( int x ) { longjmp (mybuf, 1); } +void mysegvhandler ( int x ) { longjmp (mybuf, 1); } + +static void do_tests ( void ) +{ + int groupcount; + char * cur_form; + test_group_t group_function = &testfunction_generic; + test_list_t *tests = testgroup_generic; + + struct sigaction kill_action, segv_action; + struct sigaction old_kill_action, old_segv_action; + if (enable_setjmp) { + kill_action.sa_handler = mykillhandler; + segv_action.sa_handler = mysegvhandler; + sigemptyset ( &kill_action.sa_mask ); + sigemptyset ( &segv_action.sa_mask ); + kill_action.sa_flags = SA_NODEFER; + segv_action.sa_flags = SA_NODEFER; + sigaction ( SIGILL, &kill_action, &old_kill_action); + sigaction ( SIGSEGV, &segv_action, &old_segv_action); + } + + for (groupcount = 0; tests[groupcount].name != NULL; groupcount++) { + cur_form = strdup(tests[groupcount].form); + current_test = tests[groupcount]; + if (groupcount < skip_count) continue; + if (verbose) printf("Test #%d ,", groupcount); + if (verbose > 1) printf(" instruction %s (v=%d)", current_test.name, verbose); + (*group_function) (current_test.name, current_test.func, 0, cur_form ); + printf ("\n"); + if (groupcount >= (skip_count+test_count)) break; + } + if (debug_show_labels) printf("\n"); + printf ("All done. Tested %d different instruction groups\n", groupcount); +} + +static void usage (void) +{ + fprintf(stderr, + "Usage: test_isa_XXX [OPTIONS]\n" + "\t-h: display this help and exit\n" + "\t-v: increase verbosity\n" + "\t-a <foo> : limit number of a-iterations to <foo>\n" + "\t-b <foo> : limit number of b-iterations to <foo>\n" + "\t-c <foo> : limit number of c-iterations to <foo>\n" + "\t-n <foo> : limit to this number of tests.\n" + "\t-r <foo>: run only test # <foo> \n" + "\t\n" + "\t-j :enable setjmp to recover from illegal insns. \n" + "\t-m :(dev only?) lock VRM value to zero.\n" + "\t-z :(dev only?) lock MC value to zero.\n" + "\t-p :(dev only?) disable prefix instructions\n" + "\t-s <foo>: skip <foo> tests \n" + "\t-c <foo>: stop after running <foo> # of tests \n" + "\t-f : Do the test setup but do not actually execute the test instruction. \n" + ); +} + +int main (int argc, char **argv) +{ + int c; + while ((c = getopt(argc, argv, "dhjvmpfzs:a:b:c:n:r:")) != -1) { + switch (c) { + case 'h': + usage(); + return 0; + + case 'v': + verbose++; + break; + + /* Options related to limiting the test iterations. */ + case 'a': + a_limit=atoi (optarg); + printf ("limiting a-iters to %ld.\n", a_limit); + break; + case 'b': + b_limit=atoi (optarg); + printf ("limiting b-iters to %ld.\n", b_limit); + break; + case 'c': + c_limit=atoi (optarg); + printf ("limiting c-iters to %ld.\n", c_limit); + break; + case 'n': // run this number of tests. + test_count=atoi (optarg); + printf ("limiting to %ld tests\n", test_count); + break; + case 'r': // run just test #<foo>. + skip_count=atoi (optarg); + test_count=0; + if (verbose) printf("Running only test number %ld\n", skip_count); + break; + case 's': // skip this number of tests. + skip_count=atoi (optarg); + printf ("skipping %ld tests\n", skip_count); + break; + + /* debug options. */ + case 'd': + dump_tables=1; + printf("DEBUG:dump_tables.\n"); + break; + case 'f': + setup_only=1; + printf("DEBUG:setup_only.\n"); + break; + case 'j': + enable_setjmp=1; + printf ("DEBUG:setjmp enabled.\n"); + break; + case 'm': + vrm_override=1; + printf ("DEBUG:vrm override enabled.\n"); + break; + case 'p': + prefix_override=1; + printf ("DEBUG:prefix override enabled.\n"); + break; + case 'z': + mc_override=1; + printf ("DEBUG:MC override enabled.\n"); + break; + default: + usage(); + fprintf(stderr, "Unknown argument: '%c'\n", c); + } + } + + generic_prologue (); + build_vsx_table (); + build_args_table (); + build_float_vsx_tables (); + + if (dump_tables) { + dump_float_vsx_tables (); + dump_vsxargs (); + } + + do_tests (); + + return 0; +} + +#else // HAS_ISA_3_1 +int main (int argc, char **argv) +{ + printf("NO ISA 3.1 SUPPORT\n"); + return 0; +} +#endif diff --git a/none/tests/ppc64/test_isa_3_1_VRT.stderr.exp b/none/tests/ppc64/test_isa_3_1_VRT.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_VRT.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp new file mode 100644 index 0000000000..5b35d4f9ba --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_VRT.stdout.exp @@ -0,0 +1,1703 @@ +vdivesd 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivesd 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivesd 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivesd 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => aaabdc510fae6c71,0000000000000000 +vdivesd 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdivesd ff8000007f800000,ff7ffffe7f7ffffe 7f800000ff800000,ff8000007f800000 => 0,fefeff0001020302 +vdivesd ff8000007f800000,ff7ffffe7f7ffffe ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivesd ff8000007f800000,ff7ffffe7f7ffffe ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivesd ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => aaabdafbbf1e5b5f,0000000000000000 +vdivesd ff8000007f800000,ff7ffffe7f7ffffe 0180055e0180077e,0000111e8000222e => 0,aaabdc510fae6c71 +vdivesd ff7ffffe7f7ffffe,0080000e8080000e 7f800000ff800000,ff8000007f800000 => 0,fefefefbfcfdff03 +vdivesd ff7ffffe7f7ffffe,0080000e8080000e ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivesd ff7ffffe7f7ffffe,0080000e8080000e ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivesd ff7ffffe7f7ffffe,0080000e8080000e 0080000e8080000e,0180055e0180077e => 55542daecc8a12ea,0000000000000000 +vdivesd ff7ffffe7f7ffffe,0080000e8080000e 0180055e0180077e,0000111e8000222e => 0,aaabdafbbf1e5b5f +vdivesd 0080000e8080000e,0180055e0180077e 7f800000ff800000,ff8000007f800000 => 0,0101011e1d1c1afb +vdivesd 0080000e8080000e,0180055e0180077e ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdivesd 0080000e8080000e,0180055e0180077e ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdivesd 0080000e8080000e,0180055e0180077e 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdivesd 0080000e8080000e,0180055e0180077e 0180055e0180077e,0000111e8000222e => 0,55542daecc8a12ea +vdivesd 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => ffddc2ffdda0e0de,03030dc9c6c3ba30 +vdivesd 0180055e0180077e,0000111e8000222e ff8000007f800000,ff7ffffe7f7ffffe => ffddc3006694dfcd,0000000000000000 +vdivesd 0180055e0180077e,0000111e8000222e ff7ffffe7f7ffffe,0080000e8080000e => 223cfc1f398f76,0000000000000000 +vdivesd 0180055e0180077e,0000111e8000222e 0080000e8080000e,0180055e0180077e => b6981d5317b70,0000000000000000 +vdivesd 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdivesd 0000111e8000222e,7ff0000000000000 7f800000ff800000,ff8000007f800000 => 0,0000225f5f5f5f1e +vdivesd 0000111e8000222e,7ff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,ffddc2ffdda0e0de +vdivesd 0000111e8000222e,7ff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,ffddc3006694dfcd +vdivesd 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => 0,00223cfc1f398f76 +vdivesd 0000111e8000222e,7ff0000000000000 0180055e0180077e,0000111e8000222e => 0,000b6981d5317b70 +vdivesd 7ff0000000000000,fff0000000000000 7f800000ff800000,ff8000007f800000 => 2000001fe0001fc0,0000000000000000 +vdivesd 7ff0000000000000,fff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 1fffff9fe0012040,0000000000000000 +vdivesd 7ff0000000000000,fff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => e00003a01f96dc4c,0000000000000000 +vdivesd 7ff0000000000000,fff0000000000000 0080000e8080000e,0180055e0180077e => f5557b7f821bd191,0000000000000000 +vdivesd 7ff0000000000000,fff0000000000000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdivesd fff0000000000000,2208400000000000 7f800000ff800000,ff8000007f800000 => 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=> 8030180d00000000,0000112600000000 +vdiveuw 0000111e8000222e,7ff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000112600000000 +vdiveuw 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => 0,00223bfcff0142fd +vdiveuw 0000111e8000222e,7ff0000000000000 0180055e0180077e,0000111e8000222e => 0,000b692c00000000 +vdiveuw 7ff0000000000000,fff0000000000000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdiveuw 7ff0000000000000,fff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,8030180c00000000 +vdiveuw 7ff0000000000000,fff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,8030180d00000000 +vdiveuw 7ff0000000000000,fff0000000000000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdiveuw 7ff0000000000000,fff0000000000000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdiveuw fff0000000000000,2208400000000000 7f800000ff800000,ff8000007f800000 => 22194ca600000000,0000000000000000 +vdiveuw fff0000000000000,2208400000000000 ff8000007f800000,ff7ffffe7f7ffffe => 22194ca600000000,0000000000000000 +vdiveuw fff0000000000000,2208400000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdiveuw fff0000000000000,2208400000000000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdiveuw fff0000000000000,2208400000000000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdiveuw 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => 12,4454d4d400000000 +vdiveuw 2208400000000000,0000000000000009 ff8000007f800000,ff7ffffe7f7ffffe => 12,22194ca600000000 +vdiveuw 2208400000000000,0000000000000009 ff7ffffe7f7ffffe,0080000e8080000e => 11,22194ca600000000 +vdiveuw 2208400000000000,0000000000000009 0080000e8080000e,0180055e0180077e => 5ff,0000000000000000 +vdiveuw 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => 11,0000000000000000 +vdiveuw 0000000000000009,ffff000180000001 7f800000ff800000,ff8000007f800000 => 0,0000000000000009 +vdiveuw 0000000000000009,ffff000180000001 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000012 +vdiveuw 0000000000000009,ffff000180000001 ff7ffffe7f7ffffe,0080000e8080000e => ff00fee7,0000000000000012 +vdiveuw 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => 0,0000000000000011 +vdiveuw 0000000000000009,ffff000180000001 0180055e0180077e,0000111e8000222e => ffffbba6,00000000000005ff +vdiveuw ffff000180000001,0000000000000000 7f800000ff800000,ff8000007f800000 => 0,0000000080402011 +vdiveuw ffff000180000001,0000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => 0,0000000000000000 +vdiveuw ffff000180000001,0000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => 0,0000000000000000 +vdiveuw ffff000180000001,0000000000000000 0080000e8080000e,0180055e0180077e => 0,00000000ff00fee7 +vdiveuw ffff000180000001,0000000000000000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdiveuw 0000000000000000,8000000000000000 7f800000ff800000,ff8000007f800000 => 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7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdiveuw 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 0,7fbfdfef00000000 +vdiveuw 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => fe01fde6,7fbfdff000000000 +vdiveuw 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdiveuw 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => feffbbe8,0000000000000000 + +vdivsd 7f800000ff800000,ff8000007f800000 7f800000ff800000,ff8000007f800000 => 1,0000000000000001 +vdivsd 7f800000ff800000,ff8000007f800000 ff8000007f800000,ff7ffffe7f7ffffe => 0,ffffffffffffff01 +vdivsd 7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => 0,ffffffffffffff02 +vdivsd 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 0,00000000000000fe +vdivsd 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => 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ff7ffffe7f7ffffe,0080000e8080000e 0180055e0180077e,0000111e8000222e => 77a,0000000000000000 +vdivsd 0080000e8080000e,0180055e0180077e 7f800000ff800000,ff8000007f800000 => fffffffffffffffd,0000000000000000 +vdivsd 0080000e8080000e,0180055e0180077e ff8000007f800000,ff7ffffe7f7ffffe => fffffffffffffffd,ffffffffffffffff +vdivsd 0080000e8080000e,0180055e0180077e ff7ffffe7f7ffffe,0080000e8080000e => 3,ffffffffffffffff +vdivsd 0080000e8080000e,0180055e0180077e 0080000e8080000e,0180055e0180077e => 1,0000000000000001 +vdivsd 0080000e8080000e,0180055e0180077e 0180055e0180077e,0000111e8000222e => 166e,0000000000000000 +vdivsd 0180055e0180077e,0000111e8000222e 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivsd 0180055e0180077e,0000111e8000222e ff8000007f800000,ff7ffffe7f7ffffe => 0,fffffffffffffffd +vdivsd 0180055e0180077e,0000111e8000222e ff7ffffe7f7ffffe,0080000e8080000e => 0,fffffffffffffffd +vdivsd 0180055e0180077e,0000111e8000222e 0080000e8080000e,0180055e0180077e => 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0080000e8080000e,0180055e0180077e => 0,00000000000000ff +vdivsd 7ff0000000000000,fff0000000000000 0180055e0180077e,0000111e8000222e => ffffffffffffff11,0000000000000055 +vdivsd fff0000000000000,2208400000000000 7f800000ff800000,ff8000007f800000 => ffffffffffffffbc,0000000000000000 +vdivsd fff0000000000000,2208400000000000 ff8000007f800000,ff7ffffe7f7ffffe => ffffffffffffffbc,0000000000000000 +vdivsd fff0000000000000,2208400000000000 ff7ffffe7f7ffffe,0080000e8080000e => 44,0000000000000000 +vdivsd fff0000000000000,2208400000000000 0080000e8080000e,0180055e0180077e => 16,0000000000000000 +vdivsd fff0000000000000,2208400000000000 0180055e0180077e,0000111e8000222e => 1fceb,0000000000000000 +vdivsd 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivsd 2208400000000000,0000000000000009 ff8000007f800000,ff7ffffe7f7ffffe => 0,ffffffffffffffbc +vdivsd 2208400000000000,0000000000000009 ff7ffffe7f7ffffe,0080000e8080000e => 0,ffffffffffffffbc +vdivsd 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ffff000180000001,0000000000000000 0080000e8080000e,0180055e0180077e => 0,0000000000000000 +vdivsd ffff000180000001,0000000000000000 0180055e0180077e,0000111e8000222e => 0,0000000000000000 +vdivsd 0000000000000000,8000000000000000 7f800000ff800000,ff8000007f800000 => 100,0000000000000000 +vdivsd 0000000000000000,8000000000000000 ff8000007f800000,ff7ffffe7f7ffffe => ff,0000000000000000 +vdivsd 0000000000000000,8000000000000000 ff7ffffe7f7ffffe,0080000e8080000e => ffffffffffffff01,0000000000000000 +vdivsd 0000000000000000,8000000000000000 0080000e8080000e,0180055e0180077e => ffffffffffffffab,0000000000000000 +vdivsd 0000000000000000,8000000000000000 0180055e0180077e,0000111e8000222e => fffffffffff885e3,0000000000000000 +vdivsd 8000000000000000,7f800000ff800000 7f800000ff800000,ff8000007f800000 => ffffffffffffff01,ffffffffffffffff +vdivsd 8000000000000000,7f800000ff800000 ff8000007f800000,ff7ffffe7f7ffffe => ffffffffffffff02,0000000000000100 +vdivsd 8000000000000000,7f800000ff800000 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7f800000ff800000,ff8000007f800000 ff7ffffe7f7ffffe,0080000e8080000e => ffffffff,ffffff0200000000 +vdivsw 7f800000ff800000,ff8000007f800000 0080000e8080000e,0180055e0180077e => 54,000000fe00000000 +vdivsw 7f800000ff800000,ff8000007f800000 0180055e0180077e,0000111e8000222e => fffff88600000000,0000005400000000 +vdivsw ff8000007f800000,ff7ffffe7f7ffffe 7f800000ff800000,ff8000007f800000 => 100000000,00000000ffffff01 +vdivsw ff8000007f800000,ff7ffffe7f7ffffe ff8000007f800000,ff7ffffe7f7ffffe => 100000001,0000000100000001 +vdivsw ff8000007f800000,ff7ffffe7f7ffffe ff7ffffe7f7ffffe,0080000e8080000e => ffffffff,0000000000000001 +vdivsw ff8000007f800000,ff7ffffe7f7ffffe 0080000e8080000e,0180055e0180077e => 54,00000000ffffffff +vdivsw ff8000007f800000,ff7ffffe7f7ffffe 0180055e0180077e,0000111e8000222e => fffff88600000000,0000000000000054 +vdivsw ff7ffffe7f7ffffe,0080000e8080000e 7f800000ff800000,ff8000007f800000 => ffffffff00000000,00000000ffffff02 +vdivsw ff7ffffe7f7ffffe,0080000e8080000e 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7f800000ff800000,ff8000007f800000 => ffffffff,00000000fffffffd +vdivsw 0180055e0180077e,0000111e8000222e ff8000007f800000,ff7ffffe7f7ffffe => ffffffff,fffffffd00000000 +vdivsw 0180055e0180077e,0000111e8000222e ff7ffffe7f7ffffe,0080000e8080000e => 1,fffffffd00000000 +vdivsw 0180055e0180077e,0000111e8000222e 0080000e8080000e,0180055e0180077e => ffffffab,0000000300000000 +vdivsw 0180055e0180077e,0000111e8000222e 0180055e0180077e,0000111e8000222e => 100000001,0000000100000001 +vdivsw 0000111e8000222e,7ff0000000000000 7f800000ff800000,ff8000007f800000 => ffffff0100000000,00000000000000ff +vdivsw 0000111e8000222e,7ff0000000000000 ff8000007f800000,ff7ffffe7f7ffffe => ffffff0100000000,00000000ffffffff +vdivsw 0000111e8000222e,7ff0000000000000 ff7ffffe7f7ffffe,0080000e8080000e => ff00000000,00000000ffffffff +vdivsw 0000111e8000222e,7ff0000000000000 0080000e8080000e,0180055e0180077e => 5500000000,0000000000000001 +vdivsw 0000111e8000222e,7ff0000000000000 0180055e0180077e,0000111e8000222e => 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fff0000000000000,2208400000000000 0180055e0180077e,0000111e8000222e => 1fcfa00000000,0000000000000000 +vdivsw 2208400000000000,0000000000000009 7f800000ff800000,ff8000007f800000 => 0,0000000000000000 +vdivsw 2208400000000000,0000000000000009 ff8000007f800000,ff7ffffe7f7ffffe => 0,ffffffbc00000000 +vdivsw 2208400000000000,0000000000000009 ff7ffffe7f7ffffe,0080000e8080000e => 0,ffffffbc00000000 +vdivsw 2208400000000000,0000000000000009 0080000e8080000e,0180055e0180077e => 0,0000004400000000 +vdivsw 2208400000000000,0000000000000009 0180055e0180077e,0000111e8000222e => 0,0000001600000000 +vdivsw 0000000000000009,ffff000180000001 7f800000ff800000,ff8000007f800000 => ffffffff,0000000000000000 +vdivsw 0000000000000009,ffff000180000001 ff8000007f800000,ff7ffffe7f7ffffe => ffffffff,0000000000000000 +vdivsw 0000000000000009,ffff000180000001 ff7ffffe7f7ffffe,0080000e8080000e => 1,0000000000000000 +vdivsw 0000000000000009,ffff000180000001 0080000e8080000e,0180055e0180077e => ffffffab,0000000000000000 +vdivsw 0000000000000009,ffff000180000001 0180055e0180077e,0000111e8000222e => fffffff200000001,0000000000000000 +vdivsw ffff000180000001,0000000000000000 7f800000ff800000,ff8000007f800000 => 0,00000000000000ff +vdivsw ffff000180000... [truncated message content] |
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From: Carl L. <ca...@so...> - 2020-10-07 16:35:40
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=78e7de504c9e311a15c3d081cc2098c568dc8399 commit 78e7de504c9e311a15c3d081cc2098c568dc8399 Author: Carl Love <ce...@us...> Date: Tue Oct 6 11:51:19 2020 -0500 VSX 32-byte storage access operations Diff: --- none/tests/ppc64/test_isa_3_1_RT.c | 20 +++++++++++ none/tests/ppc64/test_isa_3_1_RT.stdout.exp | 12 ++++++- none/tests/ppc64/test_isa_3_1_XT.c | 52 +++++++++++++++++++++++++++++ none/tests/ppc64/test_isa_3_1_XT.stdout.exp | 38 ++++++++++++++++++++- 4 files changed, 120 insertions(+), 2 deletions(-) diff --git a/none/tests/ppc64/test_isa_3_1_RT.c b/none/tests/ppc64/test_isa_3_1_RT.c index 23586ab5fb..c6f8422ab3 100644 --- a/none/tests/ppc64/test_isa_3_1_RT.c +++ b/none/tests/ppc64/test_isa_3_1_RT.c @@ -58,6 +58,21 @@ static void test_brw (void) { static void test_brd (void) { __asm__ __volatile__ ("brd %0, %1" : "=r" (ra) : "r" (rs) ); } +static void test_plxvp_off0 (void) { + __asm__ __volatile__ ("plxvp 20, 0(%0), 0" :: "r" (ra) ); +} +static void test_plxvp_off8 (void) { + __asm__ __volatile__ ("plxvp 20, 8(%0), 0" :: "r" (ra) ); +} +static void test_plxvp_off16 (void) { + __asm__ __volatile__ ("plxvp 20, 16(%0), 0" :: "r" (ra) ); +} +static void test_plxvp_off24 (void) { + __asm__ __volatile__ ("plxvp 20, 24(%0), 0" :: "r" (ra) ); +} +static void test_plxvp_off32 (void) { + __asm__ __volatile__ ("plxvp 20, 32(%0), 0" :: "r" (ra) ); +} static void test_setbc_0_cr0s (void) { SET_CR(0x00000000); __asm__ __volatile__ ("setbc 26, 0"); @@ -686,6 +701,11 @@ static test_list_t testgroup_generic[] = { { &test_plwz_off16, "plwz off16", "RT,D(RA),R"}, /* bcwp */ { &test_plwz_off32, "plwz off32", "RT,D(RA),R"}, /* bcwp */ { &test_plwz_off64, "plwz off64", "RT,D(RA),R"}, /* bcwp */ + { &test_plxvp_off0, "plxvp off0", "XTp,D(RA),R"}, /* bcwp */ + { &test_plxvp_off8, "plxvp off8", "XTp,D(RA),R"}, /* bcwp */ + { &test_plxvp_off16, "plxvp off16", "XTp,D(RA),R"}, /* bcwp */ + { &test_plxvp_off24, "plxvp off24", "XTp,D(RA),R"}, /* bcwp */ + { &test_plxvp_off32, "plxvp off32", "XTp,D(RA),R"}, /* bcwp */ { &test_pstb_off0, "pstb off0", "RS,D(RA),R"}, /* bcwp */ { &test_pstb_off8, "pstb off8", "RS,D(RA),R"}, /* bcwp */ { &test_pstb_off16, "pstb off16", "RS,D(RA),R"}, /* bcwp */ diff --git a/none/tests/ppc64/test_isa_3_1_RT.stdout.exp b/none/tests/ppc64/test_isa_3_1_RT.stdout.exp index bc7a6e5553..2cfd5cd66a 100644 --- a/none/tests/ppc64/test_isa_3_1_RT.stdout.exp +++ b/none/tests/ppc64/test_isa_3_1_RT.stdout.exp @@ -119,6 +119,16 @@ plwz off32 (&buffer) => 5a07a05 plwz off64 (&buffer) => bbaa7988 +plxvp off0 (&buffer) => 7ff0000000007000 7f0000007f007000 3fe00094e0007359 7ff7020304057607 + +plxvp off8 (&buffer) => 7f0000007f007000 5a05a05a05a07a05 7ff7020304057607 7ff0000000007000 + +plxvp off16 (&buffer) => 5a05a05a05a07a05 0102030405067708 7ff0000000007000 7f0000007f007000 + +plxvp off24 (&buffer) => 0102030405067708 fedcba9876547210 7f0000007f007000 5a05a05a05a07a05 + +plxvp off32 (&buffer) => fedcba9876547210 0123456789ab7def 5a05a05a05a07a05 0102030405067708 + pstb off0 (&buffer) 102030405060708 => [3fe00094e0007308 - - - - - - - ] pstb off8 (&buffer) 102030405060708 => [ - 7ff7020304057608 - - - - - - ] @@ -326,4 +336,4 @@ setnbc 31_creb => [aaaaaaaa] 0 setnbc 31_crob => [55555555] ffffffffffffffff -All done. Tested 144 different instruction groups +All done. Tested 149 different instruction groups diff --git a/none/tests/ppc64/test_isa_3_1_XT.c b/none/tests/ppc64/test_isa_3_1_XT.c index de75953d24..92d896b4e2 100644 --- a/none/tests/ppc64/test_isa_3_1_XT.c +++ b/none/tests/ppc64/test_isa_3_1_XT.c @@ -49,6 +49,45 @@ struct test_list_t current_test; #include "isa_3_1_helpers.h" +static void test_lxvp_32 (void) { + __asm__ __volatile__ ("lxvp 20, 32(%0)" :: "r" (ra) ); +} +static void test_lxvp_16 (void) { + __asm__ __volatile__ ("lxvp 20, 16(%0)" :: "r" (ra) ); +} +static void test_lxvp_0 (void) { + __asm__ __volatile__ ("lxvp 20, 0(%0)" :: "r" (ra) ); +} +static void test_lxvpx (void) { + __asm__ __volatile__ ("lxvpx 20, %0, %1" :: "r" (ra), "r" (rb) ); +} +static void test_stxvp_off0 (void) { + __asm__ __volatile__ ("stxvp 20, 0(%0)" :: "r" (ra) ); +} +static void test_stxvp_off16 (void) { + __asm__ __volatile__ ("stxvp 20, 16(%0)" :: "r" (ra) ); +} +static void test_stxvp_off32 (void) { + __asm__ __volatile__ ("stxvp 20, 32(%0)" :: "r" (ra) ); +} +static void test_stxvp_off48 (void) { + __asm__ __volatile__ ("stxvp 20, 48(%0)" :: "r" (ra) ); +} +static void test_pstxvp_off0 (void) { + __asm__ __volatile__ ("pstxvp 20, 0(%0)" :: "r" (ra) ); +} +static void test_pstxvp_off16 (void) { + __asm__ __volatile__ ("pstxvp 20, 16(%0)" :: "r" (ra) ); +} +static void test_pstxvp_off32 (void) { + __asm__ __volatile__ ("pstxvp 20, 32(%0)" :: "r" (ra) ); +} +static void test_pstxvp_off48 (void) { + __asm__ __volatile__ ("pstxvp 20, 48(%0)" :: "r" (ra) ); +} +static void test_stxvpx (void) { + __asm__ __volatile__ ("stxvpx 20, %0, %1" :: "r" (ra), "r" (rb) ); +} static void test_plfd_64 (void) { __asm__ __volatile__ ("plfd 28, 64(%0), 0" :: "r" (ra) ); } @@ -213,6 +252,10 @@ static void test_pstxv_0 (void) { } static test_list_t testgroup_generic[] = { + { &test_lxvpx, "lxvpx", "XTp,RA,RB"}, /* bcs */ + { &test_lxvp_0, "lxvp 0", "XTp,DQ(RA)"}, /* bcwp */ + { &test_lxvp_16, "lxvp 16", "XTp,DQ(RA)"}, /* bcwp */ + { &test_lxvp_32, "lxvp 32", "XTp,DQ(RA)"}, /* bcwp */ { &test_plfd_0, "plfd 0", "FRT,D(RA),R"}, /* bcwp */ { &test_plfd_4, "plfd 4", "FRT,D(RA),R"}, /* bcwp */ { &test_plfd_8, "plfd 8", "FRT,D(RA),R"}, /* bcwp */ @@ -263,10 +306,19 @@ static test_list_t testgroup_generic[] = { { &test_pstxssp_16, "pstxssp 16", "VRS,D(RA),R"}, /* bcwp */ { &test_pstxssp_32, "pstxssp 32", "VRS,D(RA),R"}, /* bcwp */ { &test_pstxssp_64, "pstxssp 64", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxvp_off0, "pstxvp off0", "XSp,D(RA),R"}, /* bcwp */ + { &test_pstxvp_off16, "pstxvp off16", "XSp,D(RA),R"}, /* bcwp */ + { &test_pstxvp_off32, "pstxvp off32", "XSp,D(RA),R"}, /* bcwp */ + { &test_pstxvp_off48, "pstxvp off48", "XSp,D(RA),R"}, /* bcwp */ { &test_pstxv_0, "pstxv 0", "XS,D(RA),R"}, /* bcwp */ { &test_pstxv_4, "pstxv 4", "XS,D(RA),R"}, /* bcwp */ { &test_pstxv_8, "pstxv 8", "XS,D(RA),R"}, /* bcwp */ { &test_pstxv_16, "pstxv 16", "XS,D(RA),R"}, /* bcwp */ + { &test_stxvpx, "stxvpx", "XSp,RA,RB"}, /* bcs */ + { &test_stxvp_off0, "stxvp off0", "XSp,DQ(RA)"}, /* bcwp */ + { &test_stxvp_off16, "stxvp off16", "XSp,DQ(RA)"}, /* bcwp */ + { &test_stxvp_off32, "stxvp off32", "XSp,DQ(RA)"}, /* bcwp */ + { &test_stxvp_off48, "stxvp off48", "XSp,DQ(RA)"}, /* bcwp */ { NULL, NULL }, }; diff --git a/none/tests/ppc64/test_isa_3_1_XT.stdout.exp b/none/tests/ppc64/test_isa_3_1_XT.stdout.exp index 2132cf1409..fab9cef020 100644 --- a/none/tests/ppc64/test_isa_3_1_XT.stdout.exp +++ b/none/tests/ppc64/test_isa_3_1_XT.stdout.exp @@ -1,3 +1,16 @@ +lxvpx 0 (&buffer) => 7ff0000000007000 7f0000007f007000 3fe00094e0007359 7ff7020304057607 +lxvpx 8 (&buffer) => 7f0000007f007000 5a05a05a05a07a05 7ff7020304057607 7ff0000000007000 +lxvpx 10 (&buffer) => 5a05a05a05a07a05 0102030405067708 7ff0000000007000 7f0000007f007000 +lxvpx 18 (&buffer) => 0102030405067708 fedcba9876547210 7f0000007f007000 5a05a05a05a07a05 +lxvpx 20 (&buffer) => fedcba9876547210 0123456789ab7def 5a05a05a05a07a05 0102030405067708 +lxvpx 28 (&buffer) => 0123456789ab7def ffeeddccbbaa7988 0102030405067708 fedcba9876547210 + +lxvp 0 (&buffer) => 7ff0000000007000 7f0000007f007000 3fe00094e0007359 7ff7020304057607 + +lxvp 16 (&buffer) => 5a05a05a05a07a05 0102030405067708 7ff0000000007000 7f0000007f007000 + +lxvp 32 (&buffer) => fedcba9876547210 0123456789ab7def 5a05a05a05a07a05 0102030405067708 + plfd 0 (&buffer) => 5.000710e-01 plfd 4 (&buffer) => 2.752739e-289 @@ -108,6 +121,14 @@ pstxssp 32 (&buffer) => [ - - - - 5a05a05a00000000 - - - ] pstxssp 64 (&buffer) => +pstxvp off0 (&buffer) 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800000 => [ff7ffffe7f7ffffe ff8000007f800000 0180055e0180077e 0080000e8080000e - - - - ] + +pstxvp off16 (&buffer) 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800000 => [ - - ff7ffffe7f7ffffe ff8000007f800000 0180055e0180077e 0080000e8080000e - - ] + +pstxvp off32 (&buffer) 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800000 => [ - - - - ff7ffffe7f7ffffe ff8000007f800000 0180055e0180077e 0080000e8080000e] + +pstxvp off48 (&buffer) 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800000 => [ - - - - - - ff7ffffe7f7ffffe ff8000007f800000] + pstxv 0 (&buffer) ff7ffffe7f7ffffe,ff8000007f800000 => [ff7ffffe7f7ffffe ff8000007f800000 - - - - - - ] pstxv 4 (&buffer) ff7ffffe7f7ffffe,ff8000007f800000 => [7f7ffffee0007359 7f800000ff7ffffe 7ff00000ff800000 - - - - - ] @@ -116,4 +137,19 @@ pstxv 8 (&buffer) ff7ffffe7f7ffffe,ff8000007f800000 => [ - ff7ffffe7f7ffffe ff8 pstxv 16 (&buffer) ff7ffffe7f7ffffe,ff8000007f800000 => [ - - ff7ffffe7f7ffffe ff8000007f800000 - - - - ] -All done. Tested 54 different instruction groups +stxvpx 0 (&buffer) 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800000 => [ff7ffffe7f7ffffe ff8000007f800000 0180055e0180077e 0080000e8080000e - - - - ] +stxvpx 8 (&buffer) 0000111e8000222e 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe => [ - 0080000e8080000e ff7ffffe7f7ffffe 0000111e8000222e 0180055e0180077e - - - ] +stxvpx 10 (&buffer) 7ff0000000000000 0000111e8000222e 0180055e0180077e 0080000e8080000e => [ - - 0180055e0180077e 0080000e8080000e 7ff0000000000000 0000111e8000222e - - ] +stxvpx 18 (&buffer) fff0000000000000 7ff0000000000000 0000111e8000222e 0180055e0180077e => [ - - - 0000111e8000222e 0180055e0180077e fff0000000000000 7ff0000000000000 - ] +stxvpx 20 (&buffer) 2208400000000000 fff0000000000000 7ff0000000000000 0000111e8000222e => [ - - - - 7ff0000000000000 0000111e8000222e 2208400000000000 fff0000000000000] +stxvpx 28 (&buffer) 0000000000000009 2208400000000000 fff0000000000000 7ff0000000000000 => [ - - - - - fff0000000000000 7ff0000000000000 0000000000000009] + +stxvp off0 (&buffer) 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800000 => [ff7ffffe7f7ffffe ff8000007f800000 0180055e0180077e 0080000e8080000e - - - - ] + +stxvp off16 (&buffer) 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800000 => [ - - ff7ffffe7f7ffffe ff8000007f800000 0180055e0180077e 0080000e8080000e - - ] + +stxvp off32 (&buffer) 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800000 => [ - - - - ff7ffffe7f7ffffe ff8000007f800000 0180055e0180077e 0080000e8080000e] + +stxvp off48 (&buffer) 0180055e0180077e 0080000e8080000e ff7ffffe7f7ffffe ff8000007f800000 => [ - - - - - - ff7ffffe7f7ffffe ff8000007f800000] + +All done. Tested 67 different instruction groups |
|
From: Carl L. <ca...@so...> - 2020-10-07 16:35:30
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=5fcffeabebc31df0e34099bec431be166ad0c44f commit 5fcffeabebc31df0e34099bec431be166ad0c44f Author: Carl Love <ce...@us...> Date: Tue Oct 6 11:44:50 2020 -0500 Set boolean support tests Diff: --- none/tests/ppc64/test_isa_3_1_RT.c | 480 ++++++++++++++++++++++++++++ none/tests/ppc64/test_isa_3_1_RT.stdout.exp | 162 +++++++++- 2 files changed, 641 insertions(+), 1 deletion(-) diff --git a/none/tests/ppc64/test_isa_3_1_RT.c b/none/tests/ppc64/test_isa_3_1_RT.c index a6e55f9210..23586ab5fb 100644 --- a/none/tests/ppc64/test_isa_3_1_RT.c +++ b/none/tests/ppc64/test_isa_3_1_RT.c @@ -58,6 +58,406 @@ static void test_brw (void) { static void test_brd (void) { __asm__ __volatile__ ("brd %0, %1" : "=r" (ra) : "r" (rs) ); } +static void test_setbc_0_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setbc 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_0_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setbc 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_0_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setbc 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_0_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setbc 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_3_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setbc 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_3_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setbc 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_3_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setbc 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_3_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setbc 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_7_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setbc 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_7_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setbc 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_7_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setbc 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_7_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setbc 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_8_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setbc 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_8_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setbc 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_8_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setbc 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_8_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setbc 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_31_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setbc 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_31_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setbc 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_31_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setbc 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbc_31_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setbc 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_0_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setbcr 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_0_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setbcr 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_0_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setbcr 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_0_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setbcr 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_3_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setbcr 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_3_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setbcr 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_3_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setbcr 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_3_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setbcr 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_7_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setbcr 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_7_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setbcr 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_7_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setbcr 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_7_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setbcr 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_8_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setbcr 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_8_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setbcr 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_8_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setbcr 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_8_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setbcr 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_31_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setbcr 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_31_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setbcr 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_31_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setbcr 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setbcr_31_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setbcr 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_0_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setnbc 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_0_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setnbc 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_0_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setnbc 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_0_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setnbc 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_3_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setnbc 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_3_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setnbc 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_3_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setnbc 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_3_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setnbc 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_7_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setnbc 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_7_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setnbc 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_7_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setnbc 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_7_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setnbc 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_8_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setnbc 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_8_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setnbc 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_8_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setnbc 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_8_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setnbc 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_31_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setnbc 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_31_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setnbc 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_31_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setnbc 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbc_31_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setnbc 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_0_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setnbcr 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_0_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setnbcr 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_0_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setnbcr 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_0_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setnbcr 26, 0"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_3_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setnbcr 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_3_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setnbcr 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_3_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setnbcr 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_3_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setnbcr 26, 3"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_7_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setnbcr 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_7_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setnbcr 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_7_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setnbcr 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_7_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setnbcr 26, 7"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_8_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setnbcr 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_8_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setnbcr 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_8_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setnbcr 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_8_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setnbcr 26, 8"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_31_cr0s (void) { + SET_CR(0x00000000); + __asm__ __volatile__ ("setnbcr 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_31_cr1s (void) { + SET_CR(0xffffffff); + __asm__ __volatile__ ("setnbcr 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_31_creb (void) { + SET_CR(0xaaaaaaaa); + __asm__ __volatile__ ("setnbcr 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} +static void test_setnbcr_31_crob (void) { + SET_CR(0x55555555); + __asm__ __volatile__ ("setnbcr 26, 31"); + GET_CR(current_cr); SET_CR_ZERO; +} static void test_plbz_off0 (void) { __asm__ __volatile__ ("plbz %0, 0(%1), 0" : "=r" (rt) : "r" (ra) ); } @@ -307,6 +707,86 @@ static test_list_t testgroup_generic[] = { { &test_pstw_off8, "pstw off8", "RS,D(RA),R"}, /* bcwp */ { &test_pstw_off16, "pstw off16", "RS,D(RA),R"}, /* bcwp */ { &test_pstw_off32, "pstw off32", "RS,D(RA),R"}, /* bcwp */ + { &test_setbcr_0_cr0s, "setbcr 0_cr0s", "RT,BI"}, /* bcwp */ + { &test_setbcr_0_cr1s, "setbcr 0_cr1s", "RT,BI"}, /* bcwp */ + { &test_setbcr_0_creb, "setbcr 0_creb", "RT,BI"}, /* bcwp */ + { &test_setbcr_0_crob, "setbcr 0_crob", "RT,BI"}, /* bcwp */ + { &test_setbcr_3_cr0s, "setbcr 3_cr0s", "RT,BI"}, /* bcwp */ + { &test_setbcr_3_cr1s, "setbcr 3_cr1s", "RT,BI"}, /* bcwp */ + { &test_setbcr_3_creb, "setbcr 3_creb", "RT,BI"}, /* bcwp */ + { &test_setbcr_3_crob, "setbcr 3_crob", "RT,BI"}, /* bcwp */ + { &test_setbcr_7_cr0s, "setbcr 7_cr0s", "RT,BI"}, /* bcwp */ + { &test_setbcr_7_cr1s, "setbcr 7_cr1s", "RT,BI"}, /* bcwp */ + { &test_setbcr_7_creb, "setbcr 7_creb", "RT,BI"}, /* bcwp */ + { &test_setbcr_7_crob, "setbcr 7_crob", "RT,BI"}, /* bcwp */ + { &test_setbcr_8_cr0s, "setbcr 8_cr0s", "RT,BI"}, /* bcwp */ + { &test_setbcr_8_cr1s, "setbcr 8_cr1s", "RT,BI"}, /* bcwp */ + { &test_setbcr_8_creb, "setbcr 8_creb", "RT,BI"}, /* bcwp */ + { &test_setbcr_8_crob, "setbcr 8_crob", "RT,BI"}, /* bcwp */ + { &test_setbcr_31_cr0s, "setbcr 31_cr0s", "RT,BI"}, /* bcwp */ + { &test_setbcr_31_cr1s, "setbcr 31_cr1s", "RT,BI"}, /* bcwp */ + { &test_setbcr_31_creb, "setbcr 31_creb", "RT,BI"}, /* bcwp */ + { &test_setbcr_31_crob, "setbcr 31_crob", "RT,BI"}, /* bcwp */ + { &test_setbc_0_cr0s, "setbc 0_cr0s", "RT,BI"}, /* bcwp */ + { &test_setbc_0_cr1s, "setbc 0_cr1s", "RT,BI"}, /* bcwp */ + { &test_setbc_0_creb, "setbc 0_creb", "RT,BI"}, /* bcwp */ + { &test_setbc_0_crob, "setbc 0_crob", "RT,BI"}, /* bcwp */ + { &test_setbc_3_cr0s, "setbc 3_cr0s", "RT,BI"}, /* bcwp */ + { &test_setbc_3_cr1s, "setbc 3_cr1s", "RT,BI"}, /* bcwp */ + { &test_setbc_3_creb, "setbc 3_creb", "RT,BI"}, /* bcwp */ + { &test_setbc_3_crob, "setbc 3_crob", "RT,BI"}, /* bcwp */ + { &test_setbc_7_cr0s, "setbc 7_cr0s", "RT,BI"}, /* bcwp */ + { &test_setbc_7_cr1s, "setbc 7_cr1s", "RT,BI"}, /* bcwp */ + { &test_setbc_7_creb, "setbc 7_creb", "RT,BI"}, /* bcwp */ + { &test_setbc_7_crob, "setbc 7_crob", "RT,BI"}, /* bcwp */ + { &test_setbc_8_cr0s, "setbc 8_cr0s", "RT,BI"}, /* bcwp */ + { &test_setbc_8_cr1s, "setbc 8_cr1s", "RT,BI"}, /* bcwp */ + { &test_setbc_8_creb, "setbc 8_creb", "RT,BI"}, /* bcwp */ + { &test_setbc_8_crob, "setbc 8_crob", "RT,BI"}, /* bcwp */ + { &test_setbc_31_cr0s, "setbc 31_cr0s", "RT,BI"}, /* bcwp */ + { &test_setbc_31_cr1s, "setbc 31_cr1s", "RT,BI"}, /* bcwp */ + { &test_setbc_31_creb, "setbc 31_creb", "RT,BI"}, /* bcwp */ + { &test_setbc_31_crob, "setbc 31_crob", "RT,BI"}, /* bcwp */ + { &test_setnbcr_0_cr0s, "setnbcr 0_cr0s", "RT,BI"}, /* bcwp */ + { &test_setnbcr_0_cr1s, "setnbcr 0_cr1s", "RT,BI"}, /* bcwp */ + { &test_setnbcr_0_creb, "setnbcr 0_creb", "RT,BI"}, /* bcwp */ + { &test_setnbcr_0_crob, "setnbcr 0_crob", "RT,BI"}, /* bcwp */ + { &test_setnbcr_3_cr0s, "setnbcr 3_cr0s", "RT,BI"}, /* bcwp */ + { &test_setnbcr_3_cr1s, "setnbcr 3_cr1s", "RT,BI"}, /* bcwp */ + { &test_setnbcr_3_creb, "setnbcr 3_creb", "RT,BI"}, /* bcwp */ + { &test_setnbcr_3_crob, "setnbcr 3_crob", "RT,BI"}, /* bcwp */ + { &test_setnbcr_7_cr0s, "setnbcr 7_cr0s", "RT,BI"}, /* bcwp */ + { &test_setnbcr_7_cr1s, "setnbcr 7_cr1s", "RT,BI"}, /* bcwp */ + { &test_setnbcr_7_creb, "setnbcr 7_creb", "RT,BI"}, /* bcwp */ + { &test_setnbcr_7_crob, "setnbcr 7_crob", "RT,BI"}, /* bcwp */ + { &test_setnbcr_8_cr0s, "setnbcr 8_cr0s", "RT,BI"}, /* bcwp */ + { &test_setnbcr_8_cr1s, "setnbcr 8_cr1s", "RT,BI"}, /* bcwp */ + { &test_setnbcr_8_creb, "setnbcr 8_creb", "RT,BI"}, /* bcwp */ + { &test_setnbcr_8_crob, "setnbcr 8_crob", "RT,BI"}, /* bcwp */ + { &test_setnbcr_31_cr0s, "setnbcr 31_cr0s", "RT,BI"}, /* bcwp */ + { &test_setnbcr_31_cr1s, "setnbcr 31_cr1s", "RT,BI"}, /* bcwp */ + { &test_setnbcr_31_creb, "setnbcr 31_creb", "RT,BI"}, /* bcwp */ + { &test_setnbcr_31_crob, "setnbcr 31_crob", "RT,BI"}, /* bcwp */ + { &test_setnbc_0_cr0s, "setnbc 0_cr0s", "RT,BI"}, /* bcwp */ + { &test_setnbc_0_cr1s, "setnbc 0_cr1s", "RT,BI"}, /* bcwp */ + { &test_setnbc_0_creb, "setnbc 0_creb", "RT,BI"}, /* bcwp */ + { &test_setnbc_0_crob, "setnbc 0_crob", "RT,BI"}, /* bcwp */ + { &test_setnbc_3_cr0s, "setnbc 3_cr0s", "RT,BI"}, /* bcwp */ + { &test_setnbc_3_cr1s, "setnbc 3_cr1s", "RT,BI"}, /* bcwp */ + { &test_setnbc_3_creb, "setnbc 3_creb", "RT,BI"}, /* bcwp */ + { &test_setnbc_3_crob, "setnbc 3_crob", "RT,BI"}, /* bcwp */ + { &test_setnbc_7_cr0s, "setnbc 7_cr0s", "RT,BI"}, /* bcwp */ + { &test_setnbc_7_cr1s, "setnbc 7_cr1s", "RT,BI"}, /* bcwp */ + { &test_setnbc_7_creb, "setnbc 7_creb", "RT,BI"}, /* bcwp */ + { &test_setnbc_7_crob, "setnbc 7_crob", "RT,BI"}, /* bcwp */ + { &test_setnbc_8_cr0s, "setnbc 8_cr0s", "RT,BI"}, /* bcwp */ + { &test_setnbc_8_cr1s, "setnbc 8_cr1s", "RT,BI"}, /* bcwp */ + { &test_setnbc_8_creb, "setnbc 8_creb", "RT,BI"}, /* bcwp */ + { &test_setnbc_8_crob, "setnbc 8_crob", "RT,BI"}, /* bcwp */ + { &test_setnbc_31_cr0s, "setnbc 31_cr0s", "RT,BI"}, /* bcwp */ + { &test_setnbc_31_cr1s, "setnbc 31_cr1s", "RT,BI"}, /* bcwp */ + { &test_setnbc_31_creb, "setnbc 31_creb", "RT,BI"}, /* bcwp */ + { &test_setnbc_31_crob, "setnbc 31_crob", "RT,BI"}, /* bcwp */ { NULL, NULL }, }; diff --git a/none/tests/ppc64/test_isa_3_1_RT.stdout.exp b/none/tests/ppc64/test_isa_3_1_RT.stdout.exp index f182d1524b..bc7a6e5553 100644 --- a/none/tests/ppc64/test_isa_3_1_RT.stdout.exp +++ b/none/tests/ppc64/test_isa_3_1_RT.stdout.exp @@ -166,4 +166,164 @@ pstw off16 (&buffer) 102030405060708 => [ - - 7ff0000005060708 - - - - pstw off32 (&buffer) 102030405060708 => [ - - - - 5a05a05a05060708 - - - ] -All done. Tested 64 different instruction groups +setbcr 0_cr0s => [00000000] 1 + +setbcr 0_cr1s => [ffffffff] 0 + +setbcr 0_creb => [aaaaaaaa] 0 + +setbcr 0_crob => [55555555] 1 + +setbcr 3_cr0s => [00000000] 1 + +setbcr 3_cr1s => [ffffffff] 0 + +setbcr 3_creb => [aaaaaaaa] 1 + +setbcr 3_crob => [55555555] 0 + +setbcr 7_cr0s => [00000000] 1 + +setbcr 7_cr1s => [ffffffff] 0 + +setbcr 7_creb => [aaaaaaaa] 1 + +setbcr 7_crob => [55555555] 0 + +setbcr 8_cr0s => [00000000] 1 + +setbcr 8_cr1s => [ffffffff] 0 + +setbcr 8_creb => [aaaaaaaa] 0 + +setbcr 8_crob => [55555555] 1 + +setbcr 31_cr0s => [00000000] 1 + +setbcr 31_cr1s => [ffffffff] 0 + +setbcr 31_creb => [aaaaaaaa] 1 + +setbcr 31_crob => [55555555] 0 + +setbc 0_cr0s => [00000000] 0 + +setbc 0_cr1s => [ffffffff] 1 + +setbc 0_creb => [aaaaaaaa] 1 + +setbc 0_crob => [55555555] 0 + +setbc 3_cr0s => [00000000] 0 + +setbc 3_cr1s => [ffffffff] 1 + +setbc 3_creb => [aaaaaaaa] 0 + +setbc 3_crob => [55555555] 1 + +setbc 7_cr0s => [00000000] 0 + +setbc 7_cr1s => [ffffffff] 1 + +setbc 7_creb => [aaaaaaaa] 0 + +setbc 7_crob => [55555555] 1 + +setbc 8_cr0s => [00000000] 0 + +setbc 8_cr1s => [ffffffff] 1 + +setbc 8_creb => [aaaaaaaa] 1 + +setbc 8_crob => [55555555] 0 + +setbc 31_cr0s => [00000000] 0 + +setbc 31_cr1s => [ffffffff] 1 + +setbc 31_creb => [aaaaaaaa] 0 + +setbc 31_crob => [55555555] 1 + +setnbcr 0_cr0s => [00000000] ffffffffffffffff + +setnbcr 0_cr1s => [ffffffff] 0 + +setnbcr 0_creb => [aaaaaaaa] 0 + +setnbcr 0_crob => [55555555] ffffffffffffffff + +setnbcr 3_cr0s => [00000000] ffffffffffffffff + +setnbcr 3_cr1s => [ffffffff] 0 + +setnbcr 3_creb => [aaaaaaaa] ffffffffffffffff + +setnbcr 3_crob => [55555555] 0 + +setnbcr 7_cr0s => [00000000] ffffffffffffffff + +setnbcr 7_cr1s => [ffffffff] 0 + +setnbcr 7_creb => [aaaaaaaa] ffffffffffffffff + +setnbcr 7_crob => [55555555] 0 + +setnbcr 8_cr0s => [00000000] ffffffffffffffff + +setnbcr 8_cr1s => [ffffffff] 0 + +setnbcr 8_creb => [aaaaaaaa] 0 + +setnbcr 8_crob => [55555555] ffffffffffffffff + +setnbcr 31_cr0s => [00000000] ffffffffffffffff + +setnbcr 31_cr1s => [ffffffff] 0 + +setnbcr 31_creb => [aaaaaaaa] ffffffffffffffff + +setnbcr 31_crob => [55555555] 0 + +setnbc 0_cr0s => [00000000] 0 + +setnbc 0_cr1s => [ffffffff] ffffffffffffffff + +setnbc 0_creb => [aaaaaaaa] ffffffffffffffff + +setnbc 0_crob => [55555555] 0 + +setnbc 3_cr0s => [00000000] 0 + +setnbc 3_cr1s => [ffffffff] ffffffffffffffff + +setnbc 3_creb => [aaaaaaaa] 0 + +setnbc 3_crob => [55555555] ffffffffffffffff + +setnbc 7_cr0s => [00000000] 0 + +setnbc 7_cr1s => [ffffffff] ffffffffffffffff + +setnbc 7_creb => [aaaaaaaa] 0 + +setnbc 7_crob => [55555555] ffffffffffffffff + +setnbc 8_cr0s => [00000000] 0 + +setnbc 8_cr1s => [ffffffff] ffffffffffffffff + +setnbc 8_creb => [aaaaaaaa] ffffffffffffffff + +setnbc 8_crob => [55555555] 0 + +setnbc 31_cr0s => [00000000] 0 + +setnbc 31_cr1s => [ffffffff] ffffffffffffffff + +setnbc 31_creb => [aaaaaaaa] 0 + +setnbc 31_crob => [55555555] ffffffffffffffff + +All done. Tested 144 different instruction groups |
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From: Carl L. <ca...@so...> - 2020-10-07 16:35:13
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ba7b3343619b72d1b963926f0b89c25fca3d360f commit ba7b3343619b72d1b963926f0b89c25fca3d360f Author: Carl Love <ce...@us...> Date: Tue Oct 6 11:41:04 2020 -0500 Add byte reverse tests ; cleanups to foundation patch. Diff: --- configure.ac | 2 +- none/tests/ppc64/Makefile.am | 2 + none/tests/ppc64/isa_3_1_helpers.h | 8 +- none/tests/ppc64/isa_3_1_register_defines.h | 11 +- none/tests/ppc64/test_isa_3_1_RT.c | 27 +- none/tests/ppc64/test_isa_3_1_RT.stdout.exp | 23 +- none/tests/ppc64/test_isa_3_1_XT.c | 15 +- none/tests/ppc64/test_isa_3_1_XT.stdout.exp | 72 ++-- none/tests/ppc64/test_isa_3_1_common.c | 536 +++++++++++++++++----------- 9 files changed, 431 insertions(+), 265 deletions(-) diff --git a/configure.ac b/configure.ac index 085c98993e..42b2a71448 100755 --- a/configure.ac +++ b/configure.ac @@ -1455,7 +1455,7 @@ AC_HWCAP_CONTAINS_FLAG([arch_2_05],[HWCAP_HAS_ISA_2_05]) AC_HWCAP_CONTAINS_FLAG([arch_2_06],[HWCAP_HAS_ISA_2_06]) AC_HWCAP_CONTAINS_FLAG([arch_2_07],[HWCAP_HAS_ISA_2_07]) AC_HWCAP_CONTAINS_FLAG([arch_3_00],[HWCAP_HAS_ISA_3_00]) -AC_HWCAP_CONTAINS_FLAG([arch_3_01],[HWCAP_HAS_ISA_3_1]) +AC_HWCAP_CONTAINS_FLAG([arch_3_1],[HWCAP_HAS_ISA_3_1]) AC_HWCAP_CONTAINS_FLAG([htm],[HWCAP_HAS_HTM]) AC_HWCAP_CONTAINS_FLAG([mma],[HWCAP_HAS_MMA]) diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index 11f0a541f0..4ca4ffc86c 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -187,6 +187,8 @@ test_isa_3_0_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $ test_isa_3_1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_3_1_FLAG) \ @FLAG_M64@ $(BUILD_FLAGS_ISA_3_1) +test_isa_3_1_RT_CFLAGS = $(test_isa_3_1_CFLAGS) +test_isa_3_1_XT_CFLAGS = $(test_isa_3_1_CFLAGS) subnormal_test_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) $(ISA_2_06_FLAG) \ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX) $(BUILD_FLAGS_ISA_2_06) diff --git a/none/tests/ppc64/isa_3_1_helpers.h b/none/tests/ppc64/isa_3_1_helpers.h index dfc0422cbc..338f55526d 100644 --- a/none/tests/ppc64/isa_3_1_helpers.h +++ b/none/tests/ppc64/isa_3_1_helpers.h @@ -5,12 +5,10 @@ extern unsigned long a_iters,b_iters,c_iters, m_iters; extern unsigned long vrai,vrbi,vrci,vrmi; extern unsigned long a_inc, b_inc, c_inc, m_inc; +extern unsigned long a_start, b_start, c_start, m_start; extern unsigned long a_limit,b_limit,c_limit; extern vector unsigned long long vrt, vra, vrb, vrc; extern vector unsigned long long vrm; -extern vector unsigned long long vec_xa; -extern vector unsigned long long vec_xb; -extern vector unsigned long long vec_xc; extern vector unsigned long long vec_xs; extern vector unsigned long long vec_xt; extern unsigned long long dcmx; @@ -64,9 +62,11 @@ extern int verbose; #define debug_printf(X) if (verbose>0) printf(X); #define debug_show_labels (verbose>0) #define debug_show_iters (verbose>1) -#define debug_show_raw_values (verbose>2) +#define debug_show_values (verbose>2) #define debug_show_all_regs (verbose>5) #define debug_show_tables (verbose>6) +#define debug_show_raw_values (verbose>7) +#define debug_enable_all_iters (verbose>8) #define CHECK_OVERRIDES { \ diff --git a/none/tests/ppc64/isa_3_1_register_defines.h b/none/tests/ppc64/isa_3_1_register_defines.h index e4d021e5c0..a8c08f5910 100644 --- a/none/tests/ppc64/isa_3_1_register_defines.h +++ b/none/tests/ppc64/isa_3_1_register_defines.h @@ -15,16 +15,15 @@ register vector long long TEST_ACC2 __asm__ ("vs18"); register vector long long TEST_ACC3 __asm__ ("vs19"); /* XSp and XTp use the same register pair, defined here as 20 and 21. - { also XSp,XTp in scripts } */ + This includes the XT and XS values too. */ register vector long long XTp0 __asm__ ("vs20"); // XTp[0];XSp[0]; register vector long long XTp1 __asm__ ("vs21"); // XTp[1];XSp[1]; // xa,xb,xc references are mapped to a specific vector register. -// out of order to allow xap mapped over xa and xc. -register vector long long xa __asm__ ("vs22"); // also xap. -register vector long long xc __asm__ ("vs23"); // also 2nd half of xap. -register vector long long xb __asm__ ("vs24"); -register vector long long xt __asm__ ("vs25"); +// out of order to allow xap mapped over vec_xa and vec_xc. +register vector long long vec_xa __asm__ ("vs22"); // also xap. +register vector long long vec_xc __asm__ ("vs23"); // also 2nd half of xap. +register vector long long vec_xb __asm__ ("vs24"); /* frs,frb (variable named frsb) both use the same register pair. (top half of vs26,vs27) */ diff --git a/none/tests/ppc64/test_isa_3_1_RT.c b/none/tests/ppc64/test_isa_3_1_RT.c index 46c109b256..a6e55f9210 100644 --- a/none/tests/ppc64/test_isa_3_1_RT.c +++ b/none/tests/ppc64/test_isa_3_1_RT.c @@ -24,11 +24,13 @@ */ #include <stdio.h> +#ifdef HAS_ISA_3_1 #include <stdint.h> #include <assert.h> #include <stdlib.h> #include <string.h> #include <unistd.h> +#include <altivec.h> #include <malloc.h> #include <string.h> @@ -43,13 +45,19 @@ unsigned long current_cr; unsigned long current_fpscr; -#ifdef HAS_ISA_3_1 +struct test_list_t current_test; -#include <altivec.h> #include "isa_3_1_helpers.h" -struct test_list_t current_test; - +static void test_brh (void) { + __asm__ __volatile__ ("brh %0, %1" : "=r" (ra) : "r" (rs) ); +} +static void test_brw (void) { + __asm__ __volatile__ ("brw %0, %1" : "=r" (ra) : "r" (rs) ); +} +static void test_brd (void) { + __asm__ __volatile__ ("brd %0, %1" : "=r" (ra) : "r" (rs) ); +} static void test_plbz_off0 (void) { __asm__ __volatile__ ("plbz %0, 0(%1), 0" : "=r" (rt) : "r" (ra) ); } @@ -235,6 +243,9 @@ static void test_pstq_off64 (void) { } static test_list_t testgroup_generic[] = { + { &test_brd, "brd", "RA,RS"}, /* bcs */ + { &test_brh, "brh", "RA,RS"}, /* bcs */ + { &test_brw, "brw", "RA,RS"}, /* bcs */ { &test_paddi_0, "paddi 0", "RT,RA,SI,R"}, /* bcwp */ { &test_paddi_12, "paddi 12", "RT,RA,SI,R"}, /* bcwp */ { &test_paddi_48, "paddi 48", "RT,RA,SI,R"}, /* bcwp */ @@ -322,10 +333,10 @@ static void testfunction_generic (const char* instruction_name, initialize_buffer (0); debug_dump_buffer (); - for (vrai = 0; vrai < a_iters ; vrai+=a_inc) { - for (vrbi = 0; vrbi < b_iters ; vrbi+=b_inc) { - for (vrci = 0; vrci < c_iters ; vrci+=c_inc) { - for (vrmi = 0; (vrmi < m_iters) ; vrmi+=m_inc) { + for (vrai = a_start; vrai < a_iters ; vrai+=a_inc) { + for (vrbi = b_start; vrbi < b_iters ; vrbi+=b_inc) { + for (vrci = c_start; vrci < c_iters ; vrci+=c_inc) { + for (vrmi = m_start; (vrmi < m_iters) ; vrmi+=m_inc) { CHECK_OVERRIDES debug_show_current_iteration (); // Be sure to initialize the target registers first. diff --git a/none/tests/ppc64/test_isa_3_1_RT.stdout.exp b/none/tests/ppc64/test_isa_3_1_RT.stdout.exp index 4ebe7e162a..f182d1524b 100644 --- a/none/tests/ppc64/test_isa_3_1_RT.stdout.exp +++ b/none/tests/ppc64/test_isa_3_1_RT.stdout.exp @@ -1,3 +1,24 @@ +brd 102030405060708 => 807060504030201 +brd a5b4c3d2e1f00918 => 1809f0e1d2c3b4a5 +brd fff7fffafff3fff1 => f1fff3fffafff7ff +brd 7ff7000100030005 => 50003000100f77f +brd ffe7111022203330 => 303320221011e7ff +brd 0 => 0 + +brh 102030405060708 => 201040306050807 +brh a5b4c3d2e1f00918 => b4a5d2c3f0e11809 +brh fff7fffafff3fff1 => f7fffafff3fff1ff +brh 7ff7000100030005 => f77f010003000500 +brh ffe7111022203330 => e7ff101120223033 +brh 0 => 0 + +brw 102030405060708 => 403020108070605 +brw a5b4c3d2e1f00918 => d2c3b4a51809f0e1 +brw fff7fffafff3fff1 => fafff7fff1fff3ff +brw 7ff7000100030005 => 100f77f05000300 +brw ffe7111022203330 => 1011e7ff30332022 +brw 0 => 0 + paddi 0 102030405060708 => 102030405060708 paddi 0 a5b4c3d2e1f00918 => a5b4c3d2e1f00918 paddi 0 fff7fffafff3fff1 => fff7fffafff3fff1 @@ -145,4 +166,4 @@ pstw off16 (&buffer) 102030405060708 => [ - - 7ff0000005060708 - - - - pstw off32 (&buffer) 102030405060708 => [ - - - - 5a05a05a05060708 - - - ] -All done. Tested 61 different instruction groups +All done. Tested 64 different instruction groups diff --git a/none/tests/ppc64/test_isa_3_1_XT.c b/none/tests/ppc64/test_isa_3_1_XT.c index b644ba1cab..de75953d24 100644 --- a/none/tests/ppc64/test_isa_3_1_XT.c +++ b/none/tests/ppc64/test_isa_3_1_XT.c @@ -24,11 +24,13 @@ */ #include <stdio.h> +#ifdef HAS_ISA_3_1 #include <stdint.h> #include <assert.h> #include <stdlib.h> #include <string.h> #include <unistd.h> +#include <altivec.h> #include <malloc.h> #include <string.h> @@ -43,13 +45,10 @@ unsigned long current_cr; unsigned long current_fpscr; -#ifdef HAS_ISA_3_1 +struct test_list_t current_test; -#include <altivec.h> #include "isa_3_1_helpers.h" -struct test_list_t current_test; - static void test_plfd_64 (void) { __asm__ __volatile__ ("plfd 28, 64(%0), 0" :: "r" (ra) ); } @@ -294,10 +293,10 @@ static void testfunction_generic (const char* instruction_name, initialize_buffer (0); debug_dump_buffer (); - for (vrai = 0; vrai < a_iters ; vrai+=a_inc) { - for (vrbi = 0; vrbi < b_iters ; vrbi+=b_inc) { - for (vrci = 0; vrci < c_iters ; vrci+=c_inc) { - for (vrmi = 0; (vrmi < m_iters) ; vrmi+=m_inc) { + for (vrai = a_start; vrai < a_iters ; vrai+=a_inc) { + for (vrbi = b_start; vrbi < b_iters ; vrbi+=b_inc) { + for (vrci = c_start; vrci < c_iters ; vrci+=c_inc) { + for (vrmi = m_start; (vrmi < m_iters) ; vrmi+=m_inc) { CHECK_OVERRIDES debug_show_current_iteration (); // Be sure to initialize the target registers first. diff --git a/none/tests/ppc64/test_isa_3_1_XT.stdout.exp b/none/tests/ppc64/test_isa_3_1_XT.stdout.exp index aec8e1270e..2132cf1409 100644 --- a/none/tests/ppc64/test_isa_3_1_XT.stdout.exp +++ b/none/tests/ppc64/test_isa_3_1_XT.stdout.exp @@ -22,29 +22,29 @@ plfs 32 (&buffer) => 1.509115e-35 plfs 64 (&buffer) => -5.202476e-03 -plxsd 0 (&buffer) => 3fe00094e0007359,0000000000000000 5.00070989e-01 +Zero +plxsd 0 (&buffer) => 3fe00094e0007359,0000000000000000 5.00070989e-01 +Zero -plxsd 4 (&buffer) => 40576073fe00094,0000000000000000 2.75273943e-289 +Zero +plxsd 4 (&buffer) => 40576073fe00094,0000000000000000 2.75273943e-289 +Zero -plxsd 8 (&buffer) => 7ff7020304057607,0000000000000000 NaN +Zero +plxsd 8 (&buffer) => 7ff7020304057607,0000000000000000 NaN +Zero -plxsd 16 (&buffer) => 7ff0000000007000,0000000000000000 NaN +Zero +plxsd 16 (&buffer) => 7ff0000000007000,0000000000000000 NaN +Zero -plxsd 32 (&buffer) => 5a05a05a05a07a05,0000000000000000 4.57479788e+125 +Zero +plxsd 32 (&buffer) => 5a05a05a05a07a05,0000000000000000 4.57479788e+125 +Zero -plxsd 64 (&buffer) => ffeeddccbbaa7988,0000000000000000 -1.73401015e+308 +Zero +plxsd 64 (&buffer) => ffeeddccbbaa7988,0000000000000000 -1.73401015e+308 +Zero -plxssp 0 (&buffer) => c4000e6b20000000,0000000000000000 -5.12225e+02 1.08420e-19 +Zero +Zero +plxssp 0 (&buffer) => c4000e6b20000000,0000000000000000 -5.12225e+02 1.08420e-19 +Zero +Zero -plxssp 4 (&buffer) => 3ffc001280000000,0000000000000000 1.96875e+00 -Zero +Zero +Zero +plxssp 4 (&buffer) => 3ffc001280000000,0000000000000000 1.96875e+00 -Zero +Zero +Zero -plxssp 8 (&buffer) => 3880aec0e0000000,0000000000000000 6.13607e-05 -3.68935e+19 +Zero +Zero +plxssp 8 (&buffer) => 3880aec0e0000000,0000000000000000 6.13607e-05 -3.68935e+19 +Zero +Zero -plxssp 16 (&buffer) => 378c000000000000,0000000000000000 1.66893e-05 +Zero +Zero +Zero +plxssp 16 (&buffer) => 378c000000000000,0000000000000000 1.66893e-05 +Zero +Zero +Zero -plxssp 32 (&buffer) => 38b40f40a0000000,0000000000000000 8.58591e-05 -1.08420e-19 +Zero +Zero +plxssp 32 (&buffer) => 38b40f40a0000000,0000000000000000 8.58591e-05 -1.08420e-19 +Zero +Zero -plxssp 64 (&buffer) => bf754f3100000000,0000000000000000 -9.58240e-01 +Zero +Zero +Zero +plxssp 64 (&buffer) => bf754f3100000000,0000000000000000 -9.58240e-01 +Zero +Zero +Zero plxv 0_0 (&buffer) => 3fe00094e0007359 7ff7020304057607 @@ -54,35 +54,35 @@ plxv 8_0 (&buffer) => 7ff7020304057607 7ff0000000007000 plxv 16_0 (&buffer) => 7ff0000000007000 7f0000007f007000 -pstfd 0 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ { 9.18734324e+18} 43dfe000003fe000 - - - - - - - ] -pstfd 0 (&buffer) 43eff000000ff000 43efefffffcff000 => [ { 1.84107153e+19} 43eff000000ff000 - - - - - - - ] +pstfd 0 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ { 9.18734324e+18} 43dfe000003fe000 - - - - - - - ] +pstfd 0 (&buffer) 43eff000000ff000 43efefffffcff000 => [ { 1.84107153e+19} 43eff000000ff000 - - - - - - - ] -pstfd 4 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ { 1.77310647e-307} 003fe000e0007359 { NaN} 7ff7020343dfe000 - - - - - - ] -pstfd 4 (&buffer) 43eff000000ff000 43efefffffcff000 => [ { +Den} 000ff000e0007359 { NaN} 7ff7020343eff000 - - - - - - ] +pstfd 4 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ { 1.77310647e-307} 003fe000e0007359 { NaN} 7ff7020343dfe000 - - - - - - ] +pstfd 4 (&buffer) 43eff000000ff000 43efefffffcff000 => [ { +Den} 000ff000e0007359 { NaN} 7ff7020343eff000 - - - - - - ] -pstfd 8 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ - { 9.18734324e+18} 43dfe000003fe000 - - - - - - ] -pstfd 8 (&buffer) 43eff000000ff000 43efefffffcff000 => [ - { 1.84107153e+19} 43eff000000ff000 - - - - - - ] +pstfd 8 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ - { 9.18734324e+18} 43dfe000003fe000 - - - - - - ] +pstfd 8 (&buffer) 43eff000000ff000 43efefffffcff000 => [ - { 1.84107153e+19} 43eff000000ff000 - - - - - - ] -pstfd 16 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ - - { 9.18734324e+18} 43dfe000003fe000 - - - - - ] -pstfd 16 (&buffer) 43eff000000ff000 43efefffffcff000 => [ - - { 1.84107153e+19} 43eff000000ff000 - - - - - ] +pstfd 16 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ - - { 9.18734324e+18} 43dfe000003fe000 - - - - - ] +pstfd 16 (&buffer) 43eff000000ff000 43efefffffcff000 => [ - - { 1.84107153e+19} 43eff000000ff000 - - - - - ] -pstfd 32 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ - - - - { 9.18734324e+18} 43dfe000003fe000 - - - ] -pstfd 32 (&buffer) 43eff000000ff000 43efefffffcff000 => [ - - - - { 1.84107153e+19} 43eff000000ff000 - - - ] +pstfd 32 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ - - - - { 9.18734324e+18} 43dfe000003fe000 - - - ] +pstfd 32 (&buffer) 43eff000000ff000 43efefffffcff000 => [ - - - - { 1.84107153e+19} 43eff000000ff000 - - - ] -pstfs 0 (&buffer) 000000005eff0000 000000005f7f8000 => [ ( 1.75002e+00 9.18734e+18) 3fe000945eff0000 - - - - - - - ] -pstfs 0 (&buffer) 000000005f7f8000 000000005f7f8000 => [ ( 1.75002e+00 1.84107e+19) 3fe000945f7f8000 - - - - - - - ] +pstfs 0 (&buffer) 000000005eff0000 000000005f7f8000 => [ ( 1.75002e+00 9.18734e+18) 3fe000945eff0000 - - - - - - - ] +pstfs 0 (&buffer) 000000005f7f8000 000000005f7f8000 => [ ( 1.75002e+00 1.84107e+19) 3fe000945f7f8000 - - - - - - - ] -pstfs 4 (&buffer) 000000005eff0000 000000005f7f8000 => [ ( 9.18734e+18 -3.70234e+19) 5eff0000e0007359 - - - - - - - ] -pstfs 4 (&buffer) 000000005f7f8000 000000005f7f8000 => [ ( 1.84107e+19 -3.70234e+19) 5f7f8000e0007359 - - - - - - - ] +pstfs 4 (&buffer) 000000005eff0000 000000005f7f8000 => [ ( 9.18734e+18 -3.70234e+19) 5eff0000e0007359 - - - - - - - ] +pstfs 4 (&buffer) 000000005f7f8000 000000005f7f8000 => [ ( 1.84107e+19 -3.70234e+19) 5f7f8000e0007359 - - - - - - - ] -pstfs 8 (&buffer) 000000005eff0000 000000005f7f8000 => [ - ( NaN 9.18734e+18) 7ff702035eff0000 - - - - - - ] -pstfs 8 (&buffer) 000000005f7f8000 000000005f7f8000 => [ - ( NaN 1.84107e+19) 7ff702035f7f8000 - - - - - - ] +pstfs 8 (&buffer) 000000005eff0000 000000005f7f8000 => [ - ( NaN 9.18734e+18) 7ff702035eff0000 - - - - - - ] +pstfs 8 (&buffer) 000000005f7f8000 000000005f7f8000 => [ - ( NaN 1.84107e+19) 7ff702035f7f8000 - - - - - - ] -pstfs 16 (&buffer) 000000005eff0000 000000005f7f8000 => [ - - ( NaN 9.18734e+18) 7ff000005eff0000 - - - - - ] -pstfs 16 (&buffer) 000000005f7f8000 000000005f7f8000 => [ - - ( NaN 1.84107e+19) 7ff000005f7f8000 - - - - - ] +pstfs 16 (&buffer) 000000005eff0000 000000005f7f8000 => [ - - ( NaN 9.18734e+18) 7ff000005eff0000 - - - - - ] +pstfs 16 (&buffer) 000000005f7f8000 000000005f7f8000 => [ - - ( NaN 1.84107e+19) 7ff000005f7f8000 - - - - - ] -pstfs 32 (&buffer) 000000005eff0000 000000005f7f8000 => [ - - - - ( 9.40312e+15 9.18734e+18) 5a05a05a5eff0000 - - - ] -pstfs 32 (&buffer) 000000005f7f8000 000000005f7f8000 => [ - - - - ( 9.40312e+15 1.84107e+19) 5a05a05a5f7f8000 - - - ] +pstfs 32 (&buffer) 000000005eff0000 000000005f7f8000 => [ - - - - ( 9.40312e+15 9.18734e+18) 5a05a05a5eff0000 - - - ] +pstfs 32 (&buffer) 000000005f7f8000 000000005f7f8000 => [ - - - - ( 9.40312e+15 1.84107e+19) 5a05a05a5f7f8000 - - - ] pstxsd 0 (&buffer) => [0000000000000000 - - - - - - - ] @@ -108,12 +108,12 @@ pstxssp 32 (&buffer) => [ - - - - 5a05a05a00000000 - - - ] pstxssp 64 (&buffer) => -pstxv 0 (&buffer) 7f800000ff800000,ff8000007f800000 => [7f800000ff800000 ff8000007f800000 - - - - - - ] +pstxv 0 (&buffer) ff7ffffe7f7ffffe,ff8000007f800000 => [ff7ffffe7f7ffffe ff8000007f800000 - - - - - - ] -pstxv 4 (&buffer) 7f800000ff800000,ff8000007f800000 => [ff800000e0007359 7f8000007f800000 7ff00000ff800000 - - - - - ] +pstxv 4 (&buffer) ff7ffffe7f7ffffe,ff8000007f800000 => [7f7ffffee0007359 7f800000ff7ffffe 7ff00000ff800000 - - - - - ] -pstxv 8 (&buffer) 7f800000ff800000,ff8000007f800000 => [ - 7f800000ff800000 ff8000007f800000 - - - - - ] +pstxv 8 (&buffer) ff7ffffe7f7ffffe,ff8000007f800000 => [ - ff7ffffe7f7ffffe ff8000007f800000 - - - - - ] -pstxv 16 (&buffer) 7f800000ff800000,ff8000007f800000 => [ - - 7f800000ff800000 ff8000007f800000 - - - - ] +pstxv 16 (&buffer) ff7ffffe7f7ffffe,ff8000007f800000 => [ - - ff7ffffe7f7ffffe ff8000007f800000 - - - - ] All done. Tested 54 different instruction groups diff --git a/none/tests/ppc64/test_isa_3_1_common.c b/none/tests/ppc64/test_isa_3_1_common.c index 58f2bdcde5..8222a857fc 100644 --- a/none/tests/ppc64/test_isa_3_1_common.c +++ b/none/tests/ppc64/test_isa_3_1_common.c @@ -38,9 +38,6 @@ unsigned long post_test; int verbose = 0; #define DEADBEEF 0x1111111111111111ULL -vector unsigned long long vec_xa; -vector unsigned long long vec_xb; -vector unsigned long long vec_xc; vector unsigned long long vec_xs; vector unsigned long long vec_xt; unsigned long long dcmx; @@ -50,6 +47,7 @@ unsigned long long dcmx; */ unsigned long a_iters, b_iters, c_iters, m_iters; unsigned long a_inc, b_inc, c_inc, m_inc; +unsigned long a_start, b_start, c_start, m_start; unsigned long vrai, vrbi, vrci, vrmi; unsigned long a_limit = 0xffff, b_limit = 0xffff, c_limit = 0xffff; @@ -133,13 +131,14 @@ bool uses_acc; // Accumulator related. bool uses_acc_src; bool uses_acc_dest; bool uses_acc_vsrs; +bool uses_pmsk; bool uses_buffer; // Buffer related. bool uses_load_buffer, uses_store_buffer, uses_any_buffer; bool uses_quad; unsigned long output_mask; // Output field special handling. -bool instruction_is_sp, instruction_is_sp_estimate; -bool instruction_is_dp, instruction_is_dp_estimate; -bool instruction_is_b16; +bool instruction_is_sp, instruction_is_sp_estimate; +bool instruction_is_dp, instruction_is_dp_estimate; +bool instruction_is_b16; unsigned long long min (unsigned long long a, unsigned long long b) { if ( a < b ) @@ -176,7 +175,7 @@ void identify_form_components (const char *instruction_name, has_frtp = strstr (cur_form, "FRTp") != NULL; has_xa = strstr (cur_form, ",XA") != NULL; - has_xap = strstr (cur_form, ",XAp") != NULL; + has_xap = strstr (cur_form, "XAp") != NULL; has_xb = strstr (cur_form, ",XB") != NULL; has_xc = strstr (cur_form, ",XC") != NULL; has_xs = (strncmp (cur_form, "XS", 2) == 0); @@ -193,6 +192,7 @@ void identify_form_components (const char *instruction_name, (strstr (instruction_name, "xxmfacc") != NULL) || (strstr (instruction_name, "xxmtacc") != NULL) ); uses_acc = uses_acc_src || uses_acc_dest || uses_acc_vsrs; + uses_pmsk = strstr (cur_form, "PMSK") !=NULL; uses_dfp128_input = ( (strncmp (instruction_name, "dctf", 4) == 0)); @@ -335,6 +335,8 @@ void display_form_components (char * cur_form) { if (uses_acc) printf ("Instruction uses ACC: (src:%d, dst:%d, vsrs:%d).\n", uses_acc_src, uses_acc_dest, uses_acc_vsrs); + if (uses_pmsk) + printf ("Instruction uses PMSK \n"); if (output_mask) { printf ("Instruction results are masked: "); printf (" (%lx) ", output_mask); @@ -417,18 +419,20 @@ void generic_print_double_as_hex (double d) { digits as seen below. */ // NAN - Maximum biased exponent and a nonzero mantissa (fraction). -#define PRINT_SP_NAN printf (" NaN"); +#define SPFMT "%16s" +#define PRINT_SP_NAN printf (SPFMT,"NaN"); // DEN - Exp == 0 and Frac != 0 -#define PRINT_SP_PLUS_DEN printf (" +Den"); -#define PRINT_SP_MINUS_DEN printf (" -Den"); +#define PRINT_SP_PLUS_DEN printf (SPFMT,"+Den"); +#define PRINT_SP_MINUS_DEN printf (SPFMT,"-Den"); // INF - Maximum biased exponent and a zero mantissa. -#define PRINT_SP_INF printf (" Inf"); -#define PRINT_SP_PLUS_INF printf (" +Inf"); -#define PRINT_SP_MINUS_INF printf (" -Inf"); -#define PRINT_SP_FLOAT(x) printf ("%13.05e", x); -#define PRINT_SP_FLOAT_EST(x) printf ("%13.03e", x); -#define PRINT_SP_FLOAT_PLUS_ZERO printf (" +Zero"); -#define PRINT_SP_FLOAT_MINUS_ZERO printf (" -Zero"); +#define PRINT_SP_INF printf (SPFMT,"Inf"); +#define PRINT_SP_PLUS_INF printf (SPFMT,"+Inf"); +#define PRINT_SP_MINUS_INF printf (SPFMT,"-Inf"); +#define PRINT_SP_FLOAT(x) printf ("%16.05e", x); +#define PRINT_SP_FLOAT_EST(x) printf ("%16.03e", x); +#define PRINT_SP_FLOAT_PLUS_ZERO printf (SPFMT,"+Zero"); +#define PRINT_SP_FLOAT_MINUS_ZERO printf (SPFMT,"-Zero"); +#define PRINT_SP_SPLAT printf (SPFMT,"*"); /* Print a SINGLE (16 bit) SP value out of the left part of a 32-bit field. */ void special_print_sp_value (uint32_t value) { @@ -486,16 +490,18 @@ void dissect_sp_value (unsigned long long foo) { } /* Print one DP values out of our vec_ field. */ -#define PRINT_DP_NAN printf (" NaN"); -#define PRINT_DP_MINUS_DEN printf (" -Den"); -#define PRINT_DP_PLUS_DEN printf (" +Den"); -#define PRINT_DP_MINUS_INF printf (" -Inf"); -#define PRINT_DP_PLUS_INF printf (" +InF"); -#define PRINT_DP_FLOAT(x) printf (" %15.08e", x); -#define PRINT_DP_FLOAT_EST(x) printf (" %15.02e", x); -#define PRINT_DP_FLOAT_PLUS_ZERO printf (" +Zero"); -#define PRINT_DP_FLOAT_MINUS_ZERO printf (" -Zero"); -#define PRINT_DP_FLOAT_ZERO printf (" 0.000000e+000"); +#define DPFMT "%17s" +#define PRINT_DP_NAN printf (DPFMT,"NaN"); +#define PRINT_DP_MINUS_DEN printf (DPFMT,"-Den"); +#define PRINT_DP_PLUS_DEN printf (DPFMT,"+Den"); +#define PRINT_DP_MINUS_INF printf (DPFMT,"-Inf"); +#define PRINT_DP_PLUS_INF printf (DPFMT,"+InF"); +#define PRINT_DP_FLOAT(x) printf ("%17.08e", x); +#define PRINT_DP_FLOAT_EST(x) printf ("%17.02e", x); +#define PRINT_DP_FLOAT_PLUS_ZERO printf (DPFMT,"+Zero"); +#define PRINT_DP_FLOAT_MINUS_ZERO printf (DPFMT,"-Zero"); +#define PRINT_DP_FLOAT_ZERO printf (DPFMT,"0.000000e+000"); +#define PRINT_DP_SPLAT printf (DPFMT,"*"); void special_print_dp_value (unsigned long long value) { unsigned long long signbit; unsigned long long exponent; @@ -506,7 +512,7 @@ void special_print_dp_value (unsigned long long value) { signbit = (value & DP_SIGNBIT_MASK) > 0; exponent = value & DP_EXPONENT_MASK; // >> double_exponent_shift; fraction = value & DP_FRACTION_MASK; - if (verbose>2) + if (debug_show_raw_values) printf ("\ndb_debug: %16llx s:%d %3llx %8llx %llx , ", value, signbit?1:0, exponent, fraction, stone.ull); if (exponent == DP_EXPONENT_MASK /* MAX */ && fraction == 0 ) { @@ -549,17 +555,18 @@ void dissect_dp_value (unsigned long long foo) { } // NAN - Maximum biased exponent and a nonzero mantissa (fraction). -#define PRINT_BF16_NAN printf (" NaN"); +#define BFFMT "%6s" +#define PRINT_BF16_NAN printf (BFFMT,"NaN"); // DEN - Exp == 0 and Frac != 0 -#define PRINT_BF16_PLUS_DEN printf (" +Den"); -#define PRINT_BF16_MINUS_DEN printf (" -Den"); +#define PRINT_BF16_PLUS_DEN printf (BFFMT,"+Den"); +#define PRINT_BF16_MINUS_DEN printf (BFFMT,"-Den"); // INF - Maximum biased exponent and a zero mantissa. -#define PRINT_BF16_INF printf (" Inf"); -#define PRINT_BF16_PLUS_INF printf (" +Inf"); -#define PRINT_BF16_MINUS_INF printf (" -Inf"); -#define PRINT_BF16_FLOAT(x) printf (" 0x%04x", x); -#define PRINT_BF16_FLOAT_PLUS_ZERO printf (" +Zero"); -#define PRINT_BF16_FLOAT_MINUS_ZERO printf (" -Zero"); +#define PRINT_BF16_INF printf (BFFMT,"Inf"); +#define PRINT_BF16_PLUS_INF printf (BFFMT,"+Inf"); +#define PRINT_BF16_MINUS_INF printf (BFFMT,"-Inf"); +#define PRINT_BF16_FLOAT(x) printf ("0x%04x", x); +#define PRINT_BF16_FLOAT_PLUS_ZERO printf (BFFMT,"+Zero"); +#define PRINT_BF16_FLOAT_MINUS_ZERO printf (BFFMT,"-Zero"); /* print a single bfloat16 value. */ void special_print_bf16_value (uint16_t value) { int signbit; @@ -573,7 +580,7 @@ void special_print_bf16_value (uint16_t value) { if (debug_show_raw_values) { printf ("\nbf16_debug: v:%08x s: %d %3x %8llx %f , ", value, signbit?1:0, exponent, fraction, stone.flt); - } else if (verbose > 0) { + } else if (debug_show_values) { printf (" v:%08x", value); } if (exponent == BF16_EXPONENT_MASK && fraction == 0 ) { @@ -614,9 +621,10 @@ void push_acc_to_vsrs () { void __print_splat_or_sp(long long vv) { - if (vv == DEADBEEF) - printf (" * "); - else { + if (vv == DEADBEEF) { + PRINT_SP_SPLAT + PRINT_SP_SPLAT + } else { special_print_sp_value (0xffffffff & (vv>>32)); special_print_sp_value (0xffffffff & (vv)); } @@ -624,7 +632,7 @@ void __print_splat_or_sp(long long vv) { void __print_splat_or_dp(long long vv) { if (vv == DEADBEEF) - printf (" * "); + PRINT_DP_SPLAT else { special_print_dp_value (vv); } @@ -632,9 +640,9 @@ void __print_splat_or_dp(long long vv) { void __print_splat_or_raw(long long vv) { if (vv == DEADBEEF) - printf (" * "); + printf (" %16s", "*"); else - printf ("%llx ", vv); + printf (" %016llx", vv); } void print_accumulator () { @@ -870,7 +878,7 @@ void dissect_fpscr_raw (unsigned long local_fpscr) { } void dissect_fpscr (unsigned long local_fpscr) { - if (verbose > 2) { + if (debug_show_values) { printf (" [[ fpscr:%lx ]] ", local_fpscr); dissect_fpscr_raw (local_fpscr); } else { @@ -925,16 +933,16 @@ void dump_changed_buffer (unsigned long range) { if (buffer[x] !=reference_buffer[x]) { buffer_changed = 1; changed_index[x] = 1; - if (verbose>2) + if (debug_show_values) printf (" {idx %d %016llx %016llx}", x, reference_buffer[x] , buffer[x] ); } } - if (verbose>2 || buffer_changed) { + if (debug_show_values || buffer_changed) { printf (" ["); for (x = 0; x < BUFFER_SIZE && (x<range); x++) { if (x) printf (" "); - if (verbose > 0) + if (verbose) printf ("%s%016llx", changed_index[x] == 1?"*":" ", buffer[x] ); if (changed_index[x]) { if (instruction_is_sp) { @@ -975,7 +983,7 @@ void dump_large_buffer (void) { } void dump_buffer () { -if (verbose>1) printf (" buffer:"); +if (debug_show_values) printf (" buffer:"); if (uses_quad) { dump_large_buffer (); } else { @@ -984,7 +992,7 @@ if (verbose>1) printf (" buffer:"); } void print_undefined () { - if (verbose>1) + if (debug_show_values) printf (" [Undef]"); else printf (" "); @@ -1062,7 +1070,7 @@ int get_declet (int start, uint64_t dword1, uint64_t dword0) { dword1_shift = 63 - (start + 9); dword0_shift = 127 - (start + 9); - if (verbose>5) printf ("\n%s (%d) %016lx %016lx", + if (debug_show_all_regs) printf ("\n%s (%d) %016lx %016lx", __FUNCTION__, start, dword1, dword0); if ( (start + 9) < 63) { /* fully within dword1 */ @@ -1352,8 +1360,10 @@ void print_frt () { void print_frs_or_frb () { unsigned long long vsrvalue1, vsrvalue3; if (debug_show_labels) { - if (has_frs) printf (" frs%s:", has_frsp?"p":"" ); - if (has_frb) printf (" frb%s:", has_frbp?"p":"" ); + printf (" fr" ); + if (has_frs) printf ("s%s:", has_frsp?"p":"" ); + else if (has_frb) printf ("b%s:", has_frbp?"p":"" ); + else printf("?"); } if (uses_dfp128_input) { if (verbose) print_vsr (26); @@ -1396,6 +1406,17 @@ void print_rc () { } void print_rs () { + if (debug_show_labels) printf (" rs:"); + printf (" %lx", rs); +} + +// Second half of a rs pair. +void print_rsp () { + if (debug_show_labels) printf (" rsp:"); + printf (" %lx", rsp); +} + +void print_rs_or_rsp () { if (debug_show_labels) printf (" rs:"); printf (" %lx", rs); if (has_rsp) { @@ -1414,35 +1435,35 @@ void print_rt () { void print_vra () { if (debug_show_labels) printf (" vra:"); - printf (" %016lx,%016lx", vra[0], vra[1]); + printf (" %016llx,%016llx", vra[0], vra[1]); } void print_vrb () { if (debug_show_labels) printf (" vrb:"); - printf (" %016lx,%016lx", vrb[0], vrb[1]); + printf (" %016llx,%016llx", vrb[0], vrb[1]); } void print_vrc () { if (debug_show_labels) printf (" vrc:"); - printf (" %016lx,%016lx", vrc[0], vrc[1]); + printf (" %016llx,%016llx", vrc[0], vrc[1]); } /* for VRM, don't print leading zeros for better visibility of diffs */ void print_vrm () { if (debug_show_labels) printf (" vrm:"); - printf (" %16lx,%16lx", vrm[0], vrm[1]); + printf (" %16llx,%16llx", vrm[0], vrm[1]); } void print_vrt () { if (debug_show_labels) printf (" vrt:"); if (debug_show_raw_values || (output_mask && uses_load_buffer )) { - printf (" %16lx,", vrt[1]); - printf ( "%016lx", vrt[0]); + printf (" %16llx,", vrt[1]); + printf ( "%016llx", vrt[0]); } if (!post_test) return; if (!output_mask) { - printf (" %16lx,", vrt[1]); - printf ("%016lx", vrt[0]); + printf (" %16llx,", vrt[1]); + printf ("%016llx", vrt[0]); } else { /* there is a mask requiring special handling. */ if (instruction_is_dp) { @@ -1464,70 +1485,69 @@ void print_vrt () { } } -void print_xa_or_xc () { - if (has_xa) { - if (debug_show_labels) printf (" vec_xa:"); - printf (" %016lx,", vec_xa[0] ); - printf ("%016lx", vec_xa[1] ); - } - if (has_xc | has_xap) { // Note that xap is shared with xc. - if (debug_show_labels) printf (" vec_x%s", has_xc?"c":"ap"); - printf (" %016lx,", vec_xc[0] ); - printf ("%016lx", vec_xc[1] ); - } +void print_xtp () { +if (debug_show_labels) printf (" vec_x[st]p:" ); + printf (" %016llx", XTp0[0]); + printf (" %016llx", XTp0[1]); + printf (" %016llx", XTp1[0]); + printf (" %016llx", XTp1[1]); +} + +void print_xsp () { + print_xtp(); +} + +void print_xa() { + if (debug_show_labels) printf (" xa:"); + printf (" %016llx,", vec_xa[0] ); + printf ("%016llx", vec_xa[1] ); +} + +/* xc may also hold the second half of an xa pair */ +void print_xc() { + if (debug_show_labels) printf (" xc:"); + printf (" %016llx,", vec_xc[0] ); + printf ("%016llx", vec_xc[1] ); +} + +/* xap is the pair at rs22 (xa) and rs23 (xc). */ +void print_xap() { + if (debug_show_labels) printf (" xap:"); + print_xa(); + print_xc(); } void print_xb () { - if (debug_show_labels) printf (" vec_xb:"); + if (debug_show_labels) printf (" xb:"); if (instruction_is_sp_estimate) { print_vec_as_sp (vec_xb[0]); printf (","); print_vec_as_sp (vec_xb[1]); } else { - printf (" %016lx,", vec_xb[0] ); - printf ("%016lx", vec_xb[1] ); + printf (" %016llx,", vec_xb[0] ); + printf ("%016llx", vec_xb[1] ); } } void print_xs () { if (debug_show_labels) printf (" vec_xs:"); - printf (" %016lx,", vec_xs[0] ); - printf ("%016lx", vec_xs[1] ); -} - -//fixme - consolidate this with print_xt variation. -void print_xtp () { -if (debug_show_labels) printf (" vec_xtp:" ); - printf (" %16lx", XTp0[0]); - printf (" %16lx", XTp0[1]); - printf (" %16lx", XTp1[0]); - printf (" %16lx", XTp1[1]); -} - -void print_xsp () { - // Xsp uses the same pair of regs as xtp does. - print_xtp (); + printf (" %016llx,", vec_xs[0] ); + printf ("%016llx", vec_xs[1] ); } void print_xt () { if (debug_show_labels) printf (" vec_xt:" ); if (debug_show_raw_values) { - printf (" %16lx", vec_xt[0]); - printf (" %16lx", vec_xt[1]); + printf (" %16llx", vec_xt[0]); + printf (" %16llx", vec_xt[1]); } // Don't print the xt value unless we are post-instruction test. if (!post_test) return; if (!output_mask ) { if (vec_xt[0] == (unsigned long)&buffer) printf (" (&buffer) "); - else printf (" %16lx", vec_xt[0]); + else printf (" %16llx", vec_xt[0]); if (vec_xt[1] == (unsigned long)&buffer) printf (" (&buffer) "); - else printf (" %16lx", vec_xt[1]); - if (has_xtp) { - printf (" %16lx", XTp0[0]); - printf (" %16lx", XTp0[1]); - printf (" %16lx", XTp1[0]); - printf (" %16lx", XTp1[1]); - } + else printf (" %16llx", vec_xt[1]); } else { /* there is a mask requiring special handling. */ if (instruction_is_dp) { @@ -1535,8 +1555,7 @@ if (debug_show_labels) printf (" vec_xt:" ); special_print_dp_value (vec_xt[0]); if (output_mask&0b010000) special_print_dp_value (vec_xt[1]); - } - if (instruction_is_sp) { + } else if (instruction_is_sp) { if (output_mask&0b1000) special_print_sp_value (0xffffffff&vec_xt[0]>>32); else print_undefined (); @@ -1549,8 +1568,7 @@ if (debug_show_labels) printf (" vec_xt:" ); if (output_mask&0b0001) special_print_sp_value (0xffffffff&vec_xt[1]); else print_undefined (); - } - if (instruction_is_b16) { + } else if (instruction_is_b16) { if (output_mask&B16_0) special_print_bf16_value (0xffffff& (vec_xt[0]>>48)); else @@ -1584,35 +1602,82 @@ if (debug_show_labels) printf (" vec_xt:" ); else print_undefined (); } + else + printf("lost special handling on instruction (sp,dp,bf) type. \n"); } } +// print_register_header* ; print our testcase input values. +// if verbosity is set, print all defined values, including +// the output register contents, regardless +// of whether they are used for this test. +void print_all() { + printf("\nALL:\n"); + print_ra(); + printf("\n"); + print_rb(); + printf("\n"); + print_rs(); + printf("\n"); + print_rsp(); + printf("\n"); + print_xap(); // includes print_xa, print_xc + printf("\n"); + print_xb(); + printf("\n"); + print_xsp(); // includes print_xs, print_xt ??? + printf("\n"); + print_xtp(); + printf("\n"); + print_vra(); + printf("\n"); + print_vrb(); + printf("\n"); + print_vrc(); + printf("\n"); + print_vrm(); + printf("\n"); + print_frs_or_frb(); + printf("\n"); + print_accumulator(); + printf("\n"); + dump_buffer(); + printf("\nEND_ALL\n"); +} + +// Call print_register_header_all if we have verbosity set and +// want to print ALL input fields. +// Otherwise, print the input values that are used by the +// instructions under test. void print_register_header () { - post_test = 0; - if (has_ra || debug_show_all_regs) print_ra (); - if (has_rb || debug_show_all_regs) print_rb (); - if (has_rc || debug_show_all_regs) print_rc (); - if (has_rs || has_rsp || debug_show_all_regs) print_rs (); - // only print the target registers before the test if verbosity is high. - if (has_rt && debug_show_all_regs) print_rt (); - if (has_xa || has_xap || has_xc || debug_show_all_regs) print_xa_or_xc (); - if (has_xb || debug_show_all_regs) print_xb (); - if (has_xs || debug_show_all_regs ) { - if (debug_show_labels) printf (" vec_xs%s:", has_xsp?"p":""); - if (has_xsp) print_xsp (); else print_xs (); - } - /* printing of the xtp pair is handled differently. */ - if (has_xt && debug_show_all_regs ) { - if (has_xtp) print_xtp (); else print_xt (); - } - if (has_vra || debug_show_all_regs) print_vra (); - if (has_vrb || debug_show_all_regs) print_vrb (); - if (has_vrc || debug_show_all_regs) print_vrc (); - if (has_vrm || debug_show_all_regs) print_vrm (); - if (has_vrt && debug_show_all_regs) print_vrt (); - if (has_frs || has_frb || debug_show_all_regs) print_frs_or_frb (); - if (uses_acc_src || debug_show_all_regs) print_accumulator (); - if (uses_load_buffer) dump_buffer (); + post_test = 0; + if (debug_show_all_regs) print_all(); + if (has_ra) print_ra (); + if (has_rb) print_rb (); + if (has_rc) print_rc (); + if (has_rs) print_rs(); + if (has_rsp) print_rsp(); + if (has_xap) { + print_xap(); + } else { + if (has_xa) print_xa(); + if (has_xc) print_xc(); + } + if (has_xb) print_xb (); + if (has_xsp) { + print_xsp(); + } else { + if (has_xs) print_xs(); + } + + if (has_vra) print_vra (); + if (has_vrb) print_vrb (); + if (has_vrc) print_vrc (); + if (has_vrm) print_vrm (); + + if (has_frs || has_frb) print_frs_or_frb (); + if (uses_acc_src) print_accumulator (); + if (uses_load_buffer) dump_buffer (); } void print_register_footer () { @@ -1621,9 +1686,7 @@ void print_register_footer () { if (debug_show_labels) printf (" CR:"); printf (" [%08lx]", current_cr); } - if (current_fpscr) dissect_fpscr (current_fpscr); - if (uses_RC) dissect_cr_rn (current_cr, 6); if (uses_acc_dest || uses_acc_vsrs) print_accumulator (); if (has_vrt || debug_show_all_regs) print_vrt (); @@ -1648,14 +1711,14 @@ void generic_prologue () { Helpers to build the VSX input table. */ #define MAX_VSX_ARRAY_SIZE 42 -unsigned long nb_divmod_num_vsxargs; -unsigned long nb_divmod_den_vsxargs; -unsigned long nb_vsxargs; +unsigned long long nb_divmod_num_vsxargs; +unsigned long long nb_divmod_den_vsxargs; +unsigned long long nb_vsxargs; unsigned long long * vsxargs = NULL; void build_vsx_table (void) { long i = 0; - vsxargs = memalign (16, MAX_VSX_ARRAY_SIZE * sizeof (unsigned long)); + vsxargs = memalign (16, MAX_VSX_ARRAY_SIZE * sizeof (unsigned long long)); /* The following hex values map to assorted Fp values including zero, inf, nan. +/-INF EXP:MAX FRAC:0 @@ -1771,8 +1834,9 @@ unsigned long nb_dfp128args = 32; void debug_show_iter_ranges () { /* Show the iteration maxes and the increments. */ if (debug_show_iters) - printf ("{ a:/%2ld (+%ld) b:/%ld (+%ld) c:/%ld (+%ld) m:/%ld (+%ld) } \n", - a_iters, a_inc, b_iters, b_inc, c_iters, c_inc, m_iters, m_inc ); + printf ("{ a:/%2ld (%ld,+%ld) b:/%ld (%ld,+%ld) c:/%ld (%ld,+%ld) m:/%ld (%ld,+%ld) } \n", + a_iters, a_start, a_inc, b_iters, b_start, b_inc, + c_iters, c_start, c_inc, m_iters, m_start, m_inc); } void set_up_iterators () { @@ -1822,8 +1886,16 @@ void set_up_iterators () { a_iters = 4; b_iters = 6; } + if (uses_acc_dest) { + a_inc+=3; b_inc+=3; c_inc+=3; + } + if (uses_pmsk) { + a_start=1; b_start=3; c_start=0; m_start=0; + } else { + a_start=0; b_start=0; c_start=0; m_start=0; + } if ((has_vra+has_vrb+has_vrc+has_vrm+has_xa+has_xb+uses_MC > 2) && - (verbose < 4)) { + (!debug_enable_all_iters)) { /* Instruction tests using multiple fields will generate a lot of output. In those cases, arbitrarily increase the increment values to cut the number of iterations. */ @@ -1844,7 +1916,7 @@ void debug_show_current_iteration () { } void debug_dump_buffer () { - if ( (verbose>4) || (verbose > 1 && uses_buffer)) { + if ( (debug_show_raw_values) || (verbose && uses_buffer)) { dump_raw_buffer (); printf ("\n"); } @@ -1857,7 +1929,7 @@ void print_result_buffer () { /* display the instruction form. */ void debug_show_form (const char * instruction_name, char * cur_form) { - if (verbose>0) { + if (verbose) { printf ("Instruction Name and form: %s ", instruction_name); display_form_components (cur_form); } @@ -2014,6 +2086,56 @@ void build_float_vsx_tables () { /* **************************************** */ /* Source/destination register initializers */ + +void init_xtp() { + XTp0[0] = DEADBEEF; //vsxargs[vrai+4]; + XTp0[1] = DEADBEEF; //vsxargs[vrai+3]; + XTp1[0] = DEADBEEF; //vsxargs[vrai+2]; + XTp1[1] = DEADBEEF; //vsxargs[vrai+1]; +} + +void init_xsp() { + XTp0[0] = vsxargs[vrai+4]; + XTp0[1] = vsxargs[vrai+3]; + XTp1[0] = vsxargs[vrai+2]; + XTp1[1] = vsxargs[vrai+1]; +} + +void init_source_acc() { + /* initialize the ACC with data */ + TEST_ACC0[0] = vsxargs[ (vrai ) % nb_vsxargs]; + TEST_ACC0[1] = vsxargs[ (vrai+1) % nb_vsxargs]; + TEST_ACC1[0] = vsxargs[ (vrai+2) % nb_vsxargs]; + TEST_ACC1[1] = vsxargs[ (vrai+3) % nb_vsxargs]; + TEST_ACC2[0] = vsxargs[ (vrai+4) % nb_vsxargs]; + TEST_ACC2[1] = vsxargs[ (vrai+5) % nb_vsxargs]; + TEST_ACC3[0] = vsxargs[ (vrai+6) % nb_vsxargs]; + TEST_ACC3[1] = vsxargs[ (vrai+7) % nb_vsxargs]; + push_vsrs_to_acc (); +} + +void init_acc_deadbeef() { + // Initialize the associated VSRs to 'DEADBEEF', then call + // xxmtacc to do the actual set. + TEST_ACC0[0] = DEADBEEF; TEST_ACC0[1] = DEADBEEF; + TEST_ACC1[0] = DEADBEEF; TEST_ACC1[1] = DEADBEEF; + TEST_ACC2[0] = DEADBEEF; TEST_ACC2[1] = DEADBEEF; + TEST_ACC3[0] = DEADBEEF; TEST_ACC3[1] = DEADBEEF; + push_vsrs_to_acc (); +} + + /* initialize the VSRs that will be used by the accumulator related tests. */ +void init_acc_vsrs() { + TEST_ACC0[0] = vsxargs[vrai] ; + TEST_ACC0[1] = vsxargs[vrai+1]; + TEST_ACC1[0] = vsxargs[vrai+2]; + TEST_ACC1[1] = vsxargs[vrai+3]; + TEST_ACC2[0] = vsxargs[vrai+4]; + TEST_ACC2[1] = vsxargs[vrai+5]; + TEST_ACC3[0] = vsxargs[vrai+6]; + TEST_ACC3[1] = vsxargs[vrai+7]; +} + void initialize_target_registers () { vrt[0] = DEADBEEF; vrt[1] = DEADBEEF; @@ -2022,16 +2144,12 @@ void initialize_target_registers () { frt = 0.0; frtp = 0.0; // xs/xt register pairs. - XTp0[0] = vsxargs[6] ; XTp0[1] = vsxargs[5]; - XTp1[0] = vsxargs[4] ; XTp1[1] = vsxargs[3]; + if (has_xtp) { + if (has_xsp) printf("Warning. uses xsp and xtp\n"); + init_xtp(); + } if (uses_acc_dest) { - // Initialize the associated VSRs to 'DEADBEEF', then call - // xxmtacc to do the actual set. - TEST_ACC0[0] = DEADBEEF; TEST_ACC0[1] = DEADBEEF; - TEST_ACC1[0] = DEADBEEF; TEST_ACC1[1] = DEADBEEF; - TEST_ACC2[0] = DEADBEEF; TEST_ACC2[1] = DEADBEEF; - TEST_ACC3[0] = DEADBEEF; TEST_ACC3[1] = DEADBEEF; - push_vsrs_to_acc (); + init_acc_deadbeef(); } } @@ -2053,19 +2171,59 @@ void initialize_source_registers () { current_fpscr = 0; SET_FPSCR_ZERO; current_fpscr = 0; - if (is_divide_or_modulo) { - vra[0] = vec_xa[0] = vsxargs[ (vrai ) % nb_divmod_num_vsxargs]; - vra[1] = vec_xa[1] = vsxargs[ (vrai+1) % nb_divmod_num_vsxargs]; - vrb[0] = vec_xb[0] = vsxargs[ (vrbi ) % nb_divmod_den_vsxargs]; - vrb[1] = vec_xb[1] = vsxargs[ (vrbi+1) % nb_divmod_den_vsxargs]; - } else { - vra[0] = vec_xa[0] = vsxargs[ (vrai ) % nb_vsxargs]; - vra[1] = vec_xa[1] = vsxargs[ (vrai+1) % nb_vsxargs]; - vrb[0] = vec_xb[0] = vsxargs[ (vrbi ) % nb_vsxargs]; - vrb[1] = vec_xb[1] = vsxargs[ (vrbi+1) % nb_vsxargs]; - if (is_testlsb) { - /* Special casing for this test to force the vec_xb low bits - to zero or one. */ + int isr_modulo; + /* Special handing for input values.. ensure if we are + dividing or doing modulo operations that we do not + attempt dividing by zero. */ + if (is_divide_or_modulo) + isr_modulo = nb_divmod_num_vsxargs; + else + isr_modulo = nb_vsxargs; + + if (has_xa) { + vec_xa[0] = vsxargs[ (vrai ) % isr_modulo]; + vec_xa[1] = vsxargs[ (vrai+1) % isr_modulo]; + } + if (has_xb) { + vec_xb[0] = vsxargs[ (vrbi ) % isr_modulo]; + vec_xb[1] = vsxargs[ (vrbi+1) % isr_modulo]; + } + if (has_vra) { + vra[0] = vsxargs[ (vrai ) % isr_modulo]; + vra[1] = vsxargs[ (vrai+1) % isr_modulo]; + } + if (has_vrb) { + vrb[0] = vsxargs[ (vrbi ) % isr_modulo]; + vrb[1] = vsxargs[ (vrbi+1) % isr_modulo]; + } + + if (has_xa) { + vec_xa[0] = vsxargs[ (vrai ) % isr_modulo]; + vec_xa[1] = vsxargs[ (vrai+1) % isr_modulo]; + } + if (has_xb) { + vec_xb[0] = vsxargs[ (vrbi ) % isr_modulo]; + vec_xb[1] = vsxargs[ (vrbi+1) % isr_modulo]; + } + + // xap 'shares' with the second half of an xa-pair. + if (has_xap ) { + vec_xc[0] = vsxargs[ (vrci+2) % isr_modulo]; + vec_xc[1] = vsxargs[ (vrci+3) % isr_modulo]; + } + // Combine with the above has_xap clause ? May need addiitonal + // logic later if these ever overlap. + if (has_xc) { + vec_xc[0] = vsxargs[ (vrai ) % isr_modulo]; + vec_xc[1] = vsxargs[ (vrai+1) % isr_modulo]; + } + if (has_vrc) { + vrc[0] = vsxargs[ (vrci ) % nb_vsxargs]; + vrc[1] = vsxargs[ (vrci+1) % nb_vsxargs]; + } + if (is_testlsb) { + /* Special casing for this test to force the vec_xb low bits + to zero or one. */ if (vrbi%3 == 0) { // force bits to zero. vec_xb[0] = vec_xb[0]&0xfefefefefefefefeUL; @@ -2075,17 +2233,8 @@ void initialize_source_registers () { // force bits to one. vec_xb[0] = vec_xb[0]|0x0101010101010101UL; vec_xb[1] = vec_xb[1]|0x0101010101010101UL; - } } - } - if (has_xap) { - /* shift this back to vrai if we are an xa pair */ - vrc[0] = vec_xc[0] = vsxargs[ (vrai+2) % nb_vsxargs]; - vrc[1] = vec_xc[1] = vsxargs[ (vrai+3) % nb_vsxargs]; - } else { - vrc[0] = vec_xc[0] = vsxargs[ (vrci ) % nb_vsxargs]; - vrc[1] = vec_xc[1] = vsxargs[ (vrci+1) % nb_vsxargs]; - } + } if (uses_xc_as_blend_mask) { vec_xc[0] = mask64[ (vrci )%MASK64SIZE]; @@ -2100,12 +2249,14 @@ void initialize_source_registers () { frsbp = vsxargs[ (vrbi+1)%nb_vsxargs]; } + /* default initializations.. */ ra = args[vrai]; rb = args[vrbi % nb_args ]; - rc = args[vrci]; + rc = 2 * vrci; rs = args[vrai % nb_args ]; rsp = args[ (vrai+1) % nb_args ]; + /* more special cases.. */ if (is_clear_or_insert_insns) { if (has_rb) rb = 2*vrbi; /* note special case for is_insert_double, see set_up_iterators () */ @@ -2113,11 +2264,10 @@ void initialize_source_registers () { if (is_insert_double) { /* For an insert_double, the results are undefined for ra > 8, so modulo those into a valid range. */ - ra =ra % 9; + ra = ra % 9; } } - if (has_rc) rc = 2*vrci; if (uses_buffer) { if (has_rb) { ra = 8*vrai; @@ -2146,35 +2296,19 @@ void initialize_source_registers () { dcmx = 1 << vrci; if (uses_acc_src) { - /* initialize the ACC with data */ - TEST_ACC0[0] = vsxargs[ (vrai ) % nb_vsxargs]; - TEST_ACC0[1] = vsxargs[ (vrai+1) % nb_vsxargs]; - TEST_ACC1[0] = vsxargs[ (vrai+2) % nb_vsxargs]; - TEST_ACC1[1] = vsxargs[ (vrai+3) % nb_vsxargs]; - TEST_ACC2[0] = vsxargs[ (vrai+4) % nb_vsxargs]; - TEST_ACC2[1] = vsxargs[ (vrai+5) % nb_vsxargs]; - TEST_ACC3[0] = vsxargs[ (vrai+6) % nb_vsxargs]; - TEST_ACC3[1] = vsxargs[ (vrai+7) % nb_vsxargs]; - push_vsrs_to_acc (); + init_source_acc(); } if (uses_acc_vsrs) { - /* initialize the VSRs that will be used by the accumulator related tests. */ - TEST_ACC0[0] = vsxargs[vrai] ; - TEST_ACC0[1] = vsxargs[vrai+1]; - TEST_ACC1[0] = vsxargs[vrai+2]; - TEST_ACC1[1] = vsxargs[vrai+3]; - TEST_ACC2[0] = vsxargs[vrai+4]; - TEST_ACC2[1] = vsxargs[vrai+5]; - TEST_ACC3[0] = vsxargs[vrai+6]; - TEST_ACC3[1] = vsxargs[vrai+7]; + init_acc_vsrs(); } if (has_xs) { - vec_xs[0] = vsxargs[ (vrai ) % nb_vsxargs]; - vec_xs[1] = vsxargs[ (vrai+1) % nb_vsxargs]; - } - if (has_xsp) { - vec_xt[0] = vsxargs[ (vrai+2) % nb_vsxargs]; - vec_xt[1] = vsxargs[ (vrai+3) % nb_vsxargs]; + init_xsp(); +// vec_xs is not directly shared with the register defined XSp/XTp, so +// explicitly assign the values when needed. + vec_xs[0] = XTp0[0]; + vec_xs[1] = XTp0[1]; + vec_xs[0] = XTp1[0]; + vec_xs[1] = XTp1[1]; } } |
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From: Carl L. <ca...@so...> - 2020-10-07 16:34:48
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=02b6a1de06e99ead310e91aa59ae1261aebaa761 commit 02b6a1de06e99ead310e91aa59ae1261aebaa761 Author: Carl Love <ce...@us...> Date: Wed May 13 15:19:07 2020 -0500 Add ISA 3.1 Vector Integer Multiply/Divide/Modulo Instructions Add support for: vdivesd Vector Divide Extended Signed Doubleword vdivesw Vector Divide Extended Signed Word vdiveud Vector Divide Extended Unsigned Doubleword vdiveuw Vector Divide Extended Unsigned Word vdivsd Vector Divide Signed Doubleword vdivsw Vector Divide Signed Word vdivud Vector Divide Unsigned Doubleword vdivuw Vector Divide Unsigned Word vmodsd Vector Modulo Signed Doubleword vmodsw Vector Modulo Signed Word vmodud Vector Modulo Unsigned Doubleword vmoduw Vector Modulo Unsigned Word vmulhsd Vector Multiply High Signed Doubleword vmulhsw Vector Multiply High Signed Word vmulhud Vector Multiply High Unsigned Doubleword vmulhuw Vector Multiply High Unsigned Word vmulld Vector Multiply Low Doubleword Diff: --- VEX/priv/guest_ppc_toIR.c | 398 +++++++++++++++++++++++++++++++++++++++++++++- VEX/priv/host_ppc_isel.c | 6 +- 2 files changed, 396 insertions(+), 8 deletions(-) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 7f5d5ba1c5..5d139d0741 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -3067,6 +3067,22 @@ static void set_XER_OV_OV32_ADDEX ( IRType ty, IRExpr* res, } } +static IRExpr * absI64( IRTemp src ) +{ + IRTemp sign_mask; + IRTemp twos_comp; + sign_mask = newTemp( Ity_I64 ); + twos_comp = newTemp( Ity_I64 ); + + assign( sign_mask, unop( Iop_1Sto64, unop( Iop_64to1, binop( Iop_Shr64, + mkexpr( src ), mkU8( 63 ) ) ) ) ); + assign( twos_comp, binop( Iop_Add64, unop( Iop_Not64, mkexpr( src ) ), mkU64( 1 ) ) ); + + return binop( Iop_Or64, + binop( Iop_And64, mkexpr ( src ), unop( Iop_Not64, mkexpr( sign_mask ) ) ), + binop( Iop_And64, mkexpr( twos_comp ), mkexpr( sign_mask ) ) ); +} + /*-----------------------------------------------------------*/ /*--- Prefix instruction helpers ---*/ /*-----------------------------------------------------------*/ @@ -4124,9 +4140,8 @@ static IRExpr * is_Denorm( IRType size, IRTemp src ) static IRExpr * is_Zero_Vector( IRType element_size, IRExpr *src ) { -/* Check elements of a 128-bit floating point vector, with element size - element_size, are zero. Return 1's in the elements of the vector - which are values. */ +/* Check elements of a 128-bit floating point vector, with element size are + zero. Return 1's in the elements of the vector which are values. */ IRTemp exp_maskV128 = newTemp( Ity_V128 ); IRTemp exp_zeroV128 = newTemp( Ity_V128 ); IRTemp frac_maskV128 = newTemp( Ity_V128 ); @@ -4159,6 +4174,23 @@ static IRExpr * is_Zero_Vector( IRType element_size, IRExpr *src ) mkexpr( frac_zeroV128 ) ); } +static IRExpr * Abs_Zero_Vector( IRType element_size, IRExpr *src ) +/* Vector of four 32-bit elements, convert any negative zeros to + positive zeros. */ +{ + IRTemp result = newTemp( Ity_V128 ); + + if ( element_size == Ity_I32 ) { + assign( result, binop( Iop_AndV128, + src, + unop( Iop_NotV128, + is_Zero_Vector( element_size, src) ) ) ); + } else + vex_printf("ERROR, Abs_Zero_Vector: Unknown input size\n"); + + return mkexpr( result ); +} + static IRExpr * is_Denorm_Vector( IRType element_size, IRExpr *src ) { /* Check elements of a 128-bit floating point vector, with element size @@ -7782,9 +7814,9 @@ static Bool dis_int_load_ds_form_prefix ( UInt prefix, break; case 0x1: // ldu (Load DWord, Update, PPC64 p474) - /* There is no prefixed version of these instructions. */ + /* There is no prefixed version of this instructions. */ if (rA_addr == 0 || rA_addr == rT_addr) { - vex_printf("dis_int_load(ppc)(ldu,rA_addr|rT_addr)\n"); + vex_printf("dis_int_load_ds_form_prefix(ppc)(ldu,rA_addr|rT_addr)\n"); return False; } DIP("ldu r%u,%u(r%u)\n", rT_addr, immediate_val, rA_addr); @@ -24772,6 +24804,347 @@ static Bool dis_av_arith ( UInt prefix, UInt theInstr ) // TODO: set VSCR[SAT] break; + case 0x08B: // vdivuw Vector Divide Unsigned Word + case 0x18B: // vdivsw Vector Divide Signed Word + case 0x289: // vmulhuw Vector Multiply High Unsigned Word + case 0x389: // vmulhsw Vector Multiply High Signed Word + case 0x28B: // vdiveuw Vector divide Extended Unsigned Word + case 0x38B: // vdivesw Vector divide Extended Signed Word + case 0x68B: // vmoduw Vector Modulo Unsigned Word + case 0x78B: // vmodsw Vector Modulo Signed Word + { + #define MAX_ELE 4 + IROp expand_op = Iop_32Uto64; + IROp extract_res = Iop_64to32; + IROp operation = Iop_DivU64; + IRTemp srcA_tmp[MAX_ELE]; + IRTemp srcB_tmp[MAX_ELE]; + IRTemp res_tmp[MAX_ELE]; + IRTemp res_tmp2[MAX_ELE]; + IRTemp res_tmp3[MAX_ELE]; + UInt shift_by = 32; + UInt i; + IRType size_op = Ity_I64, size_res = Ity_I32; + + if (opc2 == 0x08B) { + DIP("vdivuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + expand_op= Iop_32Uto64; + operation = Iop_DivU64; + extract_res = Iop_64to32; + + } else if (opc2 == 0x68B) { + DIP("vmoduw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + expand_op= Iop_32Uto64; + operation = Iop_DivU64; + extract_res = Iop_64to32; + + } else if (opc2 == 0x18B) { + DIP("vdivsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + expand_op= Iop_32Sto64; + operation = Iop_DivS64; + extract_res = Iop_64to32; + + } else if (opc2 == 0x78B) { + DIP("vmodsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + expand_op= Iop_32Sto64; + operation = Iop_DivS64; + extract_res = Iop_64to32; + + } else if (opc2 == 0x289) { + DIP("vmulhuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + expand_op = Iop_32Uto64; + operation = Iop_Mul64; + extract_res = Iop_64HIto32; + + } else if (opc2 == 0x389) { + DIP("vmulhsw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + expand_op= Iop_32Sto64; + operation = Iop_Mul64; + extract_res = Iop_64HIto32; + + } else if (opc2 == 0x28B) { + DIP("vdiveuw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + expand_op= Iop_32Uto64; + operation = Iop_DivU64; + extract_res = Iop_64to32; + + } else if (opc2 == 0x38B) { + DIP("vdivesw v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + expand_op= Iop_32Sto64; + operation = Iop_DivS64; + extract_res = Iop_64to32; + } + + for (i=0; i<MAX_ELE; i++) { + srcA_tmp[i] = newTemp( size_op ); + srcB_tmp[i] = newTemp( size_op ); + res_tmp[i] = newTemp( size_res ); + + if (( opc2 == 0x28B ) || ( opc2 == 0x38B )) { + // Operand A is left shifted 32 bits + assign( srcA_tmp[i], + binop( Iop_Shl64, + unop( expand_op, + unop( Iop_64to32, + unop( Iop_V128to64, + binop( Iop_ShrV128, + mkexpr( vA ), + mkU8( i*shift_by ) )))), + mkU8( 32 ) ) ); + } else { + assign( srcA_tmp[i], + unop( expand_op, + unop( Iop_64to32, + unop( Iop_V128to64, + binop( Iop_ShrV128, + mkexpr( vA ), + mkU8( i*shift_by ) ) ) ) ) ); + } + + assign( srcB_tmp[i], + unop( expand_op, + unop( Iop_64to32, + unop( Iop_V128to64, + binop( Iop_ShrV128, + mkexpr( vB ), + mkU8( i*shift_by ) ) ) ) ) ); + + if ( opc2 == 0x38B ) { // vdivesw + /* Take absolute value of signed operands to determine if the result fits in 31 bits. + Set result to zeros if it doesn't fit to match the HW functionality. */ + res_tmp2[i] = newTemp( Ity_I64 ); + res_tmp3[i] = newTemp( Ity_I64 ); + + /* Calculate actual result */ + assign( res_tmp2[i], + binop( operation, + mkexpr( srcA_tmp[i] ), + mkexpr( srcB_tmp[i] ) ) ); + + /* Calculate result for ABS(srcA) and ABS(srcB) */ + assign( res_tmp3[i], binop( operation, absI64( srcA_tmp[i] ), absI64( srcB_tmp[i] ) ) ); + + assign( res_tmp[i], + unop( extract_res, + binop( Iop_And64, + unop( Iop_1Sto64, + binop( Iop_CmpEQ64, + binop( Iop_Shr64, mkexpr( res_tmp3[i] ), mkU8( 31 )), + mkU64( 0x0 ) ) ), + mkexpr( res_tmp2[i] ) ) ) ); + + } else if ( opc2 == 0x28B ) { // vdiveuw + /* Check if result fits in 32-bits, set result to zeros if it doesn't fit to + match the HW functionality. */ + res_tmp2[i] = newTemp( Ity_I64 ); + assign( res_tmp2[i], + binop( operation, + mkexpr( srcA_tmp[i] ), + mkexpr( srcB_tmp[i] ) ) ); + assign( res_tmp[i], + unop( extract_res, + binop( Iop_And64, + unop( Iop_1Sto64, + binop( Iop_CmpEQ64, + binop( Iop_Shr64, mkexpr( res_tmp2[i] ), mkU8( 32 )), + mkU64( 0x0 ) ) ), + mkexpr( res_tmp2[i] ) ) ) ); + } else { + assign( res_tmp[i], + unop( extract_res, + binop( operation, + mkexpr( srcA_tmp[i] ), + mkexpr( srcB_tmp[i] ) ) ) ); + } + } + + if (!(( opc2 == 0x68B ) || ( opc2 == 0x78B ))) { + /* Doing a multiply or divide instruction */ + putVReg( vD_addr, + Abs_Zero_Vector( Ity_I32, + binop( Iop_64HLtoV128, + binop( Iop_32HLto64, + mkexpr( res_tmp[ 3 ] ), + mkexpr( res_tmp[ 2 ] ) ), + binop( Iop_32HLto64, + mkexpr( res_tmp[ 1 ] ), + mkexpr( res_tmp[ 0 ] ) ) ) ) ); + } else { + /* Doing a modulo instruction, + res_tmp[] contains the quotients of VRA/VRB. + Calculate modulo as VRA - VRB * res_tmp. */ + IRTemp res_Tmp = newTemp( Ity_V128 ); + + assign( res_Tmp, + Abs_Zero_Vector( Ity_I32, + binop( Iop_64HLtoV128, + binop( Iop_32HLto64, + mkexpr( res_tmp[ 3 ] ), + mkexpr( res_tmp[ 2 ] ) ), + binop( Iop_32HLto64, + mkexpr( res_tmp[ 1 ] ), + mkexpr( res_tmp[ 0 ] ) ) ) ) ); + + putVReg( vD_addr, binop( Iop_Sub32x4, + mkexpr( vA ), + binop( Iop_Mul32x4, + mkexpr( res_Tmp ), + mkexpr( vB ) ) ) ); + } + #undef MAX_ELE + } + break; + case 0x1C9: // vmulld Vector Multiply Low Signed Doubleword + case 0x2C9: // vmulhud Vector Multiply High Unsigned Doubleword + case 0x3C9: // vmulhsd Vector Multiply High Signed Doubleword + case 0x0CB: // vdivud Vector Divide Unsigned Doubleword + case 0x1CB: // vdivsd Vector Divide Signed Doubleword + case 0x6CB: // vmodud Vector Modulo Unsigned Doubleword + case 0x7CB: // vmodsd Vector Modulo Signed Doubleword + { + #define MAX_ELE 2 + IROp extract_res = Iop_64to32; + IROp operation = Iop_MullS64; + IRTemp srcA_tmp[MAX_ELE]; + IRTemp srcB_tmp[MAX_ELE]; + IRTemp res_tmp[MAX_ELE]; + UInt shift_by = 64; + UInt i; + IRType size_op = Ity_I64, size_res = Ity_I64; + + + if (opc2 == 0x1C9) { + DIP("vmulld v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + operation = Iop_MullS64; + extract_res = Iop_128to64; + + } else if (opc2 == 0x2C9) { + DIP("vmulhud v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + operation = Iop_MullU64; + extract_res = Iop_128HIto64; + + } else if (opc2 == 0x3C9) { + DIP("vmulhsd v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + operation = Iop_MullS64; + extract_res = Iop_128HIto64; + + } else if (opc2 == 0x0CB) { + DIP("vdivud v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + operation = Iop_DivU64; + + } else if (opc2 == 0x1CB) { + DIP("vdivsd v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + operation = Iop_DivS64; + + } else if (opc2 == 0x6CB) { + DIP("vmodud v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + operation = Iop_DivU64; + + } else if (opc2 == 0x7CB) { + DIP("vmodsd v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + operation = Iop_DivS64; + } + + for (i=0; i<MAX_ELE; i++) { + srcA_tmp[i] = newTemp( size_op ); + srcB_tmp[i] = newTemp( size_op ); + res_tmp[i] = newTemp( size_res ); + + assign( srcA_tmp[i], + unop( Iop_V128to64, + binop( Iop_ShrV128, + mkexpr( vA ), + mkU8( i*shift_by ) ) ) ); + + assign( srcB_tmp[i], + unop( Iop_V128to64, + binop( Iop_ShrV128, + mkexpr( vB ), + mkU8( i*shift_by ) ) ) ); + + if ((opc2 == 0x1C9) || (opc2 == 0x2C9) || (opc2 == 0x3C9)) { + /* multiply result is I128 */ + assign( res_tmp[i], + unop( extract_res, + binop( operation, + mkexpr( srcA_tmp[i] ), + mkexpr( srcB_tmp[i] ) ) ) ); + } else { + /* divide result is I64 */ + assign( res_tmp[i], + binop( operation, + mkexpr( srcA_tmp[i] ), + mkexpr( srcB_tmp[i] ) ) ); + } + } + + if ((opc2 == 0x6CB) || (opc2 == 0x7CB)) { + /* Doing a modulo instruction, + res_tmp[] contains the quotients of VRA/VRB. + Calculate modulo as VRA - VRB * res_tmp. */ + IRTemp res_Tmp = newTemp( Ity_V128 ); + + assign( res_Tmp, binop( Iop_64HLtoV128, + binop( Iop_Mul64, + mkexpr( res_tmp[ 1 ] ), + mkexpr( srcB_tmp[1] ) ), + binop( Iop_Mul64, + mkexpr( res_tmp[0] ), + mkexpr( srcB_tmp[0] ) ) ) ); + + putVReg( vD_addr, binop( Iop_Sub64x2, + mkexpr( vA ), + mkexpr( res_Tmp ) ) ); + + } else { + putVReg( vD_addr, binop( Iop_64HLtoV128, + mkexpr( res_tmp[ 1 ] ), + mkexpr( res_tmp[ 0 ] ) ) ); + } + + #undef MAX_ELE + } + break; + + case 0x2CB: // vdiveud Vector Divide Extended Unsigned Doubleword + case 0x3CB: { // vdivesd Vector Divide Extended Signed Doubleword + /* Do vector inst as two scalar operations */ + IRTemp divisor_hi = newTemp(Ity_I64); + IRTemp divisor_lo = newTemp(Ity_I64); + IRTemp dividend_hi = newTemp(Ity_I64); + IRTemp dividend_lo = newTemp(Ity_I64); + IRTemp result_hi = newTemp(Ity_I64); + IRTemp result_lo = newTemp(Ity_I64); + + assign( dividend_hi, unop( Iop_V128HIto64, mkexpr( vA ) ) ); + assign( dividend_lo, unop( Iop_V128to64, mkexpr( vA ) ) ); + assign( divisor_hi, unop( Iop_V128HIto64, mkexpr( vB ) ) ); + assign( divisor_lo, unop( Iop_V128to64, mkexpr( vB ) ) ); + + if (opc2 == 0x2CB) { + DIP("vdiveud v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); + assign( result_hi, + binop( Iop_DivU64E, mkexpr( dividend_hi ), + mkexpr( divisor_hi ) ) ); + assign( result_lo, + binop( Iop_DivU64E, mkexpr( dividend_lo ), + mkexpr( divisor_lo ) ) ); + putVReg( vD_addr, binop( Iop_64HLtoV128, mkexpr( result_hi ), + mkexpr( result_lo ) ) ); + + } else { + DIP("vdivesd v%d,v%d,v%d", vD_addr, vA_addr, vB_addr); + assign( result_hi, + binop( Iop_DivS64E, mkexpr( dividend_hi ), + mkexpr( divisor_hi ) ) ); + assign( result_lo, + binop( Iop_DivS64E, mkexpr( dividend_lo ), + mkexpr( divisor_lo ) ) ); + putVReg( vD_addr, binop( Iop_64HLtoV128, mkexpr( result_hi ), + mkexpr( result_lo ) ) ); + } + break; + } /* Subtract */ case 0x580: { // vsubcuw (Subtract Carryout Unsigned Word, AV p260) @@ -31433,9 +31806,22 @@ DisResult disInstr_PPC_WRK ( if (dis_av_arith( prefix, theInstr )) goto decode_success; goto decode_failure; + case 0x08B: case 0x18B: // vdivuw, vdivsw + case 0x289: case 0x389: // vmulhuw, vmulhsw + case 0x28B: case 0x38B: // vdiveuw, vdivesw + case 0x68B: case 0x78B: // vmoduw, vmodsw + case 0x1c9: // vmulld + case 0x2C9: case 0x3C9: // vmulhud, vmulhsd + case 0x0CB: case 0x1CB: // vdivud, vdivsd + case 0x2CB: case 0x3CB: // vdiveud, vdivesd + case 0x6CB: case 0x7CB: // vmodud, vmodsd + if (!allow_V) goto decode_noV; + if (dis_av_arith( prefix, theInstr )) goto decode_success; + goto decode_failure; + case 0x088: case 0x089: // vmulouw, vmuluwm case 0x0C0: case 0x0C2: // vaddudm, vmaxud - case 0x1C2: case 0x2C2: case 0x3C2: // vnaxsd, vminud, vminsd + case 0x1C2: case 0x2C2: case 0x3C2: // vmaxsd, vminud, vminsd case 0x188: case 0x288: case 0x388: // vmulosw, vmuleuw, vmulesw case 0x4C0: // vsubudm if (!allow_isa_2_07) goto decode_noP8; diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c index 93d0625800..9c79b6fa13 100644 --- a/VEX/priv/host_ppc_isel.c +++ b/VEX/priv/host_ppc_isel.c @@ -3226,8 +3226,10 @@ static PPCCondCode iselCondCode_wrk ( ISelEnv* env, const IRExpr* e, switch (e->Iex.Binop.op) { case Iop_CmpEQ64: return mk_PPCCondCode( Pct_TRUE, Pcf_7EQ ); case Iop_CmpNE64: return mk_PPCCondCode( Pct_FALSE, Pcf_7EQ ); - case Iop_CmpLT64U: return mk_PPCCondCode( Pct_TRUE, Pcf_7LT ); - case Iop_CmpLE64U: return mk_PPCCondCode( Pct_FALSE, Pcf_7GT ); + case Iop_CmpLT64U: case Iop_CmpLT64S: + return mk_PPCCondCode( Pct_TRUE, Pcf_7LT ); + case Iop_CmpLE64U: case Iop_CmpLE64S: + return mk_PPCCondCode( Pct_FALSE, Pcf_7GT ); default: vpanic("iselCondCode(ppc): CmpXX64"); } } |
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From: Carl L. <ca...@so...> - 2020-10-07 16:34:38
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=34d142fffbec096a30b265f9e2cf277adb7d5c5c commit 34d142fffbec096a30b265f9e2cf277adb7d5c5c Author: Will Schmidt <wil...@vn...> Date: Mon Jun 22 09:57:21 2020 -0500 Add ISA 3.1 VSX 32-byte Storage Access Operations Add support for the new ISA 3.1 load and store instructions: lxvpx Load VSX Vector Paired Indexed plxvp Prefixed Load VSX Vector Paired pstxvp Prefixed Store VSX Vector Paired stxvpx Store VSX Vector Paired Indexed Update the parsing of the lxvp and stxvp instructions that were previously added. lxvp Load VSX Vector Paired stxvp Store VSX Vector Paired A couple of format changes for the arguments to the calculate_prefix_EA function. Add comments to the else if and case statement to clarify which instructions meet this condition. Diff: --- VEX/priv/guest_ppc_toIR.c | 205 +++++++++++++++++++++++++++++++++++++++------- 1 file changed, 175 insertions(+), 30 deletions(-) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index aae8664ea5..7f5d5ba1c5 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -8172,21 +8172,20 @@ static Bool dis_int_store_ds_prefix ( UInt prefix, b0 = 0; b1 = 1; assign( EA, calculate_prefix_EA( prefix, theInstr, rA_addr, - ptype, DSFORM_IMMASK, - &immediate_val, &R ) ); + ptype, DSFORM_IMMASK, &immediate_val, + &R ) ); } else if (opc1 == 0x3D) { // force opc2 to 0 to map pstd to std inst b0 = 0; b1 = 0; assign( EA, calculate_prefix_EA( prefix, theInstr, rA_addr, - ptype, DSFORM_IMMASK, - &immediate_val, &R ) ); + ptype, DSFORM_IMMASK, &immediate_val, + &R ) ); } else if ( opc1 == 0x3 ) { - assign( EA, ea_rAor0_simm( rA_addr, simm16 ) ); - } else if ( opc1 == 0x3E ) { + } else if ( opc1 == 0x3E ) { // std, stdu, stq // lowest 2 bits of immediate before forming EA immediate_val = simm16 & 0xFFFFFFFC; assign( EA, ea_rAor0_simm( rA_addr, immediate_val ) ); @@ -12564,18 +12563,11 @@ static Bool dis_fp_pair_prefix ( UInt prefix, UInt theInstr ) case 0: { /* Endian aware load */ - pDIP( is_prefix, "lxvp %u,%u(%u)\n", XTp, immediate_val, rA_addr ); - DIPp( is_prefix, ",%u", R ); - - if (is_prefix && (R == 1) ) { - vex_printf("Illegal instruction R = 1; plxvp %u,%u(%u)\n", - XTp, immediate_val, rA_addr ); - return False; - } + DIP( "lxvp %u,%u(%u)\n", XTp, immediate_val, rA_addr ); // address of next 128bits - assign( EA_16, binop( Iop_Add64, mkU64( 16), mkexpr( EA ) ) ); - if (host_endness == VexEndnessLE) { + assign( EA_16, binop( Iop_Add64, mkU64( 16 ), mkexpr( EA ) ) ); + if (host_endness == VexEndnessBE) { putVSReg( XTp, load( Ity_V128, mkexpr( EA ) ) ); putVSReg( XTp+1, load( Ity_V128, mkexpr( EA_16 ) ) ); } else { @@ -12590,14 +12582,7 @@ static Bool dis_fp_pair_prefix ( UInt prefix, UInt theInstr ) IRTemp EA_8 = newTemp(ty); IRTemp EA_24 = newTemp(ty); /* Endian aware store */ - pDIP( is_prefix, "stxvp %u,%u(%u)\n", XTp, immediate_val, rA_addr ); - DIPp( is_prefix, ",%u", R ); - - if ( is_prefix && ( R == 1 ) ) { - vex_printf("Illegal instruction R = 1; pstxvp %u,%u(%u)\n", - XTp, immediate_val, rA_addr ); - return False; - } + DIP("stxvp %u,%u(%u)\n", XTp, immediate_val, rA_addr ); // address of next 128bits assign( EA_8, binop( Iop_Add64, mkU64( 8 ), mkexpr( EA ) ) ); @@ -12817,6 +12802,74 @@ static Bool dis_fp_pair_prefix ( UInt prefix, UInt theInstr ) break; } + case 0x3A: // plxvp + { + UChar XTp = ifieldRegXTp(theInstr); + + /* Endian aware prefixed load */ + pDIP( is_prefix, "lxvp %u,%u(%u)", XTp, immediate_val, rA_addr ); + DIPp( is_prefix, ",%u", R ); + + if (R == 1 ) { + vex_printf("Illegal instruction R = 1; plxvp %u,%u(%u)\n", + XTp, immediate_val, rA_addr ); + return False; + } + + assign( EA, calculate_prefix_EA( prefix, theInstr, + rA_addr, ptype, DFORM_IMMASK, + &immediate_val, &R ) ); + + // address of next 128bits + assign( EA_16, binop( Iop_Add64, mkU64( 16 ), mkexpr( EA ) ) ); + if (host_endness == VexEndnessBE) { + putVSReg( XTp, load( Ity_V128, mkexpr( EA ) ) ); + putVSReg( XTp+1, load( Ity_V128, mkexpr( EA_16 ) ) ); + } else { + putVSReg( XTp+1, load( Ity_V128, mkexpr( EA ) ) ); + putVSReg( XTp, load( Ity_V128, mkexpr( EA_16 ) ) ); + } + return True; + } + + case 0x3E: // pstxvp + { + IRTemp EA_8 = newTemp(ty); + IRTemp EA_24 = newTemp(ty); + UChar XTp = ifieldRegXTp(theInstr); + + /* Endian aware prefixed load */ + pDIP( is_prefix, "stxvp %u,%u(%u)\n", XTp, immediate_val, rA_addr ); + DIPp( is_prefix, ",%u", R ); + + if ( R == 1 ) { + vex_printf("Illegal instruction R = 1; pstxvp %u,%u(%u)\n", + XTp, immediate_val, rA_addr ); + return False; + } + + assign( EA, calculate_prefix_EA( prefix, theInstr, + rA_addr, ptype, DFORM_IMMASK, + &immediate_val, &R ) ); + + assign( EA_8, binop( Iop_Add64, mkU64( 8 ), mkexpr( EA ) ) ); + assign( EA_16, binop( Iop_Add64, mkU64( 16 ), mkexpr( EA ) ) ); + assign( EA_24, binop( Iop_Add64, mkU64( 24 ), mkexpr( EA ) ) ); + + if (host_endness == VexEndnessBE) { + store( mkexpr( EA ), unop( Iop_V128to64, getVSReg( XTp ) ) ); + store( mkexpr( EA_8 ), unop( Iop_V128HIto64, getVSReg( XTp ) ) ); + store( mkexpr( EA_16 ), unop( Iop_V128to64, getVSReg( XTp+1 ) ) ); + store( mkexpr( EA_24 ), unop( Iop_V128HIto64, getVSReg( XTp+1 ) ) ); + } else { + store( mkexpr( EA ), unop( Iop_V128to64, getVSReg( XTp+1 ) ) ); + store( mkexpr( EA_8 ), unop( Iop_V128HIto64, getVSReg( XTp+1 ) ) ); + store( mkexpr( EA_16 ), unop( Iop_V128to64, getVSReg( XTp ) ) ); + store( mkexpr( EA_24 ), unop( Iop_V128HIto64, getVSReg( XTp ) ) ); + } + return True; + } + default: vex_printf("dis_fp_pair_prefix(ppc)(instr)\n"); return False; @@ -22419,6 +22472,67 @@ dis_vx_move ( UInt prefix, UInt theInstr ) * VSX Store Instructions * NOTE: VSX supports word-aligned storage access. */ +static Bool +dis_vsx_vector_paired_load_store ( UInt prefix, UInt theInstr ) +{ + /* X-Form/DS-Form */ + UInt opc2 = ifieldOPClo9(theInstr); + UChar rA_addr = ifieldRegA(theInstr); + UChar rB_addr = ifieldRegB(theInstr); + IRType ty = mode64 ? Ity_I64 : Ity_I32; + IRTemp EA = newTemp(ty); + IRTemp EA_16 = newTemp(ty); + UChar XTp = ifieldRegXTp(theInstr); + + assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) ); + + // address of next 128bits + assign( EA_16, binop( Iop_Add64, mkU64( 16), mkexpr( EA ) ) ); + + switch (opc2) { + case 0x14D: // lxvpx + DIP( "lxvpx %u,%d(%u)\n", XTp, rA_addr, rB_addr ); + if ( host_endness == VexEndnessBE ) { + putVSReg( XTp, load( Ity_V128, mkexpr( EA ) ) ); + putVSReg( XTp+1, load( Ity_V128, mkexpr( EA_16 ) ) ); + } else { + putVSReg( XTp+1, load( Ity_V128, mkexpr( EA ) ) ); + putVSReg( XTp, load( Ity_V128, mkexpr( EA_16 ) ) ); + } + break; + + case 0x1CD: { // stxvpx + IRTemp EA_8 = newTemp(ty); + IRTemp EA_24 = newTemp(ty); + + DIP( "stxvpx %u,%d(%u)\n", XTp, rA_addr, rB_addr ); + + assign( EA_8, binop( Iop_Add64, mkU64( 8 ), mkexpr( EA ) ) ); + assign( EA_24, binop( Iop_Add64, mkU64( 24 ), mkexpr( EA ) ) ); + + if ( host_endness == VexEndnessBE ) { + store( mkexpr( EA ), unop( Iop_V128to64, getVSReg( XTp ) ) ); + store( mkexpr( EA_8 ), unop( Iop_V128HIto64, getVSReg( XTp ) ) ); + store( mkexpr( EA_16 ), unop( Iop_V128to64, getVSReg( XTp+1 ) ) ); + store( mkexpr( EA_24 ), unop( Iop_V128HIto64, getVSReg( XTp+1 ) ) ); + + } else { + store( mkexpr( EA ), unop( Iop_V128to64, getVSReg( XTp+1 ) ) ); + store( mkexpr( EA_8 ), unop( Iop_V128HIto64, getVSReg( XTp+1 ) ) ); + store( mkexpr( EA_16 ), unop( Iop_V128to64, getVSReg( XTp ) ) ); + store( mkexpr( EA_24 ), unop( Iop_V128HIto64, getVSReg( XTp ) ) ); + } + break; + } + + default: + vex_printf("dis_vsx_vector_paired_load_store\n"); + return False; + } + + return True; +} + static Bool dis_vx_store ( UInt prefix, UInt theInstr ) { @@ -29997,6 +30111,11 @@ DisResult disInstr_PPC_WRK ( if (dis_trapi( prefix, theInstr, &dres)) goto decode_success; goto decode_failure; + case 0x06: // lxvp, stxvp + if (dis_fp_pair_prefix( prefix, theInstr )) + goto decode_success; + goto decode_failure; + /* Floating Point Load Instructions */ case 0x30: // lfs if (!allow_F) goto decode_noF; @@ -30137,13 +30256,19 @@ DisResult disInstr_PPC_WRK ( goto decode_failure; /* 64bit Integer Loads */ - case 0x3A: // word inst: ld, pld, ldu, lwa, plwa + case 0x3A: // word inst: ld, ldu, lwa { UChar b1_0 = IFIELD(theInstr, 0, 2); if (!mode64) goto decode_failure; - ISA_3_1_PREFIX_CHECK - if ((b1_0 >= 0) && (b1_0 <= 2)) { + if (prefix_instruction( prefix )) { // plxvp + if ( !(allow_isa_3_1) ) goto decode_noIsa3_1; + if (dis_fp_pair_prefix( prefix, theInstr )) + goto decode_success; + + } else if ((b1_0 >= 0) && (b1_0 <= 2)) { // ld, ldu, lwa, + /* Note, here we only deal with the non prefix versions + of the instructions. Hence do not check for ISA 3.1. */ if (dis_int_load_ds_form_prefix( prefix, theInstr )) goto decode_success; } @@ -30485,9 +30610,23 @@ DisResult disInstr_PPC_WRK ( } /* 64bit Integer Stores */ - case 0x3E: // std, stdu, stq - if (dis_int_store_ds_prefix( prefix, theInstr, abiinfo )) - goto decode_success; + case 0x3E: // std, stdu, stq, pstxvp + { + UChar b1_0 = IFIELD(theInstr, 2, 0); + + if (prefix_instruction( prefix)) { // pstxvp + if (dis_fp_pair_prefix( prefix, theInstr )) + goto decode_success; + + } else if (b1_0 != 3) { // std, stdu, stq + if (dis_int_store_ds_prefix( prefix, theInstr, abiinfo )) + goto decode_success; + + } else { + vex_printf("No mapping for instruction, opc1 = 0x3E, theInstr = 0x%x\n", + theInstr); + } + } goto decode_failure; case 0x3F: @@ -30833,6 +30972,12 @@ DisResult disInstr_PPC_WRK ( goto decode_success; goto decode_failure; + case 0x14D: // lxvpx + case 0x1CD: // stxvpx + if (dis_vsx_vector_paired_load_store( prefix, theInstr )) + goto decode_success; + goto decode_failure; + default: break; // Fall through... } |
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From: Carl L. <ca...@so...> - 2020-10-07 16:34:25
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=4e75ca1578fab30c02db29fdc3c91b7a66430492 commit 4e75ca1578fab30c02db29fdc3c91b7a66430492 Author: Carl Love <ce...@us...> Date: Tue Sep 22 12:30:43 2020 -0500 Add ISA 3.1 Set Boolean Extension instruction support Add support for the new ISA 3.1 set boolean condition word instructions: setbc Set Boolean Condition setbcr Set Boolean Condition Reverse setnbc Set Negative Boolean Condition setnbcr Set Negative Boolean Condition Reverse. Diff: --- VEX/priv/guest_ppc_toIR.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 4c0cbce454..aae8664ea5 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -6883,6 +6883,9 @@ static Bool dis_int_cmp ( UInt prefix, UInt theInstr ) case 0x080: // setb (Set Boolean) { + /* Set Boolean Condition in result register. The result register + is set to all ones if the condition is true and all zeros + otherwise. */ UChar rT_addr = ifieldRegDS(theInstr); Int bfa = IFIELD(theInstr, 18, 3); IRTemp cr = newTemp(Ity_I32); @@ -9141,6 +9144,73 @@ static Bool dis_cond_logic ( UInt prefix, UInt theInstr ) return True; } +static Bool dis_set_bool_condition ( UInt prefixInstr, UInt theInstr ) +{ + UInt opc2 = ifieldOPClo10(theInstr); + UChar BI = toUChar( IFIELD( theInstr, 16, 5 ) ); + UInt rT_addr = ifieldRegDS( theInstr ); + IRType ty = mode64 ? Ity_I64 : Ity_I32; + IROp Iop_1XtoX; + + /* There is no prefixed version of these instructions. */ + vassert( !prefix_instruction( prefixInstr ) ); + + switch (opc2) { + case 0x180: // setbc + /* If bit BI of the CR contains a 1, register RT is set to 1. + Otherwise, register RT is set to 0. */ + DIP(" setbc %u,%u\n", rT_addr, BI); + Iop_1XtoX = mode64 ? Iop_1Uto64 : Iop_1Uto32; + putIReg( rT_addr, unop( Iop_1XtoX, + binop( Iop_CmpEQ32, + getCRbit( BI ), + mkU32( 1 ) ) ) ); + break; + + case 0x1A0: // setbcr + /* If bit BI of the CR contains a 1, register RT is set to 0. + Otherwise, register RT is set to 1. */ + DIP(" setbcr %u,%u\n", rT_addr, BI); + Iop_1XtoX = mode64 ? Iop_1Uto64 : Iop_1Uto32; + putIReg( rT_addr, unop( Iop_1XtoX, + binop( Iop_CmpNE32, + getCRbit( BI ), + mkU32( 1 ) ) ) ); + break; + + case 0x1C0: // setnbc + /* If bit BI of the CR contains a 1, register RT is set to -1. + Otherwise, register RT is set to 0. */ + DIP(" setnbc %u,%u\n", rT_addr, BI); + Iop_1XtoX = mode64 ? Iop_1Sto64 : Iop_1Sto32; + putIReg( rT_addr, binop( mkSzOp(ty, Iop_And8), + mkSzImm( ty, -1 ), + unop( Iop_1XtoX, + binop( Iop_CmpEQ32, + getCRbit( BI ), + mkU32( 1 ) ) ) ) ); + break; + + case 0x1E0: // setnbcr + /* If bit BI of the CR contains a 1, register RT is set to -1. + Otherwise, register RT is set to 0. */ + DIP(" setnbcr %u,%u\n", rT_addr, BI); + Iop_1XtoX = mode64 ? Iop_1Sto64 : Iop_1Sto32; + putIReg( rT_addr, binop( mkSzOp(ty, Iop_And8), + mkSzImm( ty, -1 ), + unop( Iop_1XtoX, + binop( Iop_CmpNE32, + getCRbit( BI ), + mkU32( 1 ) ) ) ) ); + break; + + default: + vex_printf("dis_set_bool_condition(ppc)(opc2)\n"); + return False; + } + + return True; +} /* Trap instructions @@ -30067,7 +30137,7 @@ DisResult disInstr_PPC_WRK ( goto decode_failure; /* 64bit Integer Loads */ - case 0x3A: // word inst: ld, ldu, lwa + case 0x3A: // word inst: ld, pld, ldu, lwa, plwa { UChar b1_0 = IFIELD(theInstr, 0, 2); @@ -30756,6 +30826,13 @@ DisResult disInstr_PPC_WRK ( if (dis_int_logic( prefix, theInstr )) goto decode_success; goto decode_failure; + case 0x180: case 0x1A0: // setbc, setbcr + case 0x1C0: case 0x1E0: // setnbc, setnbcr + if (!allow_isa_3_0) goto decode_noIsa3_1; + if (dis_set_bool_condition( prefix, theInstr )) + goto decode_success; + goto decode_failure; + default: break; // Fall through... } |
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From: Carl L. <ca...@so...> - 2020-10-07 16:34:06
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=298a0b02c8a668578bfecd54d298d7c3a3c8127a commit 298a0b02c8a668578bfecd54d298d7c3a3c8127a Author: Carl Love <ce...@us...> Date: Tue Sep 22 12:25:14 2020 -0500 Add ISA 3.1 Byte-Reverse Instruction support Add support for the new ISA 3.1 word instructions: brd Byte-Reverse Doubleword brh Byte-Reverse Halfword brw Byte-Reverse Word Diff: --- VEX/priv/guest_ppc_toIR.c | 114 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 14e78aa8db..4c0cbce454 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -5270,6 +5270,114 @@ static void storeTMfailure( Addr64 err_address, ULong tm_reason, /*--- Integer Instruction Translation --- */ /*------------------------------------------------------------*/ +/* + Byte reverse instructions +*/ +static Bool dis_byte_reverse ( UInt prefixInstr, UInt theInstr ) +{ + UChar rS_addr = ifieldRegDS( theInstr ); + UChar rA_addr = ifieldRegA( theInstr ); + UInt opc2 = IFIELD( theInstr, 1, 10 ); + IRTemp rS = newTemp( Ity_I64 ); + IRTemp tmp_0 = newTemp( Ity_I64 ); + IRTemp tmp_1 = newTemp( Ity_I64 ); + IRTemp result = newTemp( Ity_I64 ); + + assign( rS, getIReg( rS_addr ) ); + + /* NOTE: rA is the destination and rS is the source. Reverse of the normal usage. */ + switch (opc2) { + case 0xDB: // brh Byte-Reverse half word X-form + DIP("brh r%u,r%u\n", rA_addr, rS_addr); + assign( tmp_0, + binop( Iop_And64, mkexpr( rS ), mkU64( 0xFF00FF00FF00FF00 ) ) ); + assign( tmp_1, + binop( Iop_And64, mkexpr( rS ), mkU64( 0x00FF00FF00FF00FF ) ) ); + assign( result, + binop( Iop_Or64, + binop( Iop_Shr64, mkexpr( tmp_0 ), mkU8( 8 ) ), + binop( Iop_Shl64, mkexpr( tmp_1 ), mkU8( 8 ) ) ) ); + break; + + case 0x9B: { // brw Byte-Reverse word X-form + IRTemp tmp_2 = newTemp( Ity_I64 ); + IRTemp tmp_3 = newTemp( Ity_I64 ); + + DIP("brw r%u,r%u\n", rA_addr, rS_addr); + assign( tmp_0, + binop( Iop_And64, mkexpr( rS ), mkU64( 0xFF000000FF000000 ) ) ); + assign( tmp_1, + binop( Iop_And64, mkexpr( rS ), mkU64( 0x00FF000000FF0000 ) ) ); + assign( tmp_2, + binop( Iop_And64, mkexpr( rS ), mkU64( 0x0000FF000000FF00 ) ) ); + assign( tmp_3, + binop( Iop_And64, mkexpr( rS ), mkU64( 0x000000FF000000FF ) ) ); + assign( result, + binop( Iop_Or64, + binop( Iop_Or64, + binop( Iop_Shl64, mkexpr( tmp_3 ), mkU8( 24 ) ), + binop( Iop_Shl64, mkexpr( tmp_2 ), mkU8( 8 ) ) ), + binop( Iop_Or64, + binop( Iop_Shr64, mkexpr( tmp_1 ), mkU8( 8 ) ), + binop( Iop_Shr64, mkexpr( tmp_0 ), mkU8( 24 ) ) ) + ) ); + break; + } + + case 0xBB: { // brd Byte-Reverse double word X-form + IRTemp tmp_2 = newTemp( Ity_I64 ); + IRTemp tmp_3 = newTemp( Ity_I64 ); + IRTemp tmp_4 = newTemp( Ity_I64 ); + IRTemp tmp_5 = newTemp( Ity_I64 ); + IRTemp tmp_6 = newTemp( Ity_I64 ); + IRTemp tmp_7 = newTemp( Ity_I64 ); + + DIP("brd r%u,r%u\n", rA_addr, rS_addr); + assign( tmp_0, + binop( Iop_And64, mkexpr( rS ), mkU64( 0xFF00000000000000 ) ) ); + assign( tmp_1, + binop( Iop_And64, mkexpr( rS ), mkU64( 0x00FF000000000000 ) ) ); + assign( tmp_2, + binop( Iop_And64, mkexpr( rS ), mkU64( 0x0000FF0000000000 ) ) ); + assign( tmp_3, + binop( Iop_And64, mkexpr( rS ), mkU64( 0x000000FF00000000 ) ) ); + assign( tmp_4, + binop( Iop_And64, mkexpr( rS ), mkU64( 0x00000000FF000000 ) ) ); + assign( tmp_5, + binop( Iop_And64, mkexpr( rS ), mkU64( 0x0000000000FF0000 ) ) ); + assign( tmp_6, + binop( Iop_And64, mkexpr( rS ), mkU64( 0x000000000000FF00 ) ) ); + assign( tmp_7, + binop( Iop_And64, mkexpr( rS ), mkU64( 0x00000000000000FF ) ) ); + assign( result, + binop( Iop_Or64, + binop( Iop_Or64, + binop( Iop_Or64, + binop( Iop_Shl64, mkexpr( tmp_7 ), mkU8( 56 ) ), + binop( Iop_Shl64, mkexpr( tmp_6 ), mkU8( 40 ) ) ), + binop( Iop_Or64, + binop( Iop_Shl64, mkexpr( tmp_5 ), mkU8( 24 ) ), + binop( Iop_Shl64, mkexpr( tmp_4 ), mkU8( 8 ) ) ) ), + binop( Iop_Or64, + binop( Iop_Or64, + binop( Iop_Shr64, mkexpr( tmp_3 ), mkU8( 8 ) ), + binop( Iop_Shr64, mkexpr( tmp_2 ), mkU8( 24 ) ) ), + binop( Iop_Or64, + binop( Iop_Shr64, mkexpr( tmp_1 ), mkU8( 40 ) ), + binop( Iop_Shr64, mkexpr( tmp_0 ), mkU8( 56 ) ) ) ) + ) ); + break; + } + + default: + vex_printf("dis_byte_reverse(ppc): unrecognized instruction\n"); + return False; + } + + putIReg( rA_addr, mkexpr( result ) ); + return True; +} + /* Integer Arithmetic Instructions */ @@ -30657,6 +30765,12 @@ DisResult disInstr_PPC_WRK ( opc2 = IFIELD(theInstr, 1, 10); switch (opc2) { + case 0xDB: // brh + case 0x9B: // brw + case 0xBB: // brd + if (dis_byte_reverse( prefix, theInstr )) goto decode_success; + goto decode_failure; + /* Integer miscellaneous instructions */ case 0x01E: // wait RFC 2500 if (dis_int_misc( prefix, theInstr )) goto decode_success; |
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From: Michael F. <mf...@mf...> - 2020-10-07 00:31:31
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The == operator is non-standard, use = instead.
---
I noticed this through some automated shell portability checks in
pkgsrc:
ERROR: [check-portability.awk] => Found test ... == ...:
ERROR: [check-portability.awk] configure:5717: if test "$ac_cv_prog_cc_c99" == "no"; then
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 085c98993..cfd3ed59f 100755
--- a/configure.ac
+++ b/configure.ac
@@ -115,7 +115,7 @@ rm $tmpfile
# Make sure we can compile in C99 mode.
AC_PROG_CC_C99
-if test "$ac_cv_prog_cc_c99" == "no"; then
+if test "$ac_cv_prog_cc_c99" = "no"; then
AC_MSG_ERROR([Valgrind relies on a C compiler supporting C99])
fi
--
2.28.0
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