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From: Carl L. <ce...@us...> - 2020-06-04 22:28:16
|
Mark: > > On Thu, 2020-06-04 at 09:54 -0700, Carl Love wrote: > > Now that Valgrind 3.16 is out and IBM has announced the latest > > Power > > ISA 3.1 we would like to start pushing out patches to Valgrind > > mainline > > for the new ISA instruction support. You can find the ISA 3.1 at: > > > > https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0 > > Silly question maybe, but is Power10 instruction set (which I saw > recent binutils supports) an "implementation" of the Power ISA 3.1? > Can > the terms Power10 and Power ISA 3.1 be used interchangeably or is > there > a subtle difference? Power 10 will implement the ISA 3.1. Carl Love |
|
From: Mark W. <ma...@kl...> - 2020-06-04 18:07:10
|
Hi Carl, On Thu, 2020-06-04 at 09:54 -0700, Carl Love wrote: > Now that Valgrind 3.16 is out and IBM has announced the latest Power > ISA 3.1 we would like to start pushing out patches to Valgrind mainline > for the new ISA instruction support. You can find the ISA 3.1 at: > > https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0 Silly question maybe, but is Power10 instruction set (which I saw recent binutils supports) an "implementation" of the Power ISA 3.1? Can the terms Power10 and Power ISA 3.1 be used interchangeably or is there a subtle difference? Thanks, Mark |
|
From: Carl L. <ce...@us...> - 2020-06-04 16:54:37
|
Julian: Now that Valgrind 3.16 is out and IBM has announced the latest Power ISA 3.1 we would like to start pushing out patches to Valgrind mainline for the new ISA instruction support. You can find the ISA 3.1 at: https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0 The key change in this ISA is that Power will now support 64-bit and 32-bit instructions. The ISA adds a couple hundred new instructions as well. The 64-bit instructions are referred to as prefix instructions. A 32-bit instruction is referred to as a word instruction. Most prefix instruction names start with a "p". This is always true when there is a word and prefixed version of the instruction. For example instruction foo and prefix instruction pfoo. New instructions that do not have a word equivalent do not always have the leading "p" in the instruction name. A prefix instruction consists of a 32-bit prefix word with bits [0:5] (IBM numbering left to right) set to 1. The rest of the prefix word contains fields for larger immediate values and additional instruction arguments. The actual instruction opcode, register designators etc. will be found in the following 32-bit word in essentially the same instruction layout seen for the existing 32-bit instructions. Generally speaking the opc1, opc2 values for a prefixed instruction will match the opc1 and opc2 values for the equivalent word instruction but unfortunately this is not always the case. The exceptions make the parsing of prefix instructions a bit more complicated. The immediate value for a prefix instruction consists of the immediate value for the word instruction combined with additional bits from the prefix word as mentioned above. We have a series of functional patches that add the new ISA 3.1 instruction support and corresponding series of test-suite patches to test the instructions added with each functional patch. Currently the functional patch series consists of 17 patches. We are still working to polish up the last two functional patches. Some of the latter functional patches will require some discussion. There are some rather complex instructions that cannot be done strictly with IOps as they are really complex and would generate more iops then the buffer space. These instructions were implemented with clean helpers. We chose to do that rather then introduce a new iop as no other architecture is likely to every have a similar instruction. From a development standpoint, it gave an independent instruction implementation in Valgrind that could be used to verify the accuracy of the internal ISA 3.1 simulator. The new Valgrind support found "several" internal simulator bugs. When we get to these patches, we can discuss if we want to go with the clean helpers or change to supporting the instructions with new IOps. The various tests have been run on the internal simulator to generate the expected result files. The expected output was then compared with the Valgrind results. When differences were found, we had to investigate to determine if the error was in the Valgrind or internal simulator. With that introduction, please let us know if you have questions. We hope to post the first functional patch and test case soon. The first functional patch lays the ground work for the prefix instruction support and adds support for a couple of new instructions. This will be good look at the new functionality. The plan is then to push out a couple of functional patches and corresponding test-suite patches at a time for review to keep things a bit more manageable as well as get the patches reviewed and accepted in a reasonable time frame. Ideally we would get everything done for the 3.17 release but that is probably not practical. Carl Love and Will Schmidt |