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From: Carl L. <ca...@so...> - 2020-06-15 18:39:48
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=8151414f0c150a81b06c95a3eaab87a2558521a8 commit 8151414f0c150a81b06c95a3eaab87a2558521a8 Author: Carl Love <ce...@us...> Date: Mon Jun 15 11:31:16 2020 -0500 Bugzilla 423021 - PPC: Add missing ISA 3.0 documentation link and HWCAPS test. Add the check for the PPC_FEATURE2_ARCH_3_00 setting in the HWCAP2 string. Add the information on where to find the public IBM ISA 3.0B document. Diff: --- NEWS | 1 + coregrind/m_initimg/initimg-linux.c | 24 +++++++++++++++++++++++- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/NEWS b/NEWS index e23c449166..0ffcb5bf9f 100644 --- a/NEWS +++ b/NEWS @@ -42,6 +42,7 @@ where XXXXXX is the bug number as listed below. 345077 linux syscall execveat support (linux 3.19) n-i-bz helgrind: If hg_cli__realloc fails, return NULL. +423021 PPC: Add missing ISA 3.0 documentation link and HWCAPS test. Release 3.16.1 (?? June 2020) diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c index bab8aeca0f..e811ff667d 100644 --- a/coregrind/m_initimg/initimg-linux.c +++ b/coregrind/m_initimg/initimg-linux.c @@ -720,6 +720,8 @@ Addr setup_client_stack( void* init_sp, # if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) case AT_HWCAP2: { Bool auxv_2_07, hw_caps_2_07; + Bool auxv_3_0, hw_caps_3_0; + /* The HWCAP2 field may contain an arch_2_07 entry that indicates * if the processor is compliant with the 2.07 ISA. (i.e. Power 8 * or beyond). The Valgrind vai.hwcaps value @@ -752,7 +754,27 @@ Addr setup_client_stack( void* init_sp, * matches the setting in VEX HWCAPS. */ vg_assert(auxv_2_07 == hw_caps_2_07); - } + + /* Power ISA version 3.0B + March 29, 2017 + https://ibm.ent.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv + + https://openpowerfoundation.org/technical/resource-catalog/ + http://openpowerfoundation.org/wp-content/uploads/resources/leabi/leabi-20170510.pdf + 64-bit ELF V2 ABI specification for Power. HWCAP2 bit pattern + for ISA 3.0, page 112. + + */ + /* ISA 3.0 */ + auxv_3_0 = (auxv->u.a_val & 0x00800000ULL) == 0x00800000ULL; + hw_caps_3_0 = (vex_archinfo->hwcaps & VEX_HWCAPS_PPC64_ISA3_0) + == VEX_HWCAPS_PPC64_ISA3_0; + + /* Verify the PPC_FEATURE2_ARCH_3_00 setting in HWCAP2 + * matches the setting in VEX HWCAPS. + */ + vg_assert(auxv_3_0 == hw_caps_3_0); + } break; # endif |
|
From: John R. <jr...@bi...> - 2020-06-15 03:23:38
|
> I found it difficult for me to support SVE instruction. > We want to profile with Valgrind/Cachegrind on the Fugaku super-computer. > As a future task, could you (community) consider supporting SVE. Please give URL pointers to the specific documentation (in English) for SVE. Having to hunt for documentation is a significant impediment to implementation. After that, where is the qemu+gdb emulator so that an implementation can be tested on amd64 (x86_64)? Also, please compare and contrast SVE to similar implementations for other architectures, perhaps including PowerPC Altivec, ARM NEON, Intel AVX/AVX2/AVX512, etc. |
|
From: <ton...@fu...> - 2020-06-15 03:06:34
|
Dear Mark and developers, thank you for your reply and sorry for my late reply. > You don't say what your setup is based on. But from you question below I > assume it is ARM64 based. Valgrind already does mostly work on ARM64 > (GNU/Linux based at least). You can start with the README_DEVELOPERS to > get a working setup that you can hack on: I got some information from the following sites. > https://sourceware.org/git/?p=valgrind.git;a=blob;f=README_DEVELOPERS > https://sourceware.org/git/?p=valgrind.git;a=blob;f=cachegrind/cg_arch.c Cache configuration can be specified with the valgrind options (--I1=, --D1=, ...), so I think no problem on our architecture A64FX. I found it difficult for me to support SVE instruction. We want to profile with Valgrind/Cachegrind on the Fugaku super-computer. As a future task, could you (community) consider supporting SVE. Best regards, Tomotake Nakamura FUJITSU > -----Original Message----- > From: Mark Wielaard <ma...@kl...> > Sent: Wednesday, May 27, 2020 8:50 PM > To: Nakamura, Tomotake/中村 朋健 <ton...@fu...> > Cc: 'val...@li...' > <val...@li...> > Subject: Re: [Valgrind-developers] valgrind porting > > Hi, > > On Wed, May 27, 2020 at 02:23:14AM +0000, ton...@fu... wrote: > > I would like to port Valgrind for Fujitsu supercomputer (FX1000). > > I'm a beginner and I don't know much about it. Could you please teach me? > > You don't say what your setup is based on. But from you question below I > assume it is ARM64 based. Valgrind already does mostly work on ARM64 > (GNU/Linux based at least). You can start with the README_DEVELOPERS to > get a working setup that you can hack on: > https://sourceware.org/git/?p=valgrind.git;a=blob;f=README_DEVELOPER > S > > > I don't know the program structure of Valgrind and Cachegrind. > > My guess is that Cachegrind may be able to obtain information about > > cache misses, etc. after understanding the hardware specifications of > > the CPU (cache size, number of ways, etc.). > > How should the hardware specifications be used as input values to Valgrind? > > You might want to look over cachegrind/cg_arch.c: > https://sourceware.org/git/?p=valgrind.git;a=blob;f=cachegrind/cg_arch.c > > > I also would like to implement Scalable Vector Extension (SVE) > > instructions which are an extension instructions of ArmV8. Would you > > please tell me porting procedures? > > There are several bugs about adding more arm64 instruction sets, you might > want to start by reading over some: > https://bugs.kde.org/show_bug.cgi?id=369509 > https://bugs.kde.org/show_bug.cgi?id=413547 > https://bugs.kde.org/show_bug.cgi?id=414268 > > Cheers, > > Mark |