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From: Andreas A. <ar...@so...> - 2020-04-08 17:59:40
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=6a90a15b9c0cbf38b6a9f17e5fa28199e155de73 commit 6a90a15b9c0cbf38b6a9f17e5fa28199e155de73 Author: Andreas Arnez <ar...@li...> Date: Fri Apr 3 19:16:01 2020 +0200 s390x: Drop spurious register moves in CDAS instruction selector The s390x instruction selector for Ist_CAS, in its handling of "compare double and swap", adds spurious register moves after the CDAS operation itself. These moves overwrite registers returned by calls to s390_isel_int_expr(), potentially causing corruption of temp values. Delete the spurious move operations after CDAS. Diff: --- VEX/priv/host_s390_isel.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index 882e72cd6c..2f80dd8504 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -5185,10 +5185,6 @@ no_memcpy_put: addInstr(env, s390_insn_cdas(8, r8, r9, op2, r10, r11, old_high, old_low, r1)); } - addInstr(env, s390_insn_move(8, op1_high, r8)); - addInstr(env, s390_insn_move(8, op1_low, r9)); - addInstr(env, s390_insn_move(8, op3_high, r10)); - addInstr(env, s390_insn_move(8, op3_low, r11)); return; } break; |
|
From: Andreas A. <ar...@so...> - 2020-04-08 17:59:32
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=4970e20020cb80aa6b8ee80d53cefc409790547b commit 4970e20020cb80aa6b8ee80d53cefc409790547b Author: Andreas Arnez <ar...@li...> Date: Thu Apr 2 20:40:02 2020 +0200 s390x: Fix Iex_Load instruction selectors for F128/D128 types The s390x instruction selectors for Iex_Load of Ity_F128 and Ity_D128 types had a common typo that would lead to crashes when used. So far this bug didn't surface because Iex_Load is not emitted on s390x with these types. This fixes the typo. Diff: --- VEX/priv/host_s390_isel.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index ec042fb117..882e72cd6c 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -2137,7 +2137,7 @@ s390_isel_float128_expr_wrk(HReg *dst_hi, HReg *dst_lo, ISelEnv *env, *dst_hi = newVRegF(env); *dst_lo = newVRegF(env); addInstr(env, s390_insn_load(8, *dst_hi, am_hi)); - addInstr(env, s390_insn_load(8, *dst_hi, am_lo)); + addInstr(env, s390_insn_load(8, *dst_lo, am_lo)); return; } @@ -2845,7 +2845,7 @@ s390_isel_dfp128_expr_wrk(HReg *dst_hi, HReg *dst_lo, ISelEnv *env, *dst_hi = newVRegF(env); *dst_lo = newVRegF(env); addInstr(env, s390_insn_load(8, *dst_hi, am_hi)); - addInstr(env, s390_insn_load(8, *dst_hi, am_lo)); + addInstr(env, s390_insn_load(8, *dst_lo, am_lo)); return; } |
|
From: Andreas A. <ar...@so...> - 2020-04-08 17:59:24
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=4e9763c617757712747e076b5d03bbb60a91c729 commit 4e9763c617757712747e076b5d03bbb60a91c729 Author: Andreas Arnez <ar...@li...> Date: Thu Apr 2 18:00:13 2020 +0200 s390x: Introduce and exploit new ALU operator S390_ALU_ILIH The handlers of Iop_8HLto16, Iop16HLto32, and Iop_32HLto64 in s390_isel_int_wrk() yield a sequence of "shift", "and", and "or" ALU operations, the second of which modifies a register returned from a call to s390_isel_int_expr(). While this approach does not lead to wrong code generation (because only the register's upper bits are changed which are not relevant to the IR type), it violates the general "no-modify" rule. Replace this sequence of ALU operations by a single ALU operation S390_ALU_ILIH that inserts the low half of its second operand into the high half of its first operand. Use the z/Architecture instruction RISBG ("rotate then insert selected bits") for implementating it. Diff: --- VEX/priv/host_s390_defs.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++ VEX/priv/host_s390_defs.h | 2 ++ VEX/priv/host_s390_isel.c | 10 +++------ 3 files changed, 62 insertions(+), 7 deletions(-) diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index 308b6ff409..3b6121fec3 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -1508,6 +1508,22 @@ emit_RIE(UChar *p, ULong op, UChar r1, UShort i2, UChar m3) } +static UChar * +emit_RIEf(UChar *p, ULong op, UChar r1, UChar r2, + UChar i3, Char i4, UChar i5) +{ + ULong the_insn = op; + + the_insn |= ((ULong)r1) << 36; + the_insn |= ((ULong)r2) << 32; + the_insn |= ((ULong)i3) << 24; + the_insn |= ((ULong)i4) << 16; + the_insn |= ((ULong)i5) << 8; + + return emit_6bytes(p, the_insn); +} + + static UChar * emit_RR(UChar *p, UInt op, UChar r1, UChar r2) { @@ -5265,6 +5281,16 @@ s390_emit_LOCGHI(UChar *p, UChar r1, UShort i2, UChar m3) return emit_RIE(p, 0xec0000000046ULL, r1, i2, m3); } +static UChar * +s390_emit_RISBG(UChar *p, UChar r1, UChar r2, UChar i3, Char i4, UChar i5) +{ + if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) + s390_disasm(ENC6(MNM, GPR, GPR, UINT, UINT, UINT), + "risbg", r1, r2, i3, i4, i5); + + return emit_RIEf(p, 0xec0000000055ULL, r1, r2, i3, i4, i5); +} + /* Provide a symbolic name for register "R0" */ #define R0 0 @@ -7759,6 +7785,7 @@ s390_insn_as_string(const s390_insn *insn) case S390_ALU_LSH: op = "v-lsh"; break; case S390_ALU_RSH: op = "v-rsh"; break; case S390_ALU_RSHA: op = "v-rsha"; break; + case S390_ALU_ILIH: op = "v-ilih"; break; default: goto fail; } s390_sprintf(buf, "%M %R,%O", op, insn->variant.alu.dst, /* also op1 */ @@ -8677,6 +8704,24 @@ s390_insn_load_immediate_emit(UChar *buf, const s390_insn *insn) } +/* Insert low half of r2 into high half of dst. */ +static UChar * +s390_emit_ilih(UChar *buf, UChar size, UChar dst, UChar r2) +{ + if (s390_host_has_gie) + return s390_emit_RISBG(buf, dst, r2, 64 - 8 * size, 63 - 4 * size, + 4 * size); + + /* Clear dst's upper half. */ + buf = s390_emit_SLLG(buf, dst, dst, 0, DISP20(64 - 4 * size)); + buf = s390_emit_SRLG(buf, dst, dst, 0, DISP20(64 - 4 * size)); + + /* Shift r2 by appropriate amount and OR it into dst. */ + buf = s390_emit_SLLG(buf, R0, r2, 0, DISP20(4 * size)); + return s390_emit_OGR(buf, dst, R0); +} + + /* There is no easy way to do ALU operations on 1-byte or 2-byte operands. So we simply perform a 4-byte operation. Doing so uses possibly undefined bits and produces an undefined result in those extra bit positions. But @@ -8708,6 +8753,7 @@ s390_insn_alu_emit(UChar *buf, const s390_insn *insn) case S390_ALU_LSH: return s390_emit_SLL(buf, dst, r2, 0); case S390_ALU_RSH: return s390_emit_SRL(buf, dst, r2, 0); case S390_ALU_RSHA: return s390_emit_SRA(buf, dst, r2, 0); + case S390_ALU_ILIH: return s390_emit_ilih(buf, insn->size, dst, r2); } goto fail; @@ -8722,6 +8768,7 @@ s390_insn_alu_emit(UChar *buf, const s390_insn *insn) case S390_ALU_LSH: return s390_emit_SLLG(buf, dst, dst, r2, DISP20(0)); case S390_ALU_RSH: return s390_emit_SRLG(buf, dst, dst, r2, DISP20(0)); case S390_ALU_RSHA: return s390_emit_SRAG(buf, dst, dst, r2, DISP20(0)); + case S390_ALU_ILIH: return s390_emit_ilih(buf, 8, dst, r2); } goto fail; } @@ -8802,6 +8849,7 @@ s390_insn_alu_emit(UChar *buf, const s390_insn *insn) case S390_ALU_AND: return s390_emit_NR(buf, dst, R0); case S390_ALU_OR: return s390_emit_OR(buf, dst, R0); case S390_ALU_XOR: return s390_emit_XR(buf, dst, R0); + case S390_ALU_ILIH: case S390_ALU_LSH: case S390_ALU_RSH: case S390_ALU_RSHA: ; /* avoid GCC warning */ @@ -8836,6 +8884,7 @@ s390_insn_alu_emit(UChar *buf, const s390_insn *insn) buf = s390_emit_LH(buf, R0, x, b, d); return s390_emit_XR(buf, dst, R0); + case S390_ALU_ILIH: case S390_ALU_LSH: case S390_ALU_RSH: case S390_ALU_RSHA: ; /* avoid GCC warning */ @@ -8868,6 +8917,7 @@ s390_insn_alu_emit(UChar *buf, const s390_insn *insn) buf = s390_emit_LHY(buf, R0, x, b, DISP20(d)); return s390_emit_XR(buf, dst, R0); + case S390_ALU_ILIH: case S390_ALU_LSH: case S390_ALU_RSH: case S390_ALU_RSHA: ; /* avoid GCC warning */ @@ -8887,6 +8937,7 @@ s390_insn_alu_emit(UChar *buf, const s390_insn *insn) case S390_ALU_AND: return s390_emit_N(buf, dst, x, b, d); case S390_ALU_OR: return s390_emit_O(buf, dst, x, b, d); case S390_ALU_XOR: return s390_emit_X(buf, dst, x, b, d); + case S390_ALU_ILIH: case S390_ALU_LSH: case S390_ALU_RSH: case S390_ALU_RSHA: ; /* avoid GCC warning */ @@ -8902,6 +8953,7 @@ s390_insn_alu_emit(UChar *buf, const s390_insn *insn) case S390_ALU_AND: return s390_emit_NY(buf, dst, x, b, DISP20(d)); case S390_ALU_OR: return s390_emit_OY(buf, dst, x, b, DISP20(d)); case S390_ALU_XOR: return s390_emit_XY(buf, dst, x, b, DISP20(d)); + case S390_ALU_ILIH: case S390_ALU_LSH: case S390_ALU_RSH: case S390_ALU_RSHA: ; /* avoid GCC warning */ @@ -8918,6 +8970,7 @@ s390_insn_alu_emit(UChar *buf, const s390_insn *insn) case S390_ALU_AND: return s390_emit_NG(buf, dst, x, b, DISP20(d)); case S390_ALU_OR: return s390_emit_OG(buf, dst, x, b, DISP20(d)); case S390_ALU_XOR: return s390_emit_XG(buf, dst, x, b, DISP20(d)); + case S390_ALU_ILIH: case S390_ALU_LSH: case S390_ALU_RSH: case S390_ALU_RSHA: ; /* avoid GCC warning */ @@ -8965,6 +9018,8 @@ s390_insn_alu_emit(UChar *buf, const s390_insn *insn) case S390_ALU_RSHA: return s390_emit_SRA(buf, dst, 0, value); + + case S390_ALU_ILIH: ; /* avoid GCC warning */ } goto fail; @@ -8984,6 +9039,7 @@ s390_insn_alu_emit(UChar *buf, const s390_insn *insn) case S390_ALU_LSH: return s390_emit_SLL(buf, dst, 0, value); case S390_ALU_RSH: return s390_emit_SRL(buf, dst, 0, value); case S390_ALU_RSHA: return s390_emit_SRA(buf, dst, 0, value); + case S390_ALU_ILIH: ; /* avoid GCC warning */ } goto fail; @@ -9052,6 +9108,7 @@ s390_insn_alu_emit(UChar *buf, const s390_insn *insn) case S390_ALU_LSH: return s390_emit_SLLG(buf, dst, dst, 0, DISP20(value)); case S390_ALU_RSH: return s390_emit_SRLG(buf, dst, dst, 0, DISP20(value)); case S390_ALU_RSHA: return s390_emit_SRAG(buf, dst, dst, 0, DISP20(value)); + case S390_ALU_ILIH: ; /* avoid GCC warning */ } goto fail; } diff --git a/VEX/priv/host_s390_defs.h b/VEX/priv/host_s390_defs.h index c8ec665377..3f6473e10b 100644 --- a/VEX/priv/host_s390_defs.h +++ b/VEX/priv/host_s390_defs.h @@ -178,6 +178,8 @@ typedef enum { S390_ALU_AND, S390_ALU_OR, S390_ALU_XOR, + S390_ALU_ILIH, /* insert low half of 2nd operand into high half of 1st + operand */ S390_ALU_LSH, S390_ALU_RSH, S390_ALU_RSHA /* arithmetic */ diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index 6d34ca5d63..ec042fb117 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -1423,13 +1423,9 @@ s390_isel_int_expr_wrk(ISelEnv *env, IRExpr *expr) h1 = s390_isel_int_expr(env, arg1); /* Process 1st operand */ h2 = s390_isel_int_expr(env, arg2); /* Process 2nd operand */ - addInstr(env, s390_insn_move(arg_size, res, h1)); - value = s390_opnd_imm(arg_size * 8); - addInstr(env, s390_insn_alu(size, S390_ALU_LSH, res, value)); - value = s390_opnd_imm((((ULong)1) << arg_size * 8) - 1); - addInstr(env, s390_insn_alu(size, S390_ALU_AND, h2, value)); - opnd = s390_opnd_reg(h2); - addInstr(env, s390_insn_alu(size, S390_ALU_OR, res, opnd)); + addInstr(env, s390_insn_move(arg_size, res, h2)); + opnd = s390_opnd_reg(h1); + addInstr(env, s390_insn_alu(size, S390_ALU_ILIH, res, opnd)); return res; } |
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From: Andreas A. <ar...@so...> - 2020-04-08 17:59:14
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=1008ab726d43efd7e68225a56cc823a18eca8780 commit 1008ab726d43efd7e68225a56cc823a18eca8780 Author: Andreas Arnez <ar...@li...> Date: Thu Apr 2 16:19:32 2020 +0200 s390x: Fix typos in comments for sub_from_SP and add_to_SP in isel The comments for sub_from_SP() and add_to_SP() in host_s390_isel.c have typos. Fix them. Diff: --- VEX/priv/host_s390_isel.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index ce68b35c7f..6d34ca5d63 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -514,7 +514,7 @@ get_const_value_as_ulong(const IRConst *con) } -/* Substract n from stack pointer. Assumes 0 <= n <= 256 && n % 8 == 0. */ +/* Subtract n from stack pointer. Assumes 0 <= n <= 256 && n % 8 == 0. */ static void sub_from_SP ( ISelEnv* env, UInt n ) { @@ -525,7 +525,7 @@ sub_from_SP ( ISelEnv* env, UInt n ) } -/* Substract n from stack pointer. Assumes 0 <= n <= 256 && n % 8 == 0. */ +/* Add n to stack pointer. Assumes 0 <= n <= 256 && n % 8 == 0. */ static void add_to_SP ( ISelEnv* env, UInt n ) { |
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From: Andreas A. <ar...@so...> - 2020-04-08 17:59:05
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e00bd722becf198447a4f7293c3d54e2d7f9baa2 commit e00bd722becf198447a4f7293c3d54e2d7f9baa2 Author: Andreas Arnez <ar...@li...> Date: Wed Mar 18 18:59:15 2020 +0100 s390x: Drop register arg to s390_isel_int1_expr() Restructure the interface of s390_isel_int1_expr() such that no destination register is passed to it any more. Adjust all its callers accordingly. Ensure that callers never modify the returned register, but make a copy and modify that instead. Diff: --- VEX/priv/host_s390_isel.c | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index e96c7209f1..ce68b35c7f 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -127,7 +127,7 @@ static HReg s390_isel_int_expr(ISelEnv *, IRExpr *); static s390_amode *s390_isel_amode(ISelEnv *, IRExpr *); static s390_amode *s390_isel_amode_b12_b20(ISelEnv *, IRExpr *); static s390_cc_t s390_isel_cc(ISelEnv *, IRExpr *); -static HReg s390_isel_int1_expr(ISelEnv *env, IRExpr *expr, HReg dst); +static HReg s390_isel_int1_expr(ISelEnv *env, IRExpr *expr); static s390_opnd_RMI s390_isel_int_expr_RMI(ISelEnv *, IRExpr *); static void s390_isel_int128_expr(HReg *, HReg *, ISelEnv *, IRExpr *); static HReg s390_isel_float_expr(ISelEnv *, IRExpr *); @@ -1764,7 +1764,9 @@ s390_isel_int_expr_wrk(ISelEnv *env, IRExpr *expr) /* Expressions whose argument is 1-bit wide */ if (typeOfIRExpr(env->type_env, arg) == Ity_I1) { - dst = s390_isel_int1_expr(env, arg, INVALID_HREG); + h1 = s390_isel_int1_expr(env, arg); + dst = newVRegI(env); + addInstr(env, s390_insn_move(8, dst, h1)); switch (unop) { case Iop_1Uto8: @@ -3558,7 +3560,7 @@ s390_isel_cc(ISelEnv *env, IRExpr *cond) if (cond->Iex.Binop.op == Iop_And1 || cond->Iex.Binop.op == Iop_Or1) { /* Perform the calculation in registers, but ignore the resulting value. Instead, assume that the condition code is set. */ - (void) s390_isel_int1_expr(env, cond, INVALID_HREG); + (void) s390_isel_int1_expr(env, cond); return S390_CC_NE; } @@ -3689,34 +3691,30 @@ s390_isel_cc(ISelEnv *env, IRExpr *cond) values in registers always sign-extended to 64 bits. This function is mutually recursive with s390_isel_cc. */ static HReg -s390_isel_int1_expr(ISelEnv *env, IRExpr *expr, HReg dst) +s390_isel_int1_expr(ISelEnv *env, IRExpr *expr) { vassert(expr); vassert(typeOfIRExpr(env->type_env, expr) == Ity_I1); /* Variable. */ - if (expr->tag == Iex_RdTmp) { - HReg res = lookupIRTemp(env, expr->Iex.RdTmp.tmp); - if (hregIsInvalid(dst)) { - return res; - } - addInstr(env, s390_insn_move(8, dst, res)); - return dst; - } + if (expr->tag == Iex_RdTmp) + return lookupIRTemp(env, expr->Iex.RdTmp.tmp); - HReg res = hregIsInvalid(dst) ? newVRegI(env) : dst; + HReg res = newVRegI(env); /* And1 / Or1 */ if (expr->tag == Iex_Binop && (expr->Iex.Binop.op == Iop_And1 || expr->Iex.Binop.op == Iop_Or1)) { - HReg reg1 = s390_isel_int1_expr(env, expr->Iex.Binop.arg1, res); - HReg reg2 = s390_isel_int1_expr(env, expr->Iex.Binop.arg2, INVALID_HREG); + HReg reg1 = s390_isel_int1_expr(env, expr->Iex.Binop.arg1); + HReg reg2 = s390_isel_int1_expr(env, expr->Iex.Binop.arg2); s390_alu_t opkind = expr->Iex.Binop.op == Iop_And1 ? S390_ALU_AND : S390_ALU_OR; + addInstr(env, s390_insn_move(8, res, reg1)); + /* Ensure that the condition code is set; s390_isel_cc relies on it. */ - addInstr(env, s390_insn_alu(8, opkind, reg1, s390_opnd_reg(reg2))); - return reg1; + addInstr(env, s390_insn_alu(8, opkind, res, s390_opnd_reg(reg2))); + return res; } /* Else, call s390_isel_cc and force the value into a register. */ @@ -5018,8 +5016,9 @@ no_memcpy_put: break; case Ity_I1: { + src = s390_isel_int1_expr(env, stmt->Ist.WrTmp.data); dst = lookupIRTemp(env, tmp); - dst = s390_isel_int1_expr(env, stmt->Ist.WrTmp.data, dst); + addInstr(env, s390_insn_move(8, dst, src)); return; } |
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From: Andreas A. <ar...@so...> - 2020-04-08 17:35:44
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=dd627dc127a6767c497f027de6eab634815f7861 commit dd627dc127a6767c497f027de6eab634815f7861 Author: Andreas Arnez <ar...@li...> Date: Tue Feb 11 18:02:38 2020 +0100 s390x: Activate "grail" Now that the known problems with activating "grail" on s390x have been fixed, there is no need to disable it for s390x guests any more. Remove the appropriate check in "guest_generic_bb_to_IR.c". Diff: --- VEX/priv/guest_generic_bb_to_IR.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/VEX/priv/guest_generic_bb_to_IR.c b/VEX/priv/guest_generic_bb_to_IR.c index 7bc7b6dbba..5932eb8043 100644 --- a/VEX/priv/guest_generic_bb_to_IR.c +++ b/VEX/priv/guest_generic_bb_to_IR.c @@ -1449,11 +1449,6 @@ IRSB* bb_to_IR ( // hope of identifying and recovering, an "A && B" condition spread across // two basic blocks. if (irsb_be.tag == Be_Cond - /* sewardj 2019Nov30: Alas, chasing cond branches on s390 causes - Memcheck to crash, for as-yet unknown reasons. It also exposes - some unhandled Iex_ITE cases in the s390x instruction selector. - For now, disable. */ - && arch_guest != VexArchS390X /* sewardj 2019Dec14: It also causes crashing on MIPS, even for --tool=none. */ && arch_guest != VexArchMIPS64 && arch_guest != VexArchMIPS32) |
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From: Andreas A. <ar...@so...> - 2020-04-08 15:09:42
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=abe7f083fdebb40c6f4a5adbdd2b64f5c329969a commit abe7f083fdebb40c6f4a5adbdd2b64f5c329969a Author: Andreas Arnez <ar...@li...> Date: Thu Mar 19 17:35:55 2020 +0100 Bug 418997 - s390x: Support Iex_ITE for float and vector expressions The s390x backend supports Iex_ITE expressions for integer types I8, I16, I32, and I64 only. But "grail" can now generate such expressions for guarding any kind of Ist_Put statements; see add_guarded_stmt_to_end_of() in "guest_generic_bb_to_IR.c". On s390x this means that F64 and V128 can occur as well, in which case a crash would result. And such crashes are actually seen when running the test suite with "grail" enabled. Extend Iex_ITE support to the floating-point types F32 and F64 and to the vector type V128. Do this by extending S390_INSN_COND_MOVE as needed. Diff: --- NEWS | 1 + VEX/priv/host_s390_defs.c | 24 +++++++++++++++++++++--- VEX/priv/host_s390_isel.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+), 3 deletions(-) diff --git a/NEWS b/NEWS index 4b4dad0086..7c497c15fa 100644 --- a/NEWS +++ b/NEWS @@ -134,6 +134,7 @@ n-i-bz Add support for the Linux io_uring system calls n-i-bz sys_statx: don't complain if both |filename| and |buf| are NULL. n-i-bz Fix non-glibc build of test suite with s390x_features 418004 Grail code additions break ppc64. +418997 s390x: Support Iex_ITE for float and vector types Release 3.15.0 (12 April 2019) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index b61cd41a50..308b6ff409 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -6465,7 +6465,7 @@ s390_insn_cond_move(UChar size, s390_cc_t cond, HReg dst, s390_opnd_RMI src) insn->variant.cond_move.src = src; insn->variant.cond_move.dst = dst; - vassert(size == 1 || size == 2 || size == 4 || size == 8); + vassert(size == 1 || size == 2 || size == 4 || size == 8 || size == 16); return insn; } @@ -10189,7 +10189,7 @@ s390_insn_cond_move_emit(UChar *buf, const s390_insn *insn) p = buf; - if (s390_host_has_lsc) { + if (s390_host_has_lsc && hregClass(dst) == HRcInt64) { /* LOCx is not the preferred way to implement an unconditional load. */ if (cond == S390_CC_ALWAYS) goto use_branch_insn; @@ -10257,14 +10257,32 @@ use_branch_insn: switch (src.tag) { case S390_OPND_REG: - p = s390_emit_LGR(p, hregNumber(dst), hregNumber(src.variant.reg)); + switch (hregClass(dst)) { + case HRcInt64: + p = s390_emit_LGR(p, hregNumber(dst), hregNumber(src.variant.reg)); + break; + case HRcFlt64: + p = s390_emit_LDR(p, hregNumber(dst), hregNumber(src.variant.reg)); + break; + case HRcVec128: + p = s390_emit_VLR(p, hregNumber(dst), hregNumber(src.variant.reg)); + break; + default: + goto fail; + } break; case S390_OPND_AMODE: + if (hregClass(dst) != HRcInt64) + goto fail; + p = s390_emit_load_mem(p, insn->size, hregNumber(dst), src.variant.am); break; case S390_OPND_IMMEDIATE: { + if (hregClass(dst) != HRcInt64) + goto fail; + ULong value = src.variant.imm; UInt r = hregNumber(dst); diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index b374024c8c..e96c7209f1 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -2770,6 +2770,25 @@ s390_isel_float_expr_wrk(ISelEnv *env, IRExpr *expr) return dst; } + /* --------- MULTIPLEX --------- */ + case Iex_ITE: { + IRExpr *cond_expr = expr->Iex.ITE.cond; + HReg dst, r0, r1; + + vassert(typeOfIRExpr(env->type_env, cond_expr) == Ity_I1); + + dst = newVRegF(env); + r0 = s390_isel_float_expr(env, expr->Iex.ITE.iffalse); + r1 = s390_isel_float_expr(env, expr->Iex.ITE.iftrue); + size = sizeofIRType(typeOfIRExpr(env->type_env, expr->Iex.ITE.iftrue)); + + s390_cc_t cc = s390_isel_cc(env, cond_expr); + + addInstr(env, s390_insn_move(size, dst, r0)); + addInstr(env, s390_insn_cond_move(size, cc, dst, s390_opnd_reg(r1))); + return dst; + } + default: goto irreducible; } @@ -4694,6 +4713,25 @@ s390_isel_vec_expr_wrk(ISelEnv *env, IRExpr *expr) } } + /* --------- MULTIPLEX --------- */ + case Iex_ITE: { + IRExpr *cond_expr = expr->Iex.ITE.cond; + HReg dst, r0, r1; + + vassert(typeOfIRExpr(env->type_env, cond_expr) == Ity_I1); + + dst = newVRegV(env); + r0 = s390_isel_vec_expr(env, expr->Iex.ITE.iffalse); + r1 = s390_isel_vec_expr(env, expr->Iex.ITE.iftrue); + size = sizeofIRType(typeOfIRExpr(env->type_env, expr->Iex.ITE.iftrue)); + + s390_cc_t cc = s390_isel_cc(env, cond_expr); + + addInstr(env, s390_insn_move(size, dst, r0)); + addInstr(env, s390_insn_cond_move(size, cc, dst, s390_opnd_reg(r1))); + return dst; + } + default: goto irreducible; } |