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From: Andreas A. <ar...@so...> - 2019-06-12 18:24:26
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=91d53d11671a07269846b189fcb2c5f2194d1da4 commit 91d53d11671a07269846b189fcb2c5f2194d1da4 Author: Ilya Leoshkevich <ii...@li...> Date: Thu May 16 12:34:38 2019 +0200 Bug 404406 - s390x: test z14 miscellaneous instructions Reuse the existing infrastructure for add, sub and mul. Add cc checks to all mul tests. Write a new test for bic. Signed-off-by: Ilya Leoshkevich <ii...@li...> Diff: --- .gitignore | 4 + none/tests/s390x/Makefile.am | 2 +- none/tests/s390x/add-z14.c | 13 + none/tests/s390x/add-z14.stderr.exp | 2 + none/tests/s390x/add-z14.stdout.exp | 154 ++ none/tests/s390x/add-z14.vgtest | 2 + none/tests/s390x/add.c | 39 +- none/tests/s390x/add.h | 23 +- none/tests/s390x/bic.c | 78 + none/tests/s390x/bic.stderr.exp | 2 + none/tests/s390x/bic.stdout.exp | 48 + none/tests/s390x/bic.vgtest | 2 + none/tests/s390x/mul-z14.c | 25 + none/tests/s390x/mul-z14.stderr.exp | 2 + none/tests/s390x/mul-z14.stdout.exp | 1078 +++++++++ none/tests/s390x/mul-z14.vgtest | 2 + none/tests/s390x/mul.c | 33 +- none/tests/s390x/mul.h | 209 +- none/tests/s390x/mul.stdout.exp | 4488 +++++++++++++++++------------------ none/tests/s390x/mul_GE.stdout.exp | 968 ++++---- none/tests/s390x/sub-z14.c | 13 + none/tests/s390x/sub-z14.stderr.exp | 2 + none/tests/s390x/sub-z14.stdout.exp | 154 ++ none/tests/s390x/sub-z14.vgtest | 2 + none/tests/s390x/sub.c | 37 +- none/tests/s390x/sub.h | 28 +- tests/s390x_features.c | 2 + 27 files changed, 4569 insertions(+), 2843 deletions(-) diff --git a/.gitignore b/.gitignore index c5d1bcc..640b8c6 100644 --- a/.gitignore +++ b/.gitignore @@ -1778,11 +1778,13 @@ /none/tests/s390x/*.stdout.diff* /none/tests/s390x/*.stdout.out /none/tests/s390x/add +/none/tests/s390x/add-z14 /none/tests/s390x/add_EI /none/tests/s390x/add_GE /none/tests/s390x/allexec /none/tests/s390x/and /none/tests/s390x/and_EI +/none/tests/s390x/bic /none/tests/s390x/clc /none/tests/s390x/clcle /none/tests/s390x/cvb @@ -1799,12 +1801,14 @@ /none/tests/s390x/Makefile /none/tests/s390x/Makefile.in /none/tests/s390x/mul +/none/tests/s390x/mul-z14 /none/tests/s390x/mul_GE /none/tests/s390x/mvst /none/tests/s390x/or /none/tests/s390x/or_EI /none/tests/s390x/srst /none/tests/s390x/sub +/none/tests/s390x/sub-z14 /none/tests/s390x/sub_EI /none/tests/s390x/tcxb /none/tests/s390x/xc diff --git a/none/tests/s390x/Makefile.am b/none/tests/s390x/Makefile.am index 097c85a..a5fbffd 100644 --- a/none/tests/s390x/Makefile.am +++ b/none/tests/s390x/Makefile.am @@ -19,7 +19,7 @@ INSN_TESTS = clc clcle cvb cvd icm lpr tcxb lam_stam xc mvst add sub mul \ spechelper-ltr spechelper-or \ spechelper-icm-1 spechelper-icm-2 spechelper-tmll \ spechelper-tm laa vector lsc2 ppno vector_string vector_integer \ - vector_float + vector_float add-z14 sub-z14 mul-z14 bic if BUILD_DFP_TESTS INSN_TESTS += dfp-1 dfp-2 dfp-3 dfp-4 dfptest dfpext dfpconv srnmt pfpo diff --git a/none/tests/s390x/add-z14.c b/none/tests/s390x/add-z14.c new file mode 100644 index 0000000..0f43398 --- /dev/null +++ b/none/tests/s390x/add-z14.c @@ -0,0 +1,13 @@ +#include "add.h" + +#define agh(x, y) ".insn rxy,0xe30000000038, " x ", " y "\n" + +static void do_regmem_insns(unsigned long m2) +{ + memsweep(agh, m2, 0); +} + +int main() +{ + for_each_m2(do_regmem_insns); +} diff --git a/none/tests/s390x/add-z14.stderr.exp b/none/tests/s390x/add-z14.stderr.exp new file mode 100644 index 0000000..139597f --- /dev/null +++ b/none/tests/s390x/add-z14.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/s390x/add-z14.stdout.exp b/none/tests/s390x/add-z14.stdout.exp new file mode 100644 index 0000000..d1b2c26 --- /dev/null +++ b/none/tests/s390x/add-z14.stdout.exp @@ -0,0 +1,154 @@ +agh 0 + 0000000000000000 + 0000000000000000 = 0000000000000000 (cc=0) +agh 0 + 0000000000000001 + 0000000000000000 = 0000000000000001 (cc=2) +agh 0 + 000000000000FFFF + 0000000000000000 = 000000000000FFFF (cc=2) +agh 0 + 0000000000007FFF + 0000000000000000 = 0000000000007FFF (cc=2) +agh 0 + 0000000000008000 + 0000000000000000 = 0000000000008000 (cc=2) +agh 0 + 00000000FFFFFFFF + 0000000000000000 = 00000000FFFFFFFF (cc=2) +agh 0 + 0000000080000000 + 0000000000000000 = 0000000080000000 (cc=2) +agh 0 + 000000007FFFFFFF + 0000000000000000 = 000000007FFFFFFF (cc=2) +agh 0 + FFFFFFFFFFFFFFFF + 0000000000000000 = FFFFFFFFFFFFFFFF (cc=1) +agh 0 + 8000000000000000 + 0000000000000000 = 8000000000000000 (cc=1) +agh 0 + 7FFFFFFFFFFFFFFF + 0000000000000000 = 7FFFFFFFFFFFFFFF (cc=2) +agh 0 + 0000000000000000 + 7FFFFFFFFFFFFFFF = 0000000000007FFF (cc=2) +agh 0 + 0000000000000001 + 7FFFFFFFFFFFFFFF = 0000000000008000 (cc=2) +agh 0 + 000000000000FFFF + 7FFFFFFFFFFFFFFF = 0000000000017FFE (cc=2) +agh 0 + 0000000000007FFF + 7FFFFFFFFFFFFFFF = 000000000000FFFE (cc=2) +agh 0 + 0000000000008000 + 7FFFFFFFFFFFFFFF = 000000000000FFFF (cc=2) +agh 0 + 00000000FFFFFFFF + 7FFFFFFFFFFFFFFF = 0000000100007FFE (cc=2) +agh 0 + 0000000080000000 + 7FFFFFFFFFFFFFFF = 0000000080007FFF (cc=2) +agh 0 + 000000007FFFFFFF + 7FFFFFFFFFFFFFFF = 0000000080007FFE (cc=2) +agh 0 + FFFFFFFFFFFFFFFF + 7FFFFFFFFFFFFFFF = 0000000000007FFE (cc=2) +agh 0 + 8000000000000000 + 7FFFFFFFFFFFFFFF = 8000000000007FFF (cc=1) +agh 0 + 7FFFFFFFFFFFFFFF + 7FFFFFFFFFFFFFFF = 8000000000007FFE (cc=3) +agh 0 + 0000000000000000 + 8000000000000000 = FFFFFFFFFFFF8000 (cc=1) +agh 0 + 0000000000000001 + 8000000000000000 = FFFFFFFFFFFF8001 (cc=1) +agh 0 + 000000000000FFFF + 8000000000000000 = 0000000000007FFF (cc=2) +agh 0 + 0000000000007FFF + 8000000000000000 = FFFFFFFFFFFFFFFF (cc=1) +agh 0 + 0000000000008000 + 8000000000000000 = 0000000000000000 (cc=0) +agh 0 + 00000000FFFFFFFF + 8000000000000000 = 00000000FFFF7FFF (cc=2) +agh 0 + 0000000080000000 + 8000000000000000 = 000000007FFF8000 (cc=2) +agh 0 + 000000007FFFFFFF + 8000000000000000 = 000000007FFF7FFF (cc=2) +agh 0 + FFFFFFFFFFFFFFFF + 8000000000000000 = FFFFFFFFFFFF7FFF (cc=1) +agh 0 + 8000000000000000 + 8000000000000000 = 7FFFFFFFFFFF8000 (cc=3) +agh 0 + 7FFFFFFFFFFFFFFF + 8000000000000000 = 7FFFFFFFFFFF7FFF (cc=2) +agh 0 + 0000000000000000 + FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFF (cc=1) +agh 0 + 0000000000000001 + FFFFFFFFFFFFFFFF = 0000000000000000 (cc=0) +agh 0 + 000000000000FFFF + FFFFFFFFFFFFFFFF = 000000000000FFFE (cc=2) +agh 0 + 0000000000007FFF + FFFFFFFFFFFFFFFF = 0000000000007FFE (cc=2) +agh 0 + 0000000000008000 + FFFFFFFFFFFFFFFF = 0000000000007FFF (cc=2) +agh 0 + 00000000FFFFFFFF + FFFFFFFFFFFFFFFF = 00000000FFFFFFFE (cc=2) +agh 0 + 0000000080000000 + FFFFFFFFFFFFFFFF = 000000007FFFFFFF (cc=2) +agh 0 + 000000007FFFFFFF + FFFFFFFFFFFFFFFF = 000000007FFFFFFE (cc=2) +agh 0 + FFFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFE (cc=1) +agh 0 + 8000000000000000 + FFFFFFFFFFFFFFFF = 7FFFFFFFFFFFFFFF (cc=3) +agh 0 + 7FFFFFFFFFFFFFFF + FFFFFFFFFFFFFFFF = 7FFFFFFFFFFFFFFE (cc=2) +agh 0 + 0000000000000000 + 7FFFFFFF00000000 = 0000000000007FFF (cc=2) +agh 0 + 0000000000000001 + 7FFFFFFF00000000 = 0000000000008000 (cc=2) +agh 0 + 000000000000FFFF + 7FFFFFFF00000000 = 0000000000017FFE (cc=2) +agh 0 + 0000000000007FFF + 7FFFFFFF00000000 = 000000000000FFFE (cc=2) +agh 0 + 0000000000008000 + 7FFFFFFF00000000 = 000000000000FFFF (cc=2) +agh 0 + 00000000FFFFFFFF + 7FFFFFFF00000000 = 0000000100007FFE (cc=2) +agh 0 + 0000000080000000 + 7FFFFFFF00000000 = 0000000080007FFF (cc=2) +agh 0 + 000000007FFFFFFF + 7FFFFFFF00000000 = 0000000080007FFE (cc=2) +agh 0 + FFFFFFFFFFFFFFFF + 7FFFFFFF00000000 = 0000000000007FFE (cc=2) +agh 0 + 8000000000000000 + 7FFFFFFF00000000 = 8000000000007FFF (cc=1) +agh 0 + 7FFFFFFFFFFFFFFF + 7FFFFFFF00000000 = 8000000000007FFE (cc=3) +agh 0 + 0000000000000000 + 8000000000000000 = FFFFFFFFFFFF8000 (cc=1) +agh 0 + 0000000000000001 + 8000000000000000 = FFFFFFFFFFFF8001 (cc=1) +agh 0 + 000000000000FFFF + 8000000000000000 = 0000000000007FFF (cc=2) +agh 0 + 0000000000007FFF + 8000000000000000 = FFFFFFFFFFFFFFFF (cc=1) +agh 0 + 0000000000008000 + 8000000000000000 = 0000000000000000 (cc=0) +agh 0 + 00000000FFFFFFFF + 8000000000000000 = 00000000FFFF7FFF (cc=2) +agh 0 + 0000000080000000 + 8000000000000000 = 000000007FFF8000 (cc=2) +agh 0 + 000000007FFFFFFF + 8000000000000000 = 000000007FFF7FFF (cc=2) +agh 0 + FFFFFFFFFFFFFFFF + 8000000000000000 = FFFFFFFFFFFF7FFF (cc=1) +agh 0 + 8000000000000000 + 8000000000000000 = 7FFFFFFFFFFF8000 (cc=3) +agh 0 + 7FFFFFFFFFFFFFFF + 8000000000000000 = 7FFFFFFFFFFF7FFF (cc=2) +agh 0 + 0000000000000000 + FFFFFFFF00000000 = FFFFFFFFFFFFFFFF (cc=1) +agh 0 + 0000000000000001 + FFFFFFFF00000000 = 0000000000000000 (cc=0) +agh 0 + 000000000000FFFF + FFFFFFFF00000000 = 000000000000FFFE (cc=2) +agh 0 + 0000000000007FFF + FFFFFFFF00000000 = 0000000000007FFE (cc=2) +agh 0 + 0000000000008000 + FFFFFFFF00000000 = 0000000000007FFF (cc=2) +agh 0 + 00000000FFFFFFFF + FFFFFFFF00000000 = 00000000FFFFFFFE (cc=2) +agh 0 + 0000000080000000 + FFFFFFFF00000000 = 000000007FFFFFFF (cc=2) +agh 0 + 000000007FFFFFFF + FFFFFFFF00000000 = 000000007FFFFFFE (cc=2) +agh 0 + FFFFFFFFFFFFFFFF + FFFFFFFF00000000 = FFFFFFFFFFFFFFFE (cc=1) +agh 0 + 8000000000000000 + FFFFFFFF00000000 = 7FFFFFFFFFFFFFFF (cc=3) +agh 0 + 7FFFFFFFFFFFFFFF + FFFFFFFF00000000 = 7FFFFFFFFFFFFFFE (cc=2) +agh 0 + 0000000000000000 + 000000007FFFFFFF = 0000000000000000 (cc=0) +agh 0 + 0000000000000001 + 000000007FFFFFFF = 0000000000000001 (cc=2) +agh 0 + 000000000000FFFF + 000000007FFFFFFF = 000000000000FFFF (cc=2) +agh 0 + 0000000000007FFF + 000000007FFFFFFF = 0000000000007FFF (cc=2) +agh 0 + 0000000000008000 + 000000007FFFFFFF = 0000000000008000 (cc=2) +agh 0 + 00000000FFFFFFFF + 000000007FFFFFFF = 00000000FFFFFFFF (cc=2) +agh 0 + 0000000080000000 + 000000007FFFFFFF = 0000000080000000 (cc=2) +agh 0 + 000000007FFFFFFF + 000000007FFFFFFF = 000000007FFFFFFF (cc=2) +agh 0 + FFFFFFFFFFFFFFFF + 000000007FFFFFFF = FFFFFFFFFFFFFFFF (cc=1) +agh 0 + 8000000000000000 + 000000007FFFFFFF = 8000000000000000 (cc=1) +agh 0 + 7FFFFFFFFFFFFFFF + 000000007FFFFFFF = 7FFFFFFFFFFFFFFF (cc=2) +agh 0 + 0000000000000000 + 0000000080000000 = 0000000000000000 (cc=0) +agh 0 + 0000000000000001 + 0000000080000000 = 0000000000000001 (cc=2) +agh 0 + 000000000000FFFF + 0000000080000000 = 000000000000FFFF (cc=2) +agh 0 + 0000000000007FFF + 0000000080000000 = 0000000000007FFF (cc=2) +agh 0 + 0000000000008000 + 0000000080000000 = 0000000000008000 (cc=2) +agh 0 + 00000000FFFFFFFF + 0000000080000000 = 00000000FFFFFFFF (cc=2) +agh 0 + 0000000080000000 + 0000000080000000 = 0000000080000000 (cc=2) +agh 0 + 000000007FFFFFFF + 0000000080000000 = 000000007FFFFFFF (cc=2) +agh 0 + FFFFFFFFFFFFFFFF + 0000000080000000 = FFFFFFFFFFFFFFFF (cc=1) +agh 0 + 8000000000000000 + 0000000080000000 = 8000000000000000 (cc=1) +agh 0 + 7FFFFFFFFFFFFFFF + 0000000080000000 = 7FFFFFFFFFFFFFFF (cc=2) +agh 0 + 0000000000000000 + 00000000FFFFFFFF = 0000000000000000 (cc=0) +agh 0 + 0000000000000001 + 00000000FFFFFFFF = 0000000000000001 (cc=2) +agh 0 + 000000000000FFFF + 00000000FFFFFFFF = 000000000000FFFF (cc=2) +agh 0 + 0000000000007FFF + 00000000FFFFFFFF = 0000000000007FFF (cc=2) +agh 0 + 0000000000008000 + 00000000FFFFFFFF = 0000000000008000 (cc=2) +agh 0 + 00000000FFFFFFFF + 00000000FFFFFFFF = 00000000FFFFFFFF (cc=2) +agh 0 + 0000000080000000 + 00000000FFFFFFFF = 0000000080000000 (cc=2) +agh 0 + 000000007FFFFFFF + 00000000FFFFFFFF = 000000007FFFFFFF (cc=2) +agh 0 + FFFFFFFFFFFFFFFF + 00000000FFFFFFFF = FFFFFFFFFFFFFFFF (cc=1) +agh 0 + 8000000000000000 + 00000000FFFFFFFF = 8000000000000000 (cc=1) +agh 0 + 7FFFFFFFFFFFFFFF + 00000000FFFFFFFF = 7FFFFFFFFFFFFFFF (cc=2) +agh 0 + 0000000000000000 + 000000000000FFFF = 0000000000000000 (cc=0) +agh 0 + 0000000000000001 + 000000000000FFFF = 0000000000000001 (cc=2) +agh 0 + 000000000000FFFF + 000000000000FFFF = 000000000000FFFF (cc=2) +agh 0 + 0000000000007FFF + 000000000000FFFF = 0000000000007FFF (cc=2) +agh 0 + 0000000000008000 + 000000000000FFFF = 0000000000008000 (cc=2) +agh 0 + 00000000FFFFFFFF + 000000000000FFFF = 00000000FFFFFFFF (cc=2) +agh 0 + 0000000080000000 + 000000000000FFFF = 0000000080000000 (cc=2) +agh 0 + 000000007FFFFFFF + 000000000000FFFF = 000000007FFFFFFF (cc=2) +agh 0 + FFFFFFFFFFFFFFFF + 000000000000FFFF = FFFFFFFFFFFFFFFF (cc=1) +agh 0 + 8000000000000000 + 000000000000FFFF = 8000000000000000 (cc=1) +agh 0 + 7FFFFFFFFFFFFFFF + 000000000000FFFF = 7FFFFFFFFFFFFFFF (cc=2) +agh 0 + 0000000000000000 + 0000000000007FFF = 0000000000000000 (cc=0) +agh 0 + 0000000000000001 + 0000000000007FFF = 0000000000000001 (cc=2) +agh 0 + 000000000000FFFF + 0000000000007FFF = 000000000000FFFF (cc=2) +agh 0 + 0000000000007FFF + 0000000000007FFF = 0000000000007FFF (cc=2) +agh 0 + 0000000000008000 + 0000000000007FFF = 0000000000008000 (cc=2) +agh 0 + 00000000FFFFFFFF + 0000000000007FFF = 00000000FFFFFFFF (cc=2) +agh 0 + 0000000080000000 + 0000000000007FFF = 0000000080000000 (cc=2) +agh 0 + 000000007FFFFFFF + 0000000000007FFF = 000000007FFFFFFF (cc=2) +agh 0 + FFFFFFFFFFFFFFFF + 0000000000007FFF = FFFFFFFFFFFFFFFF (cc=1) +agh 0 + 8000000000000000 + 0000000000007FFF = 8000000000000000 (cc=1) +agh 0 + 7FFFFFFFFFFFFFFF + 0000000000007FFF = 7FFFFFFFFFFFFFFF (cc=2) +agh 0 + 0000000000000000 + 0000000000008000 = 0000000000000000 (cc=0) +agh 0 + 0000000000000001 + 0000000000008000 = 0000000000000001 (cc=2) +agh 0 + 000000000000FFFF + 0000000000008000 = 000000000000FFFF (cc=2) +agh 0 + 0000000000007FFF + 0000000000008000 = 0000000000007FFF (cc=2) +agh 0 + 0000000000008000 + 0000000000008000 = 0000000000008000 (cc=2) +agh 0 + 00000000FFFFFFFF + 0000000000008000 = 00000000FFFFFFFF (cc=2) +agh 0 + 0000000080000000 + 0000000000008000 = 0000000080000000 (cc=2) +agh 0 + 000000007FFFFFFF + 0000000000008000 = 000000007FFFFFFF (cc=2) +agh 0 + FFFFFFFFFFFFFFFF + 0000000000008000 = FFFFFFFFFFFFFFFF (cc=1) +agh 0 + 8000000000000000 + 0000000000008000 = 8000000000000000 (cc=1) +agh 0 + 7FFFFFFFFFFFFFFF + 0000000000008000 = 7FFFFFFFFFFFFFFF (cc=2) +agh 0 + 0000000000000000 + 000000000000FFFF = 0000000000000000 (cc=0) +agh 0 + 0000000000000001 + 000000000000FFFF = 0000000000000001 (cc=2) +agh 0 + 000000000000FFFF + 000000000000FFFF = 000000000000FFFF (cc=2) +agh 0 + 0000000000007FFF + 000000000000FFFF = 0000000000007FFF (cc=2) +agh 0 + 0000000000008000 + 000000000000FFFF = 0000000000008000 (cc=2) +agh 0 + 00000000FFFFFFFF + 000000000000FFFF = 00000000FFFFFFFF (cc=2) +agh 0 + 0000000080000000 + 000000000000FFFF = 0000000080000000 (cc=2) +agh 0 + 000000007FFFFFFF + 000000000000FFFF = 000000007FFFFFFF (cc=2) +agh 0 + FFFFFFFFFFFFFFFF + 000000000000FFFF = FFFFFFFFFFFFFFFF (cc=1) +agh 0 + 8000000000000000 + 000000000000FFFF = 8000000000000000 (cc=1) +agh 0 + 7FFFFFFFFFFFFFFF + 000000000000FFFF = 7FFFFFFFFFFFFFFF (cc=2) diff --git a/none/tests/s390x/add-z14.vgtest b/none/tests/s390x/add-z14.vgtest new file mode 100644 index 0000000..531b58f --- /dev/null +++ b/none/tests/s390x/add-z14.vgtest @@ -0,0 +1,2 @@ +prog: add-z14 +prereq: ../../../tests/s390x_features s390x-mi2 diff --git a/none/tests/s390x/add.c b/none/tests/s390x/add.c index 0041ed2..4f2f9be 100644 --- a/none/tests/s390x/add.c +++ b/none/tests/s390x/add.c @@ -1,7 +1,9 @@ -#include <stdio.h> #include "add.h" #include "opcodes.h" +#define ahi(x, y) "ahi " x ", " y "\n" +#define aghi(x, y) "aghi " x ", " y "\n" + static void do_imm_insns(void) { immsweep(ahi, 0, 0); @@ -14,6 +16,24 @@ static void do_imm_insns(void) immsweep(aghi, 32767, 0); } +#define a(x, y) "a " x ", " y "\n" +#define ah(x, y) "ah " x ", " y "\n" +#define ag(x, y) "ag " x ", " y "\n" +#define agf(x, y) "agf " x ", " y "\n" +#define al(x, y) "al " x ", " y "\n" +#define alg(x, y) "alg " x ", " y "\n" +#define agf(x, y) "agf " x ", " y "\n" +#define algf(x, y) "algf " x ", " y "\n" +#define ar(x, y) "ar " x ", " y "\n" +#define agr(x, y) "agr " x ", " y "\n" +#define agfr(x, y) "agfr " x ", " y "\n" +#define alr(x, y) "alr " x ", " y "\n" +#define algr(x, y) "algr " x ", " y "\n" +#define algfr(x, y) "algfr " x ", " y "\n" +#define alc(x, y) "alc " x ", " y "\n" +#define alcg(x, y) "alcg " x ", " y "\n" +#define alcr(x, y) "alcr " x ", " y "\n" +#define alcgr(x, y) "alcgr " x ", " y "\n" static void do_regmem_insns(unsigned long s2) { @@ -46,22 +66,7 @@ static void do_regmem_insns(unsigned long s2) int main() { - do_regmem_insns(0x0ul); - do_regmem_insns(0x7ffffffffffffffful); - do_regmem_insns(0x8000000000000000ul); - do_regmem_insns(0xfffffffffffffffful); - do_regmem_insns(0x7fffffff00000000ul); - do_regmem_insns(0x8000000000000000ul); - do_regmem_insns(0xffffffff00000000ul); - do_regmem_insns(0x000000007ffffffful); - do_regmem_insns(0x0000000080000000ul); - do_regmem_insns(0x00000000fffffffful); - do_regmem_insns(0x000000000000fffful); - do_regmem_insns(0x0000000000007ffful); - do_regmem_insns(0x0000000000008000ul); - do_regmem_insns(0x000000000000fffful); + for_each_m2(do_regmem_insns); do_imm_insns(); - - return 0; } diff --git a/none/tests/s390x/add.h b/none/tests/s390x/add.h index 5311161..a5051cf 100644 --- a/none/tests/s390x/add.h +++ b/none/tests/s390x/add.h @@ -9,7 +9,7 @@ volatile long v; int cc; \ asm volatile( "lghi 0," #CARRY "\n" \ "aghi 0, 0\n" \ - #insn " %0, %3\n" \ + insn("%0", "%3") \ "ipm %1\n" \ "srl %1,28\n" \ : "+d" (tmp), "=d" (cc) \ @@ -24,7 +24,7 @@ volatile long v; int cc; \ asm volatile( "lghi 0," #CARRY "\n" \ "aghi 0, 0\n" \ - #insn " %0, %3\n" \ + insn("%0", "%3") \ "ipm %1\n" \ "srl %1,28\n" \ : "+d" (tmp), "=d" (cc) \ @@ -39,7 +39,7 @@ volatile long v; int cc; \ asm volatile( "lghi 0," #CARRY "\n" \ "aghi 0, 0\n" \ - #insn " %0," #s2 "\n" \ + insn("%0", #s2) \ "ipm %1\n" \ "srl %1,28\n" \ : "+d" (tmp), "=d" (cc) \ @@ -204,3 +204,20 @@ volatile long v; ADD_REG_XIMM(i, 0x7ffffffffffffffful, us2, s2, carryset); \ }) +#define for_each_m2(f) \ +({ \ + f(0x0ul); \ + f(0x7ffffffffffffffful); \ + f(0x8000000000000000ul); \ + f(0xfffffffffffffffful); \ + f(0x7fffffff00000000ul); \ + f(0x8000000000000000ul); \ + f(0xffffffff00000000ul); \ + f(0x000000007ffffffful); \ + f(0x0000000080000000ul); \ + f(0x00000000fffffffful); \ + f(0x000000000000fffful); \ + f(0x0000000000007ffful); \ + f(0x0000000000008000ul); \ + f(0x000000000000fffful); \ +}) diff --git a/none/tests/s390x/bic.c b/none/tests/s390x/bic.c new file mode 100644 index 0000000..a8d28d9 --- /dev/null +++ b/none/tests/s390x/bic.c @@ -0,0 +1,78 @@ +#include <stdio.h> + +#define HEAD "agfi %[i], -8\n" \ + "jl 1f\n" \ + "larl %[table], 6f\n" \ + "sllg %[i], %[i], 3(0)\n" \ + "clgfi %[i], 4*8\n" + +#define TAIL "0: lghi %[i], 200\n" \ + "j 7f\n" \ + "1: lghi %[i], 100\n" \ + "j 7f\n" \ + "2: lghi %[i], 111\n" \ + "j 7f\n" \ + "3: lghi %[i], 122\n" \ + "j 7f\n" \ + "4: lghi %[i], 133\n" \ + "j 7f\n" \ + "5: lghi %[i], 144\n" \ + "j 7f\n" \ + "6:\n" \ + ".quad 2b\n" \ + ".quad 3b\n" \ + ".quad 4b\n" \ + ".quad 5b\n" \ + ".quad 5b\n" \ + "7:\n" + +static int bic0(int i) +{ + void *table; + asm volatile(HEAD + "brcl 10, 0f\n" + ".insn rxy, 0xe30000000047, 0, 8(%[i],%[table])\n" + "lg %[table],0(%[i],%[table])\n" + "br %[table]\n" + TAIL + : [i] "+d" (i) + , [table] "=d" (table) + :: "cc"); + return i; +} + +static int bic4(int i) +{ + void *table; + asm volatile(HEAD + ".insn rxy, 0xe30000000047, 4, 0(%[i],%[table])\n" + TAIL + : [i] "+d" (i) + , [table] "=d" (table) + :: "cc"); + return i; +} + +static int bic15(int i) +{ + void *table; + asm volatile(HEAD + "brcl 10, 0f\n" + ".insn rxy, 0xe30000000047, 15, 0(%[i],%[table])\n" + TAIL + : [i] "+d" (i) + , [table] "=d" (table) + :: "cc"); + return i; +} + +int main() +{ + int i; + + for (i = 0; i < 16; i++) { + printf("bic0: %d -> %d\n", i, bic0(i)); + printf("bic4: %d -> %d\n", i, bic4(i)); + printf("bic15: %d -> %d\n", i, bic15(i)); + } +} diff --git a/none/tests/s390x/bic.stderr.exp b/none/tests/s390x/bic.stderr.exp new file mode 100644 index 0000000..139597f --- /dev/null +++ b/none/tests/s390x/bic.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/s390x/bic.stdout.exp b/none/tests/s390x/bic.stdout.exp new file mode 100644 index 0000000..64dcac4 --- /dev/null +++ b/none/tests/s390x/bic.stdout.exp @@ -0,0 +1,48 @@ +bic0: 0 -> 100 +bic4: 0 -> 100 +bic15: 0 -> 100 +bic0: 1 -> 100 +bic4: 1 -> 100 +bic15: 1 -> 100 +bic0: 2 -> 100 +bic4: 2 -> 100 +bic15: 2 -> 100 +bic0: 3 -> 100 +bic4: 3 -> 100 +bic15: 3 -> 100 +bic0: 4 -> 100 +bic4: 4 -> 100 +bic15: 4 -> 100 +bic0: 5 -> 100 +bic4: 5 -> 100 +bic15: 5 -> 100 +bic0: 6 -> 100 +bic4: 6 -> 100 +bic15: 6 -> 100 +bic0: 7 -> 100 +bic4: 7 -> 100 +bic15: 7 -> 100 +bic0: 8 -> 111 +bic4: 8 -> 111 +bic15: 8 -> 111 +bic0: 9 -> 122 +bic4: 9 -> 122 +bic15: 9 -> 122 +bic0: 10 -> 133 +bic4: 10 -> 133 +bic15: 10 -> 133 +bic0: 11 -> 144 +bic4: 11 -> 144 +bic15: 11 -> 144 +bic0: 12 -> 200 +bic4: 12 -> 200 +bic15: 12 -> 200 +bic0: 13 -> 200 +bic4: 13 -> 200 +bic15: 13 -> 200 +bic0: 14 -> 200 +bic4: 14 -> 200 +bic15: 14 -> 200 +bic0: 15 -> 200 +bic4: 15 -> 200 +bic15: 15 -> 200 diff --git a/none/tests/s390x/bic.vgtest b/none/tests/s390x/bic.vgtest new file mode 100644 index 0000000..dfb8c23 --- /dev/null +++ b/none/tests/s390x/bic.vgtest @@ -0,0 +1,2 @@ +prog: bic +prereq: ../../../tests/s390x_features s390x-mi2 diff --git a/none/tests/s390x/mul-z14.c b/none/tests/s390x/mul-z14.c new file mode 100644 index 0000000..1a28af8 --- /dev/null +++ b/none/tests/s390x/mul-z14.c @@ -0,0 +1,25 @@ +#include "mul.h" + +#define mg(x, y) ".insn rxy,0xe30000000084, " x ", " y "\n" +#define mgh(x, y) ".insn rxy,0xe3000000003c, " x ", " y "\n" +#define mgrk(x, y, z) ".insn rrf,0xb9ec0000, " x ", " y ", " z ", 0\n" +#define msc(x, y) ".insn rxy,0xe30000000053, " x ", " y "\n" +#define msrkc(x, y, z) ".insn rrf,0xb9fd0000, " x ", " y ", " z ", 0\n" +#define msgc(x, y) ".insn rxy,0xe30000000083, " x ", " y "\n" +#define msgrkc(x, y, z) ".insn rrf,0xb9ed0000, " x ", " y ", " z ", 0\n" + +static void do_regmem_insns(unsigned long m2) +{ + memsweep(mg, m2); + memsweep(mgh, m2); + regregsweep(mgrk, m2); + memsweep(msc, m2); + regregsweep(msrkc, m2); + memsweep(msgc, m2); + regregsweep(msgrkc, m2); +} + +int main() +{ + for_each_m2(do_regmem_insns); +} diff --git a/none/tests/s390x/mul-z14.stderr.exp b/none/tests/s390x/mul-z14.stderr.exp new file mode 100644 index 0000000..139597f --- /dev/null +++ b/none/tests/s390x/mul-z14.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/s390x/mul-z14.stdout.exp b/none/tests/s390x/mul-z14.stdout.exp new file mode 100644 index 0000000..da22b57 --- /dev/null +++ b/none/tests/s390x/mul-z14.stdout.exp @@ -0,0 +1,1078 @@ +mg 0000000000000000 * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mg 0000000000000001 * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mg 000000000000FFFF * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mg 0000000000007FFF * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mg 0000000000008000 * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mg 00000000FFFFFFFF * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mg 0000000080000000 * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mg 000000007FFFFFFF * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mg FFFFFFFFFFFFFFFF * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mg 8000000000000000 * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mg 7FFFFFFFFFFFFFFF * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mgh 0000000000000000 * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mgh 0000000000000001 * 0000000000000000 = 00000000000000000000000000000001 (cc=0) +mgh 000000000000FFFF * 0000000000000000 = 0000000000000000000000000000FFFF (cc=0) +mgh 0000000000007FFF * 0000000000000000 = 00000000000000000000000000007FFF (cc=0) +mgh 0000000000008000 * 0000000000000000 = 00000000000000000000000000008000 (cc=0) +mgh 00000000FFFFFFFF * 0000000000000000 = 000000000000000000000000FFFFFFFF (cc=0) +mgh 0000000080000000 * 0000000000000000 = 00000000000000000000000080000000 (cc=0) +mgh 000000007FFFFFFF * 0000000000000000 = 0000000000000000000000007FFFFFFF (cc=0) +mgh FFFFFFFFFFFFFFFF * 0000000000000000 = 0000000000000000FFFFFFFFFFFFFFFF (cc=0) +mgh 8000000000000000 * 0000000000000000 = 00000000000000008000000000000000 (cc=0) +mgh 7FFFFFFFFFFFFFFF * 0000000000000000 = 00000000000000007FFFFFFFFFFFFFFF (cc=0) +mgrk 0000000000000000 * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mgrk 0000000000000001 * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mgrk 000000000000FFFF * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mgrk 0000000000007FFF * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mgrk 0000000000008000 * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mgrk 00000000FFFFFFFF * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mgrk 0000000080000000 * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mgrk 000000007FFFFFFF * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mgrk FFFFFFFFFFFFFFFF * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mgrk 8000000000000000 * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +mgrk 7FFFFFFFFFFFFFFF * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +msc 0000000000000000 * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +msc 0000000000000001 * 0000000000000000 = 00000000000000000000000000000001 (cc=0) +msc 000000000000FFFF * 0000000000000000 = 0000000000000000000000000000FFFF (cc=0) +msc 0000000000007FFF * 0000000000000000 = 00000000000000000000000000007FFF (cc=0) +msc 0000000000008000 * 0000000000000000 = 00000000000000000000000000008000 (cc=0) +msc 00000000FFFFFFFF * 0000000000000000 = 000000000000000000000000FFFFFFFF (cc=0) +msc 0000000080000000 * 0000000000000000 = 00000000000000000000000080000000 (cc=0) +msc 000000007FFFFFFF * 0000000000000000 = 0000000000000000000000007FFFFFFF (cc=0) +msc FFFFFFFFFFFFFFFF * 0000000000000000 = FFFFFFFF00000000FFFFFFFFFFFFFFFF (cc=0) +msc 8000000000000000 * 0000000000000000 = 80000000000000008000000000000000 (cc=0) +msc 7FFFFFFFFFFFFFFF * 0000000000000000 = 7FFFFFFF000000007FFFFFFFFFFFFFFF (cc=0) +msrkc 0000000000000000 * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000000000001 * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 000000000000FFFF * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000000007FFF * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000000008000 * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 00000000FFFFFFFF * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000080000000 * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 000000007FFFFFFF * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc FFFFFFFFFFFFFFFF * 0000000000000000 = FFFFFFFF000000000000000000000002 (cc=0) +msrkc 8000000000000000 * 0000000000000000 = 80000000000000000000000000000002 (cc=0) +msrkc 7FFFFFFFFFFFFFFF * 0000000000000000 = 7FFFFFFF000000000000000000000002 (cc=0) +msgc 0000000000000000 * 0000000000000000 = 00000000000000000000000000000000 (cc=0) +msgc 0000000000000001 * 0000000000000000 = 00000000000000000000000000000001 (cc=0) +msgc 000000000000FFFF * 0000000000000000 = 0000000000000000000000000000FFFF (cc=0) +msgc 0000000000007FFF * 0000000000000000 = 00000000000000000000000000007FFF (cc=0) +msgc 0000000000008000 * 0000000000000000 = 00000000000000000000000000008000 (cc=0) +msgc 00000000FFFFFFFF * 0000000000000000 = 000000000000000000000000FFFFFFFF (cc=0) +msgc 0000000080000000 * 0000000000000000 = 00000000000000000000000080000000 (cc=0) +msgc 000000007FFFFFFF * 0000000000000000 = 0000000000000000000000007FFFFFFF (cc=0) +msgc FFFFFFFFFFFFFFFF * 0000000000000000 = 0000000000000000FFFFFFFFFFFFFFFF (cc=0) +msgc 8000000000000000 * 0000000000000000 = 00000000000000008000000000000000 (cc=0) +msgc 7FFFFFFFFFFFFFFF * 0000000000000000 = 00000000000000007FFFFFFFFFFFFFFF (cc=0) +msgrkc 0000000000000000 * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msgrkc 0000000000000001 * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msgrkc 000000000000FFFF * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msgrkc 0000000000007FFF * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msgrkc 0000000000008000 * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msgrkc 00000000FFFFFFFF * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msgrkc 0000000080000000 * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msgrkc 000000007FFFFFFF * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msgrkc FFFFFFFFFFFFFFFF * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msgrkc 8000000000000000 * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +msgrkc 7FFFFFFFFFFFFFFF * 0000000000000000 = 00000000000000000000000000000002 (cc=0) +mg 0000000000000000 * 7FFFFFFFFFFFFFFF = 00000000000000000000000000000000 (cc=0) +mg 0000000000000001 * 7FFFFFFFFFFFFFFF = 00000000000000007FFFFFFFFFFFFFFF (cc=0) +mg 000000000000FFFF * 7FFFFFFFFFFFFFFF = 0000000000007FFF7FFFFFFFFFFF0001 (cc=0) +mg 0000000000007FFF * 7FFFFFFFFFFFFFFF = 0000000000003FFF7FFFFFFFFFFF8001 (cc=0) +mg 0000000000008000 * 7FFFFFFFFFFFFFFF = 0000000000003FFFFFFFFFFFFFFF8000 (cc=0) +mg 00000000FFFFFFFF * 7FFFFFFFFFFFFFFF = 000000007FFFFFFF7FFFFFFF00000001 (cc=0) +mg 0000000080000000 * 7FFFFFFFFFFFFFFF = 000000003FFFFFFFFFFFFFFF80000000 (cc=0) +mg 000000007FFFFFFF * 7FFFFFFFFFFFFFFF = 000000003FFFFFFF7FFFFFFF80000001 (cc=0) +mg FFFFFFFFFFFFFFFF * 7FFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFF8000000000000001 (cc=0) +mg 8000000000000000 * 7FFFFFFFFFFFFFFF = C0000000000000008000000000000000 (cc=0) +mg 7FFFFFFFFFFFFFFF * 7FFFFFFFFFFFFFFF = 3FFFFFFFFFFFFFFF0000000000000001 (cc=0) +mgh 0000000000000000 * 7FFFFFFFFFFFFFFF = 00000000000000000000000000000000 (cc=0) +mgh 0000000000000001 * 7FFFFFFFFFFFFFFF = 0000000000007FFF0000000000000001 (cc=0) +mgh 000000000000FFFF * 7FFFFFFFFFFFFFFF = 000000007FFE8001000000000000FFFF (cc=0) +mgh 0000000000007FFF * 7FFFFFFFFFFFFFFF = 000000003FFF00010000000000007FFF (cc=0) +mgh 0000000000008000 * 7FFFFFFFFFFFFFFF = 000000003FFF80000000000000008000 (cc=0) +mgh 00000000FFFFFFFF * 7FFFFFFFFFFFFFFF = 00007FFEFFFF800100000000FFFFFFFF (cc=0) +mgh 0000000080000000 * 7FFFFFFFFFFFFFFF = 00003FFF800000000000000080000000 (cc=0) +mgh 000000007FFFFFFF * 7FFFFFFFFFFFFFFF = 00003FFF7FFF8001000000007FFFFFFF (cc=0) +mgh FFFFFFFFFFFFFFFF * 7FFFFFFFFFFFFFFF = FFFFFFFFFFFF8001FFFFFFFFFFFFFFFF (cc=0) +mgh 8000000000000000 * 7FFFFFFFFFFFFFFF = 80000000000000008000000000000000 (cc=0) +mgh 7FFFFFFFFFFFFFFF * 7FFFFFFFFFFFFFFF = 7FFFFFFFFFFF80017FFFFFFFFFFFFFFF (cc=0) +mgrk 0000000000000000 * 7FFFFFFFFFFFFFFF = 00000000000000000000000000000000 (cc=0) +mgrk 0000000000000001 * 7FFFFFFFFFFFFFFF = 00000000000000007FFFFFFFFFFFFFFF (cc=0) +mgrk 000000000000FFFF * 7FFFFFFFFFFFFFFF = 0000000000007FFF7FFFFFFFFFFF0001 (cc=0) +mgrk 0000000000007FFF * 7FFFFFFFFFFFFFFF = 0000000000003FFF7FFFFFFFFFFF8001 (cc=0) +mgrk 0000000000008000 * 7FFFFFFFFFFFFFFF = 0000000000003FFFFFFFFFFFFFFF8000 (cc=0) +mgrk 00000000FFFFFFFF * 7FFFFFFFFFFFFFFF = 000000007FFFFFFF7FFFFFFF00000001 (cc=0) +mgrk 0000000080000000 * 7FFFFFFFFFFFFFFF = 000000003FFFFFFFFFFFFFFF80000000 (cc=0) +mgrk 000000007FFFFFFF * 7FFFFFFFFFFFFFFF = 000000003FFFFFFF7FFFFFFF80000001 (cc=0) +mgrk FFFFFFFFFFFFFFFF * 7FFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFF8000000000000001 (cc=0) +mgrk 8000000000000000 * 7FFFFFFFFFFFFFFF = C0000000000000008000000000000000 (cc=0) +mgrk 7FFFFFFFFFFFFFFF * 7FFFFFFFFFFFFFFF = 3FFFFFFFFFFFFFFF0000000000000001 (cc=0) +msc 0000000000000000 * 7FFFFFFFFFFFFFFF = 00000000000000000000000000000000 (cc=0) +msc 0000000000000001 * 7FFFFFFFFFFFFFFF = 000000007FFFFFFF0000000000000001 (cc=2) +msc 000000000000FFFF * 7FFFFFFFFFFFFFFF = 000000007FFF0001000000000000FFFF (cc=3) +msc 0000000000007FFF * 7FFFFFFFFFFFFFFF = 000000007FFF80010000000000007FFF (cc=3) +msc 0000000000008000 * 7FFFFFFFFFFFFFFF = 00000000FFFF80000000000000008000 (cc=3) +msc 00000000FFFFFFFF * 7FFFFFFFFFFFFFFF = 000000008000000100000000FFFFFFFF (cc=1) +msc 0000000080000000 * 7FFFFFFFFFFFFFFF = 00000000800000000000000080000000 (cc=3) +msc 000000007FFFFFFF * 7FFFFFFFFFFFFFFF = 0000000000000001000000007FFFFFFF (cc=3) +msc FFFFFFFFFFFFFFFF * 7FFFFFFFFFFFFFFF = FFFFFFFF80000001FFFFFFFFFFFFFFFF (cc=1) +msc 8000000000000000 * 7FFFFFFFFFFFFFFF = 80000000000000008000000000000000 (cc=0) +msc 7FFFFFFFFFFFFFFF * 7FFFFFFFFFFFFFFF = 7FFFFFFF800000017FFFFFFFFFFFFFFF (cc=1) +msrkc 0000000000000000 * 7FFFFFFFFFFFFFFF = 00000000000000000000000000000002 (cc=0) +msrkc 0000000000000001 * 7FFFFFFFFFFFFFFF = 00000000FFFFFFFF0000000000000002 (cc=1) +msrkc 000000000000FFFF * 7FFFFFFFFFFFFFFF = 00000000FFFF00010000000000000002 (cc=1) +msrkc 0000000000007FFF * 7FFFFFFFFFFFFFFF = 00000000FFFF80010000000000000002 (cc=1) +msrkc 0000000000008000 * 7FFFFFFFFFFFFFFF = 00000000FFFF80000000000000000002 (cc=1) +msrkc 00000000FFFFFFFF * 7FFFFFFFFFFFFFFF = 00000000000000010000000000000002 (cc=2) +msrkc 0000000080000000 * 7FFFFFFFFFFFFFFF = 00000000800000000000000000000002 (cc=3) +msrkc 000000007FFFFFFF * 7FFFFFFFFFFFFFFF = 00000000800000010000000000000002 (cc=1) +msrkc FFFFFFFFFFFFFFFF * 7FFFFFFFFFFFFFFF = FFFFFFFF000000010000000000000002 (cc=2) +msrkc 8000000000000000 * 7FFFFFFFFFFFFFFF = 80000000000000000000000000000002 (cc=0) +msrkc 7FFFFFFFFFFFFFFF * 7FFFFFFFFFFFFFFF = 7FFFFFFF000000010000000000000002 (cc=2) +msgc 0000000000000000 * 7FFFFFFFFFFFFFFF = 00000000000000000000000000000000 (cc=0) +msgc 0000000000000001 * 7FFFFFFFFFFFFFFF = 7FFFFFFFFFFFFFFF0000000000000001 (cc=2) +msgc 000000000000FFFF * 7FFFFFFFFFFFFFFF = 7FFFFFFFFFFF0001000000000000FFFF (cc=3) +msgc 0000000000007FFF * 7FFFFFFFFFFFFFFF = 7FFFFFFFFFFF80010000000000007FFF (cc=3) +msgc 0000000000008000 * 7FFFFFFFFFFFFFFF = FFFFFFFFFFFF80000000000000008000 (cc=3) +msgc 00000000FFFFFFFF * 7FFFFFFFFFFFFFFF = 7FFFFFFF0000000100000000FFFFFFFF (cc=3) +msgc 0000000080000000 * 7FFFFFFFFFFFFFFF = FFFFFFFF800000000000000080000000 (cc=3) +msgc 000000007FFFFFFF * 7FFFFFFFFFFFFFFF = 7FFFFFFF80000001000000007FFFFFFF (cc=3) +msgc FFFFFFFFFFFFFFFF * 7FFFFFFFFFFFFFFF = 8000000000000001FFFFFFFFFFFFFFFF (cc=1) +msgc 8000000000000000 * 7FFFFFFFFFFFFFFF = 80000000000000008000000000000000 (cc=3) +msgc 7FFFFFFFFFFFFFFF * 7FFFFFFFFFFFFFFF = 00000000000000017FFFFFFFFFFFFFFF (cc=3) +msgrkc 0000000000000000 * 7FFFFFFFFFFFFFFF = 00000000000000000000000000000002 (cc=0) +msgrkc 0000000000000001 * 7FFFFFFFFFFFFFFF = 7FFFFFFFFFFFFFFF0000000000000002 (cc=2) +msgrkc 000000000000FFFF * 7FFFFFFFFFFFFFFF = 7FFFFFFFFFFF00010000000000000002 (cc=3) +msgrkc 0000000000007FFF * 7FFFFFFFFFFFFFFF = 7FFFFFFFFFFF80010000000000000002 (cc=3) +msgrkc 0000000000008000 * 7FFFFFFFFFFFFFFF = FFFFFFFFFFFF80000000000000000002 (cc=3) +msgrkc 00000000FFFFFFFF * 7FFFFFFFFFFFFFFF = 7FFFFFFF000000010000000000000002 (cc=3) +msgrkc 0000000080000000 * 7FFFFFFFFFFFFFFF = FFFFFFFF800000000000000000000002 (cc=3) +msgrkc 000000007FFFFFFF * 7FFFFFFFFFFFFFFF = 7FFFFFFF800000010000000000000002 (cc=3) +msgrkc FFFFFFFFFFFFFFFF * 7FFFFFFFFFFFFFFF = 80000000000000010000000000000002 (cc=1) +msgrkc 8000000000000000 * 7FFFFFFFFFFFFFFF = 80000000000000000000000000000002 (cc=3) +msgrkc 7FFFFFFFFFFFFFFF * 7FFFFFFFFFFFFFFF = 00000000000000010000000000000002 (cc=3) +mg 0000000000000000 * 8000000000000000 = 00000000000000000000000000000000 (cc=0) +mg 0000000000000001 * 8000000000000000 = FFFFFFFFFFFFFFFF8000000000000000 (cc=0) +mg 000000000000FFFF * 8000000000000000 = FFFFFFFFFFFF80008000000000000000 (cc=0) +mg 0000000000007FFF * 8000000000000000 = FFFFFFFFFFFFC0008000000000000000 (cc=0) +mg 0000000000008000 * 8000000000000000 = FFFFFFFFFFFFC0000000000000000000 (cc=0) +mg 00000000FFFFFFFF * 8000000000000000 = FFFFFFFF800000008000000000000000 (cc=0) +mg 0000000080000000 * 8000000000000000 = FFFFFFFFC00000000000000000000000 (cc=0) +mg 000000007FFFFFFF * 8000000000000000 = FFFFFFFFC00000008000000000000000 (cc=0) +mg FFFFFFFFFFFFFFFF * 8000000000000000 = 00000000000000008000000000000000 (cc=0) +mg 8000000000000000 * 8000000000000000 = 40000000000000000000000000000000 (cc=0) +mg 7FFFFFFFFFFFFFFF * 8000000000000000 = C0000000000000008000000000000000 (cc=0) +mgh 0000000000000000 * 8000000000000000 = 00000000000000000000000000000000 (cc=0) +mgh 0000000000000001 * 8000000000000000 = FFFFFFFFFFFF80000000000000000001 (cc=0) +mgh 000000000000FFFF * 8000000000000000 = FFFFFFFF80008000000000000000FFFF (cc=0) +mgh 0000000000007FFF * 8000000000000000 = FFFFFFFFC00080000000000000007FFF (cc=0) +mgh 0000000000008000 * 8000000000000000 = FFFFFFFFC00000000000000000008000 (cc=0) +mgh 00000000FFFFFFFF * 8000000000000000 = FFFF80000000800000000000FFFFFFFF (cc=0) +mgh 0000000080000000 * 8000000000000000 = FFFFC000000000000000000080000000 (cc=0) +mgh 000000007FFFFFFF * 8000000000000000 = FFFFC00000008000000000007FFFFFFF (cc=0) +mgh FFFFFFFFFFFFFFFF * 8000000000000000 = 0000000000008000FFFFFFFFFFFFFFFF (cc=0) +mgh 8000000000000000 * 8000000000000000 = 00000000000000008000000000000000 (cc=0) +mgh 7FFFFFFFFFFFFFFF * 8000000000000000 = 00000000000080007FFFFFFFFFFFFFFF (cc=0) +mgrk 0000000000000000 * 8000000000000000 = 00000000000000000000000000000000 (cc=0) +mgrk 0000000000000001 * 8000000000000000 = FFFFFFFFFFFFFFFF8000000000000000 (cc=0) +mgrk 000000000000FFFF * 8000000000000000 = FFFFFFFFFFFF80008000000000000000 (cc=0) +mgrk 0000000000007FFF * 8000000000000000 = FFFFFFFFFFFFC0008000000000000000 (cc=0) +mgrk 0000000000008000 * 8000000000000000 = FFFFFFFFFFFFC0000000000000000000 (cc=0) +mgrk 00000000FFFFFFFF * 8000000000000000 = FFFFFFFF800000008000000000000000 (cc=0) +mgrk 0000000080000000 * 8000000000000000 = FFFFFFFFC00000000000000000000000 (cc=0) +mgrk 000000007FFFFFFF * 8000000000000000 = FFFFFFFFC00000008000000000000000 (cc=0) +mgrk FFFFFFFFFFFFFFFF * 8000000000000000 = 00000000000000008000000000000000 (cc=0) +mgrk 8000000000000000 * 8000000000000000 = 40000000000000000000000000000000 (cc=0) +mgrk 7FFFFFFFFFFFFFFF * 8000000000000000 = C0000000000000008000000000000000 (cc=0) +msc 0000000000000000 * 8000000000000000 = 00000000000000000000000000000000 (cc=0) +msc 0000000000000001 * 8000000000000000 = 00000000800000000000000000000001 (cc=1) +msc 000000000000FFFF * 8000000000000000 = 0000000080000000000000000000FFFF (cc=3) +msc 0000000000007FFF * 8000000000000000 = 00000000800000000000000000007FFF (cc=3) +msc 0000000000008000 * 8000000000000000 = 00000000000000000000000000008000 (cc=3) +msc 00000000FFFFFFFF * 8000000000000000 = 000000008000000000000000FFFFFFFF (cc=3) +msc 0000000080000000 * 8000000000000000 = 00000000000000000000000080000000 (cc=3) +msc 000000007FFFFFFF * 8000000000000000 = 0000000080000000000000007FFFFFFF (cc=3) +msc FFFFFFFFFFFFFFFF * 8000000000000000 = FFFFFFFF80000000FFFFFFFFFFFFFFFF (cc=3) +msc 8000000000000000 * 8000000000000000 = 80000000000000008000000000000000 (cc=0) +msc 7FFFFFFFFFFFFFFF * 8000000000000000 = 7FFFFFFF800000007FFFFFFFFFFFFFFF (cc=3) +msrkc 0000000000000000 * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000000000001 * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 000000000000FFFF * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000000007FFF * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000000008000 * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 00000000FFFFFFFF * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000080000000 * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 000000007FFFFFFF * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc FFFFFFFFFFFFFFFF * 8000000000000000 = FFFFFFFF000000000000000000000002 (cc=0) +msrkc 8000000000000000 * 8000000000000000 = 80000000000000000000000000000002 (cc=0) +msrkc 7FFFFFFFFFFFFFFF * 8000000000000000 = 7FFFFFFF000000000000000000000002 (cc=0) +msgc 0000000000000000 * 8000000000000000 = 00000000000000000000000000000000 (cc=0) +msgc 0000000000000001 * 8000000000000000 = 80000000000000000000000000000001 (cc=1) +msgc 000000000000FFFF * 8000000000000000 = 8000000000000000000000000000FFFF (cc=3) +msgc 0000000000007FFF * 8000000000000000 = 80000000000000000000000000007FFF (cc=3) +msgc 0000000000008000 * 8000000000000000 = 00000000000000000000000000008000 (cc=3) +msgc 00000000FFFFFFFF * 8000000000000000 = 800000000000000000000000FFFFFFFF (cc=3) +msgc 0000000080000000 * 8000000000000000 = 00000000000000000000000080000000 (cc=3) +msgc 000000007FFFFFFF * 8000000000000000 = 8000000000000000000000007FFFFFFF (cc=3) +msgc FFFFFFFFFFFFFFFF * 8000000000000000 = 8000000000000000FFFFFFFFFFFFFFFF (cc=3) +msgc 8000000000000000 * 8000000000000000 = 00000000000000008000000000000000 (cc=3) +msgc 7FFFFFFFFFFFFFFF * 8000000000000000 = 80000000000000007FFFFFFFFFFFFFFF (cc=3) +msgrkc 0000000000000000 * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msgrkc 0000000000000001 * 8000000000000000 = 80000000000000000000000000000002 (cc=1) +msgrkc 000000000000FFFF * 8000000000000000 = 80000000000000000000000000000002 (cc=3) +msgrkc 0000000000007FFF * 8000000000000000 = 80000000000000000000000000000002 (cc=3) +msgrkc 0000000000008000 * 8000000000000000 = 00000000000000000000000000000002 (cc=3) +msgrkc 00000000FFFFFFFF * 8000000000000000 = 80000000000000000000000000000002 (cc=3) +msgrkc 0000000080000000 * 8000000000000000 = 00000000000000000000000000000002 (cc=3) +msgrkc 000000007FFFFFFF * 8000000000000000 = 80000000000000000000000000000002 (cc=3) +msgrkc FFFFFFFFFFFFFFFF * 8000000000000000 = 80000000000000000000000000000002 (cc=3) +msgrkc 8000000000000000 * 8000000000000000 = 00000000000000000000000000000002 (cc=3) +msgrkc 7FFFFFFFFFFFFFFF * 8000000000000000 = 80000000000000000000000000000002 (cc=3) +mg 0000000000000000 * FFFFFFFFFFFFFFFF = 00000000000000000000000000000000 (cc=0) +mg 0000000000000001 * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF (cc=0) +mg 000000000000FFFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFFFFFFFFFFFFFF0001 (cc=0) +mg 0000000000007FFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFFFFFFFFFFFFFF8001 (cc=0) +mg 0000000000008000 * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFFFFFFFFFFFFFF8000 (cc=0) +mg 00000000FFFFFFFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFFFFFFFFFF00000001 (cc=0) +mg 0000000080000000 * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFFFFFFFFFF80000000 (cc=0) +mg 000000007FFFFFFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFFFFFFFFFF80000001 (cc=0) +mg FFFFFFFFFFFFFFFF * FFFFFFFFFFFFFFFF = 00000000000000000000000000000001 (cc=0) +mg 8000000000000000 * FFFFFFFFFFFFFFFF = 00000000000000008000000000000000 (cc=0) +mg 7FFFFFFFFFFFFFFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFF8000000000000001 (cc=0) +mgh 0000000000000000 * FFFFFFFFFFFFFFFF = 00000000000000000000000000000000 (cc=0) +mgh 0000000000000001 * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFF0000000000000001 (cc=0) +mgh 000000000000FFFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFF0001000000000000FFFF (cc=0) +mgh 0000000000007FFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFF80010000000000007FFF (cc=0) +mgh 0000000000008000 * FFFFFFFFFFFFFFFF = FFFFFFFFFFFF80000000000000008000 (cc=0) +mgh 00000000FFFFFFFF * FFFFFFFFFFFFFFFF = FFFFFFFF0000000100000000FFFFFFFF (cc=0) +mgh 0000000080000000 * FFFFFFFFFFFFFFFF = FFFFFFFF800000000000000080000000 (cc=0) +mgh 000000007FFFFFFF * FFFFFFFFFFFFFFFF = FFFFFFFF80000001000000007FFFFFFF (cc=0) +mgh FFFFFFFFFFFFFFFF * FFFFFFFFFFFFFFFF = 0000000000000001FFFFFFFFFFFFFFFF (cc=0) +mgh 8000000000000000 * FFFFFFFFFFFFFFFF = 80000000000000008000000000000000 (cc=0) +mgh 7FFFFFFFFFFFFFFF * FFFFFFFFFFFFFFFF = 80000000000000017FFFFFFFFFFFFFFF (cc=0) +mgrk 0000000000000000 * FFFFFFFFFFFFFFFF = 00000000000000000000000000000000 (cc=0) +mgrk 0000000000000001 * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF (cc=0) +mgrk 000000000000FFFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFFFFFFFFFFFFFF0001 (cc=0) +mgrk 0000000000007FFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFFFFFFFFFFFFFF8001 (cc=0) +mgrk 0000000000008000 * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFFFFFFFFFFFFFF8000 (cc=0) +mgrk 00000000FFFFFFFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFFFFFFFFFF00000001 (cc=0) +mgrk 0000000080000000 * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFFFFFFFFFF80000000 (cc=0) +mgrk 000000007FFFFFFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFFFFFFFFFF80000001 (cc=0) +mgrk FFFFFFFFFFFFFFFF * FFFFFFFFFFFFFFFF = 00000000000000000000000000000001 (cc=0) +mgrk 8000000000000000 * FFFFFFFFFFFFFFFF = 00000000000000008000000000000000 (cc=0) +mgrk 7FFFFFFFFFFFFFFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFF8000000000000001 (cc=0) +msc 0000000000000000 * FFFFFFFFFFFFFFFF = 00000000000000000000000000000000 (cc=0) +msc 0000000000000001 * FFFFFFFFFFFFFFFF = 00000000FFFFFFFF0000000000000001 (cc=1) +msc 000000000000FFFF * FFFFFFFFFFFFFFFF = 00000000FFFF0001000000000000FFFF (cc=1) +msc 0000000000007FFF * FFFFFFFFFFFFFFFF = 00000000FFFF80010000000000007FFF (cc=1) +msc 0000000000008000 * FFFFFFFFFFFFFFFF = 00000000FFFF80000000000000008000 (cc=1) +msc 00000000FFFFFFFF * FFFFFFFFFFFFFFFF = 000000000000000100000000FFFFFFFF (cc=2) +msc 0000000080000000 * FFFFFFFFFFFFFFFF = 00000000800000000000000080000000 (cc=3) +msc 000000007FFFFFFF * FFFFFFFFFFFFFFFF = 0000000080000001000000007FFFFFFF (cc=1) +msc FFFFFFFFFFFFFFFF * FFFFFFFFFFFFFFFF = FFFFFFFF00000001FFFFFFFFFFFFFFFF (cc=2) +msc 8000000000000000 * FFFFFFFFFFFFFFFF = 80000000000000008000000000000000 (cc=0) +msc 7FFFFFFFFFFFFFFF * FFFFFFFFFFFFFFFF = 7FFFFFFF000000017FFFFFFFFFFFFFFF (cc=2) +msrkc 0000000000000000 * FFFFFFFFFFFFFFFF = 00000000000000000000000000000002 (cc=0) +msrkc 0000000000000001 * FFFFFFFFFFFFFFFF = 00000000FFFFFFFF0000000000000002 (cc=1) +msrkc 000000000000FFFF * FFFFFFFFFFFFFFFF = 00000000FFFF00010000000000000002 (cc=1) +msrkc 0000000000007FFF * FFFFFFFFFFFFFFFF = 00000000FFFF80010000000000000002 (cc=1) +msrkc 0000000000008000 * FFFFFFFFFFFFFFFF = 00000000FFFF80000000000000000002 (cc=1) +msrkc 00000000FFFFFFFF * FFFFFFFFFFFFFFFF = 00000000000000010000000000000002 (cc=2) +msrkc 0000000080000000 * FFFFFFFFFFFFFFFF = 00000000800000000000000000000002 (cc=3) +msrkc 000000007FFFFFFF * FFFFFFFFFFFFFFFF = 00000000800000010000000000000002 (cc=1) +msrkc FFFFFFFFFFFFFFFF * FFFFFFFFFFFFFFFF = FFFFFFFF000000010000000000000002 (cc=2) +msrkc 8000000000000000 * FFFFFFFFFFFFFFFF = 80000000000000000000000000000002 (cc=0) +msrkc 7FFFFFFFFFFFFFFF * FFFFFFFFFFFFFFFF = 7FFFFFFF000000010000000000000002 (cc=2) +msgc 0000000000000000 * FFFFFFFFFFFFFFFF = 00000000000000000000000000000000 (cc=0) +msgc 0000000000000001 * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFF0000000000000001 (cc=1) +msgc 000000000000FFFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFF0001000000000000FFFF (cc=1) +msgc 0000000000007FFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFF80010000000000007FFF (cc=1) +msgc 0000000000008000 * FFFFFFFFFFFFFFFF = FFFFFFFFFFFF80000000000000008000 (cc=1) +msgc 00000000FFFFFFFF * FFFFFFFFFFFFFFFF = FFFFFFFF0000000100000000FFFFFFFF (cc=1) +msgc 0000000080000000 * FFFFFFFFFFFFFFFF = FFFFFFFF800000000000000080000000 (cc=1) +msgc 000000007FFFFFFF * FFFFFFFFFFFFFFFF = FFFFFFFF80000001000000007FFFFFFF (cc=1) +msgc FFFFFFFFFFFFFFFF * FFFFFFFFFFFFFFFF = 0000000000000001FFFFFFFFFFFFFFFF (cc=2) +msgc 8000000000000000 * FFFFFFFFFFFFFFFF = 80000000000000008000000000000000 (cc=3) +msgc 7FFFFFFFFFFFFFFF * FFFFFFFFFFFFFFFF = 80000000000000017FFFFFFFFFFFFFFF (cc=1) +msgrkc 0000000000000000 * FFFFFFFFFFFFFFFF = 00000000000000000000000000000002 (cc=0) +msgrkc 0000000000000001 * FFFFFFFFFFFFFFFF = FFFFFFFFFFFFFFFF0000000000000002 (cc=1) +msgrkc 000000000000FFFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFF00010000000000000002 (cc=1) +msgrkc 0000000000007FFF * FFFFFFFFFFFFFFFF = FFFFFFFFFFFF80010000000000000002 (cc=1) +msgrkc 0000000000008000 * FFFFFFFFFFFFFFFF = FFFFFFFFFFFF80000000000000000002 (cc=1) +msgrkc 00000000FFFFFFFF * FFFFFFFFFFFFFFFF = FFFFFFFF000000010000000000000002 (cc=1) +msgrkc 0000000080000000 * FFFFFFFFFFFFFFFF = FFFFFFFF800000000000000000000002 (cc=1) +msgrkc 000000007FFFFFFF * FFFFFFFFFFFFFFFF = FFFFFFFF800000010000000000000002 (cc=1) +msgrkc FFFFFFFFFFFFFFFF * FFFFFFFFFFFFFFFF = 00000000000000010000000000000002 (cc=2) +msgrkc 8000000000000000 * FFFFFFFFFFFFFFFF = 80000000000000000000000000000002 (cc=3) +msgrkc 7FFFFFFFFFFFFFFF * FFFFFFFFFFFFFFFF = 80000000000000010000000000000002 (cc=1) +mg 0000000000000000 * 7FFFFFFF00000000 = 00000000000000000000000000000000 (cc=0) +mg 0000000000000001 * 7FFFFFFF00000000 = 00000000000000007FFFFFFF00000000 (cc=0) +mg 000000000000FFFF * 7FFFFFFF00000000 = 0000000000007FFF7FFF000100000000 (cc=0) +mg 0000000000007FFF * 7FFFFFFF00000000 = 0000000000003FFF7FFF800100000000 (cc=0) +mg 0000000000008000 * 7FFFFFFF00000000 = 0000000000003FFFFFFF800000000000 (cc=0) +mg 00000000FFFFFFFF * 7FFFFFFF00000000 = 000000007FFFFFFE8000000100000000 (cc=0) +mg 0000000080000000 * 7FFFFFFF00000000 = 000000003FFFFFFF8000000000000000 (cc=0) +mg 000000007FFFFFFF * 7FFFFFFF00000000 = 000000003FFFFFFF0000000100000000 (cc=0) +mg FFFFFFFFFFFFFFFF * 7FFFFFFF00000000 = FFFFFFFFFFFFFFFF8000000100000000 (cc=0) +mg 8000000000000000 * 7FFFFFFF00000000 = C0000000800000000000000000000000 (cc=0) +mg 7FFFFFFFFFFFFFFF * 7FFFFFFF00000000 = 3FFFFFFF7FFFFFFF8000000100000000 (cc=0) +mgh 0000000000000000 * 7FFFFFFF00000000 = 00000000000000000000000000000000 (cc=0) +mgh 0000000000000001 * 7FFFFFFF00000000 = 0000000000007FFF0000000000000001 (cc=0) +mgh 000000000000FFFF * 7FFFFFFF00000000 = 000000007FFE8001000000000000FFFF (cc=0) +mgh 0000000000007FFF * 7FFFFFFF00000000 = 000000003FFF00010000000000007FFF (cc=0) +mgh 0000000000008000 * 7FFFFFFF00000000 = 000000003FFF80000000000000008000 (cc=0) +mgh 00000000FFFFFFFF * 7FFFFFFF00000000 = 00007FFEFFFF800100000000FFFFFFFF (cc=0) +mgh 0000000080000000 * 7FFFFFFF00000000 = 00003FFF800000000000000080000000 (cc=0) +mgh 000000007FFFFFFF * 7FFFFFFF00000000 = 00003FFF7FFF8001000000007FFFFFFF (cc=0) +mgh FFFFFFFFFFFFFFFF * 7FFFFFFF00000000 = FFFFFFFFFFFF8001FFFFFFFFFFFFFFFF (cc=0) +mgh 8000000000000000 * 7FFFFFFF00000000 = 80000000000000008000000000000000 (cc=0) +mgh 7FFFFFFFFFFFFFFF * 7FFFFFFF00000000 = 7FFFFFFFFFFF80017FFFFFFFFFFFFFFF (cc=0) +mgrk 0000000000000000 * 7FFFFFFF00000000 = 00000000000000000000000000000000 (cc=0) +mgrk 0000000000000001 * 7FFFFFFF00000000 = 00000000000000007FFFFFFF00000000 (cc=0) +mgrk 000000000000FFFF * 7FFFFFFF00000000 = 0000000000007FFF7FFF000100000000 (cc=0) +mgrk 0000000000007FFF * 7FFFFFFF00000000 = 0000000000003FFF7FFF800100000000 (cc=0) +mgrk 0000000000008000 * 7FFFFFFF00000000 = 0000000000003FFFFFFF800000000000 (cc=0) +mgrk 00000000FFFFFFFF * 7FFFFFFF00000000 = 000000007FFFFFFE8000000100000000 (cc=0) +mgrk 0000000080000000 * 7FFFFFFF00000000 = 000000003FFFFFFF8000000000000000 (cc=0) +mgrk 000000007FFFFFFF * 7FFFFFFF00000000 = 000000003FFFFFFF0000000100000000 (cc=0) +mgrk FFFFFFFFFFFFFFFF * 7FFFFFFF00000000 = FFFFFFFFFFFFFFFF8000000100000000 (cc=0) +mgrk 8000000000000000 * 7FFFFFFF00000000 = C0000000800000000000000000000000 (cc=0) +mgrk 7FFFFFFFFFFFFFFF * 7FFFFFFF00000000 = 3FFFFFFF7FFFFFFF8000000100000000 (cc=0) +msc 0000000000000000 * 7FFFFFFF00000000 = 00000000000000000000000000000000 (cc=0) +msc 0000000000000001 * 7FFFFFFF00000000 = 000000007FFFFFFF0000000000000001 (cc=2) +msc 000000000000FFFF * 7FFFFFFF00000000 = 000000007FFF0001000000000000FFFF (cc=3) +msc 0000000000007FFF * 7FFFFFFF00000000 = 000000007FFF80010000000000007FFF (cc=3) +msc 0000000000008000 * 7FFFFFFF00000000 = 00000000FFFF80000000000000008000 (cc=3) +msc 00000000FFFFFFFF * 7FFFFFFF00000000 = 000000008000000100000000FFFFFFFF (cc=1) +msc 0000000080000000 * 7FFFFFFF00000000 = 00000000800000000000000080000000 (cc=3) +msc 000000007FFFFFFF * 7FFFFFFF00000000 = 0000000000000001000000007FFFFFFF (cc=3) +msc FFFFFFFFFFFFFFFF * 7FFFFFFF00000000 = FFFFFFFF80000001FFFFFFFFFFFFFFFF (cc=1) +msc 8000000000000000 * 7FFFFFFF00000000 = 80000000000000008000000000000000 (cc=0) +msc 7FFFFFFFFFFFFFFF * 7FFFFFFF00000000 = 7FFFFFFF800000017FFFFFFFFFFFFFFF (cc=1) +msrkc 0000000000000000 * 7FFFFFFF00000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000000000001 * 7FFFFFFF00000000 = 00000000000000000000000000000002 (cc=0) +msrkc 000000000000FFFF * 7FFFFFFF00000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000000007FFF * 7FFFFFFF00000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000000008000 * 7FFFFFFF00000000 = 00000000000000000000000000000002 (cc=0) +msrkc 00000000FFFFFFFF * 7FFFFFFF00000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000080000000 * 7FFFFFFF00000000 = 00000000000000000000000000000002 (cc=0) +msrkc 000000007FFFFFFF * 7FFFFFFF00000000 = 00000000000000000000000000000002 (cc=0) +msrkc FFFFFFFFFFFFFFFF * 7FFFFFFF00000000 = FFFFFFFF000000000000000000000002 (cc=0) +msrkc 8000000000000000 * 7FFFFFFF00000000 = 80000000000000000000000000000002 (cc=0) +msrkc 7FFFFFFFFFFFFFFF * 7FFFFFFF00000000 = 7FFFFFFF000000000000000000000002 (cc=0) +msgc 0000000000000000 * 7FFFFFFF00000000 = 00000000000000000000000000000000 (cc=0) +msgc 0000000000000001 * 7FFFFFFF00000000 = 7FFFFFFF000000000000000000000001 (cc=2) +msgc 000000000000FFFF * 7FFFFFFF00000000 = 7FFF000100000000000000000000FFFF (cc=3) +msgc 0000000000007FFF * 7FFFFFFF00000000 = 7FFF8001000000000000000000007FFF (cc=3) +msgc 0000000000008000 * 7FFFFFFF00000000 = FFFF8000000000000000000000008000 (cc=3) +msgc 00000000FFFFFFFF * 7FFFFFFF00000000 = 800000010000000000000000FFFFFFFF (cc=3) +msgc 0000000080000000 * 7FFFFFFF00000000 = 80000000000000000000000080000000 (cc=3) +msgc 000000007FFFFFFF * 7FFFFFFF00000000 = 0000000100000000000000007FFFFFFF (cc=3) +msgc FFFFFFFFFFFFFFFF * 7FFFFFFF00000000 = 8000000100000000FFFFFFFFFFFFFFFF (cc=1) +msgc 8000000000000000 * 7FFFFFFF00000000 = 00000000000000008000000000000000 (cc=3) +msgc 7FFFFFFFFFFFFFFF * 7FFFFFFF00000000 = 80000001000000007FFFFFFFFFFFFFFF (cc=3) +msgrkc 0000000000000000 * 7FFFFFFF00000000 = 00000000000000000000000000000002 (cc=0) +msgrkc 0000000000000001 * 7FFFFFFF00000000 = 7FFFFFFF000000000000000000000002 (cc=2) +msgrkc 000000000000FFFF * 7FFFFFFF00000000 = 7FFF0001000000000000000000000002 (cc=3) +msgrkc 0000000000007FFF * 7FFFFFFF00000000 = 7FFF8001000000000000000000000002 (cc=3) +msgrkc 0000000000008000 * 7FFFFFFF00000000 = FFFF8000000000000000000000000002 (cc=3) +msgrkc 00000000FFFFFFFF * 7FFFFFFF00000000 = 80000001000000000000000000000002 (cc=3) +msgrkc 0000000080000000 * 7FFFFFFF00000000 = 80000000000000000000000000000002 (cc=3) +msgrkc 000000007FFFFFFF * 7FFFFFFF00000000 = 00000001000000000000000000000002 (cc=3) +msgrkc FFFFFFFFFFFFFFFF * 7FFFFFFF00000000 = 80000001000000000000000000000002 (cc=1) +msgrkc 8000000000000000 * 7FFFFFFF00000000 = 00000000000000000000000000000002 (cc=3) +msgrkc 7FFFFFFFFFFFFFFF * 7FFFFFFF00000000 = 80000001000000000000000000000002 (cc=3) +mg 0000000000000000 * 8000000000000000 = 00000000000000000000000000000000 (cc=0) +mg 0000000000000001 * 8000000000000000 = FFFFFFFFFFFFFFFF8000000000000000 (cc=0) +mg 000000000000FFFF * 8000000000000000 = FFFFFFFFFFFF80008000000000000000 (cc=0) +mg 0000000000007FFF * 8000000000000000 = FFFFFFFFFFFFC0008000000000000000 (cc=0) +mg 0000000000008000 * 8000000000000000 = FFFFFFFFFFFFC0000000000000000000 (cc=0) +mg 00000000FFFFFFFF * 8000000000000000 = FFFFFFFF800000008000000000000000 (cc=0) +mg 0000000080000000 * 8000000000000000 = FFFFFFFFC00000000000000000000000 (cc=0) +mg 000000007FFFFFFF * 8000000000000000 = FFFFFFFFC00000008000000000000000 (cc=0) +mg FFFFFFFFFFFFFFFF * 8000000000000000 = 00000000000000008000000000000000 (cc=0) +mg 8000000000000000 * 8000000000000000 = 40000000000000000000000000000000 (cc=0) +mg 7FFFFFFFFFFFFFFF * 8000000000000000 = C0000000000000008000000000000000 (cc=0) +mgh 0000000000000000 * 8000000000000000 = 00000000000000000000000000000000 (cc=0) +mgh 0000000000000001 * 8000000000000000 = FFFFFFFFFFFF80000000000000000001 (cc=0) +mgh 000000000000FFFF * 8000000000000000 = FFFFFFFF80008000000000000000FFFF (cc=0) +mgh 0000000000007FFF * 8000000000000000 = FFFFFFFFC00080000000000000007FFF (cc=0) +mgh 0000000000008000 * 8000000000000000 = FFFFFFFFC00000000000000000008000 (cc=0) +mgh 00000000FFFFFFFF * 8000000000000000 = FFFF80000000800000000000FFFFFFFF (cc=0) +mgh 0000000080000000 * 8000000000000000 = FFFFC000000000000000000080000000 (cc=0) +mgh 000000007FFFFFFF * 8000000000000000 = FFFFC00000008000000000007FFFFFFF (cc=0) +mgh FFFFFFFFFFFFFFFF * 8000000000000000 = 0000000000008000FFFFFFFFFFFFFFFF (cc=0) +mgh 8000000000000000 * 8000000000000000 = 00000000000000008000000000000000 (cc=0) +mgh 7FFFFFFFFFFFFFFF * 8000000000000000 = 00000000000080007FFFFFFFFFFFFFFF (cc=0) +mgrk 0000000000000000 * 8000000000000000 = 00000000000000000000000000000000 (cc=0) +mgrk 0000000000000001 * 8000000000000000 = FFFFFFFFFFFFFFFF8000000000000000 (cc=0) +mgrk 000000000000FFFF * 8000000000000000 = FFFFFFFFFFFF80008000000000000000 (cc=0) +mgrk 0000000000007FFF * 8000000000000000 = FFFFFFFFFFFFC0008000000000000000 (cc=0) +mgrk 0000000000008000 * 8000000000000000 = FFFFFFFFFFFFC0000000000000000000 (cc=0) +mgrk 00000000FFFFFFFF * 8000000000000000 = FFFFFFFF800000008000000000000000 (cc=0) +mgrk 0000000080000000 * 8000000000000000 = FFFFFFFFC00000000000000000000000 (cc=0) +mgrk 000000007FFFFFFF * 8000000000000000 = FFFFFFFFC00000008000000000000000 (cc=0) +mgrk FFFFFFFFFFFFFFFF * 8000000000000000 = 00000000000000008000000000000000 (cc=0) +mgrk 8000000000000000 * 8000000000000000 = 40000000000000000000000000000000 (cc=0) +mgrk 7FFFFFFFFFFFFFFF * 8000000000000000 = C0000000000000008000000000000000 (cc=0) +msc 0000000000000000 * 8000000000000000 = 00000000000000000000000000000000 (cc=0) +msc 0000000000000001 * 8000000000000000 = 00000000800000000000000000000001 (cc=1) +msc 000000000000FFFF * 8000000000000000 = 0000000080000000000000000000FFFF (cc=3) +msc 0000000000007FFF * 8000000000000000 = 00000000800000000000000000007FFF (cc=3) +msc 0000000000008000 * 8000000000000000 = 00000000000000000000000000008000 (cc=3) +msc 00000000FFFFFFFF * 8000000000000000 = 000000008000000000000000FFFFFFFF (cc=3) +msc 0000000080000000 * 8000000000000000 = 00000000000000000000000080000000 (cc=3) +msc 000000007FFFFFFF * 8000000000000000 = 0000000080000000000000007FFFFFFF (cc=3) +msc FFFFFFFFFFFFFFFF * 8000000000000000 = FFFFFFFF80000000FFFFFFFFFFFFFFFF (cc=3) +msc 8000000000000000 * 8000000000000000 = 80000000000000008000000000000000 (cc=0) +msc 7FFFFFFFFFFFFFFF * 8000000000000000 = 7FFFFFFF800000007FFFFFFFFFFFFFFF (cc=3) +msrkc 0000000000000000 * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000000000001 * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 000000000000FFFF * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000000007FFF * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000000008000 * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 00000000FFFFFFFF * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 0000000080000000 * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc 000000007FFFFFFF * 8000000000000000 = 00000000000000000000000000000002 (cc=0) +msrkc FFFFFFFFFFFFFFFF * 8000000000000000 = FFFFFFFF000000000000000000000002 (cc=0) +msrkc 8000000000000000 * 8000000000000000 = 80000000000000000000000000000002 (cc=0) +msrkc 7FFFFFFFFFFFFFFF * 8000000000000000 = 7FFFFFFF000000000000000000000002 (cc=0) +msgc 0000000000000000 * 8000000000000000 = 00000000000000000000000000000000 (cc=0) +msgc 0000000000000001 * 8000000000000000 = 80000000000000000000000000000001 (cc=1) +msgc 000000000000FFFF * 8000000000000000 = 8000000000000000000000000000FFFF (cc=3) +msgc 000000... [truncated message content] |
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From: Andreas A. <ar...@so...> - 2019-06-12 18:24:11
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=50b20aa244c1fddd9b9e872526d4daad49ddd7a5 commit 50b20aa244c1fddd9b9e872526d4daad49ddd7a5 Author: Ilya Leoshkevich <ii...@li...> Date: Thu May 16 12:34:37 2019 +0200 Bug 404406 - s390x: implement z14 miscellaneous instructions (from bug 404406 comment 0): Valgrind on s390x currently lacks support for the miscellaneous instruction extensions facility 2. Signed-off-by: Ilya Leoshkevich <ii...@li...> Diff: --- NEWS | 1 + VEX/priv/guest_s390_defs.h | 4 +- VEX/priv/guest_s390_helpers.c | 16 +++ VEX/priv/guest_s390_toIR.c | 219 +++++++++++++++++++++++++++++++++++++--- VEX/priv/host_s390_defs.c | 26 ++++- VEX/priv/host_s390_isel.c | 7 +- VEX/priv/main_main.c | 1 + VEX/priv/s390_disasm.c | 10 ++ VEX/priv/s390_disasm.h | 3 +- VEX/pub/libvex.h | 4 +- VEX/pub/libvex_s390x_common.h | 1 + coregrind/m_machine.c | 3 +- docs/internals/s390-opcodes.csv | 22 ++-- 13 files changed, 285 insertions(+), 32 deletions(-) diff --git a/NEWS b/NEWS index 905a868..770a231 100644 --- a/NEWS +++ b/NEWS @@ -54,6 +54,7 @@ where XXXXXX is the bug number as listed below. 407764 drd cond_post_wait gets wrong (?) condition on s390x z13 system 408009 Expose rdrand and f16c even on avx if host cpu supports them 408091 Missing pkey syscalls +404406 s390x: z14 miscellaneous instructions not implemented n-i-bz Fix minor one time leaks in dhat. n-i-bz Add --run-cxx-freeres=no in outer args to avoid inner crashes. diff --git a/VEX/priv/guest_s390_defs.h b/VEX/priv/guest_s390_defs.h index 0185de5..1470558 100644 --- a/VEX/priv/guest_s390_defs.h +++ b/VEX/priv/guest_s390_defs.h @@ -158,7 +158,9 @@ enum { S390_CC_OP_DFP_128_TO_INT_64 = 57, S390_CC_OP_PFPO_32 = 58, S390_CC_OP_PFPO_64 = 59, - S390_CC_OP_PFPO_128 = 60 + S390_CC_OP_PFPO_128 = 60, + S390_CC_OP_MUL_32 = 61, + S390_CC_OP_MUL_64 = 62 }; /*------------------------------------------------------------*/ diff --git a/VEX/priv/guest_s390_helpers.c b/VEX/priv/guest_s390_helpers.c index 63ee68b..525e700 100644 --- a/VEX/priv/guest_s390_helpers.c +++ b/VEX/priv/guest_s390_helpers.c @@ -990,6 +990,16 @@ decode_bfp_rounding_mode(UInt irrm) psw >> 28; /* cc */ \ }) +#define S390_CC_FOR_TERNARY(opcode,cc_dep1,cc_dep2) \ +({ \ + __asm__ volatile ( \ + opcode ",%[op1],%[op1],%[op2],0\n\t" \ + "ipm %[psw]\n\t" : [psw] "=d"(psw), [op1] "+d"(cc_dep1) \ + : [op2] "d"(cc_dep2) \ + : "cc");\ + psw >> 28; /* cc */ \ +}) + #define S390_CC_FOR_TERNARY_SUBB(opcode,cc_dep1,cc_dep2,cc_ndep) \ ({ \ /* Recover the original DEP2 value. See comment near s390_cc_thunk_put3 \ @@ -1802,6 +1812,12 @@ s390_calculate_cc(ULong cc_op, ULong cc_dep1, ULong cc_dep2, ULong cc_ndep) return psw >> 28; /* cc */ } + case S390_CC_OP_MUL_32: + return S390_CC_FOR_TERNARY(".insn rrf,0xb9fd0000", cc_dep1, cc_dep2); + + case S390_CC_OP_MUL_64: + return S390_CC_FOR_TERNARY(".insn rrf,0xb9ed0000", cc_dep1, cc_dep2); + default: break; } diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index 076a421..06ec27f 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -49,7 +49,7 @@ static UInt s390_decode_and_irgen(const UChar *, UInt, DisResult *); static void s390_irgen_xonc(IROp, IRTemp, IRTemp, IRTemp); static void s390_irgen_CLC_EX(IRTemp, IRTemp, IRTemp); - +static const HChar *s390_irgen_BIC(UChar r1, IRTemp op2addr); /*------------------------------------------------------------*/ /*--- Globals ---*/ @@ -3314,8 +3314,12 @@ s390_format_RXY_RRRD(const HChar *(*irgen)(UChar r1, IRTemp op2addr), mnm = irgen(r1, op2addr); - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - s390_disasm(ENC3(MNM, GPR, SDXB), mnm, r1, dh2, dl2, x2, b2); + if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) { + if (irgen == s390_irgen_BIC) + s390_disasm(ENC2(XMNM, SDXB), S390_XMNM_BIC, r1, dh2, dl2, x2, b2); + else + s390_disasm(ENC3(MNM, GPR, SDXB), mnm, r1, dh2, dl2, x2, b2); + } } static void @@ -4281,6 +4285,22 @@ s390_irgen_AHIK(UChar r1, UChar r3, UShort i2) } static const HChar * +s390_irgen_AGH(UChar r1, IRTemp op2addr) +{ + IRTemp op1 = newTemp(Ity_I64); + IRTemp op2 = newTemp(Ity_I64); + IRTemp result = newTemp(Ity_I64); + + assign(op1, get_gpr_dw0(r1)); + assign(op2, unop(Iop_16Sto64, load(Ity_I16, mkexpr(op2addr)))); + assign(result, binop(Iop_Add64, mkexpr(op1), mkexpr(op2))); + s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_64, op1, op2); + put_gpr_dw0(r1, mkexpr(result)); + + return "agh"; +} + +static const HChar * s390_irgen_AGHIK(UChar r1, UChar r3, UShort i2) { Long op2; @@ -5198,6 +5218,24 @@ s390_irgen_BCTG(UChar r1, IRTemp op2addr) } static const HChar * +s390_irgen_BIC(UChar r1, IRTemp op2addr) +{ + IRTemp cond = newTemp(Ity_I32); + + if (r1 == 0) { + /* nothing */ + } else if (r1 == 15) { + always_goto(load(Ity_I64, mkexpr(op2addr))); + } else { + assign(cond, s390_call_calculate_cond(r1)); + if_condition_goto_computed(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), + load(Ity_I64, mkexpr(op2addr))); + } + + return "bic"; +} + +static const HChar * s390_irgen_BXH(UChar r1, UChar r3, IRTemp op2addr) { IRTemp value = newTemp(Ity_I32); @@ -8334,6 +8372,54 @@ s390_irgen_MFY(UChar r1, IRTemp op2addr) } static const HChar * +s390_irgen_MG(UChar r1, IRTemp op2addr) +{ + IRTemp op1 = newTemp(Ity_I64); + IRTemp op2 = newTemp(Ity_I64); + IRTemp result = newTemp(Ity_I128); + + assign(op1, get_gpr_dw0(r1 + 1)); + assign(op2, load(Ity_I64, mkexpr(op2addr))); + assign(result, binop(Iop_MullS64, mkexpr(op1), mkexpr(op2))); + put_gpr_dw0(r1, unop(Iop_128HIto64, mkexpr(result))); + put_gpr_dw0(r1 + 1, unop(Iop_128to64, mkexpr(result))); + + return "mg"; +} + +static const HChar * +s390_irgen_MGH(UChar r1, IRTemp op2addr) +{ + IRTemp op1 = newTemp(Ity_I64); + IRTemp op2 = newTemp(Ity_I16); + IRTemp result = newTemp(Ity_I128); + + assign(op1, get_gpr_dw0(r1)); + assign(op2, load(Ity_I16, mkexpr(op2addr))); + assign(result, binop(Iop_MullS64, mkexpr(op1), unop(Iop_16Sto64, mkexpr(op2)) + )); + put_gpr_dw0(r1, unop(Iop_128to64, mkexpr(result))); + + return "mgh"; +} + +static const HChar * +s390_irgen_MGRK(UChar r3, UChar r1, UChar r2) +{ + IRTemp op2 = newTemp(Ity_I64); + IRTemp op3 = newTemp(Ity_I64); + IRTemp result = newTemp(Ity_I128); + + assign(op2, get_gpr_dw0(r2)); + assign(op3, get_gpr_dw0(r3)); + assign(result, binop(Iop_MullS64, mkexpr(op2), mkexpr(op3))); + put_gpr_dw0(r1, unop(Iop_128HIto64, mkexpr(result))); + put_gpr_dw0(r1 + 1, unop(Iop_128to64, mkexpr(result))); + + return "mgrk"; +} + +static const HChar * s390_irgen_MH(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -8523,6 +8609,38 @@ s390_irgen_MS(UChar r1, IRTemp op2addr) } static const HChar * +s390_irgen_MSC(UChar r1, IRTemp op2addr) +{ + IRTemp op1 = newTemp(Ity_I32); + IRTemp op2 = newTemp(Ity_I32); + IRTemp result = newTemp(Ity_I64); + + assign(op1, get_gpr_w1(r1)); + assign(op2, load(Ity_I32, mkexpr(op2addr))); + assign(result, binop(Iop_MullS32, mkexpr(op1), mkexpr(op2))); + s390_cc_thunk_putSS(S390_CC_OP_MUL_32, op1, op2); + put_gpr_w1(r1, unop(Iop_64to32, mkexpr(result))); + + return "msc"; +} + +static const HChar * +s390_irgen_MSRKC(UChar r3, UChar r1, UChar r2) +{ + IRTemp op2 = newTemp(Ity_I32); + IRTemp op3 = newTemp(Ity_I32); + IRTemp result = newTemp(Ity_I64); + + assign(op2, get_gpr_w1(r2)); + assign(op3, get_gpr_w1(r3)); + assign(result, binop(Iop_MullS32, mkexpr(op2), mkexpr(op3))); + s390_cc_thunk_putSS(S390_CC_OP_MUL_32, op2, op3); + put_gpr_w1(r1, unop(Iop_64to32, mkexpr(result))); + + return "msrkc"; +} + +static const HChar * s390_irgen_MSY(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -8553,6 +8671,22 @@ s390_irgen_MSG(UChar r1, IRTemp op2addr) } static const HChar * +s390_irgen_MSGC(UChar r1, IRTemp op2addr) +{ + IRTemp op1 = newTemp(Ity_I64); + IRTemp op2 = newTemp(Ity_I64); + IRTemp result = newTemp(Ity_I128); + + assign(op1, get_gpr_dw0(r1)); + assign(op2, load(Ity_I64, mkexpr(op2addr))); + assign(result, binop(Iop_MullS64, mkexpr(op1), mkexpr(op2))); + s390_cc_thunk_putSS(S390_CC_OP_MUL_64, op1, op2); + put_gpr_dw0(r1, unop(Iop_128to64, mkexpr(result))); + + return "msgc"; +} + +static const HChar * s390_irgen_MSGF(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -8600,6 +8734,22 @@ s390_irgen_MSGFI(UChar r1, UInt i2) } static const HChar * +s390_irgen_MSGRKC(UChar r3, UChar r1, UChar r2) +{ + IRTemp op2 = newTemp(Ity_I64); + IRTemp op3 = newTemp(Ity_I64); + IRTemp result = newTemp(Ity_I128); + + assign(op2, get_gpr_dw0(r2)); + assign(op3, get_gpr_dw0(r3)); + assign(result, binop(Iop_MullS64, mkexpr(op2), mkexpr(op3))); + s390_cc_thunk_putSS(S390_CC_OP_MUL_64, op2, op3); + put_gpr_dw0(r1, unop(Iop_128to64, mkexpr(result))); + + return "msgrkc"; +} + +static const HChar * s390_irgen_OR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -10061,6 +10211,22 @@ s390_irgen_SGF(UChar r1, IRTemp op2addr) } static const HChar * +s390_irgen_SGH(UChar r1, IRTemp op2addr) +{ + IRTemp op1 = newTemp(Ity_I64); + IRTemp op2 = newTemp(Ity_I64); + IRTemp result = newTemp(Ity_I64); + + assign(op1, get_gpr_dw0(r1)); + assign(op2, unop(Iop_16Sto64, load(Ity_I16, mkexpr(op2addr)))); + assign(result, binop(Iop_Sub64, mkexpr(op1), mkexpr(op2))); + s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_64, op1, op2); + put_gpr_dw0(r1, mkexpr(result)); + + return "sgh"; +} + +static const HChar * s390_irgen_SH(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -19693,8 +19859,12 @@ s390_decode_4byte_and_irgen(const UChar *bytes) case 0xb9eb: s390_format_RRF_R0RR2(s390_irgen_SLGRK, RRF4_r3(ovl), RRF4_r1(ovl), RRF4_r2(ovl)); goto ok; - case 0xb9ec: /* MGRK */ goto unimplemented; - case 0xb9ed: /* MSGRKC */ goto unimplemented; + case 0xb9ec: s390_format_RRF_R0RR2(s390_irgen_MGRK, RRF4_r3(ovl), + RRF4_r1(ovl), RRF4_r2(ovl)); + goto ok; + case 0xb9ed: s390_format_RRF_R0RR2(s390_irgen_MSGRKC, RRF4_r3(ovl), + RRF4_r1(ovl), RRF4_r2(ovl)); + goto ok; case 0xb9f2: s390_format_RRF_U0RR(s390_irgen_LOCR, RRF3_r3(ovl), RRF3_r1(ovl), RRF3_r2(ovl), S390_XMNM_LOCR); goto ok; @@ -19719,7 +19889,9 @@ s390_decode_4byte_and_irgen(const UChar *bytes) case 0xb9fb: s390_format_RRF_R0RR2(s390_irgen_SLRK, RRF4_r3(ovl), RRF4_r1(ovl), RRF4_r2(ovl)); goto ok; - case 0xb9fd: /* MSRKC */ goto unimplemented; + case 0xb9fd: s390_format_RRF_R0RR2(s390_irgen_MSRKC, RRF4_r3(ovl), + RRF4_r1(ovl), RRF4_r2(ovl)); + goto ok; } switch ((ovl & 0xff000000) >> 24) { @@ -20036,8 +20208,14 @@ s390_decode_6byte_and_irgen(const UChar *bytes) RXY_x2(ovl), RXY_b2(ovl), RXY_dl2(ovl), RXY_dh2(ovl)); goto ok; - case 0xe30000000038ULL: /* AGH */ goto unimplemented; - case 0xe30000000039ULL: /* SGH */ goto unimplemented; + case 0xe30000000038ULL: s390_format_RXY_RRRD(s390_irgen_AGH, RXY_r1(ovl), + RXY_x2(ovl), RXY_b2(ovl), + RXY_dl2(ovl), + RXY_dh2(ovl)); goto ok; + case 0xe30000000039ULL: s390_format_RXY_RRRD(s390_irgen_SGH, RXY_r1(ovl), + RXY_x2(ovl), RXY_b2(ovl), + RXY_dl2(ovl), + RXY_dh2(ovl)); goto ok; case 0xe3000000003aULL: s390_format_RXY_RRRD(s390_irgen_LLZRGF, RXY_r1(ovl), RXY_x2(ovl), RXY_b2(ovl), RXY_dl2(ovl), @@ -20046,7 +20224,10 @@ s390_decode_6byte_and_irgen(const UChar *bytes) RXY_x2(ovl), RXY_b2(ovl), RXY_dl2(ovl), RXY_dh2(ovl)); goto ok; - case 0xe3000000003cULL: /* MGH */ goto unimplemented; + case 0xe3000000003cULL: s390_format_RXY_RRRD(s390_irgen_MGH, RXY_r1(ovl), + RXY_x2(ovl), RXY_b2(ovl), + RXY_dl2(ovl), + RXY_dh2(ovl)); goto ok; case 0xe3000000003eULL: s390_format_RXY_RRRD(s390_irgen_STRV, RXY_r1(ovl), RXY_x2(ovl), RXY_b2(ovl), RXY_dl2(ovl), @@ -20059,7 +20240,10 @@ s390_decode_6byte_and_irgen(const UChar *bytes) RXY_x2(ovl), RXY_b2(ovl), RXY_dl2(ovl), RXY_dh2(ovl)); goto ok; - case 0xe30000000047ULL: /* BIC */ goto unimplemented; + case 0xe30000000047ULL: s390_format_RXY_RRRD(s390_irgen_BIC, RXY_r1(ovl), + RXY_x2(ovl), RXY_b2(ovl), + RXY_dl2(ovl), + RXY_dh2(ovl)); goto ok; case 0xe30000000048ULL: /* LLGFSG */ goto unimplemented; case 0xe30000000049ULL: /* STGSC */ goto unimplemented; case 0xe3000000004cULL: /* LGG */ goto unimplemented; @@ -20072,7 +20256,10 @@ s390_decode_6byte_and_irgen(const UChar *bytes) RXY_x2(ovl), RXY_b2(ovl), RXY_dl2(ovl), RXY_dh2(ovl)); goto ok; - case 0xe30000000053ULL: /* MSC */ goto unimplemented; + case 0xe30000000053ULL: s390_format_RXY_RRRD(s390_irgen_MSC, RXY_r1(ovl), + RXY_x2(ovl), RXY_b2(ovl), + RXY_dl2(ovl), + RXY_dh2(ovl)); goto ok; case 0xe30000000054ULL: s390_format_RXY_RRRD(s390_irgen_NY, RXY_r1(ovl), RXY_x2(ovl), RXY_b2(ovl), RXY_dl2(ovl), @@ -20177,8 +20364,14 @@ s390_decode_6byte_and_irgen(const UChar *bytes) RXY_x2(ovl), RXY_b2(ovl), RXY_dl2(ovl), RXY_dh2(ovl)); goto ok; - case 0xe30000000083ULL: /* MSGC */ goto unimplemented; - case 0xe30000000084ULL: /* MG */ goto unimplemented; + case 0xe30000000083ULL: s390_format_RXY_RRRD(s390_irgen_MSGC, RXY_r1(ovl), + RXY_x2(ovl), RXY_b2(ovl), + RXY_dl2(ovl), + RXY_dh2(ovl)); goto ok; + case 0xe30000000084ULL: s390_format_RXY_RRRD(s390_irgen_MG, RXY_r1(ovl), + RXY_x2(ovl), RXY_b2(ovl), + RXY_dl2(ovl), + RXY_dh2(ovl)); goto ok; case 0xe30000000085ULL: s390_format_RXY_RRRD(s390_irgen_LGAT, RXY_r1(ovl), RXY_x2(ovl), RXY_b2(ovl), RXY_dl2(ovl), diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index 8aa2ba6..162550f 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -3024,6 +3024,26 @@ s390_emit_MFY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * +s390_emit_MG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) +{ + if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) + s390_disasm(ENC3(MNM, GPR, SDXB), "mg", r1, dh2, dl2, x2, b2); + + return emit_RXY(p, 0xe30000000084ULL, r1, x2, b2, dl2, dh2); +} + + +static UChar * +s390_emit_MGRK(UChar *p, UChar r3, UChar r1, UChar r2) +{ + if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) + s390_disasm(ENC4(MNM, GPR, GPR, GPR), "mgrk", r1, r2, r3); + + return emit_RRF3(p, 0xb9ec0000, r3, r1, r2); +} + + +static UChar * s390_emit_MH(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) @@ -9595,7 +9615,7 @@ s390_insn_mul_emit(UChar *buf, const s390_insn *insn) case 8: if (signed_multiply) - vpanic("s390_insn_mul_emit"); + return s390_emit_MGRK(buf, r1 + 1, r1, r2); else return s390_emit_MLGR(buf, r1, r2); @@ -9640,7 +9660,7 @@ s390_insn_mul_emit(UChar *buf, const s390_insn *insn) case 8: if (signed_multiply) - vpanic("s390_insn_mul_emit"); + return s390_emit_MG(buf, r1, x, b, DISP20(d)); else return s390_emit_MLG(buf, r1, x, b, DISP20(d)); @@ -9665,7 +9685,7 @@ s390_insn_mul_emit(UChar *buf, const s390_insn *insn) case 8: buf = s390_emit_load_64imm(buf, R0, value); if (signed_multiply) - vpanic("s390_insn_mul_emit"); + return s390_emit_MGRK(buf, r1 + 1, r1, R0); else return s390_emit_MLGR(buf, r1, R0); diff --git a/VEX/priv/host_s390_isel.c b/VEX/priv/host_s390_isel.c index 9141b7b..30e5c76 100644 --- a/VEX/priv/host_s390_isel.c +++ b/VEX/priv/host_s390_isel.c @@ -1018,6 +1018,8 @@ s390_isel_int128_expr_wrk(HReg *dst_hi, HReg *dst_lo, ISelEnv *env, goto do_multiply64; case Iop_MullS64: + if (!(env->hwcaps & VEX_HWCAPS_S390X_MI2)) + goto irreducible; is_signed_multiply = True; goto do_multiply64; @@ -1125,7 +1127,10 @@ s390_isel_int128_expr_wrk(HReg *dst_hi, HReg *dst_lo, ISelEnv *env, } } - vpanic("s390_isel_int128_expr"); + /* We get here if no pattern matched. */ + irreducible: + ppIRExpr(expr); + vpanic("s390_isel_int128_expr: cannot reduce tree"); } diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c index 97c0bac..3cfe8c1 100644 --- a/VEX/priv/main_main.c +++ b/VEX/priv/main_main.c @@ -1721,6 +1721,7 @@ static const HChar* show_hwcaps_s390x ( UInt hwcaps ) { VEX_HWCAPS_S390X_PFPO, "pfpo" }, { VEX_HWCAPS_S390X_VX, "vx" }, { VEX_HWCAPS_S390X_MSA5, "msa5" }, + { VEX_HWCAPS_S390X_MI2, "mi2" }, }; /* Allocate a large enough buffer */ static HChar buf[sizeof prefix + diff --git a/VEX/priv/s390_disasm.c b/VEX/priv/s390_disasm.c index 4d3fec5..e3fbc11 100644 --- a/VEX/priv/s390_disasm.c +++ b/VEX/priv/s390_disasm.c @@ -433,6 +433,16 @@ s390_disasm(UInt command, ...) the integer mask is appended as the final operand */ if (mask == 0 || mask == 15) mask_suffix = mask; break; + case S390_XMNM_BIC: + mask = va_arg(args, UInt); + if (mask == 0) { + /* There is no special opcode when mask == 0. */ + p += vex_sprintf(p, "bic"); + mask_suffix = mask; + } else { + p += vex_sprintf(p, "%s", construct_mnemonic("bi", "", mask)); + } + break; } } continue; diff --git a/VEX/priv/s390_disasm.h b/VEX/priv/s390_disasm.h index 8469f72..eec41f8 100644 --- a/VEX/priv/s390_disasm.h +++ b/VEX/priv/s390_disasm.h @@ -91,7 +91,8 @@ enum { S390_XMNM_LOCFHR = 13, S390_XMNM_LOCHI = 14, S390_XMNM_LOCGHI = 15, - S390_XMNM_LOCHHI = 16 + S390_XMNM_LOCHHI = 16, + S390_XMNM_BIC = 17 }; void s390_disasm(UInt command, ...); diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h index 37afd18..9337a7c 100644 --- a/VEX/pub/libvex.h +++ b/VEX/pub/libvex.h @@ -163,6 +163,7 @@ typedef #define VEX_HWCAPS_S390X_PFPO (1<<17) /* Perform floating point ops facility */ #define VEX_HWCAPS_S390X_VX (1<<18) /* Vector facility */ #define VEX_HWCAPS_S390X_MSA5 (1<<19) /* message security assistance facility */ +#define VEX_HWCAPS_S390X_MI2 (1<<20) /* miscellaneous-instruction-extensions facility 2 */ /* Special value representing all available s390x hwcaps */ @@ -179,7 +180,8 @@ typedef VEX_HWCAPS_S390X_ETF2 | \ VEX_HWCAPS_S390X_PFPO | \ VEX_HWCAPS_S390X_VX | \ - VEX_HWCAPS_S390X_MSA5) + VEX_HWCAPS_S390X_MSA5 | \ + VEX_HWCAPS_S390X_MI2) #define VEX_HWCAPS_S390X(x) ((x) & ~VEX_S390X_MODEL_MASK) #define VEX_S390X_MODEL(x) ((x) & VEX_S390X_MODEL_MASK) diff --git a/VEX/pub/libvex_s390x_common.h b/VEX/pub/libvex_s390x_common.h index c976395..d945a44 100644 --- a/VEX/pub/libvex_s390x_common.h +++ b/VEX/pub/libvex_s390x_common.h @@ -99,6 +99,7 @@ #define S390_FAC_CTREXE 50 // constrained transactional execution #define S390_FAC_LSC2 53 // load/store on condition 2 and load and zero rightmost byte #define S390_FAC_MSA5 57 // message-security-assist 5 +#define S390_FAC_MI2 58 // miscellaneous-instruction-extensions 2 #define S390_FAC_TREXE 73 // transactional execution #define S390_FAC_MSA4 77 // message-security-assist 4 #define S390_FAC_VX 129 // vector facility diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c index cbb8847..9eab900 100644 --- a/coregrind/m_machine.c +++ b/coregrind/m_machine.c @@ -1534,7 +1534,8 @@ Bool VG_(machine_get_hwcaps)( void ) { False, S390_FAC_LSC, VEX_HWCAPS_S390X_LSC, "LSC" }, { False, S390_FAC_PFPO, VEX_HWCAPS_S390X_PFPO, "PFPO" }, { False, S390_FAC_VX, VEX_HWCAPS_S390X_VX, "VX" }, - { False, S390_FAC_MSA5, VEX_HWCAPS_S390X_MSA5, "MSA5" } + { False, S390_FAC_MSA5, VEX_HWCAPS_S390X_MSA5, "MSA5" }, + { False, S390_FAC_MI2, VEX_HWCAPS_S390X_MI2, "MI2" }, }; /* Set hwcaps according to the detected facilities */ diff --git a/docs/internals/s390-opcodes.csv b/docs/internals/s390-opcodes.csv index 4281f24..67d7549 100644 --- a/docs/internals/s390-opcodes.csv +++ b/docs/internals/s390-opcodes.csv @@ -1633,17 +1633,17 @@ wfsxb,"scalar vector fp subtract scalar extended","not implemented","arch12" vftcisb,"vector fp test data class immediate short","not implemented","arch12" wftcisb,"scalar vector fp test data class immediate scalar short","not implemented","arch12" wftcixb,"scalar vector fp test data class immediate scalar extended","not implemented","arch12" -agh,"add halfword to 64 bit value","not implemented","arch12" -bic,"branch indirect on condition","not implemented","arch12" -bi,"unconditional indirect branch","not implemented","arch12" -mgrk,"multiply 64x64reg -> 128","not implemented","arch12" -mg,"multiply 64x64mem -> 128","not implemented","arch12" -mgh,"multiply halfword 64x16mem -> 64","not implemented","arch12" -msrkc,"multiply single 32x32 -> 32","not implemented","arch12" -msgrkc,"multiply single 64x64 -> 64","not implemented","arch12" -msc,"multiply single 32x32mem -> 32","not implemented","arch12" -msgc,"multiply single 64x64mem -> 64","not implemented","arch12" -sgh,"subtract halfword from 64 bit value","not implemented","arch12" +agh,"add halfword to 64 bit value",implemented,"arch12" +bic,"branch indirect on condition",implemented,"arch12" +bi,"unconditional indirect branch",implemented,"arch12" +mgrk,"multiply 64x64reg -> 128",implemented,"arch12" +mg,"multiply 64x64mem -> 128",implemented,"arch12" +mgh,"multiply halfword 64x16mem -> 64",implemented,"arch12" +msrkc,"multiply single 32x32 -> 32",implemented,"arch12" +msgrkc,"multiply single 64x64 -> 64",implemented,"arch12" +msc,"multiply single 32x32mem -> 32",implemented,"arch12" +msgc,"multiply single 64x64mem -> 64",implemented,"arch12" +sgh,"subtract halfword from 64 bit value",implemented,"arch12" vlrlr,"vector load rightmost with length","not implemented","arch12" vlrl,"vector load rightmost with immediate length","not implemented","arch12" vstrlr,"vector store rightmost with length","not implemented","arch12" |
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From: Andreas A. <ar...@so...> - 2019-06-12 18:24:05
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e63f93a970b8eb83d83dfb8bb39d578229fa3496 commit e63f93a970b8eb83d83dfb8bb39d578229fa3496 Author: Andreas Arnez <ar...@li...> Date: Tue May 14 17:19:34 2019 +0200 s390x: Clean up s390-check-opcodes.pl Fix false positives when invoking s390-check-opcodes.pl. Also clean up some code formatting issues in that script. Add the instructions TPEI and IRBM to guest_s390_toIR.c and s390-opcodes.csv, so they are not longer warned about. Diff: --- VEX/priv/guest_s390_toIR.c | 2 + auxprogs/s390-check-opcodes.pl | 101 +++++++++++++++++++++------------------- docs/internals/s390-opcodes.csv | 2 + 3 files changed, 57 insertions(+), 48 deletions(-) diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index 515b6db..076a421 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -19613,8 +19613,10 @@ s390_decode_4byte_and_irgen(const UChar *bytes) case 0xb99d: /* ESEA */ goto unimplemented; case 0xb99e: /* PTI */ goto unimplemented; case 0xb99f: /* SSAIR */ goto unimplemented; + case 0xb9a1: /* TPEI */ goto unimplemented; case 0xb9a2: /* PTF */ goto unimplemented; case 0xb9aa: /* LPTEA */ goto unimplemented; + case 0xb9ac: /* IRBM */ goto unimplemented; case 0xb9ae: /* RRBM */ goto unimplemented; case 0xb9af: /* PFMF */ goto unimplemented; case 0xb9b0: s390_format_RRF_M0RERE(s390_irgen_CU14, RRF3_r3(ovl), diff --git a/auxprogs/s390-check-opcodes.pl b/auxprogs/s390-check-opcodes.pl index c02e157..3f0ac1e 100755 --- a/auxprogs/s390-check-opcodes.pl +++ b/auxprogs/s390-check-opcodes.pl @@ -27,12 +27,14 @@ my %csv_desc = (); my %csv_implemented = (); my %toir_implemented = (); my %toir_decoded = (); +my %known_arch = map {($_ => 1)} + qw(g5 z900 z990 z9-109 z9-ec z10 z196 zEC12 z13 arch12); + +# Patterns for identifying certain extended mnemonics that shall be +# skipped in "s390-opc.txt" and "s390-opcodes.csv". -# "General" form of all theese vector mnemonics is handled. -# e.g. "vab %%v1, %%v2, %%v3" is equal to "va %%v1, %%v2, %%v3, 0" -# We exclude this "submnemonics" from handling and work with the "general" ones. my @extended_mnemonics = ( - "bi", # extended mnemonics for bic + "bi", # extended mnemonic for bic "va[bhfgq]", "vacc[bhfgq]", "vacccq", @@ -124,15 +126,15 @@ my @extended_mnemonics = ( "wfpso[sdx]b", "wftci[sdx]b", "wfsq*[sdx]b", - "vfl[lr]" + "vfl[lr]", + "prno" # alternate mnemonic for ppno ); -# Compile excluded mnemonics into one regular expession to optimize speed. -# Also it simplifies the code. -my $extended_mnemonics_pattern = join '|', map "$_", @extended_mnemonics; -$extended_mnemonics_pattern = "($extended_mnemonics_pattern)"; -# print "extended_mnemonics_pattern: $extended_mnemonics_pattern\n"; +# Compile excluded mnemonics into one regular expression to optimize +# speed. Also it simplifies the code. +my $extended_mnemonics_pattern = '^(' . + join('|', map "$_", @extended_mnemonics) . ')$'; #---------------------------------------------------- # Read s390-opc.txt (binutils) @@ -142,8 +144,7 @@ while (my $line = <OPC>) { chomp $line; next if ($line =~ "^[ ]*#"); # comments next if ($line =~ /^\s*$/); # blank line - my $description = (split /"/,$line)[1]; - my ($encoding,$mnemonic,$format) = split /\s+/,$line; + my ($encoding,$mnemonic,$format) = $line =~ /^(\S+) (\S+) (\S+)/gc; # Ignore opcodes that have wildcards in them ('$', '*') # Those provide alternate mnemonics for specific instances of this opcode @@ -198,25 +199,33 @@ while (my $line = <OPC>) { next if ($mnemonic eq "mxtr"); # indistinguishable from mxtra next if ($mnemonic =~ /$extended_mnemonics_pattern/); - $description =~ s/^[\s]+//g; # remove leading blanks - $description =~ s/[\s]+$//g; # remove trailing blanks - $description =~ s/[ ][ ]+/ /g; # replace multiple blanks with a single one + my ($description) = $line =~ /\G\s+"\s*(.*?)\s*"/gc; + my ($arch) = $line =~ /\G\s+(\S+)/gc; + unless ($known_arch{$arch}) { + unless (exists $known_arch{$arch}) { + print "warning: unsupported arch \"$arch\" in s390-opc.txt\n"; + $known_arch{$arch} = 0; + } + next; + } + $description =~ s/\s\s+/ /g; # replace multiple blanks with a single one -# Certain opcodes are listed more than once. Let the first description win - if ($opc_desc{$mnemonic}) { - # already there + # Certain opcodes are listed more than once. Let the first description + # win. + if (exists $opc_desc{$mnemonic}) { + # already there # if ($opc_desc{$mnemonic} ne $description) { # print "multiple description for opcode $mnemonic\n"; # print " old: |" . $opc_desc{$mnemonic} . "|\n"; # print " new: |" . $description . "|\n"; # } } else { - $opc_desc{$mnemonic} = $description; + $opc_desc{$mnemonic} = $description; } if ($description =~ /,/) { - print "warning: description of $mnemonic contains comma\n"; + print "warning: description of $mnemonic contains comma\n"; } } close(OPC); @@ -262,20 +271,20 @@ while (my $line = <CSV>) { next if ($mnemonic eq "mdtr"); # indistinguishable from mdtra next if ($mnemonic =~ /$extended_mnemonics_pattern/); -# Complain about duplicate entries. We don't want them. + # Complain about duplicate entries. We don't want them. if ($csv_desc{$mnemonic}) { - print "$mnemonic: duplicate entry\n"; + print "$mnemonic: duplicate entry\n"; } else { - $csv_desc{$mnemonic} = $description; + $csv_desc{$mnemonic} = $description; } -# Remember whether it is implemented or not + # Remember whether it is implemented or not next if ($line =~ /not\s+implemented/); next if ($line =~ /N\/A/); next if ($line =~ /won't do/); if ($line =~ /implemented/) { - $csv_implemented{$mnemonic} = 1; + $csv_implemented{$mnemonic} = 1; } else { - print "*** unknown implementation status of $mnemonic\n"; + print "*** unknown implementation status of $mnemonic\n"; } } close(CSV); @@ -287,19 +296,15 @@ open(TOIR, "$toir_file") || die "cannot open $toir_file\n"; while (my $line = <TOIR>) { chomp $line; if ($line =~ /goto\s+unimplemented/) { - # Assume this is in the decoder - if ($line =~ /\/\*\s([A-Z][A-Z0-9]+)\s\*\//) { - my $mnemonic = $1; - $mnemonic =~ tr/A-Z/a-z/; - $toir_decoded{$mnemonic} = 1; -# print "DECODED: $mnemonic\n"; - } + # Assume this is in the decoder + if ($line =~ /\/\*\s([A-Z][A-Z0-9]*)\s\*\//) { + my $mnemonic = lc $1; + $toir_decoded{$mnemonic} = 1; + } + } elsif ($line =~ /^s390_irgen_([A-Z][A-Z0-9]*)\b/) { + my $mnemonic = lc $1; + $toir_implemented{$mnemonic} = 1; } - next if (! ($line =~ /^s390_irgen_[A-Z]/)); - $line =~ /^s390_irgen_([A-Z][A-Z0-9]*)/; - my $op = $1; - $op =~ tr/A-Z/a-z/; - $toir_implemented{$op} = 1; } close(TOIR); @@ -308,12 +313,12 @@ close(TOIR); #---------------------------------------------------- foreach my $opc (keys %opc_desc) { if (! $csv_desc{$opc}) { - print "*** opcode $opc not listed in $csv_file\n"; + print "*** opcode $opc not listed in $csv_file\n"; } } foreach my $opc (keys %csv_desc) { if (! $opc_desc{$opc}) { - print "*** opcode $opc not listed in $opc_file\n"; + print "*** opcode $opc not listed in $opc_file\n"; } } @@ -322,11 +327,11 @@ foreach my $opc (keys %csv_desc) { #---------------------------------------------------- foreach my $opc (keys %opc_desc) { if (defined $csv_desc{$opc}) { - if ($opc_desc{$opc} ne $csv_desc{$opc}) { - print "*** opcode $opc differs:\n"; - print " binutils: $opc_desc{$opc}\n"; - print " opcodes.csv: $csv_desc{$opc}\n"; - } + if ($opc_desc{$opc} ne $csv_desc{$opc}) { + print "*** opcode $opc differs:\n"; + print " binutils: $opc_desc{$opc}\n"; + print " opcodes.csv: $csv_desc{$opc}\n"; + } } } @@ -335,13 +340,13 @@ foreach my $opc (keys %opc_desc) { #---------------------------------------------------- foreach my $opc (keys %toir_implemented) { if (! $csv_implemented{$opc}) { - print "*** opcode $opc is implemented but CSV file does not say so\n"; + print "*** opcode $opc is implemented but CSV file does not say so\n"; } } foreach my $opc (keys %csv_implemented) { if (! $toir_implemented{$opc}) { - print "*** opcode $opc is not implemented but CSV file says so\n"; + print "*** opcode $opc is not implemented but CSV file says so\n"; } } @@ -353,7 +358,7 @@ foreach my $opc (keys %csv_implemented) { foreach my $opc (keys %opc_desc) { if (! $toir_implemented{$opc} && ! $toir_decoded{$opc}) { - print "*** opcode $opc is not handled by the decoder\n"; + print "*** opcode $opc is not handled by the decoder\n"; } } diff --git a/docs/internals/s390-opcodes.csv b/docs/internals/s390-opcodes.csv index d7056ff..4281f24 100644 --- a/docs/internals/s390-opcodes.csv +++ b/docs/internals/s390-opcodes.csv @@ -1344,6 +1344,8 @@ verllvh,"vector element rotate left logical reg halfword",implemented,z13 cpdt,"convert from long dfp to packed","not implemented",z13 vrepb,"vector replicate byte","implemented",z13 ppno,"perform pseudorandom number operation",implemented,z13 +irbm,"insert reference bits multiple",N/A,"privileged instruction",arch12 +tpei,"test pending external interruption",N/A,"privileged instruction",arch12 vfeef,"vector find element equal word","implemented",z13 vac,"vector add with carry",implemented,z13 verimf,"vector element rotate and insert under mask word",implemented,z13 |
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From: Andreas A. <ar...@so...> - 2019-06-12 18:24:01
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=65d8e9ed96287235b33dfe40525a442dc978e3af commit 65d8e9ed96287235b33dfe40525a442dc978e3af Author: Andreas Arnez <ar...@li...> Date: Tue Oct 2 13:47:50 2018 +0200 s390x: Add models "z14" and "z14 ZR1" Add IBM z14 and IBM z14 ZR1 to the list of known machine models. Add an expected output variant for z14 to the s390x-specific "ecag" test case. In README.s390, refer to a current version of the z/Architecture Principles of Operation that describes the instructions introduced with IBM z14. Diff: --- README.s390 | 5 ++--- VEX/priv/main_main.c | 2 ++ VEX/pub/libvex.h | 4 +++- coregrind/m_machine.c | 2 ++ none/tests/s390x/ecag.stdout.exp-z14 | 28 ++++++++++++++++++++++++++++ tests/s390x_features.c | 2 ++ 6 files changed, 39 insertions(+), 4 deletions(-) diff --git a/README.s390 b/README.s390 index 4679bb3..ac9485a 100644 --- a/README.s390 +++ b/README.s390 @@ -12,7 +12,6 @@ Limitations - 31-bit client programs are not supported. - Hexadecimal floating point is not supported. - Transactional memory is not supported. -- Instructions operating on vector registers are not supported. - memcheck, cachegrind, drd, helgrind, massif, lackey, and none are supported. - On machine models predating z10, cachegrind will assume a z10 cache @@ -49,6 +48,6 @@ Reading Material (1) Linux for zSeries ELF ABI Supplement http://refspecs.linuxfoundation.org/ELF/zSeries/index.html (2) z/Architecture Principles of Operation - http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr010.pdf + http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr011.pdf (3) z/Architecture Reference Summary - http://publibfi.boulder.ibm.com/epubs/pdf/dz9zs008.pdf + http://publibfi.boulder.ibm.com/epubs/pdf/dz9zs009.pdf diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c index ac3006d..97c0bac 100644 --- a/VEX/priv/main_main.c +++ b/VEX/priv/main_main.c @@ -1719,6 +1719,8 @@ static const HChar* show_hwcaps_s390x ( UInt hwcaps ) { VEX_HWCAPS_S390X_FPEXT, "fpext" }, { VEX_HWCAPS_S390X_LSC, "lsc" }, { VEX_HWCAPS_S390X_PFPO, "pfpo" }, + { VEX_HWCAPS_S390X_VX, "vx" }, + { VEX_HWCAPS_S390X_MSA5, "msa5" }, }; /* Allocate a large enough buffer */ static HChar buf[sizeof prefix + diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h index 1e112f5..37afd18 100644 --- a/VEX/pub/libvex.h +++ b/VEX/pub/libvex.h @@ -144,7 +144,9 @@ typedef #define VEX_S390X_MODEL_ZBC12 11 #define VEX_S390X_MODEL_Z13 12 #define VEX_S390X_MODEL_Z13S 13 -#define VEX_S390X_MODEL_UNKNOWN 14 /* always last in list */ +#define VEX_S390X_MODEL_Z14 14 +#define VEX_S390X_MODEL_Z14_ZR1 15 +#define VEX_S390X_MODEL_UNKNOWN 16 /* always last in list */ #define VEX_S390X_MODEL_MASK 0x3F #define VEX_HWCAPS_S390X_LDISP (1<<6) /* Long-displacement facility */ diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c index 56a28d1..cbb8847 100644 --- a/coregrind/m_machine.c +++ b/coregrind/m_machine.c @@ -578,6 +578,8 @@ static UInt VG_(get_machine_model)(void) { "2828", VEX_S390X_MODEL_ZBC12 }, { "2964", VEX_S390X_MODEL_Z13 }, { "2965", VEX_S390X_MODEL_Z13S }, + { "3906", VEX_S390X_MODEL_Z14 }, + { "3907", VEX_S390X_MODEL_Z14_ZR1 }, }; Int model, n, fh; diff --git a/none/tests/s390x/ecag.stdout.exp-z14 b/none/tests/s390x/ecag.stdout.exp-z14 new file mode 100644 index 0000000..98f5328 --- /dev/null +++ b/none/tests/s390x/ecag.stdout.exp-z14 @@ -0,0 +1,28 @@ +L1 topology: separate data and instruction; private +L1 cache line size data: 256 +L1 cache line size insn: 256 +L1 total cachesize data: 131072 +L1 total cachesize insn: 131072 +L1 set. assoc. data: 8 +L1 set. assoc. insn: 8 +L2 topology: separate data and instruction; private +L2 cache line size data: 256 +L2 cache line size insn: 256 +L2 total cachesize data: 4194304 +L2 total cachesize insn: 2097152 +L2 set. assoc. data: 8 +L2 set. assoc. insn: 8 +L3 topology: unified data and instruction; shared +L3 cache line size data: 256 +L3 cache line size insn: 256 +L3 total cachesize data: 134217728 +L3 total cachesize insn: 134217728 +L3 set. assoc. data: 32 +L3 set. assoc. insn: 32 +L4 topology: unified data and instruction; shared +L4 cache line size data: 256 +L4 cache line size insn: 256 +L4 total cachesize data: 704643072 +L4 total cachesize insn: 704643072 +L4 set. assoc. data: 42 +L4 set. assoc. insn: 42 diff --git a/tests/s390x_features.c b/tests/s390x_features.c index 25734ab..301785f 100644 --- a/tests/s390x_features.c +++ b/tests/s390x_features.c @@ -98,6 +98,8 @@ model_info models[] = { { "2828", "zBC12" }, { "2964", "z13" }, { "2965", "z13s" }, + { "3906", "z14" }, + { "3907", "z14 ZR1"}, }; |