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From: Mark W. <ma...@so...> - 2019-05-28 20:11:09
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=791fe5ecf909d573bcbf353b677b9404f9da0ed4 commit 791fe5ecf909d573bcbf353b677b9404f9da0ed4 Author: Mark Wielaard <ma...@kl...> Date: Mon May 27 22:19:27 2019 +0200 Expose rdrand and f16c through cpuid also if the host only has avx. The amd64 CPUID dirtyhelpers are mostly static since they emulate some existing CPU "family". The avx2 ("i7-4910MQ") CPUID variant however can "dynamicly" enable rdrand and/or f16c if the host supports them. Do the same for the avx_and_cx16 ("i5-2300") CPUID variant. https://bugs.kde.org/show_bug.cgi?id=408009 Diff: --- NEWS | 1 + VEX/priv/guest_amd64_defs.h | 4 +++- VEX/priv/guest_amd64_helpers.c | 14 +++++++++++--- VEX/priv/guest_amd64_toIR.c | 3 ++- coregrind/m_machine.c | 8 ++++---- 5 files changed, 21 insertions(+), 9 deletions(-) diff --git a/NEWS b/NEWS index 753171f..004e677 100644 --- a/NEWS +++ b/NEWS @@ -52,6 +52,7 @@ where XXXXXX is the bug number as listed below. 407218 Add support for the copy_file_range syscall 407307 Intercept stpcpy also in ld.so for arm64 407764 drd cond_post_wait gets wrong (?) condition on s390x z13 system +408009 Expose rdrand and f16c even on avx if host cpu supports them n-i-bz Fix minor one time leaks in dhat. n-i-bz Add --run-cxx-freeres=no in outer args to avoid inner crashes. diff --git a/VEX/priv/guest_amd64_defs.h b/VEX/priv/guest_amd64_defs.h index 4f34b41..a5de527 100644 --- a/VEX/priv/guest_amd64_defs.h +++ b/VEX/priv/guest_amd64_defs.h @@ -165,7 +165,9 @@ extern void amd64g_dirtyhelper_storeF80le ( Addr/*addr*/, ULong/*data*/ ); extern void amd64g_dirtyhelper_CPUID_baseline ( VexGuestAMD64State* st ); extern void amd64g_dirtyhelper_CPUID_sse3_and_cx16 ( VexGuestAMD64State* st ); extern void amd64g_dirtyhelper_CPUID_sse42_and_cx16 ( VexGuestAMD64State* st ); -extern void amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st ); +extern void amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st, + ULong hasF16C, + ULong hasRDRAND ); extern void amd64g_dirtyhelper_CPUID_avx2 ( VexGuestAMD64State* st, ULong hasF16C, ULong hasRDRAND ); diff --git a/VEX/priv/guest_amd64_helpers.c b/VEX/priv/guest_amd64_helpers.c index e4cf7e2..182bae0 100644 --- a/VEX/priv/guest_amd64_helpers.c +++ b/VEX/priv/guest_amd64_helpers.c @@ -3141,8 +3141,11 @@ void amd64g_dirtyhelper_CPUID_sse42_and_cx16 ( VexGuestAMD64State* st ) address sizes : 36 bits physical, 48 bits virtual power management: */ -void amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st ) +void amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st, + ULong hasF16C, ULong hasRDRAND ) { + vassert((hasF16C >> 1) == 0ULL); + vassert((hasRDRAND >> 1) == 0ULL); # define SET_ABCD(_a,_b,_c,_d) \ do { st->guest_RAX = (ULong)(_a); \ st->guest_RBX = (ULong)(_b); \ @@ -3157,9 +3160,14 @@ void amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st ) case 0x00000000: SET_ABCD(0x0000000d, 0x756e6547, 0x6c65746e, 0x49656e69); break; - case 0x00000001: - SET_ABCD(0x000206a7, 0x00100800, 0x1f9ae3bf, 0xbfebfbff); + case 0x00000001: { + // As a baseline, advertise neither F16C (ecx:29) nor RDRAND (ecx:30), + // but patch in support for them as directed by the caller. + UInt ecx_extra + = (hasF16C ? (1U << 29) : 0) | (hasRDRAND ? (1U << 30) : 0); + SET_ABCD(0x000206a7, 0x00100800, (0x1f9ae3bf | ecx_extra), 0xbfebfbff); break; + } case 0x00000002: SET_ABCD(0x76035a01, 0x00f0b0ff, 0x00000000, 0x00ca0000); break; diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c index 56e992c..96dee38 100644 --- a/VEX/priv/guest_amd64_toIR.c +++ b/VEX/priv/guest_amd64_toIR.c @@ -22007,7 +22007,8 @@ Long dis_ESC_0F ( vassert(fName); vassert(fAddr); IRExpr** args = NULL; - if (fAddr == &amd64g_dirtyhelper_CPUID_avx2) { + if (fAddr == &amd64g_dirtyhelper_CPUID_avx2 + || fAddr == &amd64g_dirtyhelper_CPUID_avx_and_cx16) { Bool hasF16C = (archinfo->hwcaps & VEX_HWCAPS_AMD64_F16C) != 0; Bool hasRDRAND = (archinfo->hwcaps & VEX_HWCAPS_AMD64_RDRAND) != 0; args = mkIRExprVec_3(IRExpr_GSPTR(), diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c index 3536e57..56a28d1 100644 --- a/coregrind/m_machine.c +++ b/coregrind/m_machine.c @@ -1076,10 +1076,10 @@ Bool VG_(machine_get_hwcaps)( void ) have_avx2 = (ebx & (1<<5)) != 0; /* True => have AVX2 */ } - /* Sanity check for RDRAND and F16C. These don't actually *need* AVX2, but - it's convenient to restrict them to the AVX2 case since the simulated - CPUID we'll offer them on has AVX2 as a base. */ - if (!have_avx2) { + /* Sanity check for RDRAND and F16C. These don't actually *need* AVX, but + it's convenient to restrict them to the AVX case since the simulated + CPUID we'll offer them on has AVX as a base. */ + if (!have_avx) { have_f16c = False; have_rdrand = False; } |
|
From: Carl L. <ca...@so...> - 2019-05-28 19:46:05
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=31b3a755a93daaacbb993ffd80fb0780cc76464d commit 31b3a755a93daaacbb993ffd80fb0780cc76464d Author: Carl Love <ca...@us...> Date: Tue May 28 14:03:59 2019 -0500 PPC64, Update testcases for vlogefp, vexptefp instructions https://bugs.kde.org/show_bug.cgi?id=407340 Diff: --- none/tests/ppc32/jm-insns.c | 6 ++-- none/tests/ppc32/jm-vmx.stdout.exp | 52 ++++++++++++++++++++++++++- none/tests/ppc64/jm-vmx.stdout.exp | 52 ++++++++++++++++++++++++++- none/tests/ppc64/jm-vmx.stdout.exp-LE | 52 ++++++++++++++++++++++++++- none/tests/ppc64/subnormal_test.c | 18 +++++----- none/tests/ppc64/subnormal_test.stdout.exp | 56 ++++++++++++++++++++++++++++++ 6 files changed, 220 insertions(+), 16 deletions(-) diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c index e6e947c..5316ce3 100644 --- a/none/tests/ppc32/jm-insns.c +++ b/none/tests/ppc32/jm-insns.c @@ -3256,7 +3256,6 @@ static void test_vrsqrtefp (void) __asm__ __volatile__ ("vrsqrtefp 17, 14"); } -#if 0 // TODO: Not yet supported static void test_vlogefp (void) { __asm__ __volatile__ ("vlogefp 17, 14"); @@ -3266,7 +3265,6 @@ static void test_vexptefp (void) { __asm__ __volatile__ ("vexptefp 17, 14"); } -#endif static test_t tests_afa_ops_one[] = { { &test_vrfin , " vrfin", }, @@ -3275,8 +3273,8 @@ static test_t tests_afa_ops_one[] = { { &test_vrfim , " vrfim", }, { &test_vrefp , " vrefp", }, { &test_vrsqrtefp , " vrsqrtefp", }, - // { &test_vlogefp , " vlogefp", }, // TODO: Not yet supported - // { &test_vexptefp , " vexptefp", }, // TODO: Not yet supported + { &test_vlogefp , " vlogefp", }, + { &test_vexptefp , " vexptefp", }, { NULL, NULL, }, }; #endif /* defined (HAS_ALTIVEC) */ diff --git a/none/tests/ppc32/jm-vmx.stdout.exp b/none/tests/ppc32/jm-vmx.stdout.exp index 307c75f..35ac34d 100644 --- a/none/tests/ppc32/jm-vmx.stdout.exp +++ b/none/tests/ppc32/jm-vmx.stdout.exp @@ -2636,6 +2636,56 @@ Altivec floating point arith insns with one arg: vrsqrtefp: ffbfffff ffbfffff ffbfffff ffbfffff vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000) + vlogefp: 02bfffff 02bfffff 02bfffff 02bfffff + vlogefp: => c2f2d440 c2f2d440 c2f2d440 c2f2d440 (00000000) + vlogefp: 513fffff 513fffff 513fffff 513fffff + vlogefp: => 420e5780 420e5780 420e5780 420e5780 (00000000) + vlogefp: 82bfffff 82bfffff 82bfffff 82bfffff + vlogefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) + vlogefp: d13fffff d13fffff d13fffff d13fffff + vlogefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) + vlogefp: 00000000 00000000 00000000 00000000 + vlogefp: => ff800000 ff800000 ff800000 ff800000 (00000000) + vlogefp: 80000000 80000000 80000000 80000000 + vlogefp: => ff800000 ff800000 ff800000 ff800000 (00000000) + vlogefp: 7f800000 7f800000 7f800000 7f800000 + vlogefp: => 7f800000 7f800000 7f800000 7f800000 (00000000) + vlogefp: ff800000 ff800000 ff800000 ff800000 + vlogefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) + vlogefp: 7fffffff 7fffffff 7fffffff 7fffffff + vlogefp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vlogefp: ffffffff ffffffff ffffffff ffffffff + vlogefp: => ffffffff ffffffff ffffffff ffffffff (00000000) + vlogefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff + vlogefp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vlogefp: ffbfffff ffbfffff ffbfffff ffbfffff + vlogefp: => ffffffff ffffffff ffffffff ffffffff (00000000) + + vexptefp: 02bfffff 02bfffff 02bfffff 02bfffff + vexptefp: => 3f800000 3f800000 3f800000 3f800000 (00000000) + vexptefp: 513fffff 513fffff 513fffff 513fffff + vexptefp: => 7f800000 7f800000 7f800000 7f800000 (00000000) + vexptefp: 82bfffff 82bfffff 82bfffff 82bfffff + vexptefp: => 3f800000 3f800000 3f800000 3f800000 (00000000) + vexptefp: d13fffff d13fffff d13fffff d13fffff + vexptefp: => 00000000 00000000 00000000 00000000 (00000000) + vexptefp: 00000000 00000000 00000000 00000000 + vexptefp: => 3f800000 3f800000 3f800000 3f800000 (00000000) + vexptefp: 80000000 80000000 80000000 80000000 + vexptefp: => 3f800000 3f800000 3f800000 3f800000 (00000000) + vexptefp: 7f800000 7f800000 7f800000 7f800000 + vexptefp: => 7f800000 7f800000 7f800000 7f800000 (00000000) + vexptefp: ff800000 ff800000 ff800000 ff800000 + vexptefp: => 00000000 00000000 00000000 00000000 (00000000) + vexptefp: 7fffffff 7fffffff 7fffffff 7fffffff + vexptefp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vexptefp: ffffffff ffffffff ffffffff ffffffff + vexptefp: => ffffffff ffffffff ffffffff ffffffff (00000000) + vexptefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff + vexptefp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vexptefp: ffbfffff ffbfffff ffbfffff ffbfffff + vexptefp: => ffffffff ffffffff ffffffff ffffffff (00000000) + Altivec floating point compare insns: vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) @@ -3611,4 +3661,4 @@ Altivec float special insns: vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) -All done. Tested 165 different instructions +All done. Tested 167 different instructions diff --git a/none/tests/ppc64/jm-vmx.stdout.exp b/none/tests/ppc64/jm-vmx.stdout.exp index 67e27ec..940223c 100644 --- a/none/tests/ppc64/jm-vmx.stdout.exp +++ b/none/tests/ppc64/jm-vmx.stdout.exp @@ -2636,6 +2636,56 @@ Altivec floating point arith insns with one arg: vrsqrtefp: ffbfffff ffbfffff ffbfffff ffbfffff vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000) + vlogefp: 02bfffff 02bfffff 02bfffff 02bfffff + vlogefp: => c2f2d440 c2f2d440 c2f2d440 c2f2d440 (00000000) + vlogefp: 513fffff 513fffff 513fffff 513fffff + vlogefp: => 420e5780 420e5780 420e5780 420e5780 (00000000) + vlogefp: 82bfffff 82bfffff 82bfffff 82bfffff + vlogefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) + vlogefp: d13fffff d13fffff d13fffff d13fffff + vlogefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) + vlogefp: 00000000 00000000 00000000 00000000 + vlogefp: => ff800000 ff800000 ff800000 ff800000 (00000000) + vlogefp: 80000000 80000000 80000000 80000000 + vlogefp: => ff800000 ff800000 ff800000 ff800000 (00000000) + vlogefp: 7f800000 7f800000 7f800000 7f800000 + vlogefp: => 7f800000 7f800000 7f800000 7f800000 (00000000) + vlogefp: ff800000 ff800000 ff800000 ff800000 + vlogefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) + vlogefp: 7fffffff 7fffffff 7fffffff 7fffffff + vlogefp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vlogefp: ffffffff ffffffff ffffffff ffffffff + vlogefp: => ffffffff ffffffff ffffffff ffffffff (00000000) + vlogefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff + vlogefp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vlogefp: ffbfffff ffbfffff ffbfffff ffbfffff + vlogefp: => ffffffff ffffffff ffffffff ffffffff (00000000) + + vexptefp: 02bfffff 02bfffff 02bfffff 02bfffff + vexptefp: => 3f800000 3f800000 3f800000 3f800000 (00000000) + vexptefp: 513fffff 513fffff 513fffff 513fffff + vexptefp: => 7f800000 7f800000 7f800000 7f800000 (00000000) + vexptefp: 82bfffff 82bfffff 82bfffff 82bfffff + vexptefp: => 3f800000 3f800000 3f800000 3f800000 (00000000) + vexptefp: d13fffff d13fffff d13fffff d13fffff + vexptefp: => 00000000 00000000 00000000 00000000 (00000000) + vexptefp: 00000000 00000000 00000000 00000000 + vexptefp: => 3f800000 3f800000 3f800000 3f800000 (00000000) + vexptefp: 80000000 80000000 80000000 80000000 + vexptefp: => 3f800000 3f800000 3f800000 3f800000 (00000000) + vexptefp: 7f800000 7f800000 7f800000 7f800000 + vexptefp: => 7f800000 7f800000 7f800000 7f800000 (00000000) + vexptefp: ff800000 ff800000 ff800000 ff800000 + vexptefp: => 00000000 00000000 00000000 00000000 (00000000) + vexptefp: 7fffffff 7fffffff 7fffffff 7fffffff + vexptefp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vexptefp: ffffffff ffffffff ffffffff ffffffff + vexptefp: => ffffffff ffffffff ffffffff ffffffff (00000000) + vexptefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff + vexptefp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vexptefp: ffbfffff ffbfffff ffbfffff ffbfffff + vexptefp: => ffffffff ffffffff ffffffff ffffffff (00000000) + Altivec floating point compare insns: vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) @@ -3611,4 +3661,4 @@ Altivec float special insns: vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) -All done. Tested 165 different instructions +All done. Tested 167 different instructions diff --git a/none/tests/ppc64/jm-vmx.stdout.exp-LE b/none/tests/ppc64/jm-vmx.stdout.exp-LE index e901f17..f19977d 100644 --- a/none/tests/ppc64/jm-vmx.stdout.exp-LE +++ b/none/tests/ppc64/jm-vmx.stdout.exp-LE @@ -2636,6 +2636,56 @@ Altivec floating point arith insns with one arg: vrsqrtefp: ffbfffff ffbfffff ffbfffff ffbfffff vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000) + vlogefp: 02bfffff 02bfffff 02bfffff 02bfffff + vlogefp: => c2f2d440 c2f2d440 c2f2d440 c2f2d440 (00000000) + vlogefp: 513fffff 513fffff 513fffff 513fffff + vlogefp: => 420e5780 420e5780 420e5780 420e5780 (00000000) + vlogefp: 82bfffff 82bfffff 82bfffff 82bfffff + vlogefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) + vlogefp: d13fffff d13fffff d13fffff d13fffff + vlogefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) + vlogefp: 00000000 00000000 00000000 00000000 + vlogefp: => ff800000 ff800000 ff800000 ff800000 (00000000) + vlogefp: 80000000 80000000 80000000 80000000 + vlogefp: => ff800000 ff800000 ff800000 ff800000 (00000000) + vlogefp: 7f800000 7f800000 7f800000 7f800000 + vlogefp: => 7f800000 7f800000 7f800000 7f800000 (00000000) + vlogefp: ff800000 ff800000 ff800000 ff800000 + vlogefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) + vlogefp: 7fffffff 7fffffff 7fffffff 7fffffff + vlogefp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vlogefp: ffffffff ffffffff ffffffff ffffffff + vlogefp: => ffffffff ffffffff ffffffff ffffffff (00000000) + vlogefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff + vlogefp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vlogefp: ffbfffff ffbfffff ffbfffff ffbfffff + vlogefp: => ffffffff ffffffff ffffffff ffffffff (00000000) + + vexptefp: 02bfffff 02bfffff 02bfffff 02bfffff + vexptefp: => 3f800000 3f800000 3f800000 3f800000 (00000000) + vexptefp: 513fffff 513fffff 513fffff 513fffff + vexptefp: => 7f800000 7f800000 7f800000 7f800000 (00000000) + vexptefp: 82bfffff 82bfffff 82bfffff 82bfffff + vexptefp: => 3f800000 3f800000 3f800000 3f800000 (00000000) + vexptefp: d13fffff d13fffff d13fffff d13fffff + vexptefp: => 00000000 00000000 00000000 00000000 (00000000) + vexptefp: 00000000 00000000 00000000 00000000 + vexptefp: => 3f800000 3f800000 3f800000 3f800000 (00000000) + vexptefp: 80000000 80000000 80000000 80000000 + vexptefp: => 3f800000 3f800000 3f800000 3f800000 (00000000) + vexptefp: 7f800000 7f800000 7f800000 7f800000 + vexptefp: => 7f800000 7f800000 7f800000 7f800000 (00000000) + vexptefp: ff800000 ff800000 ff800000 ff800000 + vexptefp: => 00000000 00000000 00000000 00000000 (00000000) + vexptefp: 7fffffff 7fffffff 7fffffff 7fffffff + vexptefp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vexptefp: ffffffff ffffffff ffffffff ffffffff + vexptefp: => ffffffff ffffffff ffffffff ffffffff (00000000) + vexptefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff + vexptefp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vexptefp: ffbfffff ffbfffff ffbfffff ffbfffff + vexptefp: => ffffffff ffffffff ffffffff ffffffff (00000000) + Altivec floating point compare insns: vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000) @@ -3611,4 +3661,4 @@ Altivec float special insns: vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000) vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000) -All done. Tested 165 different instructions +All done. Tested 167 different instructions diff --git a/none/tests/ppc64/subnormal_test.c b/none/tests/ppc64/subnormal_test.c index 51d7d31..00a0ad8 100644 --- a/none/tests/ppc64/subnormal_test.c +++ b/none/tests/ppc64/subnormal_test.c @@ -146,15 +146,15 @@ void do_tests( void ) { print_vector_elements(dst); - // Valgrind not supported __asm__ __volatile__ ("vexptefp %0,%1" : "=v" (dst): "v" (srcA)); - // printf (" vexptefp(srcA) result = "); - // print_vector_elements(dst); + __asm__ __volatile__ ("vexptefp %0,%1" : "=v" (dst): "v" (srcA)); + printf (" vexptefp(srcA) result = "); + print_vector_elements(dst); - /* Smallest representable floating point input does not generate - a subnormal result. */ - // Valgrind not supported __asm__ __volatile__ ("vlogefp %0,%1" : "=v" (dst): "v" (srcA)); - // printf (" vlogefp(srcA) result = "); - // print_vector_elements(dst); + /* Smallest representable floating point input does not generate + a subnormal result. */ + __asm__ __volatile__ ("vlogefp %0,%1" : "=v" (dst): "v" (srcA)); + printf (" vlogefp(srcA) result = "); + print_vector_elements(dst); __asm__ __volatile__ ("vrefp %0,%1" : "=v" (dst): "v" (srcA)); printf (" vrefp(srcA) result = "); @@ -162,7 +162,7 @@ void do_tests( void ) { print_vector_elements(dst); /* Square root of the smallest representable number is a normal - number. Square root can't generate a subnormal result. */ + number. Square root can't generate a subnormal result. */ __asm__ __volatile__ ("vrsqrtefp %0,%1" : "=v" (dst): "v" (srcA)); printf (" vrsqrtefp(srcA) result = 0x%016lx 0x%016lx\n\n", dst[1], dst[0]); diff --git a/none/tests/ppc64/subnormal_test.stdout.exp b/none/tests/ppc64/subnormal_test.stdout.exp index af8d242..bdca948 100644 --- a/none/tests/ppc64/subnormal_test.stdout.exp +++ b/none/tests/ppc64/subnormal_test.stdout.exp @@ -7,6 +7,8 @@ srcA = 0x8000012480000124 0x8000012480000124 vrfim(srcA) result = 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000 vrfin(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 vrfiz(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 vrefp(srcA) result = 0xff800000, 0xff800000, 0xff800000, 0xff800000 vrsqrtefp(srcA) result = 0x7fc000007fc00000 0x7fc000007fc00000 @@ -941,6 +943,8 @@ srcA = 0x8000012480000124 0x8000012480000124 vrfim(srcA) result = 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000 vrfin(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 vrfiz(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 vrefp(srcA) result = 0xff800000, 0xff800000, 0xff800000, 0xff800000 vrsqrtefp(srcA) result = 0x7fc000007fc00000 0x7fc000007fc00000 @@ -1875,6 +1879,8 @@ srcA = 0x000000080000000a 0x000000060000000c vrfim(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 vrfin(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 vrfiz(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0xc3126a00, 0xc3116a00, 0xc3120000, 0xc311ae00 vrefp(srcA) result = 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 vrsqrtefp(srcA) result = 0x63ffff0063e4f8c0 0x6413cd0063d105c0 @@ -2809,6 +2815,8 @@ srcA = 0xfffffefcfffffdfd 0xfffffafafffffbfb vrfim(srcA) result = 0xfffffafa, 0xfffffbfb, 0xfffffefc, 0xfffffdfd vrfin(srcA) result = 0xfffffafa, 0xfffffbfb, 0xfffffefc, 0xfffffdfd vrfiz(srcA) result = 0xfffffafa, 0xfffffbfb, 0xfffffefc, 0xfffffdfd + vexptefp(srcA) result = 0xfffffafa, 0xfffffbfb, 0xfffffefc, 0xfffffdfd + vlogefp(srcA) result = 0xfffffafa, 0xfffffbfb, 0xfffffefc, 0xfffffdfd vrefp(srcA) result = 0xfffffafa, 0xfffffbfb, 0xfffffefc, 0xfffffdfd vrsqrtefp(srcA) result = 0xfffffefcfffffdfd 0xfffffafafffffbfb @@ -3743,6 +3751,8 @@ srcA = 0x0000026800000278 0x0000024800000258 vrfim(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 vrfin(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 vrfiz(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0xc30bcf00, 0xc30bc500, 0xc30bbb80, 0xc30bb280 vrefp(srcA) result = 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 vrsqrtefp(srcA) result = 0x626963c062666a80 0x626fb2c0626c7b00 @@ -4677,6 +4687,8 @@ srcA = 0x0000000400000008 0x0000000200000002 vrfim(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 vrfin(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 vrfiz(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0xc3140000, 0xc3140000, 0xc3130000, 0xc3120000 vrefp(srcA) result = 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 vrsqrtefp(srcA) result = 0x6435040063ffff00 0x647fff00647fff00 @@ -5611,6 +5623,8 @@ srcA = 0xc2fe0000c2fd0000 0xc3000000c3020000 vrfim(srcA) result = 0xc3000000, 0xc3020000, 0xc2fe0000, 0xc2fe0000 vrfin(srcA) result = 0xc3000000, 0xc3020000, 0xc2fe0000, 0xc2fc0000 vrfiz(srcA) result = 0xc3000000, 0xc3020000, 0xc2fe0000, 0xc2fc0000 + vexptefp(srcA) result = 0x00200000, 0x00080000, 0x00400000, 0x005a8000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 vrefp(srcA) result = 0xbbfffe00, 0xbbfc0d40, 0xbc010100, 0xbc018500 vrsqrtefp(srcA) result = 0x7fc000007fc00000 0x7fc000007fc00000 @@ -6545,6 +6559,8 @@ srcA = 0xc2fe0000c2fd0000 0xc3000000c3020000 vrfim(srcA) result = 0xc3000000, 0xc3020000, 0xc2fe0000, 0xc2fe0000 vrfin(srcA) result = 0xc3000000, 0xc3020000, 0xc2fe0000, 0xc2fc0000 vrfiz(srcA) result = 0xc3000000, 0xc3020000, 0xc2fe0000, 0xc2fc0000 + vexptefp(srcA) result = 0x00200000, 0x00080000, 0x00400000, 0x005a8000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 vrefp(srcA) result = 0xbbfffe00, 0xbbfc0d40, 0xbc010100, 0xbc018500 vrsqrtefp(srcA) result = 0x7fc000007fc00000 0x7fc000007fc00000 @@ -7479,6 +7495,8 @@ srcA = 0x0000000400000002 0xc2fe0000c2fd0000 vrfim(srcA) result = 0xc2fe0000, 0xc2fe0000, 0x00000000, 0x00000000 vrfin(srcA) result = 0xc2fe0000, 0xc2fc0000, 0x00000000, 0x00000000 vrfiz(srcA) result = 0xc2fe0000, 0xc2fc0000, 0x00000000, 0x00000000 + vexptefp(srcA) result = 0x00400000, 0x005a8000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0xc3130000, 0xc3140000 vrefp(srcA) result = 0xbc010100, 0xbc018500, 0x7f800000, 0x7f800000 vrsqrtefp(srcA) result = 0x64350400647fff00 0x7fc000007fc00000 @@ -8413,6 +8431,8 @@ srcA = 0x7e9676997e700022 0xc2fe0000c2fd0000 vrfim(srcA) result = 0xc2fe0000, 0xc2fe0000, 0x7e967699, 0x7e700022 vrfin(srcA) result = 0xc2fe0000, 0xc2fc0000, 0x7e967699, 0x7e700022 vrfiz(srcA) result = 0xc2fe0000, 0xc2fc0000, 0x7e967699, 0x7e700022 + vexptefp(srcA) result = 0x00400000, 0x005a8000, 0x7f800000, 0x7f800000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0x42fc7800, 0x42fbcfc0 vrefp(srcA) result = 0xbc010100, 0xbc018500, 0x006ce430, 0x00888840 vrsqrtefp(srcA) result = 0x1fec1e6820043300 0x7fc000007fc00000 @@ -9347,6 +9367,8 @@ srcA = 0x80b0000480b00006 0x80b0000180b00002 vrfim(srcA) result = 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000 vrfin(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 vrfiz(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 vrefp(srcA) result = 0xfe3a2dc0, 0xfe3a2dc0, 0xfe3a2dc0, 0xfe3a2dc0 vrsqrtefp(srcA) result = 0x7fc000007fc00000 0x7fc000007fc00000 @@ -10281,6 +10303,8 @@ srcA = 0x80b0000280b00004 0x80b0000080b00001 vrfim(srcA) result = 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000 vrfin(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 vrfiz(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 vrefp(srcA) result = 0xfe3a2dc0, 0xfe3a2dc0, 0xfe3a2dc0, 0xfe3a2dc0 vrsqrtefp(srcA) result = 0x7fc000007fc00000 0x7fc000007fc00000 @@ -11215,6 +11239,8 @@ srcA = 0x4e8000004e800000 0x4e8000004e800000 vrfim(srcA) result = 0x4e800000, 0x4e800000, 0x4e800000, 0x4e800000 vrfin(srcA) result = 0x4e800000, 0x4e800000, 0x4e800000, 0x4e800000 vrfiz(srcA) result = 0x4e800000, 0x4e800000, 0x4e800000, 0x4e800000 + vexptefp(srcA) result = 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 + vlogefp(srcA) result = 0x41f00000, 0x41f00000, 0x41f00000, 0x41f00000 vrefp(srcA) result = 0x307ffe00, 0x307ffe00, 0x307ffe00, 0x307ffe00 vrsqrtefp(srcA) result = 0x37ffff0037ffff00 0x37ffff0037ffff00 @@ -12149,6 +12175,8 @@ srcA = 0xb0000000b0000000 0xb0000000b0000000 vrfim(srcA) result = 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000 vrfin(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 vrfiz(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 vrefp(srcA) result = 0xcefffe00, 0xcefffe00, 0xcefffe00, 0xcefffe00 vrsqrtefp(srcA) result = 0x7fc000007fc00000 0x7fc000007fc00000 @@ -13085,6 +13113,8 @@ srcA = 0x8000012480000124 0x8000012480000124 vrfim(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 vrfin(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 vrfiz(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0xff800000, 0xff800000, 0xff800000, 0xff800000 vrefp(srcA) result = 0xff800000, 0xff800000, 0xff800000, 0xff800000 vrsqrtefp(srcA) result = 0xff800000ff800000 0xff800000ff800000 @@ -14019,6 +14049,8 @@ srcA = 0x8000012480000124 0x8000012480000124 vrfim(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 vrfin(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 vrfiz(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0xff800000, 0xff800000, 0xff800000, 0xff800000 vrefp(srcA) result = 0xff800000, 0xff800000, 0xff800000, 0xff800000 vrsqrtefp(srcA) result = 0xff800000ff800000 0xff800000ff800000 @@ -14953,6 +14985,8 @@ srcA = 0x000000080000000a 0x000000060000000c vrfim(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 vrfin(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 vrfiz(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0xff800000, 0xff800000, 0xff800000, 0xff800000 vrefp(srcA) result = 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 vrsqrtefp(srcA) result = 0x7f8000007f800000 0x7f8000007f800000 @@ -15887,6 +15921,8 @@ srcA = 0xfffffefcfffffdfd 0xfffffafafffffbfb vrfim(srcA) result = 0xfffffafa, 0xfffffbfb, 0xfffffefc, 0xfffffdfd vrfin(srcA) result = 0xfffffafa, 0xfffffbfb, 0xfffffefc, 0xfffffdfd vrfiz(srcA) result = 0xfffffafa, 0xfffffbfb, 0xfffffefc, 0xfffffdfd + vexptefp(srcA) result = 0xfffffafa, 0xfffffbfb, 0xfffffefc, 0xfffffdfd + vlogefp(srcA) result = 0xfffffafa, 0xfffffbfb, 0xfffffefc, 0xfffffdfd vrefp(srcA) result = 0xfffffafa, 0xfffffbfb, 0xfffffefc, 0xfffffdfd vrsqrtefp(srcA) result = 0xfffffefcfffffdfd 0xfffffafafffffbfb @@ -16821,6 +16857,8 @@ srcA = 0x0000026800000278 0x0000024800000258 vrfim(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 vrfin(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 vrfiz(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0xff800000, 0xff800000, 0xff800000, 0xff800000 vrefp(srcA) result = 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 vrsqrtefp(srcA) result = 0x7f8000007f800000 0x7f8000007f800000 @@ -17755,6 +17793,8 @@ srcA = 0x0000000400000008 0x0000000200000002 vrfim(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 vrfin(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 vrfiz(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0xff800000, 0xff800000, 0xff800000, 0xff800000 vrefp(srcA) result = 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 vrsqrtefp(srcA) result = 0x7f8000007f800000 0x7f8000007f800000 @@ -18689,6 +18729,8 @@ srcA = 0xc2fe0000c2fd0000 0xc3000000c3020000 vrfim(srcA) result = 0xc3000000, 0xc3020000, 0xc2fe0000, 0xc2fe0000 vrfin(srcA) result = 0xc3000000, 0xc3020000, 0xc2fe0000, 0xc2fc0000 vrfiz(srcA) result = 0xc3000000, 0xc3020000, 0xc2fe0000, 0xc2fc0000 + vexptefp(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 vrefp(srcA) result = 0xbbfffe00, 0xbbfc0d40, 0xbc010100, 0xbc018500 vrsqrtefp(srcA) result = 0x7fc000007fc00000 0x7fc000007fc00000 @@ -19623,6 +19665,8 @@ srcA = 0xc2fe0000c2fd0000 0xc3000000c3020000 vrfim(srcA) result = 0xc3000000, 0xc3020000, 0xc2fe0000, 0xc2fe0000 vrfin(srcA) result = 0xc3000000, 0xc3020000, 0xc2fe0000, 0xc2fc0000 vrfiz(srcA) result = 0xc3000000, 0xc3020000, 0xc2fe0000, 0xc2fc0000 + vexptefp(srcA) result = 0x00000000, 0x00000000, 0x00000000, 0x00000000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 vrefp(srcA) result = 0xbbfffe00, 0xbbfc0d40, 0xbc010100, 0xbc018500 vrsqrtefp(srcA) result = 0x7fc000007fc00000 0x7fc000007fc00000 @@ -20557,6 +20601,8 @@ srcA = 0x0000000400000002 0xc2fe0000c2fd0000 vrfim(srcA) result = 0xc2fe0000, 0xc2fe0000, 0x00000000, 0x00000000 vrfin(srcA) result = 0xc2fe0000, 0xc2fc0000, 0x00000000, 0x00000000 vrfiz(srcA) result = 0xc2fe0000, 0xc2fc0000, 0x00000000, 0x00000000 + vexptefp(srcA) result = 0x00000000, 0x00000000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0xff800000, 0xff800000 vrefp(srcA) result = 0xbc010100, 0xbc018500, 0x7f800000, 0x7f800000 vrsqrtefp(srcA) result = 0x7f8000007f800000 0x7fc000007fc00000 @@ -21491,6 +21537,8 @@ srcA = 0x7e9676997e700022 0xc2fe0000c2fd0000 vrfim(srcA) result = 0xc2fe0000, 0xc2fe0000, 0x7e967699, 0x7e700022 vrfin(srcA) result = 0xc2fe0000, 0xc2fc0000, 0x7e967699, 0x7e700022 vrfiz(srcA) result = 0xc2fe0000, 0xc2fc0000, 0x7e967699, 0x7e700022 + vexptefp(srcA) result = 0x00000000, 0x00000000, 0x7f800000, 0x7f800000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0x42fc7800, 0x42fbcfc0 vrefp(srcA) result = 0xbc010100, 0xbc018500, 0x00000000, 0x00888840 vrsqrtefp(srcA) result = 0x1fec1e6820043300 0x7fc000007fc00000 @@ -22425,6 +22473,8 @@ srcA = 0x80b0000480b00006 0x80b0000180b00002 vrfim(srcA) result = 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000 vrfin(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 vrfiz(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 vrefp(srcA) result = 0xfe3a2dc0, 0xfe3a2dc0, 0xfe3a2dc0, 0xfe3a2dc0 vrsqrtefp(srcA) result = 0x7fc000007fc00000 0x7fc000007fc00000 @@ -23359,6 +23409,8 @@ srcA = 0x80b0000280b00004 0x80b0000080b00001 vrfim(srcA) result = 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000 vrfin(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 vrfiz(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 vrefp(srcA) result = 0xfe3a2dc0, 0xfe3a2dc0, 0xfe3a2dc0, 0xfe3a2dc0 vrsqrtefp(srcA) result = 0x7fc000007fc00000 0x7fc000007fc00000 @@ -24293,6 +24345,8 @@ srcA = 0x4e8000004e800000 0x4e8000004e800000 vrfim(srcA) result = 0x4e800000, 0x4e800000, 0x4e800000, 0x4e800000 vrfin(srcA) result = 0x4e800000, 0x4e800000, 0x4e800000, 0x4e800000 vrfiz(srcA) result = 0x4e800000, 0x4e800000, 0x4e800000, 0x4e800000 + vexptefp(srcA) result = 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 + vlogefp(srcA) result = 0x41f00000, 0x41f00000, 0x41f00000, 0x41f00000 vrefp(srcA) result = 0x307ffe00, 0x307ffe00, 0x307ffe00, 0x307ffe00 vrsqrtefp(srcA) result = 0x37ffff0037ffff00 0x37ffff0037ffff00 @@ -25227,6 +25281,8 @@ srcA = 0xb0000000b0000000 0xb0000000b0000000 vrfim(srcA) result = 0xbf800000, 0xbf800000, 0xbf800000, 0xbf800000 vrfin(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 vrfiz(srcA) result = 0x80000000, 0x80000000, 0x80000000, 0x80000000 + vexptefp(srcA) result = 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 + vlogefp(srcA) result = 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000 vrefp(srcA) result = 0xcefffe00, 0xcefffe00, 0xcefffe00, 0xcefffe00 vrsqrtefp(srcA) result = 0x7fc000007fc00000 0x7fc000007fc00000 |
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From: Carl L. <ca...@so...> - 2019-05-28 19:45:59
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3a345d9f8e8e98ee74f2c66f69ab51220cd18d47 commit 3a345d9f8e8e98ee74f2c66f69ab51220cd18d47 Author: Carl Love <ca...@us...> Date: Tue May 28 14:07:04 2019 -0500 PPC64, Add support for vlogefp, vexptefp instructions Add Iop_Exp2_32Fx4 to VEX/pub/libvex_ir.h to support the 2^x instruction. Enable the existing test support for the two instructions in none/tests/ppc64/subnormal_test.c and none/tests/ppc64/jm-insns.c. https://bugs.kde.org/show_bug.cgi?id=407340 Diff: --- NEWS | 1 + VEX/priv/guest_ppc_toIR.c | 12 ++++++++---- VEX/priv/host_ppc_defs.c | 4 ++++ VEX/priv/host_ppc_defs.h | 2 +- VEX/priv/host_ppc_isel.c | 2 ++ VEX/priv/ir_defs.c | 4 +++- VEX/pub/libvex_ir.h | 2 ++ memcheck/mc_translate.c | 1 + memcheck/tests/vbit-test/irops.c | 1 + 9 files changed, 23 insertions(+), 6 deletions(-) diff --git a/NEWS b/NEWS index 788e92f..753171f 100644 --- a/NEWS +++ b/NEWS @@ -212,6 +212,7 @@ where XXXXXX is the bug number as listed below. 406360 memcheck/tests/libstdc++.supp needs more supression variants 406422 none/tests/amd64-linux/map_32bits.vgtest fails too easily 406465 arm64 insn selector fails on "t0 = <expr>" where <expr> has type Ity_F16 +407340 PPC64, does not support the vlogefp, vexptefp instructions. n-i-bz add syswrap for PTRACE_GET|SET_THREAD_AREA on amd64. n-i-bz Fix callgrind_annotate non deterministic order for equal total n-i-bz callgrind_annotate --threshold=100 does not print all functions. diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index ad79b5e..12480b3 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -27702,17 +27702,21 @@ static Bool dis_av_fp_arith ( UInt theInstr ) case 0x18A: // vexptefp (2 Raised to the Exp Est FP, AV p173) DIP("vexptefp v%d,v%d\n", vD_addr, vB_addr); - DIP(" => not implemented\n"); /* NOTE, need to address dnormalized value handling when this is implemented. */ - return False; + putVReg( vD_addr, + dnorm_adj_Vector( unop( Iop_Exp2_32Fx4, + dnorm_adj_Vector( mkexpr( vB ) ) ) ) ); + return True; case 0x1CA: // vlogefp (Log2 Estimate FP, AV p175) DIP("vlogefp v%d,v%d\n", vD_addr, vB_addr); - DIP(" => not implemented\n"); /* NOTE, need to address dnormalized value handling when this is implemented. */ - return False; + putVReg( vD_addr, + dnorm_adj_Vector( unop( Iop_Log2_32Fx4, + dnorm_adj_Vector( mkexpr( vB ) ) ) ) ); + return True; default: vex_printf("dis_av_fp_arith(ppc)(opc2=0x%x)\n",opc2); diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c index 682500a..6c298fa 100644 --- a/VEX/priv/host_ppc_defs.c +++ b/VEX/priv/host_ppc_defs.c @@ -750,6 +750,8 @@ const HChar* showPPCAvFpOp ( PPCAvFpOp op ) { /* Floating Point Unary */ case Pavfp_RCPF: return "vrefp"; case Pavfp_RSQRTF: return "vrsqrtefp"; + case Pavfp_Log2: return "vlogefp"; + case Pavfp_Exp2: return "vexptefp"; case Pavfp_CVTU2F: return "vcfux"; case Pavfp_CVTS2F: return "vcfsx"; case Pavfp_QCVTF2U: return "vctuxs"; @@ -5733,6 +5735,8 @@ Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, switch (i->Pin.AvUn32Fx4.op) { case Pavfp_RCPF: opc2 = 266; break; // vrefp case Pavfp_RSQRTF: opc2 = 330; break; // vrsqrtefp + case Pavfp_Log2: opc2 = 458; break; // vlogefp + case Pavfp_Exp2: opc2 = 394; break; // vexptefp case Pavfp_CVTU2F: opc2 = 778; break; // vcfux case Pavfp_CVTS2F: opc2 = 842; break; // vcfsx case Pavfp_QCVTF2U: opc2 = 906; break; // vctuxs diff --git a/VEX/priv/host_ppc_defs.h b/VEX/priv/host_ppc_defs.h index 0d05954..70c3b6c 100644 --- a/VEX/priv/host_ppc_defs.h +++ b/VEX/priv/host_ppc_defs.h @@ -489,7 +489,7 @@ typedef Pavfp_CMPEQF, Pavfp_CMPGTF, Pavfp_CMPGEF, /* Floating point unary */ - Pavfp_RCPF, Pavfp_RSQRTF, + Pavfp_RCPF, Pavfp_RSQRTF, Pavfp_Log2, Pavfp_Exp2, Pavfp_CVTU2F, Pavfp_CVTS2F, Pavfp_QCVTF2U, Pavfp_QCVTF2S, Pavfp_ROUNDM, Pavfp_ROUNDP, Pavfp_ROUNDN, Pavfp_ROUNDZ, } diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c index e05145c..5e2a3b8 100644 --- a/VEX/priv/host_ppc_isel.c +++ b/VEX/priv/host_ppc_isel.c @@ -5779,6 +5779,8 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e, case Iop_RecipEst32Fx4: fpop = Pavfp_RCPF; goto do_32Fx4_unary; case Iop_RSqrtEst32Fx4: fpop = Pavfp_RSQRTF; goto do_32Fx4_unary; + case Iop_Log2_32Fx4: fpop = Pavfp_Log2; goto do_32Fx4_unary; + case Iop_Exp2_32Fx4: fpop = Pavfp_Exp2; goto do_32Fx4_unary; case Iop_I32UtoF32x4_DEP: fpop = Pavfp_CVTU2F; goto do_32Fx4_unary; case Iop_I32StoF32x4_DEP: fpop = Pavfp_CVTS2F; goto do_32Fx4_unary; case Iop_QF32toI32Ux4_RZ: fpop = Pavfp_QCVTF2U; goto do_32Fx4_unary; diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c index f30cf0d..30e936a 100644 --- a/VEX/priv/ir_defs.c +++ b/VEX/priv/ir_defs.c @@ -707,7 +707,8 @@ void ppIROp ( IROp op ) case Iop_Scale2_64Fx2: vex_printf("Scale2_64Fx2"); return; case Iop_Log2_32Fx4: vex_printf("Log2_32Fx4"); return; case Iop_Log2_64Fx2: vex_printf("Log2_64Fx2"); return; - + case Iop_Exp2_32Fx4: vex_printf("Iop_Exp2_32Fx4"); return; + case Iop_Sub32Fx4: vex_printf("Sub32Fx4"); return; case Iop_Sub32Fx2: vex_printf("Sub32Fx2"); return; case Iop_Sub32F0x4: vex_printf("Sub32F0x4"); return; @@ -3012,6 +3013,7 @@ void typeOfPrimop ( IROp op, TERNARY(ity_RMode,Ity_V128,Ity_V128, Ity_V128); case Iop_Log2_32Fx4: case Iop_Log2_64Fx2: + case Iop_Exp2_32Fx4: UNARY(Ity_V128, Ity_V128); case Iop_V128to64: case Iop_V128HIto64: diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h index d797bd4..d5e7f50 100644 --- a/VEX/pub/libvex_ir.h +++ b/VEX/pub/libvex_ir.h @@ -1385,6 +1385,8 @@ typedef /* Vector floating-point base 2 logarithm */ Iop_Log2_32Fx4, + /* Vector floating-point exponential 2^x */ + Iop_Exp2_32Fx4, /* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0. Note, that of one of the arguments is zero and another one is infiinty diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c index 424de15..02b93ba 100644 --- a/memcheck/mc_translate.c +++ b/memcheck/mc_translate.c @@ -4921,6 +4921,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom ) case Iop_Neg32Fx4: case Iop_RSqrtEst32Fx4: case Iop_Log2_32Fx4: + case Iop_Exp2_32Fx4: return unary32Fx4(mce, vatom); case Iop_I32UtoF32x2_DEP: diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c index 58d03e9..29451b4 100644 --- a/memcheck/tests/vbit-test/irops.c +++ b/memcheck/tests/vbit-test/irops.c @@ -631,6 +631,7 @@ static irop_t irops[] = { { DEFOP(Iop_Sqrt32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Scale2_32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Log2_32Fx4, UNDEF_UNKNOWN), }, + { DEFOP(Iop_Exp2_32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_Neg32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_RecipEst32Fx4, UNDEF_UNKNOWN), }, { DEFOP(Iop_RecipStep32Fx4, UNDEF_UNKNOWN), }, |
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From: Carl L. <ca...@so...> - 2019-05-28 18:51:55
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=d2cbb78a151256290d490fcb7a805884d6406a7e commit d2cbb78a151256290d490fcb7a805884d6406a7e Author: Carl Love <ca...@us...> Date: Tue May 28 11:33:00 2019 -0500 PPC64, Subnormal testcase changes VEX patch fixed issues with generating subnormal results. This patch adds a specific test case and updates the expected values for the existing test case. Update jm-vmx tests, add subnormal test case. https://bugs.kde.org/show_bug.cgi?id=406256 Diff: --- none/tests/ppc32/jm-insns.c | 5 +- none/tests/ppc32/jm-vmx.stdout.exp | 384 +- none/tests/ppc64/Makefile.am | 16 +- none/tests/ppc64/jm-vmx.stdout.exp | 384 +- none/tests/ppc64/jm-vmx.stdout.exp-LE | 384 +- none/tests/ppc64/subnormal_test.c | 306 + none/tests/ppc64/subnormal_test.stderr.exp | 2 + none/tests/ppc64/subnormal_test.stdout.exp | 26156 +++++++++++++++++++++++++++ none/tests/ppc64/subnormal_test.vgtest | 2 + 9 files changed, 27060 insertions(+), 579 deletions(-) diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c index 339ebe8..e6e947c 100644 --- a/none/tests/ppc32/jm-insns.c +++ b/none/tests/ppc32/jm-insns.c @@ -7200,7 +7200,8 @@ static void test_av_float_three_args (const char* name, test_func_t func, /* Valgrind emulation for vmaddfp and vnmsubfp generates negative * NAN. Technically, NAN is not positive or negative so mask off - * the sign bit to eliminate false errors. + * the sign bit to eliminate false errors. The lower 22-bits of + * the 23-bit significand are a don't care for a NAN. Mask them off. * * Valgrind emulation is creating negative zero. Mask off negative * from zero result. @@ -7216,7 +7217,7 @@ static void test_av_float_three_args (const char* name, test_func_t func, /* NAN result*/ if (((dst[n] & 0x7F800000) == 0x7F800000) && ((dst[n] & 0x7FFFFF) != 0)) - dst[n] &= 0x7FFFFFFF; + dst[n] &= 0x7FC00000; /* Negative zero result */ else if (dst[n] == 0x80000000) diff --git a/none/tests/ppc32/jm-vmx.stdout.exp b/none/tests/ppc32/jm-vmx.stdout.exp index 43faa1a..307c75f 100644 --- a/none/tests/ppc32/jm-vmx.stdout.exp +++ b/none/tests/ppc32/jm-vmx.stdout.exp @@ -1912,578 +1912,578 @@ Altivec floating point arith insns with three args: vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vmaddfp: => 00000000 00000000 00000000 00000000 (00000000) vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000) vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000) vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vmaddfp: => 00000000 00000000 00000000 00000000 (00000000) vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000) vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000) vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vmaddfp: => 00000000 00000000 00000000 00000000 (00000000) vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vmaddfp: => 00000000 00000000 00000000 00000000 (00000000) vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vmaddfp: => 00000000 00000000 00000000 00000000 (00000000) vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vmaddfp: => 00000000 00000000 00000000 00000000 (00000000) vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000) vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000) vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000) vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000) vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000) vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000) vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000) vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000) vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000) vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000) vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000) vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000) vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000) vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000) vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000) vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000 - vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000) + vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000) vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff - vnmsubfp: => 7fffffff 7fffffff 7fffff... [truncated message content] |
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From: Carl L. <ca...@so...> - 2019-05-28 18:51:48
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=991db2a39bcbdbf5cdb4337684c29f96c63070a8 commit 991db2a39bcbdbf5cdb4337684c29f96c63070a8 Author: Carl Love <ca...@us...> Date: Tue May 28 11:26:13 2019 -0500 PPC64, fix issues with dnormal values in the vector fp instructions. The result of the floating point instructions vmaddfp, vnmsubfp, vaddfp, vsubfp, vmaxfp, vminfp, vrefp, vrsqrtefp, vcmpeqfp, vcmpeqfp, vcmpgefp, vcmpgtfp are controlled by the setting of the NJ bit in the VSCR register. If VSCR[NJ] = 0; then denormalized values are handled as specified by Java and the IEEE standard. If the bit is a 1, then the denormalized element in the vector is replaced with a zero. Valgrind was not properly handling the denormalized case for these instructions. This patch fixes the issue. https://bugs.kde.org/show_bug.cgi?id=406256 Diff: --- NEWS | 2 + VEX/priv/guest_ppc_helpers.c | 20 +- VEX/priv/guest_ppc_toIR.c | 389 ++++++++++++++++++++++---- coregrind/m_dispatch/dispatch-ppc32-linux.S | 5 +- coregrind/m_dispatch/dispatch-ppc64be-linux.S | 8 +- coregrind/m_dispatch/dispatch-ppc64le-linux.S | 8 +- 6 files changed, 373 insertions(+), 59 deletions(-) diff --git a/NEWS b/NEWS index 53c92ce..788e92f 100644 --- a/NEWS +++ b/NEWS @@ -203,6 +203,8 @@ where XXXXXX is the bug number as listed below. 405782 "VEX temporary storage exhausted" when attempting to debug slic3r-pe 406198 none/tests/ppc64/test_isa_3_0_other test sporadically including CA bit in output. +406256 PPC64, vector floating point instructions don't handle subnormal + according to VSCR[NJ] bit setting. 406352 cachegrind/callgrind fails ann tests because of missing a.c 406354 dhat is broken on x86 (32bit) 406355 mcsignopass, mcsigpass, mcbreak fail due to difference in gdb output diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c index 9cabe28..80c7965 100644 --- a/VEX/priv/guest_ppc_helpers.c +++ b/VEX/priv/guest_ppc_helpers.c @@ -833,7 +833,15 @@ void LibVEX_GuestPPC32_initialise ( /*OUT*/VexGuestPPC32State* vex_state ) vex_state->guest_VRSAVE = 0; - vex_state->guest_VSCR = 0x0; // Non-Java mode = 0 +# if defined(VGP_ppc64be_linux) + /* By default, the HW for BE sets the VSCR[NJ] bit to 1. + VSR is a 128-bit register, NJ bit is bit 111 (IBM numbering). + However, VSCR is modeled as a 64-bit register. */ + vex_state->guest_VSCR = 0x1 << (127 - 111); +# else + /* LE API requires NJ be set to 0. */ + vex_state->guest_VSCR = 0x0; +#endif vex_state->guest_EMNOTE = EmNote_NONE; @@ -1000,7 +1008,15 @@ void LibVEX_GuestPPC64_initialise ( /*OUT*/VexGuestPPC64State* vex_state ) vex_state->guest_VRSAVE = 0; - vex_state->guest_VSCR = 0x0; // Non-Java mode = 0 +# if defined(VGP_ppc64be_linux) + /* By default, the HW for BE sets the VSCR[NJ] bit to 1. + VSR is a 128-bit register, NJ bit is bit 111 (IBM numbering). + However, VSCR is modeled as a 64-bit register. */ + vex_state->guest_VSCR = 0x1 << (127 - 111); +# else + /* LE API requires NJ be set to 0. */ + vex_state->guest_VSCR = 0x0; +#endif vex_state->guest_EMNOTE = EmNote_NONE; diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 81ae16f..ad79b5e 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -154,6 +154,35 @@ * register" (i.e, the part on the left side). * */ + +/* Notes on handling subnormal results: + * + * The various vector floating point instructions: + * vmaddfp, vaddfp, vsubfp, vmaxfp, vminfp, vrefp, vexptefp, + * vlogefp, vcmpeqfp, vcmpgefp, vcmpgtfp, vcmpbfp, vrfin, vrfiz, + * vrfip, vrfim + * generate subnormal results that are controled by the VSCR[NJ] bit setting. + * + * The following describes how the host and guest is setup so that the function + * dnorm_adj_Vector() can properly handle the results of the Iops in the guest + * state. + * + * At startup, on all host variants, we set VSCR[NJ].host = 0 (don't flush to + * zero). It stays at 0 permanently. + * + * At startup, we set VSCR[NJ].guest = (if BE then 1 else 0) + * + * When running, guest insns can set/clear/query VSCR[NJ].guest as they + * like. + * + * When running, any (guest) insn whose result depends on VSCR[NJ] will query + * VSCR[NJ].guest and the results will be truncated accordingly, by + * dnorm_adj_Vector(). Because VSCR[NJ].host is always 0, we will always + * be able to provide correct guest results for either value of + * VSCR[NJ].guest. + */ + + /* Translates PPC32/64 code to IR. */ /* References @@ -470,23 +499,6 @@ typedef enum { /*------------------------------------------------------------*/ -/*--- FP Helpers ---*/ -/*------------------------------------------------------------*/ - -/* Produce the 32-bit pattern corresponding to the supplied - float. */ -static UInt float_to_bits ( Float f ) -{ - union { UInt i; Float f; } u; - vassert(4 == sizeof(UInt)); - vassert(4 == sizeof(Float)); - vassert(4 == sizeof(u)); - u.f = f; - return u.i; -} - - -/*------------------------------------------------------------*/ /*--- Misc Helpers ---*/ /*------------------------------------------------------------*/ @@ -3666,6 +3678,7 @@ static IRExpr * fp_exp_part( IRType size, IRTemp src ) #define I32_EXP_MASK 0x7F800000 #define I32_FRACTION_MASK 0x007FFFFF #define I32_MSB_FRACTION_MASK 0x00400000 +#define I32_SIGN_MASK 0x80000000 #define I64_EXP_MASK 0x7FF0000000000000ULL #define I64_FRACTION_MASK 0x000FFFFFFFFFFFFFULL #define I64_MSB_FRACTION_MASK 0x0008000000000000ULL @@ -3943,6 +3956,117 @@ static IRExpr * is_Denorm( IRType size, IRTemp src ) return mkAND1( zero_exp, not_zero_frac ); } +static IRExpr * is_Zero_Vector( IRType element_size, IRExpr *src ) +{ +/* Check elements of a 128-bit floating point vector, with element size + element_size, are zero. Return 1's in the elements of the vector + which are values. */ + IRTemp exp_maskV128 = newTemp( Ity_V128 ); + IRTemp exp_zeroV128 = newTemp( Ity_V128 ); + IRTemp frac_maskV128 = newTemp( Ity_V128 ); + IRTemp frac_zeroV128 = newTemp( Ity_V128 ); + IRTemp zeroV128 = newTemp( Ity_V128 ); + + assign( zeroV128, mkV128( 0 ) ); + + if ( element_size == Ity_I32 ) { + assign( exp_maskV128, unop( Iop_Dup32x4, mkU32( I32_EXP_MASK ) ) ); + assign( frac_maskV128, unop( Iop_Dup32x4, mkU32( I32_FRACTION_MASK ) ) ); + + } else + vex_printf("ERROR, is_Zero_Vector: Unknown input size\n"); + + /* CmpEQ32x4 returns all 1's in elements where comparison is true */ + assign( exp_zeroV128, + binop( Iop_CmpEQ32x4, + binop( Iop_AndV128, + mkexpr( exp_maskV128 ), src ), + mkexpr( zeroV128 ) ) ); + + assign( frac_zeroV128, + binop( Iop_CmpEQ32x4, + binop( Iop_AndV128, + mkexpr( frac_maskV128 ), src ), + mkexpr( zeroV128 ) ) ); + + return binop( Iop_AndV128, mkexpr( exp_zeroV128 ), + mkexpr( frac_zeroV128 ) ); +} + +static IRExpr * is_Denorm_Vector( IRType element_size, IRExpr *src ) +{ +/* Check elements of a 128-bit floating point vector, with element size + element_size, are Denorm. Return 1's in the elements of the vector + which are denormalized values. */ + IRTemp exp_maskV128 = newTemp( Ity_V128 ); + IRTemp exp_zeroV128 = newTemp( Ity_V128 ); + IRTemp frac_maskV128 = newTemp( Ity_V128 ); + IRTemp frac_nonzeroV128 = newTemp( Ity_V128 ); + IRTemp zeroV128 = newTemp( Ity_V128 ); + + assign( zeroV128, mkV128(0 ) ); + + if ( element_size == Ity_I32 ) { + assign( exp_maskV128, unop( Iop_Dup32x4, mkU32( I32_EXP_MASK ) ) ); + assign( frac_maskV128, unop( Iop_Dup32x4, mkU32( I32_FRACTION_MASK ) ) ); + + } else + vex_printf("ERROR, is_Denorm_Vector: Unknown input size\n"); + + /* CmpEQ32x4 returns all 1's in elements where comparison is true */ + assign( exp_zeroV128, + binop( Iop_CmpEQ32x4, + binop( Iop_AndV128, + mkexpr( exp_maskV128 ), src ), + mkexpr( zeroV128 ) ) ); + + assign( frac_nonzeroV128, + unop( Iop_NotV128, + binop( Iop_CmpEQ32x4, + binop( Iop_AndV128, + mkexpr( frac_maskV128 ), src ), + mkexpr( zeroV128 ) ) ) ); + + return binop( Iop_AndV128, mkexpr( exp_zeroV128 ), + mkexpr( frac_nonzeroV128 ) ); +} + +static IRExpr * is_NaN_Vector( IRType element_size, IRExpr *src ) +{ + IRTemp max_expV128 = newTemp( Ity_V128 ); + IRTemp not_zero_fracV128 = newTemp( Ity_V128 ); + IRTemp zeroV128 = newTemp( Ity_V128 ); + IRTemp exp_maskV128 = newTemp( Ity_V128 ); + IRTemp frac_maskV128 = newTemp( Ity_V128 ); + IROp opCmpEQ; + + assign( zeroV128, mkV128( 0 ) ); + + if ( element_size == Ity_I32 ) { + assign( exp_maskV128, unop( Iop_Dup32x4, mkU32( I32_EXP_MASK ) ) ); + assign( frac_maskV128, unop( Iop_Dup32x4, mkU32( I32_FRACTION_MASK ) ) ); + opCmpEQ = Iop_CmpEQ32x4; + + } else + vex_printf("ERROR, is_NaN_Vector: Unknown input size\n"); + + /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */ + assign( max_expV128, + binop( opCmpEQ, + binop( Iop_AndV128, src, mkexpr( exp_maskV128 ) ), + mkexpr( exp_maskV128 ) ) ); + + /* check fractional part is not zero */ + assign( not_zero_fracV128, + unop( Iop_NotV128, + binop( opCmpEQ, + binop( Iop_AndV128, src, mkexpr( frac_maskV128 ) ), + mkexpr( zeroV128 ) ) ) ); + + return binop( Iop_AndV128, mkexpr( max_expV128 ), + mkexpr( not_zero_fracV128 ) ); +} + #if 0 /* Normalized number has exponent between 1 and max_exp -1, or in other words the exponent is not zero and not equal to the max exponent value. */ @@ -4171,6 +4295,31 @@ static IRTemp getNegatedResult_32(IRTemp intermediateResult) return negatedResult; } +static IRExpr* negate_Vector ( IRType element_size, IRExpr* value ) +{ + /* This function takes a vector of floats. If the value is + not a NaN, the value is negated. */ + + IRTemp not_nan_mask = newTemp( Ity_V128 ); + IRTemp sign_maskV128 = newTemp( Ity_V128 ); + + if ( element_size == Ity_I32 ) { + assign( sign_maskV128, unop( Iop_Dup32x4, mkU32( I32_SIGN_MASK ) ) ); + + } else + vex_printf("ERROR, negate_Vector: Unknown input size\n"); + + /* Determine if vector elementes are not a NaN, negate sign bit + for non NaN elements */ + assign ( not_nan_mask, + unop( Iop_NotV128, is_NaN_Vector( element_size, value ) ) ); + + return binop( Iop_XorV128, + binop( Iop_AndV128, + mkexpr( sign_maskV128 ), mkexpr( not_nan_mask ) ), + value ); +} + /* This function takes two quad_precision floating point numbers of type V128 and return 1 if src_A > src_B, 0 otherwise. */ static IRExpr * Quad_precision_gt ( IRTemp src_A, IRTemp src_B ) @@ -4807,6 +4956,106 @@ static IRExpr * UNSIGNED_CMP_GT_V128 ( IRExpr *vA, IRExpr *vB ) { } /*------------------------------------------------------------*/ +/*--- FP Helpers ---*/ +/*------------------------------------------------------------*/ + +/* Produce the 32-bit pattern corresponding to the supplied + float. */ +static UInt float_to_bits ( Float f ) +{ + union { UInt i; Float f; } u; + vassert(4 == sizeof(UInt)); + vassert(4 == sizeof(Float)); + vassert(4 == sizeof(u)); + u.f = f; + return u.i; +} + +static IRExpr* dnorm_adj_Vector ( IRExpr* src ) +{ + /* This function takes a vector of 32-bit floats. It does the required + adjustment on denormalized values based on the setting of the + VSCR[NJ] bit. + + The VSCR[NJ] bit controlls how subnormal (denormalized) results for + vector floating point operations are handled. VSCR[NJ] is bit 17 + (bit 111 IBM numbering). + + VSCR[NJ] = 0 Denormalized values are handled as + specified by Java and the IEEE standard. + + VSCR[NJ] = 1 If an element in a source VR contains a denormalized + value, the value 0 is used instead. If an instruction + causes an Underflow Exception, the corresponding element + in the target VR is set to 0. In both cases the 0 has + the same sign as the denormalized or underflowing value. + Convert negative zero to positive zero. + + The ABI for LE requires VSCR[NJ] = 0. For BE mode, VSCR[NJ] = 1 by + default. The PPC guest state is initialized to match the HW setup. + */ + IRTemp sign_bit_maskV128 = newTemp( Ity_V128 ); + IRTemp ones_maskV128 = newTemp( Ity_V128 ); + IRTemp clear_dnorm_maskV128 = newTemp( Ity_V128 ); + IRTemp adj_valueV128 = newTemp( Ity_V128 ); + IRTemp dnormV128 = newTemp( Ity_V128 ); + IRTemp zeroV128 = newTemp( Ity_V128 ); + IRTemp VSCR_NJ = newTemp( Ity_I64 ); + IRTemp VSCR_NJ_mask = newTemp( Ity_V128 ); + IRTemp resultV128 = newTemp( Ity_V128 ); + + /* get the VSCR[NJ] bit */ + assign( VSCR_NJ, + unop( Iop_1Sto64, + unop( Iop_32to1, + binop( Iop_Shr32, + getGST( PPC_GST_VSCR ), + mkU8( 16 ) ) ) ) ); + + assign ( VSCR_NJ_mask, binop( Iop_64HLtoV128, + mkexpr( VSCR_NJ ) , + mkexpr( VSCR_NJ ) ) ); + + /* Create the masks to do the rounding of dnorm values and absolute + value of zero. */ + assign( dnormV128, is_Denorm_Vector( Ity_I32, src ) ); + assign( zeroV128, is_Zero_Vector( Ity_I32, src ) ); + + /* If the value is dnorm, then we need to clear the significand and + exponent but leave the sign bit. Put 1'x in elements that are not + denormalized values. */ + assign( sign_bit_maskV128, unop( Iop_Dup32x4, mkU32( 0x80000000 ) ) ); + + assign( clear_dnorm_maskV128, + binop( Iop_OrV128, + binop( Iop_AndV128, + mkexpr( dnormV128 ), + mkexpr( sign_bit_maskV128 ) ), + unop( Iop_NotV128, mkexpr( dnormV128 ) ) ) ); + + assign( ones_maskV128, mkV128( 0xFFFF ) ); + + assign( adj_valueV128, binop( Iop_AndV128, + mkexpr( clear_dnorm_maskV128 ), + binop( Iop_AndV128, + src, + mkexpr( ones_maskV128 ) ) ) ); + + /* If the VSCR[NJ] bit is 1, then clear the denormalized values, + otherwise just return the input unchanged. */ + assign( resultV128, + binop( Iop_OrV128, + binop( Iop_AndV128, + mkexpr( VSCR_NJ_mask ), + mkexpr( adj_valueV128 ) ), + binop( Iop_AndV128, + unop( Iop_NotV128, mkexpr( VSCR_NJ_mask ) ), + src ) ) ); + + return mkexpr(resultV128); +} + +/*------------------------------------------------------------*/ /* Transactional memory helpers * *------------------------------------------------------------*/ @@ -27364,22 +27613,33 @@ static Bool dis_av_fp_arith ( UInt theInstr ) DIP("vmaddfp v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vC_addr, vB_addr); putVReg( vD_addr, - triop(Iop_Add32Fx4, mkU32(Irrm_NEAREST), - mkexpr(vB), - triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST), - mkexpr(vA), mkexpr(vC))) ); + dnorm_adj_Vector( + triop( Iop_Add32Fx4, + mkU32( Irrm_NEAREST ), + dnorm_adj_Vector( mkexpr( vB ) ), + dnorm_adj_Vector( triop( Iop_Mul32Fx4, + mkU32( Irrm_NEAREST ), + dnorm_adj_Vector( mkexpr( vA ) ), + dnorm_adj_Vector( mkexpr( vC ) ) ) + ) ) ) ); return True; case 0x2F: { // vnmsubfp (Negative Multiply-Subtract FP, AV p215) DIP("vnmsubfp v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vC_addr, vB_addr); putVReg( vD_addr, - triop(Iop_Sub32Fx4, mkU32(Irrm_NEAREST), - mkexpr(vB), - triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST), - mkexpr(vA), mkexpr(vC))) ); - return True; - } + negate_Vector( Ity_I32, + dnorm_adj_Vector( + triop( Iop_Sub32Fx4, + mkU32( Irrm_NEAREST ), + dnorm_adj_Vector( + triop( Iop_Mul32Fx4, + mkU32( Irrm_NEAREST ), + dnorm_adj_Vector( mkexpr( vA ) ), + dnorm_adj_Vector( mkexpr( vC ) ) ) ), + dnorm_adj_Vector( mkexpr( vB ) ) ) ) ) ); + return True; + } default: break; // Fall through... @@ -27389,24 +27649,32 @@ static Bool dis_av_fp_arith ( UInt theInstr ) switch (opc2) { case 0x00A: // vaddfp (Add FP, AV p137) DIP("vaddfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); - putVReg( vD_addr, triop(Iop_Add32Fx4, - mkU32(Irrm_NEAREST), mkexpr(vA), mkexpr(vB)) ); + putVReg( vD_addr, + dnorm_adj_Vector( triop( Iop_Add32Fx4, mkU32( Irrm_NEAREST ), + dnorm_adj_Vector( mkexpr( vA ) ), + dnorm_adj_Vector( mkexpr( vB ) ) ) ) ); return True; case 0x04A: // vsubfp (Subtract FP, AV p261) DIP("vsubfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); - putVReg( vD_addr, triop(Iop_Sub32Fx4, - mkU32(Irrm_NEAREST), mkexpr(vA), mkexpr(vB)) ); + putVReg( vD_addr, + dnorm_adj_Vector( triop( Iop_Sub32Fx4, mkU32( Irrm_NEAREST ), + dnorm_adj_Vector( mkexpr( vA ) ), + dnorm_adj_Vector( mkexpr( vB ) ) ) ) ); return True; case 0x40A: // vmaxfp (Maximum FP, AV p178) DIP("vmaxfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); - putVReg( vD_addr, binop(Iop_Max32Fx4, mkexpr(vA), mkexpr(vB)) ); + putVReg( vD_addr, + dnorm_adj_Vector( binop( Iop_Max32Fx4, + mkexpr( vA ), mkexpr( vB ) ) ) ); return True; case 0x44A: // vminfp (Minimum FP, AV p187) DIP("vminfp v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr); - putVReg( vD_addr, binop(Iop_Min32Fx4, mkexpr(vA), mkexpr(vB)) ); + putVReg( vD_addr, + dnorm_adj_Vector( binop( Iop_Min32Fx4, + mkexpr( vA ), mkexpr( vB ) ) ) ); return True; default: @@ -27422,22 +27690,28 @@ static Bool dis_av_fp_arith ( UInt theInstr ) switch (opc2) { case 0x10A: // vrefp (Reciprocal Esimate FP, AV p228) DIP("vrefp v%d,v%d\n", vD_addr, vB_addr); - putVReg( vD_addr, unop(Iop_RecipEst32Fx4, mkexpr(vB)) ); + putVReg( vD_addr, dnorm_adj_Vector( unop( Iop_RecipEst32Fx4, + dnorm_adj_Vector( mkexpr( vB ) ) ) ) ); return True; case 0x14A: // vrsqrtefp (Reciprocal Sqrt Estimate FP, AV p237) DIP("vrsqrtefp v%d,v%d\n", vD_addr, vB_addr); - putVReg( vD_addr, unop(Iop_RSqrtEst32Fx4, mkexpr(vB)) ); + putVReg( vD_addr, dnorm_adj_Vector( unop( Iop_RSqrtEst32Fx4, + dnorm_adj_Vector( mkexpr( vB ) ) ) ) ); return True; case 0x18A: // vexptefp (2 Raised to the Exp Est FP, AV p173) DIP("vexptefp v%d,v%d\n", vD_addr, vB_addr); DIP(" => not implemented\n"); + /* NOTE, need to address dnormalized value handling when this is + implemented. */ return False; case 0x1CA: // vlogefp (Log2 Estimate FP, AV p175) DIP("vlogefp v%d,v%d\n", vD_addr, vB_addr); DIP(" => not implemented\n"); + /* NOTE, need to address dnormalized value handling when this is + implemented. */ return False; default: @@ -27477,25 +27751,34 @@ static Bool dis_av_fp_cmp ( UInt theInstr ) case 0x0C6: // vcmpeqfp (Compare Equal-to FP, AV p159) DIP("vcmpeqfp%s v%d,v%d,v%d\n", (flag_rC ? ".":""), vD_addr, vA_addr, vB_addr); - assign( vD, binop(Iop_CmpEQ32Fx4, mkexpr(vA), mkexpr(vB)) ); + assign( vD, binop( Iop_CmpEQ32Fx4, + dnorm_adj_Vector( mkexpr( vA ) ), + dnorm_adj_Vector( mkexpr( vB ) ) ) ); break; case 0x1C6: // vcmpgefp (Compare Greater-than-or-Equal-to, AV p163) DIP("vcmpgefp%s v%d,v%d,v%d\n", (flag_rC ? ".":""), vD_addr, vA_addr, vB_addr); - assign( vD, binop(Iop_CmpGE32Fx4, mkexpr(vA), mkexpr(vB)) ); + assign( vD, binop( Iop_CmpGE32Fx4, + dnorm_adj_Vector( mkexpr( vA ) ), + dnorm_adj_Vector( mkexpr( vB ) ) ) ); break; case 0x2C6: // vcmpgtfp (Compare Greater-than FP, AV p164) DIP("vcmpgtfp%s v%d,v%d,v%d\n", (flag_rC ? ".":""), vD_addr, vA_addr, vB_addr); - assign( vD, binop(Iop_CmpGT32Fx4, mkexpr(vA), mkexpr(vB)) ); + assign( vD, binop( Iop_CmpGT32Fx4, + dnorm_adj_Vector( mkexpr( vA ) ), + dnorm_adj_Vector( mkexpr( vB ) ) ) ); break; case 0x3C6: { // vcmpbfp (Compare Bounds FP, AV p157) IRTemp gt = newTemp(Ity_V128); IRTemp lt = newTemp(Ity_V128); IRTemp zeros = newTemp(Ity_V128); + IRTemp srcA = newTemp(Ity_V128); + IRTemp srcB = newTemp(Ity_V128); + DIP("vcmpbfp%s v%d,v%d,v%d\n", (flag_rC ? ".":""), vD_addr, vA_addr, vB_addr); cmp_bounds = True; @@ -27509,13 +27792,17 @@ static Bool dis_av_fp_cmp ( UInt theInstr ) need this for the other compares too (vcmpeqfp etc)... Better still, tighten down the spec for compare irops. */ - assign( gt, unop(Iop_NotV128, - binop(Iop_CmpLE32Fx4, mkexpr(vA), mkexpr(vB))) ); - assign( lt, unop(Iop_NotV128, - binop(Iop_CmpGE32Fx4, mkexpr(vA), - triop(Iop_Sub32Fx4, mkU32(Irrm_NEAREST), - mkexpr(zeros), - mkexpr(vB)))) ); + assign ( srcA, dnorm_adj_Vector( mkexpr( vA ) ) ); + assign ( srcB, dnorm_adj_Vector( mkexpr( vB ) ) ); + + assign( gt, unop( Iop_NotV128, + binop( Iop_CmpLE32Fx4, mkexpr( srcA ), + mkexpr( srcB ) ) ) ); + assign( lt, unop( Iop_NotV128, + binop( Iop_CmpGE32Fx4, mkexpr( srcA ), + triop( Iop_Sub32Fx4, mkU32( Irrm_NEAREST ), + mkexpr( zeros ), + mkexpr( srcB ) ) ) ) ); // finally, just shift gt,lt to correct position assign( vD, binop(Iop_ShlN32x4, @@ -27617,22 +27904,26 @@ static Bool dis_av_fp_convert ( UInt theInstr ) switch (opc2) { case 0x20A: // vrfin (Round to FP Integer Nearest, AV p231) DIP("vrfin v%d,v%d\n", vD_addr, vB_addr); - putVReg( vD_addr, unop(Iop_RoundF32x4_RN, mkexpr(vB)) ); + putVReg( vD_addr, unop(Iop_RoundF32x4_RN, + dnorm_adj_Vector( mkexpr( vB ) ) ) ); break; case 0x24A: // vrfiz (Round to FP Integer toward zero, AV p233) DIP("vrfiz v%d,v%d\n", vD_addr, vB_addr); - putVReg( vD_addr, unop(Iop_RoundF32x4_RZ, mkexpr(vB)) ); + putVReg( vD_addr, unop(Iop_RoundF32x4_RZ, + dnorm_adj_Vector( mkexpr( vB ) ) ) ); break; case 0x28A: // vrfip (Round to FP Integer toward +inf, AV p232) DIP("vrfip v%d,v%d\n", vD_addr, vB_addr); - putVReg( vD_addr, unop(Iop_RoundF32x4_RP, mkexpr(vB)) ); + putVReg( vD_addr, unop(Iop_RoundF32x4_RP, + dnorm_adj_Vector( mkexpr( vB ) ) ) ); break; case 0x2CA: // vrfim (Round to FP Integer toward -inf, AV p230) DIP("vrfim v%d,v%d\n", vD_addr, vB_addr); - putVReg( vD_addr, unop(Iop_RoundF32x4_RM, mkexpr(vB)) ); + putVReg( vD_addr, unop(Iop_RoundF32x4_RM, + dnorm_adj_Vector( mkexpr(vB ) ) ) ); break; default: diff --git a/coregrind/m_dispatch/dispatch-ppc32-linux.S b/coregrind/m_dispatch/dispatch-ppc32-linux.S index 002345d..b679a2e 100644 --- a/coregrind/m_dispatch/dispatch-ppc32-linux.S +++ b/coregrind/m_dispatch/dispatch-ppc32-linux.S @@ -217,7 +217,7 @@ LafterFP2: #ifdef HAS_ALTIVEC vspltisw 3,0x0 /* generate zero */ - mtvscr 3 + mtvscr 3 /* sets VSCR[NJ]=0 */ #endif LafterVMX2: @@ -275,7 +275,8 @@ LafterFP8: beq LafterVMX8 #ifdef HAS_ALTIVEC - /* Check VSCR[NJ] == 1 */ + /* Expect VSCR[NJ] to be 0, call invariant_violation if + VSCR[NJ] == 1 . */ /* first generate 4x 0x00010000 */ vspltisw 4,0x1 /* 4x 0x00000001 */ vspltisw 5,0x0 /* zero */ diff --git a/coregrind/m_dispatch/dispatch-ppc64be-linux.S b/coregrind/m_dispatch/dispatch-ppc64be-linux.S index 27fcc69..9722fd8 100644 --- a/coregrind/m_dispatch/dispatch-ppc64be-linux.S +++ b/coregrind/m_dispatch/dispatch-ppc64be-linux.S @@ -234,7 +234,8 @@ VG_(disp_run_translations): beq .LafterVMX2 vspltisw 3,0x0 /* generate zero */ - mtvscr 3 + mtvscr 3 /* sets VSCR[NJ]=0 */ + .LafterVMX2: /* make a stack frame for the code we are calling */ @@ -284,7 +285,8 @@ VG_(disp_run_translations): cmpldi 11,0 /* Do we have altivec? */ beq .LafterVMX8 - /* Check VSCR[NJ] == 1 */ + /* Expect VSCR[NJ] to be 0, call invariant_violation if + VSCR[NJ] == 1 . */ /* first generate 4x 0x00010000 */ vspltisw 4,0x1 /* 4x 0x00000001 */ vspltisw 5,0x0 /* zero */ @@ -294,7 +296,7 @@ VG_(disp_run_translations): vand 7,7,6 /* gives NJ flag */ vspltw 7,7,0x3 /* flags-word to all lanes */ vcmpequw. 8,6,7 /* CR[24] = 1 if v6 == v7 */ - bt 24,.invariant_violation /* branch if all_equal */ + bt 24,.invariant_violation /* branch if all_equal, i.e. NJ=1 */ .LafterVMX8: /* otherwise we're OK */ diff --git a/coregrind/m_dispatch/dispatch-ppc64le-linux.S b/coregrind/m_dispatch/dispatch-ppc64le-linux.S index a2ad8fc..e790ae8 100644 --- a/coregrind/m_dispatch/dispatch-ppc64le-linux.S +++ b/coregrind/m_dispatch/dispatch-ppc64le-linux.S @@ -255,7 +255,8 @@ VG_(disp_run_translations): beq .LafterVMX2 vspltisw 3,0x0 /* generate zero */ - mtvscr 3 + mtvscr 3 /* sets VSCR[NJ]=0 */ + .LafterVMX2: /* make a stack frame for the code we are calling */ @@ -310,7 +311,8 @@ VG_(disp_run_translations): cmpldi 11,0 /* Do we have altivec? */ beq .LafterVMX8 - /* Check VSCR[NJ] == 1 */ + /* Expect VSCR[NJ] to be 0, call invariant_violation if + VSCR[NJ] == 1 . */ /* first generate 4x 0x00010000 */ vspltisw 4,0x1 /* 4x 0x00000001 */ vspltisw 5,0x0 /* zero */ @@ -320,7 +322,7 @@ VG_(disp_run_translations): vand 7,7,6 /* gives NJ flag */ vspltw 7,7,0x3 /* flags-word to all lanes */ vcmpequw. 8,6,7 /* CR[24] = 1 if v6 == v7 */ - bt 24,.invariant_violation /* branch if all_equal */ + bt 24,.invariant_violation /* branch if all_equal, i.e. NJ=1 */ .LafterVMX8: /* otherwise we're OK */ |
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From: Andreas A. <ar...@so...> - 2019-05-28 16:36:55
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=c39ee0c37082e2d1723a8671fca2b3af029e2712 commit c39ee0c37082e2d1723a8671fca2b3af029e2712 Author: Andreas Arnez <ar...@li...> Date: Thu May 23 17:17:43 2019 +0200 Bug 407764 - s390x: drd fails on z13 due to function wrapping issue The s390x-specific inline assembly macros for function wrapping in include/valgrind.h have a few issues. When the compiler uses vector registers, such as with "-march=z13", all vector registers must be declared as clobbered by the callee. Because this is missing, many drd test failures are seen with "-march=z13". Also, the inline assemblies write the return value into the target register before restoring r11. If r11 is used as the target register, this means that the restore operation corrupts the result. This bug causes failures with memcheck's "wrap6" test case. These bugs are fixed. The clobber list is extended by the vector registers (if appropriate), and the target register is now written at the end, after restoring r11. Diff: --- NEWS | 1 + include/valgrind.h | 38 +++++++++++++++++++++++--------------- 2 files changed, 24 insertions(+), 15 deletions(-) diff --git a/NEWS b/NEWS index ba0f128..53c92ce 100644 --- a/NEWS +++ b/NEWS @@ -51,6 +51,7 @@ where XXXXXX is the bug number as listed below. 406824 Unsupported baseline 407218 Add support for the copy_file_range syscall 407307 Intercept stpcpy also in ld.so for arm64 +407764 drd cond_post_wait gets wrong (?) condition on s390x z13 system n-i-bz Fix minor one time leaks in dhat. n-i-bz Add --run-cxx-freeres=no in outer args to avoid inner crashes. diff --git a/include/valgrind.h b/include/valgrind.h index f071bd3..815efa8 100644 --- a/include/valgrind.h +++ b/include/valgrind.h @@ -4687,8 +4687,16 @@ typedef r14 in s390_irgen_noredir (VEX/priv/guest_s390_irgen.c) to give the function a proper return address. All others are ABI defined call clobbers. */ -#define __CALLER_SAVED_REGS "0","1","2","3","4","5","14", \ - "f0","f1","f2","f3","f4","f5","f6","f7" +#if defined(__VX__) || defined(__S390_VX__) +#define __CALLER_SAVED_REGS "0", "1", "2", "3", "4", "5", "14", \ + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" +#else +#define __CALLER_SAVED_REGS "0", "1", "2", "3", "4", "5", "14", \ + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7" +#endif /* Nb: Although r11 is modified in the asm snippets below (inside VALGRIND_CFI_PROLOGUE) it is not listed in the clobber section, for @@ -4710,9 +4718,9 @@ typedef "aghi 15,-160\n\t" \ "lg 1, 0(1)\n\t" /* target->r1 */ \ VALGRIND_CALL_NOREDIR_R1 \ - "lgr %0, 2\n\t" \ "aghi 15,160\n\t" \ VALGRIND_CFI_EPILOGUE \ + "lgr %0, 2\n\t" \ : /*out*/ "=d" (_res) \ : /*in*/ "d" (&_argvec[0]) __FRAME_POINTER \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \ @@ -4734,9 +4742,9 @@ typedef "lg 2, 8(1)\n\t" \ "lg 1, 0(1)\n\t" \ VALGRIND_CALL_NOREDIR_R1 \ - "lgr %0, 2\n\t" \ "aghi 15,160\n\t" \ VALGRIND_CFI_EPILOGUE \ + "lgr %0, 2\n\t" \ : /*out*/ "=d" (_res) \ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \ @@ -4759,9 +4767,9 @@ typedef "lg 3,16(1)\n\t" \ "lg 1, 0(1)\n\t" \ VALGRIND_CALL_NOREDIR_R1 \ - "lgr %0, 2\n\t" \ "aghi 15,160\n\t" \ VALGRIND_CFI_EPILOGUE \ + "lgr %0, 2\n\t" \ : /*out*/ "=d" (_res) \ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \ @@ -4786,9 +4794,9 @@ typedef "lg 4,24(1)\n\t" \ "lg 1, 0(1)\n\t" \ VALGRIND_CALL_NOREDIR_R1 \ - "lgr %0, 2\n\t" \ "aghi 15,160\n\t" \ VALGRIND_CFI_EPILOGUE \ + "lgr %0, 2\n\t" \ : /*out*/ "=d" (_res) \ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \ @@ -4815,9 +4823,9 @@ typedef "lg 5,32(1)\n\t" \ "lg 1, 0(1)\n\t" \ VALGRIND_CALL_NOREDIR_R1 \ - "lgr %0, 2\n\t" \ "aghi 15,160\n\t" \ VALGRIND_CFI_EPILOGUE \ + "lgr %0, 2\n\t" \ : /*out*/ "=d" (_res) \ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7" \ @@ -4846,9 +4854,9 @@ typedef "lg 6,40(1)\n\t" \ "lg 1, 0(1)\n\t" \ VALGRIND_CALL_NOREDIR_R1 \ - "lgr %0, 2\n\t" \ "aghi 15,160\n\t" \ VALGRIND_CFI_EPILOGUE \ + "lgr %0, 2\n\t" \ : /*out*/ "=d" (_res) \ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \ @@ -4880,9 +4888,9 @@ typedef "mvc 160(8,15), 48(1)\n\t" \ "lg 1, 0(1)\n\t" \ VALGRIND_CALL_NOREDIR_R1 \ - "lgr %0, 2\n\t" \ "aghi 15,168\n\t" \ VALGRIND_CFI_EPILOGUE \ + "lgr %0, 2\n\t" \ : /*out*/ "=d" (_res) \ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \ @@ -4916,9 +4924,9 @@ typedef "mvc 168(8,15), 56(1)\n\t" \ "lg 1, 0(1)\n\t" \ VALGRIND_CALL_NOREDIR_R1 \ - "lgr %0, 2\n\t" \ "aghi 15,176\n\t" \ VALGRIND_CFI_EPILOGUE \ + "lgr %0, 2\n\t" \ : /*out*/ "=d" (_res) \ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \ @@ -4954,9 +4962,9 @@ typedef "mvc 176(8,15), 64(1)\n\t" \ "lg 1, 0(1)\n\t" \ VALGRIND_CALL_NOREDIR_R1 \ - "lgr %0, 2\n\t" \ "aghi 15,184\n\t" \ VALGRIND_CFI_EPILOGUE \ + "lgr %0, 2\n\t" \ : /*out*/ "=d" (_res) \ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \ @@ -4994,9 +5002,9 @@ typedef "mvc 184(8,15), 72(1)\n\t" \ "lg 1, 0(1)\n\t" \ VALGRIND_CALL_NOREDIR_R1 \ - "lgr %0, 2\n\t" \ "aghi 15,192\n\t" \ VALGRIND_CFI_EPILOGUE \ + "lgr %0, 2\n\t" \ : /*out*/ "=d" (_res) \ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \ @@ -5036,9 +5044,9 @@ typedef "mvc 192(8,15), 80(1)\n\t" \ "lg 1, 0(1)\n\t" \ VALGRIND_CALL_NOREDIR_R1 \ - "lgr %0, 2\n\t" \ "aghi 15,200\n\t" \ VALGRIND_CFI_EPILOGUE \ + "lgr %0, 2\n\t" \ : /*out*/ "=d" (_res) \ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \ @@ -5080,9 +5088,9 @@ typedef "mvc 200(8,15), 88(1)\n\t" \ "lg 1, 0(1)\n\t" \ VALGRIND_CALL_NOREDIR_R1 \ - "lgr %0, 2\n\t" \ "aghi 15,208\n\t" \ VALGRIND_CFI_EPILOGUE \ + "lgr %0, 2\n\t" \ : /*out*/ "=d" (_res) \ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \ @@ -5126,9 +5134,9 @@ typedef "mvc 208(8,15), 96(1)\n\t" \ "lg 1, 0(1)\n\t" \ VALGRIND_CALL_NOREDIR_R1 \ - "lgr %0, 2\n\t" \ "aghi 15,216\n\t" \ VALGRIND_CFI_EPILOGUE \ + "lgr %0, 2\n\t" \ : /*out*/ "=d" (_res) \ : /*in*/ "a" (&_argvec[0]) __FRAME_POINTER \ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \ |
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From: Mark W. <ma...@so...> - 2019-05-28 16:14:16
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=791c0ba910f210f09646add24c34faa9ba4b162d commit 791c0ba910f210f09646add24c34faa9ba4b162d Author: Mark Wielaard <ma...@kl...> Date: Mon May 27 20:31:35 2019 +0200 ppc64: Arguments to iselInt128Expr_to_32x4 should be initialized. Make sure to initialize the arguments to iselInt128Expr_to_32x4. iselInt128Expr_to_32x4 will check that iselInt128Expr_to_32x4_wrk has assigned the correct type of values to the arguments. But if the arguments were never initialized it might not be able to when iselInt128Expr_to_32x4_wrk was unable to assign a value. Reviewed-by: Carl Love <ce...@us...> Diff: --- VEX/priv/host_ppc_isel.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c index 68cb503..e05145c 100644 --- a/VEX/priv/host_ppc_isel.c +++ b/VEX/priv/host_ppc_isel.c @@ -6537,7 +6537,10 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt, IREndness IEndianess ) return; } if (!mode64 && ty == Ity_I128) { - HReg r_srcHi, r_srcMedHi, r_srcMedLo, r_srcLo; + HReg r_srcHi = INVALID_HREG; + HReg r_srcMedHi = INVALID_HREG; + HReg r_srcMedLo = INVALID_HREG; + HReg r_srcLo = INVALID_HREG; HReg r_dstHi, r_dstMedHi, r_dstMedLo, r_dstLo; iselInt128Expr_to_32x4(&r_srcHi, &r_srcMedHi, |
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From: Mark W. <ma...@so...> - 2019-05-28 16:12:18
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=a82b92e2ebfdd84ac953b05f679c67834942062b commit a82b92e2ebfdd84ac953b05f679c67834942062b Author: Mark Wielaard <ma...@kl...> Date: Tue May 28 17:20:31 2019 +0200 Fix coding nit in x86amd64g_calculate_FXTRACT. The current code "return getExp ? posInf : posInf;" looks like a typo. But when the argument is positive infinity then both the significand and the exponent are positive infinity (there is a fxtract testcase that checks that). So no need to check getExp. Just always return posInf if arg == posInf, but add a comment explaining why. Diff: --- VEX/priv/guest_generic_x87.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VEX/priv/guest_generic_x87.c b/VEX/priv/guest_generic_x87.c index 1e76395..85ebebd 100644 --- a/VEX/priv/guest_generic_x87.c +++ b/VEX/priv/guest_generic_x87.c @@ -453,7 +453,7 @@ ULong x86amd64g_calculate_FXTRACT ( ULong arg, HWord getExp ) /* Mimic Core i5 behaviour for special cases. */ if (arg == posInf) - return getExp ? posInf : posInf; + return posInf; /* Both significand and exponent are posInf. */ if (arg == negInf) return getExp ? posInf : negInf; if ((arg & nanMask) == nanMask) |
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From: Mark W. <ma...@kl...> - 2019-05-28 08:11:33
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On Mon, 2019-05-27 at 19:03 -0700, John Reiser wrote:
> > So explicitly don't assign a value. Then the compiler will
> > warn if we
> > would ever forget to assign it a value value later on before
> > using it.
>
> That's too optimistic; the compiler is not that good.
> Yes, the compiler usually catches such mistakes,
> but sometimes it does not. For instance, the BEAM
> static analysis tool ("Bugs, Errors, And Mistakes")
> does report uses of uninitialized variables
> that "ordinary" compilers do not notice.
Yeah, Julian pointed out the same on irc. I am probably too optimistic
about the data flow analysis of compilers. In this particular case it
really is that simple for the compiler to notice though. Since the code
is a simple exhaustive switch case after which the variables are
immediately checked. I did test that part with various gcc versions
(forget to handle it in any switch case, and you do get a
warning/error). But I'll not change any other code.
Cheers,
Mark
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From: John R. <jr...@bi...> - 2019-05-28 02:04:11
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> So explicitly don't assign a value. Then the compiler will warn if we
> would ever forget to assign it a value value later on before using it.
That's too optimistic; the compiler is not that good.
Yes, the compiler usually catches such mistakes,
but sometimes it does not. For instance, the BEAM
static analysis tool ("Bugs, Errors, And Mistakes")
does report uses of uninitialized variables
that "ordinary" compilers do not notice.
For a hack: make it easy to switch between uninitialized an initialized.
Uninitialized probably is better for development, in order to take
advantage of "pretty good" compiler. But initialized is better
for a shipping product, because a 100% reproducible bug is MUCH better
(easier and faster to find and fix) than an intermittent bug.
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