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From: Petar J. <pe...@so...> - 2019-03-27 18:43:21
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=92ecddd13ea52003c0c8fd0a3300411005c8d6b3 commit 92ecddd13ea52003c0c8fd0a3300411005c8d6b3 Author: Petar Jovanovic <mip...@gm...> Date: Wed Mar 27 18:42:05 2019 +0000 mips: code refactoring (NFC) Code in VEX/priv/guest_mips_toIR.c is notably refactored. DSP ASE dissasembly has been put in a separate file: guest_mipsdsp_toIR.c. Patch by Aleksandar Rikalo. Diff: --- Makefile.vex.am | 2 + VEX/Makefile-gcc | 6 + VEX/priv/guest_mips_toIR.c | 52141 +++++++++++++++++----------------------- VEX/priv/guest_mipsdsp_toIR.c | 9688 ++++++++ VEX/priv/mips_defs.h | 421 + 5 files changed, 32047 insertions(+), 30211 deletions(-) diff --git a/Makefile.vex.am b/Makefile.vex.am index 2b54b8a..10e1890 100644 --- a/Makefile.vex.am +++ b/Makefile.vex.am @@ -47,6 +47,7 @@ noinst_HEADERS = \ priv/guest_arm64_defs.h \ priv/guest_s390_defs.h \ priv/guest_mips_defs.h \ + priv/mips_defs.h \ priv/host_generic_regs.h \ priv/host_generic_simd64.h \ priv/host_generic_simd128.h \ @@ -143,6 +144,7 @@ LIBVEX_SOURCES_COMMON = \ priv/guest_s390_helpers.c \ priv/guest_s390_toIR.c \ priv/guest_mips_helpers.c \ + priv/guest_mipsdsp_toIR.c \ priv/guest_mips_toIR.c \ priv/host_generic_regs.c \ priv/host_generic_simd64.c \ diff --git a/VEX/Makefile-gcc b/VEX/Makefile-gcc index 0822712..0b94e13 100644 --- a/VEX/Makefile-gcc +++ b/VEX/Makefile-gcc @@ -34,6 +34,7 @@ PRIV_HEADERS = priv/host_x86_defs.h \ priv/guest_arm_defs.h \ priv/guest_ppc_defs.h \ priv/guest_mips_defs.h \ + priv/mips_defs.h \ priv/s390_disasm.h \ priv/s390_defs.h \ priv/ir_match.h \ @@ -82,6 +83,7 @@ LIB_OBJS = priv/ir_defs.o \ priv/guest_arm64_toIR.o \ priv/guest_ppc_toIR.o \ priv/guest_s390_toIR.o \ + priv/guest_mipsdsp_toIR.o \ priv/guest_mips_toIR.o PUB_INCLUDES = -Ipub @@ -409,6 +411,10 @@ priv/guest_mips_helpers.o: $(ALL_HEADERS) priv/guest_mips_helpers.c $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest_mips_helpers.o \ -c priv/guest_mips_helpers.c +priv/guest_mipsdsp_toIR.o: $(ALL_HEADERS) priv/guest_mipsdsp_toIR.c + $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest_mipsdsp_toIR.o \ + -c priv/guest_mipsdsp_toIR.c + priv/guest_mips_toIR.o: $(ALL_HEADERS) priv/guest_mips_toIR.c $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest_mips_toIR.o \ -c priv/guest_mips_toIR.c diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c old mode 100644 new mode 100755 index 4748ba4..eb437ec --- a/VEX/priv/guest_mips_toIR.c +++ b/VEX/priv/guest_mips_toIR.c @@ -40,6 +40,7 @@ #include "main_globals.h" #include "guest_generic_bb_to_IR.h" #include "guest_mips_defs.h" +#include "mips_defs.h" /*------------------------------------------------------------*/ /*--- Globals ---*/ @@ -55,7 +56,7 @@ static VexEndness host_endness; /* Pointer to the guest code area. */ -static const UChar *guest_code; +const UChar *guest_code; /* CONST: The guest address for the instruction currently being translated. */ @@ -66,14 +67,14 @@ static Addr64 guest_PC_curr_instr; #endif /* MOD: The IRSB* into which we're generating code. */ -static IRSB *irsb; +IRSB *irsb; /* Is our guest binary 32 or 64bit? Set at each call to disInstr_MIPS below. */ -static Bool mode64 = False; +Bool mode64 = False; /* CPU has FPU and 32 dbl. prec. FP registers. */ -static Bool fp_mode64 = False; + static Bool fp_mode64 = False; /* FPU works in FRE mode */ static Bool fp_mode64_fre = False; @@ -86,14 +87,6 @@ static Bool has_msa = False; #define ONE_DOUBLE 0x3FF0000000000000ULL /*------------------------------------------------------------*/ -/*--- Debugging output ---*/ -/*------------------------------------------------------------*/ - -#define DIP(format, args...) \ - if (vex_traceflags & VEX_TRACE_FE) \ - vex_printf(format, ## args) - -/*------------------------------------------------------------*/ /*--- Helper bits and pieces for deconstructing the ---*/ /*--- mips insn stream. ---*/ /*------------------------------------------------------------*/ @@ -106,12812 +99,6014 @@ static UInt integerGuestRegOffset(UInt iregNo) registers are accessed, but I don't think that ever happens on MIPS. */ UInt ret; - if (!mode64) - switch (iregNo) { - case 0: - ret = offsetof(VexGuestMIPS32State, guest_r0); break; - case 1: - ret = offsetof(VexGuestMIPS32State, guest_r1); break; - case 2: - ret = offsetof(VexGuestMIPS32State, guest_r2); break; - case 3: - ret = offsetof(VexGuestMIPS32State, guest_r3); break; - case 4: - ret = offsetof(VexGuestMIPS32State, guest_r4); break; - case 5: - ret = offsetof(VexGuestMIPS32State, guest_r5); break; - case 6: - ret = offsetof(VexGuestMIPS32State, guest_r6); break; - case 7: - ret = offsetof(VexGuestMIPS32State, guest_r7); break; - case 8: - ret = offsetof(VexGuestMIPS32State, guest_r8); break; - case 9: - ret = offsetof(VexGuestMIPS32State, guest_r9); break; - case 10: - ret = offsetof(VexGuestMIPS32State, guest_r10); break; - case 11: - ret = offsetof(VexGuestMIPS32State, guest_r11); break; - case 12: - ret = offsetof(VexGuestMIPS32State, guest_r12); break; - case 13: - ret = offsetof(VexGuestMIPS32State, guest_r13); break; - case 14: - ret = offsetof(VexGuestMIPS32State, guest_r14); break; - case 15: - ret = offsetof(VexGuestMIPS32State, guest_r15); break; - case 16: - ret = offsetof(VexGuestMIPS32State, guest_r16); break; - case 17: - ret = offsetof(VexGuestMIPS32State, guest_r17); break; - case 18: - ret = offsetof(VexGuestMIPS32State, guest_r18); break; - case 19: - ret = offsetof(VexGuestMIPS32State, guest_r19); break; - case 20: - ret = offsetof(VexGuestMIPS32State, guest_r20); break; - case 21: - ret = offsetof(VexGuestMIPS32State, guest_r21); break; - case 22: - ret = offsetof(VexGuestMIPS32State, guest_r22); break; - case 23: - ret = offsetof(VexGuestMIPS32State, guest_r23); break; - case 24: - ret = offsetof(VexGuestMIPS32State, guest_r24); break; - case 25: - ret = offsetof(VexGuestMIPS32State, guest_r25); break; - case 26: - ret = offsetof(VexGuestMIPS32State, guest_r26); break; - case 27: - ret = offsetof(VexGuestMIPS32State, guest_r27); break; - case 28: - ret = offsetof(VexGuestMIPS32State, guest_r28); break; - case 29: - ret = offsetof(VexGuestMIPS32State, guest_r29); break; - case 30: - ret = offsetof(VexGuestMIPS32State, guest_r30); break; - case 31: - ret = offsetof(VexGuestMIPS32State, guest_r31); break; - default: - vassert(0); - break; - } - else - switch (iregNo) { - case 0: - ret = offsetof(VexGuestMIPS64State, guest_r0); break; - case 1: - ret = offsetof(VexGuestMIPS64State, guest_r1); break; - case 2: - ret = offsetof(VexGuestMIPS64State, guest_r2); break; - case 3: - ret = offsetof(VexGuestMIPS64State, guest_r3); break; - case 4: - ret = offsetof(VexGuestMIPS64State, guest_r4); break; - case 5: - ret = offsetof(VexGuestMIPS64State, guest_r5); break; - case 6: - ret = offsetof(VexGuestMIPS64State, guest_r6); break; - case 7: - ret = offsetof(VexGuestMIPS64State, guest_r7); break; - case 8: - ret = offsetof(VexGuestMIPS64State, guest_r8); break; - case 9: - ret = offsetof(VexGuestMIPS64State, guest_r9); break; - case 10: - ret = offsetof(VexGuestMIPS64State, guest_r10); break; - case 11: - ret = offsetof(VexGuestMIPS64State, guest_r11); break; - case 12: - ret = offsetof(VexGuestMIPS64State, guest_r12); break; - case 13: - ret = offsetof(VexGuestMIPS64State, guest_r13); break; - case 14: - ret = offsetof(VexGuestMIPS64State, guest_r14); break; - case 15: - ret = offsetof(VexGuestMIPS64State, guest_r15); break; - case 16: - ret = offsetof(VexGuestMIPS64State, guest_r16); break; - case 17: - ret = offsetof(VexGuestMIPS64State, guest_r17); break; - case 18: - ret = offsetof(VexGuestMIPS64State, guest_r18); break; - case 19: - ret = offsetof(VexGuestMIPS64State, guest_r19); break; - case 20: - ret = offsetof(VexGuestMIPS64State, guest_r20); break; - case 21: - ret = offsetof(VexGuestMIPS64State, guest_r21); break; - case 22: - ret = offsetof(VexGuestMIPS64State, guest_r22); break; - case 23: - ret = offsetof(VexGuestMIPS64State, guest_r23); break; - case 24: - ret = offsetof(VexGuestMIPS64State, guest_r24); break; - case 25: - ret = offsetof(VexGuestMIPS64State, guest_r25); break; - case 26: - ret = offsetof(VexGuestMIPS64State, guest_r26); break; - case 27: - ret = offsetof(VexGuestMIPS64State, guest_r27); break; - case 28: - ret = offsetof(VexGuestMIPS64State, guest_r28); break; - case 29: - ret = offsetof(VexGuestMIPS64State, guest_r29); break; - case 30: - ret = offsetof(VexGuestMIPS64State, guest_r30); break; - case 31: - ret = offsetof(VexGuestMIPS64State, guest_r31); break; - default: - vassert(0); - break; - } - return ret; -} - -#if defined(VGP_mips32_linux) -#define OFFB_PC offsetof(VexGuestMIPS32State, guest_PC) -#else -#define OFFB_PC offsetof(VexGuestMIPS64State, guest_PC) -#endif -/* ---------------- Floating point registers ---------------- */ - -static UInt floatGuestRegOffset(UInt fregNo) -{ - vassert(fregNo < 32); - UInt ret; if (!mode64) - switch (fregNo) { - case 0: - ret = offsetof(VexGuestMIPS32State, guest_f0); break; - case 1: - ret = offsetof(VexGuestMIPS32State, guest_f1); break; - case 2: - ret = offsetof(VexGuestMIPS32State, guest_f2); break; - case 3: - ret = offsetof(VexGuestMIPS32State, guest_f3); break; - case 4: - ret = offsetof(VexGuestMIPS32State, guest_f4); break; - case 5: - ret = offsetof(VexGuestMIPS32State, guest_f5); break; - case 6: - ret = offsetof(VexGuestMIPS32State, guest_f6); break; - case 7: - ret = offsetof(VexGuestMIPS32State, guest_f7); break; - case 8: - ret = offsetof(VexGuestMIPS32State, guest_f8); break; - case 9: - ret = offsetof(VexGuestMIPS32State, guest_f9); break; - case 10: - ret = offsetof(VexGuestMIPS32State, guest_f10); break; - case 11: - ret = offsetof(VexGuestMIPS32State, guest_f11); break; - case 12: - ret = offsetof(VexGuestMIPS32State, guest_f12); break; - case 13: - ret = offsetof(VexGuestMIPS32State, guest_f13); break; - case 14: - ret = offsetof(VexGuestMIPS32State, guest_f14); break; - case 15: - ret = offsetof(VexGuestMIPS32State, guest_f15); break; - case 16: - ret = offsetof(VexGuestMIPS32State, guest_f16); break; - case 17: - ret = offsetof(VexGuestMIPS32State, guest_f17); break; - case 18: - ret = offsetof(VexGuestMIPS32State, guest_f18); break; - case 19: - ret = offsetof(VexGuestMIPS32State, guest_f19); break; - case 20: - ret = offsetof(VexGuestMIPS32State, guest_f20); break; - case 21: - ret = offsetof(VexGuestMIPS32State, guest_f21); break; - case 22: - ret = offsetof(VexGuestMIPS32State, guest_f22); break; - case 23: - ret = offsetof(VexGuestMIPS32State, guest_f23); break; - case 24: - ret = offsetof(VexGuestMIPS32State, guest_f24); break; - case 25: - ret = offsetof(VexGuestMIPS32State, guest_f25); break; - case 26: - ret = offsetof(VexGuestMIPS32State, guest_f26); break; - case 27: - ret = offsetof(VexGuestMIPS32State, guest_f27); break; - case 28: - ret = offsetof(VexGuestMIPS32State, guest_f28); break; - case 29: - ret = offsetof(VexGuestMIPS32State, guest_f29); break; - case 30: - ret = offsetof(VexGuestMIPS32State, guest_f30); break; - case 31: - ret = offsetof(VexGuestMIPS32State, guest_f31); break; - default: - vassert(0); - break; - } - else - switch (fregNo) { - case 0: - ret = offsetof(VexGuestMIPS64State, guest_f0); break; - case 1: - ret = offsetof(VexGuestMIPS64State, guest_f1); break; - case 2: - ret = offsetof(VexGuestMIPS64State, guest_f2); break; - case 3: - ret = offsetof(VexGuestMIPS64State, guest_f3); break; - case 4: - ret = offsetof(VexGuestMIPS64State, guest_f4); break; - case 5: - ret = offsetof(VexGuestMIPS64State, guest_f5); break; - case 6: - ret = offsetof(VexGuestMIPS64State, guest_f6); break; - case 7: - ret = offsetof(VexGuestMIPS64State, guest_f7); break; - case 8: - ret = offsetof(VexGuestMIPS64State, guest_f8); break; - case 9: - ret = offsetof(VexGuestMIPS64State, guest_f9); break; - case 10: - ret = offsetof(VexGuestMIPS64State, guest_f10); break; - case 11: - ret = offsetof(VexGuestMIPS64State, guest_f11); break; - case 12: - ret = offsetof(VexGuestMIPS64State, guest_f12); break; - case 13: - ret = offsetof(VexGuestMIPS64State, guest_f13); break; - case 14: - ret = offsetof(VexGuestMIPS64State, guest_f14); break; - case 15: - ret = offsetof(VexGuestMIPS64State, guest_f15); break; - case 16: - ret = offsetof(VexGuestMIPS64State, guest_f16); break; - case 17: - ret = offsetof(VexGuestMIPS64State, guest_f17); break; - case 18: - ret = offsetof(VexGuestMIPS64State, guest_f18); break; - case 19: - ret = offsetof(VexGuestMIPS64State, guest_f19); break; - case 20: - ret = offsetof(VexGuestMIPS64State, guest_f20); break; - case 21: - ret = offsetof(VexGuestMIPS64State, guest_f21); break; - case 22: - ret = offsetof(VexGuestMIPS64State, guest_f22); break; - case 23: - ret = offsetof(VexGuestMIPS64State, guest_f23); break; - case 24: - ret = offsetof(VexGuestMIPS64State, guest_f24); break; - case 25: - ret = offsetof(VexGuestMIPS64State, guest_f25); break; - case 26: - ret = offsetof(VexGuestMIPS64State, guest_f26); break; - case 27: - ret = offsetof(VexGuestMIPS64State, guest_f27); break; - case 28: - ret = offsetof(VexGuestMIPS64State, guest_f28); break; - case 29: - ret = offsetof(VexGuestMIPS64State, guest_f29); break; - case 30: - ret = offsetof(VexGuestMIPS64State, guest_f30); break; - case 31: - ret = offsetof(VexGuestMIPS64State, guest_f31); break; - default: - vassert(0); - break; - } - return ret; -} - -/* ---------------- MIPS32 DSP ASE(r2) accumulators ---------------- */ - -static UInt accumulatorGuestRegOffset(UInt acNo) -{ - vassert(!mode64); - vassert(acNo <= 3); - UInt ret; - switch (acNo) { - case 0: - ret = offsetof(VexGuestMIPS32State, guest_ac0); break; - case 1: - ret = offsetof(VexGuestMIPS32State, guest_ac1); break; - case 2: - ret = offsetof(VexGuestMIPS32State, guest_ac2); break; - case 3: - ret = offsetof(VexGuestMIPS32State, guest_ac3); break; - default: - vassert(0); - break; - } - return ret; -} - -/* ---------------- MIPS32 MSA registers ---------------- */ - -static UInt msaGuestRegOffset(UInt msaRegNo) { - vassert(msaRegNo <= 31); - UInt ret; - - if (mode64) { - switch (msaRegNo) { + switch (iregNo) { case 0: - ret = offsetof(VexGuestMIPS64State, guest_w0); + ret = offsetof(VexGuestMIPS32State, guest_r0); break; case 1: - ret = offsetof(VexGuestMIPS64State, guest_w1); + ret = offsetof(VexGuestMIPS32State, guest_r1); break; case 2: - ret = offsetof(VexGuestMIPS64State, guest_w2); + ret = offsetof(VexGuestMIPS32State, guest_r2); break; case 3: - ret = offsetof(VexGuestMIPS64State, guest_w3); + ret = offsetof(VexGuestMIPS32State, guest_r3); break; case 4: - ret = offsetof(VexGuestMIPS64State, guest_w4); + ret = offsetof(VexGuestMIPS32State, guest_r4); break; case 5: - ret = offsetof(VexGuestMIPS64State, guest_w5); + ret = offsetof(VexGuestMIPS32State, guest_r5); break; case 6: - ret = offsetof(VexGuestMIPS64State, guest_w6); + ret = offsetof(VexGuestMIPS32State, guest_r6); break; case 7: - ret = offsetof(VexGuestMIPS64State, guest_w7); + ret = offsetof(VexGuestMIPS32State, guest_r7); break; case 8: - ret = offsetof(VexGuestMIPS64State, guest_w8); + ret = offsetof(VexGuestMIPS32State, guest_r8); break; case 9: - ret = offsetof(VexGuestMIPS64State, guest_w9); + ret = offsetof(VexGuestMIPS32State, guest_r9); break; case 10: - ret = offsetof(VexGuestMIPS64State, guest_w10); + ret = offsetof(VexGuestMIPS32State, guest_r10); break; case 11: - ret = offsetof(VexGuestMIPS64State, guest_w11); + ret = offsetof(VexGuestMIPS32State, guest_r11); break; case 12: - ret = offsetof(VexGuestMIPS64State, guest_w12); + ret = offsetof(VexGuestMIPS32State, guest_r12); break; case 13: - ret = offsetof(VexGuestMIPS64State, guest_w13); + ret = offsetof(VexGuestMIPS32State, guest_r13); break; case 14: - ret = offsetof(VexGuestMIPS64State, guest_w14); + ret = offsetof(VexGuestMIPS32State, guest_r14); break; case 15: - ret = offsetof(VexGuestMIPS64State, guest_w15); + ret = offsetof(VexGuestMIPS32State, guest_r15); break; case 16: - ret = offsetof(VexGuestMIPS64State, guest_w16); + ret = offsetof(VexGuestMIPS32State, guest_r16); break; case 17: - ret = offsetof(VexGuestMIPS64State, guest_w17); + ret = offsetof(VexGuestMIPS32State, guest_r17); break; case 18: - ret = offsetof(VexGuestMIPS64State, guest_w18); + ret = offsetof(VexGuestMIPS32State, guest_r18); break; case 19: - ret = offsetof(VexGuestMIPS64State, guest_w19); + ret = offsetof(VexGuestMIPS32State, guest_r19); break; case 20: - ret = offsetof(VexGuestMIPS64State, guest_w20); + ret = offsetof(VexGuestMIPS32State, guest_r20); break; case 21: - ret = offsetof(VexGuestMIPS64State, guest_w21); + ret = offsetof(VexGuestMIPS32State, guest_r21); break; case 22: - ret = offsetof(VexGuestMIPS64State, guest_w22); + ret = offsetof(VexGuestMIPS32State, guest_r22); break; case 23: - ret = offsetof(VexGuestMIPS64State, guest_w23); + ret = offsetof(VexGuestMIPS32State, guest_r23); break; case 24: - ret = offsetof(VexGuestMIPS64State, guest_w24); + ret = offsetof(VexGuestMIPS32State, guest_r24); break; case 25: - ret = offsetof(VexGuestMIPS64State, guest_w25); + ret = offsetof(VexGuestMIPS32State, guest_r25); break; case 26: - ret = offsetof(VexGuestMIPS64State, guest_w26); + ret = offsetof(VexGuestMIPS32State, guest_r26); break; case 27: - ret = offsetof(VexGuestMIPS64State, guest_w27); + ret = offsetof(VexGuestMIPS32State, guest_r27); break; case 28: - ret = offsetof(VexGuestMIPS64State, guest_w28); + ret = offsetof(VexGuestMIPS32State, guest_r28); break; case 29: - ret = offsetof(VexGuestMIPS64State, guest_w29); + ret = offsetof(VexGuestMIPS32State, guest_r29); break; case 30: - ret = offsetof(VexGuestMIPS64State, guest_w30); + ret = offsetof(VexGuestMIPS32State, guest_r30); break; case 31: - ret = offsetof(VexGuestMIPS64State, guest_w31); + ret = offsetof(VexGuestMIPS32State, guest_r31); break; default: vassert(0); break; } - } else { - switch (msaRegNo) { + else + switch (iregNo) { case 0: - ret = offsetof(VexGuestMIPS32State, guest_w0); + ret = offsetof(VexGuestMIPS64State, guest_r0); break; case 1: - ret = offsetof(VexGuestMIPS32State, guest_w1); + ret = offsetof(VexGuestMIPS64State, guest_r1); break; case 2: - ret = offsetof(VexGuestMIPS32State, guest_w2); + ret = offsetof(VexGuestMIPS64State, guest_r2); break; case 3: - ret = offsetof(VexGuestMIPS32State, guest_w3); + ret = offsetof(VexGuestMIPS64State, guest_r3); break; case 4: - ret = offsetof(VexGuestMIPS32State, guest_w4); + ret = offsetof(VexGuestMIPS64State, guest_r4); break; case 5: - ret = offsetof(VexGuestMIPS32State, guest_w5); + ret = offsetof(VexGuestMIPS64State, guest_r5); break; case 6: - ret = offsetof(VexGuestMIPS32State, guest_w6); + ret = offsetof(VexGuestMIPS64State, guest_r6); break; case 7: - ret = offsetof(VexGuestMIPS32State, guest_w7); + ret = offsetof(VexGuestMIPS64State, guest_r7); break; case 8: - ret = offsetof(VexGuestMIPS32State, guest_w8); + ret = offsetof(VexGuestMIPS64State, guest_r8); break; case 9: - ret = offsetof(VexGuestMIPS32State, guest_w9); + ret = offsetof(VexGuestMIPS64State, guest_r9); break; case 10: - ret = offsetof(VexGuestMIPS32State, guest_w10); + ret = offsetof(VexGuestMIPS64State, guest_r10); break; case 11: - ret = offsetof(VexGuestMIPS32State, guest_w11); + ret = offsetof(VexGuestMIPS64State, guest_r11); break; case 12: - ret = offsetof(VexGuestMIPS32State, guest_w12); + ret = offsetof(VexGuestMIPS64State, guest_r12); break; case 13: - ret = offsetof(VexGuestMIPS32State, guest_w13); + ret = offsetof(VexGuestMIPS64State, guest_r13); break; case 14: - ret = offsetof(VexGuestMIPS32State, guest_w14); + ret = offsetof(VexGuestMIPS64State, guest_r14); break; case 15: - ret = offsetof(VexGuestMIPS32State, guest_w15); + ret = offsetof(VexGuestMIPS64State, guest_r15); break; case 16: - ret = offsetof(VexGuestMIPS32State, guest_w16); + ret = offsetof(VexGuestMIPS64State, guest_r16); break; case 17: - ret = offsetof(VexGuestMIPS32State, guest_w17); + ret = offsetof(VexGuestMIPS64State, guest_r17); break; case 18: - ret = offsetof(VexGuestMIPS32State, guest_w18); + ret = offsetof(VexGuestMIPS64State, guest_r18); break; case 19: - ret = offsetof(VexGuestMIPS32State, guest_w19); + ret = offsetof(VexGuestMIPS64State, guest_r19); break; case 20: - ret = offsetof(VexGuestMIPS32State, guest_w20); + ret = offsetof(VexGuestMIPS64State, guest_r20); break; case 21: - ret = offsetof(VexGuestMIPS32State, guest_w21); + ret = offsetof(VexGuestMIPS64State, guest_r21); break; case 22: - ret = offsetof(VexGuestMIPS32State, guest_w22); + ret = offsetof(VexGuestMIPS64State, guest_r22); break; case 23: - ret = offsetof(VexGuestMIPS32State, guest_w23); + ret = offsetof(VexGuestMIPS64State, guest_r23); break; case 24: - ret = offsetof(VexGuestMIPS32State, guest_w24); + ret = offsetof(VexGuestMIPS64State, guest_r24); break; case 25: - ret = offsetof(VexGuestMIPS32State, guest_w25); + ret = offsetof(VexGuestMIPS64State, guest_r25); break; case 26: - ret = offsetof(VexGuestMIPS32State, guest_w26); + ret = offsetof(VexGuestMIPS64State, guest_r26); break; case 27: - ret = offsetof(VexGuestMIPS32State, guest_w27); + ret = offsetof(VexGuestMIPS64State, guest_r27); break; case 28: - ret = offsetof(VexGuestMIPS32State, guest_w28); + ret = offsetof(VexGuestMIPS64State, guest_r28); break; case 29: - ret = offsetof(VexGuestMIPS32State, guest_w29); + ret = offsetof(VexGuestMIPS64State, guest_r29); break; case 30: - ret = offsetof(VexGuestMIPS32State, guest_w30); + ret = offsetof(VexGuestMIPS64State, guest_r30); break; case 31: - ret = offsetof(VexGuestMIPS32State, guest_w31); + ret = offsetof(VexGuestMIPS64State, guest_r31); break; default: vassert(0); break; } - } return ret; } - -/* Do a endian load of a 32-bit word, regardless of the endianness of the - underlying host. */ -static inline UInt getUInt(const UChar * p) -{ - UInt w = 0; -#if defined (_MIPSEL) - w = (w << 8) | p[3]; - w = (w << 8) | p[2]; - w = (w << 8) | p[1]; - w = (w << 8) | p[0]; -#elif defined (_MIPSEB) - w = (w << 8) | p[0]; - w = (w << 8) | p[1]; - w = (w << 8) | p[2]; - w = (w << 8) | p[3]; +#if defined(VGP_mips32_linux) +#define OFFB_PC offsetof(VexGuestMIPS32State, guest_PC) +#else +#define OFFB_PC offsetof(VexGuestMIPS64State, guest_PC) #endif - return w; -} -#define BITS2(_b1,_b0) \ - (((_b1) << 1) | (_b0)) +/* ---------------- Floating point registers ---------------- */ -#define BITS3(_b2,_b1,_b0) \ - (((_b2) << 2) | ((_b1) << 1) | (_b0)) +static UInt floatGuestRegOffset(UInt fregNo) +{ + vassert(fregNo < 32); + UInt ret; -#define BITS4(_b3,_b2,_b1,_b0) \ - (((_b3) << 3) | ((_b2) << 2) | ((_b1) << 1) | (_b0)) + if (!mode64) + switch (fregNo) { + case 0: + ret = offsetof(VexGuestMIPS32State, guest_f0); + break; -#define BITS5(_b4,_b3,_b2,_b1,_b0) \ - (((_b4) << 4) | BITS4((_b3),(_b2),(_b1),(_b0))) + case 1: + ret = offsetof(VexGuestMIPS32State, guest_f1); + break; -#define BITS6(_b5,_b4,_b3,_b2,_b1,_b0) \ - ((BITS2((_b5),(_b4)) << 4) \ - | BITS4((_b3),(_b2),(_b1),(_b0))) + case 2: + ret = offsetof(VexGuestMIPS32State, guest_f2); + break; -#define BITS8(_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0) \ - ((BITS4((_b7),(_b6),(_b5),(_b4)) << 4) \ - | BITS4((_b3),(_b2),(_b1),(_b0))) + case 3: + ret = offsetof(VexGuestMIPS32State, guest_f3); + break; -#define LOAD_STORE_PATTERN \ - t1 = newTemp(mode64 ? Ity_I64 : Ity_I32); \ - if(!mode64) \ - assign(t1, binop(Iop_Add32, getIReg(rs), \ - mkU32(extend_s_16to32(imm)))); \ - else \ - assign(t1, binop(Iop_Add64, getIReg(rs), \ - mkU64(extend_s_16to64(imm)))); \ + case 4: + ret = offsetof(VexGuestMIPS32State, guest_f4); + break; -#define LOAD_STORE_PATTERN_MSA(imm) \ - t1 = newTemp(mode64 ? Ity_I64 : Ity_I32); \ - if (!mode64) \ - assign(t1, binop(Iop_Add32, getIReg(ws), \ - mkU32(extend_s_10to32(imm)))); \ - else \ - assign(t1, binop(Iop_Add64, getIReg(ws), \ - mkU64(extend_s_10to64(imm)))); \ + case 5: + ret = offsetof(VexGuestMIPS32State, guest_f5); + break; -#define LOADX_STORE_PATTERN \ - t1 = newTemp(mode64 ? Ity_I64 : Ity_I32); \ - if(!mode64) \ - assign(t1, binop(Iop_Add32, getIReg(regRs), getIReg(regRt))); \ - else \ - assign(t1, binop(Iop_Add64, getIReg(regRs), getIReg(regRt))); + case 6: + ret = offsetof(VexGuestMIPS32State, guest_f6); + break; -#define LWX_SWX_PATTERN64 \ - t2 = newTemp(Ity_I64); \ - assign(t2, binop(Iop_And64, mkexpr(t1), mkU64(0xFFFFFFFFFFFFFFFCULL))); \ - t4 = newTemp(Ity_I32); \ - assign(t4, mkNarrowTo32( ty, binop(Iop_And64, \ - mkexpr(t1), mkU64(0x3)))); + case 7: + ret = offsetof(VexGuestMIPS32State, guest_f7); + break; -#define LWX_SWX_PATTERN64_1 \ - t2 = newTemp(Ity_I64); \ - assign(t2, binop(Iop_And64, mkexpr(t1), mkU64(0xFFFFFFFFFFFFFFF8ULL))); \ - t4 = newTemp(Ity_I64); \ - assign(t4, binop(Iop_And64, mkexpr(t1), mkU64(0x7))); + case 8: + ret = offsetof(VexGuestMIPS32State, guest_f8); + break; -#define LWX_SWX_PATTERN \ - t2 = newTemp(Ity_I32); \ - assign(t2, binop(Iop_And32, mkexpr(t1), mkU32(0xFFFFFFFC))); \ - t4 = newTemp(Ity_I32); \ - assign(t4, binop(Iop_And32, mkexpr(t1), mkU32(0x00000003))) + case 9: + ret = offsetof(VexGuestMIPS32State, guest_f9); + break; -#define SXXV_PATTERN(op) \ - putIReg(rd, binop(op, \ - getIReg(rt), \ - unop(Iop_32to8, \ - binop(Iop_And32, \ - getIReg(rs), \ - mkU32(0x0000001F) \ - ) \ - ) \ - ) \ - ) + case 10: + ret = offsetof(VexGuestMIPS32State, guest_f10); + break; -#define SXXV_PATTERN64(op) \ - putIReg(rd, mkWidenFrom32(ty, binop(op, \ - mkNarrowTo32(ty, getIReg(rt)), \ - unop(Iop_32to8, \ - binop(Iop_And32, \ - mkNarrowTo32(ty, getIReg(rs)), \ - mkU32(0x0000001F) \ - ) \ - ) \ - ), True \ - )) + case 11: + ret = offsetof(VexGuestMIPS32State, guest_f11); + break; -#define SXX_PATTERN(op) \ - putIReg(rd, binop(op, getIReg(rt), mkU8(sa))); + case 12: + ret = offsetof(VexGuestMIPS32State, guest_f12); + break; -#define ALU_PATTERN(op) \ - putIReg(rd, binop(op, getIReg(rs), getIReg(rt))); + case 13: + ret = offsetof(VexGuestMIPS32State, guest_f13); + break; -#define ALUI_PATTERN(op) \ - putIReg(rt, binop(op, getIReg(rs), mkU32(imm))); + case 14: + ret = offsetof(VexGuestMIPS32State, guest_f14); + break; -#define ALUI_PATTERN64(op) \ - putIReg(rt, binop(op, getIReg(rs), mkU64(imm))); + case 15: + ret = offsetof(VexGuestMIPS32State, guest_f15); + break; -#define ALU_PATTERN64(op) \ - putIReg(rd, mkWidenFrom32(ty, binop(op, \ - mkNarrowTo32(ty, getIReg(rs)), \ - mkNarrowTo32(ty, getIReg(rt))), True)); + case 16: + ret = offsetof(VexGuestMIPS32State, guest_f16); + break; -#define FP_CONDITIONAL_CODE \ - t3 = newTemp(Ity_I32); \ - assign(t3, binop(Iop_And32, \ - IRExpr_ITE( binop(Iop_CmpEQ32, mkU32(cc), mkU32(0)), \ - binop(Iop_Shr32, getFCSR(), mkU8(23)), \ - binop(Iop_Shr32, getFCSR(), mkU8(24+cc))), \ - mkU32(0x1))); + case 17: + ret = offsetof(VexGuestMIPS32State, guest_f17); + break; -#define ILLEGAL_INSTRUCTON \ - putPC(mkU32(guest_PC_curr_instr + 4)); \ - dres.jk_StopHere = Ijk_SigILL; \ - dres.whatNext = Dis_StopHere; + case 18: + ret = offsetof(VexGuestMIPS32State, guest_f18); + break; -#define LLADDR_INVALID \ - (mode64 ? mkU64(0xFFFFFFFFFFFFFFFFULL) : mkU32(0xFFFFFFFF)) + case 19: + ret = offsetof(VexGuestMIPS32State, guest_f19); + break; -/*------------------------------------------------------------*/ -/*--- Field helpers ---*/ -/*------------------------------------------------------------*/ + case 20: + ret = offsetof(VexGuestMIPS32State, guest_f20); + break; -static UInt get_opcode(UInt mipsins) -{ - return (0xFC000000 & mipsins) >> 26; -} + case 21: + ret = offsetof(VexGuestMIPS32State, guest_f21); + break; -static UInt get_rs(UInt mipsins) -{ - return (0x03E00000 & mipsins) >> 21; -} + case 22: + ret = offsetof(VexGuestMIPS32State, guest_f22); + break; -static UInt get_rt(UInt mipsins) -{ - return (0x001F0000 & mipsins) >> 16; -} + case 23: + ret = offsetof(VexGuestMIPS32State, guest_f23); + break; -static UInt get_imm(UInt mipsins) -{ - return (0x0000FFFF & mipsins); -} + case 24: + ret = offsetof(VexGuestMIPS32State, guest_f24); + break; -static UInt get_instr_index(UInt mipsins) -{ - return (0x03FFFFFF & mipsins); -} + case 25: + ret = offsetof(VexGuestMIPS32State, guest_f25); + break; -static UInt get_rd(UInt mipsins) -{ - return (0x0000F800 & mipsins) >> 11; -} + case 26: + ret = offsetof(VexGuestMIPS32State, guest_f26); + break; -static UInt get_sa(UInt mipsins) -{ - return (0x000007C0 & mipsins) >> 6; -} + case 27: + ret = offsetof(VexGuestMIPS32State, guest_f27); + break; -static UInt get_function(UInt mipsins) -{ - return (0x0000003F & mipsins); -} + case 28: + ret = offsetof(VexGuestMIPS32State, guest_f28); + break; -static UInt get_ft(UInt mipsins) -{ - return (0x001F0000 & mipsins) >> 16; -} + case 29: + ret = offsetof(VexGuestMIPS32State, guest_f29); + break; -static UInt get_fs(UInt mipsins) -{ - return (0x0000F800 & mipsins) >> 11; -} + case 30: + ret = offsetof(VexGuestMIPS32State, guest_f30); + break; -static UInt get_fd(UInt mipsins) -{ - return (0x000007C0 & mipsins) >> 6; -} + case 31: + ret = offsetof(VexGuestMIPS32State, guest_f31); + break; -static UInt get_mov_cc(UInt mipsins) -{ - return (0x001C0000 & mipsins) >> 18; -} + default: + vassert(0); + break; + } + else + switch (fregNo) { + case 0: + ret = offsetof(VexGuestMIPS64State, guest_f0); + break; -static UInt get_bc1_cc(UInt mipsins) -{ - return (0x001C0000 & mipsins) >> 18; -} + case 1: + ret = offsetof(VexGuestMIPS64State, guest_f1); + break; -static UInt get_fpc_cc(UInt mipsins) -{ - return (0x00000700 & mipsins) >> 8; -} + case 2: + ret = offsetof(VexGuestMIPS64State, guest_f2); + break; -static UInt get_tf(UInt mipsins) -{ - return (0x00010000 & mipsins) >> 16; -} + case 3: + ret = offsetof(VexGuestMIPS64State, guest_f3); + break; -static UInt get_nd(UInt mipsins) -{ - return (0x00020000 & mipsins) >> 17; -} + case 4: + ret = offsetof(VexGuestMIPS64State, guest_f4); + break; -static UInt get_fmt(UInt mipsins) -{ - return (0x03E00000 & mipsins) >> 21; -} + case 5: + ret = offsetof(VexGuestMIPS64State, guest_f5); + break; -static UInt get_FC(UInt mipsins) -{ - return (0x000000F0 & mipsins) >> 4; -} + case 6: + ret = offsetof(VexGuestMIPS64State, guest_f6); + break; -static UInt get_cond(UInt mipsins) -{ - return (0x0000000F & mipsins); -} + case 7: + ret = offsetof(VexGuestMIPS64State, guest_f7); + break; -/* for break & syscall */ -static UInt get_code(UInt mipsins) -{ - return (0xFFC0 & mipsins) >> 6; -} + case 8: + ret = offsetof(VexGuestMIPS64State, guest_f8); + break; -static UInt get_lsb(UInt mipsins) -{ - return (0x7C0 & mipsins) >> 6; -} + case 9: + ret = offsetof(VexGuestMIPS64State, guest_f9); + break; -static UInt get_msb(UInt mipsins) -{ - return (0x0000F800 & mipsins) >> 11; -} + case 10: + ret = offsetof(VexGuestMIPS64State, guest_f10); + break; -static UInt get_rot(UInt mipsins) -{ - return (0x00200000 & mipsins) >> 21; -} + case 11: + ret = offsetof(VexGuestMIPS64State, guest_f11); + break; -static UInt get_rotv(UInt mipsins) -{ - return (0x00000040 & mipsins) >> 6; -} + case 12: + ret = offsetof(VexGuestMIPS64State, guest_f12); + break; -static UInt get_sel(UInt mipsins) -{ - return (0x00000007 & mipsins); -} + case 13: + ret = offsetof(VexGuestMIPS64State, guest_f13); + break; -/* Get acc number for all MIPS32 DSP ASE(r2) instructions that use them, - except for MFHI and MFLO. */ -static UInt get_acNo(UInt mipsins) -{ - return (0x00001800 & mipsins) >> 11; -} + case 14: + ret = offsetof(VexGuestMIPS64State, guest_f14); + break; -/* Get accumulator number for MIPS32 DSP ASEr2 MFHI and MFLO instructions. */ -static UInt get_acNo_mfhilo(UInt mipsins) -{ - return (0x00600000 & mipsins) >> 21; -} + case 15: + ret = offsetof(VexGuestMIPS64State, guest_f15); + break; -/* Get mask field (helper function for wrdsp instruction). */ -static UInt get_wrdspMask(UInt mipsins) -{ - return (0x001ff800 & mipsins) >> 11; -} + case 16: + ret = offsetof(VexGuestMIPS64State, guest_f16); + break; -/* Get mask field (helper function for rddsp instruction). */ -static UInt get_rddspMask(UInt mipsins) -{ - return (0x03ff0000 & mipsins) >> 16; -} + case 17: + ret = offsetof(VexGuestMIPS64State, guest_f17); + break; -/* Get shift field (helper function for DSP ASE instructions). */ -static UInt get_shift(UInt mipsins) -{ - return (0x03f00000 & mipsins) >> 20; -} + case 18: + ret = offsetof(VexGuestMIPS64State, guest_f18); + break; -/* Get immediate field for DSP ASE instructions. */ -static UInt get_dspImm(UInt mipsins) -{ - return (0x03ff0000 & mipsins) >> 16; -} + case 19: + ret = offsetof(VexGuestMIPS64State, guest_f19); + break; -static Bool branch_or_jump(const UChar * addr) -{ - UInt fmt; - UInt cins = getUInt(addr); + case 20: + ret = offsetof(VexGuestMIPS64State, guest_f20); + break; - UInt opcode = get_opcode(cins); - UInt rt = get_rt(cins); - UInt function = get_function(cins); + case 21: + ret = offsetof(VexGuestMIPS64State, guest_f21); + break; - /* bgtz, blez, bne, beq, jal */ - if (opcode == 0x07 || opcode == 0x06 || opcode == 0x05 || opcode == 0x04 - || opcode == 0x03 || opcode == 0x02) { - return True; - } + case 22: + ret = offsetof(VexGuestMIPS64State, guest_f22); + break; - /* bgez */ - if (opcode == 0x01 && rt == 0x01) { - return True; - } + case 23: + ret = offsetof(VexGuestMIPS64State, guest_f23); + break; - /* bgezal */ - if (opcode == 0x01 && rt == 0x11) { - return True; - } + case 24: + ret = offsetof(VexGuestMIPS64State, guest_f24); + break; - /* bltzal */ - if (opcode == 0x01 && rt == 0x10) { - return True; - } + case 25: + ret = offsetof(VexGuestMIPS64State, guest_f25); + break; - /* bltz */ - if (opcode == 0x01 && rt == 0x00) { - return True; - } + case 26: + ret = offsetof(VexGuestMIPS64State, guest_f26); + break; - /* jalr */ - if (opcode == 0x00 && function == 0x09) { - return True; - } + case 27: + ret = offsetof(VexGuestMIPS64State, guest_f27); + break; - /* jr */ - if (opcode == 0x00 && function == 0x08) { - return True; - } + case 28: + ret = offsetof(VexGuestMIPS64State, guest_f28); + break; - if (opcode == 0x11) { - /* bc1f & bc1t */ - fmt = get_fmt(cins); - if (fmt == 0x08) { - return True; - } + case 29: + ret = offsetof(VexGuestMIPS64State, guest_f29); + break; - /* MSA branches */ - /* bnz.df, bz.df */ - if (fmt >= 0x18) { - return True; - } - /* bnz.v */ - if (fmt == 0x0f) { - return True; - } - /* bz.v */ - if (fmt == 0x0b) { - return True; - } + case 30: + ret = offsetof(VexGuestMIPS64State, guest_f30); + break; - /* R6 branches */ - /* bc1eqz */ - if (fmt == 0x09) { - return True; - } + case 31: + ret = offsetof(VexGuestMIPS64State, guest_f31); + break; - /* bc1nez */ - if (fmt == 0x0D) { - return True; + default: + vassert(0); + break; } - } - - /* bposge32 */ - if (opcode == 0x01 && rt == 0x1c) { - return True; - } - - /* Cavium Specific instructions. */ - if (opcode == 0x32 || opcode == 0x3A || opcode == 0x36 || opcode == 0x3E) { - /* BBIT0, BBIT1, BBIT032, BBIT132 */ - return True; - } - return False; + return ret; } -static Bool is_Branch_or_Jump_and_Link(const UChar * addr) +/* ---------------- MIPS32 DSP ASE(r2) accumulators ---------------- */ + +UInt accumulatorGuestRegOffset(UInt acNo) { - UInt cins = getUInt(addr); + vassert(!mode64); + vassert(acNo <= 3); + UInt ret; - UInt opcode = get_opcode(cins); - UInt rt = get_rt(cins); - UInt function = get_function(cins); + switch (acNo) { + case 0: + ret = offsetof(VexGuestMIPS32State, guest_ac0); + break; - /* jal */ - if (opcode == 0x02) { - return True; - } + case 1: + ret = offsetof(VexGuestMIPS32State, guest_ac1); + break; - /* bgezal or bal(r6) */ - if (opcode == 0x01 && rt == 0x11) { - return True; - } + case 2: + ret = offsetof(VexGuestMIPS32State, guest_ac2); + break; - /* bltzal */ - if (opcode == 0x01 && rt == 0x10) { - return True; - } + case 3: + ret = offsetof(VexGuestMIPS32State, guest_ac3); + break; - /* jalr */ - if (opcode == 0x00 && function == 0x09) { - return True; + default: + vassert(0); + break; } - return False; + return ret; } -static Bool branch_or_link_likely(const UChar * addr) -{ - UInt cins = getUInt(addr); - UInt opcode = get_opcode(cins); - UInt rt = get_rt(cins); +/* ---------------- MIPS32 MSA registers ---------------- */ - /* bgtzl, blezl, bnel, beql */ - if (opcode == 0x17 || opcode == 0x16 || opcode == 0x15 || opcode == 0x14) - return True; +static UInt msaGuestRegOffset(UInt msaRegNo) +{ + vassert(msaRegNo <= 31); + UInt ret; - /* bgezl */ - if (opcode == 0x01 && rt == 0x03) - return True; + if (mode64) { + switch (msaRegNo) { + case 0: + ret = offsetof(VexGuestMIPS64State, guest_w0); + break; - /* bgezall */ - if (opcode == 0x01 && rt == 0x13) - return True; + case 1: + ret = offsetof(VexGuestMIPS64State, guest_w1); + break; - /* bltzall */ - if (opcode == 0x01 && rt == 0x12) - return True; + case 2: + ret = offsetof(VexGuestMIPS64State, guest_w2); + break; - /* bltzl */ - if (opcode == 0x01 && rt == 0x02) - return True; + case 3: + ret = offsetof(VexGuestMIPS64State, guest_w3); + break; - return False; -} + case 4: + ret = offsetof(VexGuestMIPS64State, guest_w4); + break; -/*------------------------------------------------------------*/ -/*--- Helper bits and pieces for creating IR fragments. ---*/ -/*------------------------------------------------------------*/ + case 5: + ret = offsetof(VexGuestMIPS64State, guest_w5); + break; -static IRExpr *mkU8(UInt i) -{ - vassert(i < 256); - return IRExpr_Const(IRConst_U8((UChar) i)); -} + case 6: + ret = offsetof(VexGuestMIPS64State, guest_w6); + break; -/* Create an expression node for a 16-bit integer constant. */ -static IRExpr *mkU16(UInt i) -{ - return IRExpr_Const(IRConst_U16(i)); -} + case 7: + ret = offsetof(VexGuestMIPS64State, guest_w7); + break; -/* Create an expression node for a 32-bit integer constant. */ -static IRExpr *mkU32(UInt i) -{ - return IRExpr_Const(IRConst_U32(i)); -} + case 8: + ret = offsetof(VexGuestMIPS64State, guest_w8); + break; -/* Create an expression node for a 64-bit integer constant. */ -static IRExpr *mkU64(ULong i) -{ - return IRExpr_Const(IRConst_U64(i)); -} + case 9: + ret = offsetof(VexGuestMIPS64State, guest_w9); + break; -static IRExpr *mkexpr(IRTemp tmp) -{ - return IRExpr_RdTmp(tmp); -} + case 10: + ret = offsetof(VexGuestMIPS64State, guest_w10); + break; -static IRExpr *unop(IROp op, IRExpr * a) -{ - return IRExpr_Unop(op, a); -} + case 11: + ret = offsetof(VexGuestMIPS64State, guest_w11); + break; -static IRExpr *binop(IROp op, IRExpr * a1, IRExpr * a2) -{ - return IRExpr_Binop(op, a1, a2); -} + case 12: + ret = offsetof(VexGuestMIPS64State, guest_w12); + break; -static IRExpr *triop(IROp op, IRExpr * a1, IRExpr * a2, IRExpr * a3) -{ - return IRExpr_Triop(op, a1, a2, a3); -} + case 13: + ret = offsetof(VexGuestMIPS64State, guest_w13); + break; -static IRExpr *qop ( IROp op, IRExpr * a1, IRExpr * a2, IRExpr * a3, - IRExpr * a4 ) -{ - return IRExpr_Qop(op, a1, a2, a3, a4); -} + case 14: + ret = offsetof(VexGuestMIPS64State, guest_w14); + break; -static IRExpr *load(IRType ty, IRExpr * addr) -{ - IRExpr *load1 = NULL; -#if defined (_MIPSEL) - load1 = IRExpr_Load(Iend_LE, ty, addr); -#elif defined (_MIPSEB) - load1 = IRExpr_Load(Iend_BE, ty, addr); -#endif - return load1; -} + case 15: + ret = offsetof(VexGuestMIPS64State, guest_w15); + break; -/* Add a statement to the list held by "irsb". */ -static void stmt(IRStmt * st) -{ - addStmtToIRSB(irsb, st); -} + case 16: + ret = offsetof(VexGuestMIPS64State, guest_w16); + break; -static void assign(IRTemp dst, IRExpr * e) -{ - stmt(IRStmt_WrTmp(dst, e)); -} + case 17: + ret = offsetof(VexGuestMIPS64State, guest_w17); + break; -static void store(IRExpr * addr, IRExpr * data) -{ -#if defined (_MIPSEL) - stmt(IRStmt_Store(Iend_LE, addr, data)); -#elif defined (_MIPSEB) - stmt(IRStmt_Store(Iend_BE, addr, data)); -#endif -} + case 18: + ret = offsetof(VexGuestMIPS64State, guest_w18); + break; -/* Generate a new temporary of the given type. */ -static IRTemp newTemp(IRType ty) -{ - vassert(isPlausibleIRType(ty)); - return newIRTemp(irsb->tyenv, ty); -} + case 19: + ret = offsetof(VexGuestMIPS64State, guest_w19); + break; -/* Generate an expression for SRC rotated right by ROT. */ -static IRExpr *genROR32(IRExpr * src, Int rot) -{ - vassert(rot >= 0 && rot < 32); - if (rot == 0) - return src; - return binop(Iop_Or32, binop(Iop_Shl32, src, mkU8(32 - rot)), - binop(Iop_Shr32, src, mkU8(rot))); -} + case 20: + ret = offsetof(VexGuestMIPS64State, guest_w20); + break; -static IRExpr *genRORV32(IRExpr * src, IRExpr * rs) -{ - IRTemp t0 = newTemp(Ity_I8); - IRTemp t1 = newTemp(Ity_I8); + case 21: + ret = offsetof(VexGuestMIPS64State, guest_w21); + break; - assign(t0, unop(Iop_32to8, binop(Iop_And32, rs, mkU32(0x0000001F)))); - assign(t1, binop(Iop_Sub8, mkU8(32), mkexpr(t0))); - return binop(Iop_Or32, binop(Iop_Shl32, src, mkexpr(t1)), - binop(Iop_Shr32, src, mkexpr(t0))); -} + case 22: + ret = offsetof(VexGuestMIPS64State, guest_w22); + break; + case 23: + ret = offsetof(VexGuestMIPS64State, guest_w23); + break; -static UShort extend_s_9to16(UInt x) -{ - return (UShort) ((((Int) x) << 23) >> 23); -} + case 24: + ret = offsetof(VexGuestMIPS64State, guest_w24); + break; -static UShort extend_s_10to16(UInt x) -{ - return (UShort) ((((Int) x) << 22) >> 22); -} + case 25: + ret = offsetof(VexGuestMIPS64State, guest_w25); + break; -static UInt extend_s_10to32(UInt x) -{ - return (UInt)((((Int) x) << 22) >> 22); -} + case 26: + ret = offsetof(VexGuestMIPS64State, guest_w26); + break; -static ULong extend_s_10to64(UInt x) -{ - return (ULong)((((Long) x) << 54) >> 54); -} + case 27: + ret = offsetof(VexGuestMIPS64State, guest_w27); + break; -static UInt extend_s_16to32(UInt x) -{ - return (UInt) ((((Int) x) << 16) >> 16); -} + case 28: + ret = offsetof(VexGuestMIPS64State, guest_w28); + break; -static UInt extend_s_18to32(UInt x) -{ - return (UInt) ((((Int) x) << 14) >> 14); -} + case 29: + ret = offsetof(VexGuestMIPS64State, guest_w29); + break; -static UInt extend_s_19to32(UInt x) -{ - return (UInt) ((((Int) x) << 13) >> 13); -} + case 30: + ret = offsetof(VexGuestMIPS64State, guest_w30); + break; -static UInt extend_s_23to32(UInt x) -{ - return (UInt) ((((Int) x) << 9) >> 9); -} + case 31: + ret = offsetof(VexGuestMIPS64State, guest_w31); + break; -static UInt extend_s_26to32(UInt x) -{ - return (UInt) ((((Int) x) << 6) >> 6); -} + default: + vassert(0); + break; + } + } else { + switch (msaRegNo) { + case 0: + ret = offsetof(VexGuestMIPS32State, guest_w0); + break; -static ULong extend_s_16to64 ( UInt x ) -{ - return (ULong) ((((Long) x) << 48) >> 48); -} + case 1: + ret = offsetof(VexGuestMIPS32State, guest_w1); + break; -static ULong extend_s_18to64 ( UInt x ) -{ - return (ULong) ((((Long) x) << 46) >> 46); -} + case 2: + ret = offsetof(VexGuestMIPS32State, guest_w2); + break; -static ULong extend_s_19to64(UInt x) -{ - return (ULong) ((((Long) x) << 45) >> 45); -} + case 3: + ret = offsetof(VexGuestMIPS32State, guest_w3); + break; -static ULong extend_s_23to64(UInt x) -{ - return (ULong) ((((Long) x) << 41) >> 41); -} + case 4: + ret = offsetof(VexGuestMIPS32State, guest_w4); + break; -static ULong extend_s_26to64(UInt x) -{ - return (ULong) ((((Long) x) << 38) >> 38); -} + case 5: + ret = offsetof(VexGuestMIPS32State, guest_w5); + break; -static ULong extend_s_32to64 ( UInt x ) -{ - return (ULong) ((((Long) x) << 32) >> 32); -} + case 6: + ret = offsetof(VexGuestMIPS32State, guest_w6); + break; -static void jmp_lit32 ( /*MOD*/ DisResult* dres, IRJumpKind kind, Addr32 d32 ) -{ - vassert(dres->whatNext == Dis_Continue); - vassert(dres->len == 0); - vassert(dres->continueAt == 0); - vassert(dres->jk_StopHere == Ijk_INVALID); - dres->whatNext = Dis_StopHere; - dres->jk_StopHere = kind; - stmt( IRStmt_Put( OFFB_PC, mkU32(d32) ) ); -} + case 7: + ret = offsetof(VexGuestMIPS32State, guest_w7); + break; -static void jmp_lit64 ( /*MOD*/ DisResult* dres, IRJumpKind kind, Addr64 d64 ) -{ - vassert(dres->whatNext == Dis_Continue); - vassert(dres->len == 0); - vassert(dres->continueAt == 0); - vassert(dres->jk_StopHere == Ijk_INVALID); - dres->whatNext = Dis_StopHere; - dres->jk_StopHere = kind; - stmt(IRStmt_Put(OFFB_PC, mkU64(d64))); -} + case 8: + ret = offsetof(VexGuestMIPS32State, guest_w8); + break; -/* Get value from accumulator (helper function for MIPS32 DSP ASE instructions). - This function should be called before any other operation if widening - multiplications are used. */ -static IRExpr *getAcc(UInt acNo) -{ - vassert(!mode64); - vassert(acNo <= 3); - return IRExpr_Get(accumulatorGuestRegOffset(acNo), Ity_I64); -} + case 9: + ret = offsetof(VexGuestMIPS32State, guest_w9); + break; -/* Get value from DSPControl register (helper function for MIPS32 DSP ASE - instructions). */ -static IRExpr *getDSPControl(void) -{ - vassert(!mode64); - return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_DSPControl), Ity_I32); -} + case 10: + ret = offsetof(VexGuestMIPS32State, guest_w10); + break; -/* Put value to DSPControl register. Expression e is written to DSPControl as - is. If only certain bits of DSPControl need to be changed, it should be done - before calling putDSPControl(). It could be done by reading DSPControl and - ORing it with appropriate mask. */ -static void putDSPControl(IRExpr * e) -{ - vassert(!mode64); - stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_DSPControl), e)); -} + case 11: + ret = offsetof(VexGuestMIPS32State, guest_w11); + break; -/* Fetch a byte from the guest insn stream. */ -static UChar getIByte(Int delta) -{ - return guest_code[delta]; -} + case 12: + ret = offsetof(VexGuestMIPS32State, guest_w12); + break; -static IRExpr *getIReg(UInt iregNo) -{ - if (0 == iregNo) { - return mode64 ? mkU64(0x0) : mkU32(0x0); - } else { - IRType ty = mode64 ? Ity_I64 : Ity_I32; - vassert(iregNo < 32); - return IRExpr_Get(integerGuestRegOffset(iregNo), ty); - } -} + case 13: + ret = offsetof(VexGuestMIPS32State, guest_w13); + break; + case 14: + ret = offsetof(VexGuestMIPS32State, guest_w14); + break; -static IRExpr *getWReg(UInt wregNo) { - vassert(wregNo <= 31); - return IRExpr_Get(msaGuestRegOffset(wregNo), Ity_V128); -} + case 15: + ret = offsetof(VexGuestMIPS32State, guest_w15); + break; -static IRExpr *getHI(void) -{ - if (mode64) - return IRExpr_Get(offsetof(VexGuestMIPS64State, guest_HI), Ity_I64); - else - return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_HI), Ity_I32); -} + case 16: + ret = offsetof(VexGuestMIPS32State, guest_w16); + break; -static IRExpr *getLO(void) -{ - if (mode64) - return IRExpr_Get(offsetof(VexGuestMIPS64State, guest_LO), Ity_I64); - else - return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_LO), Ity_I32); -} + case 17: + ret = offsetof(VexGuestMIPS32State, guest_w17); + break; -static IRExpr *getFCSR(void) -{ - if (mode64) - return IRExpr_Get(offsetof(VexGuestMIPS64State, guest_FCSR), Ity_I32); - else - return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_FCSR), Ity_I32); -} + case 18: + ret = offsetof(VexGuestMIPS32State, guest_w18); + break; -static IRExpr *getLLaddr(void) -{ - if (mode64) - return IRExpr_Get(offsetof(VexGuestMIPS64State, guest_LLaddr), Ity_I64); - else - return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_LLaddr), Ity_I32); -} + case 19: + ret = offsetof(VexGuestMIPS32State, guest_w19); + break; -static IRExpr *getLLdata(void) -{ - if (mode64) - return IRExpr_Get(offsetof(VexGuestMIPS64State, guest_LLdata), Ity_I64); - else - return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_LLdata), Ity_I32); -} + case 20: + ret = offsetof(VexGuestMIPS32State, guest_w20); + break; -static IRExpr *getMSACSR(void) { - if (mode64) - return IRExpr_Get(offsetof(VexGuestMIPS64State, guest_MSACSR), Ity_I32); - else - return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_MSACSR), Ity_I32); -} + case 21: + ret = offsetof(VexGuestMIPS32State, guest_w21); + break; -/* Get byte from register reg, byte pos from 0 to 3 (or 7 for MIPS64) . */ -static IRExpr *getByteFromReg(UInt reg, UInt byte_pos) -{ - UInt pos = byte_pos * 8; - if (mode64) - return unop(Iop_64to8, binop(Iop_And64, - binop(Iop_Shr64, getIReg(reg), mkU8(pos)), - mkU64(0xFF))); - else - return unop(Iop_32to8, binop(Iop_And32, - binop(Iop_Shr32, getIReg(reg), mkU8(pos)), - mkU32(0xFF))); -} + case 22: + ret = offsetof(VexGuestMIPS32State, guest_w22); + break; -static void putFCSR(IRExpr * e) -{ - if (mode64) - stmt(IRStmt_Put(offsetof(VexGuestMIPS64State, guest_FCSR), e)); - else - stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_FCSR), e)); -} + case 23: + ret = offsetof(VexGuestMIPS32State, guest_w23); + break; -static void putLLaddr(IRExpr * e) -{ - if (mode64) - stmt(IRStmt_Put(offsetof(VexGuestMIPS64State, guest_LLaddr), e)); - els... [truncated message content] |
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From: Mark W. <ma...@so...> - 2019-03-27 14:56:08
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=8ed9b61432848dc23890375e425cdf1c37582bf5 commit 8ed9b61432848dc23890375e425cdf1c37582bf5 Author: Mark Wielaard <ma...@kl...> Date: Wed Mar 27 15:51:34 2019 +0100 Use ULong instead of unsigned long in s390_irgen_EX_SS. ovl was defined as an unsigned long. This would cause warnings from gcc: guest_s390_toIR.c:195:30: warning: right shift count >= width of type [-Wshift-count-overflow] when building on 32bit arches, or building a 32bit secondary arch. Fix this by defining ovl as ULong which is always guaranteed 64bit. Diff: --- VEX/priv/guest_s390_toIR.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index b4b8e3d..acff370 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -12745,7 +12745,7 @@ s390_irgen_EX_SS(UChar r, IRTemp addr2, IRTemp cond; IRDirty *d; IRTemp torun; - unsigned long ovl; + ULong ovl; IRTemp start1 = newTemp(Ity_I64); IRTemp start2 = newTemp(Ity_I64); |
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From: Mark W. <ma...@so...> - 2019-03-27 14:36:22
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=f04ae9f359411a2fff42f6c4b72fb8b0e56f5f58 commit f04ae9f359411a2fff42f6c4b72fb8b0e56f5f58 Author: Mark Wielaard <ma...@wi...> Date: Tue Mar 12 23:17:32 2019 +0100 Use gcc -Wimplicit-fallthrough=2 by default if available GCC 7 instroduced -Wimplicit-fallthrough https://developers.redhat.com/blog/2017/03/10/wimplicit-fallthrough-in-gcc-7/ It caught a couple of bugs, but it does need a bit of extra comments to explain when a switch case statement fall-through is deliberate. Luckily with -Wimplicit-fallthrough=2 various existing comments already do that. I have fixed the bugs, but adding explicit break statements where necessary and added comments where the fall-through was correct. https://bugs.kde.org/show_bug.cgi?id=405430 Diff: --- Makefile.all.am | 1 + NEWS | 1 + VEX/priv/guest_amd64_toIR.c | 2 ++ VEX/priv/guest_arm64_toIR.c | 6 ++--- VEX/priv/guest_arm_toIR.c | 3 +-- VEX/priv/guest_mips_toIR.c | 46 +++++++++++++++++++------------------ VEX/priv/guest_ppc_toIR.c | 3 +++ VEX/priv/guest_x86_toIR.c | 18 +++++++-------- VEX/priv/host_arm64_isel.c | 2 +- VEX/priv/host_arm_isel.c | 2 +- VEX/priv/host_mips_defs.c | 4 ++-- VEX/priv/host_mips_isel.c | 4 ++++ configure.ac | 1 + coregrind/m_gdbserver/m_gdbserver.c | 3 ++- coregrind/m_syswrap/syswrap-linux.c | 3 ++- memcheck/mc_malloc_wrappers.c | 4 ++-- 16 files changed, 59 insertions(+), 44 deletions(-) diff --git a/Makefile.all.am b/Makefile.all.am index daa7e41..3786e34 100644 --- a/Makefile.all.am +++ b/Makefile.all.am @@ -115,6 +115,7 @@ AM_CFLAGS_BASE = \ @FLAG_W_MISSING_PARAMETER_TYPE@ \ @FLAG_W_LOGICAL_OP@ \ @FLAG_W_ENUM_CONVERSION@ \ + @FLAG_W_IMPLICIT_FALLTHROUGH@ \ @FLAG_W_OLD_STYLE_DECLARATION@ \ @FLAG_FINLINE_FUNCTIONS@ \ @FLAG_FNO_STACK_PROTECTOR@ \ diff --git a/NEWS b/NEWS index bf90093..0b432a1 100644 --- a/NEWS +++ b/NEWS @@ -119,6 +119,7 @@ where XXXXXX is the bug number as listed below. 405363 PPC64, xvcvdpsxws, xvcvdpuxws, do not handle NaN arguments correctly. 405365 PPC64, function _get_maxmin_fp_NaN() doesn't handle QNaN, SNaN case correctly. +405430 Use gcc -Wimplicit-fallthrough=2 by default if available 405733 PPC64, xvcvdpsp should write 32-bit result to upper and lower 32-bits of the 64-bit destination field. 405734 PPC64, vrlwnm, vrlwmi, vrldrm, vrldmi do not work properly when me < mb diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c index 7e57933..7a20d45 100644 --- a/VEX/priv/guest_amd64_toIR.c +++ b/VEX/priv/guest_amd64_toIR.c @@ -30914,6 +30914,7 @@ Long dis_ESC_0F3A__VEX ( # undef CVT goto decode_success; } + break; case 0x09: /* VROUNDPD imm8, xmm2/m128, xmm1 */ @@ -31007,6 +31008,7 @@ Long dis_ESC_0F3A__VEX ( # undef CVT goto decode_success; } + break; case 0x0A: case 0x0B: diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c index 476eedc..64c6982 100644 --- a/VEX/priv/guest_arm64_toIR.c +++ b/VEX/priv/guest_arm64_toIR.c @@ -6419,8 +6419,8 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, } else { storeLE(addr, getQRegLane((tt+3) % 32, ix, ty)); } - /* fallthrough */ } + /* fallthrough */ case 3: { IRExpr* addr = binop(Iop_Add64, mkexpr(tTA), mkU64(2 * laneSzB)); @@ -6429,8 +6429,8 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, } else { storeLE(addr, getQRegLane((tt+2) % 32, ix, ty)); } - /* fallthrough */ } + /* fallthrough */ case 2: { IRExpr* addr = binop(Iop_Add64, mkexpr(tTA), mkU64(1 * laneSzB)); @@ -6439,8 +6439,8 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn, } else { storeLE(addr, getQRegLane((tt+1) % 32, ix, ty)); } - /* fallthrough */ } + /* fallthrough */ case 1: { IRExpr* addr = binop(Iop_Add64, mkexpr(tTA), mkU64(0 * laneSzB)); diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c index 35a62a1..5b63a80 100644 --- a/VEX/priv/guest_arm_toIR.c +++ b/VEX/priv/guest_arm_toIR.c @@ -6507,9 +6507,8 @@ Bool dis_neon_data_2reg_and_shift ( UInt theInstr, IRTemp condT ) } return True; } - } else { - /* fall through */ } + /* else fall through */ case 9: dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF); mreg = ((theInstr >> 1) & 0x10) | (theInstr & 0xF); diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c index d05816e..4748ba4 100644 --- a/VEX/priv/guest_mips_toIR.c +++ b/VEX/priv/guest_mips_toIR.c @@ -26348,7 +26348,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, /* Conditions starting with S should signal exception on QNaN inputs. */ switch (function) { case 8: /* SAF */ - signaling = CMPSAFD; + signaling = CMPSAFD; /* fallthrough */ case 0: /* AF */ assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); calculateFCSR(fs, ft, signaling, False, 2); @@ -26357,7 +26357,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, get_IR_roundingmode(), mkU64(0))); break; case 9: /* SUN */ - signaling = CMPSAFD; + signaling = CMPSAFD; /* fallthrough */ case 1: /* UN */ assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); calculateFCSR(fs, ft, signaling, False, 2); @@ -26369,7 +26369,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, get_IR_roundingmode(), mkU64(0)))); break; case 0x19: /* SOR */ - signaling = CMPSAFD; + signaling = CMPSAFD; /* fallthrough */ case 0x11: /* OR */ assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); calculateFCSR(fs, ft, signaling, False, 2); @@ -26381,7 +26381,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU64(0xFFFFFFFFFFFFFFFFULL)))); break; case 0xa: /* SEQ */ - signaling = CMPSAFD; + signaling = CMPSAFD; /* fallthrough */ case 2: /* EQ */ assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); calculateFCSR(fs, ft, signaling, False, 2); @@ -26393,7 +26393,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, get_IR_roundingmode(), mkU64(0)))); break; case 0x1A: /* SNEQ */ - signaling = CMPSAFD; + signaling = CMPSAFD; /* fallthrough */ case 0x12: /* NEQ */ assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); calculateFCSR(fs, ft, signaling, False, 2); @@ -26405,7 +26405,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU64(0xFFFFFFFFFFFFFFFFULL)))); break; case 0xB: /* SUEQ */ - signaling = CMPSAFD; + signaling = CMPSAFD; /* fallthrough */ case 0x3: /* UEQ */ assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); calculateFCSR(fs, ft, signaling, False, 2); @@ -26422,7 +26422,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU64(0))))); break; case 0x1B: /* SNEQ */ - signaling = CMPSAFD; + signaling = CMPSAFD; /* fallthrough */ case 0x13: /* NEQ */ assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); calculateFCSR(fs, ft, signaling, False, 2); @@ -26439,7 +26439,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU64(0))))); break; case 0xC: /* SLT */ - signaling = CMPSAFD; + signaling = CMPSAFD; /* fallthrough */ case 0x4: /* LT */ assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); calculateFCSR(fs, ft, signaling, False, 2); @@ -26451,7 +26451,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, get_IR_roundingmode(), mkU64(0)))); break; case 0xD: /* SULT */ - signaling = CMPSAFD; + signaling = CMPSAFD; /* fallthrough */ case 0x5: /* ULT */ assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); calculateFCSR(fs, ft, signaling, False, 2); @@ -26468,7 +26468,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU64(0))))); break; case 0xE: /* SLE */ - signaling = CMPSAFD; + signaling = CMPSAFD; /* fallthrough */ case 0x6: /* LE */ assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); calculateFCSR(fs, ft, signaling, False, 2); @@ -26485,7 +26485,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU64(0))))); break; case 0xF: /* SULE */ - signaling = CMPSAFD; + signaling = CMPSAFD; /* fallthrough */ case 0x7: /* ULE */ assign(t0, binop(Iop_CmpF64, getDReg(fs), getDReg(ft))); calculateFCSR(fs, ft, signaling, False, 2); @@ -26514,7 +26514,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, /* Conditions starting with S should signal exception on QNaN inputs. */ switch (function) { case 8: /* SAF */ - signaling = CMPSAFS; + signaling = CMPSAFS; /* fallthrough */ case 0: /* AF */ assign(t0, binop(Iop_CmpF32, getLoFromF64(Ity_F64, getFReg(fs)), @@ -26526,7 +26526,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, get_IR_roundingmode(), mkU32(0)))); break; case 9: /* SUN */ - signaling = CMPSAFS; + signaling = CMPSAFS; /* fallthrough */ case 1: /* UN */ assign(t0, binop(Iop_CmpF32, getLoFromF64(Ity_F64, getFReg(fs)), @@ -26543,7 +26543,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU32(0))))); break; case 0x19: /* SOR */ - signaling = CMPSAFS; + signaling = CMPSAFS; /* fallthrough */ case 0x11: /* OR */ assign(t0, binop(Iop_CmpF32, getLoFromF64(Ity_F64, getFReg(fs)), @@ -26560,7 +26560,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU32(0xFFFFFFFFU))))); break; case 0xa: /* SEQ */ - signaling = CMPSAFS; + signaling = CMPSAFS; /* fallthrough */ case 2: /* EQ */ assign(t0, binop(Iop_CmpF32, getLoFromF64(Ity_F64, getFReg(fs)), @@ -26577,7 +26577,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU32(0))))); break; case 0x1A: /* SNEQ */ - signaling = CMPSAFS; + signaling = CMPSAFS; /* fallthrough */ case 0x12: /* NEQ */ assign(t0, binop(Iop_CmpF32, getLoFromF64(Ity_F64, getFReg(fs)), @@ -26594,7 +26594,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU32(0xFFFFFFFFU))))); break; case 0xB: /* SUEQ */ - signaling = CMPSAFS; + signaling = CMPSAFS; /* fallthrough */ case 0x3: /* UEQ */ assign(t0, binop(Iop_CmpF32, getLoFromF64(Ity_F64, getFReg(fs)), @@ -26616,7 +26616,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU32(0)))))); break; case 0x1B: /* SNEQ */ - signaling = CMPSAFS; + signaling = CMPSAFS; /* fallthrough */ case 0x13: /* NEQ */ assign(t0, binop(Iop_CmpF32, getLoFromF64(Ity_F64, getFReg(fs)), @@ -26638,7 +26638,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU32(0)))))); break; case 0xC: /* SLT */ - signaling = CMPSAFS; + signaling = CMPSAFS; /* fallthrough */ case 0x4: /* LT */ assign(t0, binop(Iop_CmpF32, getLoFromF64(Ity_F64, getFReg(fs)), @@ -26655,7 +26655,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU32(0))))); break; case 0xD: /* SULT */ - signaling = CMPSAFS; + signaling = CMPSAFS; /* fallthrough */ case 0x5: /* ULT */ assign(t0, binop(Iop_CmpF32, getLoFromF64(Ity_F64, getFReg(fs)), @@ -26677,7 +26677,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU32(0)))))); break; case 0xE: /* SLE */ - signaling = CMPSAFS; + signaling = CMPSAFS; /* fallthrough */ case 0x6: /* LE */ assign(t0, binop(Iop_CmpF32, getLoFromF64(Ity_F64, getFReg(fs)), @@ -26699,7 +26699,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, mkU32(0)))))); break; case 0xF: /* SULE */ - signaling = CMPSAFS; + signaling = CMPSAFS; /* fallthrough */ case 0x7: /* ULE */ assign(t0, binop(Iop_CmpF32, getLoFromF64(Ity_F64, getFReg(fs)), @@ -28051,6 +28051,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, break; } else { ILLEGAL_INSTRUCTON; + break; } } @@ -31583,6 +31584,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, } } else { ILLEGAL_INSTRUCTON; + break; } } diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index ab14cf8..ec7c63a 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -7429,6 +7429,7 @@ static Bool dis_int_store ( UInt theInstr, const VexAbiInfo* vbi ) case 0x3E: // immediate offset: 64bit: std/stdu/stq: mask off // lowest 2 bits of immediate before forming EA simm16 = simm16 & 0xFFFFFFFC; + /* fallthrough */ default: // immediate offset assign( EA, ea_rAor0_simm( rA_addr, simm16 ) ); break; @@ -28424,6 +28425,7 @@ DisResult disInstr_PPC_WRK ( if (!allow_DFP) goto decode_noDFP; if (dis_dfp_arith( theInstr )) goto decode_success; + goto decode_failure; case 0x82: // dcmpo, DFP comparison ordered instruction case 0x282: // dcmpu, DFP comparison unordered instruction if (!allow_DFP) goto decode_noDFP; @@ -28904,6 +28906,7 @@ DisResult disInstr_PPC_WRK ( abiinfo ) ) goto decode_success; } + /* fallthrough to dis_vx_scalar_quad_precision */ /* Instructions implemented with Pre ISA 3.0 Iops */ /* VSX Scalar Quad-Precision instructions */ diff --git a/VEX/priv/guest_x86_toIR.c b/VEX/priv/guest_x86_toIR.c index 2e3b803..9a6e417 100644 --- a/VEX/priv/guest_x86_toIR.c +++ b/VEX/priv/guest_x86_toIR.c @@ -14295,25 +14295,25 @@ DisResult disInstr_X86_WRK ( switch (abyte) { /* According to the Intel manual, "repne movs" should never occur, but * in practice it has happened, so allow for it here... */ - case 0xA4: sz = 1; /* REPNE MOVS<sz> */ + case 0xA4: sz = 1; /* REPNE MOVS<sz> fallthrough */ case 0xA5: dis_REP_op ( &dres, X86CondNZ, dis_MOVS, sz, eip_orig, guest_EIP_bbstart+delta, "repne movs" ); break; - case 0xA6: sz = 1; /* REPNE CMP<sz> */ + case 0xA6: sz = 1; /* REPNE CMP<sz> fallthrough */ case 0xA7: dis_REP_op ( &dres, X86CondNZ, dis_CMPS, sz, eip_orig, guest_EIP_bbstart+delta, "repne cmps" ); break; - case 0xAA: sz = 1; /* REPNE STOS<sz> */ + case 0xAA: sz = 1; /* REPNE STOS<sz> fallthrough */ case 0xAB: dis_REP_op ( &dres, X86CondNZ, dis_STOS, sz, eip_orig, guest_EIP_bbstart+delta, "repne stos" ); break; - case 0xAE: sz = 1; /* REPNE SCAS<sz> */ + case 0xAE: sz = 1; /* REPNE SCAS<sz> fallthrough */ case 0xAF: dis_REP_op ( &dres, X86CondNZ, dis_SCAS, sz, eip_orig, guest_EIP_bbstart+delta, "repne scas" ); @@ -14351,31 +14351,31 @@ DisResult disInstr_X86_WRK ( } break; - case 0xA4: sz = 1; /* REP MOVS<sz> */ + case 0xA4: sz = 1; /* REP MOVS<sz> fallthrough */ case 0xA5: dis_REP_op ( &dres, X86CondAlways, dis_MOVS, sz, eip_orig, guest_EIP_bbstart+delta, "rep movs" ); break; - case 0xA6: sz = 1; /* REPE CMP<sz> */ + case 0xA6: sz = 1; /* REPE CMP<sz> fallthrough */ case 0xA7: dis_REP_op ( &dres, X86CondZ, dis_CMPS, sz, eip_orig, guest_EIP_bbstart+delta, "repe cmps" ); break; - case 0xAA: sz = 1; /* REP STOS<sz> */ + case 0xAA: sz = 1; /* REP STOS<sz> fallthrough */ case 0xAB: dis_REP_op ( &dres, X86CondAlways, dis_STOS, sz, eip_orig, guest_EIP_bbstart+delta, "rep stos" ); break; - case 0xAC: sz = 1; /* REP LODS<sz> */ + case 0xAC: sz = 1; /* REP LODS<sz> fallthrough */ case 0xAD: dis_REP_op ( &dres, X86CondAlways, dis_LODS, sz, eip_orig, guest_EIP_bbstart+delta, "rep lods" ); break; - case 0xAE: sz = 1; /* REPE SCAS<sz> */ + case 0xAE: sz = 1; /* REPE SCAS<sz> fallthrough */ case 0xAF: dis_REP_op ( &dres, X86CondZ, dis_SCAS, sz, eip_orig, guest_EIP_bbstart+delta, "repe scas" ); diff --git a/VEX/priv/host_arm64_isel.c b/VEX/priv/host_arm64_isel.c index 50f9205..49d0f0b 100644 --- a/VEX/priv/host_arm64_isel.c +++ b/VEX/priv/host_arm64_isel.c @@ -2040,7 +2040,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) addInstr(env, ARM64Instr_MovI(dst, hregARM64_X0())); return dst; } - /* else fall through; will hit the irreducible: label */ + goto irreducible; } /* --------- LITERAL --------- */ diff --git a/VEX/priv/host_arm_isel.c b/VEX/priv/host_arm_isel.c index da4f4aa..9ef4269 100644 --- a/VEX/priv/host_arm_isel.c +++ b/VEX/priv/host_arm_isel.c @@ -2001,7 +2001,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e ) addInstr(env, mk_iMOVds_RR(dst, hregARM_R0())); return dst; } - /* else fall through; will hit the irreducible: label */ + goto irreducible; } /* --------- LITERAL --------- */ diff --git a/VEX/priv/host_mips_defs.c b/VEX/priv/host_mips_defs.c index 7a3faed..717fd27 100644 --- a/VEX/priv/host_mips_defs.c +++ b/VEX/priv/host_mips_defs.c @@ -3396,10 +3396,10 @@ static UChar *mkFormBIT(UChar *p, UInt op, UInt df, UInt ms, UInt ws, UInt wd) { switch (df) { case 0: dfm |= 0x10; - + /* fallthrough */ case 1: dfm |= 0x20; - + /* fallthrough */ case 2: dfm |= 0x40; } diff --git a/VEX/priv/host_mips_isel.c b/VEX/priv/host_mips_isel.c index f6d5b0a..c0cdfb0 100644 --- a/VEX/priv/host_mips_isel.c +++ b/VEX/priv/host_mips_isel.c @@ -2022,18 +2022,21 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e) switch (op_unop) { case Iop_1Uto64: vassert(mode64); + /* fallthrough */ case Iop_1Uto8: case Iop_1Uto32: mask = toUShort(0x1); break; case Iop_8Uto64: vassert(mode64); + /* fallthrough */ case Iop_8Uto16: case Iop_8Uto32: mask = toUShort(0xFF); break; case Iop_16Uto64: vassert(mode64); + /* fallthrough */ case Iop_16Uto32: mask = toUShort(0xFFFF); break; @@ -2155,6 +2158,7 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e) case Iop_Clz64: vassert(mode64); + /* fallthrough */ case Iop_Clz32: { HReg r_dst = newVRegI(env); HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg); diff --git a/configure.ac b/configure.ac index 3c92f71..e26b503 100755 --- a/configure.ac +++ b/configure.ac @@ -2113,6 +2113,7 @@ AC_GCC_WARNING_SUBST([ignored-qualifiers], [FLAG_W_IGNORED_QUALIFIERS]) AC_GCC_WARNING_SUBST([missing-parameter-type], [FLAG_W_MISSING_PARAMETER_TYPE]) AC_GCC_WARNING_SUBST([logical-op], [FLAG_W_LOGICAL_OP]) AC_GCC_WARNING_SUBST([enum-conversion], [FLAG_W_ENUM_CONVERSION]) +AC_GCC_WARNING_SUBST([implicit-fallthrough=2], [FLAG_W_IMPLICIT_FALLTHROUGH]) # Does this compiler support -Wformat-security ? # Special handling is needed, because certain GCC versions require -Wformat diff --git a/coregrind/m_gdbserver/m_gdbserver.c b/coregrind/m_gdbserver/m_gdbserver.c index 1f98ac9..96372fd 100644 --- a/coregrind/m_gdbserver/m_gdbserver.c +++ b/coregrind/m_gdbserver/m_gdbserver.c @@ -911,7 +911,8 @@ void VG_(invoke_gdbserver) ( int check ) interrupts_non_interruptible++; VG_(force_vgdb_poll) (); give_control_back_to_vgdb(); - + /* If give_control_back_to_vgdb returns in an non interruptable + state something went horribly wrong, fallthrough to vg_assert. */ default: vg_assert(0); } } diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c index 2f6ca3d..73ef98d 100644 --- a/coregrind/m_syswrap/syswrap-linux.c +++ b/coregrind/m_syswrap/syswrap-linux.c @@ -898,8 +898,8 @@ PRE(sys_clone) break; case VKI_CLONE_VFORK | VKI_CLONE_VM: /* vfork */ - // FALLTHROUGH - assume vfork (somewhat) == fork, see ML_(do_fork_clone). cloneflags &= ~VKI_CLONE_VM; + // FALLTHROUGH - assume vfork (somewhat) == fork, see ML_(do_fork_clone). case 0: /* plain fork */ SET_STATUS_from_SysRes( @@ -11960,6 +11960,7 @@ PRE(sys_bpf) PRE_MEM_WRITE("bpf(attr->btf_log_buf)", attr->btf_log_buf, attr->btf_log_size); } + break; case VKI_BPF_TASK_FD_QUERY: /* Get info about the task. Write collected info. */ PRE_MEM_READ("bpf(attr->task_fd_query.pid)", (Addr)&attr->task_fd_query.pid, sizeof(attr->task_fd_query.pid)); diff --git a/memcheck/mc_malloc_wrappers.c b/memcheck/mc_malloc_wrappers.c index 875eba7..caf097f 100644 --- a/memcheck/mc_malloc_wrappers.c +++ b/memcheck/mc_malloc_wrappers.c @@ -199,8 +199,8 @@ MC_Chunk* create_MC_Chunk ( ThreadId tid, Addr p, SizeT szB, mc->szB = szB; mc->allockind = kind; switch ( MC_(n_where_pointers)() ) { - case 2: mc->where[1] = 0; // fallback to 1 - case 1: mc->where[0] = 0; // fallback to 0 + case 2: mc->where[1] = 0; // fallthrough to 1 + case 1: mc->where[0] = 0; // fallthrough to 0 case 0: break; default: tl_assert(0); } |