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From: Carl L. <ca...@so...> - 2019-03-22 17:54:26
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=ed80ebfa1704682de3a9a5ddfe3ce4ffef1878da commit ed80ebfa1704682de3a9a5ddfe3ce4ffef1878da Author: Carl Love <ca...@us...> Date: Fri Mar 22 12:50:52 2019 -0500 PPC64, fix for vrlwnm, vrlwmi, vrldrm, vrldmi instructions. Fixes the case where the specified end bit is less then the start bit. Valgrind bug 405734 Diff: --- NEWS | 4 +- VEX/priv/guest_ppc_toIR.c | 106 +++++++++++++++++++++++++++++++++------------- 2 files changed, 80 insertions(+), 30 deletions(-) diff --git a/NEWS b/NEWS index c2a7848..bf90093 100644 --- a/NEWS +++ b/NEWS @@ -119,7 +119,9 @@ where XXXXXX is the bug number as listed below. 405363 PPC64, xvcvdpsxws, xvcvdpuxws, do not handle NaN arguments correctly. 405365 PPC64, function _get_maxmin_fp_NaN() doesn't handle QNaN, SNaN case correctly. -405733 PPC64, xvcvdpsp should write 32-bit result to upper and lower 32-bits of the 64-bit destination field. +405733 PPC64, xvcvdpsp should write 32-bit result to upper and lower 32-bits + of the 64-bit destination field. +405734 PPC64, vrlwnm, vrlwmi, vrldrm, vrldmi do not work properly when me < mb n-i-bz add syswrap for PTRACE_GET|SET_THREAD_AREA on amd64. n-i-bz Fix callgrind_annotate non deterministic order for equal total diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 9bc7c3b..ab14cf8 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -15619,8 +15619,12 @@ static Bool dis_av_rotate ( UInt theInstr ) IRTemp vA_word[4]; IRTemp left_bits[4]; IRTemp right_bits[4]; + IRTemp mb[4]; + IRTemp me[4]; IRTemp shift[4]; IRTemp mask[4]; + IRTemp tmp_mask[4]; + IRTemp invert_mask[4]; IRTemp tmp128[4]; UInt i; UInt num_words; @@ -15664,7 +15668,11 @@ static Bool dis_av_rotate ( UInt theInstr ) left_bits[i] = newTemp( Ity_I8 ); right_bits[i] = newTemp( Ity_I8 ); shift[i] = newTemp( Ity_I8 ); - mask[i] = newTemp( Ity_V128 ); + mb[i] = newTemp( Ity_I64 ); + me[i] = newTemp( Ity_I64 ); + tmp_mask[i] = newTemp( Ity_I64 ); + invert_mask[i] = newTemp( Ity_I64 ); + mask[i] = newTemp( Ity_V128 ); tmp128[i] = newTemp( Ity_V128 ); vA_word[i] = newTemp( Ity_V128 ); @@ -15678,50 +15686,90 @@ static Bool dis_av_rotate ( UInt theInstr ) * word_size ) ), mkexpr( field_mask ) ) ) ) ); + assign( mb[i], unop( Iop_V128to64, + binop( Iop_AndV128, + binop( Iop_ShrV128, + mkexpr( vB ), + mkU8( ( num_words - 1 - i ) + * word_size + 16 ) ), + mkexpr( field_mask ) ) ) ); + + assign( me[i], unop( Iop_V128to64, + binop( Iop_AndV128, + binop( Iop_ShrV128, + mkexpr( vB ), + mkU8( ( num_words - 1 - i ) + * word_size + 8 ) ), + mkexpr( field_mask ) ) ) ); + + /* If me < mb, we have to flip things around and invert the mask */ + assign( invert_mask[i], + unop( Iop_1Sto64, binop( Iop_CmpLT64U, + mkexpr( me[i] ), mkexpr( mb[i] ) ) ) ); + /* left_bits = 63 - mb. Tells us how many bits to the left * of mb to clear. Note for a word left_bits = 32+mb, for a double * word left_bits = mb */ assign( left_bits[i], unop( Iop_64to8, - binop( Iop_Add64, - mkU64( 64 - word_size ), - unop( Iop_V128to64, - binop( Iop_AndV128, - binop( Iop_ShrV128, - mkexpr( vB ), - mkU8( ( num_words - 1 - i ) - * word_size + 16 ) ), - mkexpr( field_mask ) ) ) ) ) ); + binop( Iop_Or64, + binop( Iop_And64, // mb < me + unop( Iop_Not64, mkexpr( invert_mask[i] ) ), + binop( Iop_Add64, + mkU64( 64 - word_size ), + mkexpr( mb[i] ) ) ), + binop( Iop_And64, // me < mb + mkexpr( invert_mask[i] ), + binop( Iop_Add64, + mkU64( 64 + 1 - word_size ), + mkexpr( me[i] ) ) ) ) ) ); + /* right_bits = 63 - me. Tells us how many bits to the right * of me to clear. Note for a word, left_bits = me+32, for a double * word left_bits = me */ assign( right_bits[i], unop( Iop_64to8, - binop( Iop_Sub64, - mkU64( word_size - 1 ), - unop( Iop_V128to64, - binop( Iop_AndV128, - binop( Iop_ShrV128, - mkexpr( vB ), - mkU8( ( num_words - 1 - i ) - * word_size + 8 ) ), - mkexpr( field_mask ) ) ) ) ) ); + binop( Iop_Or64, + binop( Iop_And64, // mb < me + unop( Iop_Not64, mkexpr( invert_mask[i] ) ), + binop( Iop_Sub64, + mkU64( word_size - 1 ), + mkexpr( me[i] ) ) ), + binop( Iop_And64, // me < mb + mkexpr( invert_mask[i] ), + binop( Iop_Sub64, + mkU64( word_size - 1 + 1), + mkexpr( mb[i] ) ) ) ) ) ); /* create mask for 32-bit word or 64-bit word */ + assign( tmp_mask[i], + binop( Iop_Shl64, + binop( Iop_Shr64, + binop( Iop_Shr64, + binop( Iop_Shl64, + mkU64( 0xFFFFFFFFFFFFFFFF ), + mkexpr( left_bits[i] ) ), + mkexpr( left_bits[i] ) ), + mkexpr( right_bits[i] ) ), + mkexpr( right_bits[i] ) ) ); + assign( mask[i], binop( Iop_64HLtoV128, mkU64( 0 ), - binop( Iop_Shl64, - binop( Iop_Shr64, - binop( Iop_Shr64, - binop( Iop_Shl64, - mkU64( 0xFFFFFFFFFFFFFFFF ), - mkexpr( left_bits[i] ) ), - mkexpr( left_bits[i] ) ), - mkexpr( right_bits[i] ) ), - mkexpr( right_bits[i] ) ) ) ); + binop( Iop_Or64, + binop( Iop_And64, + unop( Iop_Not64, mkexpr( invert_mask[i] ) ), + mkexpr( tmp_mask[i] ) ), + binop( Iop_And64, + mkexpr( invert_mask[i] ), + /* Need to make sure mask is only the size + desired word.*/ + binop( Iop_And64, + mkU64( word_mask ), + unop( Iop_Not64, + mkexpr( tmp_mask[i] ) ) ) )))); /* Need to rotate vA using a left and right shift of vA OR'd together * then ANDed with the mask. @@ -15750,7 +15798,7 @@ static Bool dis_av_rotate ( UInt theInstr ) mkU32( word_size ), unop( Iop_8Uto32, mkexpr( shift[i] ) ) ) - ) ) ) ) ); + ) ) ) ) ); } switch (opc2) { |
|
From: Carl L. <ca...@so...> - 2019-03-22 17:46:51
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=30a24515f09f9118c469ae11c9d574da729c97ed commit 30a24515f09f9118c469ae11c9d574da729c97ed Author: Carl Love <ca...@us...> Date: Fri Mar 22 12:42:27 2019 -0500 PPC64, fix output for xvcvdpsp instruction. The instruction should write the output to the upper and lower 32-bit halfs of the results. Valgrind bugzilla 405733. Diff: --- NEWS | 1 + VEX/priv/guest_ppc_toIR.c | 15 +++++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/NEWS b/NEWS index a18d340..c2a7848 100644 --- a/NEWS +++ b/NEWS @@ -119,6 +119,7 @@ where XXXXXX is the bug number as listed below. 405363 PPC64, xvcvdpsxws, xvcvdpuxws, do not handle NaN arguments correctly. 405365 PPC64, function _get_maxmin_fp_NaN() doesn't handle QNaN, SNaN case correctly. +405733 PPC64, xvcvdpsp should write 32-bit result to upper and lower 32-bits of the 64-bit destination field. n-i-bz add syswrap for PTRACE_GET|SET_THREAD_AREA on amd64. n-i-bz Fix callgrind_annotate non deterministic order for equal total diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 3725e6a..9bc7c3b 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -16332,6 +16332,9 @@ dis_vx_conv ( UInt theInstr, UInt opc2 ) case 0x312: // xvcvdpsp (VSX Vector round Double-Precision to single-precision // and Convert to Single-Precision format) DIP("xvcvdpsp v%u,v%u\n", XT, XB); + + /* Note, the 32-bit result is put into the upper and lower bits of the + doubleword result. */ putVSReg( XT, binop( Iop_64HLtoV128, binop( Iop_32HLto64, @@ -16340,14 +16343,22 @@ dis_vx_conv ( UInt theInstr, UInt opc2 ) binop( Iop_RoundF64toF32, get_IR_roundingmode(), mkexpr( xB ) ) ) ), - mkU32( 0 ) ), + unop( Iop_ReinterpF32asI32, + unop( Iop_TruncF64asF32, + binop( Iop_RoundF64toF32, + get_IR_roundingmode(), + mkexpr( xB ) ) ) ) ), binop( Iop_32HLto64, unop( Iop_ReinterpF32asI32, unop( Iop_TruncF64asF32, binop( Iop_RoundF64toF32, get_IR_roundingmode(), mkexpr( xB2 ) ) ) ), - mkU32( 0 ) ) ) ); + unop( Iop_ReinterpF32asI32, + unop( Iop_TruncF64asF32, + binop( Iop_RoundF64toF32, + get_IR_roundingmode(), + mkexpr( xB2 ) ) ) ) ) ) ); break; case 0x390: // xvcvdpuxds (VSX Vector truncate Double-Precision to integer // and Convert to Unsigned Integer Doubleword format |
|
From: Carl L. <ca...@so...> - 2019-03-22 17:34:36
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=e9986500957ae53ef6374e86938188bca4d1c6df commit e9986500957ae53ef6374e86938188bca4d1c6df Author: Carl Love <ca...@us...> Date: Fri Mar 22 12:32:29 2019 -0500 PPC64, The function _get_maxmin_fp_NaN does not handle the case of QNaN, SNaN correctly. This patch fixes Valgrind to handle the case of QNaN, SNaN input the same as the HW handles it. Valgrind bug 405365. Diff: --- NEWS | 2 ++ VEX/priv/guest_ppc_toIR.c | 16 ++++++++++++---- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/NEWS b/NEWS index fe30a0f..a18d340 100644 --- a/NEWS +++ b/NEWS @@ -117,6 +117,8 @@ where XXXXXX is the bug number as listed below. the upper and lower 32-bits of the 64-bit result 405362 PPC64, vmsummbm instruction doesn't handle overflow case correctly 405363 PPC64, xvcvdpsxws, xvcvdpuxws, do not handle NaN arguments correctly. +405365 PPC64, function _get_maxmin_fp_NaN() doesn't handle QNaN, SNaN case + correctly. n-i-bz add syswrap for PTRACE_GET|SET_THREAD_AREA on amd64. n-i-bz Fix callgrind_annotate non deterministic order for equal total diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index d40de2d..3725e6a 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -17485,7 +17485,10 @@ static IRExpr * _get_maxmin_fp_NaN(IRTemp frA_I64, IRTemp frB_I64) * if frA is a SNaN * result = frA converted to QNaN * else if frB is a SNaN - * result = frB converted to QNaN + * if (frA is QNan) + * result = frA + * else + * result = frB converted to QNaN * else if frB is a QNaN * result = frA * // One of frA or frB was a NaN in order for this function to be called, so @@ -17496,14 +17499,19 @@ static IRExpr * _get_maxmin_fp_NaN(IRTemp frA_I64, IRTemp frB_I64) */ #define SNAN_MASK 0x0008000000000000ULL + return - IRExpr_ITE(mkexpr(frA_isSNaN), + IRExpr_ITE(mkexpr(frA_isSNaN), /* then: result = frA converted to QNaN */ binop(Iop_Or64, mkexpr(frA_I64), mkU64(SNAN_MASK)), /* else: if frB is a SNaN */ IRExpr_ITE(mkexpr(frB_isSNaN), - /* then: result = frB converted to QNaN */ - binop(Iop_Or64, mkexpr(frB_I64), mkU64(SNAN_MASK)), + IRExpr_ITE(mkexpr(frA_isQNaN), + /* then: result = frA */ + mkexpr(frA_I64), + /* else: result = frB converted to QNaN */ + binop(Iop_Or64, mkexpr(frB_I64), + mkU64(SNAN_MASK))), /* else: if frB is a QNaN */ IRExpr_ITE(mkexpr(frB_isQNaN), /* then: result = frA */ |
|
From: Carl L. <ca...@so...> - 2019-03-22 17:26:33
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=d4686f635ec9d9ee9f5aa4c6675d486c89e2c7a6 commit d4686f635ec9d9ee9f5aa4c6675d486c89e2c7a6 Author: Carl Love <ca...@us...> Date: Fri Mar 22 12:26:00 2019 -0500 PPC64, instructions xvcvdpsxws, xvcvdpuxws do not handle over/underflow, NaN correctly The instructions are not checking for overflow, underflow, NaN and setting the output correctly. Valgrind bugzilla 405363 Diff: --- NEWS | 1 + VEX/priv/guest_ppc_toIR.c | 174 +++++++++++++++++++++++++++++++++++++++------- 2 files changed, 151 insertions(+), 24 deletions(-) diff --git a/NEWS b/NEWS index c59168b..fe30a0f 100644 --- a/NEWS +++ b/NEWS @@ -116,6 +116,7 @@ where XXXXXX is the bug number as listed below. 405356 PPC64, xvcvsxdsp, xvcvuxdsp are supposed to write the 32-bit result to the upper and lower 32-bits of the 64-bit result 405362 PPC64, vmsummbm instruction doesn't handle overflow case correctly +405363 PPC64, xvcvdpsxws, xvcvdpuxws, do not handle NaN arguments correctly. n-i-bz add syswrap for PTRACE_GET|SET_THREAD_AREA on amd64. n-i-bz Fix callgrind_annotate non deterministic order for equal total diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index fb6f989..d40de2d 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -16064,18 +16064,160 @@ dis_vx_conv ( UInt theInstr, UInt opc2 ) break; case 0x1b0: // xvcvdpsxws (VSX Vector truncate Double-Precision to integer and Convert // to Signed Integer Word format with Saturate) + case 0x190: // xvcvdpuxws (VSX Vector truncate Double-Precision to integer and + // Convert to Unsigned Integer Word format with Saturate) { - IRTemp hiResult_32 = newTemp(Ity_I32); - IRTemp loResult_32 = newTemp(Ity_I32); + IRTemp value_f64[2]; + IRTemp Result_32[2]; + IRTemp Result_32_tmp[2]; + IRTemp nan_mask[2]; + IRTemp underflow_mask[2]; + IRTemp overflow_mask[2]; + IRTemp error_mask[2]; + IRTemp error_value[2]; + IRTemp tmp_64[2]; + + Int i; + Int underflow_value; + Int overflow_value; IRExpr* rmZero = mkU32(Irrm_ZERO); - DIP("xvcvdpsxws v%u,v%u\n", XT, XB); - assign(hiResult_32, binop(Iop_F64toI32S, rmZero, mkexpr(xB))); - assign(loResult_32, binop(Iop_F64toI32S, rmZero, mkexpr(xB2))); + value_f64[0] = newTemp(Ity_F64); + assign( value_f64[0], mkexpr( xB ) ); + + value_f64[1] = newTemp(Ity_F64); + assign( value_f64[1], mkexpr( xB2 ) ); + + for ( i = 0; i < 2; i++) { + Result_32[i] = newTemp(Ity_I32); + Result_32_tmp[i] = newTemp(Ity_I32); + nan_mask[i] = newTemp(Ity_I32); + underflow_mask[i] = newTemp(Ity_I32); + overflow_mask[i] = newTemp(Ity_I32); + error_mask[i] = newTemp(Ity_I32); + error_value[i] = newTemp(Ity_I32); + tmp_64[i] = newTemp(Ity_I64); + + if ( opc2 == 0x1b0 ) { // xvcvdpsxws + assign(Result_32_tmp[i], binop(Iop_F64toI32S, + rmZero, mkexpr( value_f64[i] ) ) ); + + /* result of Iop_CmpF64 is 0x01 if A < -2^31. */ + assign( underflow_mask[i], + unop( Iop_1Sto32, + unop( Iop_32to1, + binop( Iop_CmpF64, + mkexpr( value_f64[i] ), + unop( Iop_ReinterpI64asF64, + mkU64( 0xC1E0000000000000 )))))); + overflow_value = 0x7FFFFFFF; + underflow_value = 0x80000000; + + } else { // xvcvdpuxws + assign( Result_32_tmp[i], + binop( Iop_F64toI32U, + mkU32( Irrm_ZERO ), + mkexpr( value_f64[i] ) ) ); + + /* result of Iop_CmpF64 is 0x01 if A < 0. */ + assign( underflow_mask[i], + unop( Iop_1Sto32, + unop( Iop_32to1, + binop( Iop_CmpF64, + mkexpr( value_f64[i] ), + unop( Iop_ReinterpI64asF64, + mkU64( 0x0 ) ) ) ) ) ); + overflow_value = 0xFFFFFFFF; + underflow_value = 0; + } + + /* Check if input is NaN, output is 0x80000000. + if input < -2^31, output is 0x80000000. + if input > 2^31 - 1, output is 0x7FFFFFFF */ + assign( tmp_64[i], unop (Iop_ReinterpF64asI64, + mkexpr( value_f64[i] ) ) ); + + assign( nan_mask[i], unop( Iop_1Sto32, + is_NaN( Ity_I64, tmp_64[i] ) ) ); + + /* result of Iop_CmpF64 is 0x00 if A > 2^31 - 1. */ + assign( overflow_mask[i], + unop( Iop_1Sto32, + binop( Iop_CmpEQ32, + mkU32( 0 ), + binop( Iop_CmpF64, + mkexpr( value_f64[i] ), + unop( Iop_ReinterpI64asF64, + mkU64( 0x41DFFFFFFFC00000 )))))); + + assign( error_mask[i], binop( Iop_Or32, mkexpr( overflow_mask[i] ), + binop( Iop_Or32, + mkexpr( underflow_mask[i] ), + mkexpr( nan_mask[i] ) ) ) ); + + if ( opc2 == 0x1b0 ) { // xvcvdpsxws + /* NaN takes precedence over underflow/overflow for vxcvdpsxws */ + assign( error_value[i], + binop( Iop_Or32, + binop( Iop_And32, + unop( Iop_Not32, mkexpr( nan_mask[i] ) ), + binop( Iop_Or32, + binop( Iop_And32, + mkexpr( overflow_mask[i] ), + mkU32( overflow_value ) ), + binop( Iop_And32, + mkexpr( underflow_mask[i] ), + mkU32( underflow_value ) ) ) ), + binop( Iop_And32, + mkexpr( nan_mask[i] ), + mkU32( 0x80000000 ) ) ) ); + } else { + /* Less then zeo takes precedence over NaN/overflow + for vxcvdpuxws in the hardware. Matching the HW here + but it does not appear to match ISA. */ + assign( error_value[i], + binop( Iop_Or32, + binop( Iop_And32, + unop( Iop_Not32, + mkexpr( underflow_mask[i] ) ), + binop( Iop_Or32, + binop( Iop_And32, + mkexpr( overflow_mask[i] ), + mkU32( overflow_value ) ), + binop( Iop_And32, + mkexpr( nan_mask[i] ), + mkU32( 0x80000000 ) ) ) ), + binop( Iop_And32, + mkexpr( underflow_mask[i] ), + mkU32( underflow_value ) ) ) ); + } + + assign( Result_32[i], binop( Iop_Or32, + binop( Iop_And32, + mkexpr( Result_32_tmp[i] ), + unop( Iop_Not32, + mkexpr( error_mask[i] ) ) ), + binop( Iop_And32, + mkexpr( error_value[i] ), + mkexpr( error_mask[i] ) ) ) ); + } + + if ( opc2 == 0x1b0 ) { + DIP("xvcvdpsxws v%u,v%u\n", XT, XB); + + } else { + DIP("xvcvdpuxws v%u,v%u", XT, XB); + } + + /* Result is put in the hi and low 32-bits of the double word result. */ putVSReg( XT, - binop( Iop_64HLtoV128, - unop( Iop_32Sto64, mkexpr( hiResult_32 ) ), - unop( Iop_32Sto64, mkexpr( loResult_32 ) ) ) ); + binop( Iop_64HLtoV128, + binop( Iop_32HLto64, + mkexpr( Result_32[0] ), + mkexpr( Result_32[0] ) ), + binop( Iop_32HLto64, + mkexpr( Result_32[1] ), + mkexpr( Result_32[1] ) ) ) ); break; } case 0x130: case 0x110: // xvcvspsxws, xvcvspuxws @@ -16216,22 +16358,6 @@ dis_vx_conv ( UInt theInstr, UInt opc2 ) binop( Iop_F64toI64U, mkU32( Irrm_ZERO ), mkexpr( xB ) ), binop( Iop_F64toI64U, mkU32( Irrm_ZERO ), mkexpr( xB2 ) ) ) ); break; - case 0x190: // xvcvdpuxws (VSX Vector truncate Double-Precision to integer and - // Convert to Unsigned Integer Word format with Saturate) - DIP("xvcvdpuxws v%u,v%u\n", XT, XB); - putVSReg( XT, - binop( Iop_64HLtoV128, - binop( Iop_32HLto64, - binop( Iop_F64toI32U, - mkU32( Irrm_ZERO ), - mkexpr( xB ) ), - mkU32( 0 ) ), - binop( Iop_32HLto64, - binop( Iop_F64toI32U, - mkU32( Irrm_ZERO ), - mkexpr( xB2 ) ), - mkU32( 0 ) ) ) ); - break; case 0x392: // xvcvspdp (VSX Vector Convert Single-Precision to Double-Precision format) DIP("xvcvspdp v%u,v%u\n", XT, XB); putVSReg( XT, |
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From: Carl L. <ca...@so...> - 2019-03-22 17:20:34
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=2da60f569fd5b2e9c8d6361e860731e98cf8053d commit 2da60f569fd5b2e9c8d6361e860731e98cf8053d Author: Carl Love <ca...@us...> Date: Fri Mar 22 12:06:31 2019 -0500 PPC64, fix for vmsummbm instruction. The instruction needs to have the 32-bit "lane" values chopped to 32-bits. The current lane implementation is not doing the chopping. Need to explicitly do the chop and add. Valgrind bug 405362 Diff: --- NEWS | 1 + VEX/priv/guest_ppc_toIR.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/NEWS b/NEWS index a2c055e..c59168b 100644 --- a/NEWS +++ b/NEWS @@ -115,6 +115,7 @@ where XXXXXX is the bug number as listed below. 405716 drd: Fix an integer overflow in the stack margin calculation 405356 PPC64, xvcvsxdsp, xvcvuxdsp are supposed to write the 32-bit result to the upper and lower 32-bits of the 64-bit result +405362 PPC64, vmsummbm instruction doesn't handle overflow case correctly n-i-bz add syswrap for PTRACE_GET|SET_THREAD_AREA on amd64. n-i-bz Fix callgrind_annotate non deterministic order for equal total diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index d6c671a..fb6f989 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -24029,6 +24029,12 @@ static Bool dis_av_multarith ( UInt theInstr ) IRTemp abEO = newTemp(Ity_V128); IRTemp abOE = newTemp(Ity_V128); IRTemp abOO = newTemp(Ity_V128); + IRTemp prod = newTemp(Ity_V128); + IRTemp sum0 = newTemp(Ity_I32); + IRTemp sum1 = newTemp(Ity_I32); + IRTemp sum2 = newTemp(Ity_I32); + IRTemp sum3 = newTemp(Ity_I32); + aEvn = aOdd = bEvn = bOdd = IRTemp_INVALID; DIP("vmsummbm v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr); @@ -24045,11 +24051,53 @@ static Bool dis_av_multarith ( UInt theInstr ) assign( abOO, binop(Iop_MullEven16Sx8, mkexpr(aOdd), mkexpr(bOdd)) ); /* add results together, + vC */ +/* Unfortunately, we need to chop the results of the adds to 32-bits. The + following lane based calculations don't handle the overflow correctly. Need + to explicitly do the adds and 32-bit chops. + putVReg( vD_addr, binop(Iop_QAdd32Sx4, mkexpr(vC), binop(Iop_QAdd32Sx4, binop(Iop_QAdd32Sx4, mkexpr(abEE), mkexpr(abEO)), binop(Iop_QAdd32Sx4, mkexpr(abOE), mkexpr(abOO)))) ); +*/ + + assign(prod, + binop(Iop_QAdd32Sx4, + binop(Iop_QAdd32Sx4, mkexpr(abEE), mkexpr(abEO)), + binop(Iop_QAdd32Sx4, mkexpr(abOE), mkexpr(abOO)))); + assign( sum0, + unop(Iop_64to32, + binop(Iop_Add64, + unop(Iop_32Sto64, + unop(Iop_64HIto32, unop(Iop_V128HIto64, mkexpr(prod)))), + unop(Iop_32Sto64, + unop(Iop_64HIto32, unop(Iop_V128HIto64, mkexpr(vC))))))); + assign( sum1, + unop(Iop_64to32, + binop(Iop_Add64, + unop(Iop_32Sto64, + unop(Iop_64to32, unop(Iop_V128HIto64, mkexpr(prod)))), + unop(Iop_32Sto64, + unop(Iop_64to32, unop(Iop_V128HIto64, mkexpr(vC))))))); + assign( sum2, + unop(Iop_64to32, + binop(Iop_Add64, + unop(Iop_32Sto64, + unop(Iop_64HIto32, unop(Iop_V128to64, mkexpr(prod)))), + unop(Iop_32Sto64, + unop(Iop_64HIto32, unop(Iop_V128to64, mkexpr(vC))))))); + assign( sum3, + unop(Iop_64to32, + binop(Iop_Add64, + unop(Iop_32Sto64, + unop(Iop_64to32, unop(Iop_V128to64, mkexpr(prod)))), + unop(Iop_32Sto64, + unop(Iop_64to32, unop(Iop_V128to64, mkexpr(vC))))))); + putVReg( vD_addr, binop(Iop_64HLtoV128, + binop(Iop_32HLto64, mkexpr(sum0), mkexpr(sum1)), + binop(Iop_32HLto64, mkexpr(sum2), mkexpr(sum3)))); + break; } case 0x26: { // vmsumuhm (Multiply Sum Unsigned HW Modulo, AV p205) |
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From: Carl L. <ca...@so...> - 2019-03-22 17:03:16
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=886b0a1cf49412cfa597253a122dcd8bbc89fc49 commit 886b0a1cf49412cfa597253a122dcd8bbc89fc49 Author: Carl Love <ca...@us...> Date: Fri Mar 22 11:56:38 2019 -0500 PPC64, fix implementation of xvcvsxdsp and xvcvuxddp instructions. Instructions need to write result to upper and lower 32-bit half of the 64-bit result. This is a fix for Valgrind bug 405356. Diff: --- NEWS | 2 ++ VEX/priv/guest_ppc_toIR.c | 91 ++++++++++++++++++++++++++++------------------- 2 files changed, 57 insertions(+), 36 deletions(-) diff --git a/NEWS b/NEWS index a460d8e..a2c055e 100644 --- a/NEWS +++ b/NEWS @@ -113,6 +113,8 @@ where XXXXXX is the bug number as listed below. 405403 s390x disassembler cannot be used on x86 405458 MIPS mkFormVEC arguments swapped? 405716 drd: Fix an integer overflow in the stack margin calculation +405356 PPC64, xvcvsxdsp, xvcvuxdsp are supposed to write the 32-bit result to + the upper and lower 32-bits of the 64-bit result n-i-bz add syswrap for PTRACE_GET|SET_THREAD_AREA on amd64. n-i-bz Fix callgrind_annotate non deterministic order for equal total diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index 00ae6df..d6c671a 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -16312,52 +16312,71 @@ dis_vx_conv ( UInt theInstr, UInt opc2 ) break; case 0x370: // xvcvsxdsp (VSX Vector Convert and round Signed Integer Doubleword // to Single-Precision format) - DIP("xvcvsxddp v%u,v%u\n", XT, XB); + { + IRTemp result32hi = newTemp(Ity_I32); + IRTemp result32lo = newTemp(Ity_I32); + + DIP("xvcvsxdsp v%u,v%u\n", XT, XB); + assign( result32hi, + unop( Iop_ReinterpF32asI32, + unop( Iop_TruncF64asF32, + binop( Iop_RoundF64toF32, + get_IR_roundingmode(), + binop( Iop_I64StoF64, + get_IR_roundingmode(), + mkexpr( xB ) ) ) ) ) ); + assign( result32lo, + unop( Iop_ReinterpF32asI32, + unop( Iop_TruncF64asF32, + binop( Iop_RoundF64toF32, + get_IR_roundingmode(), + binop( Iop_I64StoF64, + get_IR_roundingmode(), + mkexpr( xB2 ) ) ) ) ) ); + putVSReg( XT, binop( Iop_64HLtoV128, binop( Iop_32HLto64, - unop( Iop_ReinterpF32asI32, - unop( Iop_TruncF64asF32, - binop( Iop_RoundF64toF32, - get_IR_roundingmode(), - binop( Iop_I64StoF64, - get_IR_roundingmode(), - mkexpr( xB ) ) ) ) ), - mkU32( 0 ) ), + mkexpr( result32hi ), + mkexpr( result32hi ) ), binop( Iop_32HLto64, - unop( Iop_ReinterpF32asI32, - unop( Iop_TruncF64asF32, - binop( Iop_RoundF64toF32, - get_IR_roundingmode(), - binop( Iop_I64StoF64, - get_IR_roundingmode(), - mkexpr( xB2 ) ) ) ) ), - mkU32( 0 ) ) ) ); - break; + mkexpr( result32lo ), + mkexpr( result32lo ) ) ) ); + } + break; case 0x350: // xvcvuxdsp (VSX Vector Convert and round Unsigned Integer Doubleword // to Single-Precision format) - DIP("xvcvuxddp v%u,v%u\n", XT, XB); + { + IRTemp result32hi = newTemp(Ity_I32); + IRTemp result32lo = newTemp(Ity_I32); + + DIP("xvcvuxdsp v%u,v%u\n", XT, XB); + assign( result32hi, + unop( Iop_ReinterpF32asI32, + unop( Iop_TruncF64asF32, + binop( Iop_RoundF64toF32, + get_IR_roundingmode(), + binop( Iop_I64UtoF64, + get_IR_roundingmode(), + mkexpr( xB ) ) ) ) ) ); + assign( result32lo, + unop( Iop_ReinterpF32asI32, + unop( Iop_TruncF64asF32, + binop( Iop_RoundF64toF32, + get_IR_roundingmode(), + binop( Iop_I64UtoF64, + get_IR_roundingmode(), + mkexpr( xB2 ) ) ) ) ) ); putVSReg( XT, binop( Iop_64HLtoV128, binop( Iop_32HLto64, - unop( Iop_ReinterpF32asI32, - unop( Iop_TruncF64asF32, - binop( Iop_RoundF64toF32, - get_IR_roundingmode(), - binop( Iop_I64UtoF64, - get_IR_roundingmode(), - mkexpr( xB ) ) ) ) ), - mkU32( 0 ) ), + mkexpr( result32hi ), + mkexpr( result32hi ) ), binop( Iop_32HLto64, - unop( Iop_ReinterpF32asI32, - unop( Iop_TruncF64asF32, - binop( Iop_RoundF64toF32, - get_IR_roundingmode(), - binop( Iop_I64UtoF64, - get_IR_roundingmode(), - mkexpr( xB2 ) ) ) ) ), - mkU32( 0 ) ) ) ); - break; + mkexpr( result32lo ), + mkexpr( result32lo ) ) ) ); + } + break; case 0x1f0: // xvcvsxwdp (VSX Vector Convert Signed Integer Word to Double-Precision format) DIP("xvcvsxwdp v%u,v%u\n", XT, XB); |
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From: Bart V. A. <bva...@so...> - 2019-03-22 03:09:50
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=30b3264e60aea7c0b5d6578f6bb87087fd99ff05 commit 30b3264e60aea7c0b5d6578f6bb87087fd99ff05 Author: Bart Van Assche <bva...@ac...> Date: Thu Mar 21 20:08:45 2019 -0700 drd: Fix an integer overflow in the stack margin calculation Diff: --- NEWS | 1 + drd/drd_main.c | 5 ++--- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/NEWS b/NEWS index c9431a2..a460d8e 100644 --- a/NEWS +++ b/NEWS @@ -112,6 +112,7 @@ where XXXXXX is the bug number as listed below. 405079 unhandled ppc64le-linux syscall: 131 (quotactl) 405403 s390x disassembler cannot be used on x86 405458 MIPS mkFormVEC arguments swapped? +405716 drd: Fix an integer overflow in the stack margin calculation n-i-bz add syswrap for PTRACE_GET|SET_THREAD_AREA on amd64. n-i-bz Fix callgrind_annotate non deterministic order for equal total diff --git a/drd/drd_main.c b/drd/drd_main.c index 3df967e..6d6ca63 100644 --- a/drd/drd_main.c +++ b/drd/drd_main.c @@ -705,12 +705,11 @@ static void drd_thread_finished(ThreadId vg_tid) = (DRD_(thread_get_stack_max)(drd_tid) - DRD_(thread_get_stack_min_min)(drd_tid)); VG_(message)(Vg_UserMsg, - "thread %u%s finished and used %lu bytes out of %lu" - " on its stack. Margin: %lu bytes.\n", + "thread %u%s finished and used %lu bytes out of %lu on its stack. Margin: %ld bytes.\n", drd_tid, DRD_(thread_get_joinable)(drd_tid) ? "" : " (which is a detached thread)", - used_stack, stack_size, stack_size - used_stack); + used_stack, stack_size, (long)(stack_size - used_stack)); } drd_stop_using_mem(DRD_(thread_get_stack_min)(drd_tid), |