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From: Rhys K. <rhy...@gm...> - 2019-02-03 03:56:48
|
Avoid use of two manners of setting automake configuration options, and consolidate them into AM_INIT_AUTOMAKE macro. Signed-off-by: Rhys Kidd <rhy...@gm...> --- Makefile.am | 2 +- configure.ac | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile.am b/Makefile.am index 631c845ab..a63cd9bde 100644 --- a/Makefile.am +++ b/Makefile.am @@ -1,5 +1,5 @@ -AUTOMAKE_OPTIONS = foreign 1.10 dist-bzip2 +AUTOMAKE_OPTIONS = 1.10 include $(top_srcdir)/Makefile.all.am diff --git a/configure.ac b/configure.ac index b69935e9b..d0b68b46b 100644 --- a/configure.ac +++ b/configure.ac @@ -11,7 +11,7 @@ AC_INIT([Valgrind],[3.15.0.GIT],[val...@li...]) AC_CONFIG_SRCDIR(coregrind/m_main.c) AC_CONFIG_HEADERS([config.h]) -AM_INIT_AUTOMAKE([foreign subdir-objects]) +AM_INIT_AUTOMAKE([foreign dist-bzip2 subdir-objects]) AM_MAINTAINER_MODE -- 2.19.1 |
|
From: Rhys K. <rhy...@gm...> - 2019-02-03 03:56:48
|
Since f38d96d -fno-stack-protector has been added to $(AM_CFLAGS_BASE) on all
platforms, if the compiler supports it. Accordingly, there's no need to still add
this a second time specifically for macOS.
Fixes: f38d96d ("Add -Wformat -Wformat-security to the list of compile flags.")
Signed-off-by: Rhys Kidd <rhy...@gm...>
---
Makefile.all.am | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Makefile.all.am b/Makefile.all.am
index 2ad54034f..daa7e413f 100644
--- a/Makefile.all.am
+++ b/Makefile.all.am
@@ -222,14 +222,14 @@ AM_CCASFLAGS_ARM64_LINUX = @FLAG_M64@ -g
AM_FLAG_M3264_X86_DARWIN = -arch i386
AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
-mmacosx-version-min=10.6 \
- -fno-stack-protector -fno-pic -fno-PIC
+ -fno-pic -fno-PIC
AM_CFLAGS_PSO_X86_DARWIN = $(AM_CFLAGS_X86_DARWIN) $(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_X86_DARWIN = -arch i386 -g
AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
- -mmacosx-version-min=10.6 -fno-stack-protector
+ -mmacosx-version-min=10.6
AM_CFLAGS_PSO_AMD64_DARWIN = $(AM_CFLAGS_AMD64_DARWIN) $(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_AMD64_DARWIN = -arch x86_64 -g
--
2.19.1
|
|
From: Rhys K. <rhy...@gm...> - 2019-02-03 03:56:48
|
Autoconf says:
"This macro is obsolescent, as current systems have conforming
header files. New programs need not use this macro".
Was previously required to ensure the system has C header files conforming
to ANSI C89 (ISO C90). Specifically, this macro checks for stdlib.h,
stdarg.h, string.h, and float.h.
This autoconf option was used to provide conditional fallback support
via defined STDC_HEADERS.
valgrind does not utilize conditional fallback support so, so this macro
is both obsolete and unused, so let's drop it.
Signed-off-by: Rhys Kidd <rhy...@gm...>
---
configure.ac | 1 -
1 file changed, 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index b885bd91b..b69935e9b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -4011,7 +4011,6 @@ fi # test "$VGCONF_OS" = "solaris"
# Checks for C header files.
#----------------------------------------------------------------------------
-AC_HEADER_STDC
AC_CHECK_HEADERS([ \
asm/unistd.h \
endian.h \
--
2.19.1
|
|
From: Rhys K. <rhy...@gm...> - 2019-02-03 03:56:46
|
This approach is utilized consistently throughout the file, and would make alphabetical reordering easier. Adopt it here as well. Signed-off-by: Rhys Kidd <rhy...@gm...> --- Makefile.am | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Makefile.am b/Makefile.am index a63cd9bde..0458c931d 100644 --- a/Makefile.am +++ b/Makefile.am @@ -3,7 +3,8 @@ AUTOMAKE_OPTIONS = 1.10 include $(top_srcdir)/Makefile.all.am -TOOLS = memcheck \ +TOOLS = \ + memcheck \ cachegrind \ callgrind \ helgrind \ @@ -13,7 +14,8 @@ TOOLS = memcheck \ lackey \ none -EXP_TOOLS = exp-sgcheck \ +EXP_TOOLS = \ + exp-sgcheck \ exp-bbv # Put docs last because building the HTML is slow and we want to get -- 2.19.1 |
|
From: Rhys K. <rhy...@gm...> - 2019-02-03 03:56:46
|
A short series of autotools-related cleanup patches. I'd appreciate if I could get a review from at least one of the other valgrind developers before I actually commit these patches to master. It started out as some small things noticed whilst looking at a larger feature and here we are six patches later. The series itself should be fairly straightforward. Has been tested on macOS 10.11, 10.12 and 10.13 and Ubuntu 16.04. The series itself can also be found on my GitHub repo at: https://github.com/Echelon9/valgrind/tree/series/autotools-series An interested reviewer could add the repo, check out a local branch with the patches and re-build valgrind as follows: # Add repo and checkout a local branch with the patches git remote add rhyskidd-gh https://github.com/Echelon9/valgrind.git git checkout -b series/autotools-series rhyskidd-gh/series/autotools-series # Clean build environment, re-run autotools and build make distclean ./autogen.sh && ./configure && make === I also wonder whether valgrind should be explicit about a minimum supported version of autoconf (via AC_PREREQ() macro)? This would allow some of the existing backwards compatible hacks to be dropped. The only current location that a minimum version is mentioned is at http://valgrind.org/downloads/repository.html, where autoconf >=2.68 is stated as a dependency upon automake >= 1.10. A minimum automake version dependency is currently specified in the code. Thoughts? Cc: Julian Seward <js...@ac...> Cc: Philippe Waroquiers <phi...@sk...> Cc: Ivo Raisr <iv...@iv...> Cc: Petar Jovanovic <mip...@gm...> Cc: Mark Wielaard <ma...@kl...> Rhys Kidd (6): config: remove unrequired AC_HEADER_STDC config: Set automake options consistenly in one location Makefile.am: Consistent indent and align config: Conditionalize -finline-functions on compiler support macOS: Don't duplicate -fno-stack-protector Add missing documentation file from EXTRA_DIST Makefile.all.am | 7 ++++--- Makefile.am | 9 ++++++--- configure.ac | 24 ++++++++++++++++++++++-- 3 files changed, 32 insertions(+), 8 deletions(-) -- 2.19.1 |
|
From: Julian S. <se...@so...> - 2019-02-02 15:11:57
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=cad6b8a984c99a198c8648a556c4c4f62d02489e commit cad6b8a984c99a198c8648a556c4c4f62d02489e Author: Julian Seward <js...@ac...> Date: Sat Feb 2 16:10:50 2019 +0100 Fix "make post-regtest-checks" after 441bfc5f51c7f5f80cc6491d23cbe2dc711d191f (dhat overhaul). Diff: --- tests/check_headers_and_includes | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/check_headers_and_includes b/tests/check_headers_and_includes index 1c3e3f5..49a51e1 100755 --- a/tests/check_headers_and_includes +++ b/tests/check_headers_and_includes @@ -52,7 +52,7 @@ my %tool_dirs = ( "lackey" => 1, "none" => 1, "exp-bbv" => 1, - "exp-sgcheck" => 1 + "exp-sgcheck" => 1, "shared" => 1, ); |
|
From: Julian S. <se...@so...> - 2019-02-02 13:23:51
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=7094b51f0a22f7f264732a2bfc840b00b74a7c23 commit 7094b51f0a22f7f264732a2bfc840b00b74a7c23 Author: Julian Seward <js...@ac...> Date: Sat Feb 2 14:22:43 2019 +0100 Another -Wformat-signedness fix that was missed in dee1c5ac841ef11151ddf92b1ca98be7041f0785. Diff: --- coregrind/m_gdbserver/remote-utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/coregrind/m_gdbserver/remote-utils.c b/coregrind/m_gdbserver/remote-utils.c index 2d4320c..2d13b79 100644 --- a/coregrind/m_gdbserver/remote-utils.c +++ b/coregrind/m_gdbserver/remote-utils.c @@ -1158,7 +1158,7 @@ void prepare_resume_reply (char *buf, char status, unsigned char sig) VG_(sprintf) (buf, "%s:%x;", valgrind_stopped_before_syscall () ? "syscall_entry" : "syscall_return", - valgrind_stopped_by_syscall ()); + (UInt)valgrind_stopped_by_syscall ()); buf += strlen (buf); } |
|
From: Julian S. <se...@so...> - 2019-02-02 13:22:10
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=cadbb5d441acf1925f4707d8012db77c02766cc2 commit cadbb5d441acf1925f4707d8012db77c02766cc2 Author: Julian Seward <js...@ac...> Date: Sat Feb 2 14:20:49 2019 +0100 Enable -Wformat-signedness, if the compiler supports it. Diff: --- configure.ac | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/configure.ac b/configure.ac index a02a76b..b885bd9 100644 --- a/configure.ac +++ b/configure.ac @@ -2095,18 +2095,11 @@ AC_GCC_WARNING_SUBST_NO([unused-function], [FLAG_W_NO_UNUSED_FUNCTION]) AC_GCC_WARNING_SUBST_NO([static-local-in-inline], [FLAG_W_NO_STATIC_LOCAL_IN_INLINE]) AC_GCC_WARNING_SUBST_NO([mismatched-new-delete], [FLAG_W_NO_MISMATCHED_NEW_DELETE]) AC_GCC_WARNING_SUBST_NO([infinite-recursion], [FLAG_W_NO_INFINITE_RECURSION]) + AC_GCC_WARNING_SUBST([write-strings], [FLAG_W_WRITE_STRINGS]) AC_GCC_WARNING_SUBST([empty-body], [FLAG_W_EMPTY_BODY]) AC_GCC_WARNING_SUBST([format], [FLAG_W_FORMAT]) -# Disabled for now until all platforms are clean -format_checking_enabled=no -#format_checking_enabled=yes -if test "$format_checking_enabled" = "yes"; then - AC_GCC_WARNING_SUBST([format-signedness], [FLAG_W_FORMAT_SIGNEDNESS]) -else - dumy_assignment_to_avoid_syntax_errors=1 - AC_SUBST([FLAG_W_FORMAT_SIGNEDNESS], []) -fi +AC_GCC_WARNING_SUBST([format-signedness], [FLAG_W_FORMAT_SIGNEDNESS]) AC_GCC_WARNING_SUBST([cast-qual], [FLAG_W_CAST_QUAL]) AC_GCC_WARNING_SUBST([old-style-declaration], [FLAG_W_OLD_STYLE_DECLARATION]) AC_GCC_WARNING_SUBST([ignored-qualifiers], [FLAG_W_IGNORED_QUALIFIERS]) |
|
From: Julian S. <se...@so...> - 2019-02-02 13:07:52
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=dee1c5ac841ef11151ddf92b1ca98be7041f0785 commit dee1c5ac841ef11151ddf92b1ca98be7041f0785 Author: Julian Seward <js...@ac...> Date: Sat Feb 2 14:03:17 2019 +0100 Fix format string warnings from gcc9. No functional change (I think!) Diff: --- VEX/priv/guest_arm_toIR.c | 2 +- VEX/priv/guest_mips_toIR.c | 18 +++--- VEX/priv/guest_ppc_toIR.c | 114 ++++++++++++++++++------------------ coregrind/m_gdbserver/m_gdbserver.c | 2 +- coregrind/m_libcassert.c | 2 +- coregrind/m_signals.c | 2 +- coregrind/m_syswrap/syswrap-linux.c | 4 +- coregrind/m_xtree.c | 20 +++---- helgrind/libhb_core.c | 4 +- 9 files changed, 84 insertions(+), 84 deletions(-) diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c index ff426be..35a62a1 100644 --- a/VEX/priv/guest_arm_toIR.c +++ b/VEX/priv/guest_arm_toIR.c @@ -12816,7 +12816,7 @@ static Bool decode_V8_instruction ( stmt(IRStmt_Dirty(di)); putQReg(regD >> 1, mkexpr(res), IRTemp_INVALID); - DIP("%s.8 q%d, q%d\n", iNames[opc], regD >> 1, regM >> 1); + DIP("%s.8 q%u, q%u\n", iNames[opc], regD >> 1, regM >> 1); return True; } /* fall through */ diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c index f8ef88f..e2eeb0a 100644 --- a/VEX/priv/guest_mips_toIR.c +++ b/VEX/priv/guest_mips_toIR.c @@ -26183,25 +26183,25 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, switch (df) { case 0x00: { /* BNZ.B */ - DIP("BNZ.B w%d, %d", ft, imm); + DIP("BNZ.B w%u, %u", ft, imm); assign(t3, binop(Iop_CmpEQ8x16, mkexpr(t1), mkexpr(t2))); break; } case 0x01: { /* BNZ.H */ - DIP("BNZ.H w%d, %d", ft, imm); + DIP("BNZ.H w%u, %u", ft, imm); assign(t3, binop(Iop_CmpEQ16x8, mkexpr(t1), mkexpr(t2))); break; } case 0x02: { /* BNZ.W */ - DIP("BNZ.W w%d, %d", ft, imm); + DIP("BNZ.W w%u, %u", ft, imm); assign(t3, binop(Iop_CmpEQ32x4, mkexpr(t1), mkexpr(t2))); break; } case 0x03: { /* BNZ.D */ - DIP("BNZ.D w%d, %d", ft, imm); + DIP("BNZ.D w%u, %u", ft, imm); assign(t3, binop(Iop_CmpEQ64x2, mkexpr(t1), mkexpr(t2))); break; } @@ -26245,25 +26245,25 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, switch (df) { case 0x00: { /* BZ.B */ - DIP("BZ.B w%d, %d", ft, imm); + DIP("BZ.B w%u, %u", ft, imm); assign(t3, binop(Iop_CmpEQ8x16, mkexpr(t1), mkexpr(t2))); break; } case 0x01: { /* BZ.H */ - DIP("BZ.H w%d, %d", ft, imm); + DIP("BZ.H w%u, %u", ft, imm); assign(t3, binop(Iop_CmpEQ16x8, mkexpr(t1), mkexpr(t2))); break; } case 0x02: { /* BZ.W */ - DIP("BZ.W w%d, %d", ft, imm); + DIP("BZ.W w%u, %u", ft, imm); assign(t3, binop(Iop_CmpEQ32x4, mkexpr(t1), mkexpr(t2))); break; } case 0x03: { /* BZ.D */ - DIP("BZ.D w%d, %d", ft, imm); + DIP("BZ.D w%u, %u", ft, imm); assign(t3, binop(Iop_CmpEQ64x2, mkexpr(t1), mkexpr(t2))); break; } @@ -29959,7 +29959,7 @@ static DisResult disInstr_MIPS_WRK ( Bool(*resteerOkFn) (/*opaque */void *, } case 0x08 ... 0x0f: { /* DALIGN */ if (VEX_MIPS_CPU_HAS_MIPSR6(archinfo->hwcaps)) { - DIP("daling r%u, r%u, r%u, %d", rd, rs, rt, lsb & 0x7); + DIP("daling r%u, r%u, r%u, %u", rd, rs, rt, lsb & 0x7); UInt bp = (lsb & 0x7) << 3; if (bp) { putIReg(rd, binop(Iop_Or64, diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c index c2d28f2..e207642 100644 --- a/VEX/priv/guest_ppc_toIR.c +++ b/VEX/priv/guest_ppc_toIR.c @@ -6138,7 +6138,7 @@ static Bool dis_int_misc ( UInt theInstr ) switch (opc2) { case 0x01E: // wait, (X-from) - DIP("wait %u\n", wc); + DIP("wait %d\n", wc); /* The wait instruction causes instruction fetching and execution * to be suspended. Instruction fetching and execution are resumed @@ -8577,7 +8577,7 @@ static Bool dis_memsync ( UInt theInstr ) vex_printf("dis_memsync(ppc)(mbar,b11to20|b0)\n"); return False; } - DIP("mbar %d\n", M0); + DIP("mbar %u\n", M0); } /* Insert a memory fence, just to be on the safe side. */ stmt( IRStmt_MBE(Imbe_Fence) ); @@ -11556,7 +11556,7 @@ static Bool dis_fp_pair ( UInt theInstr ) break; case 0x2: // lxsd (Load VSX Scalar Doubleword) - DIP("lxsd v%u,%d(r%u)\n", vRT, DS, rA_addr); + DIP("lxsd v%u,%u(r%u)\n", vRT, DS, rA_addr); assign( EA, ea_rAor0_simm( rA_addr, DS<<2 ) ); @@ -11567,7 +11567,7 @@ static Bool dis_fp_pair ( UInt theInstr ) case 0x3: // lxssp (Load VSX Scalar Single from memory, // store as double in register) - DIP("lxssp v%u,%d(r%u)\n", vRT, DS, rA_addr); + DIP("lxssp v%u,%u(r%u)\n", vRT, DS, rA_addr); assign( EA, ea_rAor0_simm( rA_addr, DS<<2 ) ); @@ -11624,7 +11624,7 @@ static Bool dis_fp_pair ( UInt theInstr ) if ( IFIELD( theInstr, 0, 3) == 1) { // lxv (Load VSX Vector) - DIP("lxv v%u,%d(r%u)\n", vRS, DS, rA_addr); + DIP("lxv v%u,%u(r%u)\n", vRS, DS, rA_addr); assign( word[0], load( Ity_I64, mkexpr( EA ) ) ); @@ -11645,7 +11645,7 @@ static Bool dis_fp_pair ( UInt theInstr ) } else if ( IFIELD( theInstr, 0, 3) == 5) { // stxv (Store VSX Vector) - DIP("stxv v%u,%d(r%u)\n", vRS, DS, rA_addr); + DIP("stxv v%u,%u(r%u)\n", vRS, DS, rA_addr); if (host_endness == VexEndnessBE) { store( mkexpr(EA), unop( Iop_V128HIto64, @@ -11672,7 +11672,7 @@ static Bool dis_fp_pair ( UInt theInstr ) } case 0x2: // stxsd (Store VSX Scalar Doubleword) - DIP("stxsd v%u,%d(r%u)\n", vRS, DS, rA_addr); + DIP("stxsd v%u,%u(r%u)\n", vRS, DS, rA_addr); assign( EA, ea_rAor0_simm( rA_addr, DS<<2 ) ); @@ -11694,7 +11694,7 @@ static Bool dis_fp_pair ( UInt theInstr ) IRTemp high64 = newTemp(Ity_F64); IRTemp val32 = newTemp(Ity_I32); - DIP("stxssp v%u,%d(r%u)\n", vRS, DS, rA_addr); + DIP("stxssp v%u,%u(r%u)\n", vRS, DS, rA_addr); assign( EA, ea_rAor0_simm( rA_addr, DS<<2 ) ); assign(high64, unop( Iop_ReinterpI64asF64, @@ -12041,7 +12041,7 @@ static Bool dis_fp_scr ( UInt theInstr, Bool GX_level ) putGST_masked( PPC_GST_FPSCR, mkexpr( frB_int ), MASK_FPSCR_DRN ); } else if ((b11to12 == 2) && (b13to15 == 5)) { - DIP("mffscdrni fr%u,%d\n", frD_addr, DRN); + DIP("mffscdrni fr%u,%u\n", frD_addr, DRN); /* Clear all of the FPSCR bits except for the DRN field, VE, OE, UE, ZE and XE bits and write the result to the frD @@ -18621,7 +18621,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, UInt uim = IFIELD( theInstr, 11, 8 ); UInt word_value = ( uim << 24 ) | ( uim << 16 ) | ( uim << 8 ) | uim; - DIP("xxspltib v%d,%d\n", (UInt)XT, uim); + DIP("xxspltib v%u,%u\n", (UInt)XT, uim); putVSReg(XT, binop( Iop_64HLtoV128, binop( Iop_32HLto64, mkU32( word_value ), @@ -18647,7 +18647,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, IRTemp vB_hi = newTemp( Ity_I64 ); IRExpr *mask = mkU64( 0x7FF0000000000000 ); - DIP("xscmpexpdp %d,v%d,v%d\n", BF, XA, XB); + DIP("xscmpexpdp %u,v%u,v%u\n", BF, XA, XB); assign( vA_hi, unop( Iop_V128HIto64, mkexpr( vA ) ) ); assign( vB_hi, unop( Iop_V128HIto64, mkexpr( vB ) ) ); @@ -18708,7 +18708,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, { UInt uim = IFIELD( theInstr, 16, 4 ); - DIP("xxextractuw v%d,v%d,%d\n", (UInt)XT, (UInt)XB, uim); + DIP("xxextractuw v%u,v%u,%u\n", (UInt)XT, (UInt)XB, uim); putVSReg( XT, binop( Iop_ShlV128, @@ -18728,7 +18728,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, IRTemp vT = newTemp( Ity_V128 ); IRTemp tmp = newTemp( Ity_V128 ); - DIP("xxinsertw v%d,v%d,%d\n", (UInt)XT, (UInt)XB, uim); + DIP("xxinsertw v%u,v%u,%u\n", (UInt)XT, (UInt)XB, uim); assign( vT, getVSReg( XT ) ); assign( tmp, binop( Iop_AndV128, @@ -18773,7 +18773,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, binop(Iop_ShlV128, mkexpr(vB), mkU8(1)), mkU8(1))); } - DIP("xsabsdp v%d,v%d\n", XT, XB); + DIP("xsabsdp v%u,v%u\n", XT, XB); putVSReg(XT, mkexpr(absVal)); break; } @@ -18789,7 +18789,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, UInt inst_select = IFIELD( theInstr, 16, 5); if (inst_select == 0) { - DIP("xsxexpd %d,v%d\n", (UInt)XT, (UInt)XB); + DIP("xsxexpd %u,v%u\n", (UInt)XT, (UInt)XB); assign( rT, binop( Iop_Shr64, binop( Iop_And64, @@ -18800,7 +18800,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, IRExpr *normal; IRTemp tmp = newTemp(Ity_I64); - DIP("xsxsigdp v%d,v%d\n", (UInt)XT, (UInt)XB); + DIP("xsxsigdp v%u,v%u\n", (UInt)XT, (UInt)XB); assign( tmp, unop( Iop_V128HIto64, mkexpr( vB ) ) ); @@ -18829,7 +18829,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, * is undefined. */ - DIP("xscvhpdp v%d, v%d\n", (UInt)XT, (UInt)XB); + DIP("xscvhpdp v%u, v%u\n", (UInt)XT, (UInt)XB); assign( result, unop( Iop_F16toF64x2, mkexpr( vB ) ) ); putVSReg( XT, mkexpr( result ) ); @@ -18845,7 +18845,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, * the V128 and stores the 16-bit result in the upper word of the * V128 result. The contents of the lower 64-bits is undefined. */ - DIP("xscvdphp v%d, v%d\n", (UInt)XT, (UInt)XB); + DIP("xscvdphp v%u, v%u\n", (UInt)XT, (UInt)XB); assign( result, unop( Iop_F64toF16x2_DEP, mkexpr( vB ) ) ); assign( value, unop( Iop_64to32, unop( Iop_V128HIto64, mkexpr( result ) ) ) ); @@ -18855,7 +18855,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, } else { vex_printf( "dis_vxv_scalar_extract_exp_sig invalid inst_select (ppc)(opc2)\n" ); - vex_printf("inst_select = %d\n", inst_select); + vex_printf("inst_select = %u\n", inst_select); return False; } } @@ -18896,7 +18896,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, assign( zero, unop( Iop_1Uto64, is_Zero( Ity_I64, vB_hi ) ) ); if (opc2 == 0x254) { - DIP("xststdcsp %d,v%d,%d\n", BF, (UInt)XB, DCMX_mask); + DIP("xststdcsp %u,v%u,%u\n", BF, (UInt)XB, DCMX_mask); /* The least significant bit of the CC is set to 1 if the double precision value is not representable as a single precision @@ -18929,7 +18929,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, mkU64( 0x0 ) ) ) ) ) ); } else { - DIP("xststdcdp %d,v%d,%d\n", BF, (UInt)XB, DCMX_mask); + DIP("xststdcdp %u,v%u,%u\n", BF, (UInt)XB, DCMX_mask); assign( not_sp, mkU64( 0 ) ); assign( dnorm, unop( Iop_1Uto64, is_Denorm( Ity_I64, vB_hi ) ) ); } @@ -19162,7 +19162,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, IRTemp dnorm[4]; Int i; - DIP("xvtstdcsp v%d,v%d,%d\n", (UInt)XT, (UInt)XB, DCMX_mask); + DIP("xvtstdcsp v%u,v%u,%u\n", (UInt)XT, (UInt)XB, DCMX_mask); for (i = 0; i < 4; i++) { NaN[i] = newTemp(Ity_I32); @@ -19297,7 +19297,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, IRTemp rA = newTemp( Ity_I64 ); IRTemp rB = newTemp( Ity_I64 ); - DIP("xsiexpdp v%d,%d,%d\n", (UInt)XT, (UInt)rA_addr, (UInt)rB_addr); + DIP("xsiexpdp v%u,%u,%u\n", (UInt)XT, (UInt)rA_addr, (UInt)rB_addr); assign( rA, getIReg(rA_addr)); assign( rB, getIReg(rB_addr)); @@ -19394,7 +19394,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, IRTemp sub_element0 = newTemp( Ity_V128 ); IRTemp sub_element1 = newTemp( Ity_V128 ); - DIP("xxbrh v%d, v%d\n", (UInt)XT, (UInt)XB); + DIP("xxbrh v%u, v%u\n", (UInt)XT, (UInt)XB); assign( sub_element0, binop( Iop_ShrV128, @@ -19492,7 +19492,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, IRTemp sub_element2 = newTemp( Ity_V128 ); IRTemp sub_element3 = newTemp( Ity_V128 ); - DIP("xxbrw v%d, v%d\n", (UInt)XT, (UInt)XB); + DIP("xxbrw v%u, v%u\n", (UInt)XT, (UInt)XB); assign( sub_element0, binop( Iop_ShrV128, @@ -19537,7 +19537,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, mkexpr( sub_element0 ) ) ) ); } else if (inst_select == 23) { - DIP("xxbrd v%d, v%d\n", (UInt)XT, (UInt)XB); + DIP("xxbrd v%u, v%u\n", (UInt)XT, (UInt)XB); int i; int shift = 56; @@ -19665,7 +19665,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, IRTemp sub_element[16]; IRTemp new_xT[9]; - DIP("xxbrq v%d, v%d\n", (UInt) XT, (UInt) XB); + DIP("xxbrq v%u, v%u\n", (UInt) XT, (UInt) XB); new_xT[0] = newTemp( Ity_V128 ); assign( new_xT[0], binop( Iop_64HLtoV128, @@ -19726,7 +19726,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2, IRTemp value[2]; Int i; - DIP("xvtstdcdp v%d,v%d,%d\n", (UInt)XT, (UInt)XB, DCMX_mask); + DIP("xvtstdcdp v%u,v%u,%u\n", (UInt)XT, (UInt)XB, DCMX_mask); for (i = 0; i < 2; i++) { NaN[i] = newTemp(Ity_I64); @@ -20217,7 +20217,7 @@ dis_vx_load ( UInt theInstr ) IRTemp word[4]; int i; - DIP("lxvx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); + DIP("lxvx %u,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); if ( host_endness == VexEndnessBE ) { for ( i = 3; i>= 0; i-- ) { @@ -20273,7 +20273,7 @@ dis_vx_load ( UInt theInstr ) case 0x10D: // lxvl { - DIP("lxvl %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); + DIP("lxvl %u,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); IRTemp byte[16]; UInt i; @@ -20447,7 +20447,7 @@ dis_vx_load ( UInt theInstr ) IRTemp base_addr = newTemp( ty ); IRTemp nb_compare_zero = newTemp( Ity_I64 ); - DIP("lxvll %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); + DIP("lxvll %u,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); tmp_low[0] = newTemp(Ity_I64); tmp_hi[0] = newTemp(Ity_I64); @@ -20536,7 +20536,7 @@ dis_vx_load ( UInt theInstr ) { IRTemp data = newTemp( Ity_I64 ); - DIP("lxvwsx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); + DIP("lxvwsx %u,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); /* The load is a 64-bit fetch that is Endian aware, just want * the lower 32 bits. */ @@ -20607,7 +20607,7 @@ dis_vx_load ( UInt theInstr ) IRExpr *byte; IRExpr* irx_addr; - DIP("lxsibzx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); + DIP("lxsibzx %u,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); if ( host_endness == VexEndnessBE ) irx_addr = binop( Iop_Sub64, mkexpr( EA ), mkU64( 7 ) ); @@ -20629,7 +20629,7 @@ dis_vx_load ( UInt theInstr ) IRExpr *byte; IRExpr* irx_addr; - DIP("lxsihzx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); + DIP("lxsihzx %u,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); if ( host_endness == VexEndnessBE ) irx_addr = binop( Iop_Sub64, mkexpr( EA ), mkU64( 6 ) ); @@ -20677,7 +20677,7 @@ dis_vx_load ( UInt theInstr ) { IRExpr *t0; - DIP("lxvw4x %d,r%u,r%u\n", XT, rA_addr, rB_addr); + DIP("lxvw4x %u,r%u,r%u\n", XT, rA_addr, rB_addr); /* The load will result in the data being in BE order. */ if (host_endness == VexEndnessLE) { @@ -20701,7 +20701,7 @@ dis_vx_load ( UInt theInstr ) case 0x32C: // lxvh8x { - DIP("lxvh8x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); + DIP("lxvh8x %u,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); IRTemp h_word[8]; int i; @@ -20757,7 +20757,7 @@ dis_vx_load ( UInt theInstr ) case 0x36C: // lxvb16x { - DIP("lxvb16x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); + DIP("lxvb16x %u,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr); /* The result of lxvb16x should be the same on big and little endian systems. We do a host load, then reverse the bytes in @@ -20814,7 +20814,7 @@ dis_vx_move ( UInt theInstr ) switch (opc2) { case 0x133: // mfvsrld RA,XS Move From VSR Lower Doubleword - DIP("mfvsrld %d,r%u\n", (UInt)XS, rA_addr); + DIP("mfvsrld %u,r%u\n", (UInt)XS, rA_addr); assign( vS, getVSReg( XS ) ); putIReg( rA_addr, unop(Iop_V128to64, mkexpr( vS) ) ); @@ -20825,7 +20825,7 @@ dis_vx_move ( UInt theInstr ) { IRTemp tmp = newTemp( Ity_I32 ); - DIP("mfvsrdd %d,r%u\n", (UInt)XS, rA_addr); + DIP("mfvsrdd %u,r%u\n", (UInt)XS, rA_addr); assign( tmp, unop( Iop_64to32, getIReg(rA_addr) ) ); assign( vS, binop( Iop_64HLtoV128, @@ -20844,7 +20844,7 @@ dis_vx_move ( UInt theInstr ) IRTemp rA = newTemp( ty ); IRTemp rB = newTemp( ty ); - DIP("mfvsrws %d,r%u\n", (UInt)XS, rA_addr); + DIP("mfvsrws %u,r%u\n", (UInt)XS, rA_addr); if ( rA_addr == 0 ) assign( rA, mkU64 ( 0 ) ); @@ -20912,7 +20912,7 @@ dis_vx_store ( UInt theInstr ) IRTemp word1 = newTemp( Ity_I64 ); IRTemp word2 = newTemp( Ity_I64 ); IRTemp word3 = newTemp( Ity_I64 ); - DIP("stxvx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); + DIP("stxvx %u,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); assign( word0, binop( Iop_Shr64, unop( Iop_V128HIto64, mkexpr( vS ) ), @@ -20991,7 +20991,7 @@ dis_vx_store ( UInt theInstr ) IRTemp store_val = newTemp( Ity_V128 ); IRTemp nb_mask = newTemp( Ity_V128 ); - DIP("stxvl %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); + DIP("stxvl %u,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); assign( nb_field, binop( Iop_Shr64, getIReg(rB_addr), @@ -21139,7 +21139,7 @@ dis_vx_store ( UInt theInstr ) IRTemp nb_field_compare_zero = newTemp( Ity_I64 ); Int i; - DIP("stxvll %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); + DIP("stxvll %u,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); assign( nb_field, binop( Iop_Shr64, getIReg(rB_addr), @@ -21381,7 +21381,7 @@ dis_vx_store ( UInt theInstr ) { IRTemp high64 = newTemp(Ity_F64); IRTemp val32 = newTemp(Ity_I32); - DIP("stxsspx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); + DIP("stxsspx %u,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); assign(high64, unop( Iop_ReinterpI64asF64, unop( Iop_V128HIto64, mkexpr( vS ) ) ) ); assign(val32, unop( Iop_ReinterpF32asI32, @@ -21393,7 +21393,7 @@ dis_vx_store ( UInt theInstr ) case 0x2CC: { IRExpr * high64; - DIP("stxsdx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); + DIP("stxsdx %u,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); high64 = unop( Iop_V128HIto64, mkexpr( vS ) ); store( mkexpr( EA ), high64 ); break; @@ -21404,7 +21404,7 @@ dis_vx_store ( UInt theInstr ) IRExpr *stored_word; IRTemp byte_to_store = newTemp( Ity_I64 ); - DIP("stxsibx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); + DIP("stxsibx %u,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); /* Can't store just a byte, need to fetch the word at EA merge data * and store. @@ -21428,7 +21428,7 @@ dis_vx_store ( UInt theInstr ) IRExpr *stored_word; IRTemp byte_to_store = newTemp( Ity_I64 ); - DIP("stxsihx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); + DIP("stxsihx %u,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); /* Can't store just a halfword, need to fetch the word at EA merge data * and store. @@ -21450,7 +21450,7 @@ dis_vx_store ( UInt theInstr ) case 0x3CC: { IRExpr * high64, *low64; - DIP("stxvd2x %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); + DIP("stxvd2x %u,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); high64 = unop( Iop_V128HIto64, mkexpr( vS ) ); low64 = unop( Iop_V128to64, mkexpr( vS ) ); store( mkexpr( EA ), high64 ); @@ -21465,7 +21465,7 @@ dis_vx_store ( UInt theInstr ) IRTemp hi64 = newTemp( Ity_I64 ); IRTemp lo64 = newTemp( Ity_I64 ); - DIP("stxvw4x %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); + DIP("stxvw4x %u,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); // This instruction supports word-aligned stores, so EA may not be // quad-word aligned. Therefore, do 4 individual word-size stores. @@ -21500,7 +21500,7 @@ dis_vx_store ( UInt theInstr ) IRTemp half_word6 = newTemp( Ity_I64 ); IRTemp half_word7 = newTemp( Ity_I64 ); - DIP("stxvb8x %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); + DIP("stxvb8x %u,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); assign( half_word0, binop( Iop_Shr64, unop( Iop_V128HIto64, mkexpr( vS ) ), @@ -21633,7 +21633,7 @@ dis_vx_store ( UInt theInstr ) IRExpr* irx_addr; IRTemp byte[16]; - DIP("stxvb16x %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); + DIP("stxvb16x %u,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr); for ( i = 0; i < 8; i++ ) { byte[i] = newTemp( Ity_I64 ); @@ -22194,9 +22194,9 @@ dis_vx_scalar_quad_precision ( UInt theInstr ) IRTemp CC = newTemp( Ity_I32 ); if (opc2 == 0x084) { - DIP("xscmpoqp %d,v%d,v%d\n", BF, vA_addr, vB_addr); + DIP("xscmpoqp %u,v%d,v%u\n", BF, vA_addr, vB_addr); } else { - DIP("xscmpuqp %d,v%d,v%d\n", BF, vA_addr, vB_addr); + DIP("xscmpuqp %u,v%d,v%u\n", BF, vA_addr, vB_addr); } assign( vA, getVSReg(vA_addr)); @@ -22295,7 +22295,7 @@ dis_vx_scalar_quad_precision ( UInt theInstr ) IRTemp eq_lt_gt = newTemp( Ity_I32 ); IRTemp CC = newTemp( Ity_I32 ); - DIP("xscmpexpqp %d,v%d,v%d\n", BF, vA_addr, vB_addr); + DIP("xscmpexpqp %u,v%d,v%u\n", BF, vA_addr, vB_addr); assign( vA, getVSReg(vA_addr)); @@ -22372,7 +22372,7 @@ dis_vx_scalar_quad_precision ( UInt theInstr ) IRTemp zero = newTemp( Ity_I64 ); IRTemp dnorm = newTemp( Ity_I64 ); - DIP("xststdcqp %d,v%d,%d\n", BF, vB_addr, DCMX_mask); + DIP("xststdcqp %u,v%d,%u\n", BF, vB_addr, DCMX_mask); assign( zero, unop( Iop_1Uto64, is_Zero( Ity_V128, vB ) ) ); assign( pos, unop( Iop_1Uto64, @@ -22657,11 +22657,11 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 ) IRTemp vB_adj = newTemp( Ity_V128 ); if ( opc2 == 0x68 ) { - DIP("xxperm v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); + DIP("xxperm v%u,v%u,v%u\n", (UInt)XT, (UInt)XA, (UInt)XB); } else { /* Same as xperm just the index is 31 - idx */ - DIP("xxpermr v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB); + DIP("xxpermr v%u,v%u,v%u\n", (UInt)XT, (UInt)XA, (UInt)XB); } assign( vT, getVSReg( XT ) ); diff --git a/coregrind/m_gdbserver/m_gdbserver.c b/coregrind/m_gdbserver/m_gdbserver.c index 9913c88..1f98ac9 100644 --- a/coregrind/m_gdbserver/m_gdbserver.c +++ b/coregrind/m_gdbserver/m_gdbserver.c @@ -1044,7 +1044,7 @@ static Bool catch_this_syscall (Int sysno) void VG_(gdbserver_report_syscall) (Bool before, UWord sysno, ThreadId tid) { - dlog(4, "VG_(gdbserver_report_syscall) before %d sysno %lu tid %d\n", + dlog(4, "VG_(gdbserver_report_syscall) before %d sysno %lu tid %u\n", before, sysno, tid); if (UNLIKELY(catching_syscalls)) { diff --git a/coregrind/m_libcassert.c b/coregrind/m_libcassert.c index 3dba677..353dc6c 100644 --- a/coregrind/m_libcassert.c +++ b/coregrind/m_libcassert.c @@ -309,7 +309,7 @@ static void print_thread_state (Bool stack_usage, VG_SYSNUM_STRING(VG_(is_in_syscall_no)(i))); else syscallno[0] = 0; - VG_(printf)("\n%sThread %d: status = %s%s (lwpid %d)\n", prefix, i, + VG_(printf)("\n%sThread %u: status = %s%s (lwpid %d)\n", prefix, i, VG_(name_of_ThreadStatus)(VG_(threads)[i].status), syscallno, VG_(threads)[i].os_state.lwpid); diff --git a/coregrind/m_signals.c b/coregrind/m_signals.c index e572f17..2357757 100644 --- a/coregrind/m_signals.c +++ b/coregrind/m_signals.c @@ -1731,7 +1731,7 @@ static void default_action(const vki_siginfo_t *info, ThreadId tid) || VG_(clo_xml) ) { if (VG_(clo_xml)) { VG_(printf_xml)("<fatal_signal>\n"); - VG_(printf_xml)(" <tid>%d</tid>\n", tid); + VG_(printf_xml)(" <tid>%u</tid>\n", tid); if (tst->thread_name) { VG_(printf_xml)(" <threadname>%s</threadname>\n", tst->thread_name); diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c index 90d4a85..2f6ca3d 100644 --- a/coregrind/m_syswrap/syswrap-linux.c +++ b/coregrind/m_syswrap/syswrap-linux.c @@ -3673,7 +3673,7 @@ PRE(sys_statx) { FUSE_COMPATIBLE_MAY_BLOCK(); PRINT("sys_statx ( %ld, %#" FMT_REGWORD "x(%s), %ld, %ld, %#" FMT_REGWORD "x )", - ARG1,ARG2,(char*)(Addr)ARG2,ARG3,ARG4,ARG5); + (Word)ARG1,ARG2,(char*)(Addr)ARG2,(Word)ARG3,(Word)ARG4,ARG5); PRE_REG_READ5(long, "statx", int, dirfd, char *, file_name, int, flags, unsigned int, mask, struct statx *, buf); @@ -11669,7 +11669,7 @@ PRE(sys_bpf) UInt res, key_size, value_size; PRINT("sys_bpf ( %ld, %#" FMT_REGWORD "x, %" FMT_REGWORD "u )", - ARG1, ARG2, ARG3); + (Word)ARG1, ARG2, ARG3); PRE_REG_READ3(long, "bpf", int, cmd, union vki_bpf_attr *, attr, unsigned int, size); switch (ARG1) { diff --git a/coregrind/m_xtree.c b/coregrind/m_xtree.c index 7dbba71..3e3a1ed 100644 --- a/coregrind/m_xtree.c +++ b/coregrind/m_xtree.c @@ -417,9 +417,9 @@ static void FP_pos_str(VgFile* fp, const HChar* name, UInt pos, if (!VG_(clo_xtree_compress_strings)) FP("%s=%s\n", name, value); else if (value_new) - FP("%s=(%d) %s\n", name, pos, value); + FP("%s=(%u) %s\n", name, pos, value); else - FP("%s=(%d)\n", name, pos); + FP("%s=(%u)\n", name, pos); } void VG_(XT_callgrind_print) @@ -569,9 +569,9 @@ void VG_(XT_callgrind_print) FP_pos_str(fp, "fn", called_fnname_nr, called_fnname, called_fnname_new); if (ips_idx == 0) - FP("%d %s\n", called_linenum, img); + FP("%u %s\n", called_linenum, img); else - FP("%d\n", called_linenum); //no self cost. + FP("%u\n", called_linenum); //no self cost. prev_linenum = called_linenum; if (ips_idx >= 1) { CALLED_FLF(ips_idx-1); @@ -586,8 +586,8 @@ void VG_(XT_callgrind_print) calls column the nr of stacktrace containing this arc, which is very confusing. So, the less bad is to give a 0 call count. */ - FP("calls=0 %d\n", called_linenum); - FP("%d %s\n", prev_linenum, img); + FP("calls=0 %u\n", called_linenum); + FP("%u %s\n", prev_linenum, img); } } FP("\n"); @@ -761,8 +761,8 @@ static void ms_output_group (VgFile* fp, UInt depth, UInt indent, if (group->ms_ec == NULL) { const HChar* s = ( 1 == group->n_ec? "," : "s, all" ); vg_assert(group->group_ip == 0); - FP("%*sn0: %lu in %d place%s below massif's threshold (%.2f%%)\n", - indent+1, "", group->total, group->n_ec, s, sig_pct_threshold); + FP("%*sn0: %lu in %u place%s below massif's threshold (%.2f%%)\n", + (Int)(indent+1), "", group->total, group->n_ec, s, sig_pct_threshold); return; } @@ -791,8 +791,8 @@ static void ms_output_group (VgFile* fp, UInt depth, UInt indent, const HChar* buf = VG_(describe_IP)(cur_ep, cur_ip, iipc); Bool is_inlined = VG_(next_IIPC)(iipc); - FP("%*s" "n%u: %ld %s\n", - indent + 1, "", + FP("%*s" "n%u: %lu %s\n", + (Int)(indent + 1), "", is_inlined ? 1 : n_groups, // Inlined frames always have one child. group->total, buf); diff --git a/helgrind/libhb_core.c b/helgrind/libhb_core.c index 7169d0c..1105c03 100644 --- a/helgrind/libhb_core.c +++ b/helgrind/libhb_core.c @@ -4624,7 +4624,7 @@ static Bool check_cached_rcec_ok (Thr* thr, Addr previous_frame0) instructions between 'previous_frame0' and current_pc. To investigate the last case, typically, disass the range of instructions where an invalidate cached stack might miss. */ - VG_(printf)("%s diff tid %d frame %d " + VG_(printf)("%s diff tid %u frame %u " "cached_pc %p check_pc %p\n", reason ? reason : "unexpected", thr->hgthread->coretid, @@ -4663,7 +4663,7 @@ static RCEC* get_RCEC ( Thr* thr ) const Addr cur_ip = VG_(get_IP)(thr->hgthread->coretid); if (DEBUG_CACHED_RCEC) - VG_(printf)("get rcec tid %d at IP %p SP %p" + VG_(printf)("get rcec tid %u at IP %p SP %p" " first_sp_delta %ld cached valid %d\n", thr->hgthread->coretid, (void*)cur_ip, |
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From: Nicholas N. <nj...@so...> - 2019-02-01 20:43:05
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=7e5fc882e9fc86c1bfaa65c2842d27c9f10d4114 commit 7e5fc882e9fc86c1bfaa65c2842d27c9f10d4114 Author: Nicholas Nethercote <nne...@mo...> Date: Sat Feb 2 07:41:02 2019 +1100 Remove reference to non-existent *.post.exp files in dhat/tests/. Diff: --- dhat/tests/Makefile.am | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/dhat/tests/Makefile.am b/dhat/tests/Makefile.am index 5f0c43e..2cb842b 100644 --- a/dhat/tests/Makefile.am +++ b/dhat/tests/Makefile.am @@ -4,12 +4,12 @@ include $(top_srcdir)/Makefile.tool-tests.am dist_noinst_SCRIPTS = filter_stderr EXTRA_DIST = \ - acc.post.exp acc.stderr.exp acc.vgtest \ - basic.post.exp basic.stderr.exp basic.vgtest \ - big.post.exp big.stderr.exp big.vgtest \ - empty.post.exp empty.stderr.exp empty.vgtest \ - sig.post.exp sig.stderr.exp sig.vgtest \ - single.post.exp single.stderr.exp single.vgtest + acc.stderr.exp acc.vgtest \ + basic.stderr.exp basic.vgtest \ + big.stderr.exp big.vgtest \ + empty.stderr.exp empty.vgtest \ + sig.stderr.exp sig.vgtest \ + single.stderr.exp single.vgtest check_PROGRAMS = \ acc \ |
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From: Nicholas N. <n.n...@gm...> - 2019-02-01 04:21:06
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I just landed the new DHAT. Thank you to those who gave feedback. Nick On Fri, 11 Jan 2019 at 14:41, Nicholas Nethercote <n.n...@gm...> wrote: > I have updated the patch -- I finally got around to rewriting the > documentation :) > > I think the new DHAT is ready to land. I've been using it in earnest for a > couple of months to optimize the Rust compiler; it works really well. > > Nick > > On Thu, 20 Dec 2018 at 20:19, Nicholas Nethercote <n.n...@gm...> > wrote: > >> Hi, >> >> I have rewritten DHAT. The details, and a patch, are in >> https://bugs.kde.org/show_bug.cgi?id=402369. I'd be interested to hear >> feedback from anyone who wants to try it out. >> >> Nick >> > |
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From: Nicholas N. <nj...@so...> - 2019-02-01 04:09:51
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=f71002f1b58ce61a0e8266777ba628ab6f15c23e commit f71002f1b58ce61a0e8266777ba628ab6f15c23e Author: Nicholas Nethercote <nne...@mo...> Date: Fri Feb 1 15:08:31 2019 +1100 Add missing stuff for a DHAT test. Diff: --- .gitignore | 1 + dhat/tests/Makefile.am | 1 + 2 files changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 1d98500..cec920f 100644 --- a/.gitignore +++ b/.gitignore @@ -272,6 +272,7 @@ /dhat/tests/basic /dhat/tests/big /dhat/tests/empty +/dhat/tests/sig /dhat/tests/single # /docs/ diff --git a/dhat/tests/Makefile.am b/dhat/tests/Makefile.am index d1ad7e7..5f0c43e 100644 --- a/dhat/tests/Makefile.am +++ b/dhat/tests/Makefile.am @@ -8,6 +8,7 @@ EXTRA_DIST = \ basic.post.exp basic.stderr.exp basic.vgtest \ big.post.exp big.stderr.exp big.vgtest \ empty.post.exp empty.stderr.exp empty.vgtest \ + sig.post.exp sig.stderr.exp sig.vgtest \ single.post.exp single.stderr.exp single.vgtest check_PROGRAMS = \ |