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From: Mark W. <ma...@so...> - 2018-09-18 21:04:08
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=6ee4d476c68339c4d9cda19e8d950a1738df5a27 commit 6ee4d476c68339c4d9cda19e8d950a1738df5a27 Author: Mark Wielaard <ma...@kl...> Date: Tue Sep 18 22:55:45 2018 +0200 Run power_ISA2_0[57] tests with -q memcheck/tests/ppc64/power_ISA2_0[57] could spuriously fail when some internal glibc function would allocate and free some memory. To get the expected output run the tests with -q and clear stderr.exp. Diff: --- memcheck/tests/ppc64/power_ISA2_05.stderr.exp | 10 ---------- memcheck/tests/ppc64/power_ISA2_05.vgtest | 2 +- memcheck/tests/ppc64/power_ISA2_07.stderr.exp | 10 ---------- memcheck/tests/ppc64/power_ISA2_07.vgtest | 2 +- 4 files changed, 2 insertions(+), 22 deletions(-) diff --git a/memcheck/tests/ppc64/power_ISA2_05.stderr.exp b/memcheck/tests/ppc64/power_ISA2_05.stderr.exp index c22dd7f..e69de29 100644 --- a/memcheck/tests/ppc64/power_ISA2_05.stderr.exp +++ b/memcheck/tests/ppc64/power_ISA2_05.stderr.exp @@ -1,10 +0,0 @@ - - -HEAP SUMMARY: - in use at exit: 0 bytes in 0 blocks - total heap usage: 0 allocs, 0 frees, 0 bytes allocated - -For a detailed leak analysis, rerun with: --leak-check=full - -For counts of detected and suppressed errors, rerun with: -v -ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) diff --git a/memcheck/tests/ppc64/power_ISA2_05.vgtest b/memcheck/tests/ppc64/power_ISA2_05.vgtest index 0279ccc..64df84a 100644 --- a/memcheck/tests/ppc64/power_ISA2_05.vgtest +++ b/memcheck/tests/ppc64/power_ISA2_05.vgtest @@ -1,3 +1,3 @@ prog: power_ISA2_05 ## depricated option --workaround-gcc296-bugs=yes -vgopts: --ignore-range-below-sp=1024-1 +vgopts: -q --ignore-range-below-sp=1024-1 diff --git a/memcheck/tests/ppc64/power_ISA2_07.stderr.exp b/memcheck/tests/ppc64/power_ISA2_07.stderr.exp index c22dd7f..e69de29 100644 --- a/memcheck/tests/ppc64/power_ISA2_07.stderr.exp +++ b/memcheck/tests/ppc64/power_ISA2_07.stderr.exp @@ -1,10 +0,0 @@ - - -HEAP SUMMARY: - in use at exit: 0 bytes in 0 blocks - total heap usage: 0 allocs, 0 frees, 0 bytes allocated - -For a detailed leak analysis, rerun with: --leak-check=full - -For counts of detected and suppressed errors, rerun with: -v -ERROR SUMMARY: 0 errors from 0 contexts (suppressed: 0 from 0) diff --git a/memcheck/tests/ppc64/power_ISA2_07.vgtest b/memcheck/tests/ppc64/power_ISA2_07.vgtest index fa34a1e..fa6e5e2 100644 --- a/memcheck/tests/ppc64/power_ISA2_07.vgtest +++ b/memcheck/tests/ppc64/power_ISA2_07.vgtest @@ -1,3 +1,3 @@ prereq: ../../../tests/check_ppc64_auxv_cap arch_2_07 prog: power_ISA2_07 -vgopts: +vgopts: -q |
|
From: Mark W. <ma...@so...> - 2018-09-18 19:57:14
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=dee4914e6ff9a76a3442fdcea17ec861f8e165b0 commit dee4914e6ff9a76a3442fdcea17ec861f8e165b0 Author: Mark Wielaard <ma...@kl...> Date: Tue Sep 18 21:55:45 2018 +0200 Hook up linux membarrier syscall for x86-linux Fixes none/tests/linux/membarrier on x86-linux. Diff: --- coregrind/m_syswrap/syswrap-x86-linux.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/coregrind/m_syswrap/syswrap-x86-linux.c b/coregrind/m_syswrap/syswrap-x86-linux.c index ea4f354..f05619e 100644 --- a/coregrind/m_syswrap/syswrap-x86-linux.c +++ b/coregrind/m_syswrap/syswrap-x86-linux.c @@ -1606,6 +1606,8 @@ static SyscallTableEntry syscall_table[] = { LINXY(__NR_recvmsg, sys_recvmsg), // 372 LINX_(__NR_shutdown, sys_shutdown), // 373 + LINX_(__NR_membarrier, sys_membarrier), // 375 + LINXY(__NR_statx, sys_statx), // 383 /* Explicitly not supported on i386 yet. */ |
|
From: Mark W. <ma...@so...> - 2018-09-18 16:23:33
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=fbefb81c3cb85af61252e2f6b54f77c506bfe13a commit fbefb81c3cb85af61252e2f6b54f77c506bfe13a Author: Mark Wielaard <ma...@kl...> Date: Tue Sep 18 18:21:21 2018 +0200 Hook up linux membarrier syscall for ppc64[le] Fixes none/tests/linux/membarrier on ppc64[le] platforms. Diff: --- coregrind/m_syswrap/syswrap-ppc64-linux.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/coregrind/m_syswrap/syswrap-ppc64-linux.c b/coregrind/m_syswrap/syswrap-ppc64-linux.c index 2d699a4..6549dd1 100644 --- a/coregrind/m_syswrap/syswrap-ppc64-linux.c +++ b/coregrind/m_syswrap/syswrap-ppc64-linux.c @@ -939,6 +939,8 @@ static SyscallTableEntry syscall_table[] = { LINXY(__NR_getrandom, sys_getrandom), // 359 LINXY(__NR_memfd_create, sys_memfd_create), // 360 + LINX_(__NR_membarrier, sys_membarrier), // 365 + LINXY(__NR_statx, sys_statx), // 383 }; |
|
From: Carl L. <ce...@us...> - 2018-09-18 14:59:08
|
Julian:
I think the Power stuff is all good to go. I don't have any fixes or
changes that need to go in at this time. The test results look good.
Carl Love
|
|
From: Julian S. <se...@so...> - 2018-09-18 07:58:35
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=66a462415e8721f4a4aaf25c20c46172115bd1a6 commit 66a462415e8721f4a4aaf25c20c46172115bd1a6 Author: Julian Seward <js...@ac...> Date: Tue Sep 18 09:58:11 2018 +0200 Update. Diff: --- NEWS | 3 ++- docs/internals/3_13_BUGSTATUS.txt | 7 ------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/NEWS b/NEWS index 6310b37..f688392 100644 --- a/NEWS +++ b/NEWS @@ -30,7 +30,7 @@ support for X86/macOS 10.13, AMD64/macOS 10.13. * mips: support for MIPS SIMD architecture (MSA) has been added. -* mips: support for MIPS N32 ABI support has been added. +* mips: support for MIPS N32 ABI has been added. * ==================== TOOL CHANGES ==================== @@ -155,6 +155,7 @@ where XXXXXX is the bug number as listed below. 395682 Accept read-only PT_LOAD segments and .rodata by ld -z separate-code == 384727 396475 valgrind OS-X build: config.h not found (out-of-tree macOS builds) +395991 arm-linux: wine's unit tests enter a signal delivery loop [..] 396887 arch_prctl should return EINVAL on unknown option == 397286 crash before launching binary (Unsupported arch_prctl option) == 397393 valgrind: the 'impossible' happened: (Archlinux) diff --git a/docs/internals/3_13_BUGSTATUS.txt b/docs/internals/3_13_BUGSTATUS.txt index ca1543c..8171b23 100644 --- a/docs/internals/3_13_BUGSTATUS.txt +++ b/docs/internals/3_13_BUGSTATUS.txt @@ -197,10 +197,6 @@ Should possibly take 393182 Add support for pthread_setname_np() to set thread name (I thought this already worked) -395991 wine's unit tests enter a signal delivery loop under valgrind on - armv7l when SIGSEGV is used -FIX for 3.14 (arm32 signal-resume stuff) - 396369 WARNING: unhandled amd64-linux syscall: 332 397265 [PATCH] Add (partial) support for userfaultfd syscall and related ioctl @@ -648,9 +644,6 @@ Probably invalid (3.11.0) 396706 VEX issue with AMD64 SHR instruction? Missing spec rule, fix this -397089 [PATCH] Incorrect decoding of three-register vmovss/vmovsd opcode 11h -FIX FOR 3.14 - 398183 Vex errors with _mm256_shuffle_epi8/vpshufb. Generates too much code |
|
From: Julian S. <se...@so...> - 2018-09-18 07:55:31
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=43115c8058052fdb0e1c5dd76ec286519e2bfe78 commit 43115c8058052fdb0e1c5dd76ec286519e2bfe78 Author: Julian Seward <js...@ac...> Date: Tue Sep 18 09:53:38 2018 +0200 Bug 395991 - wine's unit tests enter a signal delivery loop under valgrind on armv7l when SIGSEGV is used. On signal handler return, restore r0 .. r15 inclusive from the sigcontext that we gave to the handler, so that any changes the handler has made to those values will take effect on return. Diff: --- coregrind/m_sigframe/sigframe-arm-linux.c | 111 ++++++++++++++++-------------- 1 file changed, 58 insertions(+), 53 deletions(-) diff --git a/coregrind/m_sigframe/sigframe-arm-linux.c b/coregrind/m_sigframe/sigframe-arm-linux.c index 499023e..6816d78 100644 --- a/coregrind/m_sigframe/sigframe-arm-linux.c +++ b/coregrind/m_sigframe/sigframe-arm-linux.c @@ -54,12 +54,12 @@ /* This uses the hack of dumping the vex guest state along with both shadows in the frame, and restoring it afterwards from there, - rather than pulling it out of the ucontext. That means that signal - handlers which modify the ucontext and then return, expecting their - modifications to take effect, will have those modifications - ignored. This could be fixed properly with an hour or so more - effort. */ - + rather than pulling it out of the ucontext. Then, integer + registers, the SP and the PC are restored from the ucontext. That + means that signal handlers which modify floating point registers or + in general any register state apart from R0 to R15 in the ucontext + and then return, expecting their modifications to take effect, will + have those modifications ignored. */ struct vg_sig_private { UInt magicPI; @@ -95,24 +95,12 @@ static void synth_ucontext( ThreadId tid, const vki_siginfo_t *si, uc->uc_sigmask = *set; uc->uc_stack = tst->altstack; -# define SC2(reg,REG) sc->arm_##reg = tst->arch.vex.guest_##REG - SC2(r0,R0); - SC2(r1,R1); - SC2(r2,R2); - SC2(r3,R3); - SC2(r4,R4); - SC2(r5,R5); - SC2(r6,R6); - SC2(r7,R7); - SC2(r8,R8); - SC2(r9,R9); - SC2(r10,R10); - SC2(fp,R11); - SC2(ip,R12); - SC2(sp,R13); - SC2(lr,R14); - SC2(pc,R15T); -# undef SC2 +# define TO_CTX(reg,REG) sc->arm_##reg = tst->arch.vex.guest_##REG + TO_CTX(r0,R0); TO_CTX(r1,R1); TO_CTX(r2,R2); TO_CTX(r3,R3); + TO_CTX(r4,R4); TO_CTX(r5,R5); TO_CTX(r6,R6); TO_CTX(r7,R7); + TO_CTX(r8,R8); TO_CTX(r9,R9); TO_CTX(r10,R10); TO_CTX(fp,R11); + TO_CTX(ip,R12); TO_CTX(sp,R13); TO_CTX(lr,R14); TO_CTX(pc,R15T); +# undef TO_CTX sc->trap_no = trapno; sc->error_code = err; @@ -170,11 +158,9 @@ void VG_(sigframe_create)( ThreadId tid, const vki_sigset_t *mask, void *restorer ) { -// struct vg_sig_private *priv; Addr sp = sp_top_of_frame; ThreadState *tst; Int sigNo = siginfo->si_signo; -// Addr faultaddr; UInt size; tst = VG_(get_ThreadState)(tid); @@ -200,7 +186,8 @@ void VG_(sigframe_create)( ThreadId tid, VG_(memcpy)(&rsf->info, siginfo, sizeof(vki_siginfo_t)); if(sigNo == VKI_SIGILL && siginfo->si_code > 0) { - rsf->info._sifields._sigfault._addr = (Addr *) (tst)->arch.vex.guest_R12; /* IP */ + rsf->info._sifields._sigfault._addr + = (Addr *) (tst)->arch.vex.guest_R12; /* IP */ } VG_TRACK( post_mem_write, Vg_CoreSignal, tst->tid, /* ^^^^^ */ (Addr)rsf, offsetof(struct rt_sigframe, sig)); @@ -230,6 +217,12 @@ void VG_(sigframe_create)( ThreadId tid, tst->arch.vex.guest_R15T = (Addr) handler; /* R15 == PC */ + /* Regardless of what the state of ITSTATE was, it makes no sense + to enter the handler with the first 1-4 instructions possibly + predicated as "don't execute". So set ITSTATE to [AL,AL,AL,AL] + before entering the handler. */ + tst->arch.vex.guest_ITSTATE = 0; + if (VG_(clo_trace_signals)) VG_(message)(Vg_DebugMsg, "VG_(sigframe_create): continuing in handler with PC=%#lx\n", @@ -251,6 +244,8 @@ void VG_(sigframe_destroy)( ThreadId tid, Bool isRT ) Int sigNo; Bool has_siginfo = isRT; + struct rt_sigframe *rt_frame = NULL; + vg_assert(VG_(is_valid_tid)(tid)); tst = VG_(get_ThreadState)(tid); sp = tst->arch.vex.guest_R13; @@ -261,47 +256,57 @@ void VG_(sigframe_destroy)( ThreadId tid, Bool isRT ) priv = &frame->sig.vp; vg_assert(priv->magicPI == 0x31415927); tst->sig_mask = frame->sig.uc.uc_sigmask; + rt_frame = frame; } else { struct sigframe *frame = (struct sigframe *)sp; frame_size = sizeof(*frame); priv = &frame->vp; vg_assert(priv->magicPI == 0x31415927); tst->sig_mask = frame->uc.uc_sigmask; - /*tst->sig_mask.sig[0] = frame->uc.uc_mcontext.oldmask; - tst->sig_mask.sig[1] = frame->uc.uc_mcontext._unused[3]; - VG_(printf)("Setting signmask to %08x%08x\n",tst->sig_mask[0],tst->sig_mask[1]); -*/ } tst->tmp_sig_mask = tst->sig_mask; sigNo = priv->sigNo_private; -//ZZ //XXX: restore regs -//ZZ # define REST(reg,REG) tst->arch.vex.guest_##REG = mc->arm_##reg; -//ZZ REST(r0,R0); -//ZZ REST(r1,R1); -//ZZ REST(r2,R2); -//ZZ REST(r3,R3); -//ZZ REST(r4,R4); -//ZZ REST(r5,R5); -//ZZ REST(r6,R6); -//ZZ REST(r7,R7); -//ZZ REST(r8,R8); -//ZZ REST(r9,R9); -//ZZ REST(r10,R10); -//ZZ REST(fp,R11); -//ZZ REST(ip,R12); -//ZZ REST(sp,R13); -//ZZ REST(lr,R14); -//ZZ REST(pc,R15T); -//ZZ # undef REST - - /* Uh, the next line makes all the REST() above pointless. */ + /* Restore the entire machine state from our private copy. This + isn't really right, but we'll now move on to pick up at least + some changes that the signal handler may have made to the + sigcontext. */ tst->arch.vex = priv->vex; - tst->arch.vex_shadow1 = priv->vex_shadow1; tst->arch.vex_shadow2 = priv->vex_shadow2; + if (has_siginfo) { + /* Pick up at least some state changes from the ucontext, just + in case the handler changed it. The shadow values will be + wrong, but hey. This restores the integer registers, the + program counter and stack pointer. FP/Vector regs, and any + condition code, FP status/control bits, etc, are not + restored. */ + vg_assert(rt_frame != NULL); + struct vki_sigcontext *sc = &rt_frame->sig.uc.uc_mcontext; + Bool handler_changed_pc = sc->arm_pc != tst->arch.vex.guest_R15T; + +# define FROM_CTX(reg,REG) tst->arch.vex.guest_##REG = sc->arm_##reg; + FROM_CTX(r0,R0); FROM_CTX(r1,R1); FROM_CTX(r2,R2); FROM_CTX(r3,R3); + FROM_CTX(r4,R4); FROM_CTX(r5,R5); FROM_CTX(r6,R6); FROM_CTX(r7,R7); + FROM_CTX(r8,R8); FROM_CTX(r9,R9); FROM_CTX(r10,R10); FROM_CTX(fp,R11); + FROM_CTX(ip,R12); FROM_CTX(sp,R13); FROM_CTX(lr,R14); FROM_CTX(pc,R15T); +# undef FROM_CTX + + /* A nasty ITSTATE hack -- apparently necessary as there doesn't + seem to be anywhere in the mcontext in which the ITSTATE is + stored. If the handler appears to have changed the PC, set + ITSTATE to [AL,AL,AL,AL] on the basis that it would be nuts + to start executing code with an ITSTATE value that pertained + to some other code address. Otherwise ITSTATE is restored + directly from the VEX state that we shoved on the stack when + creating the signal frame. */ + if (handler_changed_pc) { + tst->arch.vex.guest_ITSTATE = 0; + } + } + VG_TRACK( die_mem_stack_signal, sp - VG_STACK_REDZONE_SZB, frame_size + VG_STACK_REDZONE_SZB ); |
|
From: Julian S. <se...@so...> - 2018-09-18 07:25:10
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3c89fada21933d901bd9cf6ce2667183d7cdfc44 commit 3c89fada21933d901bd9cf6ce2667183d7cdfc44 Author: Julian Seward <js...@ac...> Date: Tue Sep 18 09:24:01 2018 +0200 A bit of whitespace and guard changes relating to VGABI_N32. No functional change. n-i-bz. * coregrind/m_redir.c: whitespace changes only * memcheck/mc_main.c: - change 6 guards of the form "defined (VGABI_N32)" to "defined(VGA_mips64) && defined(VGABI_N32)" - Fix up poor indentation Diff: --- coregrind/m_redir.c | 18 +++++-------- memcheck/mc_main.c | 77 +++++++++++++++++++++++++++-------------------------- 2 files changed, 46 insertions(+), 49 deletions(-) diff --git a/coregrind/m_redir.c b/coregrind/m_redir.c index 660e696..6bc01b4 100644 --- a/coregrind/m_redir.c +++ b/coregrind/m_redir.c @@ -1577,7 +1577,6 @@ void VG_(redir_initialise) ( void ) # elif defined(VGP_mips32_linux) if (0==VG_(strcmp)("Memcheck", VG_(details).name)) { - /* this is mandatory - can't sanely continue without it */ add_hardwired_spec( "ld.so.1", "strlen", @@ -1589,19 +1588,17 @@ void VG_(redir_initialise) ( void ) (Addr)&VG_(mips32_linux_REDIR_FOR_index), complain_about_stripped_glibc_ldso ); -# if defined(VGPV_mips32_linux_android) +# if defined(VGPV_mips32_linux_android) add_hardwired_spec( "NONE", "__dl_strlen", (Addr)&VG_(mips32_linux_REDIR_FOR_strlen), NULL ); -# endif - +# endif } # elif defined(VGP_mips64_linux) if (0==VG_(strcmp)("Memcheck", VG_(details).name)) { - /* this is mandatory - can't sanely continue without it */ add_hardwired_spec( "ld.so.1", "strlen", @@ -1613,8 +1610,7 @@ void VG_(redir_initialise) ( void ) (Addr)&VG_(mips64_linux_REDIR_FOR_index), complain_about_stripped_glibc_ldso ); - -#if defined(VGABI_64) +# if defined(VGABI_64) add_hardwired_spec( "ld-linux-mipsn8.so.1", "strlen", (Addr)&VG_(mips64_linux_REDIR_FOR_strlen), @@ -1625,15 +1621,15 @@ void VG_(redir_initialise) ( void ) (Addr)&VG_(mips64_linux_REDIR_FOR_index), complain_about_stripped_glibc_ldso ); -#elif defined(VGABI_N32) +# elif defined(VGABI_N32) add_hardwired_spec( "ld.so.1", "strchr", (Addr)&VG_(mips64_linux_REDIR_FOR_index), complain_about_stripped_glibc_ldso ); -#else -#error unknown mips64 ABI -#endif +# else +# error unknown mips64 ABI +# endif } # elif defined(VGP_x86_solaris) diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c index f1dc900..a1edb9a 100644 --- a/memcheck/mc_main.c +++ b/memcheck/mc_main.c @@ -1393,13 +1393,12 @@ ULong mc_LOADVn_slow ( Addr a, SizeT nBits, Bool bigendian ) from LOADV64 and LOADV32. */ -#if defined (VGABI_N32) - if (LIKELY(sizeof(void*) == 4 - && nBits == 64 && VG_IS_8_ALIGNED(a))) { -#else - if (LIKELY(sizeof(void*) == 8 - && nBits == 64 && VG_IS_8_ALIGNED(a))) { -#endif +# if defined(VGA_mips64) && defined(VGABI_N32) + if (LIKELY(sizeof(void*) == 4 && nBits == 64 && VG_IS_8_ALIGNED(a))) +# else + if (LIKELY(sizeof(void*) == 8 && nBits == 64 && VG_IS_8_ALIGNED(a))) +# endif + { SecMap* sm = get_secmap_for_reading(a); UWord sm_off16 = SM_OFF_16(a); UWord vabits16 = sm->vabits16[sm_off16]; @@ -1409,13 +1408,13 @@ ULong mc_LOADVn_slow ( Addr a, SizeT nBits, Bool bigendian ) return V_BITS64_UNDEFINED; /* else fall into the slow case */ } -#if defined (VGABI_N32) - if (LIKELY(sizeof(void*) == 4 - && nBits == 32 && VG_IS_4_ALIGNED(a))) { -#else - if (LIKELY(sizeof(void*) == 8 - && nBits == 32 && VG_IS_4_ALIGNED(a))) { -#endif + +# if defined(VGA_mips64) && defined(VGABI_N32) + if (LIKELY(sizeof(void*) == 4 && nBits == 32 && VG_IS_4_ALIGNED(a))) +# else + if (LIKELY(sizeof(void*) == 8 && nBits == 32 && VG_IS_4_ALIGNED(a))) +# endif + { SecMap* sm = get_secmap_for_reading(a); UWord sm_off = SM_OFF(a); UWord vabits8 = sm->vabits8[sm_off]; @@ -1425,6 +1424,7 @@ ULong mc_LOADVn_slow ( Addr a, SizeT nBits, Bool bigendian ) return ((UWord)0xFFFFFFFF00000000ULL | (UWord)V_BITS32_UNDEFINED); /* else fall into slow case */ } + /* ------------ END semi-fast cases ------------ */ ULong vbits64 = V_BITS64_UNDEFINED; /* result */ @@ -1496,13 +1496,14 @@ ULong mc_LOADVn_slow ( Addr a, SizeT nBits, Bool bigendian ) /* "at least one of the addresses is invalid" */ tl_assert(pessim64 != V_BITS64_DEFINED); -#if defined (VGABI_N32) +# if defined(VGA_mips64) && defined(VGABI_N32) if (szB == VG_WORDSIZE * 2 && VG_IS_WORD_ALIGNED(a) - && n_addrs_bad < VG_WORDSIZE * 2) { -#else + && n_addrs_bad < VG_WORDSIZE * 2) +# else if (szB == VG_WORDSIZE && VG_IS_WORD_ALIGNED(a) - && n_addrs_bad < VG_WORDSIZE) { -#endif + && n_addrs_bad < VG_WORDSIZE) +# endif + { /* Exemption applies. Use the previously computed pessimising value for vbits64 and return the combined result, but don't flag an addressing error. The pessimising value is Defined @@ -1520,13 +1521,14 @@ ULong mc_LOADVn_slow ( Addr a, SizeT nBits, Bool bigendian ) for this case. Note that the first clause of the conditional (VG_WORDSIZE == 8) is known at compile time, so the whole clause will get folded out in 32 bit builds. */ -#if defined (VGABI_N32) +# if defined(VGA_mips64) && defined(VGABI_N32) if (VG_WORDSIZE == 4 - && VG_IS_4_ALIGNED(a) && nBits == 32 && n_addrs_bad < 4) { -#else + && VG_IS_4_ALIGNED(a) && nBits == 32 && n_addrs_bad < 4) +# else if (VG_WORDSIZE == 8 - && VG_IS_4_ALIGNED(a) && nBits == 32 && n_addrs_bad < 4) { -#endif + && VG_IS_4_ALIGNED(a) && nBits == 32 && n_addrs_bad < 4) +# endif + { tl_assert(V_BIT_UNDEFINED == 1 && V_BIT_DEFINED == 0); /* (really need "UifU" here...) vbits64 UifU= pessim64 (is pessimised by it, iow) */ @@ -1566,13 +1568,12 @@ void mc_STOREVn_slow ( Addr a, SizeT nBits, ULong vbytes, Bool bigendian ) is somewhat similar to some cases extensively commented in MC_(helperc_STOREV8). */ -#if defined (VGABI_N32) - if (LIKELY(sizeof(void*) == 4 - && nBits == 64 && VG_IS_8_ALIGNED(a))) { -#else - if (LIKELY(sizeof(void*) == 8 - && nBits == 64 && VG_IS_8_ALIGNED(a))) { -#endif +# if defined(VGA_mips64) && defined(VGABI_N32) + if (LIKELY(sizeof(void*) == 4 && nBits == 64 && VG_IS_8_ALIGNED(a))) +# else + if (LIKELY(sizeof(void*) == 8 && nBits == 64 && VG_IS_8_ALIGNED(a))) +# endif + { SecMap* sm = get_secmap_for_reading(a); UWord sm_off16 = SM_OFF_16(a); UWord vabits16 = sm->vabits16[sm_off16]; @@ -1593,13 +1594,13 @@ void mc_STOREVn_slow ( Addr a, SizeT nBits, ULong vbytes, Bool bigendian ) } /* else fall into the slow case */ } -#if defined (VGABI_N32) - if (LIKELY(sizeof(void*) == 4 - && nBits == 32 && VG_IS_4_ALIGNED(a))) { -#else - if (LIKELY(sizeof(void*) == 8 - && nBits == 32 && VG_IS_4_ALIGNED(a))) { -#endif + +# if defined(VGA_mips64) && defined(VGABI_N32) + if (LIKELY(sizeof(void*) == 4 && nBits == 32 && VG_IS_4_ALIGNED(a))) +# else + if (LIKELY(sizeof(void*) == 8 && nBits == 32 && VG_IS_4_ALIGNED(a))) +# endif + { SecMap* sm = get_secmap_for_reading(a); UWord sm_off = SM_OFF(a); UWord vabits8 = sm->vabits8[sm_off]; |
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From: Rhys K. <rhy...@gm...> - 2018-09-18 04:06:01
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On Mon, 17 Sep 2018 at 17:51, Philippe Waroquiers < phi...@sk...> wrote: > On Mon, 2018-09-17 at 23:31 +0200, Mark Wielaard wrote: > > Hi, > > > > On Sun, Sep 02, 2018 at 03:55:00PM +0200, Philippe Waroquiers wrote: > > > Recently, I have done another change for > > > 393146 - failing assert "is_DebugInfo_active(di)" > > > (at least, this solves the case reproduced on gnu/linux with qt5). > > > I also updated gdbserver tests for glibc 2.27. > > > > > > I do not think I have anything more burning waiting for a fix in > > > the 3.14 release. > > > > I also don't have anything urgent. > Nothing new for me, and I used a recent 3.14-GIT at work > without any problems. > So, ok to release from my selfish point of view :). > I'm okay for a release 3.14 from the perspective of macOS. We've got some important bug fixes for this platform in git, which it would be great to have a packaged release out there which includes them. > > The bug : > Bug 398028 - Assertion `csfi_fits` failing in simple C program with > embedded Julia code. > has however been reported also by another user on valgrind-users. > So, there is a problem in this area (maybe triggered by a newer gcc or > glibc or ...). > > Philippe > > > > _______________________________________________ > Valgrind-developers mailing list > Val...@li... > https://lists.sourceforge.net/lists/listinfo/valgrind-developers > |