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From: Petar J. <pe...@so...> - 2018-01-31 16:43:25
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=817011f8f77f0567a1d4fde123dc8c9022ab46a1 commit 817011f8f77f0567a1d4fde123dc8c9022ab46a1 Author: Petar Jovanovic <mip...@gm...> Date: Wed Jan 31 17:27:13 2018 +0100 mips: add support for Iop_Shr16 and Iop_Sar16 This should fix memcheck/tests/vbit-test/vbit-test on mips32/64 platforms. Diff: --- VEX/priv/host_mips_isel.c | 21 +++++++++++++++++++++ memcheck/tests/vbit-test/irops.c | 4 ++-- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/VEX/priv/host_mips_isel.c b/VEX/priv/host_mips_isel.c index 9e9bcb59..ebc25a4 100644 --- a/VEX/priv/host_mips_isel.c +++ b/VEX/priv/host_mips_isel.c @@ -991,10 +991,12 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e) case Iop_Shl64: shftOp = Mshft_SLL; break; + case Iop_Shr16: case Iop_Shr32: case Iop_Shr64: shftOp = Mshft_SRL; break; + case Iop_Sar16: case Iop_Sar32: case Iop_Sar64: shftOp = Mshft_SRA; @@ -1016,6 +1018,25 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e) if (ty == Ity_I8) { vassert(0); + } else if (ty == Ity_I16) { + if (shftOp == Mshft_SRA) { + HReg tmp = newVRegI(env); + HReg r_srcL_se = newVRegI(env); + addInstr(env, MIPSInstr_Shft(Mshft_SLL, True, tmp, + r_srcL, MIPSRH_Imm(False, 16))); + addInstr(env, MIPSInstr_Shft(Mshft_SRA, True, r_srcL_se, + tmp, MIPSRH_Imm(False, 16))); + addInstr(env, MIPSInstr_Shft(shftOp, True, + r_dst, r_srcL_se, ri_srcR)); + } else if (shftOp == Mshft_SRL) { + HReg r_srcL_se = newVRegI(env); + addInstr(env, MIPSInstr_Alu(Malu_AND, r_srcL_se, r_srcL, + MIPSRH_Imm(False, 0xFFFF))); + addInstr(env, MIPSInstr_Shft(shftOp, True, + r_dst, r_srcL_se, ri_srcR)); + } else { + vassert(0); + } } else if (ty == Ity_I32) { if (mode64 && (shftOp == Mshft_SRA || shftOp == Mshft_SRL)) { HReg tmp = newVRegI(env); diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c index 5eea89b..a969a14 100644 --- a/memcheck/tests/vbit-test/irops.c +++ b/memcheck/tests/vbit-test/irops.c @@ -65,11 +65,11 @@ static irop_t irops[] = { { DEFOP(Iop_Shl32, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, { DEFOP(Iop_Shl64, UNDEF_SHL), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts { DEFOP(Iop_Shr8, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32/64 assert - { DEFOP(Iop_Shr16, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32/64 assert + { DEFOP(Iop_Shr16, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, // ppc32/64 assert { DEFOP(Iop_Shr32, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, { DEFOP(Iop_Shr64, UNDEF_SHR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts { DEFOP(Iop_Sar8, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32/64 assert - { DEFOP(Iop_Sar16, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, // ppc32/64 assert + { DEFOP(Iop_Sar16, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1, .mips64 = 1 }, // ppc32/64 assert { DEFOP(Iop_Sar32, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 1, .mips64 = 1 }, { DEFOP(Iop_Sar64, UNDEF_SAR), .s390x = 1, .amd64 = 1, .x86 = 0, .arm = 1, .ppc64 = 1, .ppc32 = 0, .mips32 = 0, .mips64 = 1 }, // ppc32 asserts { DEFOP(Iop_CmpEQ8, UNDEF_CMP_EQ_NE), .s390x = 1, .amd64 = 1, .x86 = 1, .arm = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0, .mips64 = 0 }, |