You can subscribe to this list here.
| 2002 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
(1) |
Oct
(122) |
Nov
(152) |
Dec
(69) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2003 |
Jan
(6) |
Feb
(25) |
Mar
(73) |
Apr
(82) |
May
(24) |
Jun
(25) |
Jul
(10) |
Aug
(11) |
Sep
(10) |
Oct
(54) |
Nov
(203) |
Dec
(182) |
| 2004 |
Jan
(307) |
Feb
(305) |
Mar
(430) |
Apr
(312) |
May
(187) |
Jun
(342) |
Jul
(487) |
Aug
(637) |
Sep
(336) |
Oct
(373) |
Nov
(441) |
Dec
(210) |
| 2005 |
Jan
(385) |
Feb
(480) |
Mar
(636) |
Apr
(544) |
May
(679) |
Jun
(625) |
Jul
(810) |
Aug
(838) |
Sep
(634) |
Oct
(521) |
Nov
(965) |
Dec
(543) |
| 2006 |
Jan
(494) |
Feb
(431) |
Mar
(546) |
Apr
(411) |
May
(406) |
Jun
(322) |
Jul
(256) |
Aug
(401) |
Sep
(345) |
Oct
(542) |
Nov
(308) |
Dec
(481) |
| 2007 |
Jan
(427) |
Feb
(326) |
Mar
(367) |
Apr
(255) |
May
(244) |
Jun
(204) |
Jul
(223) |
Aug
(231) |
Sep
(354) |
Oct
(374) |
Nov
(497) |
Dec
(362) |
| 2008 |
Jan
(322) |
Feb
(482) |
Mar
(658) |
Apr
(422) |
May
(476) |
Jun
(396) |
Jul
(455) |
Aug
(267) |
Sep
(280) |
Oct
(253) |
Nov
(232) |
Dec
(304) |
| 2009 |
Jan
(486) |
Feb
(470) |
Mar
(458) |
Apr
(423) |
May
(696) |
Jun
(461) |
Jul
(551) |
Aug
(575) |
Sep
(134) |
Oct
(110) |
Nov
(157) |
Dec
(102) |
| 2010 |
Jan
(226) |
Feb
(86) |
Mar
(147) |
Apr
(117) |
May
(107) |
Jun
(203) |
Jul
(193) |
Aug
(238) |
Sep
(300) |
Oct
(246) |
Nov
(23) |
Dec
(75) |
| 2011 |
Jan
(133) |
Feb
(195) |
Mar
(315) |
Apr
(200) |
May
(267) |
Jun
(293) |
Jul
(353) |
Aug
(237) |
Sep
(278) |
Oct
(611) |
Nov
(274) |
Dec
(260) |
| 2012 |
Jan
(303) |
Feb
(391) |
Mar
(417) |
Apr
(441) |
May
(488) |
Jun
(655) |
Jul
(590) |
Aug
(610) |
Sep
(526) |
Oct
(478) |
Nov
(359) |
Dec
(372) |
| 2013 |
Jan
(467) |
Feb
(226) |
Mar
(391) |
Apr
(281) |
May
(299) |
Jun
(252) |
Jul
(311) |
Aug
(352) |
Sep
(481) |
Oct
(571) |
Nov
(222) |
Dec
(231) |
| 2014 |
Jan
(185) |
Feb
(329) |
Mar
(245) |
Apr
(238) |
May
(281) |
Jun
(399) |
Jul
(382) |
Aug
(500) |
Sep
(579) |
Oct
(435) |
Nov
(487) |
Dec
(256) |
| 2015 |
Jan
(338) |
Feb
(357) |
Mar
(330) |
Apr
(294) |
May
(191) |
Jun
(108) |
Jul
(142) |
Aug
(261) |
Sep
(190) |
Oct
(54) |
Nov
(83) |
Dec
(22) |
| 2016 |
Jan
(49) |
Feb
(89) |
Mar
(33) |
Apr
(50) |
May
(27) |
Jun
(34) |
Jul
(53) |
Aug
(53) |
Sep
(98) |
Oct
(206) |
Nov
(93) |
Dec
(53) |
| 2017 |
Jan
(65) |
Feb
(82) |
Mar
(102) |
Apr
(86) |
May
(187) |
Jun
(67) |
Jul
(23) |
Aug
(93) |
Sep
(65) |
Oct
(45) |
Nov
(35) |
Dec
(17) |
| 2018 |
Jan
(26) |
Feb
(35) |
Mar
(38) |
Apr
(32) |
May
(8) |
Jun
(43) |
Jul
(27) |
Aug
(30) |
Sep
(43) |
Oct
(42) |
Nov
(38) |
Dec
(67) |
| 2019 |
Jan
(32) |
Feb
(37) |
Mar
(53) |
Apr
(64) |
May
(49) |
Jun
(18) |
Jul
(14) |
Aug
(53) |
Sep
(25) |
Oct
(30) |
Nov
(49) |
Dec
(31) |
| 2020 |
Jan
(87) |
Feb
(45) |
Mar
(37) |
Apr
(51) |
May
(99) |
Jun
(36) |
Jul
(11) |
Aug
(14) |
Sep
(20) |
Oct
(24) |
Nov
(40) |
Dec
(23) |
| 2021 |
Jan
(14) |
Feb
(53) |
Mar
(85) |
Apr
(15) |
May
(19) |
Jun
(3) |
Jul
(14) |
Aug
(1) |
Sep
(57) |
Oct
(73) |
Nov
(56) |
Dec
(22) |
| 2022 |
Jan
(3) |
Feb
(22) |
Mar
(6) |
Apr
(55) |
May
(46) |
Jun
(39) |
Jul
(15) |
Aug
(9) |
Sep
(11) |
Oct
(34) |
Nov
(20) |
Dec
(36) |
| 2023 |
Jan
(79) |
Feb
(41) |
Mar
(99) |
Apr
(169) |
May
(48) |
Jun
(16) |
Jul
(16) |
Aug
(57) |
Sep
(19) |
Oct
|
Nov
|
Dec
|
| S | M | T | W | T | F | S |
|---|---|---|---|---|---|---|
|
1
(2) |
2
(8) |
3
(3) |
4
|
5
(1) |
6
|
7
|
|
8
|
9
|
10
(1) |
11
(4) |
12
(5) |
13
(1) |
14
(2) |
|
15
(1) |
16
|
17
(2) |
18
|
19
(1) |
20
(2) |
21
|
|
22
|
23
|
24
(1) |
25
(1) |
26
(1) |
27
(6) |
28
(1) |
|
29
|
30
|
31
(2) |
|
|
|
|
|
From: Julian S. <se...@so...> - 2017-10-02 16:48:53
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=08b043f53a9e3f37b10b5af6abc2e218678b9e2f commit 08b043f53a9e3f37b10b5af6abc2e218678b9e2f Author: Julian Seward <js...@ac...> Date: Mon Oct 2 18:43:22 2017 +0200 libvex_BackEnd: lift the assembler out into its own function, for tidyness. No functional change. Diff: --- VEX/priv/main_main.c | 1342 +++++++++++++++++++++++++------------------------- 1 file changed, 681 insertions(+), 661 deletions(-) diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c index 8caaca2..0629c15 100644 --- a/VEX/priv/main_main.c +++ b/VEX/priv/main_main.c @@ -891,760 +891,779 @@ AssemblyBufferOffset emitSimpleInsn ( /*MB_MOD*/Int* offs_profInc, } -/* ---- The back end proper ---- */ +/* ---- The assembler ---- */ -/* Back end of the compilation pipeline. Is not exported. */ +/* Assemble RCODE, writing the resulting machine code into the buffer + specified by VTA->host_bytes of size VTA->host_bytes_size. When done, + store the number of bytes written at the location specified by + VTA->host_bytes_used. RES->offs_profInc may be modified as a result. No + other fields of RES are changed. -static void libvex_BackEnd ( const VexTranslateArgs *vta, - /*MOD*/ VexTranslateResult* res, - /*MOD*/ IRSB* irsb, - VexRegisterUpdates pxControl ) + Returns True for OK, False for 'ran out of buffer space'. +*/ +static +Bool theAssembler ( /*MOD*/VexTranslateResult* res, + const VexTranslateArgs* vta, + HInstrIfThenElse* (*isIfThenElse)( const HInstr* ), + const Bool mode64, + const HInstrSB* rcode ) { - /* This the bundle of functions we need to do the back-end stuff - (insn selection, reg-alloc, assembly) whilst being insulated - from the target instruction set. */ - Bool (*isMove) ( const HInstr*, HReg*, HReg* ); - void (*getRegUsage) ( HRegUsage*, const HInstr*, Bool ); - void (*mapRegs) ( HRegRemap*, HInstr*, Bool ); - HInstrIfThenElse* (*isIfThenElse)( const HInstr* ); - void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool ); - void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool ); - HInstr* (*genMove) ( HReg, HReg, Bool ); - HInstr* (*genHInstrITE) ( HInstrIfThenElse* ); - HInstr* (*directReload) ( HInstr*, HReg, Short ); - void (*ppInstr) ( const HInstr*, Bool ); - void (*ppCondCode) ( HCondCode ); - UInt (*ppReg) ( HReg ); - HInstrSB* (*iselSB) ( const IRSB*, VexArch, const VexArchInfo*, - const VexAbiInfo*, Int, Int, Bool, Bool, - Addr ); - Int (*emit) ( /*MB_MOD*/Bool*, - UChar*, Int, const HInstr*, Bool, VexEndness, - const void*, const void*, const void*, - const void* ); - Bool (*preciseMemExnsFn) ( Int, Int, VexRegisterUpdates ); - - const RRegUniverse* rRegUniv = NULL; + // QElem are work Queue elements. The work Queue is the top level data + // structure for the emitter. It is initialised with the HInstrVec* of + // the overall HInstrSB. Every OOL HInstrVec* in the tree will at some + // point be present in the Queue. IL HInstrVec*s are never present in + // the Queue because the inner emitter loop processes them in-line, using + // a Stack (see below) to keep track of its nesting level. + // + // The Stack (see below) is empty before and after every Queue element is + // processed. In other words, the Stack only holds state needed during + // the processing of a single Queue element. + // + // The ordering of elements in the Queue is irrelevant -- correct code + // will be emitted even with set semantics (arbitrary order). However, + // the FIFOness of the queue is believed to generate code in which + // colder and colder code (more deeply nested OOLs) is placed further + // and further from the start of the emitted machine code, which sounds + // like a layout which should minimise icache misses. + // + // QElems also contain two pieces of jump-fixup information. When we + // finally come to process a QElem, we need to know: + // + // * |jumpToOOLpoint|: the place which wants to jump to the start of the + // emitted insns for this QElem. We must have already emitted that, + // since it will be the conditional jump that leads to this QElem (OOL + // block). + // + // * |resumePoint|: the place we should jump back to after the QElem is + // finished (the "resume point"), which is the emitted code of the + // HInstr immediately following the HInstrIfThenElse that has this + // QElem as its OOL block. + // + // When the QElem is processed, we know both the |jumpToOOLpoint| and + // the |resumePoint|, and so the first can be patched, and the second + // we generate an instruction to jump to. + // + // There are three complications with patching: + // + // (1) per comments on Stack elems, we do not know the |resumePoint| when + // creating a QElem. That will only be known when processing of the + // corresponding IL block is completed. + // + // (2) The top level HInstrVec* has neither a |jumpToOOLpoint| nor a + // |resumePoint|. + // + // (3) Non-top-level OOLs may not have a valid |resumePoint| if they do + // an unconditional IR-level Exit. We can generate the resume point + // branch, but it will be never be used. + typedef + struct { + // The HInstrs for this OOL. + HInstrVec* oolVec; + // Where we should patch to jump to the OOL ("how do we get here?") + Bool jumpToOOLpoint_valid; + Relocation jumpToOOLpoint; + // Resume point offset, in bytes from start of output buffer + // ("where do we go after this block is completed?") + Bool resumePoint_valid; + AssemblyBufferOffset resumePoint; + } + QElem; - Bool mode64, chainingAllowed; - Int out_used; - Int guest_sizeB; - Int offB_HOST_EvC_COUNTER; - Int offB_HOST_EvC_FAILADDR; - Addr max_ga; - HInstrSB* vcode; - HInstrSB* rcode; - isMove = NULL; - getRegUsage = NULL; - mapRegs = NULL; - isIfThenElse = NULL; - genSpill = NULL; - genReload = NULL; - genMove = NULL; - genHInstrITE = NULL; - directReload = NULL; - ppInstr = NULL; - ppCondCode = NULL; - ppReg = NULL; - iselSB = NULL; - emit = NULL; + // SElem are stack elements. When we suspend processing a HInstrVec* in + // order to process an IL path in an IfThenElse, we push the HInstrVec* + // and the next index to process on the stack, so that we know where to + // resume when the nested IL sequence is completed. |vec| and |vec_next| + // record the resume HInstr. + // + // A second effect of processing a nested IL sequence is that we will + // have to (later) process the corresponding OOL sequence. And that OOL + // sequence will have to finish with a jump back to the "resume point" + // (the emitted instruction immediately following the IfThenElse). We + // only know the offset of the resume point instruction in the output + // buffer when we actually resume emitted from there -- that is, when the + // entry we pushed, is popped. So, when we pop, we must mark the + // corresponding OOL entry in the Queue to record there the resume point + // offset. For this reason we also carry |ool_qindex|, which is the + // index of the corresponding OOL entry in the Queue. + typedef + struct { + HInstrVec* vec; // resume point HInstr vector + UInt vec_next; // resume point HInstr vector index + Int ool_qindex; // index in Queue of OOL to mark when we resume + } + SElem; - mode64 = False; - chainingAllowed = False; - guest_sizeB = 0; - offB_HOST_EvC_COUNTER = 0; - offB_HOST_EvC_FAILADDR = 0; - preciseMemExnsFn = NULL; + // The Stack. The stack depth is bounded by maximum number of nested + // hot (IL) sections, so in practice it is going to be very small. + const Int nSTACK = 4; - vassert(vex_initdone); - vassert(vta->disp_cp_xassisted != NULL); + SElem stack[nSTACK]; + Int stackPtr; // points to most recently pushed entry <=> "-1 means empty" - vex_traceflags = vta->traceflags; + // The Queue. The queue size is bounded by the number of cold (OOL) + // sections in the entire HInstrSB, so it's also going to be pretty + // small. + const Int nQUEUE = 8; - /* Both the chainers and the indir are either NULL or non-NULL. */ - if (vta->disp_cp_chain_me_to_slowEP != NULL) { - vassert(vta->disp_cp_chain_me_to_fastEP != NULL); - vassert(vta->disp_cp_xindir != NULL); - chainingAllowed = True; - } else { - vassert(vta->disp_cp_chain_me_to_fastEP == NULL); - vassert(vta->disp_cp_xindir == NULL); - } + QElem queue[nQUEUE]; + Int queueOldest; // index of oldest entry, initially 0 + Int queueNewest; // index of newest entry, + // initially -1, otherwise must be >= queueOldest - switch (vta->arch_guest) { + /////////////////////////////////////////////////////// - case VexArchX86: - preciseMemExnsFn - = X86FN(guest_x86_state_requires_precise_mem_exns); - guest_sizeB = sizeof(VexGuestX86State); - offB_HOST_EvC_COUNTER = offsetof(VexGuestX86State,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestX86State,host_EvC_FAILADDR); - break; + const Bool verbose_asm = (vex_traceflags & VEX_TRACE_ASM) != 0; - case VexArchAMD64: - preciseMemExnsFn - = AMD64FN(guest_amd64_state_requires_precise_mem_exns); - guest_sizeB = sizeof(VexGuestAMD64State); - offB_HOST_EvC_COUNTER = offsetof(VexGuestAMD64State,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestAMD64State,host_EvC_FAILADDR); - break; + const EmitConstants emitConsts + = { .mode64 = mode64, + .endness_host = vta->archinfo_host.endness, + .disp_cp_chain_me_to_slowEP = vta->disp_cp_chain_me_to_slowEP, + .disp_cp_chain_me_to_fastEP = vta->disp_cp_chain_me_to_fastEP, + .disp_cp_xindir = vta->disp_cp_xindir, + .disp_cp_xassisted = vta->disp_cp_xassisted }; - case VexArchPPC32: - preciseMemExnsFn - = PPC32FN(guest_ppc32_state_requires_precise_mem_exns); - guest_sizeB = sizeof(VexGuestPPC32State); - offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC32State,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC32State,host_EvC_FAILADDR); - break; + AssemblyBufferOffset cursor = 0; + AssemblyBufferOffset cursor_limit = vta->host_bytes_size; - case VexArchPPC64: - preciseMemExnsFn - = PPC64FN(guest_ppc64_state_requires_precise_mem_exns); - guest_sizeB = sizeof(VexGuestPPC64State); - offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC64State,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC64State,host_EvC_FAILADDR); - break; + *(vta->host_bytes_used) = 0; - case VexArchS390X: - preciseMemExnsFn - = S390FN(guest_s390x_state_requires_precise_mem_exns); - guest_sizeB = sizeof(VexGuestS390XState); - offB_HOST_EvC_COUNTER = offsetof(VexGuestS390XState,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestS390XState,host_EvC_FAILADDR); - break; + queueOldest = 0; + queueNewest = -1; - case VexArchARM: - preciseMemExnsFn - = ARMFN(guest_arm_state_requires_precise_mem_exns); - guest_sizeB = sizeof(VexGuestARMState); - offB_HOST_EvC_COUNTER = offsetof(VexGuestARMState,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestARMState,host_EvC_FAILADDR); - break; + vassert(queueNewest < nQUEUE); + queueNewest++; + { + QElem* qe = &queue[queueNewest]; + vex_bzero(qe, sizeof(*qe)); + qe->oolVec = rcode->insns; + qe->jumpToOOLpoint_valid = False; + qe->resumePoint_valid = False; + } + vassert(queueNewest == 0); - case VexArchARM64: - preciseMemExnsFn - = ARM64FN(guest_arm64_state_requires_precise_mem_exns); - guest_sizeB = sizeof(VexGuestARM64State); - offB_HOST_EvC_COUNTER = offsetof(VexGuestARM64State,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestARM64State,host_EvC_FAILADDR); - break; + /* Main loop, processing Queue entries, until there are no more. */ + while (queueOldest <= queueNewest) { - case VexArchMIPS32: - preciseMemExnsFn - = MIPS32FN(guest_mips32_state_requires_precise_mem_exns); - guest_sizeB = sizeof(VexGuestMIPS32State); - offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS32State,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR); - break; + Int qCur = queueOldest; + if (UNLIKELY(verbose_asm)) + vex_printf("BEGIN queue[%d]\n", qCur); - case VexArchMIPS64: - preciseMemExnsFn - = MIPS64FN(guest_mips64_state_requires_precise_mem_exns); - guest_sizeB = sizeof(VexGuestMIPS64State); - offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS64State,host_EvC_COUNTER); - offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS64State,host_EvC_FAILADDR); - break; + // Take the oldest entry in the queue + QElem* qe = &queue[queueOldest]; + queueOldest++; - default: - vpanic("LibVEX_Codegen: unsupported guest insn set"); - } + // Stay sane. Only the top level block has no branch to it and no + // resume point. + if (qe->oolVec == rcode->insns) { + // This is the top level block + vassert(!qe->jumpToOOLpoint_valid); + vassert(!qe->resumePoint_valid); + } else { + vassert(qe->jumpToOOLpoint_valid); + vassert(qe->resumePoint_valid); + // In the future, we might be able to allow the resume point to be + // invalid for non-top-level blocks, if the block contains an + // unconditional exit. Currently the IR can't represent that, so + // the assertion is valid. + } + // Processing |qe| + if (qe->jumpToOOLpoint_valid) { + // patch qe->jmpToOOLpoint to jump to |here| + if (UNLIKELY(verbose_asm)) { + vex_printf(" -- APPLY "); + ppRelocation(qe->jumpToOOLpoint); + vex_printf("\n"); + } + applyRelocation(qe->jumpToOOLpoint, &vta->host_bytes[0], + cursor, cursor, vta->archinfo_host.endness, + verbose_asm); + } - switch (vta->arch_host) { + // Initialise the stack, for processing of |qe|. + stackPtr = 0; // "contains one element" - case VexArchX86: - mode64 = False; - rRegUniv = X86FN(getRRegUniverse_X86()); - isMove = CAST_TO_TYPEOF(isMove) X86FN(isMove_X86Instr); - getRegUsage - = CAST_TO_TYPEOF(getRegUsage) X86FN(getRegUsage_X86Instr); - mapRegs = CAST_TO_TYPEOF(mapRegs) X86FN(mapRegs_X86Instr); - isIfThenElse = CAST_TO_TYPEOF(isIfThenElse) X86FN(isIfThenElse_X86Instr); - genSpill = CAST_TO_TYPEOF(genSpill) X86FN(genSpill_X86); - genReload = CAST_TO_TYPEOF(genReload) X86FN(genReload_X86); - genMove = CAST_TO_TYPEOF(genMove) X86FN(genMove_X86); - genHInstrITE = CAST_TO_TYPEOF(genHInstrITE) X86FN(X86Instr_IfThenElse); - directReload = CAST_TO_TYPEOF(directReload) X86FN(directReload_X86); - ppInstr = CAST_TO_TYPEOF(ppInstr) X86FN(ppX86Instr); - ppCondCode = CAST_TO_TYPEOF(ppCondCode) X86FN(ppX86CondCode); - ppReg = CAST_TO_TYPEOF(ppReg) X86FN(ppHRegX86); - iselSB = X86FN(iselSB_X86); - emit = CAST_TO_TYPEOF(emit) X86FN(emit_X86Instr); - vassert(vta->archinfo_host.endness == VexEndnessLE); - break; + stack[stackPtr].vec = qe->oolVec; + stack[stackPtr].vec_next = 0; + stack[stackPtr].ool_qindex = -1; // INVALID - case VexArchAMD64: - mode64 = True; - rRegUniv = AMD64FN(getRRegUniverse_AMD64()); - isMove = CAST_TO_TYPEOF(isMove) AMD64FN(isMove_AMD64Instr); - getRegUsage - = CAST_TO_TYPEOF(getRegUsage) AMD64FN(getRegUsage_AMD64Instr); - mapRegs = CAST_TO_TYPEOF(mapRegs) AMD64FN(mapRegs_AMD64Instr); - genSpill = CAST_TO_TYPEOF(genSpill) AMD64FN(genSpill_AMD64); - genReload = CAST_TO_TYPEOF(genReload) AMD64FN(genReload_AMD64); - genMove = CAST_TO_TYPEOF(genMove) AMD64FN(genMove_AMD64); - directReload = CAST_TO_TYPEOF(directReload) AMD64FN(directReload_AMD64); - ppInstr = CAST_TO_TYPEOF(ppInstr) AMD64FN(ppAMD64Instr); - ppReg = CAST_TO_TYPEOF(ppReg) AMD64FN(ppHRegAMD64); - iselSB = AMD64FN(iselSB_AMD64); - emit = CAST_TO_TYPEOF(emit) AMD64FN(emit_AMD64Instr); - vassert(vta->archinfo_host.endness == VexEndnessLE); - break; + // Iterate till the stack is empty. This effectively does a + // depth-first traversal of the hot-path (IL) tree reachable from + // here, and at the same time adds any encountered cold-path (OOL) + // blocks to the Queue for later processing. This is the heart of the + // flattening algorithm. + while (stackPtr >= 0) { - case VexArchPPC32: - mode64 = False; - rRegUniv = PPC32FN(getRRegUniverse_PPC(mode64)); - isMove = CAST_TO_TYPEOF(isMove) PPC32FN(isMove_PPCInstr); - getRegUsage - = CAST_TO_TYPEOF(getRegUsage) PPC32FN(getRegUsage_PPCInstr); - mapRegs = CAST_TO_TYPEOF(mapRegs) PPC32FN(mapRegs_PPCInstr); - genSpill = CAST_TO_TYPEOF(genSpill) PPC32FN(genSpill_PPC); - genReload = CAST_TO_TYPEOF(genReload) PPC32FN(genReload_PPC); - genMove = CAST_TO_TYPEOF(genMove) PPC32FN(genMove_PPC); - ppInstr = CAST_TO_TYPEOF(ppInstr) PPC32FN(ppPPCInstr); - ppReg = CAST_TO_TYPEOF(ppReg) PPC32FN(ppHRegPPC); - iselSB = PPC32FN(iselSB_PPC); - emit = CAST_TO_TYPEOF(emit) PPC32FN(emit_PPCInstr); - vassert(vta->archinfo_host.endness == VexEndnessBE); - break; + if (UNLIKELY(verbose_asm)) + vex_printf(" -- CONSIDER stack[%d]\n", stackPtr); - case VexArchPPC64: - mode64 = True; - rRegUniv = PPC64FN(getRRegUniverse_PPC(mode64)); - isMove = CAST_TO_TYPEOF(isMove) PPC64FN(isMove_PPCInstr); - getRegUsage - = CAST_TO_TYPEOF(getRegUsage) PPC64FN(getRegUsage_PPCInstr); - mapRegs = CAST_TO_TYPEOF(mapRegs) PPC64FN(mapRegs_PPCInstr); - genSpill = CAST_TO_TYPEOF(genSpill) PPC64FN(genSpill_PPC); - genReload = CAST_TO_TYPEOF(genReload) PPC64FN(genReload_PPC); - genMove = CAST_TO_TYPEOF(genMove) PPC64FN(genMove_PPC); - ppInstr = CAST_TO_TYPEOF(ppInstr) PPC64FN(ppPPCInstr); - ppReg = CAST_TO_TYPEOF(ppReg) PPC64FN(ppHRegPPC); - iselSB = PPC64FN(iselSB_PPC); - emit = CAST_TO_TYPEOF(emit) PPC64FN(emit_PPCInstr); - vassert(vta->archinfo_host.endness == VexEndnessBE || - vta->archinfo_host.endness == VexEndnessLE ); - break; + HInstrVec* vec = stack[stackPtr].vec; + UInt vec_next = stack[stackPtr].vec_next; + Int ool_qindex = stack[stackPtr].ool_qindex; + stackPtr--; - case VexArchS390X: - mode64 = True; - rRegUniv = S390FN(getRRegUniverse_S390()); - isMove = CAST_TO_TYPEOF(isMove) S390FN(isMove_S390Instr); - getRegUsage - = CAST_TO_TYPEOF(getRegUsage) S390FN(getRegUsage_S390Instr); - mapRegs = CAST_TO_TYPEOF(mapRegs) S390FN(mapRegs_S390Instr); - genSpill = CAST_TO_TYPEOF(genSpill) S390FN(genSpill_S390); - genReload = CAST_TO_TYPEOF(genReload) S390FN(genReload_S390); - genMove = CAST_TO_TYPEOF(genMove) S390FN(genMove_S390); - // fixs390: consider implementing directReload_S390 - ppInstr = CAST_TO_TYPEOF(ppInstr) S390FN(ppS390Instr); - ppReg = CAST_TO_TYPEOF(ppReg) S390FN(ppHRegS390); - iselSB = S390FN(iselSB_S390); - emit = CAST_TO_TYPEOF(emit) S390FN(emit_S390Instr); - vassert(vta->archinfo_host.endness == VexEndnessBE); - break; + if (vec_next > 0) { + // We're resuming the current IL block having just finished + // processing a nested IL. The OOL counterpart to the nested IL + // we just finished processing will have to jump back to here. + // So we'll need to mark its Queue entry to record that fact. - case VexArchARM: - mode64 = False; - rRegUniv = ARMFN(getRRegUniverse_ARM()); - isMove = CAST_TO_TYPEOF(isMove) ARMFN(isMove_ARMInstr); - getRegUsage - = CAST_TO_TYPEOF(getRegUsage) ARMFN(getRegUsage_ARMInstr); - mapRegs = CAST_TO_TYPEOF(mapRegs) ARMFN(mapRegs_ARMInstr); - genSpill = CAST_TO_TYPEOF(genSpill) ARMFN(genSpill_ARM); - genReload = CAST_TO_TYPEOF(genReload) ARMFN(genReload_ARM); - genMove = CAST_TO_TYPEOF(genMove) ARMFN(genMove_ARM); - ppInstr = CAST_TO_TYPEOF(ppInstr) ARMFN(ppARMInstr); - ppReg = CAST_TO_TYPEOF(ppReg) ARMFN(ppHRegARM); - iselSB = ARMFN(iselSB_ARM); - emit = CAST_TO_TYPEOF(emit) ARMFN(emit_ARMInstr); - vassert(vta->archinfo_host.endness == VexEndnessLE); - break; + // First assert that the OOL actually *is* in the Queue (it + // must be, since we can't have processed it yet). + vassert(queueOldest <= queueNewest); // "at least 1 entry in Q" + vassert(queueOldest <= ool_qindex && ool_qindex <= queueNewest); - case VexArchARM64: - mode64 = True; - rRegUniv = ARM64FN(getRRegUniverse_ARM64()); - isMove = CAST_TO_TYPEOF(isMove) ARM64FN(isMove_ARM64Instr); - getRegUsage - = CAST_TO_TYPEOF(getRegUsage) ARM64FN(getRegUsage_ARM64Instr); - mapRegs = CAST_TO_TYPEOF(mapRegs) ARM64FN(mapRegs_ARM64Instr); - genSpill = CAST_TO_TYPEOF(genSpill) ARM64FN(genSpill_ARM64); - genReload = CAST_TO_TYPEOF(genReload) ARM64FN(genReload_ARM64); - genMove = CAST_TO_TYPEOF(genMove) ARM64FN(genMove_ARM64); - ppInstr = CAST_TO_TYPEOF(ppInstr) ARM64FN(ppARM64Instr); - ppReg = CAST_TO_TYPEOF(ppReg) ARM64FN(ppHRegARM64); - iselSB = ARM64FN(iselSB_ARM64); - emit = CAST_TO_TYPEOF(emit) ARM64FN(emit_ARM64Instr); - vassert(vta->archinfo_host.endness == VexEndnessLE); - break; + vassert(!queue[ool_qindex].resumePoint_valid); + queue[ool_qindex].resumePoint = cursor; + queue[ool_qindex].resumePoint_valid = True; + if (UNLIKELY(verbose_asm)) + vex_printf(" -- RESUME previous IL\n"); + } else { + // We're starting a new IL. Due to the tail-recursive nature of + // entering ILs, this means we can actually only be starting the + // outermost (top level) block for this particular Queue entry. + vassert(ool_qindex == -1); + vassert(vec == qe->oolVec); + if (UNLIKELY(verbose_asm)) + vex_printf(" -- START new IL\n"); + } - case VexArchMIPS32: - mode64 = False; - rRegUniv = MIPS32FN(getRRegUniverse_MIPS(mode64)); - isMove = CAST_TO_TYPEOF(isMove) MIPS32FN(isMove_MIPSInstr); - getRegUsage - = CAST_TO_TYPEOF(getRegUsage) MIPS32FN(getRegUsage_MIPSInstr); - mapRegs = CAST_TO_TYPEOF(mapRegs) MIPS32FN(mapRegs_MIPSInstr); - genSpill = CAST_TO_TYPEOF(genSpill) MIPS32FN(genSpill_MIPS); - genReload = CAST_TO_TYPEOF(genReload) MIPS32FN(genReload_MIPS); - genMove = CAST_TO_TYPEOF(genMove) MIPS32FN(genMove_MIPS); - ppInstr = CAST_TO_TYPEOF(ppInstr) MIPS32FN(ppMIPSInstr); - ppReg = CAST_TO_TYPEOF(ppReg) MIPS32FN(ppHRegMIPS); - iselSB = MIPS32FN(iselSB_MIPS); - emit = CAST_TO_TYPEOF(emit) MIPS32FN(emit_MIPSInstr); - vassert(vta->archinfo_host.endness == VexEndnessLE - || vta->archinfo_host.endness == VexEndnessBE); - break; + // Repeatedly process "zero or more simple HInstrs followed by (an + // IfThenElse or end-of-block)" + while (True) { - case VexArchMIPS64: - mode64 = True; - rRegUniv = MIPS64FN(getRRegUniverse_MIPS(mode64)); - isMove = CAST_TO_TYPEOF(isMove) MIPS64FN(isMove_MIPSInstr); - getRegUsage - = CAST_TO_TYPEOF(getRegUsage) MIPS64FN(getRegUsage_MIPSInstr); - mapRegs = CAST_TO_TYPEOF(mapRegs) MIPS64FN(mapRegs_MIPSInstr); - genSpill = CAST_TO_TYPEOF(genSpill) MIPS64FN(genSpill_MIPS); - genReload = CAST_TO_TYPEOF(genReload) MIPS64FN(genReload_MIPS); - genMove = CAST_TO_TYPEOF(genMove) MIPS64FN(genMove_MIPS); - ppInstr = CAST_TO_TYPEOF(ppInstr) MIPS64FN(ppMIPSInstr); - ppReg = CAST_TO_TYPEOF(ppReg) MIPS64FN(ppHRegMIPS); - iselSB = MIPS64FN(iselSB_MIPS); - emit = CAST_TO_TYPEOF(emit) MIPS64FN(emit_MIPSInstr); - vassert(vta->archinfo_host.endness == VexEndnessLE - || vta->archinfo_host.endness == VexEndnessBE); - break; + // Process "zero or more simple HInstrs" + while (vec_next < vec->insns_used + && !isIfThenElse(vec->insns[vec_next])) { + AssemblyBufferOffset cursor_next + = emitSimpleInsn( &(res->offs_profInc), &vta->host_bytes[0], + cursor, cursor_limit, vec->insns[vec_next], + &emitConsts, vta ); + if (UNLIKELY(cursor_next == cursor)) { + // We ran out of output space. Give up. + return False; + } + vec_next++; + cursor = cursor_next; + } + + // Now we've either got to the end of the hot path, or we have + // an IfThenElse. + if (vec_next >= vec->insns_used) + break; + + // So we have an IfThenElse. + HInstrIfThenElse* hite = isIfThenElse(vec->insns[vec_next]); + vassert(hite); + vassert(hite->n_phis == 0); // the regalloc will have removed them + + // Put |ite|'s OOL block in the Queue. We'll deal with it + // later. Also, generate the (skeleton) conditional branch to it, + // and collect enough information that we can create patch the + // branch later, once we know where the destination is. + vassert(queueNewest < nQUEUE-1); // else out of Queue space + queueNewest++; + queue[queueNewest].oolVec = hite->outOfLine; + queue[queueNewest].resumePoint_valid = False; // not yet known + queue[queueNewest].resumePoint = -1; // invalid + + HInstr* cond_branch + = X86Instr_JmpCond(hite->ccOOL, + queueNewest/*FOR DEBUG PRINTING ONLY*/); + AssemblyBufferOffset cursor_next + = emitSimpleInsn( &(res->offs_profInc), &vta->host_bytes[0], + cursor, cursor_limit, cond_branch, + &emitConsts, vta ); + if (UNLIKELY(cursor_next == cursor)) { + // We ran out of output space. Give up. + return False; + } + queue[queueNewest].jumpToOOLpoint_valid = True; + queue[queueNewest].jumpToOOLpoint + = collectRelocInfo_X86(cursor, cond_branch); - default: - vpanic("LibVEX_Translate: unsupported host insn set"); - } + cursor = cursor_next; - // Are the host's hardware capabilities feasible. The function will - // not return if hwcaps are infeasible in some sense. - check_hwcaps(vta->arch_host, vta->archinfo_host.hwcaps); + // Now we descend into |ite's| IL block. So we need to save + // where we are in this block, so we can resume when the inner + // one is done. + vassert(stackPtr < nSTACK-1); // else out of Stack space + stackPtr++; + stack[stackPtr].vec = vec; + stack[stackPtr].vec_next = vec_next+1; + stack[stackPtr].ool_qindex = queueNewest; + // And now descend into the inner block. We could have just + // pushed its details on the stack and immediately pop it, but + // it seems simpler to update |vec| and |vec_next| and continue + // directly. + if (UNLIKELY(verbose_asm)) { + vex_printf(" -- START inner IL\n"); + } + vec = hite->fallThrough; + vec_next = 0; - /* Turn it into virtual-registerised code. Build trees -- this - also throws away any dead bindings. */ - max_ga = ado_treebuild_BB( irsb, preciseMemExnsFn, pxControl ); + // And continue with "Repeatedly process ..." + } - if (vta->finaltidy) { - irsb = vta->finaltidy(irsb); - } + // Getting here means we've completed an inner IL and now want to + // resume the parent IL. That is, pop a saved context off the + // stack. + } - vexAllocSanityCheck(); + // Hot path is complete. Now, probably, we have to add a jump + // back to the resume point. + if (qe->resumePoint_valid) { + if (0) + vex_printf(" // Generate jump to resume point [%03u]\n", + qe->resumePoint); + HInstr* jmp = X86Instr_Jmp(cursor, qe->resumePoint); + AssemblyBufferOffset cursor_next + = emitSimpleInsn( &(res->offs_profInc), &vta->host_bytes[0], + cursor, cursor_limit, jmp, + &emitConsts, vta ); + if (UNLIKELY(cursor_next == cursor)) { + // We ran out of output space. Give up. + return False; + } + cursor = cursor_next; + } - if (vex_traceflags & VEX_TRACE_TREES) { - vex_printf("\n------------------------" - " After tree-building " - "------------------------\n\n"); - ppIRSB ( irsb ); - vex_printf("\n"); + if (UNLIKELY(verbose_asm)) + vex_printf("END queue[%d]\n\n", qCur); + // Finished with this Queue entry. } + // Queue empty, all blocks processed - /* HACK */ - if (0) { - *(vta->host_bytes_used) = 0; - res->status = VexTransOK; return; - } - /* end HACK */ + *(vta->host_bytes_used) = cursor; - if (vex_traceflags & VEX_TRACE_VCODE) - vex_printf("\n------------------------" - " Instruction selection " - "------------------------\n"); + return True; // OK +} - /* No guest has its IP field at offset zero. If this fails it - means some transformation pass somewhere failed to update/copy - irsb->offsIP properly. */ - vassert(irsb->offsIP >= 16); - vcode = iselSB ( irsb, vta->arch_host, - &vta->archinfo_host, - &vta->abiinfo_both, - offB_HOST_EvC_COUNTER, - offB_HOST_EvC_FAILADDR, - chainingAllowed, - vta->addProfInc, - max_ga ); +/* ---- The back end proper ---- */ - vexAllocSanityCheck(); +/* Back end of the compilation pipeline. Is not exported. */ - if (vex_traceflags & VEX_TRACE_VCODE) - vex_printf("\n"); +static void libvex_BackEnd ( const VexTranslateArgs* vta, + /*MOD*/ VexTranslateResult* res, + /*MOD*/ IRSB* irsb, + VexRegisterUpdates pxControl ) +{ + /* This the bundle of functions we need to do the back-end stuff + (insn selection, reg-alloc, assembly) whilst being insulated + from the target instruction set. */ + Bool (*isMove) ( const HInstr*, HReg*, HReg* ); + void (*getRegUsage) ( HRegUsage*, const HInstr*, Bool ); + void (*mapRegs) ( HRegRemap*, HInstr*, Bool ); + HInstrIfThenElse* (*isIfThenElse)( const HInstr* ); + void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool ); + void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool ); + HInstr* (*genMove) ( HReg, HReg, Bool ); + HInstr* (*genHInstrITE) ( HInstrIfThenElse* ); + HInstr* (*directReload) ( HInstr*, HReg, Short ); + void (*ppInstr) ( const HInstr*, Bool ); + void (*ppCondCode) ( HCondCode ); + UInt (*ppReg) ( HReg ); + HInstrSB* (*iselSB) ( const IRSB*, VexArch, const VexArchInfo*, + const VexAbiInfo*, Int, Int, Bool, Bool, + Addr ); + Int (*emit) ( /*MB_MOD*/Bool*, + UChar*, Int, const HInstr*, Bool, VexEndness, + const void*, const void*, const void*, + const void* ); + Bool (*preciseMemExnsFn) ( Int, Int, VexRegisterUpdates ); - if (vex_traceflags & VEX_TRACE_VCODE) { - ppHInstrSB(vcode, isIfThenElse, ppInstr, ppCondCode, mode64); - } + const RRegUniverse* rRegUniv = NULL; - /* Register allocate. */ - RegAllocControl con = { - .univ = rRegUniv, .isMove = isMove, .getRegUsage = getRegUsage, - .mapRegs = mapRegs, .isIfThenElse = isIfThenElse, .genSpill = genSpill, - .genReload = genReload, .genMove = genMove, .genHInstrITE = genHInstrITE, - .directReload = directReload, .guest_sizeB = guest_sizeB, - .ppInstr = ppInstr, .ppCondCode = ppCondCode, .ppReg = ppReg, - .mode64 = mode64}; - rcode = doRegisterAllocation(vcode, &con); + Bool mode64, chainingAllowed; + Int guest_sizeB; + Int offB_HOST_EvC_COUNTER; + Int offB_HOST_EvC_FAILADDR; + Addr max_ga; + HInstrSB* vcode; + HInstrSB* rcode; - vexAllocSanityCheck(); + isMove = NULL; + getRegUsage = NULL; + mapRegs = NULL; + isIfThenElse = NULL; + genSpill = NULL; + genReload = NULL; + genMove = NULL; + genHInstrITE = NULL; + directReload = NULL; + ppInstr = NULL; + ppCondCode = NULL; + ppReg = NULL; + iselSB = NULL; + emit = NULL; - if (vex_traceflags & VEX_TRACE_RCODE) { - vex_printf("\n------------------------" - " Register-allocated code " - "------------------------\n\n"); - ppHInstrSB(rcode, isIfThenElse, ppInstr, ppCondCode, mode64); - vex_printf("\n"); - } + mode64 = False; + chainingAllowed = False; + guest_sizeB = 0; + offB_HOST_EvC_COUNTER = 0; + offB_HOST_EvC_FAILADDR = 0; + preciseMemExnsFn = NULL; - /* HACK */ - if (0) { - *(vta->host_bytes_used) = 0; - res->status = VexTransOK; return; - } - /* end HACK */ + vassert(vex_initdone); + vassert(vta->disp_cp_xassisted != NULL); - /* Assemble */ - if (vex_traceflags & VEX_TRACE_ASM) { - vex_printf("\n------------------------" - " Assembly " - "------------------------\n\n"); + vex_traceflags = vta->traceflags; + + /* Both the chainers and the indir are either NULL or non-NULL. */ + if (vta->disp_cp_chain_me_to_slowEP != NULL) { + vassert(vta->disp_cp_chain_me_to_fastEP != NULL); + vassert(vta->disp_cp_xindir != NULL); + chainingAllowed = True; + } else { + vassert(vta->disp_cp_chain_me_to_fastEP == NULL); + vassert(vta->disp_cp_xindir == NULL); } - //////////////////////////////////////////////////////// - //// BEGIN the assembler + switch (vta->arch_guest) { - // QElem are work Queue elements. The work Queue is the top level data - // structure for the emitter. It is initialised with the HInstrVec* of - // the overall HInstrSB. Every OOL HInstrVec* in the tree will at some - // point be present in the Queue. IL HInstrVec*s are never present in - // the Queue because the inner emitter loop processes them in-line, using - // a Stack (see below) to keep track of its nesting level. - // - // The Stack (see below) is empty before and after every Queue element is - // processed. In other words, the Stack only holds state needed during - // the processing of a single Queue element. - // - // The ordering of elements in the Queue is irrelevant -- correct code - // will be emitted even with set semantics (arbitrary order). However, - // the FIFOness of the queue is believed to generate code in which - // colder and colder code (more deeply nested OOLs) is placed further - // and further from the start of the emitted machine code, which sounds - // like a layout which should minimise icache misses. - // - // QElems also contain two pieces of jump-fixup information. When we - // finally come to process a QElem, we need to know: - // - // * |jumpToOOLpoint|: the place which wants to jump to the start of the - // emitted insns for this QElem. We must have already emitted that, - // since it will be the conditional jump that leads to this QElem (OOL - // block). - // - // * |resumePoint|: the place we should jump back to after the QElem is - // finished (the "resume point"), which is the emitted code of the - // HInstr immediately following the HInstrIfThenElse that has this - // QElem as its OOL block. - // - // When the QElem is processed, we know both the |jumpToOOLpoint| and - // the |resumePoint|, and so the first can be patched, and the second - // we generate an instruction to jump to. - // - // There are three complications with patching: - // - // (1) per comments on Stack elems, we do not know the |resumePoint| when - // creating a QElem. That will only be known when processing of the - // corresponding IL block is completed. - // - // (2) The top level HInstrVec* has neither a |jumpToOOLpoint| nor a - // |resumePoint|. - // - // (3) Non-top-level OOLs may not have a valid |resumePoint| if they do - // an unconditional IR-level Exit. We can generate the resume point - // branch, but it will be never be used. - typedef - struct { - // The HInstrs for this OOL. - HInstrVec* oolVec; - // Where we should patch to jump to the OOL ("how do we get here?") - Bool jumpToOOLpoint_valid; - Relocation jumpToOOLpoint; - // Resume point offset, in bytes from start of output buffer - // ("where do we go after this block is completed?") - Bool resumePoint_valid; - AssemblyBufferOffset resumePoint; - } - QElem; + case VexArchX86: + preciseMemExnsFn + = X86FN(guest_x86_state_requires_precise_mem_exns); + guest_sizeB = sizeof(VexGuestX86State); + offB_HOST_EvC_COUNTER = offsetof(VexGuestX86State,host_EvC_COUNTER); + offB_HOST_EvC_FAILADDR = offsetof(VexGuestX86State,host_EvC_FAILADDR); + break; + + case VexArchAMD64: + preciseMemExnsFn + = AMD64FN(guest_amd64_state_requires_precise_mem_exns); + guest_sizeB = sizeof(VexGuestAMD64State); + offB_HOST_EvC_COUNTER = offsetof(VexGuestAMD64State,host_EvC_COUNTER); + offB_HOST_EvC_FAILADDR = offsetof(VexGuestAMD64State,host_EvC_FAILADDR); + break; + case VexArchPPC32: + preciseMemExnsFn + = PPC32FN(guest_ppc32_state_requires_precise_mem_exns); + guest_sizeB = sizeof(VexGuestPPC32State); + offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC32State,host_EvC_COUNTER); + offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC32State,host_EvC_FAILADDR); + break; - // SElem are stack elements. When we suspend processing a HInstrVec* in - // order to process an IL path in an IfThenElse, we push the HInstrVec* - // and the next index to process on the stack, so that we know where to - // resume when the nested IL sequence is completed. |vec| and |vec_next| - // record the resume HInstr. - // - // A second effect of processing a nested IL sequence is that we will - // have to (later) process the corresponding OOL sequence. And that OOL - // sequence will have to finish with a jump back to the "resume point" - // (the emitted instruction immediately following the IfThenElse). We - // only know the offset of the resume point instruction in the output - // buffer when we actually resume emitted from there -- that is, when the - // entry we pushed, is popped. So, when we pop, we must mark the - // corresponding OOL entry in the Queue to record there the resume point - // offset. For this reason we also carry |ool_qindex|, which is the - // index of the corresponding OOL entry in the Queue. - typedef - struct { - HInstrVec* vec; // resume point HInstr vector - UInt vec_next; // resume point HInstr vector index - Int ool_qindex; // index in Queue of OOL to mark when we resume - } - SElem; + case VexArchPPC64: + preciseMemExnsFn + = PPC64FN(guest_ppc64_state_requires_precise_mem_exns); + guest_sizeB = sizeof(VexGuestPPC64State); + offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC64State,host_EvC_COUNTER); + offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC64State,host_EvC_FAILADDR); + break; - // The Stack. The stack depth is bounded by maximum number of nested - // hot (IL) sections, so in practice it is going to be very small. - const Int nSTACK = 4; + case VexArchS390X: + preciseMemExnsFn + = S390FN(guest_s390x_state_requires_precise_mem_exns); + guest_sizeB = sizeof(VexGuestS390XState); + offB_HOST_EvC_COUNTER = offsetof(VexGuestS390XState,host_EvC_COUNTER); + offB_HOST_EvC_FAILADDR = offsetof(VexGuestS390XState,host_EvC_FAILADDR); + break; - SElem stack[nSTACK]; - Int stackPtr; // points to most recently pushed entry <=> "-1 means empty" + case VexArchARM: + preciseMemExnsFn + = ARMFN(guest_arm_state_requires_precise_mem_exns); + guest_sizeB = sizeof(VexGuestARMState); + offB_HOST_EvC_COUNTER = offsetof(VexGuestARMState,host_EvC_COUNTER); + offB_HOST_EvC_FAILADDR = offsetof(VexGuestARMState,host_EvC_FAILADDR); + break; - // The Queue. The queue size is bounded by the number of cold (OOL) - // sections in the entire HInstrSB, so it's also going to be pretty - // small. - const Int nQUEUE = 8; + case VexArchARM64: + preciseMemExnsFn + = ARM64FN(guest_arm64_state_requires_precise_mem_exns); + guest_sizeB = sizeof(VexGuestARM64State); + offB_HOST_EvC_COUNTER = offsetof(VexGuestARM64State,host_EvC_COUNTER); + offB_HOST_EvC_FAILADDR = offsetof(VexGuestARM64State,host_EvC_FAILADDR); + break; - QElem queue[nQUEUE]; - Int queueOldest; // index of oldest entry, initially 0 - Int queueNewest; // index of newest entry, - // initially -1, otherwise must be >= queueOldest + case VexArchMIPS32: + preciseMemExnsFn + = MIPS32FN(guest_mips32_state_requires_precise_mem_exns); + guest_sizeB = sizeof(VexGuestMIPS32State); + offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS32State,host_EvC_COUNTER); + offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR); + break; - /////////////////////////////////////////////////////// + case VexArchMIPS64: + preciseMemExnsFn + = MIPS64FN(guest_mips64_state_requires_precise_mem_exns); + guest_sizeB = sizeof(VexGuestMIPS64State); + offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS64State,host_EvC_COUNTER); + offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS64State,host_EvC_FAILADDR); + break; - const Bool verbose_asm = (vex_traceflags & VEX_TRACE_ASM) != 0; + default: + vpanic("LibVEX_Codegen: unsupported guest insn set"); + } - const EmitConstants emitConsts - = { .mode64 = mode64, - .endness_host = vta->archinfo_host.endness, - .disp_cp_chain_me_to_slowEP = vta->disp_cp_chain_me_to_slowEP, - .disp_cp_chain_me_to_fastEP = vta->disp_cp_chain_me_to_fastEP, - .disp_cp_xindir = vta->disp_cp_xindir, - .disp_cp_xassisted = vta->disp_cp_xassisted }; - AssemblyBufferOffset cursor = 0; - AssemblyBufferOffset cursor_limit = vta->host_bytes_size; + switch (vta->arch_host) { - queueOldest = 0; - queueNewest = -1; + case VexArchX86: + mode64 = False; + rRegUniv = X86FN(getRRegUniverse_X86()); + isMove = CAST_TO_TYPEOF(isMove) X86FN(isMove_X86Instr); + getRegUsage + = CAST_TO_TYPEOF(getRegUsage) X86FN(getRegUsage_X86Instr); + mapRegs = CAST_TO_TYPEOF(mapRegs) X86FN(mapRegs_X86Instr); + isIfThenElse = CAST_TO_TYPEOF(isIfThenElse) X86FN(isIfThenElse_X86Instr); + genSpill = CAST_TO_TYPEOF(genSpill) X86FN(genSpill_X86); + genReload = CAST_TO_TYPEOF(genReload) X86FN(genReload_X86); + genMove = CAST_TO_TYPEOF(genMove) X86FN(genMove_X86); + genHInstrITE = CAST_TO_TYPEOF(genHInstrITE) X86FN(X86Instr_IfThenElse); + directReload = CAST_TO_TYPEOF(directReload) X86FN(directReload_X86); + ppInstr = CAST_TO_TYPEOF(ppInstr) X86FN(ppX86Instr); + ppCondCode = CAST_TO_TYPEOF(ppCondCode) X86FN(ppX86CondCode); + ppReg = CAST_TO_TYPEOF(ppReg) X86FN(ppHRegX86); + iselSB = X86FN(iselSB_X86); + emit = CAST_TO_TYPEOF(emit) X86FN(emit_X86Instr); + vassert(vta->archinfo_host.endness == VexEndnessLE); + break; - vassert(queueNewest < nQUEUE); - queueNewest++; - { - QElem* qe = &queue[queueNewest]; - vex_bzero(qe, sizeof(*qe)); - qe->oolVec = rcode->insns; - qe->jumpToOOLpoint_valid = False; - qe->resumePoint_valid = False; - } - vassert(queueNewest == 0); + case VexArchAMD64: + mode64 = True; + rRegUniv = AMD64FN(getRRegUniverse_AMD64()); + isMove = CAST_TO_TYPEOF(isMove) AMD64FN(isMove_AMD64Instr); + getRegUsage + = CAST_TO_TYPEOF(getRegUsage) AMD64FN(getRegUsage_AMD64Instr); + mapRegs = CAST_TO_TYPEOF(mapRegs) AMD64FN(mapRegs_AMD64Instr); + genSpill = CAST_TO_TYPEOF(genSpill) AMD64FN(genSpill_AMD64); + genReload = CAST_TO_TYPEOF(genReload) AMD64FN(genReload_AMD64); + genMove = CAST_TO_TYPEOF(genMove) AMD64FN(genMove_AMD64); + directReload = CAST_TO_TYPEOF(directReload) AMD64FN(directReload_AMD64); + ppInstr = CAST_TO_TYPEOF(ppInstr) AMD64FN(ppAMD64Instr); + ppReg = CAST_TO_TYPEOF(ppReg) AMD64FN(ppHRegAMD64); + iselSB = AMD64FN(iselSB_AMD64); + emit = CAST_TO_TYPEOF(emit) AMD64FN(emit_AMD64Instr); + vassert(vta->archinfo_host.endness == VexEndnessLE); + break; - /* Main loop, processing Queue entries, until there are no more. */ - while (queueOldest <= queueNewest) { + case VexArchPPC32: + mode64 = False; + rRegUniv = PPC32FN(getRRegUniverse_PPC(mode64)); + isMove = CAST_TO_TYPEOF(isMove) PPC32FN(isMove_PPCInstr); + getRegUsage + = CAST_TO_TYPEOF(getRegUsage) PPC32FN(getRegUsage_PPCInstr); + mapRegs = CAST_TO_TYPEOF(mapRegs) PPC32FN(mapRegs_PPCInstr); + genSpill = CAST_TO_TYPEOF(genSpill) PPC32FN(genSpill_PPC); + genReload = CAST_TO_TYPEOF(genReload) PPC32FN(genReload_PPC); + genMove = CAST_TO_TYPEOF(genMove) PPC32FN(genMove_PPC); + ppInstr = CAST_TO_TYPEOF(ppInstr) PPC32FN(ppPPCInstr); + ppReg = CAST_TO_TYPEOF(ppReg) PPC32FN(ppHRegPPC); + iselSB = PPC32FN(iselSB_PPC); + emit = CAST_TO_TYPEOF(emit) PPC32FN(emit_PPCInstr); + vassert(vta->archinfo_host.endness == VexEndnessBE); + break; - Int qCur = queueOldest; - if (UNLIKELY(verbose_asm)) - vex_printf("BEGIN queue[%d]\n", qCur); + case VexArchPPC64: + mode64 = True; + rRegUniv = PPC64FN(getRRegUniverse_PPC(mode64)); + isMove = CAST_TO_TYPEOF(isMove) PPC64FN(isMove_PPCInstr); + getRegUsage + = CAST_TO_TYPEOF(getRegUsage) PPC64FN(getRegUsage_PPCInstr); + mapRegs = CAST_TO_TYPEOF(mapRegs) PPC64FN(mapRegs_PPCInstr); + genSpill = CAST_TO_TYPEOF(genSpill) PPC64FN(genSpill_PPC); + genReload = CAST_TO_TYPEOF(genReload) PPC64FN(genReload_PPC); + genMove = CAST_TO_TYPEOF(genMove) PPC64FN(genMove_PPC); + ppInstr = CAST_TO_TYPEOF(ppInstr) PPC64FN(ppPPCInstr); + ppReg = CAST_TO_TYPEOF(ppReg) PPC64FN(ppHRegPPC); + iselSB = PPC64FN(iselSB_PPC); + emit = CAST_TO_TYPEOF(emit) PPC64FN(emit_PPCInstr); + vassert(vta->archinfo_host.endness == VexEndnessBE || + vta->archinfo_host.endness == VexEndnessLE ); + break; - // Take the oldest entry in the queue - QElem* qe = &queue[queueOldest]; - queueOldest++; + case VexArchS390X: + mode64 = True; + rRegUniv = S390FN(getRRegUniverse_S390()); + isMove = CAST_TO_TYPEOF(isMove) S390FN(isMove_S390Instr); + getRegUsage + = CAST_TO_TYPEOF(getRegUsage) S390FN(getRegUsage_S390Instr); + mapRegs = CAST_TO_TYPEOF(mapRegs) S390FN(mapRegs_S390Instr); + genSpill = CAST_TO_TYPEOF(genSpill) S390FN(genSpill_S390); + genReload = CAST_TO_TYPEOF(genReload) S390FN(genReload_S390); + genMove = CAST_TO_TYPEOF(genMove) S390FN(genMove_S390); + // fixs390: consider implementing directReload_S390 + ppInstr = CAST_TO_TYPEOF(ppInstr) S390FN(ppS390Instr); + ppReg = CAST_TO_TYPEOF(ppReg) S390FN(ppHRegS390); + iselSB = S390FN(iselSB_S390); + emit = CAST_TO_TYPEOF(emit) S390FN(emit_S390Instr); + vassert(vta->archinfo_host.endness == VexEndnessBE); + break; - // Stay sane. Only the top level block has no branch to it and no - // resume point. - if (qe->oolVec == rcode->insns) { - // This is the top level block - vassert(!qe->jumpToOOLpoint_valid); - vassert(!qe->resumePoint_valid); - } else { - vassert(qe->jumpToOOLpoint_valid); - vassert(qe->resumePoint_valid); - // In the future, we might be able to allow the resume point to be - // invalid for non-top-level blocks, if the block contains an - // unconditional exit. Currently the IR can't represent that, so - // the assertion is valid. - } + case VexArchARM: + mode64 = False; + rRegUniv = ARMFN(getRRegUniverse_ARM()); + isMove = CAST_TO_TYPEOF(isMove) ARMFN(isMove_ARMInstr); + getRegUsage + = CAST_TO_TYPEOF(getRegUsage) ARMFN(getRegUsage_ARMInstr); + mapRegs = CAST_TO_TYPEOF(mapRegs) ARMFN(mapRegs_ARMInstr); + genSpill = CAST_TO_TYPEOF(genSpill) ARMFN(genSpill_ARM); + genReload = CAST_TO_TYPEOF(genReload) ARMFN(genReload_ARM); + genMove = CAST_TO_TYPEOF(genMove) ARMFN(genMove_ARM); + ppInstr = CAST_TO_TYPEOF(ppInstr) ARMFN(ppARMInstr); + ppReg = CAST_TO_TYPEOF(ppReg) ARMFN(ppHRegARM); + iselSB = ARMFN(iselSB_ARM); + emit = CAST_TO_TYPEOF(emit) ARMFN(emit_ARMInstr); + vassert(vta->archinfo_host.endness == VexEndnessLE); + break; - // Processing |qe| - if (qe->jumpToOOLpoint_valid) { - // patch qe->jmpToOOLpoint to jump to |here| - if (UNLIKELY(verbose_asm)) { - vex_printf(" -- APPLY "); - ppRelocation(qe->jumpToOOLpoint); - vex_printf("\n"); - } - applyRelocation(qe->jumpToOOLpoint, &vta->host_bytes[0], - cursor, cursor, vta->archinfo_host.endness, - verbose_asm); - } + case VexArchARM64: + mode64 = True; + rRegUniv = ARM64FN(getRRegUniverse_ARM64()); + isMove = CAST_TO_TYPEOF(isMove) ARM64FN(isMove_ARM64Instr); + getRegUsage + = CAST_TO_TYPEOF(getRegUsage) ARM64FN(getRegUsage_ARM64Instr); + mapRegs = CAST_TO_TYPEOF(mapRegs) ARM64FN(mapRegs_ARM64Instr); + genSpill = CAST_TO_TYPEOF(genSpill) ARM64FN(genSpill_ARM64); + genReload = CAST_TO_TYPEOF(genReload) ARM64FN(genReload_ARM64); + genMove = CAST_TO_TYPEOF(genMove) ARM64FN(genMove_ARM64); + ppInstr = CAST_TO_TYPEOF(ppInstr) ARM64FN(ppARM64Instr); + ppReg = CAST_TO_TYPEOF(ppReg) ARM64FN(ppHRegARM64); + iselSB = ARM64FN(iselSB_ARM64); + emit = CAST_TO_TYPEOF(emit) ARM64FN(emit_ARM64Instr); + vassert(vta->archinfo_host.endness == VexEndnessLE); + break; - // Initialise the stack, for processing of |qe|. - stackPtr = 0; // "contains one element" + case VexArchMIPS32: + mode64 = False; + rRegUniv = MIPS32FN(getRRegUniverse_MIPS(mode64)); + isMove = CAST_TO_TYPEOF(isMove) MIPS32FN(isMove_MIPSInstr); + getRegUsage + = CAST_TO_TYPEOF(getRegUsage) MIPS32FN(getRegUsage_MIPSInstr); + mapRegs = CAST_TO_TYPEOF(mapRegs) MIPS32FN(mapRegs_MIPSInstr); + genSpill = CAST_TO_TYPEOF(genSpill) MIPS32FN(genSpill_MIPS); + genReload = CAST_TO_TYPEOF(genReload) MIPS32FN(genReload_MIPS); + genMove = CAST_TO_TYPEOF(genMove) MIPS32FN(genMove_MIPS); + ppInstr = CAST_TO_TYPEOF(ppInstr) MIPS32FN(ppMIPSInstr); + ppReg = CAST_TO_TYPEOF(ppReg) MIPS32FN(ppHRegMIPS); + iselSB = MIPS32FN(iselSB_MIPS); + emit = CAST_TO_TYPEOF(emit) MIPS32FN(emit_MIPSInstr); + vassert(vta->archinfo_host.endness == VexEndnessLE + || vta->archinfo_host.endness == VexEndnessBE); + break; - stack[stackPtr].vec = qe->oolVec; - stack[stackPtr].vec_next = 0; - stack[stackPtr].ool_qindex = -1; // INVALID + case VexArchMIPS64: + mode64 = True; + rRegUniv = MIPS64FN(getRRegUniverse_MIPS(mode64)); + isMove = CAST_TO_TYPEOF(isMove) MIPS64FN(isMove_MIPSInstr); + getRegUsage + = CAST_TO_TYPEOF(getRegUsage) MIPS64FN(getRegUsage_MIPSInstr); + mapRegs = CAST_TO_TYPEOF(mapRegs) MIPS64FN(mapRegs_MIPSInstr); + genSpill = CAST_TO_TYPEOF(genSpill) MIPS64FN(genSpill_MIPS); + genReload = CAST_TO_TYPEOF(genReload) MIPS64FN(genReload_MIPS); + genMove = CAST_TO_TYPEOF(genMove) MIPS64FN(genMove_MIPS); + ppInstr = CAST_TO_TYPEOF(ppInstr) MIPS64FN(ppMIPSInstr); + ppReg = CAST_TO_TYPEOF(ppReg) MIPS64FN(ppHRegMIPS); + iselSB = MIPS64FN(iselSB_MIPS); + emit = CAST_TO_TYPEOF(emit) MIPS64FN(emit_MIPSInstr); + vassert(vta->archinfo_host.endness == VexEndnessLE + || vta->archinfo_host.endness == VexEndnessBE); + break; - // Iterate till the stack is empty. This effectively does a - // depth-first traversal of the hot-path (IL) tree reachable from - // here, and at the same time adds any encountered cold-path (OOL) - // blocks to the Queue for later processing. This is the heart of the - // flattening algorithm. - while (stackPtr >= 0) { + default: + vpanic("LibVEX_Translate: unsupported host insn set"); + } - if (UNLIKELY(verbose_asm)) - vex_printf(" -- CONSIDER stack[%d]\n", stackPtr); + // Are the host's hardware capabilities feasible. The function will + // not return if hwcaps are infeasible in some sense. + check_hwcaps(vta->arch_host, vta->archinfo_host.hwcaps); - HInstrVec* vec = stack[stackPtr].vec; - UInt vec_next = stack[stackPtr].vec_next; - Int ool_qindex = stack[stackPtr].ool_qindex; - stackPtr--; - if (vec_next > 0) { - // We're resuming the current IL block having just finished - // processing a nested IL. The OOL counterpart to the nested IL - // we just finished processing will have to jump back to here. - // So we'll need to mark its Queue entry to record that fact. + /* Turn it into virtual-registerised code. Build trees -- this + also throws away any dead bindings. */ + max_ga = ado_treebuild_BB( irsb, preciseMemExnsFn, pxControl ); - // First assert that the OOL actually *is* in the Queue (it - // must be, since we can't have processed it yet). - vassert(queueOldest <= queueNewest); // "at least 1 entry in Q" - vassert(queueOldest <= ool_qindex && ool_qindex <= queueNewest); + if (vta->finaltidy) { + irsb = vta->finaltidy(irsb); + } - vassert(!queue[ool_qindex].resumePoint_valid); - queue[ool_qindex].resumePoint = cursor; - queue[ool_qindex].resumePoint_valid = True; - if (UNLIKELY(verbose_asm)) - vex_printf(" -- RESUME previous IL\n"); - } else { - // We're starting a new IL. Due to the tail-recursive nature of - // entering ILs, this means we can actually only be starting the - // outermost (top level) block for this particular Queue entry. - vassert(ool_qindex == -1); - vassert(vec == qe->oolVec); - if (UNLIKELY(verbose_asm)) - vex_printf(" -- START new IL\n"); - } + vexAllocSanityCheck(); - ... [truncated message content] |
|
From: Petar J. <pe...@so...> - 2017-10-02 12:55:54
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=da3987aa18e77a8b4eb8176eed705b1aeb5c1151 commit da3987aa18e77a8b4eb8176eed705b1aeb5c1151 Author: Petar Jovanovic <mip...@gm...> Date: Mon Oct 2 14:54:20 2017 +0200 mips32: add BE-exp files for several tests This fixes several tests on mips32 BE platforms: memcheck/tests/mips32/fadvise64 drd/tests/tc19_shadowmem helgrind/tests/tc19_shadowmem Diff: --- drd/tests/Makefile.am | 1 + drd/tests/tc19_shadowmem.stderr.exp-32bit-BE | 4224 +++ helgrind/tests/Makefile.am | 1 + helgrind/tests/tc19_shadowmem.stderr.exp-mips32-BE | 26122 +++++++++++++++++++ memcheck/tests/mips32/Makefile.am | 3 +- memcheck/tests/mips32/fadvise64.stderr.exp-BE | 24 + 6 files changed, 30374 insertions(+), 1 deletion(-) diff --git a/drd/tests/Makefile.am b/drd/tests/Makefile.am index bafa412..9b604e9 100644 --- a/drd/tests/Makefile.am +++ b/drd/tests/Makefile.am @@ -321,6 +321,7 @@ EXTRA_DIST = \ tc18_semabuse.stderr.exp-solaris \ tc18_semabuse.vgtest \ tc19_shadowmem.stderr.exp-32bit \ + tc19_shadowmem.stderr.exp-32bit-BE \ tc19_shadowmem.stderr.exp-64bit \ tc19_shadowmem.vgtest \ tc21_pthonce.stderr.exp \ diff --git a/drd/tests/tc19_shadowmem.stderr.exp-32bit-BE b/drd/tests/tc19_shadowmem.stderr.exp-32bit-BE new file mode 100644 index 0000000..64f20bf --- /dev/null +++ b/drd/tests/tc19_shadowmem.stderr.exp-32bit-BE @@ -0,0 +1,4224 @@ + + +=========================================================== +=== 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 === +=========================================================== + +---------- char gran, 0 .. 99, skip 0 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:288) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 0 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 1 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:290) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 1 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 2 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:292) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 2 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 3 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:294) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 3 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 4 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:296) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 4 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 5 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:298) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 5 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 6 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:300) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 6 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 7 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:302) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 7 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 8 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:304) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 8 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 9 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:306) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 9 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 10 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:308) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 10 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 11 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:310) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 11 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 12 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:312) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 12 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 13 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:314) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 13 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 14 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:316) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 14 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 15 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:318) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 15 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 16 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:320) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 16 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 17 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:322) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 17 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 18 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:324) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 18 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 19 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:326) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 19 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 20 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:328) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 20 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 21 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:330) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 21 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 22 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:332) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 22 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 23 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:334) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 23 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 24 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:336) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 24 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 25 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:338) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 25 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 26 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:340) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 26 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 27 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:342) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 27 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 28 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:344) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 28 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 29 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:346) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 29 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 30 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:348) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 30 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 31 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:350) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 31 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 32 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:352) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 32 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 33 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:354) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 33 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 34 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:356) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 34 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 35 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:358) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 35 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 36 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:360) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 36 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 37 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:362) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 37 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 38 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:364) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 38 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 39 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:366) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 39 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 40 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:368) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 40 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 41 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:370) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 41 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 42 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:372) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 42 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 43 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:374) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 43 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 44 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:376) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 44 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 45 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:378) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 45 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 46 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:380) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 46 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 47 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:382) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 47 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 48 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:384) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 48 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 49 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:386) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 49 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 50 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:388) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 50 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 51 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:390) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 51 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 52 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:392) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 52 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 53 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:394) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 53 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 54 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:396) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 54 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 55 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:398) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 55 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 56 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:400) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 56 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 57 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:402) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 57 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 58 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:404) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 58 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 59 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:406) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 59 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 60 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:408) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 60 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 61 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:410) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 61 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 62 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:412) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 62 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 63 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:414) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 63 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 64 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:416) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 64 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 65 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:418) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 65 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 66 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:420) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 66 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 67 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:422) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 67 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 68 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:424) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 68 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 69 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:426) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 69 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 70 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:428) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 70 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 71 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:430) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 71 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 72 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:432) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 72 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 73 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:434) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 73 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 74 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:436) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 74 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 75 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:438) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 75 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 76 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:440) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 76 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 77 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:442) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 77 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 78 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:444) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 78 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 79 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:446) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 79 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 80 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:448) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 80 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 81 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:450) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 81 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 82 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:452) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 82 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 83 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:454) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 83 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 84 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:456) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 84 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 85 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:458) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 85 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 86 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:460) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 86 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 87 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:462) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 87 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 88 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:464) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 88 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 89 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:466) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 89 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 90 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:468) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 90 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 91 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:470) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 91 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 92 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:472) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 92 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 93 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:474) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 93 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 94 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:476) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 94 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 95 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:478) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 95 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 96 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:480) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 96 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 97 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:482) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 97 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- char gran, 0 .. 99, skip 98 ---------- +Conflicting store by thread x at 0x........ size 1 + at 0x........: child8 (tc19_shadowmem.c:33) + by 0x........: steer (tc19_shadowmem.c:484) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 98 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + + +========================================================== +=== 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 === +========================================================== + +---------- short gran, 0 .. 98, skip 0 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:288) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 0 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 1 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:290) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 1 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 2 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:292) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 2 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 3 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:294) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 3 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 4 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:296) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 4 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 5 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:298) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 5 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 6 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:300) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 6 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 7 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:302) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 7 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 8 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:304) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 8 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 9 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:306) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 9 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 10 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:308) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 10 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 11 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:310) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 11 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 12 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:312) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 12 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 13 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:314) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 13 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 14 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:316) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 14 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 15 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:318) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 15 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 16 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:320) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 16 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 17 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:322) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 17 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 18 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:324) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 18 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 19 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:326) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 19 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 20 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:328) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 20 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 21 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:330) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 21 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 22 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:332) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 22 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 23 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:334) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 23 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 24 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:336) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 24 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 25 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:338) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 25 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 26 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:340) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 26 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 27 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:342) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 27 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 28 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:344) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 28 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 29 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:346) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 29 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 30 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:348) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 30 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 31 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:350) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 31 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 0 .. 98, skip 32 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:352) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is at offset 32 from 0x......... Allocation context: + at 0x........: malloc (vg_replace_malloc.c:...) + by 0x........: main (tc19_shadowmem.c:144) + +---------- short gran, 1 .. 98, skip 33 ---------- +Conflicting store by thread x at 0x........ size 2 + at 0x........: child16 (tc19_shadowmem.c:57) + by 0x........: steer (tc19_shadowmem.c:354) + by 0x........: vgDrd_thread_wrapper (drd_pthread_intercepts.c:?) +Address 0x........ is ... [truncated message content] |
|
From: Petar J. <pe...@so...> - 2017-10-02 11:40:27
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=f3637a085306f3dbb22c52d953b23bd76a85178c commit f3637a085306f3dbb22c52d953b23bd76a85178c Author: Petar Jovanovic <mip...@gm...> Date: Mon Oct 2 13:28:50 2017 +0200 mips: make sure configure script checks for correct ABIs For mips64, we currently build for n64. For mips32, we currently build for o32. Pass these flags explicitly in configure checks. Diff: --- configure.ac | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/configure.ac b/configure.ac index 483d9bd..392081d 100644 --- a/configure.ac +++ b/configure.ac @@ -1720,15 +1720,15 @@ AC_SUBST(FLAG_M64) # does this compiler support -march=mips32 (mips32 default) ? -AC_MSG_CHECKING([if gcc accepts -march=mips32]) +AC_MSG_CHECKING([if gcc accepts -march=mips32 -mabi=32]) safe_CFLAGS=$CFLAGS -CFLAGS="$CFLAGS -march=mips32 -Werror" +CFLAGS="$CFLAGS -march=mips32 -mabi=32 -Werror" AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[ return 0; ]])], [ -FLAG_MIPS32="-march=mips32" +FLAG_MIPS32="-march=mips32 -mabi=32" AC_MSG_RESULT([yes]) ], [ FLAG_MIPS32="" @@ -1740,15 +1740,15 @@ AC_SUBST(FLAG_MIPS32) # does this compiler support -march=mips64r2 (mips64r2 default) ? -AC_MSG_CHECKING([if gcc accepts -march=mips64r2]) +AC_MSG_CHECKING([if gcc accepts -march=mips64r2 -mabi=64]) safe_CFLAGS=$CFLAGS -CFLAGS="$CFLAGS -march=mips64r2 -Werror" +CFLAGS="$CFLAGS -march=mips64r2 -mabi=64 -Werror" AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[ return 0; ]])], [ -FLAG_MIPS64="-march=mips64r2" +FLAG_MIPS64="-march=mips64r2 -mabi=64" AC_MSG_RESULT([yes]) ], [ FLAG_MIPS64="" |
|
From: Ivo R. <ir...@so...> - 2017-10-02 03:47:45
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=c7b4630f0610505915c64eff78de904dd9533304 commit c7b4630f0610505915c64eff78de904dd9533304 Author: Ivo Raisr <iv...@iv...> Date: Mon Oct 2 05:46:46 2017 +0200 Register allocator: Implement merging of Assigned/Spilled vregs. Diff: --- VEX/priv/host_generic_reg_alloc3.c | 158 +++++++++++++++++++++++++------------ 1 file changed, 109 insertions(+), 49 deletions(-) diff --git a/VEX/priv/host_generic_reg_alloc3.c b/VEX/priv/host_generic_reg_alloc3.c index 948ad2c..cfe807f 100644 --- a/VEX/priv/host_generic_reg_alloc3.c +++ b/VEX/priv/host_generic_reg_alloc3.c @@ -194,6 +194,7 @@ typedef #define IS_VALID_VREGNO(v) ((v) >= 0 && (v) < state->n_vregs) #define IS_VALID_RREGNO(r) ((r) >= 0 && (r) < state->n_rregs) +#define MK_VREG(idx, reg_class) mkHReg(True, (reg_class), 0, idx) #define FREE_VREG(v) \ do { \ @@ -644,6 +645,39 @@ static inline void reg_reg_move(RegAllocChunk* chunk, RegAllocState* state, FREE_RREG(&state->rregs[rs_idx]); } +/* Assigns a vreg to a free rreg. If |genReload| is True, generates reload + ("fill" in the proper terminology) as well. */ +static inline void assign_vreg(RegAllocChunk* chunk, RegAllocState* state, + HReg vreg, HReg rreg, Bool genReload, UInt depth, const RegAllocControl* con) +{ + UInt v_idx = hregIndex(vreg); + UInt r_idx = hregIndex(rreg); + + if (genReload) { + HInstr* reload1 = NULL; + HInstr* reload2 = NULL; + con->genReload(&reload1, &reload2, rreg, state->vregs[v_idx].spill_offset, + con->mode64); + vassert(reload1 != NULL || reload2 != NULL); + if (reload1 != NULL) { + emit_instr(chunk, reload1, depth, con, "reload1"); + } + if (reload2 != NULL) { + emit_instr(chunk, reload2, depth, con, "reload2"); + } + } + + vassert(state->rregs[r_idx].disp == Free); + state->rregs[r_idx].disp = Bound; + state->rregs[r_idx].vreg = vreg; + state->rregs[r_idx].eq_spill_slot = True; + + vassert(state->vregs[v_idx].disp == Unallocated + || state->vregs[v_idx].disp == Spilled); + state->vregs[v_idx].disp = Assigned; + state->vregs[v_idx].rreg = rreg; +} + /* --- Stage 1. --- Determine total ordering of instructions and structure of HInstrIfThenElse. @@ -1444,27 +1478,15 @@ static void stage4_chunk(RegAllocChunk* chunk, RegAllocState* state, /* Generate reload only if the vreg is spilled and is about to being read or modified. If it is merely written than reloading it first would be pointless. */ + Bool genReload; if ((state->vregs[v_idx].disp == Spilled) && (reg_usage->vMode[j] != HRmWrite)) { - - HInstr* reload1 = NULL; - HInstr* reload2 = NULL; - con->genReload(&reload1, &reload2, rreg, - state->vregs[v_idx].spill_offset, con->mode64); - vassert(reload1 != NULL || reload2 != NULL); - if (reload1 != NULL) { - emit_instr(chunk, reload1, depth, con, "reload1"); - } - if (reload2 != NULL) { - emit_instr(chunk, reload2, depth, con, "reload2"); - } + genReload = True; + } else { + genReload = False; } - state->rregs[r_idx].disp = Bound; - state->rregs[r_idx].vreg = vreg; - state->rregs[r_idx].eq_spill_slot = True; - state->vregs[v_idx].disp = Assigned; - state->vregs[v_idx].rreg = rreg; + assign_vreg(chunk, state, vreg, rreg, genReload, depth, con); addToHRegRemap(&remap, vreg, rreg); } @@ -1540,17 +1562,20 @@ static void stage4_emit_HInstrIfThenElse(RegAllocChunk* chunk, UInt depth, } /* Merges states of two vregs into the destination vreg: - |v1_idx| + |v2_idx| -> |vd_idx|. - Usually |v1_idx| == |v2_idx| == |vd_idx| so the merging happens between + |vreg1| + |vreg2| -> |vregD|. + Usually |vreg1| == |vreg2| == |vregD| so the merging happens between different states but for the same vreg. - For phi node merging, |v1_idx| != |v2_idx| != |vd_idx|. - Note: |v1_idx| and |vd_idx| are indexes to |state1|, |v2_idx| to |state2|. */ + For phi node merging, |vreg1| != |vreg2| != |vregD|. + Note: |vreg1| and |vregD| refer to |state1|, |vreg2| to |state2|. */ static void merge_vreg_states(RegAllocChunk* chunk, RegAllocState* state1, RegAllocState* state2, - UInt v1_idx, UInt v2_idx, UInt vd_idx, HReg vregD, + HReg vreg1, HReg vreg2, HReg vregD, UInt depth, const RegAllocControl* con) { RegAllocChunk* outOfLine = chunk->IfThenElse.outOfLine; + UInt v1_idx = hregIndex(vreg1); + UInt v2_idx = hregIndex(vreg2); + UInt vd_idx = hregIndex(vregD); VRegState* v1_src_state = &state1->vregs[v1_idx]; VRegState* v2_src_state = &state2->vregs[v2_idx]; VRegState* v1_dst_state = &state1->vregs[vd_idx]; @@ -1581,7 +1606,9 @@ static void merge_vreg_states(RegAllocChunk* chunk, } break; - case Assigned: + case Assigned: { + HReg rreg1 = v1_src_state->rreg; + switch (v2_src_state->disp) { case Unallocated: vpanic("Logic error during register allocator state merge " @@ -1589,26 +1616,23 @@ static void merge_vreg_states(RegAllocChunk* chunk, case Assigned: { /* Check if both vregs are assigned to the same rreg. */ - HReg rreg1 = v1_src_state->rreg; HReg rreg2 = v2_src_state->rreg; if (! sameHReg(rreg1, rreg2)) { switch (state2->rregs[hregIndex(rreg1)].disp) { case Free: { /* Move rreg2 to rreg1 in outOfLine/state2. */ reg_reg_move(outOfLine, state2, hregIndex(rreg2), - hregIndex(rreg1), state2->rregs[hregIndex(rreg2)].vreg, - depth, con); + hregIndex(rreg1), vreg2, depth, con); break; } case Bound: { /* Make room in state2->rregs[rreg1] first. */ UInt r_spilled_idx = spill_vreg(outOfLine, state2, - state2->rregs[hregIndex(rreg1)].vreg, - chunk->next->ii_total_start, depth, con); + state2->rregs[hregIndex(rreg1)].vreg, + chunk->next->ii_total_start, depth, con); vassert(r_spilled_idx == hregIndex(rreg1)); reg_reg_move(outOfLine, state2, hregIndex(rreg2), - hregIndex(rreg1), state2->rregs[hregIndex(rreg2)].vreg, - depth, con); + hregIndex(rreg1), vreg2, depth, con); break; } default: @@ -1616,6 +1640,42 @@ static void merge_vreg_states(RegAllocChunk* chunk, } } + /* Proceed to phi node merging bellow. */ + break; + } + + case Spilled: + switch (state2->rregs[hregIndex(rreg1)].disp) { + case Free: + assign_vreg(outOfLine, state2, vreg2, rreg1, True, depth, con); + break; + case Bound: { + /* Make a room in state2->rregs[rreg1] first. */ + HReg vreg_dead = state2->rregs[hregIndex(rreg1)].vreg; + UInt vdead_idx = hregIndex(vreg_dead); + /* That vreg should be dead by now. */ + vassert(state2->vregs[vdead_idx].dead_before + <= chunk->next->ii_total_start); + + FREE_VREG(&state2->vregs[vdead_idx]); + FREE_RREG(&state2->rregs[hregIndex(rreg1)]); + + assign_vreg(outOfLine, state2, vreg2, rreg1, True, depth, con); + break; + } + default: + vassert(0); + } + + /* Proceed to phi node merging bellow. */ + break; + + default: + vassert(0); + } + + /* Phi node merging. */ + if (! sameHReg(vreg1, vreg2)) { FREE_VREG(v1_src_state); FREE_VREG(v2_src_state); v1_dst_state->disp = Assigned; @@ -1625,21 +1685,12 @@ static void merge_vreg_states(RegAllocChunk* chunk, UInt r_idx = hregIndex(rreg1); vassert(state1->rregs[r_idx].disp == Bound); - state1->rregs[r_idx].eq_spill_slot = False; - if (v1_idx != vd_idx) { - vassert(!hregIsInvalid(vregD)); - state1->rregs[r_idx].vreg = vregD; - } - break; - } - case Spilled: - /* Generate reload. */ - vpanic("Reload not implemented, yet."); - break; - default: - vassert(0); + state1->rregs[r_idx].eq_spill_slot + = (state1->rregs[r_idx].eq_spill_slot && state2->rregs[r_idx].eq_spill_slot); + state1->rregs[r_idx].vreg = vregD; } break; + } // case Assigned case Spilled: switch (v2_src_state->disp) { @@ -1688,10 +1739,15 @@ static void stage4_merge_states(RegAllocChunk* chunk, for (UInt i = 0; i < chunk->IfThenElse.n_phis; i++) { const HPhiNode* phi_node = &chunk->IfThenElse.phi_nodes[i]; - merge_vreg_states(chunk, state, cloned, - hregIndex(phi_node->srcFallThrough), - hregIndex(phi_node->srcOutOfLine), - hregIndex(phi_node->dst), phi_node->dst, depth, con); + if (DEBUG_REGALLOC) { + print_depth(depth); + vex_printf("Now merging: "); + ppHPhiNode(phi_node); + vex_printf("\n"); + } + + merge_vreg_states(chunk, state, cloned, phi_node->srcFallThrough, + phi_node->srcOutOfLine, phi_node->dst, depth, con); } if (DEBUG_REGALLOC) { @@ -1711,8 +1767,12 @@ static void stage4_merge_states(RegAllocChunk* chunk, } for (UInt v_idx = 0; v_idx < state->n_vregs; v_idx++) { - merge_vreg_states(chunk, state, cloned, v_idx, v_idx, v_idx, INVALID_HREG, - depth, con); + HRegClass reg_class = state->vregs[v_idx].reg_class; + if (reg_class != HRcINVALID) { + merge_vreg_states(chunk, state, cloned, MK_VREG(v_idx, reg_class), + MK_VREG(v_idx, reg_class), MK_VREG(v_idx, reg_class), + depth, con); + } } if (DEBUG_REGALLOC) { |
|
From: Ivo R. <ir...@so...> - 2017-10-02 03:47:40
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=251cc5781b848c27de2c44062de804f33d5bb543 commit 251cc5781b848c27de2c44062de804f33d5bb543 Author: Ivo Raisr <iv...@iv...> Date: Mon Oct 2 03:45:56 2017 +0200 Register allocator: Implement merging of Assigned/Assigned bound rreg. Diff: --- VEX/priv/host_generic_reg_alloc3.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/VEX/priv/host_generic_reg_alloc3.c b/VEX/priv/host_generic_reg_alloc3.c index 69996c2..948ad2c 100644 --- a/VEX/priv/host_generic_reg_alloc3.c +++ b/VEX/priv/host_generic_reg_alloc3.c @@ -483,12 +483,11 @@ static inline void mark_vreg_spilled(UInt v_idx, RegAllocState* state) /* Spills a vreg assigned to some rreg. The vreg is spilled and the rreg is freed. Returns rreg's index. */ -static inline UInt spill_vreg( - RegAllocChunk* chunk, RegAllocState* state, - HReg vreg, UInt v_idx, Short ii_total_current, - UInt depth, const RegAllocControl* con) +static inline UInt spill_vreg(RegAllocChunk* chunk, RegAllocState* state, + HReg vreg, Short ii_total_current, UInt depth, const RegAllocControl* con) { /* Check some invariants first. */ + UInt v_idx = hregIndex(vreg); vassert(IS_VALID_VREGNO((v_idx))); vassert(state->vregs[v_idx].disp == Assigned); HReg rreg = state->vregs[v_idx].rreg; @@ -1099,8 +1098,7 @@ static void stage4_chunk(RegAllocChunk* chunk, RegAllocState* state, HReg vreg_to_spill = find_vreg_to_spill(chunk, state, \ &chunk->reg_usage[ii_chunk], (_reg_class), \ ii_chunk, con); \ - _r_free_idx = spill_vreg(chunk, state, \ - vreg_to_spill, hregIndex(vreg_to_spill), \ + _r_free_idx = spill_vreg(chunk, state, vreg_to_spill, \ INSTRNO_TOTAL, depth, con); \ } \ \ @@ -1301,8 +1299,8 @@ static void stage4_chunk(RegAllocChunk* chunk, RegAllocState* state, mark_vreg_spilled(v_idx, state); } else { /* Spill the vreg. It is not used by this instruction.*/ - spill_vreg(chunk, state, vreg, v_idx, INSTRNO_TOTAL, - depth, con); + spill_vreg(chunk, state, vreg, INSTRNO_TOTAL, depth, + con); } } else { /* Find or make a free rreg where to move this vreg to. */ @@ -1598,12 +1596,21 @@ static void merge_vreg_states(RegAllocChunk* chunk, case Free: { /* Move rreg2 to rreg1 in outOfLine/state2. */ reg_reg_move(outOfLine, state2, hregIndex(rreg2), - hregIndex(rreg1), vregD, depth, con); + hregIndex(rreg1), state2->rregs[hregIndex(rreg2)].vreg, + depth, con); break; } - case Bound: - vpanic("Assigned/Assigned move to a bound rreg not implemented"); + case Bound: { + /* Make room in state2->rregs[rreg1] first. */ + UInt r_spilled_idx = spill_vreg(outOfLine, state2, + state2->rregs[hregIndex(rreg1)].vreg, + chunk->next->ii_total_start, depth, con); + vassert(r_spilled_idx == hregIndex(rreg1)); + reg_reg_move(outOfLine, state2, hregIndex(rreg2), + hregIndex(rreg1), state2->rregs[hregIndex(rreg2)].vreg, + depth, con); break; + } default: vassert(0); } |
|
From: Ivo R. <ir...@so...> - 2017-10-02 03:47:35
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=0e32a73cbd2e9a11c7ab75cca63a9096dfc858a8 commit 0e32a73cbd2e9a11c7ab75cca63a9096dfc858a8 Author: Ivo Raisr <iv...@iv...> Date: Mon Oct 2 03:35:03 2017 +0200 Register allocator: Fix merging of Assigned/Assigned vregs. Diff: --- VEX/priv/host_generic_reg_alloc3.c | 101 +++++++++++++++++++++++++++---------- 1 file changed, 74 insertions(+), 27 deletions(-) diff --git a/VEX/priv/host_generic_reg_alloc3.c b/VEX/priv/host_generic_reg_alloc3.c index 81cf5c5..69996c2 100644 --- a/VEX/priv/host_generic_reg_alloc3.c +++ b/VEX/priv/host_generic_reg_alloc3.c @@ -32,6 +32,18 @@ #include "main_util.h" #include "host_generic_regs.h" +/* TODO-JIT: There is still a room for lot of improvements around phi node + merging. For example: + - When processing out-of-line leg, we may want to reserve rregs which + are assigned to phi node destinations, as to avoid spilling and reg-reg + move during the merge. + - Although RRegLR's are local to every instruction chunk, the register + allocator should have more visibility to what lies ahead after the merge. + Avoids the situation when registers are allocated somehow + in the fall-through leg and need to be spilled just few instructions + after the merge (because of a helper call, for example). +*/ + /* Set to 1 for lots of debugging output. */ #define DEBUG_REGALLOC 0 @@ -613,6 +625,26 @@ static inline Bool find_free_rreg( return found; } +/* Generates a rreg-rreg move for a given |vreg| from |rs_idx| -> |rd_idx|. + Updates the register allocator state. */ +static inline void reg_reg_move(RegAllocChunk* chunk, RegAllocState* state, + UInt rs_idx, UInt rd_idx, HReg vreg, UInt depth, const RegAllocControl* con) +{ + HInstr* move = con->genMove(con->univ->regs[rs_idx], + con->univ->regs[rd_idx], con->mode64); + vassert(move != NULL); + emit_instr(chunk, move, depth, con, "move"); + + /* Update the register allocator state. */ + UInt v_idx = hregIndex(vreg); + state->vregs[v_idx].disp = Assigned; + state->vregs[v_idx].rreg = con->univ->regs[rd_idx]; + state->rregs[rd_idx].disp = Bound; + state->rregs[rd_idx].vreg = vreg; + state->rregs[rd_idx].eq_spill_slot = state->rregs[rs_idx].eq_spill_slot; + FREE_RREG(&state->rregs[rs_idx]); +} + /* --- Stage 1. --- Determine total ordering of instructions and structure of HInstrIfThenElse. @@ -1278,18 +1310,9 @@ static void stage4_chunk(RegAllocChunk* chunk, RegAllocState* state, v_idx, state->vregs[v_idx].reg_class, True); /* Generate "move" between real registers. */ - HInstr* move = con->genMove(con->univ->regs[r_idx], - con->univ->regs[r_free_idx], con->mode64); - vassert(move != NULL); - emit_instr(chunk, move, depth, con, "move"); - - /* Update the register allocator state. */ vassert(state->vregs[v_idx].disp == Assigned); - state->vregs[v_idx].rreg = con->univ->regs[r_free_idx]; - state->rregs[r_free_idx].disp = Bound; - state->rregs[r_free_idx].vreg = vreg; - state->rregs[r_free_idx].eq_spill_slot = rreg->eq_spill_slot; - FREE_RREG(rreg); + reg_reg_move(chunk, state, r_idx, r_free_idx, vreg, + depth, con); } break; } @@ -1571,11 +1594,19 @@ static void merge_vreg_states(RegAllocChunk* chunk, HReg rreg1 = v1_src_state->rreg; HReg rreg2 = v2_src_state->rreg; if (! sameHReg(rreg1, rreg2)) { - /* Generate "move" from rreg2 to rreg1. */ - HInstr* move = con->genMove(con->univ->regs[hregIndex(rreg2)], - con->univ->regs[hregIndex(rreg1)], con->mode64); - vassert(move != NULL); - emit_instr(outOfLine, move, depth + 1, con, "move"); + switch (state2->rregs[hregIndex(rreg1)].disp) { + case Free: { + /* Move rreg2 to rreg1 in outOfLine/state2. */ + reg_reg_move(outOfLine, state2, hregIndex(rreg2), + hregIndex(rreg1), vregD, depth, con); + break; + } + case Bound: + vpanic("Assigned/Assigned move to a bound rreg not implemented"); + break; + default: + vassert(0); + } } FREE_VREG(v1_src_state); @@ -1638,6 +1669,33 @@ static void stage4_merge_states(RegAllocChunk* chunk, RegAllocState* state, RegAllocState* cloned, UInt depth, const RegAllocControl* con) { + /* Process phi nodes first. */ + if (chunk->IfThenElse.n_phis > 0) { + if (DEBUG_REGALLOC) { + print_state(chunk, state, chunk->next->ii_total_start, depth, con, + "Before phi node merge: fall-through leg"); + print_state(chunk, cloned, chunk->next->ii_total_start, depth, con, + "Before phi node merge: out-of-line leg"); + } + + for (UInt i = 0; i < chunk->IfThenElse.n_phis; i++) { + const HPhiNode* phi_node = &chunk->IfThenElse.phi_nodes[i]; + + merge_vreg_states(chunk, state, cloned, + hregIndex(phi_node->srcFallThrough), + hregIndex(phi_node->srcOutOfLine), + hregIndex(phi_node->dst), phi_node->dst, depth, con); + } + + if (DEBUG_REGALLOC) { + print_state(chunk, state, chunk->next->ii_total_start, depth, con, + "After phi node merge"); + } + } + + /* Merge remaining vreg states. VRegs mentioned by phi nodes are processed + as well but merging is no-op for them now. */ + if (DEBUG_REGALLOC) { print_state(chunk, state, chunk->next->ii_total_start, depth, con, "Before state merge: fall-through leg"); @@ -1645,17 +1703,6 @@ static void stage4_merge_states(RegAllocChunk* chunk, "Before state merge: out-of-line leg"); } - /* Process phi nodes first. */ - for (UInt i = 0; i < chunk->IfThenElse.n_phis; i++) { - const HPhiNode* phi_node = &chunk->IfThenElse.phi_nodes[i]; - - merge_vreg_states(chunk, state, cloned, - hregIndex(phi_node->srcFallThrough), hregIndex(phi_node->srcOutOfLine), - hregIndex(phi_node->dst), phi_node->dst, depth, con); - } - - /* Merge remaining vreg states. VRegs mentioned by phi nodes are processed - as well but merging is no-op for them now. */ for (UInt v_idx = 0; v_idx < state->n_vregs; v_idx++) { merge_vreg_states(chunk, state, cloned, v_idx, v_idx, v_idx, INVALID_HREG, depth, con); |
|
From: Rhys K. <rhy...@so...> - 2017-10-02 01:10:06
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=7221d28cad21d44ebd73750b64229e9457034659 commit 7221d28cad21d44ebd73750b64229e9457034659 Author: Rhys Kidd <rhy...@gm...> Date: Sun Oct 1 20:57:04 2017 -0400 gitignore: Fix up false directory-level .gitignore settings So we never intended to ignore all changes from the top-level down in /include or /cachegrind. Instead allow the filetype-specific .gitignore patterns match to the contents of these two folders. Also, don't ignore changes to include/valgrind.h as it exists in the repository and should be tracked for any changes developers might make. Changes tested by running a git clean force and then full rebuild. No stray build artifacts were being tracked erroneously by git after these changes. Diff: --- .gitignore | 3 --- 1 file changed, 3 deletions(-) diff --git a/.gitignore b/.gitignore index ba06188..ec61217 100644 --- a/.gitignore +++ b/.gitignore @@ -7,7 +7,6 @@ /autom4te-*.cache /autom4te.cache /bin -/cachegrind /cachegrind.out.* /compile /config.guess @@ -19,7 +18,6 @@ /default.supp /depcomp /glibc-2.X.supp -/include /install-sh /lib /Makefile @@ -694,7 +692,6 @@ /include/Makefile.in /include/Makefile /include/tool.h -/include/valgrind.h /include/vgversion.h # /include/vki/ |
|
From: Rhys K. <rhy...@so...> - 2017-10-02 00:05:23
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=1ce04c35c2ebbc8ea3c2b38ba69daa9dd40cde35 commit 1ce04c35c2ebbc8ea3c2b38ba69daa9dd40cde35 Author: Rhys Kidd <rhy...@gm...> Date: Sun Sep 10 11:34:32 2017 -0400 Preliminary support for Darwin 17.x (macOS 10.13) Diff: --- NEWS | 4 +- README | 6 +- configure.ac | 9 +- coregrind/fixup_macho_loadcmds.c | 3 +- coregrind/m_syswrap/priv_syswrap-darwin.h | 22 +- coregrind/m_syswrap/syswrap-amd64-darwin.c | 3 +- coregrind/m_syswrap/syswrap-darwin.c | 26 +- coregrind/m_syswrap/syswrap-x86-darwin.c | 3 +- darwin17.supp | 768 +++++++++++++++++++++++++++++ include/vki/vki-scnums-darwin.h | 28 ++ 10 files changed, 858 insertions(+), 14 deletions(-) diff --git a/NEWS b/NEWS index 4d6d840..2dfcf32 100644 --- a/NEWS +++ b/NEWS @@ -8,13 +8,15 @@ bug fixes. This release supports X86/Linux, AMD64/Linux, ARM32/Linux, ARM64/Linux, PPC32/Linux, PPC64BE/Linux, PPC64LE/Linux, S390X/Linux, MIPS32/Linux, MIPS64/Linux, ARM/Android, ARM64/Android, MIPS32/Android, X86/Android, -X86/Solaris, AMD64/Solaris and AMD64/MacOSX 10.12. +X86/Solaris, AMD64/Solaris and AMD64/MacOSX 10.12. There is also preliminary +support for X86/macOS 10.13, AMD64/macOS 10.13. * ==================== CORE CHANGES =================== * ================== PLATFORM CHANGES ================= +* Preliminary support for macOS 10.13 has been added. * ==================== TOOL CHANGES ==================== diff --git a/README b/README index 6959707..6f333d3 100644 --- a/README +++ b/README @@ -37,8 +37,8 @@ platforms: - PPC32/Linux - PPC64/Linux - ARM/Linux -- x86/MacOSX -- AMD64/MacOSX +- x86/macOS +- AMD64/macOS - S390X/Linux - MIPS32/Linux - MIPS64/Linux @@ -46,7 +46,7 @@ platforms: - AMD64/Solaris Note that AMD64 is just another name for x86_64, and Valgrind runs fine -on Intel processors. Also note that the core of MacOSX is called +on Intel processors. Also note that the core of macOS is called "Darwin" and this name is used sometimes. Valgrind is licensed under the GNU General Public License, version 2. diff --git a/configure.ac b/configure.ac index fde97ae..483d9bd 100644 --- a/configure.ac +++ b/configure.ac @@ -349,6 +349,7 @@ case "${host_os}" in AC_DEFINE([DARWIN_10_10], 101000, [DARWIN_VERS value for Mac OS X 10.10]) AC_DEFINE([DARWIN_10_11], 101100, [DARWIN_VERS value for Mac OS X 10.11]) AC_DEFINE([DARWIN_10_12], 101200, [DARWIN_VERS value for macOS 10.12]) + AC_DEFINE([DARWIN_10_13], 101300, [DARWIN_VERS value for macOS 10.13]) AC_MSG_CHECKING([for the kernel version]) kernel=`uname -r` @@ -418,9 +419,15 @@ case "${host_os}" in DEFAULT_SUPP="darwin16.supp ${DEFAULT_SUPP}" DEFAULT_SUPP="darwin10-drd.supp ${DEFAULT_SUPP}" ;; + 17.*) + AC_MSG_RESULT([Darwin 17.x (${kernel}) / macOS 10.13 High Sierra]) + AC_DEFINE([DARWIN_VERS], DARWIN_10_13, [Darwin / Mac OS X version]) + DEFAULT_SUPP="darwin17.supp ${DEFAULT_SUPP}" + DEFAULT_SUPP="darwin10-drd.supp ${DEFAULT_SUPP}" + ;; *) AC_MSG_RESULT([unsupported (${kernel})]) - AC_MSG_ERROR([Valgrind works on Darwin 10.x, 11.x, 12.x, 13.x, 14.x, 15.x and 16.x (Mac OS X 10.6/7/8/9/10/11 and macOS 10.12)]) + AC_MSG_ERROR([Valgrind works on Darwin 10.x, 11.x, 12.x, 13.x, 14.x, 15.x, 16.x and 17.x (Mac OS X 10.6/7/8/9/10/11 and macOS 10.12/13)]) ;; esac ;; diff --git a/coregrind/fixup_macho_loadcmds.c b/coregrind/fixup_macho_loadcmds.c index 516b7ba..cdb3622 100644 --- a/coregrind/fixup_macho_loadcmds.c +++ b/coregrind/fixup_macho_loadcmds.c @@ -122,7 +122,8 @@ #if DARWIN_VERS != DARWIN_10_5 && DARWIN_VERS != DARWIN_10_6 \ && DARWIN_VERS != DARWIN_10_7 && DARWIN_VERS != DARWIN_10_8 \ && DARWIN_VERS != DARWIN_10_9 && DARWIN_VERS != DARWIN_10_10 \ - && DARWIN_VERS != DARWIN_10_11 && DARWIN_VERS != DARWIN_10_12 + && DARWIN_VERS != DARWIN_10_11 && DARWIN_VERS != DARWIN_10_12 \ + && DARWIN_VERS != DARWIN_10_13 # error "Unknown DARWIN_VERS value. This file only compiles on Darwin." #endif diff --git a/coregrind/m_syswrap/priv_syswrap-darwin.h b/coregrind/m_syswrap/priv_syswrap-darwin.h index bdefd61..29e491d 100644 --- a/coregrind/m_syswrap/priv_syswrap-darwin.h +++ b/coregrind/m_syswrap/priv_syswrap-darwin.h @@ -248,7 +248,9 @@ DECL_TEMPLATE(darwin, seteuid); // 183 DECL_TEMPLATE(darwin, sigreturn); // 184 DECL_TEMPLATE(darwin, FAKE_SIGRETURN); // NYI chud 185 -// 186 +#if DARWIN_VERS >= DARWIN_10_13 +// NYI thread_selfcounts // 186 +#endif /* DARWIN_VERS >= DARWIN_10_13 */ // 187 // GEN stat 188 // GEN fstat 189 @@ -470,7 +472,9 @@ DECL_TEMPLATE(darwin, __thread_selfid); // 372 #if DARWIN_VERS >= DARWIN_10_11 // NYI kevent_qos // 374 #endif /* DARWIN_VERS >= DARWIN_10_11 */ -// 375 +#if DARWIN_VERS >= DARWIN_10_13 +// NYI kevent_id // 375 +#endif /* DARWIN_VERS >= DARWIN_10_13 */ // 376 // 377 // 378 @@ -634,6 +638,16 @@ DECL_TEMPLATE(darwin, ulock_wake); // 516 // NYI terminate_with_payload // 520 // NYI abort_with_payload // 521 #endif /* DARWIN_VERS >= DARWIN_10_12 */ +#if DARWIN_VERS >= DARWIN_10_13 +// NYI necp_session_open // 522 +// NYI necp_session_action // 523 +// NYI setattrlistat // 524 +// NYI net_qos_guideline // 525 +// NYI fmount // 526 +// NYI ntp_adjtime // 527 +// NYI ntp_gettime // 528 +// NYI os_fault_with_payload // 529 +#endif /* DARWIN_VERS >= DARWIN_10_13 */ // Mach message helpers DECL_TEMPLATE(darwin, mach_port_set_context); @@ -750,6 +764,10 @@ DECL_TEMPLATE(darwin, semaphore_timedwait_signal); DECL_TEMPLATE(darwin, task_for_pid); DECL_TEMPLATE(darwin, pid_for_task); +#if DARWIN_VERS >= DARWIN_10_13 +// NYI thread_get_special_reply_port // 50 +#endif /* DARWIN_VERS >= DARWIN_10_13 */ + #if DARWIN_VERS >= DARWIN_10_12 DECL_TEMPLATE(darwin, host_create_mach_voucher_trap); DECL_TEMPLATE(darwin, task_register_dyld_image_infos); diff --git a/coregrind/m_syswrap/syswrap-amd64-darwin.c b/coregrind/m_syswrap/syswrap-amd64-darwin.c index c827bab..f509329 100644 --- a/coregrind/m_syswrap/syswrap-amd64-darwin.c +++ b/coregrind/m_syswrap/syswrap-amd64-darwin.c @@ -482,7 +482,8 @@ void wqthread_hijack(Addr self, Addr kport, Addr stackaddr, Addr workitem, # elif DARWIN_VERS == DARWIN_10_9 \ || DARWIN_VERS == DARWIN_10_10 \ || DARWIN_VERS == DARWIN_10_11 \ - || DARWIN_VERS == DARWIN_10_12 + || DARWIN_VERS == DARWIN_10_12 \ + || DARWIN_VERS == DARWIN_10_13 UWord magic_delta = 0xE0; # else # error "magic_delta: to be computed on new OS version" diff --git a/coregrind/m_syswrap/syswrap-darwin.c b/coregrind/m_syswrap/syswrap-darwin.c index e8097e3..fe732b2 100644 --- a/coregrind/m_syswrap/syswrap-darwin.c +++ b/coregrind/m_syswrap/syswrap-darwin.c @@ -10575,6 +10575,18 @@ const SyscallTableEntry ML_(syscall_table)[] = { // _____(__NR_terminate_with_payload), // 520 // _____(__NR_abort_with_payload), // 521 #endif +#if DARWIN_VERS >= DARWIN_10_13 +// _____(__NR_thread_selfcounts), // 186 +// _____(__NR_kevent_id, // 375 +// _____(__NR_necp_session_open), // 522 +// _____(__NR_necp_session_action), // 523 +// _____(__NR_setattrlistat), // 524 +// _____(__NR_net_qos_guideline), // 525 +// _____(__NR_fmount), // 526 +// _____(__NR_ntp_adjtime), // 527 +// _____(__NR_ntp_gettime), // 528 +// _____(__NR_os_fault_with_payload), // 529 +#endif // _____(__NR_MAXSYSCALL) MACX_(__NR_DARWIN_FAKE_SIGRETURN, FAKE_SIGRETURN) }; @@ -10698,17 +10710,23 @@ const SyscallTableEntry ML_(mach_trap_table)[] = { #if defined(VGA_x86) // _____(__NR_macx_swapon), // _____(__NR_macx_swapoff), +#else + _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(48)), + _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(49)), +#endif +#if DARWIN_VERS >= DARWIN_10_13 +// _____(__NR_thread_get_special_reply_port, // 50 +#else _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(50)), +#endif /* DARWIN_VERS >= DARWIN_10_13 */ +#if defined(VGA_x86) // _____(__NR_macx_triggers), // _____(__NR_macx_backing_store_suspend), // _____(__NR_macx_backing_store_recovery), #else - _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(48)), - _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(49)), - _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(50)), _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(51)), _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(52)), - _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(53)), + _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(53)), #endif _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(54)), _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(55)), diff --git a/coregrind/m_syswrap/syswrap-x86-darwin.c b/coregrind/m_syswrap/syswrap-x86-darwin.c index dac5c7d..a5d9e97 100644 --- a/coregrind/m_syswrap/syswrap-x86-darwin.c +++ b/coregrind/m_syswrap/syswrap-x86-darwin.c @@ -430,7 +430,8 @@ void wqthread_hijack(Addr self, Addr kport, Addr stackaddr, Addr workitem, # elif DARWIN_VERS == DARWIN_10_9 \ || DARWIN_VERS == DARWIN_10_10 \ || DARWIN_VERS == DARWIN_10_11 \ - || DARWIN_VERS == DARWIN_10_12 + || DARWIN_VERS == DARWIN_10_12 \ + || DARWIN_VERS == DARWIN_10_13 UWord magic_delta = 0xB0; # else # error "magic_delta: to be computed on new OS version" diff --git a/darwin17.supp b/darwin17.supp new file mode 100644 index 0000000..78f3347 --- /dev/null +++ b/darwin17.supp @@ -0,0 +1,768 @@ + +# Suppressions for Darwin 17.x / macOS 10.13 High Sierra + +############################################ +## Leaks. For other stuff see below. + +{ + OSX1013:1-Leak + Memcheck:Leak + match-leak-kinds: possible + fun:malloc_zone_?alloc + ... + fun:_read_images +} + +{ + OSX1013:2-Leak + Memcheck:Leak + match-leak-kinds: definite + fun:malloc_zone_?alloc + ... + fun:_read_images +} + +{ + OSX1013:3-Leak + Memcheck:Leak + match-leak-kinds: definite + fun:malloc_zone_?alloc + fun:recursive_mutex_init + ... + fun:_os_object_init + fun:libdispatch_init + fun:libSystem_initializer + ... +} + +{ + OSX1013:4-Leak + Memcheck:Leak + fun:malloc_zone_?alloc + ... + fun:dyld_register_image_state_change_handler + ... +} + +{ + OSX1013:5-Leak + Memcheck:Leak + match-leak-kinds: reachable + fun:?alloc + ... + fun:dyld_register_image_state_change_handler + ... +} + +{ + OSX1013:6-Leak + Memcheck:Leak + match-leak-kinds: reachable + fun:malloc_zone_?alloc + ... + fun:map_images_nolock + fun:map_2_images + ... +} + +{ + OSX1013:7-Leak + Memcheck:Leak + match-leak-kinds: possible + fun:malloc_zone_?alloc + ... + fun:map_images_nolock + fun:map_2_images + ... +} + +{ + OSX1013:8-Leak + Memcheck:Leak + match-leak-kinds: definite + fun:?alloc + ... + fun:libSystem_initializer + ... +} + +{ + OSX1013:9-Leak + Memcheck:Leak + match-leak-kinds: reachable + fun:malloc_zone_?alloc + ... + fun:libSystem_initializer + ... +} + +{ + OSX1013:10-Leak + Memcheck:Leak + match-leak-kinds: reachable + fun:?alloc + ... + fun:libSystem_initializer + ... +} + +#{ +# OSX1013:11-Leak +# Memcheck:Leak +# match-leak-kinds: definite +# fun:malloc +# fun:currentlocale +#} +# +#{ +# OSX1013:12-Leak +# Memcheck:Leak +# match-leak-kinds: possible +# fun:malloc +# fun:tzsetwall_basic +# fun:_st_tzset_basic +#} + +{ + OSX1013:13-Leak + Memcheck:Leak + match-leak-kinds: reachable + fun:malloc_zone_memalign + ... + fun:_ZN4dyld24initializeMainExecutableEv + ... +} + +{ + OSX1013:14-Leak + Memcheck:Leak + match-leak-kinds: reachable + fun:?alloc + ... + fun:libSystem_atfork_child + ... +} + +{ + OSX1013:15-Leak + Memcheck:Leak + match-leak-kinds: reachable + fun:malloc + fun:__smakebuf + ... + fun:printf + ... +} + +{ + OSX1013:16-Leak + Memcheck:Leak + match-leak-kinds: possible + fun:?alloc + ... + fun:_read_images +} + +{ + OSX1013:17-Leak + Memcheck:Leak + match-leak-kinds: reachable + fun:?alloc + ... + fun:_read_images +} + +{ + OSX1013:18-Leak + Memcheck:Leak + match-leak-kinds: reachable + fun:malloc_zone_?alloc + ... + fun:_read_images +} + +{ + OSX1013:19-Leak + Memcheck:Leak + match-leak-kinds: possible + fun:malloc_zone_?alloc + ... + fun:*NX*Map* + fun:*NX*Map* +} + +{ + OSX1013:20-Leak + Memcheck:Leak + match-leak-kinds: indirect + fun:?alloc + ... + fun:libSystem_initializer + ... +} + +{ + OSX1013:21-Leak + Memcheck:Leak + match-leak-kinds: definite + fun:malloc_zone_memalign + ... + fun:_ZN4dyld24initializeMainExecutableEv + ... +} + + +############################################ +## Non-leak errors + +##{ +## OSX1013:CoreFoundation-1 +## Memcheck:Cond +## obj:*CoreFoundation.framework*CoreFoundation* +## obj:*CoreFoundation.framework*CoreFoundation* +## obj:*CoreFoundation.framework*CoreFoundation* +##} + +{ + OSX1013:CoreFoundation-2 + Memcheck:Cond + obj:*CoreFoundation.framework*CoreFoundation* + obj:*libdispatch.dylib* + obj:*libdispatch.dylib* +} + +{ + OSX1013:CoreFoundation-3 + Memcheck:Cond + obj:*CoreFoundation.framework*CoreFoundation* + obj:*CoreFoundation.framework*CoreFoundation* + obj:*Foundation.framework*Foundation* +} + +{ + OSX1013:CoreFoundation-4 + Memcheck:Cond + obj:*CoreFoundation.framework*CoreFoundation* + obj:*CoreFoundation.framework*CoreFoundation* + obj:*SystemConfiguration.framework*SystemConfiguration* +} + +{ + OSX1013:CoreFoundation-5 + Memcheck:Cond + obj:*CoreFoundation.framework*CoreFoundation* + obj:*CoreFoundation.framework*CoreFoundation* + obj:*HIServices.framework*HIServices* +} + +{ + OSX1013:CoreFoundation-6 + Memcheck:Cond + obj:*CoreFoundation.framework*CoreFoundation* + obj:*SystemConfiguration.framework*SystemConfiguration* + obj:*SystemConfiguration.framework*SystemConfiguration* +} + +{ + OSX1013:CoreFoundation-7 + Memcheck:Cond + obj:*CoreFoundation.framework*CoreFoundation* + obj:*SystemConfiguration.framework*SystemConfiguration* + obj:*CoreFoundation.framework*CoreFoundation* +} + +{ + OSX1013:CoreFoundation-8 + Memcheck:Cond + obj:*CoreFoundation.framework*CoreFoundation* + obj:*IOKit.framework*IOKit* +} + +{ + OSX1013:CoreFoundation-9 + Memcheck:Cond + obj:*CoreFoundation.framework*CoreFoundation* + obj:*Foundation.framework*Foundation* + obj:*AppKit.framework*AppKit* +} + +{ + OSX1013:CoreFoundation-10 + Memcheck:Cond + obj:*CoreFoundation.framework*CoreFoundation* + obj:*HIToolbox.framework*HIToolbox* + obj:*HIToolbox.framework*HIToolbox* +} + +{ + OSX1013:CoreFoundation-11 + Memcheck:Cond + obj:*CoreFoundation.framework*CoreFoundation* + obj:*AE.framework*AE* + obj:*AE.framework*AE* +} + +{ + OSX1013:CoreFoundation-12 + Memcheck:Cond + obj:*CoreFoundation.framework*CoreFoundation* + obj:*CoreFoundation.framework*CoreFoundation* + obj:*HIToolbox.framework*HIToolbox* +} + +{ + OSX1013:CoreFoundation-13 + Memcheck:Cond + obj:*CoreFoundation.framework*CoreFoundation* + obj:*CoreFoundation.framework*CoreFoundation* + obj:*AE.framework*AE* +} + +{ + OSX1013:AppKit-1 + Memcheck:Cond + obj:*AppKit.framework*AppKit* + obj:*AppKit.framework*AppKit* + obj:*AppKit.framework*AppKit* +} + +{ + OSX1013:AppKit-2 + Memcheck:Cond + obj:*AppKit.framework*AppKit* + obj:*AppKit.framework*AppKit* + obj:*libdispatch.dylib* +} + +#{ +# OSX1013:AppKit-3 +# Memcheck:Cond +# obj:*AppKit.framework*AppKit* +# obj:*libdispatch.dylib* +# obj:*libdispatch.dylib* +#} + +##{ +## OSX1013:AppKit-4 +## Memcheck:Cond +## obj:*AppKit.framework*AppKit* +## obj:*AppKit.framework*AppKit* +## obj:*CoreFoundation.framework*CoreFoundation* +##} + +{ + OSX1013:AppKit-5 + Memcheck:Cond + obj:*AppKit.framework*AppKit* + obj:*AppKit.framework*AppKit* + obj:*Foundation.framework*Foundation* +} + +{ + OSX1013:AppKit-6 + Memcheck:Cond + obj:*AppKit.framework*AppKit* + obj:*Foundation.framework*Foundation* + obj:*AppKit.framework*AppKit* +} + +{ + OSX1013:AppKit-7 + Memcheck:Cond + obj:*AppKit.framework*AppKit* + obj:*libdispatch.dylib* + obj:*libdispatch.dylib* +} + +{ + OSX1013:AppKit-8 + Memcheck:Cond + obj:*AppKit.framework*AppKit* + obj:*Foundation.framework*Foundation* + obj:*Foundation.framework*Foundation* +} + +{ + OSX1013:ColorSync-1 + Memcheck:Cond + obj:*ColorSync.framework*ColorSync* + obj:*ColorSync.framework*ColorSync* + obj:*ColorSync.framework*ColorSync* +} + +#{ +# OSX1013:ColorSync-2 +# Memcheck:Value8 +# obj:*ColorSync.framework*ColorSync* +# obj:*ColorSync.framework*ColorSync* +# obj:*ColorSync.framework*ColorSync* +#} + +{ + OSX1013:CoreGraphics-1 + Memcheck:Cond + obj:*CoreGraphics.framework*CoreGraphics* + obj:*CoreGraphics.framework*CoreGraphics* +} + +#{ +# OSX1013:CoreGraphics-2 +# Memcheck:Value8 +# obj:*CoreGraphics.framework*CoreGraphics* +# obj:*CoreGraphics.framework*CoreGraphics* +# obj:*CoreGraphics.framework*CoreGraphics* +#} + +{ + OSX1013:CoreGraphics-3 + Memcheck:Cond + obj:*CoreGraphics.framework*CoreGraphics* + obj:*CoreGraphics.framework*libRIP* + obj:*CoreGraphics.framework*libRIP* +} + +#{ +# OSX1013:CoreGraphics-4 +# Memcheck:Cond +# obj:*CoreGraphics.framework*CoreGraphics* +# obj:*CoreGraphics.framework*CoreGraphics* +# obj:*CoreGraphics.framework*libRIP* +#} + +{ + OSX1013:CoreGraphics-5 + Memcheck:Cond + obj:*CoreGraphics.framework*CoreGraphics* + obj:*libdispatch.dylib* + obj:*libdispatch.dylib* +} + +#{ +# OSX1013:CoreGraphics-6 +# Memcheck:Cond +# obj:*CoreGraphics.framework*CoreGraphics* +# obj:*CoreGraphics.framework*CoreGraphics* +# obj:*HIToolbox.framework*HIToolbox* +#} + +{ + OSX1013:HIServices-1 + Memcheck:Cond + obj:*HIServices.framework*HIServices* + obj:*HIToolbox.framework*HIToolbox* + obj:*HIToolbox.framework*HIToolbox* +} + +{ + OSX1013:LaunchServices-1 + Memcheck:Cond + obj:*LaunchServices.framework*LaunchServices* + obj:*AppKit.framework*AppKit* + obj:*AppKit.framework*AppKit* +} + +{ + OSX1013:LaunchServices-2 + Memcheck:Cond + obj:*LaunchServices.framework*LaunchServices* + obj:*libdispatch.dylib* + obj:*libdispatch.dylib* +} + +{ + OSX1013:QuartzCore-1 + Memcheck:Cond + obj:*QuartzCore.framework*QuartzCore + obj:*QuartzCore.framework*QuartzCore + obj:*QuartzCore.framework*QuartzCore +} + +#{ +# OSX1013:vImage-1 +# Memcheck:Cond +# obj:*vImage.framework*vImage* +# obj:*vImage.framework*vImage* +# obj:*CoreGraphics.framework*CoreGraphics* +#} + +{ + OSX1013:zlib-C + Memcheck:Cond + obj:/usr/lib/libz.*dylib + obj:/usr/lib/libz.*dylib +} + +{ + OSX1013:zlib-8 + Memcheck:Value8 + obj:/usr/lib/libz.*dylib + obj:/usr/lib/libz.*dylib +} + +{ + OSX1013:32bit:_libxpc_initializer + Memcheck:Cond + obj:/usr/lib/system/libsystem_c.dylib + obj:/usr/lib/system/libsystem_c.dylib + fun:_libxpc_initializer + obj:/usr/lib/libSystem.B.dylib + fun:*ImageLoaderMachO*doModInitFunctions* +} + +{ + OSX1013:dyld-1 + Memcheck:Cond + fun:*ImageLoader*weakBind* + fun:*ImageLoader*link* + fun:*dyld*link* +} + +{ + OSX1013:dyld-2 + Memcheck:Cond + fun:exit + obj:*libdyld*dylib* +} + +{ + OSX1013:dyld-3 + Memcheck:Cond + fun:bcmp + fun:_ZN16ImageLoaderMachO18validateFirstPagesEPK21linkedit_data_commandiPKhmxRKN11ImageLoader11LinkContextE + ... +} + +{ + OSX1013:dyld-4 + Memcheck:Value8 + fun:bcmp + fun:_ZN16ImageLoaderMachO18validateFirstPagesEPK21linkedit_data_commandiPKhmxRKN11ImageLoader11LinkContextE + ... +} + +{ + OSX1013:dyld-5 + Memcheck:Cond + fun:_ZN16ImageLoaderMachO18validateFirstPagesEPK21linkedit_data_commandiPKhmxRKN11ImageLoader11LinkContextE + fun:_ZN26ImageLoaderMachOCompressed19instantiateFromFileEPKciPKhmyyRK4statjjPK21linkedit_data_commandPK23encryption_info_commandRKN11ImageLoader11LinkContextE + fun:_ZN16ImageLoaderMachO19instantiateFromFileEPKciPKhmyyRK4statRKN11ImageLoader11LinkContextE + fun:_ZN4dyldL10loadPhase6EiRK4statPKcRKNS_11LoadContextE +} + +{ + OSX1013:libsystem_kernel-1 + Memcheck:Cond + obj:*libsystem_kernel*dylib* + obj:*libsystem_kernel*dylib* + obj:*CoreFoundation.framework*CoreFoundation* +} + +{ + OSX1013:CoreServicesInternal-1 + Memcheck:Cond + obj:*CoreServicesInternal.framework*CoreServicesInternal* + obj:*CoreServices.framework*LaunchServices* + obj:*CoreServices.framework*LaunchServices* +} + +{ + OSX1013:CoreServicesInternal-2 + Memcheck:Cond + obj:*CoreServicesInternal.framework*CoreServicesInternal* + obj:*CoreServicesInternal.framework*CoreServicesInternal* + obj:*CoreServicesInternal.framework*CoreServicesInternal* +} + +{ + OSX1013:CoreServicesInternal-3 + Memcheck:Cond + obj:*CoreServicesInternal.framework*CoreServicesInternal* + obj:*CoreServicesInternal.framework*CoreServicesInternal* + obj:*CoreFoundation.framework*CoreFoundation* +} + +{ + OSX1013:CoreServices-1 + Memcheck:Cond + obj:*CoreServices.framework*LaunchServices* + obj:*CoreServices.framework*LaunchServices* + obj:*CoreServices.framework*LaunchServices* +} + +##{ +## OSX1013:libsystem_pthread-1 +## Memcheck:Cond +## obj:*libsystem_pthread*dylib* +## obj:*ImageIO.framework*ImageIO* +## obj:*ImageIO.framework*ImageIO* +##} + +{ + OSX1013:ApplicationServices-1 + Memcheck:Cond + obj:*ApplicationServices.framework*ATS* + obj:*libsystem_pthread*dylib* + obj:*libsystem_platform*dylib* +} + +{ + OSX1013:HIToolbox-1 + Memcheck:Cond + obj:*HIToolbox.framework*HIToolbox* + obj:*HIToolbox.framework*HIToolbox* + obj:*HIToolbox.framework*HIToolbox* +} + +{ + OSX1013:RawCamera-1 + Memcheck:Cond + obj:*RawCamera.bundle*RawCamera* + obj:*libdispatch.dylib* + obj:*libdispatch.dylib* +} + +##{ +## OSX1013:CoreImage-1 +## Memcheck:Cond +## obj:*CoreImage.framework*CoreImage* +## obj:*CoreImage.framework*CoreImage* +## obj:*CoreImage.framework*CoreImage* +##} + +##{ +## OSX1013:strncpy-1 +## Memcheck:Cond +## fun:strncpy +## obj:*CoreServicesInternal.framework*CoreServicesInternal +## obj:*CoreServicesInternal.framework*CoreServicesInternal +##} + +{ + OSX1013:pthread_rwlock_init + Memcheck:Cond + fun:pthread_rwlock_init + obj:*ImageIO.framework*ImageIO* + obj:*ImageIO.framework*ImageIO* +} + +{ + OSX1013:CFBasicHash + Memcheck:Value8 + fun:*CFBasicHash* + fun:*CF* +} + +{ + OSX1013:AppleIntelHD4000GraphicsGLDriver-1-Addr8 + Memcheck:Addr8 + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* +} +{ + OSX1013:AppleIntelHD4000GraphicsGLDriver-1-Addr8 + Memcheck:Addr4 + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* +} + +{ + OSX1013:AppleIntelHD4000GraphicsGLDriver-2-Addr8 + Memcheck:Addr8 + fun:*platform_memmove* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* +} +{ + OSX1013:AppleIntelHD4000GraphicsGLDriver-2-Addr2 + Memcheck:Addr2 + fun:*platform_memmove* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* +} + +{ + OSX1013:AppleIntelHD4000GraphicsGLDriver-3-Addr8 + Memcheck:Addr8 + fun:*platform_memmove* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*GLEngine.bundle*GLEngine* +} +{ + OSX1013:AppleIntelHD4000GraphicsGLDriver-3-Addr2 + Memcheck:Addr2 + fun:*platform_memmove* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*GLEngine.bundle*GLEngine* +} +{ + OSX1013:AppleIntelHD4000GraphicsGLDriver-3-Addr1 + Memcheck:Addr1 + fun:*platform_memmove* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*GLEngine.bundle*GLEngine* +} + +{ + OSX1013:AppleIntelHD4000GraphicsGLDriver-4 + Memcheck:Addr8 + fun:*platform_bzero* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* +} + +{ + OSX1013:AppleIntelHD4000GraphicsGLDriver-6-Addr8 + Memcheck:Addr8 + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*GLEngine.bundle*GLEngine* +} +{ + OSX1013:AppleIntelHD4000GraphicsGLDriver-6-Addr4 + Memcheck:Addr4 + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*GLEngine.bundle*GLEngine* +} + +{ + OSX1013:AppleIntelHD4000GraphicsGLDriver-7 + Memcheck:Addr4 + obj:*AppleIntelHD4000GraphicsGLDriver.bundle*AppleIntelHD4000GraphicsGLDriver* + obj:*GLEngine.bundle*GLEngine* +} + +{ + OSX1013:OSAtomicAdd32 + Memcheck:Addr4 + fun:*OSAtomicAdd32* + obj:*IOAccelerator.framework*IOAccelerator* + obj:*GPUSupport.framework*GPUSupportMercury* +} + +{ + OSX1013:IOAccelerator-1 + Memcheck:Addr4 + obj:*IOAccelerator.framework*IOAccelerator* + obj:*GPUSupport.framework*GPUSupportMercury* +} + +# See https://bugs.kde.org/show_bug.cgi?id=188572 about this; it's +# unavoidable due to BSD setenv() semantics. +{ + macos-__setenv-leak-see-our-bug-188572 + Memcheck:Leak + match-leak-kinds: definite + fun:malloc + fun:_owned_ptr_alloc + fun:setenv +} + +# See https://bugs.kde.org/show_bug.cgi?id=196528 +{ +macos-__pthread_rwlock_init-see-our-bug-196528 +Memcheck:Cond +fun:pthread_rwlock_init +} diff --git a/include/vki/vki-scnums-darwin.h b/include/vki/vki-scnums-darwin.h index 961e335..d600ed3 100644 --- a/include/vki/vki-scnums-darwin.h +++ b/include/vki/vki-scnums-darwin.h @@ -191,6 +191,13 @@ #if defined(VGA_x86) #define __NR_macx_swapon VG_DARWIN_SYSCALL_CONSTRUCT_MACH(48) #define __NR_macx_swapoff VG_DARWIN_SYSCALL_CONSTRUCT_MACH(49) +#endif + +#if DARWIN_VERS >= DARWIN_10_13 +#define __NR_thread_get_special_reply_port VG_DARWIN_SYSCALL_CONSTRUCT_MACH(50) +#endif /* DARWIN_VERS >= DARWIN_10_13 */ + +#if defined(VGA_x86) #define __NR_macx_triggers VG_DARWIN_SYSCALL_CONSTRUCT_MACH(51) #define __NR_macx_backing_store_suspend VG_DARWIN_SYSCALL_CONSTRUCT_MACH(52) #define __NR_macx_backing_store_recovery VG_DARWIN_SYSCALL_CONSTRUCT_MACH(53) @@ -409,7 +416,11 @@ #define __NR_seteuid VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(183) #define __NR_sigreturn VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(184) #define __NR_chud VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(185) +#if DARWIN_VERS >= DARWIN_10_13 +#define __NR_thread_selfcounts VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(186) +#else /* 186 */ +#endif /* DARWIN_VERS >= DARWIN_10_13 */ #if DARWIN_VERS >= DARWIN_10_6 #define __NR_fdatasync VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(187) #else @@ -654,7 +665,11 @@ #if DARWIN_VERS >= DARWIN_10_11 #define __NR_kevent_qos VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(374) #endif /* DARWIN_VERS >= DARWIN_10_11 */ +#if DARWIN_VERS >= DARWIN_10_13 +#define __NR_kevent_id VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(375) +#else /* 375 */ +#endif /* DARWIN_VERS >= DARWIN_10_13 */ /* 376 */ /* 377 */ /* 378 */ @@ -810,6 +825,17 @@ #define __NR_abort_with_payload VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(521) #endif /* DARWIN_VERS >= DARWIN_10_12 */ +#if DARWIN_VERS >= DARWIN_10_13 +#define __NR_necp_session_open VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(522) +#define __NR_necp_session_action VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(523) +#define __NR_setattrlistat VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(524) +#define __NR_net_qos_guideline VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(525) +#define __NR_fmount VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(526) +#define __NR_ntp_adjtime VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(527) +#define __NR_ntp_gettime VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(528) +#define __NR_os_fault_with_payload VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(529) +#endif /* DARWIN_VERS >= DARWIN_10_13 */ + #if DARWIN_VERS < DARWIN_10_6 #define __NR_MAXSYSCALL VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(427) #elif DARWIN_VERS < DARWIN_10_7 @@ -824,6 +850,8 @@ #define __NR_MAXSYSCALL VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(500) #elif DARWIN_VERS == DARWIN_10_12 #define __NR_MAXSYSCALL VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(522) +#elif DARWIN_VERS == DARWIN_10_13 +#define __NR_MAXSYSCALL VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(530) #else #error unknown darwin version #endif |