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From: Philippe W. <phi...@sk...> - 2017-09-11 22:06:49
|
14 valgrind regression tests are failing on Debian 9/x86_64 (all tests were succesful on Debian 8). memcheck/tests/overlap tests fails because valgrind does not detect anymore memcpy calls with overlapping arguments. As far as I can see, this is because memcpy on avx+erms+... CPUs is (with glibc 2.24) implemented by calling an optimised memmove implementation: (gdb) bt #0 () at ../sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S:210 #1 0x000055555555478e in main () at redirf.c:22 (gdb) list redirf.c:22 17 x[i] = 0; 18 19 } 20 21 memcpy(x+50, x, 20); // no overlap 22 memcpy(x+70, x, 10); // no overlap 23 return 0; 24 } (gdb) The redir mechanism of valgrind then redirects the memcpy calls to its memmove vg_replace_mem.c, that does not detect overlap. This somewhat sounds like the return of https://bugs.kde.org/show_bug.cgi?id=275284 Is that failure also seen on other x86_64 glibc 2.24 or 2.25 systems ? Is there any way to improve the redir mechanism to e.g. redirect at the level of the call to callq 0x555555554580 <memcpy@plt> rather than redirecting later at the ifunc function that points to __memmove_avx_unaligned_erms ? Any other idea ? Philippe |
|
From: Rhys K. <rhy...@so...> - 2017-09-10 15:10:20
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=2e5843802daee5eabb73a8d66c0f2d7964d52963 commit 2e5843802daee5eabb73a8d66c0f2d7964d52963 Author: Rhys Kidd <rhy...@gm...> Date: Sun Sep 10 11:08:20 2017 -0400 Update AUTHORS Diff: --- AUTHORS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/AUTHORS b/AUTHORS index da822b9..4c03a66 100644 --- a/AUTHORS +++ b/AUTHORS @@ -82,6 +82,8 @@ liaison. Maran Pakkirisamy implemented support for decimal floating point on s390. +Rhys Kidd updated and maintains the macOS port. + Many, many people sent bug reports, patches, and helpful feedback. Development of Valgrind was supported in part by the Tri-Lab Partners |
|
From: Rhys K. <rhy...@so...> - 2017-09-10 14:51:12
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=128fd6e6a5c94beb6af97ff8146a91422ab50efb commit 128fd6e6a5c94beb6af97ff8146a91422ab50efb Author: Rhys Kidd <rhy...@gm...> Date: Sun Sep 10 01:12:15 2017 -0400 Fix syscall param msg->desc.port.name on macOS 10.12. bz#379373 Based upon patch from Louis Brunner. Diff: --- NEWS | 2 ++ coregrind/m_syswrap/syswrap-darwin.c | 18 +++++++++++++++--- darwin14.supp | 18 ------------------ darwin15.supp | 18 ------------------ darwin16.supp | 18 ------------------ 5 files changed, 17 insertions(+), 57 deletions(-) diff --git a/NEWS b/NEWS index 1b5c80a..e43410a 100644 --- a/NEWS +++ b/NEWS @@ -35,6 +35,8 @@ To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX where XXXXXX is the bug number as listed below. +379373 Fix syscall param msg->desc.port.name points to uninitialised byte(s) + on macOS 10.12 379748 Fix missing pselect syscall (OS X 10.11) 380397 s390x: __GI_strcspn() replacemenet needed 381162 possible array overrun in VEX register allocator diff --git a/coregrind/m_syswrap/syswrap-darwin.c b/coregrind/m_syswrap/syswrap-darwin.c index 0ae281c..0670824 100644 --- a/coregrind/m_syswrap/syswrap-darwin.c +++ b/coregrind/m_syswrap/syswrap-darwin.c @@ -9580,8 +9580,20 @@ PRE(kernelrpc_mach_port_construct_trap) { UWord a1; UWord a2; ULong a3; UWord a4; munge_wwlw(&a1, &a2, &a3, &a4, ARG1, ARG2, ARG3, ARG4, ARG5); - PRINT("kernelrpc_mach_port_construct_trap(FIXME)" - "(%lx,%lx,%llx,%lx)", a1, a2, a3, a4); + PRINT("kernelrpc_mach_port_construct_trap" + "(target: %s, options: %#lx, content: %llx, name: %p)", + name_for_port(a1), a2, a3, *(mach_port_name_t**)a4); + PRE_MEM_WRITE("kernelrpc_mach_port_construct_trap(name)", a4, + sizeof(mach_port_name_t*)); +} +POST(kernelrpc_mach_port_construct_trap) +{ + UWord a1; UWord a2; ULong a3; UWord a4; + munge_wwlw(&a1, &a2, &a3, &a4, ARG1, ARG2, ARG3, ARG4, ARG5); + PRINT("-> name:%p", *(mach_port_name_t**)a4); + if (ML_(safe_to_deref)((mach_port_name_t*)a4, sizeof(mach_port_name_t*))) { + POST_MEM_WRITE(a4, sizeof(mach_port_name_t*)); + } } PRE(kernelrpc_mach_port_destruct_trap) @@ -10597,7 +10609,7 @@ const SyscallTableEntry ML_(mach_trap_table)[] = { # endif # if DARWIN_VERS >= DARWIN_10_9 - MACX_(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(24), kernelrpc_mach_port_construct_trap), + MACXY(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(24), kernelrpc_mach_port_construct_trap), MACX_(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(25), kernelrpc_mach_port_destruct_trap), # else _____(VG_DARWIN_SYSCALL_CONSTRUCT_MACH(24)), diff --git a/darwin14.supp b/darwin14.supp index ba818d5..63fe2b4 100644 --- a/darwin14.supp +++ b/darwin14.supp @@ -665,24 +665,6 @@ obj:*GPUSupport.framework*GPUSupportMercury* } -{ - OSX1010:mach_msg_trap-1 - Memcheck:Param - msg->desc.port.name - fun:mach_msg_trap - obj:*libsystem_kernel.dylib* - obj:*SystemConfiguration.framework*SystemConfiguration* -} - -{ - OSX1010:mach_msg_trap-2 - Memcheck:Param - msg->desc.port.name - fun:mach_msg_trap - obj:*SystemConfiguration.framework*SystemConfiguration* - obj:*SystemConfiguration.framework*SystemConfiguration* -} - # See https://bugs.kde.org/show_bug.cgi?id=188572 about this; it's # unavoidable due to BSD setenv() semantics. { diff --git a/darwin15.supp b/darwin15.supp index e745cf0..a383d24 100644 --- a/darwin15.supp +++ b/darwin15.supp @@ -724,24 +724,6 @@ obj:*GPUSupport.framework*GPUSupportMercury* } -{ - OSX1011:mach_msg_trap-1 - Memcheck:Param - msg->desc.port.name - fun:mach_msg_trap - obj:*libsystem_kernel.dylib* - obj:*SystemConfiguration.framework*SystemConfiguration* -} - -{ - OSX1011:mach_msg_trap-2 - Memcheck:Param - msg->desc.port.name - fun:mach_msg_trap - obj:*SystemConfiguration.framework*SystemConfiguration* - obj:*SystemConfiguration.framework*SystemConfiguration* -} - # See https://bugs.kde.org/show_bug.cgi?id=188572 about this; it's # unavoidable due to BSD setenv() semantics. { diff --git a/darwin16.supp b/darwin16.supp index b3f9dbd..18dda6a 100644 --- a/darwin16.supp +++ b/darwin16.supp @@ -749,24 +749,6 @@ obj:*GPUSupport.framework*GPUSupportMercury* } -{ - OSX1012:mach_msg_trap-1 - Memcheck:Param - msg->desc.port.name - fun:mach_msg_trap - obj:*libsystem_kernel.dylib* - obj:*SystemConfiguration.framework*SystemConfiguration* -} - -{ - OSX1012:mach_msg_trap-2 - Memcheck:Param - msg->desc.port.name - fun:mach_msg_trap - obj:*SystemConfiguration.framework*SystemConfiguration* - obj:*SystemConfiguration.framework*SystemConfiguration* -} - # See https://bugs.kde.org/show_bug.cgi?id=188572 about this; it's # unavoidable due to BSD setenv() semantics. { |
|
From: Ivo R. <ir...@so...> - 2017-09-10 09:47:51
|
https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=6a113f32c270e98db2a179c4d414e9a1cdf87363 commit 6a113f32c270e98db2a179c4d414e9a1cdf87363 Author: Ivo Raisr <iv...@iv...> Date: Sun Sep 10 11:47:01 2017 +0200 Cherry-pick 3117cd9637a843cbab5de302fb30e22153fbfc1c from master. Reduce number of spill instructions generated by VEX register allocator v3. Keeps track whether the bound real register has been reloaded from a virtual register recently and if this real reg is still equal to that spill slot. Avoids unnecessary spilling that vreg later, when this rreg needs to be reserved, usually as a caller save register for a helper call. Diff: --- VEX/priv/host_generic_reg_alloc3.c | 109 +++++++++++++++++++++++++++---------- 1 file changed, 80 insertions(+), 29 deletions(-) diff --git a/VEX/priv/host_generic_reg_alloc3.c b/VEX/priv/host_generic_reg_alloc3.c index 8c3628e..a13d620 100644 --- a/VEX/priv/host_generic_reg_alloc3.c +++ b/VEX/priv/host_generic_reg_alloc3.c @@ -141,6 +141,12 @@ typedef /* If .disp == Bound, what vreg is it bound to? */ HReg vreg; + + /* If .disp == Bound, has the associated vreg been reloaded from its spill + slot recently and is this rreg still equal to that spill slot? + Avoids unnecessary spilling that vreg later, when this rreg needs + to be reserved. */ + Bool eq_spill_slot; } RRegState; @@ -309,6 +315,12 @@ static inline void enlarge_rreg_lrs(RRegLRState* rreg_lrs) rreg_lrs->lrs_size = 2 * rreg_lrs->lrs_used; } +#define PRINT_STATE(what) \ + do { \ + print_state(chunk, vreg_state, n_vregs, rreg_state, INSTRNO_TOTAL, \ + depth, con, what); \ + } while (0) + static inline void print_state(const RegAllocChunk* chunk, const VRegState* vreg_state, UInt n_vregs, const RRegState* rreg_state, Short ii_total_current, UInt depth, const RegAllocControl* con, @@ -374,6 +386,9 @@ static inline void print_state(const RegAllocChunk* chunk, case Bound: vex_printf("bound for "); con->ppReg(rreg->vreg); + if (rreg->eq_spill_slot) { + vex_printf(" (equals to its spill slot)"); + } vex_printf("\n"); break; case Reserved: @@ -400,6 +415,21 @@ static inline void emit_instr(RegAllocChunk* chunk, HInstr* instr, UInt depth, addHInstr(chunk->instrs_out, instr); } +/* Updates register allocator state after vreg has been spilled. */ +static inline void mark_vreg_spilled( + UInt v_idx, VRegState* vreg_state, UInt n_vregs, + RRegState* rreg_state, UInt n_rregs) +{ + HReg rreg = vreg_state[v_idx].rreg; + UInt r_idx = hregIndex(rreg); + + vreg_state[v_idx].disp = Spilled; + vreg_state[v_idx].rreg = INVALID_HREG; + rreg_state[r_idx].disp = Free; + rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].eq_spill_slot = False; +} + /* Spills a vreg assigned to some rreg. The vreg is spilled and the rreg is freed. Returns rreg's index. */ @@ -434,12 +464,7 @@ static inline UInt spill_vreg( emit_instr(chunk, spill2, depth, con, "spill2"); } - /* Update register allocator state. */ - vreg_state[v_idx].disp = Spilled; - vreg_state[v_idx].rreg = INVALID_HREG; - rreg_state[r_idx].disp = Free; - rreg_state[r_idx].vreg = INVALID_HREG; - + mark_vreg_spilled(v_idx, vreg_state, n_vregs, rreg_state, n_rregs); return r_idx; } @@ -1039,8 +1064,7 @@ static void stage4_chunk(RegAllocChunk* chunk, vex_printf("---- "); con->ppInstr(chunk->instrs_in->insns[ii_vec], con->mode64); vex_printf("\n\n"); - print_state(chunk, vreg_state, n_vregs, rreg_state, INSTRNO_TOTAL, - depth, con, "Initial Register Allocator state"); + PRINT_STATE("Initial Register Allocator state"); vex_printf("\n"); } @@ -1084,6 +1108,8 @@ static void stage4_chunk(RegAllocChunk* chunk, vassert(IS_VALID_VREGNO(v_idx)); vassert(vreg_state[v_idx].disp == Assigned); vassert(hregIndex(vreg_state[v_idx].rreg) == r_idx); + } else { + vassert(rreg_state[r_idx].eq_spill_slot == False); } } @@ -1133,7 +1159,8 @@ static void stage4_chunk(RegAllocChunk* chunk, UInt r_idx = hregIndex(rreg); vassert(rreg_state[r_idx].disp == Bound); - rreg_state[r_idx].vreg = vregD; + rreg_state[r_idx].vreg = vregD; + rreg_state[r_idx].eq_spill_slot = False; if (DEBUG_REGALLOC) { print_depth(depth); @@ -1152,8 +1179,9 @@ static void stage4_chunk(RegAllocChunk* chunk, if (vreg_state[vd_idx].dead_before <= INSTRNO_TOTAL + 1) { vreg_state[vd_idx].disp = Unallocated; vreg_state[vd_idx].rreg = INVALID_HREG; - rreg_state[r_idx].disp = Free; - rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].disp = Free; + rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].eq_spill_slot = False; } /* Move on to the next instruction. We skip the post-instruction @@ -1203,16 +1231,22 @@ static void stage4_chunk(RegAllocChunk* chunk, if ((rreg_lrs->lr_current->live_after <= ii_chunk) && (ii_chunk < rreg_lrs->lr_current->dead_before)) { - if (rreg->disp == Bound) { + switch (rreg->disp) { + case Bound: { /* Yes, there is an associated vreg. We need to deal with it now somehow. */ HReg vreg = rreg->vreg; UInt v_idx = hregIndex(vreg); if (! HRegUsage__contains(reg_usage, vreg)) { - /* Spill the vreg. It is not used by this instruction. */ - spill_vreg(chunk, vreg_state, n_vregs, rreg_state, - vreg, v_idx, INSTRNO_TOTAL, depth, con); + if (rreg->eq_spill_slot) { + mark_vreg_spilled(v_idx, vreg_state, n_vregs, + rreg_state, n_rregs); + } else { + /* Spill the vreg. It is not used by this instruction.*/ + spill_vreg(chunk, vreg_state, n_vregs, rreg_state, + vreg, v_idx, INSTRNO_TOTAL, depth, con); + } } else { /* Find or make a free rreg where to move this vreg to. */ UInt r_free_idx = FIND_OR_MAKE_FREE_RREG( @@ -1229,9 +1263,17 @@ static void stage4_chunk(RegAllocChunk* chunk, vreg_state[v_idx].rreg = con->univ->regs[r_free_idx]; rreg_state[r_free_idx].disp = Bound; rreg_state[r_free_idx].vreg = vreg; - rreg->disp = Free; - rreg->vreg = INVALID_HREG; + rreg_state[r_free_idx].eq_spill_slot = rreg->eq_spill_slot; + rreg->disp = Free; + rreg->vreg = INVALID_HREG; + rreg->eq_spill_slot = False; } + break; + } + case Free: + break; + default: + vassert(0); } /* Finally claim the rreg as reserved. */ @@ -1342,15 +1384,16 @@ static void stage4_chunk(RegAllocChunk* chunk, UInt v_idx = hregIndex(vreg); vassert(IS_VALID_VREGNO(v_idx)); HReg rreg = vreg_state[v_idx].rreg; + UInt r_idx; if (vreg_state[v_idx].disp == Assigned) { - UInt r_idx = hregIndex(rreg); + r_idx = hregIndex(rreg); vassert(rreg_state[r_idx].disp == Bound); addToHRegRemap(&remap, vreg, rreg); } else { vassert(hregIsInvalid(rreg)); /* Find or make a free rreg of the correct class. */ - UInt r_idx = FIND_OR_MAKE_FREE_RREG( + r_idx = FIND_OR_MAKE_FREE_RREG( v_idx, vreg_state[v_idx].reg_class, False); rreg = con->univ->regs[r_idx]; @@ -1373,12 +1416,18 @@ static void stage4_chunk(RegAllocChunk* chunk, } } - rreg_state[r_idx].disp = Bound; - rreg_state[r_idx].vreg = vreg; + rreg_state[r_idx].disp = Bound; + rreg_state[r_idx].vreg = vreg; + rreg_state[r_idx].eq_spill_slot = True; vreg_state[v_idx].disp = Assigned; vreg_state[v_idx].rreg = rreg; addToHRegRemap(&remap, vreg, rreg); } + + /* If this vreg is written or modified, mark it so. */ + if (reg_usage->vMode[j] != HRmRead) { + rreg_state[r_idx].eq_spill_slot = False; + } } con->mapRegs(&remap, instr, con->mode64); @@ -1386,8 +1435,7 @@ static void stage4_chunk(RegAllocChunk* chunk, if (DEBUG_REGALLOC) { print_depth(depth); - print_state(chunk, vreg_state, n_vregs, rreg_state, INSTRNO_TOTAL, - depth, con, "Register Allocator state after dealing with" + PRINT_STATE("Register Allocator state after dealing with" " the current instruction"); vex_printf("\n"); } @@ -1406,8 +1454,9 @@ static void stage4_chunk(RegAllocChunk* chunk, if (rreg_lrs->lrs_used > 0) { /* Consider "dead before" the next instruction. */ if (rreg_lrs->lr_current->dead_before <= ii_chunk + 1) { - rreg_state[r_idx].disp = Free; - rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].disp = Free; + rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].eq_spill_slot = False; if (rreg_lrs->lr_current_idx < rreg_lrs->lrs_used - 1) { rreg_lrs->lr_current_idx += 1; rreg_lrs->lr_current @@ -1422,8 +1471,9 @@ static void stage4_chunk(RegAllocChunk* chunk, if (vreg_state[v_idx].dead_before <= INSTRNO_TOTAL + 1) { vreg_state[v_idx].disp = Unallocated; vreg_state[v_idx].rreg = INVALID_HREG; - rreg_state[r_idx].disp = Free; - rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].disp = Free; + rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].eq_spill_slot = False; } break; } @@ -1515,8 +1565,9 @@ HInstrSB* doRegisterAllocation( every Out-Of-Line leg. */ RRegState* rreg_state = LibVEX_Alloc_inline(n_rregs * sizeof(RRegState)); for (UInt r_idx = 0; r_idx < n_rregs; r_idx++) { - rreg_state[r_idx].disp = Free; - rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].disp = Free; + rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].eq_spill_slot = False; } /* --- Stage 1. Determine total ordering of instructions and structure |
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From: Ivo R. <ir...@so...> - 2017-09-10 07:44:33
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=3117cd9637a843cbab5de302fb30e22153fbfc1c commit 3117cd9637a843cbab5de302fb30e22153fbfc1c Author: Ivo Raisr <iv...@iv...> Date: Sat Sep 9 22:08:21 2017 +0200 Reduce number of spill instructions generated by VEX register allocator v3. Keeps track whether the bound real register has been reloaded from a virtual register recently and if this real reg is still equal to that spill slot. Avoids unnecessary spilling that vreg later, when this rreg needs to be reserved, usually as a caller save register for a helper call. Fixes BZ#384526. Diff: --- NEWS | 1 + VEX/priv/host_generic_reg_alloc3.c | 115 +++++++++++++++++++++++++++---------- 2 files changed, 85 insertions(+), 31 deletions(-) diff --git a/NEWS b/NEWS index 835e35f..1b5c80a 100644 --- a/NEWS +++ b/NEWS @@ -50,6 +50,7 @@ where XXXXXX is the bug number as listed below. 382998 xml-socket doesn't work 383275 massif valgrind: m_xarray.c:162 (ensureSpaceXA): Assertion '!xa->arr' failed 384096 Mention AddrCheck at Memcheck's command line option --undef-value-errors=no +384526 reduce number of spill instructions generated by VEX register allocator v3 Release 3.13.0 (15 June 2017) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/VEX/priv/host_generic_reg_alloc3.c b/VEX/priv/host_generic_reg_alloc3.c index f798372..8ee4e48 100644 --- a/VEX/priv/host_generic_reg_alloc3.c +++ b/VEX/priv/host_generic_reg_alloc3.c @@ -96,6 +96,12 @@ typedef /* If .disp == Bound, what vreg is it bound to? */ HReg vreg; + + /* If .disp == Bound, has the associated vreg been reloaded from its spill + slot recently and is this rreg still equal to that spill slot? + Avoids unnecessary spilling that vreg later, when this rreg needs + to be reserved. */ + Bool eq_spill_slot; } RRegState; @@ -157,6 +163,12 @@ static inline void enlarge_rreg_lrs(RRegLRState* rreg_lrs) rreg_lrs->lrs_size = 2 * rreg_lrs->lrs_used; } +#define PRINT_STATE \ + do { \ + print_state(con, vreg_state, n_vregs, rreg_state, n_rregs, \ + rreg_lr_state, ii); \ + } while (0) + static inline void print_state( const RegAllocControl* con, const VRegState* vreg_state, UInt n_vregs, @@ -217,6 +229,9 @@ static inline void print_state( case Bound: vex_printf("bound for "); con->ppReg(rreg->vreg); + if (rreg->eq_spill_slot) { + vex_printf(" (equals to its spill slot)"); + } vex_printf("\n"); break; case Reserved: @@ -243,6 +258,21 @@ static inline void emit_instr(HInstr* instr, HInstrArray* instrs_out, addHInstr(instrs_out, instr); } +/* Updates register allocator state after vreg has been spilled. */ +static inline void mark_vreg_spilled( + UInt v_idx, VRegState* vreg_state, UInt n_vregs, + RRegState* rreg_state, UInt n_rregs) +{ + HReg rreg = vreg_state[v_idx].rreg; + UInt r_idx = hregIndex(rreg); + + vreg_state[v_idx].disp = Spilled; + vreg_state[v_idx].rreg = INVALID_HREG; + rreg_state[r_idx].disp = Free; + rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].eq_spill_slot = False; +} + /* Spills a vreg assigned to some rreg. The vreg is spilled and the rreg is freed. Returns rreg's index. */ @@ -274,12 +304,7 @@ static inline UInt spill_vreg( emit_instr(spill2, instrs_out, con, "spill2"); } - /* Update register allocator state. */ - vreg_state[v_idx].disp = Spilled; - vreg_state[v_idx].rreg = INVALID_HREG; - rreg_state[r_idx].disp = Free; - rreg_state[r_idx].vreg = INVALID_HREG; - + mark_vreg_spilled(v_idx, vreg_state, n_vregs, rreg_state, n_rregs); return r_idx; } @@ -508,8 +533,9 @@ HInstrArray* doRegisterAllocation_v3( } for (UInt r_idx = 0; r_idx < n_rregs; r_idx++) { - rreg_state[r_idx].disp = Free; - rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].disp = Free; + rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].eq_spill_slot = False; } for (UInt r_idx = 0; r_idx < n_rregs; r_idx++) { @@ -777,8 +803,7 @@ HInstrArray* doRegisterAllocation_v3( vex_printf("---- "); con->ppInstr(instrs_in->arr[ii], con->mode64); vex_printf("\n\nInitial state:\n"); - print_state(con, vreg_state, n_vregs, rreg_state, n_rregs, - rreg_lr_state, ii); + PRINT_STATE; vex_printf("\n"); } @@ -820,6 +845,8 @@ HInstrArray* doRegisterAllocation_v3( vassert(IS_VALID_VREGNO(v_idx)); vassert(vreg_state[v_idx].disp == Assigned); vassert(hregIndex(vreg_state[v_idx].rreg) == r_idx); + } else { + vassert(rreg_state[r_idx].eq_spill_slot == False); } } @@ -869,7 +896,8 @@ HInstrArray* doRegisterAllocation_v3( UInt r_idx = hregIndex(rreg); vassert(rreg_state[r_idx].disp == Bound); - rreg_state[r_idx].vreg = vregD; + rreg_state[r_idx].vreg = vregD; + rreg_state[r_idx].eq_spill_slot = False; if (DEBUG_REGALLOC) { vex_printf("coalesced: "); @@ -887,8 +915,9 @@ HInstrArray* doRegisterAllocation_v3( if (vreg_state[vd_idx].dead_before <= (Short) ii + 1) { vreg_state[vd_idx].disp = Unallocated; vreg_state[vd_idx].rreg = INVALID_HREG; - rreg_state[r_idx].disp = Free; - rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].disp = Free; + rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].eq_spill_slot = False; } /* Move on to the next instruction. We skip the post-instruction @@ -938,16 +967,22 @@ HInstrArray* doRegisterAllocation_v3( if ((rreg_lrs->lr_current->live_after <= (Short) ii) && ((Short) ii < rreg_lrs->lr_current->dead_before)) { - if (rreg->disp == Bound) { + switch (rreg->disp) { + case Bound: { /* Yes, there is an associated vreg. We need to deal with it now somehow. */ HReg vreg = rreg->vreg; UInt v_idx = hregIndex(vreg); if (! HRegUsage__contains(®_usage[ii], vreg)) { - /* Spill the vreg. It is not used by this instruction. */ - spill_vreg(vreg, v_idx, ii, vreg_state, n_vregs, - rreg_state, n_rregs, instrs_out, con); + if (rreg->eq_spill_slot) { + mark_vreg_spilled(v_idx, vreg_state, n_vregs, + rreg_state, n_rregs); + } else { + /* Spill the vreg. It is not used by this instruction.*/ + spill_vreg(vreg, v_idx, ii, vreg_state, n_vregs, + rreg_state, n_rregs, instrs_out, con); + } } else { /* Find or make a free rreg where to move this vreg to. */ UInt r_free_idx = FIND_OR_MAKE_FREE_RREG( @@ -962,11 +997,19 @@ HInstrArray* doRegisterAllocation_v3( /* Update the register allocator state. */ vassert(vreg_state[v_idx].disp == Assigned); vreg_state[v_idx].rreg = con->univ->regs[r_free_idx]; - rreg_state[r_free_idx].disp = Bound; - rreg_state[r_free_idx].vreg = vreg; - rreg->disp = Free; - rreg->vreg = INVALID_HREG; + rreg_state[r_free_idx].disp = Bound; + rreg_state[r_free_idx].vreg = vreg; + rreg_state[r_free_idx].eq_spill_slot = rreg->eq_spill_slot; + rreg->disp = Free; + rreg->vreg = INVALID_HREG; + rreg->eq_spill_slot = False; } + break; + } + case Free: + break; + default: + vassert(0); } /* Finally claim the rreg as reserved. */ @@ -1073,15 +1116,16 @@ HInstrArray* doRegisterAllocation_v3( UInt v_idx = hregIndex(vreg); vassert(IS_VALID_VREGNO(v_idx)); HReg rreg = vreg_state[v_idx].rreg; + UInt r_idx; if (vreg_state[v_idx].disp == Assigned) { - UInt r_idx = hregIndex(rreg); + r_idx = hregIndex(rreg); vassert(rreg_state[r_idx].disp == Bound); addToHRegRemap(&remap, vreg, rreg); } else { vassert(hregIsInvalid(rreg)); /* Find or make a free rreg of the correct class. */ - UInt r_idx = FIND_OR_MAKE_FREE_RREG( + r_idx = FIND_OR_MAKE_FREE_RREG( ii, v_idx, vreg_state[v_idx].reg_class, False); rreg = con->univ->regs[r_idx]; @@ -1102,14 +1146,22 @@ HInstrArray* doRegisterAllocation_v3( if (reload2 != NULL) { emit_instr(reload2, instrs_out, con, "reload2"); } + + } - rreg_state[r_idx].disp = Bound; - rreg_state[r_idx].vreg = vreg; + rreg_state[r_idx].disp = Bound; + rreg_state[r_idx].vreg = vreg; + rreg_state[r_idx].eq_spill_slot = True; vreg_state[v_idx].disp = Assigned; vreg_state[v_idx].rreg = rreg; addToHRegRemap(&remap, vreg, rreg); } + + /* If this vreg is written or modified, mark it so. */ + if (reg_usage[ii].vMode[j] != HRmRead) { + rreg_state[r_idx].eq_spill_slot = False; + } } con->mapRegs(&remap, instr, con->mode64); @@ -1117,8 +1169,7 @@ HInstrArray* doRegisterAllocation_v3( if (DEBUG_REGALLOC) { vex_printf("After dealing with current instruction:\n"); - print_state(con, vreg_state, n_vregs, rreg_state, n_rregs, - rreg_lr_state, ii); + PRINT_STATE; vex_printf("\n"); } @@ -1136,8 +1187,9 @@ HInstrArray* doRegisterAllocation_v3( if (rreg_lrs->lrs_used > 0) { /* Consider "dead before" the next instruction. */ if (rreg_lrs->lr_current->dead_before <= (Short) ii + 1) { - rreg_state[r_idx].disp = Free; - rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].disp = Free; + rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].eq_spill_slot = False; if (rreg_lrs->lr_current_idx < rreg_lrs->lrs_used - 1) { rreg_lrs->lr_current_idx += 1; rreg_lrs->lr_current @@ -1152,8 +1204,9 @@ HInstrArray* doRegisterAllocation_v3( if (vreg_state[v_idx].dead_before <= (Short) ii + 1) { vreg_state[v_idx].disp = Unallocated; vreg_state[v_idx].rreg = INVALID_HREG; - rreg_state[r_idx].disp = Free; - rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].disp = Free; + rreg_state[r_idx].vreg = INVALID_HREG; + rreg_state[r_idx].eq_spill_slot = False; } break; } |
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From: Ivo R. <ir...@so...> - 2017-09-09 11:22:47
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=1639d6c7830261c3be1bc402a6a4cd3cef487077 commit 1639d6c7830261c3be1bc402a6a4cd3cef487077 Author: Ivo Raisr <iv...@iv...> Date: Mon Sep 4 09:21:05 2017 +0200 Small performance enhancement to VEX register allocator v2. Iterate only over real registers of the target hreg class. Diff: --- VEX/priv/host_generic_reg_alloc2.c | 40 ++++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/VEX/priv/host_generic_reg_alloc2.c b/VEX/priv/host_generic_reg_alloc2.c index ec291d3..eb4600e 100644 --- a/VEX/priv/host_generic_reg_alloc2.c +++ b/VEX/priv/host_generic_reg_alloc2.c @@ -162,23 +162,25 @@ typedef spill, or -1 if none was found. */ static Int findMostDistantlyMentionedVReg ( - HRegUsage* reg_usages_in, - Int search_from_instr, - Int num_instrs, - RRegState* state, - Int n_state + HRegUsage* reg_usages_in, + Int search_from_instr, + Int num_instrs, + RRegState* rreg_state, + HRegClass hreg_class, + const RegAllocControl* con ) { - Int k, m; + Int m; Int furthest_k = -1; Int furthest = -1; vassert(search_from_instr >= 0); - for (k = 0; k < n_state; k++) { - if (!state[k].is_spill_cand) + for (UInt k = con->univ->allocable_start[hreg_class]; + k <= con->univ->allocable_end[hreg_class]; k++) { + if (!rreg_state[k].is_spill_cand) continue; - vassert(state[k].disp == Bound); + vassert(rreg_state[k].disp == Bound); for (m = search_from_instr; m < num_instrs; m++) { - if (HRegUsage__contains(®_usages_in[m], state[k].vreg)) + if (HRegUsage__contains(®_usages_in[m], rreg_state[k].vreg)) break; } if (m > furthest) { @@ -210,7 +212,7 @@ static void ensureRRLRspace_SLOW ( RRegLR** info, Int* size, Int used ) Int k; RRegLR* arr2; if (0) - vex_printf("ensureRRISpace: %d -> %d\n", *size, 2 * *size); + vex_printf("ensureRRLRspace: %d -> %d\n", *size, 2 * *size); vassert(used == *size); arr2 = LibVEX_Alloc_inline(2 * *size * sizeof(RRegLR)); for (k = 0; k < *size; k++) @@ -1291,9 +1293,9 @@ HInstrArray* doRegisterAllocation_v2 ( as possible. */ Int k_suboptimal = -1; Int k; - for (k = 0; k < n_rregs; k++) { - if (rreg_state[k].disp != Free - || hregClass(con->univ->regs[k]) != hregClass(vreg)) + for (k = con->univ->allocable_start[hregClass(vreg)]; + k <= con->univ->allocable_end[hregClass(vreg)]; k++) { + if (rreg_state[k].disp != Free) continue; if (rreg_state[k].has_hlrs) { /* Well, at least we can use k_suboptimal if we really @@ -1308,7 +1310,7 @@ HInstrArray* doRegisterAllocation_v2 ( if (k_suboptimal >= 0) k = k_suboptimal; - if (k < n_rregs) { + if (k <= con->univ->allocable_end[hregClass(vreg)]) { rreg_state[k].disp = Bound; rreg_state[k].vreg = vreg; Int p = hregIndex(vreg); @@ -1356,12 +1358,11 @@ HInstrArray* doRegisterAllocation_v2 ( /* First, mark in the rreg_state, those rregs which are not spill candidates, due to holding a vreg mentioned by this instruction. Or being of the wrong class. */ - for (k = 0; k < n_rregs; k++) { + for (k = con->univ->allocable_start[hregClass(vreg)]; + k <= con->univ->allocable_end[hregClass(vreg)]; k++) { rreg_state[k].is_spill_cand = False; if (rreg_state[k].disp != Bound) continue; - if (hregClass(con->univ->regs[k]) != hregClass(vreg)) - continue; rreg_state[k].is_spill_cand = True; /* Note, the following loop visits only the virtual regs mentioned by the instruction. */ @@ -1380,7 +1381,8 @@ HInstrArray* doRegisterAllocation_v2 ( of consequent reloads required. */ Int spillee = findMostDistantlyMentionedVReg ( - reg_usage_arr, ii+1, instrs_in->arr_used, rreg_state, n_rregs ); + reg_usage_arr, ii+1, instrs_in->arr_used, rreg_state, + hregClass(vreg), con); if (spillee == -1) { /* Hmmmmm. There don't appear to be any spill candidates. |
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From: Son T. VU <son...@gm...> - 2017-09-08 17:35:55
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Hello all, I am currently using angr (http://angr.io/) to analyze FreeRTOS compiled to ARM Thumb2 assembly. I actually caught some bugs (I think) in VEX IR: - For MRS/MSR instructions (at least in Thumb mode), VEX only accepts APSR as its PSR operand, while in reality we can have for example BASEPRI or CONTROL registers as well. Apparently these registers don't exist in VEX? - For SVC instruction, VEX only supports the system call case, do you think it may have a chance to be able to handle exceptions in any near future? Thank you for your help, Cheers, Son Vu |
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From: Ivo R. <iv...@iv...> - 2017-09-04 06:29:53
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Dear developers, Would the Valgrind community be interested in a Valgrind developer room at FOSDEM 2018 [1]? The deadline for developer room proposals is September 20th. I volunteer to help with the organization, similarly to the last year. We had a dev room at FOSDEM 2014, 2015, and 2017 and it seemed to be quite interesting experience for all participating... If I remember correctly, devroom at FOSDEM 2017 was constantly over packed! Kind regards, I. [1] https://submission.fosdem.org/devroom.php |
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From: Rhys K. <rhy...@so...> - 2017-09-03 17:08:22
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=55fe390c7ac2bbd6b1b591747329fa4041d6c464 commit 55fe390c7ac2bbd6b1b591747329fa4041d6c464 Author: Rhys Kidd <rhy...@gm...> Date: Sun Sep 3 12:55:52 2017 -0400 Fix missing pselect syscall (OS X 10.11). bz#379748 Based upon patch from Louis Brunner. Diff: --- NEWS | 1 + coregrind/m_syswrap/priv_syswrap-darwin.h | 4 ++++ coregrind/m_syswrap/syswrap-darwin.c | 34 +++++++++++++++++++++++++++++++ include/vki/vki-scnums-darwin.h | 6 ++++++ memcheck/tests/darwin/scalar.c | 10 +++++++++ memcheck/tests/darwin/scalar.stderr.exp | 27 ++++++++++++++++++++++++ 6 files changed, 82 insertions(+) diff --git a/NEWS b/NEWS index 316beaf..835e35f 100644 --- a/NEWS +++ b/NEWS @@ -35,6 +35,7 @@ To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX where XXXXXX is the bug number as listed below. +379748 Fix missing pselect syscall (OS X 10.11) 380397 s390x: __GI_strcspn() replacemenet needed 381162 possible array overrun in VEX register allocator 381272 ppc64 doesn't compile test_isa_2_06_partx.c without VSX support diff --git a/coregrind/m_syswrap/priv_syswrap-darwin.h b/coregrind/m_syswrap/priv_syswrap-darwin.h index 4755e71..bdefd61 100644 --- a/coregrind/m_syswrap/priv_syswrap-darwin.h +++ b/coregrind/m_syswrap/priv_syswrap-darwin.h @@ -489,7 +489,11 @@ DECL_TEMPLATE(darwin, __mac_syscall); // 381 // NYI __mac_get_lcid 391 // NYI __mac_get_lctx 392 // NYI __mac_set_lctx 393 +#if DARWIN_VERS >= DARWIN_10_11 +DECL_TEMPLATE(darwin, pselect); // 394 +#else // NYI setlcid 394 +#endif /* DARWIN_VERS >= DARWIN_10_11 */ // NYI getlcid 395 // GEN read_nocancel 396 // GEN write_nocancel 397 diff --git a/coregrind/m_syswrap/syswrap-darwin.c b/coregrind/m_syswrap/syswrap-darwin.c index f219920..0ae281c 100644 --- a/coregrind/m_syswrap/syswrap-darwin.c +++ b/coregrind/m_syswrap/syswrap-darwin.c @@ -9794,6 +9794,39 @@ PRE(guarded_writev_np) /* --------------------------------------------------------------------- + Added for OSX 10.11 (El Capitan) + ------------------------------------------------------------------ */ + +#if DARWIN_VERS >= DARWIN_10_11 + +PRE(pselect) +{ + *flags |= SfMayBlock; + PRINT("pselect ( %ld, %#lx, %#lx, %#lx, %#lx, %#lx )", SARG1, ARG2, ARG3, + ARG4, ARG5, ARG6); + PRE_REG_READ5(long, "pselect", + int, n, vki_fd_set *, readfds, vki_fd_set *, writefds, + vki_fd_set *, exceptfds, struct vki_timeval *, timeout); + // XXX: this possibly understates how much memory is read. + if (ARG2 != 0) + PRE_MEM_READ( "pselect(readfds)", + ARG2, ARG1/8 /* __FD_SETSIZE/8 */ ); + if (ARG3 != 0) + PRE_MEM_READ( "pselect(writefds)", + ARG3, ARG1/8 /* __FD_SETSIZE/8 */ ); + if (ARG4 != 0) + PRE_MEM_READ( "pselect(exceptfds)", + ARG4, ARG1/8 /* __FD_SETSIZE/8 */ ); + if (ARG5 != 0) + PRE_timeval_READ( "pselect(timeout)", ARG5 ); + if (ARG6 != 0) + PRE_MEM_READ( "pselect(sigmask)", ARG6, sizeof(vki_sigset_t) ); +} + +#endif /* DARWIN_VERS >= DARWIN_10_11 */ + + +/* --------------------------------------------------------------------- Added for macOS 10.12 (Sierra) ------------------------------------------------------------------ */ @@ -10454,6 +10487,7 @@ const SyscallTableEntry ML_(syscall_table)[] = { #if DARWIN_VERS >= DARWIN_10_11 // _____(__NR_kdebug_trace_string), // 178 // _____(__NR_kevent_qos), // 374 + MACX_(__NR_pselect, pselect), // 394 // _____(__NR_netagent_trigger), // 490 // _____(__NR_stack_snapshot_with_config), // 491 // _____(__NR_microstackshot), // 492 diff --git a/include/vki/vki-scnums-darwin.h b/include/vki/vki-scnums-darwin.h index 04b42c8..961e335 100644 --- a/include/vki/vki-scnums-darwin.h +++ b/include/vki/vki-scnums-darwin.h @@ -673,7 +673,13 @@ #define __NR___mac_get_lcid VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(391) #define __NR___mac_get_lctx VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(392) #define __NR___mac_set_lctx VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(393) + +#if DARWIN_VERS >= DARWIN_10_11 +#define __NR_pselect VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(394) +#else #define __NR_setlcid VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(394) +#endif /* DARWIN_VERS >= DARWIN_10_11 */ + #define __NR_getlcid VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(395) #define __NR_read_nocancel VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(396) #define __NR_write_nocancel VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(397) diff --git a/memcheck/tests/darwin/scalar.c b/memcheck/tests/darwin/scalar.c index d74996c..4aac07a 100644 --- a/memcheck/tests/darwin/scalar.c +++ b/memcheck/tests/darwin/scalar.c @@ -676,7 +676,17 @@ int main(void) // __NR___mac_get_lcid 391 // __NR___mac_get_lctx 392 // __NR___mac_set_lctx 393 + +#if DARWIN_VERS >= DARWIN_10_11 + { + long args[6] = { x0+8, x0+0xffffffee, x0+1, x0+1, x0+1, x0+1 }; + GO(__NR_pselect, 394, "1s 6m"); + SY(__NR_pselect, args+x0); FAIL; + } +#else // __NR_setlcid 394 +#endif /* DARWIN_VERS >= DARWIN_10_11 */ + // __NR_getlcid 395 // The nocancel syscalls (396--423) are tested in scalar_nocancel.c. diff --git a/memcheck/tests/darwin/scalar.stderr.exp b/memcheck/tests/darwin/scalar.stderr.exp index 56fd999..aba39e8 100644 --- a/memcheck/tests/darwin/scalar.stderr.exp +++ b/memcheck/tests/darwin/scalar.stderr.exp @@ -1177,6 +1177,33 @@ Syscall param getfsstat64(buf) points to unaddressable byte(s) (369-379): unused ----------------------------------------------------- ----------------------------------------------------- +x200018a(394): __NR_pselect 1s 6m +----------------------------------------------------- +Syscall param pselect(readfds) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:684) + +Syscall param pselect(writefds) contains uninitialised byte(s) + ... + by 0x........: main (scalar.c:684) + +Syscall param pselect(readfds) points to uninitialised byte(s) + ... + by 0x........: main (scalar.c:684) + Address 0x........ is on thread 1's stack + in frame #1, created by main (scalar.c:12) + +Syscall param pselect(writefds) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:684) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +Syscall param pselect(exceptfds) points to unaddressable byte(s) + ... + by 0x........: main (scalar.c:684) + Address 0x........ is not stack'd, malloc'd or (recently) free'd + +----------------------------------------------------- x270f(9999): 9999 1e ----------------------------------------------------- WARNING: unhandled amd64-darwin syscall: unix:9999 |
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From: Ivo R. <ir...@so...> - 2017-09-02 11:24:45
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=0fc3751e1bdaab7294813d4e3aa7ea5d8e880bad commit 0fc3751e1bdaab7294813d4e3aa7ea5d8e880bad Author: Ivo Raisr <iv...@iv...> Date: Sat Sep 2 13:23:30 2017 +0200 Used UInt instead of UChar for bitset array element. Diff: --- VEX/priv/ir_defs.c | 24 ++++++++++++------------ VEX/pub/libvex_ir.h | 14 ++++++++------ 2 files changed, 20 insertions(+), 18 deletions(-) diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c index f01eb40..ee2fa7f 100644 --- a/VEX/priv/ir_defs.c +++ b/VEX/priv/ir_defs.c @@ -1751,13 +1751,13 @@ void ppIRTypeEnvDefd(const IRTypeEnv* tyenv, const IRTempDefSet* defset, UInt tmps_printed = 0; for (UInt slot = 0; slot < defset->slots_used; slot++) { - UChar slot_value = defset->set[slot]; - for (UInt bit = 0; bit < sizeof(UChar); bit++) { + UInt slot_value = defset->set[slot]; + for (UInt bit = 0; bit < BITS_PER_SLOT; bit++) { if (slot_value & (1 << bit)) { if (tmps_printed % 8 == 0) print_depth(depth); - IRTemp tmp = slot * sizeof(UChar) + bit; + IRTemp tmp = slot * BITS_PER_SLOT + bit; ppIRTemp(tmp); if (tyenv != NULL) { vex_printf(":"); @@ -2265,9 +2265,9 @@ IRTempDefSet* emptyIRTempDefSet(void) { IRTempDefSet* defset = LibVEX_Alloc_inline(sizeof(IRTempDefSet)); defset->slots_used = 0; - defset->slots_size = 8 / sizeof(UChar); + defset->slots_size = 32 / sizeof(UInt); vassert(defset->slots_size >= 1); - defset->set = LibVEX_Alloc_inline(defset->slots_size * sizeof(UChar)); + defset->set = LibVEX_Alloc_inline(defset->slots_size * sizeof(UInt)); return defset; } @@ -2649,7 +2649,7 @@ IRTempDefSet* deepCopyIRTempDefSet(const IRTempDefSet* defset) { IRTempDefSet* defset2 = LibVEX_Alloc_inline(sizeof(IRTempDefSet)); defset2->slots_used = defset2->slots_size = defset->slots_used; - UChar* set2 = LibVEX_Alloc_inline(defset2->slots_used * sizeof(UChar)); + UInt* set2 = LibVEX_Alloc_inline(defset2->slots_used * sizeof(UInt)); for (UInt i = 0; i < defset2->slots_used; i++) { set2[i] = defset->set[i]; } @@ -3811,12 +3811,12 @@ void addIRPhiToIRPhiVec(IRPhiVec* phi_nodes, IRPhi* phi) void setIRTempDefined(IRTempDefSet* defset, IRTemp tmp) { - UInt slots_required = (tmp + sizeof(UChar)) / sizeof(UChar); + UInt slots_required = (tmp + BITS_PER_SLOT) / BITS_PER_SLOT; - if (slots_required >= defset->slots_size) { - UInt new_size = (slots_required > 2 * defset->slots_size) ? + if (slots_required > defset->slots_size) { + UInt new_size = (slots_required > 2 * defset->slots_size) ? slots_required : 2 * defset->slots_size; - UChar* new_set = LibVEX_Alloc_inline(new_size * sizeof(UChar)); + UInt* new_set = LibVEX_Alloc_inline(new_size * sizeof(UInt)); for (UInt i = 0; i < defset->slots_used; i++) { new_set[i] = defset->set[i]; } @@ -3833,8 +3833,8 @@ void setIRTempDefined(IRTempDefSet* defset, IRTemp tmp) vassert(!isIRTempDefined(defset, tmp)); - UInt mask = (1 << (tmp % sizeof(UChar))); - defset->set[tmp / sizeof(UChar)] |= mask; + UInt mask = (1 << (tmp % BITS_PER_SLOT)); + defset->set[tmp / BITS_PER_SLOT] |= mask; } void clearIRTempDefSet(IRTempDefSet* defset) diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h index af56186..73f3963 100644 --- a/VEX/pub/libvex_ir.h +++ b/VEX/pub/libvex_ir.h @@ -2761,17 +2761,19 @@ extern void addIRPhiToIRPhiVec(IRPhiVec* , IRPhi*); */ typedef struct { - UChar* set; // a bit set, use isIRTempDefined() for access - UInt slots_used; - UInt slots_size; + UInt* set; // a bit set, use isIRTempDefined() for access + UInt slots_used; + UInt slots_size; } IRTempDefSet; +#define BITS_PER_SLOT (sizeof(UInt) * 8) + static inline Bool isIRTempDefined(const IRTempDefSet* defset, IRTemp tmp) { - if ((tmp / sizeof(UChar)) < defset->slots_size) { - UInt mask = (1 << (tmp % sizeof(UChar))); - return toBool(defset->set[tmp / sizeof(UChar)] & mask); + if ((tmp / BITS_PER_SLOT) < defset->slots_size) { + UInt mask = (1 << (tmp % BITS_PER_SLOT)); + return toBool(defset->set[tmp / BITS_PER_SLOT] & mask); } return False; } |
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From: <sv...@va...> - 2017-09-02 08:33:21
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Author: iraisr Date: Sat Sep 2 09:33:13 2017 New Revision: 526 Log: Document Valgrind http mirror available at repo.or.cz. Comes handy if you are behind a firewall. Modified: trunk/downloads/repository.html Modified: trunk/downloads/repository.html ============================================================================== --- trunk/downloads/repository.html (original) +++ trunk/downloads/repository.html Sat Sep 2 09:33:13 2017 @@ -8,11 +8,12 @@ properly.</p> <p>The actively developed, current (v3.13 and later) code is in a -<a href="https://git-scm.com/">git</a> repository at sourceware.org.<br /> +<a href="https://git-scm.com/">git</a> repository +at <a href="http://sourceware.org/">sourceware.org</a>. </p> <p>If you are doing any development work, please do it using the -code from the current repository at sourceware.org!</p> +code from the current repository at <code>sourceware.org</code>!</p> <div class="hr_brown"><hr/></div> @@ -45,3 +46,13 @@ <p>To do the build, you'll need automake version 1.10 or later and a compatible version of autoconf (e.g. 2.68). These should come as standard on any non-ancient Linux distribution.</p> + +<p> +There is also an <code>http</code> mirror for the repository set up at +<code>repo.or.cz</code>. You can use it if you are behind a firewall and +cannot tunnel through with <code>socat</code>. To clone from this mirror, +do this:</p> + +<pre> + git clone http://repo.or.cz/valgrind.git +</pre> |
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From: Ivo R. <ir...@so...> - 2017-09-01 15:31:00
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https://sourceware.org/git/gitweb.cgi?p=valgrind.git;h=82b3f16a18f8f6dd5888d1e0cde7bd6c0dcef3e2 commit 82b3f16a18f8f6dd5888d1e0cde7bd6c0dcef3e2 Author: Ivo Raisr <iv...@iv...> Date: Fri Sep 1 17:27:08 2017 +0200 Small fixes to notes about Inner/Outer setup. Diff: --- README_DEVELOPERS | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/README_DEVELOPERS b/README_DEVELOPERS index ab0cf66..07a48c4 100644 --- a/README_DEVELOPERS +++ b/README_DEVELOPERS @@ -151,19 +151,18 @@ This section explains : (1) Check out 2 trees, "Inner" and "Outer". Inner runs the app directly. Outer runs Inner. -(2) Configure inner with --enable-inner and build/install as usual. +(2) Configure Inner with --enable-inner and build as usual. -(3) Configure Outer normally and build/install as usual. +(3) Configure Outer normally and build+install as usual. + Note: You must use a "make install"-ed valgrind. + Do *not* use vg-in-place for the Outer valgrind. (4) Choose a very simple program (date) and try outer/.../bin/valgrind --sim-hints=enable-outer --trace-children=yes \ --smc-check=all-non-file \ --run-libc-freeres=no --tool=cachegrind -v \ - inner/.../bin/valgrind --vgdb-prefix=./inner --tool=none -v prog - -Note: You must use a "make install"-ed valgrind. -Do *not* use vg-in-place for the outer valgrind. + inner/.../vg-in-place --vgdb-prefix=./inner --tool=none -v prog If you omit the --trace-children=yes, you'll only monitor Inner's launcher program, not its stage2. Outer needs --run-libc-freeres=no, as otherwise @@ -191,12 +190,12 @@ setup, this prefix causes the reg test diff to fail. Give --sim-hints=no-inner-prefix to the Inner to disable the production of the prefix in the stdout/stderr output of Inner. -The allocator (coregrind/m_mallocfree.c) is annotated with client requests -so Memcheck can be used to find leaks and use after free in an Inner -Valgrind. +The allocators in coregrind/m_mallocfree.c and VEX/priv/main_util.h are +annotated with client requests so Memcheck can be used to find leaks +and use after free in an Inner Valgrind. The Valgrind "big lock" is annotated with helgrind client requests -so helgrind and drd can be used to find race conditions in an Inner +so Helgrind and DRD can be used to find race conditions in an Inner Valgrind. All this has not been tested much, so don't be surprised if you hit problems. |
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From: John R. <jr...@bi...> - 2017-09-01 14:03:56
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>> If you are considering translating the entire program and caching it, I >> think that would be much faster, > > Mhm, but then you have the problem of finding all the code that is part of > the program, which is equivalent to solving the halting problem. In practice is it not that hard; I've done it twice. Transitive closure of lexical calls, using as roots the .e_entry and all the function symbols, goes a long way. The rest is covered by C++ virtual function tables (or equivalent), and recognizing the code for 'switch' statements. (Yeah, that's ugly+heuristic+compiler-dependent, but it works well enough after a few iterations.) -- |
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From: Diane M <dia...@gm...> - 2017-09-01 13:52:42
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Forgot to mention that we might be able to look up code in a cache using offsets from function symbols, rather than addresses... I still don't think this will be faster though. Diane On Fri, Sep 1, 2017 at 9:50 AM, Diane M <dia...@gm...> wrote: > Julian, > > Somehow this message wound up in my spam folder. This is a very > interesting thread. > Please see my comments below. > > On Thu, Aug 31, 2017 at 4:25 AM, Julian Seward <js...@ac...> wrote: > >> >> > > If you are considering translating the entire program and caching it, I >> > think that would be much faster, >> >> Mhm, but then you have the problem of finding all the code that is part of >> the program, which is equivalent to solving the halting problem. >> > > It depends how you go about it. Oracle's Discover does this, but it > depends upon annotations inserted > by the Studio compilers to tell it where functions start and end, when > things in the .text section are > actually not code, etc. So Discover is function-based, and Valgrind is > code block-based. Obviously > the latter is much more robust, but unfortunately, slower. > >> >> ----- >> >> For these reasons, my preference is to make the JIT faster, and ultimately >> to move to having a "two speed" JIT. That is, where code initially is >> instrumented using a fast and low quality JIT, to reduce latency and to >> gather branch and block-use statistics. When we decide a particular path >> is hot enough then those blocks are given to a slower, optimising JIT, so >> we ultimately get both low latency for cold paths and high performance for >> hot paths. This seems to be the "modern way". >> >> Also, the optimising JIT can run in a helper thread, so in effect we never >> have to wait for it, because we can just use the unoptimised version of >> a (super)block until the optimised version is ready. >> > > Those optimizing JITs can take a very long time, but I like the idea of > using the slower code while > waiting for the faster code to be optimized by a separate thread. Though > there are issues with > doing that also having to do with maintaining correct program state when > switching between the two. > > Diane > > >> >> J >> > > |
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From: Diane M <dia...@gm...> - 2017-09-01 13:51:11
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Julian, Somehow this message wound up in my spam folder. This is a very interesting thread. Please see my comments below. On Thu, Aug 31, 2017 at 4:25 AM, Julian Seward <js...@ac...> wrote: > > > If you are considering translating the entire program and caching it, I > > think that would be much faster, > > Mhm, but then you have the problem of finding all the code that is part of > the program, which is equivalent to solving the halting problem. > It depends how you go about it. Oracle's Discover does this, but it depends upon annotations inserted by the Studio compilers to tell it where functions start and end, when things in the .text section are actually not code, etc. So Discover is function-based, and Valgrind is code block-based. Obviously the latter is much more robust, but unfortunately, slower. > > ----- > > For these reasons, my preference is to make the JIT faster, and ultimately > to move to having a "two speed" JIT. That is, where code initially is > instrumented using a fast and low quality JIT, to reduce latency and to > gather branch and block-use statistics. When we decide a particular path > is hot enough then those blocks are given to a slower, optimising JIT, so > we ultimately get both low latency for cold paths and high performance for > hot paths. This seems to be the "modern way". > > Also, the optimising JIT can run in a helper thread, so in effect we never > have to wait for it, because we can just use the unoptimised version of > a (super)block until the optimised version is ready. > Those optimizing JITs can take a very long time, but I like the idea of using the slower code while waiting for the faster code to be optimized by a separate thread. Though there are issues with doing that also having to do with maintaining correct program state when switching between the two. Diane > > J > |