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From: <sv...@va...> - 2017-03-10 20:10:56
|
Author: carll
Date: Fri Mar 10 20:10:49 2017
New Revision: 16262
Log:
PowerPC: Fix incorrect register pair check for lxv, stxv, stxsd, stxssp, lxsd,
lxssp instructions
The lfdpx, stdpx, lfdp and stfdp instructions work on a register pair. The
register pair test must only be applied to these instructions in the
dis_fp_pair() function.
Updating NEWS file for the commit
VEX commit 3308 makes the fix in VEX/priv/guest_ppc_toIR.c
bugzilla 377427
Modified:
trunk/NEWS
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Fri Mar 10 20:10:49 2017
@@ -138,6 +138,7 @@
376611 ppc64 and arm64 don't know about prlimit64 syscall
376729 PPC64, remove R2 from the clobber list
== 371668
+377427 PPC64, lxv instruction failing on odd destination register
Release 3.12.0 (20 October 2016)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
From: <sv...@va...> - 2017-03-10 20:07:22
|
Author: carll
Date: Fri Mar 10 20:07:09 2017
New Revision: 3308
Log:
PowerPC: Fix incorrect register pair check for lxv, stxv, stxsd, stxssp, lxsd,
lxssp instructions
The lfdpx, stdpx, lfdp and stfdp instructions work on a register pair. The
register pair test must only be applied to these instructions in the
dis_fp_pair() function.
bugzilla 377427
Modified:
trunk/priv/guest_ppc_toIR.c
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Fri Mar 10 20:07:09 2017
@@ -11310,13 +11310,16 @@
UChar b0 = ifieldBIT0(theInstr);
Bool is_load = 0;
- if ((frT_hi_addr %2) != 0) {
- vex_printf("dis_fp_pair(ppc) : odd frT register\n");
- return False;
- }
-
switch (opc1) {
case 0x1F: // register offset
+ /* These instructions work on a pair of registers. The specified
+ * register must be even.
+ */
+ if ((frT_hi_addr %2) != 0) {
+ vex_printf("dis_fp_pair(ppc) ldpx or stdpx: odd frT register\n");
+ return False;
+ }
+
switch(opc2) {
case 0x317: // lfdpx (FP Load Double Pair X-form, ISA 2.05 p125)
DIP("ldpx fr%u,r%u,r%u\n", frT_hi_addr, rA_addr, rB_addr);
@@ -11346,6 +11349,14 @@
switch(opc2) {
case 0x0: // lfdp (FP Load Double Pair DS-form, ISA 2.05 p125)
+ /* This instruction works on a pair of registers. The specified
+ * register must be even.
+ */
+ if ((frT_hi_addr %2) != 0) {
+ vex_printf("dis_fp_pair(ppc) lfdp : odd frT register\n");
+ return False;
+ }
+
DIP("lfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr);
assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
is_load = 1;
@@ -11390,6 +11401,14 @@
switch(opc2) {
case 0x0:
// stfdp (FP Store Double Pair DS-form, ISA 2.05 p125)
+ /* This instruction works on a pair of registers. The specified
+ * register must be even.
+ */
+ if ((frT_hi_addr %2) != 0) {
+ vex_printf("dis_fp_pair(ppc) stfdp : odd frT register\n");
+ return False;
+ }
+
DIP("stfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr);
assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
break;
|