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From: <sv...@va...> - 2017-02-18 13:20:24
|
Author: mjw
Date: Sat Feb 18 13:20:16 2017
New Revision: 16228
Log:
Bug 376611 - ppc64 and arm64 don't know about prlimit64 syscall.
Modified:
trunk/NEWS
trunk/coregrind/m_syswrap/syswrap-arm64-linux.c
trunk/coregrind/m_syswrap/syswrap-ppc64-linux.c
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Sat Feb 18 13:20:16 2017
@@ -116,6 +116,7 @@
375806 Test helgrind/tests/tc22_exit_w_lock fails with glibc 2.24
376455 Solaris: unhandled syscall lgrpsys(180)
376518 Solaris: unhandled fast trap getlgrp(6)
+376611 ppc64 and arm64 don't know about prlimit64 syscall
Release 3.12.0 (20 October 2016)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Modified: trunk/coregrind/m_syswrap/syswrap-arm64-linux.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-arm64-linux.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-arm64-linux.c Sat Feb 18 13:20:16 2017
@@ -868,6 +868,7 @@
LINXY(__NR_recvmmsg, sys_recvmmsg), // 243
GENXY(__NR_wait4, sys_wait4), // 260
+ LINXY(__NR_prlimit64, sys_prlimit64), // 261
LINXY(__NR_name_to_handle_at, sys_name_to_handle_at), // 264
LINXY(__NR_open_by_handle_at, sys_open_by_handle_at), // 265
Modified: trunk/coregrind/m_syswrap/syswrap-ppc64-linux.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-ppc64-linux.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-ppc64-linux.c Sat Feb 18 13:20:16 2017
@@ -905,6 +905,7 @@
LINX_(__NR_pwritev, sys_pwritev), // 321
LINXY(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo),// 322
+ LINXY(__NR_prlimit64, sys_prlimit64), // 325
LINXY(__NR_socket, sys_socket), // 326
LINX_(__NR_bind, sys_bind), // 327
LINX_(__NR_connect, sys_connect), // 328
|
|
From: Will S. <wil...@vn...> - 2017-02-17 17:28:01
|
On ppc64*, the TOC ptr should not be considered a scratch
register, and should not be in the clobber list.
This is called out in newer GCC (i.e. gcc7) and triggers an error.
Thusly, remove R2 from the clobber list.
Signed-Off-By: Will Schmidt <wil...@vn...>
---
diff --git a/coregrind/m_debuglog.c b/coregrind/m_debuglog.c
index dc6e26d..be77680 100644
--- a/coregrind/m_debuglog.c
+++ b/coregrind/m_debuglog.c
@@ -215,7 +215,7 @@ static UInt local_sys_write_stderr ( const HChar* buf, Int n )
:
: "b" (block)
: "cc","memory","cr0","ctr",
- "r0","r2","r3","r4","r5","r6","r7","r8","r9","r10","r11","r12"
+ "r0","r3","r4","r5","r6","r7","r8","r9","r10","r11","r12"
);
if (block[0] < 0)
block[0] = -1;
@@ -231,7 +231,7 @@ static UInt local_sys_getpid ( void )
: "=&r" (__res)
: "i" (__NR_getpid)
: "cc","memory","cr0","ctr",
- "r0","r2","r4","r5","r6","r7","r8","r9","r10","r11","r12"
+ "r0","r4","r5","r6","r7","r8","r9","r10","r11","r12"
);
return (UInt)__res;
}
diff --git a/include/valgrind.h b/include/valgrind.h
index 6892007..d2e7c38 100644
--- a/include/valgrind.h
+++ b/include/valgrind.h
@@ -2708,7 +2708,7 @@ typedef
#define __CALLER_SAVED_REGS \
"lr", "ctr", "xer", \
"cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
- "r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
+ "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
"r11", "r12", "r13"
/* Macros to save and align the stack before making a function
@@ -3264,7 +3264,7 @@ typedef
#define __CALLER_SAVED_REGS \
"lr", "ctr", "xer", \
"cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
- "r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
+ "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
"r11", "r12", "r13"
/* Macros to save and align the stack before making a function
|
|
From: <sv...@va...> - 2017-02-16 18:29:54
|
Author: iraisr
Date: Thu Feb 16 18:29:46 2017
New Revision: 16227
Log:
Solaris: Add syscall wrapper for fast trap getlgrp(6)
Fixes BZ#376518.
Modified:
trunk/NEWS
trunk/coregrind/m_syswrap/syswrap-solaris.c
trunk/include/vki/vki-scnums-solaris.h
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Thu Feb 16 18:29:46 2017
@@ -115,6 +115,7 @@
for ML_(find_rx_mapping)()
375806 Test helgrind/tests/tc22_exit_w_lock fails with glibc 2.24
376455 Solaris: unhandled syscall lgrpsys(180)
+376518 Solaris: unhandled fast trap getlgrp(6)
Release 3.12.0 (20 October 2016)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Modified: trunk/coregrind/m_syswrap/syswrap-solaris.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-solaris.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-solaris.c Thu Feb 16 18:29:46 2017
@@ -1076,6 +1076,7 @@
DECL_TEMPLATE(solaris, fast_gethrtime);
DECL_TEMPLATE(solaris, fast_gethrvtime);
DECL_TEMPLATE(solaris, fast_gethrestime);
+DECL_TEMPLATE(solaris, fast_getlgrp);
#if defined(SOLARIS_GETHRT_FASTTRAP)
DECL_TEMPLATE(solaris, fast_gethrt);
#endif /* SOLARIS_GETHRT_FASTTRAP */
@@ -10674,6 +10675,13 @@
PRE_REG_READ0(long, "gethrestime");
}
+PRE(fast_getlgrp)
+{
+ /* Fasttrap number shared between gethomelgroup() and getcpuid(). */
+ PRINT("fast_getlgrp ( )");
+ PRE_REG_READ0(long, "getlgrp");
+}
+
#if defined(SOLARIS_GETHRT_FASTTRAP)
PRE(fast_gethrt)
{
@@ -11011,7 +11019,8 @@
static SyscallTableEntry fasttrap_table[] = {
SOLX_(__NR_gethrtime, fast_gethrtime), /* 3 */
SOLX_(__NR_gethrvtime, fast_gethrvtime), /* 4 */
- SOLX_(__NR_gethrestime, fast_gethrestime) /* 5 */
+ SOLX_(__NR_gethrestime, fast_gethrestime), /* 5 */
+ SOLX_(__NR_getlgrp, fast_getlgrp) /* 6 */
#if defined(SOLARIS_GETHRT_FASTTRAP)
,
SOLXY(__NR_gethrt, fast_gethrt) /* 7 */
Modified: trunk/include/vki/vki-scnums-solaris.h
==============================================================================
--- trunk/include/vki/vki-scnums-solaris.h (original)
+++ trunk/include/vki/vki-scnums-solaris.h Thu Feb 16 18:29:46 2017
@@ -28,7 +28,7 @@
The GNU General Public License is contained in the file COPYING.
*/
-/* Copyright 2013-2016, Ivo Raisr <iv...@iv...>. */
+/* Copyright 2013-2017, Ivo Raisr <iv...@iv...>. */
/* Copyright 2013, OmniTI Computer Consulting, Inc. All rights reserved. */
@@ -353,10 +353,8 @@
VG_SOLARIS_SYSCALL_CONSTRUCT_FASTTRAP(T_GETHRVTIME)
#define __NR_gethrestime \
VG_SOLARIS_SYSCALL_CONSTRUCT_FASTTRAP(T_GETHRESTIME)
-/*
#define __NR_getlgrp \
VG_SOLARIS_SYSCALL_CONSTRUCT_FASTTRAP(T_GETLGRP)
-*/
#if defined(SOLARIS_GETHRT_FASTTRAP)
#define __NR_gethrt \
VG_SOLARIS_SYSCALL_CONSTRUCT_FASTTRAP(T_GETHRT)
|
|
From: <sv...@va...> - 2017-02-15 15:22:14
|
Author: iraisr
Date: Wed Feb 15 15:22:05 2017
New Revision: 16226
Log:
Solaris: include <sys/lgrp_user_impl.h> only on newer Solaris.
Follow up to SVN r16224 and r16225, BZ#376455.
Modified:
trunk/configure.ac
trunk/include/vki/vki-solaris.h
trunk/memcheck/tests/solaris/scalar.c
Modified: trunk/configure.ac
==============================================================================
--- trunk/configure.ac (original)
+++ trunk/configure.ac Wed Feb 15 15:22:05 2017
@@ -2757,6 +2757,8 @@
#----------------------------------------------------------------------------
if test "$VGCONF_OS" = "solaris" ; then
+AC_CHECK_HEADERS([sys/lgrp_user_impl.h])
+
# Solaris-specific check determining if the Sun Studio Assembler is used to
# build Valgrind. The test checks if the x86/amd64 assembler understands the
# cmovl.l instruction, if yes then it's Sun Assembler.
Modified: trunk/include/vki/vki-solaris.h
==============================================================================
--- trunk/include/vki/vki-solaris.h (original)
+++ trunk/include/vki/vki-solaris.h Wed Feb 15 15:22:05 2017
@@ -605,10 +605,10 @@
#include <sys/lgrp_user.h>
-#define vki_lgrp_view_t lgrp_view_t
-
-
+#if defined(HAVE_SYS_LGRP_USER_IMPL_H)
+/* Include implementation specific header file on newer Solaris. */
#include <sys/lgrp_user_impl.h>
+#endif /* HAVE_SYS_LGRP_USER_IMPL_H */
#define VKI_LGRP_SYS_MEMINFO LGRP_SYS_MEMINFO
#define VKI_LGRP_SYS_GENERATION LGRP_SYS_GENERATION
#define VKI_LGRP_SYS_VERSION LGRP_SYS_VERSION
@@ -621,6 +621,7 @@
#define VKI_LGRP_SYS_AFF_INHERIT_SET LGRP_SYS_AFF_INHERIT_SET
#define VKI_LGRP_SYS_DEVICE_LGRPS LGRP_SYS_DEVICE_LGRPS
#define VKI_LGRP_SYS_MAXSOCKETS_GET LGRP_SYS_MAXSOCKETS_GET
+#define vki_lgrp_view_t lgrp_view_t
#include <sys/loadavg.h>
Modified: trunk/memcheck/tests/solaris/scalar.c
==============================================================================
--- trunk/memcheck/tests/solaris/scalar.c (original)
+++ trunk/memcheck/tests/solaris/scalar.c Wed Feb 15 15:22:05 2017
@@ -1,6 +1,7 @@
/* Basic syscall test, see memcheck/tests/x86-linux/scalar.c for more info. */
#include "scalar.h"
+#include "config.h"
#include <bsm/audit.h>
#include <nfs/nfs.h>
@@ -9,7 +10,10 @@
#include <sys/door.h>
#include <sys/fcntl.h>
#include <sys/fstyp.h>
+#include <sys/lgrp_user.h>
+#if defined(HAVE_SYS_LGRP_USER_IMPL_H)
#include <sys/lgrp_user_impl.h>
+#endif /* HAVE_SYS_LGRP_USER_IMPL_H */
#include <sys/mman.h>
#include <sys/modctl.h>
#include <sys/mount.h>
|
2017-02-14 21:33 GMT+01:00 <pa...@fr...>: >> +#include <sys/lgrp_user_impl.h> > > I think that should be > >> +#include <sys/lgrp_user.h> > > There's no _impl version on Solaris 11.3. Yes, indeed. This situation is true in Solaris 11.next (former Solaris 12). In Solaris 11.3 we still have only lgrp_user.h. I will fix that shortly. Thank you for reporting this. I. |
|
From: Knapp, R. L <ras...@in...> - 2017-02-14 22:19:24
|
Hello Julian and Valgrind developers,
We were very happy to receive your detailed response regarding this proposal. I have met with my team and the managers involved to coordinate our response to your posed questions and the process/technical points you have outlined. Our responses are inlined with [RLK] prefix. We look forward to working with Valgrind.
Best regards,
-Rashawn
-----Original Message-----
From: Julian Seward [mailto:js...@ac...]
Sent: Thursday, February 09, 2017 10:01 AM
To: Knapp, Rashawn L <ras...@in...>
Cc: val...@li...
Subject: Re: [Valgrind-developers] AVX-512 development proposal
Hi Rashawn,
Thank you for the offer of adding AVX-512 support, and sorry for the slow response. Some of the Valgrind developers discussed this briefly at Fosdem in Brussels last weekend and there was general agreement that this would be a good thing to do.
I would be happy to be a point of contact for technical and process assistance. I have both technical and process comments regarding your proposal.
>From a process point of view:
* This is likely to take several months and may involve more than one
round of review and iteration. That's based on experience from
other large chunks of instruction-set development work.
[RLK] We understand this may take several months.
* As an example, have a look the following 5 bugs, which show a staged
approach to implementation of the recent POWER ISA 3.0 extensions:
https://bugs.kde.org/show_bug.cgi?id=359767
https://bugs.kde.org/show_bug.cgi?id=361207
https://bugs.kde.org/show_bug.cgi?id=362329
https://bugs.kde.org/show_bug.cgi?id=363858
https://bugs.kde.org/show_bug.cgi?id=364948
* Patches should go on the bug tracker, as per the examples above, and
will be reviewed there.
[RLK] We will follow a staged approach, with all patches submitted on
the bug tracker.
* All contributions to the tree need to be licensed "GNU GPL 2 or
later". Are you OK with that? GPL 2-only is not possible.
[RLK] This will not be problematic.
* There is a general, although largely unstated, expectation that parties
who contribute large chunks of code continue afterwards to provide at
least some minimal level of support/bugfixing, especially around
release-time. We've had problems in the past with large bits of the
code going into the tree and the developers later simply disappearing,
and would prefer to avoid that in future. Would you be able to
provide that level of support going forward?
[RLK] Our intention is to support this; we agreed in our meeting that not
doing so may risk this work becoming deprecated.
* Similarly, there is an expectation that you have some machine which
can run nightly tests (from our framework) and send results to the
valgrind-testresults mailing list. Since none of the developers
(AFAIK) have AVX512 capable hardware, we have no other way to know
whether the support is working.
[RLK] We have internal machines for developing and testing. I will
inquire about funding options for Valgrind to invest in a machine
which Valgrind would host. We will acquaint ourselves with running nightly
tests.
* VEX is basically a mini-compiler for basic blocks. Not essential,
but it will help if your developer(s) have a bit of basic background
in compiler internals.
[RLK] We are ramping up on these skills.
Regarding your proposed implementation steps, they sound plausible.
However:
* You need a step zero, which is to extend Valgrind's HW capabilities
detection (coregrind/m_machine.c) to detect AVX512 support and tell
VEX about it. That has to happen before any insns get implemented.
[RLK] We have started with this step in our internal work thus far.
* Also, you will need to extend the implementation of XSAVE and XRSTOR
to cover the new register state. Given the inflexibility of VEX's
IR (intermediate representation), the current AVX2-level XSAVE and
XRSTOR was difficult to implement and is hard to understand, so this
is likely to be a challenge. I suggest you deal with it sooner
rather than later, since we've found that runtime libraries rely on
XSAVE and XRSTOR and so you won't be able to run any real code with
AVX512 until those two are working.
[RLK] We have started with this step in our internal work thus far.
* I assume (although you didn't say this) that you are doing this for
the 64-bit instruction set only. Our 32 bit insn set support is
essentially legacy, having stopped at SSSE3, and doesn't have a
proper prefix decoder in the same way that the 64 bit front end
does.
[RLK] Our intention was to do this for the 64-bit instructions set.
* Write test cases for the insns first, and make sure they are
comprehensive enough and work well. This reduces the general stress
and difficulty of implementing the instructions. Bear in mind that
incorrect instruction emulation can corrupt program state in a way
that isn't apparent until hundreds of millions of instructions
later, by which time it is impossible to figure out what went wrong.
So a good test suite is essential. See for example
none/tests/amd64/avx2-1.c and many others in the same directory.
[RLK] We will follow this advice; we have started with several
instructions.
* Some of the existing AVX256 insn implementations are less than
ideal, in the sense that they generate very verbose IR that performs
operations a lane at a time, rather than as a vector as a whole.
That gives rise to problems like
https://bugs.kde.org/show_bug.cgi?id=375839
The practical consequence is that (often) you won't be able to just
implement a 512-bit variant of an existing 256-bit insn by doubling
up the IR -- we'll have to do something better (wider and shallower)
here.
[RLK] We have reviewed this bug report and are seeking to implement
vector wide IRs in the future.
* If -- as seems likely -- you need to add new IROps to facilitate
this support, then you will also need to add support for them in
memcheck/mc_translate.c.
* Since you are adding register state, you'll need to futz with
memcheck/mc_machine.c too.
[RLK] We will update the memcheck files as appropriate.
* You will need to be careful to ensure that the back end provides
SIMD integer support capable of supporting Memcheck's instrumentation
of the front end's SIMD FP IR. Without that, you'll wind up in a
situation where you can run AVX512 code with the 'none' tool but not
with 'memcheck'. This is an arcane but important detail. We can
come back to it later.
[RLK] We have added this to our success metrics for this work.
J
|
----- Original Message ----- > Author: iraisr > Date: Tue Feb 14 10:35:20 2017 > New Revision: 16224 Hi Ivo > Modified: trunk/include/vki/vki-solaris.h > ============================================================================== > --- trunk/include/vki/vki-solaris.h (original) > +++ trunk/include/vki/vki-solaris.h Tue Feb 14 10:35:20 2017 > @@ -604,6 +604,21 @@ > #define vki_semid64_ds semid_ds64 > > > +#include <sys/lgrp_user_impl.h> I think that should be > +#include <sys/lgrp_user.h> There's no _impl version on Solaris 11.3. A+ Paul |
Author: iraisr
Date: Tue Feb 14 12:38:06 2017
New Revision: 16225
Log:
Solaris: Add additional subcodes for lgrpsys(180) syscall
Fixes BZ#376455.
Modified:
trunk/coregrind/m_syswrap/syswrap-solaris.c
trunk/include/vki/vki-solaris.h
trunk/memcheck/tests/solaris/scalar.c
trunk/memcheck/tests/solaris/scalar.stderr.exp
Modified: trunk/coregrind/m_syswrap/syswrap-solaris.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-solaris.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-solaris.c Tue Feb 14 12:38:06 2017
@@ -28,7 +28,7 @@
The GNU General Public License is contained in the file COPYING.
*/
-/* Copyright 2013-2016, Ivo Raisr <iv...@iv...>. */
+/* Copyright 2013-2017, Ivo Raisr <iv...@iv...>. */
/* Copyright 2015-2015, Tomas Jedlicka <jed...@gm...>. */
@@ -7517,6 +7517,25 @@
(Addr) minfo->mi_validity, SARG2 * sizeof(vki_uint_t));
}
break;
+ case VKI_LGRP_SYS_GENERATION:
+ /* Liblgrp: lgrp_gen_t lgrp_generation(lgrp_view_t view); */
+ PRINT("sys_lgrpsys ( %ld, %ld )", SARG1, SARG2);
+ PRE_REG_READ2(long, SC2("lgrpsys", "generation"), int, subcode,
+ vki_lgrp_view_t, view);
+ break;
+ case VKI_LGRP_SYS_VERSION:
+ /* Liblgrp: int lgrp_version(int version); */
+ PRINT("sys_lgrpsys ( %ld, %ld )", SARG1, SARG2);
+ PRE_REG_READ2(long, SC2("lgrpsys", "version"), int, subcode,
+ int, version);
+ break;
+ case VKI_LGRP_SYS_SNAPSHOT:
+ /* Liblgrp: int lgrp_snapshot(void *buf, size_t bufsize); */
+ PRINT("sys_lgrpsys ( %ld, %lu, %#lx )", SARG1, ARG2, ARG3);
+ PRE_REG_READ3(long, SC2("lgrpsys", "snapshot"), int, subcode,
+ vki_size_t, bufsize, void *, buf);
+ PRE_MEM_WRITE("lgrpsys(buf)", ARG3, ARG2);
+ break;
default:
VG_(unimplemented)("Syswrap of the lgrpsys call with subcode %ld.",
SARG1);
@@ -7536,6 +7555,12 @@
POST_MEM_WRITE((Addr) minfo->mi_validity, SARG2 * sizeof(vki_uint_t));
}
break;
+ case VKI_LGRP_SYS_GENERATION:
+ case VKI_LGRP_SYS_VERSION:
+ break;
+ case VKI_LGRP_SYS_SNAPSHOT:
+ POST_MEM_WRITE(ARG3, RES);
+ break;
default:
vg_assert(0);
break;
Modified: trunk/include/vki/vki-solaris.h
==============================================================================
--- trunk/include/vki/vki-solaris.h (original)
+++ trunk/include/vki/vki-solaris.h Tue Feb 14 12:38:06 2017
@@ -604,6 +604,10 @@
#define vki_semid64_ds semid_ds64
+#include <sys/lgrp_user.h>
+#define vki_lgrp_view_t lgrp_view_t
+
+
#include <sys/lgrp_user_impl.h>
#define VKI_LGRP_SYS_MEMINFO LGRP_SYS_MEMINFO
#define VKI_LGRP_SYS_GENERATION LGRP_SYS_GENERATION
Modified: trunk/memcheck/tests/solaris/scalar.c
==============================================================================
--- trunk/memcheck/tests/solaris/scalar.c (original)
+++ trunk/memcheck/tests/solaris/scalar.c Tue Feb 14 12:38:06 2017
@@ -730,6 +730,27 @@
}
__attribute__((noinline))
+static void sys_lgrpsys4(void)
+{
+ GO(SYS_lgrpsys, "(LGRP_SYS_GENERATION) 2s 0m");
+ SY(SYS_lgrpsys, x0 + LGRP_SYS_GENERATION, x0 + 0); SUCC;
+}
+
+__attribute__((noinline))
+static void sys_lgrpsys5(void)
+{
+ GO(SYS_lgrpsys, "(LGRP_SYS_VERSION) 2s 0m");
+ SY(SYS_lgrpsys, x0 + LGRP_SYS_VERSION, x0 + 0); SUCC;
+}
+
+__attribute__((noinline))
+static void sys_lgrpsys6(void)
+{
+ GO(SYS_lgrpsys, "(LGRP_SYS_SNAPSHOT) 3s 1m");
+ SY(SYS_lgrpsys, x0 + LGRP_SYS_SNAPSHOT, x0 + 10, x0 + 1); FAIL;
+}
+
+__attribute__((noinline))
static void sys_rusagesys(void)
{
GO(SYS_rusagesys, "(_RUSAGESYS_GETRUSAGE) 2s 1m");
@@ -2217,6 +2238,9 @@
sys_lgrpsys();
sys_lgrpsys2();
sys_lgrpsys3();
+ sys_lgrpsys4();
+ sys_lgrpsys5();
+ sys_lgrpsys6();
/* SYS_rusagesys 181 */
sys_rusagesys();
Modified: trunk/memcheck/tests/solaris/scalar.stderr.exp
==============================================================================
--- trunk/memcheck/tests/solaris/scalar.stderr.exp (original)
+++ trunk/memcheck/tests/solaris/scalar.stderr.exp Tue Feb 14 12:38:06 2017
@@ -2870,6 +2870,40 @@
Address 0x........ is not stack'd, malloc'd or (recently) free'd
---------------------------------------------------------
+180: SYS_lgrpsys (LGRP_SYS_GENERATION) 2s 0m
+---------------------------------------------------------
+Syscall param lgrpsys_generation(subcode) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_generation(view) contains uninitialised byte(s)
+ ...
+
+---------------------------------------------------------
+180: SYS_lgrpsys (LGRP_SYS_VERSION) 2s 0m
+---------------------------------------------------------
+Syscall param lgrpsys_version(subcode) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_version(version) contains uninitialised byte(s)
+ ...
+
+---------------------------------------------------------
+180: SYS_lgrpsys (LGRP_SYS_SNAPSHOT) 3s 1m
+---------------------------------------------------------
+Syscall param lgrpsys_snapshot(subcode) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_snapshot(bufsize) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_snapshot(buf) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys(buf) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+---------------------------------------------------------
181: SYS_rusagesys (_RUSAGESYS_GETRUSAGE) 2s 1m
---------------------------------------------------------
Syscall param rusagesys_getrusage(code) contains uninitialised byte(s)
|
Author: iraisr
Date: Tue Feb 14 10:35:20 2017
New Revision: 16224
Log:
Solaris: Add syscall wrapper for lgrpsys(180)
Fixes BZ#376455.
Modified:
trunk/NEWS
trunk/coregrind/m_syswrap/syswrap-solaris.c
trunk/include/vki/vki-scnums-solaris.h
trunk/include/vki/vki-solaris.h
trunk/memcheck/tests/solaris/scalar.c
trunk/memcheck/tests/solaris/scalar.stderr.exp
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Tue Feb 14 10:35:20 2017
@@ -114,6 +114,7 @@
375772 +1 error in get_elf_symbol_info() when computing value of 'hi' address
for ML_(find_rx_mapping)()
375806 Test helgrind/tests/tc22_exit_w_lock fails with glibc 2.24
+376455 Solaris: unhandled syscall lgrpsys(180)
Release 3.12.0 (20 October 2016)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Modified: trunk/coregrind/m_syswrap/syswrap-solaris.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-solaris.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-solaris.c Tue Feb 14 10:35:20 2017
@@ -1025,6 +1025,7 @@
DECL_TEMPLATE(solaris, sys_lwp_cond_broadcast);
DECL_TEMPLATE(solaris, sys_pread);
DECL_TEMPLATE(solaris, sys_pwrite);
+DECL_TEMPLATE(solaris, sys_lgrpsys);
DECL_TEMPLATE(solaris, sys_rusagesys);
DECL_TEMPLATE(solaris, sys_port);
DECL_TEMPLATE(solaris, sys_pollsys);
@@ -7494,6 +7495,53 @@
POST_MEM_WRITE(ARG2, RES * sizeof(vki_size_t));
}
+PRE(sys_lgrpsys)
+{
+ /* Kernel: int lgrpsys(int subcode, long ia, void *ap); */
+ switch (ARG1 /*subcode*/) {
+ case VKI_LGRP_SYS_MEMINFO:
+ PRINT("sys_lgrpsys ( %ld, %ld, %#lx )", SARG1, SARG2, ARG3);
+ PRE_REG_READ3(long, SC2("lgrpsys", "meminfo"), int, subcode,
+ int, addr_count, vki_meminfo_t *, minfo);
+ PRE_MEM_READ("lgrpsys(minfo)", ARG3, sizeof(vki_meminfo_t));
+
+ if (ML_(safe_to_deref)((vki_meminfo_t *) ARG3, sizeof(vki_meminfo_t))) {
+ vki_meminfo_t *minfo = (vki_meminfo_t *) ARG3;
+ PRE_MEM_READ("lgrpsys(minfo->mi_inaddr)",
+ (Addr) minfo->mi_inaddr, SARG2 * sizeof(vki_uint64_t));
+ PRE_MEM_READ("lgrpsys(minfo->mi_info_req)", (Addr) minfo->mi_info_req,
+ minfo->mi_info_count * sizeof(vki_uint_t));
+ PRE_MEM_WRITE("lgrpsys(minfo->mi_outdata)", (Addr) minfo->mi_outdata,
+ SARG2 * minfo->mi_info_count * sizeof(vki_uint64_t));
+ PRE_MEM_WRITE("lgrpsys(minfo->mi_validity)",
+ (Addr) minfo->mi_validity, SARG2 * sizeof(vki_uint_t));
+ }
+ break;
+ default:
+ VG_(unimplemented)("Syswrap of the lgrpsys call with subcode %ld.",
+ SARG1);
+ /*NOTREACHED*/
+ break;
+ }
+}
+
+POST(sys_lgrpsys)
+{
+ switch (ARG1 /*subcode*/) {
+ case VKI_LGRP_SYS_MEMINFO:
+ {
+ vki_meminfo_t *minfo = (vki_meminfo_t *) ARG3;
+ POST_MEM_WRITE((Addr) minfo->mi_outdata,
+ SARG2 * minfo->mi_info_count * sizeof(vki_uint64_t));
+ POST_MEM_WRITE((Addr) minfo->mi_validity, SARG2 * sizeof(vki_uint_t));
+ }
+ break;
+ default:
+ vg_assert(0);
+ break;
+ }
+}
+
PRE(sys_rusagesys)
{
/* Kernel: int rusagesys(int code, void *arg1, void *arg2,
@@ -7554,7 +7602,6 @@
vg_assert(0);
break;
}
-
}
PRE(sys_port)
@@ -10864,6 +10911,7 @@
#if defined(VGP_x86_solaris)
PLAX_(__NR_llseek, sys_llseek32), /* 175 */
#endif /* VGP_x86_solaris */
+ SOLXY(__NR_lgrpsys, sys_lgrpsys), /* 180 */
SOLXY(__NR_rusagesys, sys_rusagesys), /* 181 */
SOLXY(__NR_port, sys_port), /* 182 */
SOLXY(__NR_pollsys, sys_pollsys), /* 183 */
Modified: trunk/include/vki/vki-scnums-solaris.h
==============================================================================
--- trunk/include/vki/vki-scnums-solaris.h (original)
+++ trunk/include/vki/vki-scnums-solaris.h Tue Feb 14 10:35:20 2017
@@ -237,8 +237,7 @@
//#define __NR_brand SYS_brand
//#define __NR_kaio SYS_kaio
//#define __NR_cpc SYS_cpc
-//#define __NR_lgrpsys SYS_lgrpsys
-//#define __NR_meminfosys SYS_meminfosys /* = SYS_lgrpsys */
+#define __NR_lgrpsys SYS_lgrpsys
#define __NR_rusagesys SYS_rusagesys
#define __NR_port SYS_port
#define __NR_pollsys SYS_pollsys
Modified: trunk/include/vki/vki-solaris.h
==============================================================================
--- trunk/include/vki/vki-solaris.h (original)
+++ trunk/include/vki/vki-solaris.h Tue Feb 14 10:35:20 2017
@@ -604,6 +604,21 @@
#define vki_semid64_ds semid_ds64
+#include <sys/lgrp_user_impl.h>
+#define VKI_LGRP_SYS_MEMINFO LGRP_SYS_MEMINFO
+#define VKI_LGRP_SYS_GENERATION LGRP_SYS_GENERATION
+#define VKI_LGRP_SYS_VERSION LGRP_SYS_VERSION
+#define VKI_LGRP_SYS_SNAPSHOT LGRP_SYS_SNAPSHOT
+#define VKI_LGRP_SYS_AFFINITY_GET LGRP_SYS_AFFINITY_GET
+#define VKI_LGRP_SYS_AFFINITY_SET LGRP_SYS_AFFINITY_SET
+#define VKI_LGRP_SYS_LATENCY LGRP_SYS_LATENCY
+#define VKI_LGRP_SYS_HOME LGRP_SYS_HOME
+#define VKI_LGRP_SYS_AFF_INHERIT_GET LGRP_SYS_AFF_INHERIT_GET
+#define VKI_LGRP_SYS_AFF_INHERIT_SET LGRP_SYS_AFF_INHERIT_SET
+#define VKI_LGRP_SYS_DEVICE_LGRPS LGRP_SYS_DEVICE_LGRPS
+#define VKI_LGRP_SYS_MAXSOCKETS_GET LGRP_SYS_MAXSOCKETS_GET
+
+
#include <sys/loadavg.h>
#define VKI_LOADAVG_NSTATS LOADAVG_NSTATS
@@ -643,6 +658,8 @@
#define VKI_MC_UNLOCKAS MC_UNLOCKAS
#define VKI_MC_HAT_ADVISE MC_HAT_ADVISE
+#define vki_meminfo_t meminfo_t
+
#include <sys/mntio.h>
#define VKI_MNTIOC_GETEXTMNTENT MNTIOC_GETEXTMNTENT
Modified: trunk/memcheck/tests/solaris/scalar.c
==============================================================================
--- trunk/memcheck/tests/solaris/scalar.c (original)
+++ trunk/memcheck/tests/solaris/scalar.c Tue Feb 14 10:35:20 2017
@@ -9,6 +9,7 @@
#include <sys/door.h>
#include <sys/fcntl.h>
#include <sys/fstyp.h>
+#include <sys/lgrp_user_impl.h>
#include <sys/mman.h>
#include <sys/modctl.h>
#include <sys/mount.h>
@@ -701,6 +702,34 @@
}
__attribute__((noinline))
+static void sys_lgrpsys(void)
+{
+ GO(SYS_lgrpsys, "(LGRP_SYS_MEMINFO) 3s 1m");
+ SY(SYS_lgrpsys, x0 + LGRP_SYS_MEMINFO, x0 + 0, x0 + 1); FAIL;
+}
+
+__attribute__((noinline))
+static void sys_lgrpsys2(void)
+{
+ GO(SYS_lgrpsys, "(LGRP_SYS_MEMINFO) 3s 1m");
+ SY(SYS_lgrpsys, x0 + LGRP_SYS_MEMINFO, x0 + 1, x0 + 1); FAIL;
+}
+
+__attribute__((noinline))
+static void sys_lgrpsys3(void)
+{
+ meminfo_t minfo;
+ minfo.mi_inaddr = (void *)(x0 + 1);
+ minfo.mi_info_req = (void *)(x0 + 1);
+ minfo.mi_info_count = x0 + 1;
+ minfo.mi_outdata = (void *)(x0 + 1);
+ minfo.mi_validity = (void *)(x0 + 1);
+
+ GO(SYS_lgrpsys, "(LGRP_SYS_MEMINFO) 4s 4m");
+ SY(SYS_lgrpsys, x0 + LGRP_SYS_MEMINFO, x0 + 1, x0 + &minfo); FAIL;
+}
+
+__attribute__((noinline))
static void sys_rusagesys(void)
{
GO(SYS_rusagesys, "(_RUSAGESYS_GETRUSAGE) 2s 1m");
@@ -2185,7 +2214,9 @@
/* XXX Missing wrapper. */
/* SYS_lgrpsys 180 */
- /* XXX Missing wrapper. */
+ sys_lgrpsys();
+ sys_lgrpsys2();
+ sys_lgrpsys3();
/* SYS_rusagesys 181 */
sys_rusagesys();
Modified: trunk/memcheck/tests/solaris/scalar.stderr.exp
==============================================================================
--- trunk/memcheck/tests/solaris/scalar.stderr.exp (original)
+++ trunk/memcheck/tests/solaris/scalar.stderr.exp Tue Feb 14 10:35:20 2017
@@ -2806,6 +2806,70 @@
Address 0x........ is not stack'd, malloc'd or (recently) free'd
---------------------------------------------------------
+180: SYS_lgrpsys (LGRP_SYS_MEMINFO) 3s 1m
+---------------------------------------------------------
+Syscall param lgrpsys_meminfo(subcode) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_meminfo(addr_count) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_meminfo(minfo) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys(minfo) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+---------------------------------------------------------
+180: SYS_lgrpsys (LGRP_SYS_MEMINFO) 3s 1m
+---------------------------------------------------------
+Syscall param lgrpsys_meminfo(subcode) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_meminfo(addr_count) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_meminfo(minfo) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys(minfo) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+---------------------------------------------------------
+180: SYS_lgrpsys (LGRP_SYS_MEMINFO) 4s 4m
+---------------------------------------------------------
+Syscall param lgrpsys_meminfo(subcode) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_meminfo(addr_count) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys_meminfo(minfo) contains uninitialised byte(s)
+ ...
+
+Syscall param lgrpsys(minfo) points to uninitialised byte(s)
+ ...
+ Address 0x........ is on thread 1's stack
+
+Syscall param lgrpsys(minfo->mi_inaddr) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param lgrpsys(minfo->mi_info_req) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param lgrpsys(minfo->mi_outdata) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+Syscall param lgrpsys(minfo->mi_validity) points to unaddressable byte(s)
+ ...
+ Address 0x........ is not stack'd, malloc'd or (recently) free'd
+
+---------------------------------------------------------
181: SYS_rusagesys (_RUSAGESYS_GETRUSAGE) 2s 1m
---------------------------------------------------------
Syscall param rusagesys_getrusage(code) contains uninitialised byte(s)
|
|
From: <sv...@va...> - 2017-02-13 18:06:17
|
Author: petarj
Date: Mon Feb 13 18:06:10 2017
New Revision: 16223
Log:
add none/tests/linux/clonev to svn:ignore list
add clonev to the svn:ignore list, for the sake of tidiness.
Modified:
trunk/none/tests/linux/ (props changed)
|
|
From: <sv...@va...> - 2017-02-13 16:15:32
|
Author: petarj
Date: Mon Feb 13 16:15:24 2017
New Revision: 3304
Log:
mips64: do correct 32-bit comparison for Iop_CmpNE32
Make sure that we take into account 32-bit size of values in comparison
on MIPS64-platforms. This is done either by sign extending these values
before comparison or sign extending xored values (depending on what
comparison we do). This should avoid false-positives like the one
reported in BZ #341481.
Patch based on code provided by Crestez Dan Leonard and Tamara Vlahovic.
Modified:
trunk/priv/host_mips_defs.c
trunk/priv/host_mips_isel.c
Modified: trunk/priv/host_mips_defs.c
==============================================================================
--- trunk/priv/host_mips_defs.c (original)
+++ trunk/priv/host_mips_defs.c Mon Feb 13 16:15:24 2017
@@ -1584,8 +1584,15 @@
addHRegUse(u, HRmWrite, i->Min.Shft.dst);
return;
case Min_Cmp:
- addHRegUse(u, HRmRead, i->Min.Cmp.srcL);
- addHRegUse(u, HRmRead, i->Min.Cmp.srcR);
+ if (i->Min.Cmp.sz32 && mode64 &&
+ (i->Min.Cmp.cond != MIPScc_EQ) &&
+ (i->Min.Cmp.cond != MIPScc_NE)) {
+ addHRegUse(u, HRmModify, i->Min.Cmp.srcL);
+ addHRegUse(u, HRmModify, i->Min.Cmp.srcR);
+ } else {
+ addHRegUse(u, HRmRead, i->Min.Cmp.srcL);
+ addHRegUse(u, HRmRead, i->Min.Cmp.srcR);
+ }
addHRegUse(u, HRmWrite, i->Min.Cmp.dst);
return;
case Min_Unary:
@@ -2754,35 +2761,68 @@
UInt r_srcL = iregNo(i->Min.Cmp.srcL, mode64);
UInt r_srcR = iregNo(i->Min.Cmp.srcR, mode64);
UInt r_dst = iregNo(i->Min.Cmp.dst, mode64);
+ Bool sz32 = i->Min.Cmp.sz32;
switch (i->Min.Cmp.cond) {
case MIPScc_EQ:
/* xor r_dst, r_srcL, r_srcR
sltiu r_dst, r_dst, 1 */
p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 38);
+ if (mode64 && sz32) {
+ /* sll r_dst, r_dst, 0 */
+ p = mkFormS(p, 0, r_dst, 0, r_dst, 0, 0);
+ }
p = mkFormI(p, 11, r_dst, r_dst, 1);
break;
case MIPScc_NE:
/* xor r_dst, r_srcL, r_srcR
sltu r_dst, zero, r_dst */
p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 38);
+ if (mode64 && sz32) {
+ /* sll r_dst, r_dst, 0 */
+ p = mkFormS(p, 0, r_dst, 0, r_dst, 0, 0);
+ }
p = mkFormR(p, 0, 0, r_dst, r_dst, 0, 43);
break;
case MIPScc_LT:
+ if (mode64 && sz32) {
+ /* sll r_srcL, r_srcL, 0
+ sll r_srcR, r_srcR, 0 */
+ p = mkFormS(p, 0, r_srcL, 0, r_srcL, 0, 0);
+ p = mkFormS(p, 0, r_srcR, 0, r_srcR, 0, 0);
+ }
/* slt r_dst, r_srcL, r_srcR */
p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 42);
break;
case MIPScc_LO:
+ if (mode64 && sz32) {
+ /* sll r_srcL, r_srcL, 0
+ sll r_srcR, r_srcR, 0 */
+ p = mkFormS(p, 0, r_srcL, 0, r_srcL, 0, 0);
+ p = mkFormS(p, 0, r_srcR, 0, r_srcR, 0, 0);
+ }
/* sltu r_dst, r_srcL, r_srcR */
p = mkFormR(p, 0, r_srcL, r_srcR, r_dst, 0, 43);
break;
case MIPScc_LE:
+ if (mode64 && sz32) {
+ /* sll r_srcL, r_srcL, 0
+ sll r_srcR, r_srcR, 0 */
+ p = mkFormS(p, 0, r_srcL, 0, r_srcL, 0, 0);
+ p = mkFormS(p, 0, r_srcR, 0, r_srcR, 0, 0);
+ }
/* slt r_dst, r_srcR, r_srcL
xori r_dst, r_dst, 1 */
p = mkFormR(p, 0, r_srcR, r_srcL, r_dst, 0, 42);
p = mkFormI(p, 14, r_dst, r_dst, 1);
break;
case MIPScc_LS:
+ if (mode64 && sz32) {
+ /* sll r_srcL, r_srcL, 0
+ sll r_srcR, r_srcR, 0 */
+ p = mkFormS(p, 0, r_srcL, 0, r_srcL, 0, 0);
+ p = mkFormS(p, 0, r_srcR, 0, r_srcR, 0, 0);
+ }
/* sltu r_dst, rsrcR, r_srcL
xori r_dsr, r_dst, 1 */
p = mkFormR(p, 0, r_srcR, r_srcL, r_dst, 0, 43);
Modified: trunk/priv/host_mips_isel.c
==============================================================================
--- trunk/priv/host_mips_isel.c (original)
+++ trunk/priv/host_mips_isel.c Mon Feb 13 16:15:24 2017
@@ -1000,7 +1000,7 @@
break;
case Iop_CmpNE64:
cc = MIPScc_NE;
- size32 = True;
+ size32 = False;
break;
case Iop_CmpLT32S:
cc = MIPScc_LT;
@@ -2080,7 +2080,7 @@
break;
case Iop_CmpNE64:
cc = MIPScc_NE;
- size32 = True;
+ size32 = False;
break;
case Iop_CmpLT32S:
cc = MIPScc_LT;
|
|
From: Petar J. <mip...@gm...> - 2017-02-11 11:05:27
|
Tom has just fixed it (r3301), before I had a chance to commit my fix.
Sorry about the breakage.
Regards,
Petar
On Sat, Feb 11, 2017 at 8:12 AM, <pa...@fr...> wrote:
> Hi
>
> I'm getting build breakage with this change.
>
> ----- Original Message -----
>> Author: petarj
>> Date: Fri Feb 10 17:58:40 2017
>> New Revision: 3300
>>
>> Log:
>> mips: rewrite mips_irgen_load_and_add32|64 and code around it
>>
>> Make sure that mips_irgen_load_and_add32 gets both expected value and
>> new value, so the function code makes more sense and does load/store
>> in
>> a atomic way.
>>
>> Minor renaming and code style issues added too.
>>
>> Patch by Tamara Vlahovic.
>>
>> Modified:
>> trunk/priv/guest_mips_toIR.c
>>
>> Modified: trunk/priv/guest_mips_toIR.c
>> ==============================================================================
>> --- trunk/priv/guest_mips_toIR.c (original)
>> +++ trunk/priv/guest_mips_toIR.c Fri Feb 10 17:58:40 2017
>> @@ -2187,17 +2187,19 @@
>> }
>>
>> /* Based on s390_irgen_load_and_add32. */
>> -static void mips_irgen_load_and_add32(IRTemp op1addr, IRTemp
>> new_val,
>> - UChar rd, Bool putIntoRd)
>> +static void mips_load_store32(IRTemp op1addr, IRTemp new_val,
>> + IRTemp expd, UChar rd, Bool putIntoRd)
>> {
>> IRCAS *cas;
>> IRTemp old_mem = newTemp(Ity_I32);
>> - IRTemp expd = newTemp(Ity_I32);
>> -
>> - assign(expd, load(Ity_I32, mkexpr(op1addr)));
>> + IRType ty = mode64 ? Ity_I64 : Ity_I32;
>>
>> cas = mkIRCAS(IRTemp_INVALID, old_mem,
>> - Iend_LE, mkexpr(op1addr),
>> +#if defined (_MIPSEL)
>> + Iend_LE, mkexpr(op1addr),
>> +#elif defined (_MIPSEB)
>> + Iend_BE, mkexpr(op1addr),
>> +#endif
>
>
> As far as I can see, _MIPSEL and _MIPSEB and gcc builtin macros for the MIPS platform. The problem is that neither is defined on other platforms. This means that neither #if nor #elif is true, which causes the two arguments to me missing (see below).
>
> Shouldn't this be
>
> #if defined (_MIPSEL)
> Iend_LE, mkexpr(op1addr),
> #else
> Iend_BE, mkexpr(op1addr),
> #endif
>
> (perhaps the condition the other way round).
>
> A+
> Paul
>
>
> gcc -DHAVE_CONFIG_H -I. -I.. -I.. -I../include -I../VEX/pub -I../VEX/pub -DVGA_amd64=1 -DVGO_linux=1 -DVGP_amd64_linux=1 -DVGPV_amd64_linux_vanilla=1 -Ipriv -m64 -O2 -g -std=gnu99 -Wall -Wmissing-prototypes -Wshadow -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations -Wcast-align -Wcast-qual -Wwrite-strings -Wempty-body -Wformat -Wformat-security -Wignored-qualifiers -Wmissing-parameter-type -Wold-style-declaration -fno-stack-protector -fno-strict-aliasing -fno-builtin -fomit-frame-pointer -Wbad-function-cast -fstrict-aliasing -MT priv/libvex_amd64_linux_a-guest_mips_toIR.o -MD -MP -MF priv/.deps/libvex_amd64_linux_a-guest_mips_toIR.Tpo -c -o priv/libvex_amd64_linux_a-guest_mips_toIR.o `test -f 'priv/guest_mips_toIR.c' || echo './'`priv/guest_mips_toIR.c
> In file included from priv/guest_mips_toIR.c:39:0:
> priv/guest_mips_toIR.c: In function ‘mips_load_store32’:
> priv/main_util.h:44:14: error: incompatible type for argument 3 of ‘mkIRCAS’
> #define NULL ((void*)0)
> ^
> priv/guest_mips_toIR.c:2203:18: note: in expansion of macro ‘NULL’
> NULL, mkexpr(expd), /* expected value */
> ^~~~
> In file included from priv/guest_mips_toIR.c:34:0:
> ../VEX/pub/libvex_ir.h:2584:15: note: expected ‘IREndness {aka enum <anonymous>}’ but argument is of type ‘void *’
> extern IRCAS* mkIRCAS ( IRTemp oldHi, IRTemp oldLo,
> ^~~~~~~
> priv/guest_mips_toIR.c:2197:10: error: too few arguments to function ‘mkIRCAS’
> cas = mkIRCAS(IRTemp_INVALID, old_mem,
> ^~~~~~~
> In file included from priv/guest_mips_toIR.c:34:0:
> ../VEX/pub/libvex_ir.h:2584:15: note: declared here
> extern IRCAS* mkIRCAS ( IRTemp oldHi, IRTemp oldLo,
>
>
>
> ------------------------------------------------------------------------------
> Check out the vibrant tech community on one of the world's most
> engaging tech sites, SlashDot.org! http://sdm.link/slashdot
> _______________________________________________
> Valgrind-developers mailing list
> Val...@li...
> https://lists.sourceforge.net/lists/listinfo/valgrind-developers
|
|
From: <sv...@va...> - 2017-02-11 10:47:04
|
Author: tom
Date: Sat Feb 11 10:46:57 2017
New Revision: 3303
Log:
Add comment about HINT instructions.
Modified:
trunk/priv/guest_arm64_toIR.c
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Sat Feb 11 10:46:57 2017
@@ -7025,6 +7025,9 @@
/* -------------------- HINT ------------------- */
/* 31 23 15 11 4 3
1101 0101 0000 0011 0010 imm7 1 1111
+ Catch otherwise unhandled HINT instructions - any
+ like YIELD which are explicitly handled should go
+ above this case.
*/
if (INSN(31,24) == BITS8(1,1,0,1,0,1,0,1)
&& INSN(23,16) == BITS8(0,0,0,0,0,0,1,1)
|
|
From: <sv...@va...> - 2017-02-11 10:46:08
|
Author: tom
Date: Sat Feb 11 10:46:02 2017
New Revision: 16222
Log:
Document BZ#376279
Modified:
trunk/docs/internals/3_12_BUGSTATUS.txt
Modified: trunk/docs/internals/3_12_BUGSTATUS.txt
==============================================================================
--- trunk/docs/internals/3_12_BUGSTATUS.txt (original)
+++ trunk/docs/internals/3_12_BUGSTATUS.txt Sat Feb 11 10:46:02 2017
@@ -48,6 +48,8 @@
=== VEX/arm64 ==========================================================
+376279 disInstr(arm64): unhandled instruction 0xD50320FF
+
=== VEX/x86 ============================================================
=== VEX/mips ===========================================================
|
|
From: <sv...@va...> - 2017-02-11 10:44:36
|
Author: tom
Date: Sat Feb 11 10:44:29 2017
New Revision: 3302
Log:
Handle unknown HINT instructions on aarch64 by ignoring them. BZ#376279.
Modified:
trunk/priv/guest_arm64_toIR.c
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Sat Feb 11 10:44:29 2017
@@ -7022,6 +7022,19 @@
return True;
}
+ /* -------------------- HINT ------------------- */
+ /* 31 23 15 11 4 3
+ 1101 0101 0000 0011 0010 imm7 1 1111
+ */
+ if (INSN(31,24) == BITS8(1,1,0,1,0,1,0,1)
+ && INSN(23,16) == BITS8(0,0,0,0,0,0,1,1)
+ && INSN(15,12) == BITS4(0,0,1,0)
+ && INSN(4,0) == BITS5(1,1,1,1,1)) {
+ UInt imm7 = INSN(11,5);
+ DIP("hint #%u\n", imm7);
+ return True;
+ }
+
/* ------------------- CLREX ------------------ */
/* 31 23 15 11 7
1101 0101 0000 0011 0011 m 0101 1111 CLREX CRm
|
|
From: <sv...@va...> - 2017-02-11 10:40:55
|
Author: tom
Date: Sat Feb 11 10:40:48 2017
New Revision: 3301
Log:
Fix non-mips build breakage from VEX r3300
Modified:
trunk/priv/guest_mips_toIR.c
Modified: trunk/priv/guest_mips_toIR.c
==============================================================================
--- trunk/priv/guest_mips_toIR.c (original)
+++ trunk/priv/guest_mips_toIR.c Sat Feb 11 10:40:48 2017
@@ -2196,9 +2196,9 @@
cas = mkIRCAS(IRTemp_INVALID, old_mem,
#if defined (_MIPSEL)
- Iend_LE, mkexpr(op1addr),
-#elif defined (_MIPSEB)
- Iend_BE, mkexpr(op1addr),
+ Iend_LE, mkexpr(op1addr),
+#else /* _MIPSEB */
+ Iend_BE, mkexpr(op1addr),
#endif
NULL, mkexpr(expd), /* expected value */
NULL, mkexpr(new_val) /* new value */);
@@ -2220,9 +2220,9 @@
vassert(mode64);
cas = mkIRCAS(IRTemp_INVALID, old_mem,
#if defined (_MIPSEL)
- Iend_LE, mkexpr(op1addr),
-#elif defined (_MIPSEB)
- Iend_BE, mkexpr(op1addr),
+ Iend_LE, mkexpr(op1addr),
+#else /* _MIPSEB */
+ Iend_BE, mkexpr(op1addr),
#endif
NULL, mkexpr(expd), /* expected value */
NULL, mkexpr(new_val) /* new value */);
|
|
From: <pa...@fr...> - 2017-02-11 07:12:57
|
Hi
I'm getting build breakage with this change.
----- Original Message -----
> Author: petarj
> Date: Fri Feb 10 17:58:40 2017
> New Revision: 3300
>
> Log:
> mips: rewrite mips_irgen_load_and_add32|64 and code around it
>
> Make sure that mips_irgen_load_and_add32 gets both expected value and
> new value, so the function code makes more sense and does load/store
> in
> a atomic way.
>
> Minor renaming and code style issues added too.
>
> Patch by Tamara Vlahovic.
>
> Modified:
> trunk/priv/guest_mips_toIR.c
>
> Modified: trunk/priv/guest_mips_toIR.c
> ==============================================================================
> --- trunk/priv/guest_mips_toIR.c (original)
> +++ trunk/priv/guest_mips_toIR.c Fri Feb 10 17:58:40 2017
> @@ -2187,17 +2187,19 @@
> }
>
> /* Based on s390_irgen_load_and_add32. */
> -static void mips_irgen_load_and_add32(IRTemp op1addr, IRTemp
> new_val,
> - UChar rd, Bool putIntoRd)
> +static void mips_load_store32(IRTemp op1addr, IRTemp new_val,
> + IRTemp expd, UChar rd, Bool putIntoRd)
> {
> IRCAS *cas;
> IRTemp old_mem = newTemp(Ity_I32);
> - IRTemp expd = newTemp(Ity_I32);
> -
> - assign(expd, load(Ity_I32, mkexpr(op1addr)));
> + IRType ty = mode64 ? Ity_I64 : Ity_I32;
>
> cas = mkIRCAS(IRTemp_INVALID, old_mem,
> - Iend_LE, mkexpr(op1addr),
> +#if defined (_MIPSEL)
> + Iend_LE, mkexpr(op1addr),
> +#elif defined (_MIPSEB)
> + Iend_BE, mkexpr(op1addr),
> +#endif
As far as I can see, _MIPSEL and _MIPSEB and gcc builtin macros for the MIPS platform. The problem is that neither is defined on other platforms. This means that neither #if nor #elif is true, which causes the two arguments to me missing (see below).
Shouldn't this be
#if defined (_MIPSEL)
Iend_LE, mkexpr(op1addr),
#else
Iend_BE, mkexpr(op1addr),
#endif
(perhaps the condition the other way round).
A+
Paul
gcc -DHAVE_CONFIG_H -I. -I.. -I.. -I../include -I../VEX/pub -I../VEX/pub -DVGA_amd64=1 -DVGO_linux=1 -DVGP_amd64_linux=1 -DVGPV_amd64_linux_vanilla=1 -Ipriv -m64 -O2 -g -std=gnu99 -Wall -Wmissing-prototypes -Wshadow -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations -Wcast-align -Wcast-qual -Wwrite-strings -Wempty-body -Wformat -Wformat-security -Wignored-qualifiers -Wmissing-parameter-type -Wold-style-declaration -fno-stack-protector -fno-strict-aliasing -fno-builtin -fomit-frame-pointer -Wbad-function-cast -fstrict-aliasing -MT priv/libvex_amd64_linux_a-guest_mips_toIR.o -MD -MP -MF priv/.deps/libvex_amd64_linux_a-guest_mips_toIR.Tpo -c -o priv/libvex_amd64_linux_a-guest_mips_toIR.o `test -f 'priv/guest_mips_toIR.c' || echo './'`priv/guest_mips_toIR.c
In file included from priv/guest_mips_toIR.c:39:0:
priv/guest_mips_toIR.c: In function ‘mips_load_store32’:
priv/main_util.h:44:14: error: incompatible type for argument 3 of ‘mkIRCAS’
#define NULL ((void*)0)
^
priv/guest_mips_toIR.c:2203:18: note: in expansion of macro ‘NULL’
NULL, mkexpr(expd), /* expected value */
^~~~
In file included from priv/guest_mips_toIR.c:34:0:
../VEX/pub/libvex_ir.h:2584:15: note: expected ‘IREndness {aka enum <anonymous>}’ but argument is of type ‘void *’
extern IRCAS* mkIRCAS ( IRTemp oldHi, IRTemp oldLo,
^~~~~~~
priv/guest_mips_toIR.c:2197:10: error: too few arguments to function ‘mkIRCAS’
cas = mkIRCAS(IRTemp_INVALID, old_mem,
^~~~~~~
In file included from priv/guest_mips_toIR.c:34:0:
../VEX/pub/libvex_ir.h:2584:15: note: declared here
extern IRCAS* mkIRCAS ( IRTemp oldHi, IRTemp oldLo,
|
|
From: <sv...@va...> - 2017-02-10 17:58:48
|
Author: petarj
Date: Fri Feb 10 17:58:40 2017
New Revision: 3300
Log:
mips: rewrite mips_irgen_load_and_add32|64 and code around it
Make sure that mips_irgen_load_and_add32 gets both expected value and
new value, so the function code makes more sense and does load/store in
a atomic way.
Minor renaming and code style issues added too.
Patch by Tamara Vlahovic.
Modified:
trunk/priv/guest_mips_toIR.c
Modified: trunk/priv/guest_mips_toIR.c
==============================================================================
--- trunk/priv/guest_mips_toIR.c (original)
+++ trunk/priv/guest_mips_toIR.c Fri Feb 10 17:58:40 2017
@@ -2187,17 +2187,19 @@
}
/* Based on s390_irgen_load_and_add32. */
-static void mips_irgen_load_and_add32(IRTemp op1addr, IRTemp new_val,
- UChar rd, Bool putIntoRd)
+static void mips_load_store32(IRTemp op1addr, IRTemp new_val,
+ IRTemp expd, UChar rd, Bool putIntoRd)
{
IRCAS *cas;
IRTemp old_mem = newTemp(Ity_I32);
- IRTemp expd = newTemp(Ity_I32);
-
- assign(expd, load(Ity_I32, mkexpr(op1addr)));
+ IRType ty = mode64 ? Ity_I64 : Ity_I32;
cas = mkIRCAS(IRTemp_INVALID, old_mem,
- Iend_LE, mkexpr(op1addr),
+#if defined (_MIPSEL)
+ Iend_LE, mkexpr(op1addr),
+#elif defined (_MIPSEB)
+ Iend_BE, mkexpr(op1addr),
+#endif
NULL, mkexpr(expd), /* expected value */
NULL, mkexpr(new_val) /* new value */);
stmt(IRStmt_CAS(cas));
@@ -2206,21 +2208,22 @@
Otherwise, it did not */
jump_back(binop(Iop_CmpNE32, mkexpr(old_mem), mkexpr(expd)));
if (putIntoRd)
- putIReg(rd, mkWidenFrom32(Ity_I64, mkexpr(old_mem), True));
+ putIReg(rd, mkWidenFrom32(ty, mkexpr(old_mem), True));
}
/* Based on s390_irgen_load_and_add64. */
-static void mips_irgen_load_and_add64(IRTemp op1addr, IRTemp new_val,
- UChar rd, Bool putIntoRd)
+static void mips_load_store64(IRTemp op1addr, IRTemp new_val,
+ IRTemp expd, UChar rd, Bool putIntoRd)
{
IRCAS *cas;
IRTemp old_mem = newTemp(Ity_I64);
- IRTemp expd = newTemp(Ity_I64);
-
- assign(expd, load(Ity_I64, mkexpr(op1addr)));
-
+ vassert(mode64);
cas = mkIRCAS(IRTemp_INVALID, old_mem,
- Iend_LE, mkexpr(op1addr),
+#if defined (_MIPSEL)
+ Iend_LE, mkexpr(op1addr),
+#elif defined (_MIPSEB)
+ Iend_BE, mkexpr(op1addr),
+#endif
NULL, mkexpr(expd), /* expected value */
NULL, mkexpr(new_val) /* new value */);
stmt(IRStmt_CAS(cas));
@@ -2267,12 +2270,14 @@
case 0x18: { /* Store Atomic Add Word - SAA; Cavium OCTEON */
DIP("saa r%u, (r%u)", regRt, regRs);
IRTemp addr = newTemp(Ity_I64);
- IRTemp new = newTemp(Ity_I32);
- assign (addr, getIReg(regRs));
- assign(new, binop(Iop_Add32,
- load(Ity_I32, mkexpr(addr)),
- mkNarrowTo32(ty, getIReg(regRt))));
- mips_irgen_load_and_add32(addr, new, 0, False);
+ IRTemp new_val = newTemp(Ity_I32);
+ IRTemp old = newTemp(Ity_I32);
+ assign(addr, getIReg(regRs));
+ assign(old, load(Ity_I32, mkexpr(addr)));
+ assign(new_val, binop(Iop_Add32,
+ mkexpr(old),
+ mkNarrowTo32(ty, getIReg(regRt))));
+ mips_load_store32(addr, new_val, old, 0, False);
break;
}
@@ -2280,12 +2285,14 @@
case 0x19: {
DIP( "saad r%u, (r%u)", regRt, regRs);
IRTemp addr = newTemp(Ity_I64);
- IRTemp new = newTemp(Ity_I64);
- assign (addr, getIReg(regRs));
- assign(new, binop(Iop_Add64,
- load(Ity_I64, mkexpr(addr)),
- getIReg(regRt)));
- mips_irgen_load_and_add64(addr, new, 0, False);
+ IRTemp new_val = newTemp(Ity_I64);
+ IRTemp old = newTemp(Ity_I64);
+ assign(addr, getIReg(regRs));
+ assign(old, load(Ity_I64, mkexpr(addr)));
+ assign(new_val, binop(Iop_Add64,
+ mkexpr(old),
+ getIReg(regRt)));
+ mips_load_store64(addr, new_val, old, 0, False);
break;
}
@@ -2298,121 +2305,145 @@
/* Load Atomic Increment Word - LAI; Cavium OCTEON2 */
case 0x02: {
DIP("lai r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I32);
+ IRTemp new_val = newTemp(Ity_I32);
+ IRTemp old = newTemp(Ity_I32);
assign(addr, getIReg(regRs));
- assign(new, binop(Iop_Add32,
- load(Ity_I32, mkexpr(addr)),
- mkU32(1)));
- mips_irgen_load_and_add32(addr, new, regRd, True);
+ assign(old, load(Ity_I32, mkexpr(addr)));
+ assign(new_val, binop(Iop_Add32,
+ mkexpr(old),
+ mkU32(1)));
+ mips_load_store32(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Increment Doubleword - LAID; Cavium OCTEON2 */
case 0x03: {
DIP("laid r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I64);
+ IRTemp new_val = newTemp(Ity_I64);
+ IRTemp old = newTemp(Ity_I64);
assign(addr, getIReg(regRs));
- assign(new, binop(Iop_Add64,
- load(Ity_I64, mkexpr(addr)),
- mkU64(1)));
- mips_irgen_load_and_add64(addr, new, regRd, True);
+ assign(old, load(Ity_I64, mkexpr(addr)));
+ assign(new_val, binop(Iop_Add64,
+ mkexpr(old),
+ mkU64(1)));
+ mips_load_store64(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Decrement Word - LAD; Cavium OCTEON2 */
case 0x06: {
DIP("lad r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I32);
+ IRTemp new_val = newTemp(Ity_I32);
+ IRTemp old = newTemp(Ity_I32);
assign(addr, getIReg(regRs));
- assign(new, binop(Iop_Sub32,
- load(Ity_I32, mkexpr(addr)),
- mkU32(1)));
- mips_irgen_load_and_add32(addr, new, regRd, True);
+ assign(old, load(Ity_I32, mkexpr(addr)));
+ assign(new_val, binop(Iop_Sub32,
+ mkexpr(old),
+ mkU32(1)));
+ mips_load_store32(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Decrement Doubleword - LADD; Cavium OCTEON2 */
case 0x07: {
DIP("ladd r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I64);
- assign (addr, getIReg(regRs));
- assign(new, binop(Iop_Sub64,
- load(Ity_I64, mkexpr(addr)),
- mkU64(1)));
- mips_irgen_load_and_add64(addr, new, regRd, True);
+ IRTemp new_val = newTemp(Ity_I64);
+ IRTemp old = newTemp(Ity_I64);
+ assign(addr, getIReg(regRs));
+ assign(old, load(Ity_I64, mkexpr(addr)));
+ assign(new_val, binop(Iop_Sub64,
+ mkexpr(old),
+ mkU64(1)));
+ mips_load_store64(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Set Word - LAS; Cavium OCTEON2 */
case 0x0a: {
DIP("las r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I32);
+ IRTemp new_val = newTemp(Ity_I32);
+ IRTemp old = newTemp(Ity_I32);
assign(addr, getIReg(regRs));
- assign(new, mkU32(0xffffffff));
- mips_irgen_load_and_add32(addr, new, regRd, True);
+ assign(new_val, mkU32(0xffffffff));
+ assign(old, load(Ity_I32, mkexpr(addr)));
+ mips_load_store32(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Set Doubleword - LASD; Cavium OCTEON2 */
case 0x0b: {
DIP("lasd r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I64);
- assign (addr, getIReg(regRs));
- assign(new, mkU64(0xffffffffffffffffULL));
- mips_irgen_load_and_add64(addr, new, regRd, True);
+ IRTemp new_val = newTemp(Ity_I64);
+ IRTemp old = newTemp(Ity_I64);
+ assign(addr, getIReg(regRs));
+ assign(new_val, mkU64(0xffffffffffffffffULL));
+ assign(old, load(Ity_I64, mkexpr(addr)));
+ mips_load_store64(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Clear Word - LAC; Cavium OCTEON2 */
case 0x0e: {
DIP("lac r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I32);
- assign (addr, getIReg(regRs));
- assign(new, mkU32(0));
- mips_irgen_load_and_add32(addr, new, regRd, True);
+ IRTemp new_val = newTemp(Ity_I32);
+ IRTemp old = newTemp(Ity_I32);
+ assign(addr, getIReg(regRs));
+ assign(new_val, mkU32(0));
+ assign(old, load(Ity_I32, mkexpr(addr)));
+ mips_load_store32(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Clear Doubleword - LACD; Cavium OCTEON2 */
case 0x0f: {
DIP("lacd r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I64);
+ IRTemp new_val = newTemp(Ity_I64);
+ IRTemp old = newTemp(Ity_I64);
assign(addr, getIReg(regRs));
- assign(new, mkU64(0));
- mips_irgen_load_and_add64(addr, new, regRd, True);
+ assign(new_val, mkU64(0));
+ assign(old, load(Ity_I64, mkexpr(addr)));
+ mips_load_store64(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Add Word - LAA; Cavium OCTEON2 */
case 0x12: {
DIP("laa r%u,(r%u),r%u\n", regRd, regRs, regRt);
- IRTemp new = newTemp(Ity_I32);
+ IRTemp new_val = newTemp(Ity_I32);
+ IRTemp old = newTemp(Ity_I32);
assign(addr, getIReg(regRs));
- assign(new, binop(Iop_Add32,
- load(Ity_I32, mkexpr(addr)),
- mkNarrowTo32(ty, getIReg(regRt))));
- mips_irgen_load_and_add32(addr, new, regRd, True);
+ assign(old, load(Ity_I32, mkexpr(addr)));
+ assign(new_val, binop(Iop_Add32,
+ mkexpr(old),
+ mkNarrowTo32(ty, getIReg(regRt))));
+ mips_load_store32(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Add Doubleword - LAAD; Cavium OCTEON2 */
case 0x13: {
DIP("laad r%u,(r%u),r%u\n", regRd, regRs, regRt);
- IRTemp new = newTemp(Ity_I64);
- assign (addr, getIReg(regRs));
- assign(new, binop(Iop_Add64,
- load(Ity_I64, mkexpr(addr)),
- getIReg(regRt)));
- mips_irgen_load_and_add64(addr, new, regRd, True);
+ IRTemp new_val = newTemp(Ity_I64);
+ IRTemp old = newTemp(Ity_I64);
+ assign(addr, getIReg(regRs));
+ assign(old, load(Ity_I64, mkexpr(addr)));
+ assign(new_val, binop(Iop_Add64,
+ load(Ity_I64, mkexpr(addr)),
+ getIReg(regRt)));
+ mips_load_store64(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Swap Word - LAW; Cavium OCTEON2 */
case 0x16: {
DIP("law r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I32);
+ IRTemp new_val = newTemp(Ity_I32);
+ IRTemp old = newTemp(Ity_I32);
assign(addr, getIReg(regRs));
- assign(new, mkNarrowTo32(ty, getIReg(regRt)));
- mips_irgen_load_and_add32(addr, new, regRd, True);
+ assign(new_val, mkNarrowTo32(ty, getIReg(regRt)));
+ assign(old, load(Ity_I32, mkexpr(addr)));
+ mips_load_store32(addr, new_val, old, regRd, True);
break;
}
/* Load Atomic Swap Doubleword - LAWD; Cavium OCTEON2 */
case 0x17: {
DIP("lawd r%u,(r%u)\n", regRd, regRs);
- IRTemp new = newTemp(Ity_I64);
+ IRTemp new_val = newTemp(Ity_I64);
+ IRTemp old = newTemp(Ity_I64);
assign(addr, getIReg(regRs));
- assign(new, getIReg(regRt));
- mips_irgen_load_and_add64(addr, new, regRd, True);
+ assign(new_val, getIReg(regRt));
+ assign(old, load(Ity_I64, mkexpr(addr)));
+ mips_load_store64(addr, new_val, old, regRd, True);
break;
}
default:
|
|
From: Julian S. <js...@ac...> - 2017-02-09 18:01:33
|
Hi Rashawn,
Thank you for the offer of adding AVX-512 support, and sorry for the
slow response. Some of the Valgrind developers discussed this briefly
at Fosdem in Brussels last weekend and there was general agreement
that this would be a good thing to do.
I would be happy to be a point of contact for technical and process
assistance. I have both technical and process comments regarding
your proposal.
>From a process point of view:
* This is likely to take several months and may involve more than one
round of review and iteration. That's based on experience from
other large chunks of instruction-set development work.
* As an example, have a look the following 5 bugs, which show a staged
approach to implementation of the recent POWER ISA 3.0 extensions:
https://bugs.kde.org/show_bug.cgi?id=359767
https://bugs.kde.org/show_bug.cgi?id=361207
https://bugs.kde.org/show_bug.cgi?id=362329
https://bugs.kde.org/show_bug.cgi?id=363858
https://bugs.kde.org/show_bug.cgi?id=364948
* Patches should go on the bug tracker, as per the examples above, and
will be reviewed there.
* All contributions to the tree need to be licensed "GNU GPL 2 or
later". Are you OK with that? GPL 2-only is not possible.
* There is a general, although largely unstated, expectation that parties
who contribute large chunks of code continue afterwards to provide at
least some minimal level of support/bugfixing, especially around
release-time. We've had problems in the past with large bits of the
code going into the tree and the developers later simply disappearing,
and would prefer to avoid that in future. Would you be able to
provide that level of support going forward?
* Similarly, there is an expectation that you have some machine which
can run nightly tests (from our framework) and send results to the
valgrind-testresults mailing list. Since none of the developers
(AFAIK) have AVX512 capable hardware, we have no other way to know
whether the support is working.
* VEX is basically a mini-compiler for basic blocks. Not essential,
but it will help if your developer(s) have a bit of basic background
in compiler internals.
Regarding your proposed implementation steps, they sound plausible.
However:
* You need a step zero, which is to extend Valgrind's HW capabilities
detection (coregrind/m_machine.c) to detect AVX512 support and tell
VEX about it. That has to happen before any insns get implemented.
* Also, you will need to extend the implementation of XSAVE and XRSTOR
to cover the new register state. Given the inflexibility of VEX's
IR (intermediate representation), the current AVX2-level XSAVE and
XRSTOR was difficult to implement and is hard to understand, so this
is likely to be a challenge. I suggest you deal with it sooner
rather than later, since we've found that runtime libraries rely on
XSAVE and XRSTOR and so you won't be able to run any real code with
AVX512 until those two are working.
* I assume (although you didn't say this) that you are doing this for
the 64-bit instruction set only. Our 32 bit insn set support is
essentially legacy, having stopped at SSSE3, and doesn't have a
proper prefix decoder in the same way that the 64 bit front end
does.
* Write test cases for the insns first, and make sure they are
comprehensive enough and work well. This reduces the general stress
and difficulty of implementing the instructions. Bear in mind that
incorrect instruction emulation can corrupt program state in a way
that isn't apparent until hundreds of millions of instructions
later, by which time it is impossible to figure out what went wrong.
So a good test suite is essential. See for example
none/tests/amd64/avx2-1.c and many others in the same directory.
* Some of the existing AVX256 insn implementations are less than
ideal, in the sense that they generate very verbose IR that performs
operations a lane at a time, rather than as a vector as a whole.
That gives rise to problems like
https://bugs.kde.org/show_bug.cgi?id=375839
The practical consequence is that (often) you won't be able to just
implement a 512-bit variant of an existing 256-bit insn by doubling
up the IR -- we'll have to do something better (wider and shallower)
here.
* If -- as seems likely -- you need to add new IROps to facilitate
this support, then you will also need to add support for them in
memcheck/mc_translate.c.
* Since you are adding register state, you'll need to futz with
memcheck/mc_machine.c too.
* You will need to be careful to ensure that the back end provides
SIMD integer support capable of supporting Memcheck's instrumentation
of the front end's SIMD FP IR. Without that, you'll wind up in a
situation where you can run AVX512 code with the 'none' tool but not
with 'memcheck'. This is an arcane but important detail. We can
come back to it later.
J
|
|
From: Mike L. <mik...@gm...> - 2017-02-09 01:04:05
|
Adding some example output:
With default flags:
==3382== Callgrind, a call-graph generating cache profiler
==3382== Copyright (C) 2002-2015, and GNU GPL'd, by Josef Weidendorfer et
al.
==3382== Using Valgrind-3.12.0 and LibVEX; rerun with -h for copyright info
==3382== Command:
parsec-3.0/pkgs/apps/blackscholes/inst/amd64-linux.gcc-pthreads/bin/blackscholes
4 in_4.txt prices.txt
==3382==
==3382== For interactive control, run 'callgrind_control -h'.
PARSEC Benchmark Suite Version 3.0-beta-20150206
Num of Options: 4
Num of Runs: 100
Size of data: 160
*Thread switched to: 4*
*Thread switched to: 3*
*Thread switched to: 2*
*Thread switched to: 1*
*Thread switched to: 5*
*Thread switched to: 4*
*Thread switched to: 1*
==3382==
==3382== Events : Ir
==3382== Collected : 569502
==3382==
==3382== I refs: 569,502
With --fair-sched=yes:
==3375== Callgrind, a call-graph generating cache profiler
==3375== Copyright (C) 2002-2015, and GNU GPL'd, by Josef Weidendorfer et
al.
==3375== Using Valgrind-3.12.0 and LibVEX; rerun with -h for copyright info
==3375== Command:
parsec-3.0/pkgs/apps/blackscholes/inst/amd64-linux.gcc-pthreads/bin/blackscholes
4 in_4.txt prices.txt
==3375==
==3375== For interactive control, run 'callgrind_control -h'.
PARSEC Benchmark Suite Version 3.0-beta-20150206
Num of Options: 4
Num of Runs: 100
Size of data: 160
*Thread switched to: 2*
*Thread switched to: 1*
*Thread switched to: 3*
*Thread switched to: 2*
*Thread switched to: 1*
*Thread switched to: 4*
*Thread switched to: 3*
*Thread switched to: 1*
*Thread switched to: 4*
*Thread switched to: 2*
*Thread switched to: 1*
*Thread switched to: 2*
*Thread switched to: 1*
==3375==
==3375== Events : Ir
==3375== Collected : 569505
==3375==
==3375== I refs: 569,505
On Wed, Feb 8, 2017 at 7:56 PM Mike Lui <mik...@gm...> wrote:
> I'm working on a project that leverages Callgrind to generate VEX IR
> traces. I'm using Valgrind 3.12.0.
> I also use Callgrind's infrastructure to detect when Valgrind switches
> thread contexts, however I'm getting unexpected behavior.
>
> It looks like the best place to detect a thread context switch in
> Callgrind is in CLG_(setup_bbcc) in bbcc.c (line 561):
>
> /* This is needed because thread switches can not reliable be tracked
> * with callback CLG_(run_thread) only: we have otherwise no way to get
> * the thread ID after a signal handler returns.
> * This could be removed again if that bug is fixed in Valgrind.
> * This is in the hot path but hopefully not to costly.
> */
> tid = VG_(get_running_tid)();
> #if 1
> /* CLG_(switch_thread) is a no-op when tid is equal to CLG_(current_tid).
> * As this is on the hot path, we only call CLG_(switch_thread)(tid)
> * if tid differs from the CLG_(current_tid).
> */
> if (UNLIKELY(tid != CLG_(current_tid)))
> CLG_(switch_thread)(tid);
>
> The above is called every instrumented basic block.
> I've noticed strange behavior, where* a thread switch would not always be
> detected.*
> I detected the unexpected behavior with the following modifications:
>
> To investigate further, I modified the above:
> - if (UNLIKELY(tid != CLG_(current_tid)))
> + if (UNLIKELY(tid != CLG_(current_tid))) {
> CLG_(switch_thread)(tid);
> + VG_(printf)("Thread switched to: %d\n", tid);
> + }
>
>
> - With this change, I run the parsec 3.0 benchmark blackscholes with 4
> threads, input_test.tar, and expect to see *5 *threads (numbered 1-5,
> 1 master and 4 worker threads) printed.
> - Under default flags, I'm seeing all 5 threads printed
> - when I add --fair-sched=yes, often I'd see the last thread (5) *not
> printed*.
> - I confirmed this behavior by printing VG_(get_running_tid)() every
> instrumented basic block.
> - I know that the thread switch happened or else the application would
> have failed.
>
> This does not happen all the time but it happens on the majority of runs. I
> also noticed that if I put a print statement in the blackscholes worker
> thread, the unexpected behavior manifests far less often. I conclude it
> must have something to do with the thread exiting too quickly and not
> having enough work to do.
>
> *Is this considered a bug? If not, how do I detect every time the Valgrind
> thread context changes. I saw this thread
> <http://valgrind-developers.narkive.com/ualztznb/thread-change-callback>from
> a long time ago but I'm not sure if there's been any progress.*
>
> $ uname -a
> Linux ubuntu-VirtualBox 3.19.0-25-generic #26~14.04.1-Ubuntu SMP Fri Jul
> 24 21:16:20 UTC 2015 x86_64 x86_64 x86_64 GNU/Linux
>
> *Steps to reproduce:*
> mkdir detect_thread_switch && cd detect_thread_switch
> curl -L http://parsec.cs.princeton.edu/download/3.0/parsec-3.0-core.tar.gz
> | tar xz
> parsec-3.0/bin/parsecmgmt -a build -p blackscholes -c gcc-pthreads
> tar xf parsec-3.0/pkgs/apps/blackscholes/inputs/input_test.tar
>
> curl -L http://valgrind.org/downloads/valgrind-3.12.0.tar.bz2 | tar xj
> *# MAKE THE CHANGE TO bbcc.c TO PRINT THREAD ID ON THREAD SWITCH*
>
> cd valgrind-3.12.0 && ./autogen.sh && ./configure
> make -j4 && cd ..
>
> *# WILL SHOW THREADS 1-5*
> valgrind-3.12.0/vg-in-place --tool=callgrind
> parsec-3.0/pkgs/apps/blackscholes/inst/amd64-linux.gcc-pthreads/bin/blackscholes
> 4 in_4.txt prices.txt
>
> *# MAY HAVE TO RUN SEVERAL TIMES IN SUCCESSION, WILL EVENTUALLY BE MISSING
> THREAD 5*
> valgrind-3.12.0/vg-in-place --fair-sched=yes --tool=callgrind
> parsec-3.0/pkgs/apps/blackscholes/inst/amd64-linux.gcc-pthreads/bin/blackscholes
> 4 in_4.txt prices.txt
>
> Thanks!
> Mike
>
|
|
From: Mike L. <mik...@gm...> - 2017-02-09 00:56:23
|
I'm working on a project that leverages Callgrind to generate VEX IR
traces. I'm using Valgrind 3.12.0.
I also use Callgrind's infrastructure to detect when Valgrind switches
thread contexts, however I'm getting unexpected behavior.
It looks like the best place to detect a thread context switch in Callgrind
is in CLG_(setup_bbcc) in bbcc.c (line 561):
/* This is needed because thread switches can not reliable be tracked
* with callback CLG_(run_thread) only: we have otherwise no way to get
* the thread ID after a signal handler returns.
* This could be removed again if that bug is fixed in Valgrind.
* This is in the hot path but hopefully not to costly.
*/
tid = VG_(get_running_tid)();
#if 1
/* CLG_(switch_thread) is a no-op when tid is equal to CLG_(current_tid).
* As this is on the hot path, we only call CLG_(switch_thread)(tid)
* if tid differs from the CLG_(current_tid).
*/
if (UNLIKELY(tid != CLG_(current_tid)))
CLG_(switch_thread)(tid);
The above is called every instrumented basic block.
I've noticed strange behavior, where* a thread switch would not always be
detected.*
I detected the unexpected behavior with the following modifications:
To investigate further, I modified the above:
- if (UNLIKELY(tid != CLG_(current_tid)))
+ if (UNLIKELY(tid != CLG_(current_tid))) {
CLG_(switch_thread)(tid);
+ VG_(printf)("Thread switched to: %d\n", tid);
+ }
- With this change, I run the parsec 3.0 benchmark blackscholes with 4
threads, input_test.tar, and expect to see *5 *threads (numbered 1-5, 1
master and 4 worker threads) printed.
- Under default flags, I'm seeing all 5 threads printed
- when I add --fair-sched=yes, often I'd see the last thread (5) *not
printed*.
- I confirmed this behavior by printing VG_(get_running_tid)() every
instrumented basic block.
- I know that the thread switch happened or else the application would
have failed.
This does not happen all the time but it happens on the majority of runs. I
also noticed that if I put a print statement in the blackscholes worker
thread, the unexpected behavior manifests far less often. I conclude it
must have something to do with the thread exiting too quickly and not
having enough work to do.
*Is this considered a bug? If not, how do I detect every time the Valgrind
thread context changes. I saw this thread
<http://valgrind-developers.narkive.com/ualztznb/thread-change-callback>from
a long time ago but I'm not sure if there's been any progress.*
$ uname -a
Linux ubuntu-VirtualBox 3.19.0-25-generic #26~14.04.1-Ubuntu SMP Fri Jul 24
21:16:20 UTC 2015 x86_64 x86_64 x86_64 GNU/Linux
*Steps to reproduce:*
mkdir detect_thread_switch && cd detect_thread_switch
curl -L http://parsec.cs.princeton.edu/download/3.0/parsec-3.0-core.tar.gz
| tar xz
parsec-3.0/bin/parsecmgmt -a build -p blackscholes -c gcc-pthreads
tar xf parsec-3.0/pkgs/apps/blackscholes/inputs/input_test.tar
curl -L http://valgrind.org/downloads/valgrind-3.12.0.tar.bz2 | tar xj
*# MAKE THE CHANGE TO bbcc.c TO PRINT THREAD ID ON THREAD SWITCH*
cd valgrind-3.12.0 && ./autogen.sh && ./configure
make -j4 && cd ..
*# WILL SHOW THREADS 1-5*
valgrind-3.12.0/vg-in-place --tool=callgrind
parsec-3.0/pkgs/apps/blackscholes/inst/amd64-linux.gcc-pthreads/bin/blackscholes
4 in_4.txt prices.txt
*# MAY HAVE TO RUN SEVERAL TIMES IN SUCCESSION, WILL EVENTUALLY BE MISSING
THREAD 5*
valgrind-3.12.0/vg-in-place --fair-sched=yes --tool=callgrind
parsec-3.0/pkgs/apps/blackscholes/inst/amd64-linux.gcc-pthreads/bin/blackscholes
4 in_4.txt prices.txt
Thanks!
Mike
|
|
From: <pa...@fr...> - 2017-02-08 21:12:28
|
----- Original Message -----
> 2017-02-05 20:31 GMT+01:00 <pa...@fr...>:
> > Hi all
> >
> > I'm trying to understand how valgrind resolves replacement
> > functions at runtime.
>
> Hi Paul,
> Have a look at pub_tool_redir.h, mechanics and Z-encoding rules are
> described there.
Hi Ivo
Thanks for the info. What was confusing me the most was why code that called operator delete(void* ptr, std::size_t) was being detected by an unmodified valgrind as operator delete(void* ptr). Looking at the libstdc++ source this is now obvious:
_GLIBCXX_WEAK_DEFINITION void
operator delete(void* ptr, std::size_t) _GLIBCXX_USE_NOEXCEPT
{
::operator delete (ptr);
}
[and libcxx does the same]
So currently this works because the new functions just wrap the old ones.
A+
Paul
|
|
From: <sv...@va...> - 2017-02-08 08:27:43
|
Author: sewardj
Date: Wed Feb 8 08:27:34 2017
New Revision: 16221
Log:
am_munmap_both_wrk: safely initialise out-param for all return paths.
Silences what I think is a false complaint from gcc at -O3.
Modified:
trunk/coregrind/m_aspacemgr/aspacemgr-linux.c
Modified: trunk/coregrind/m_aspacemgr/aspacemgr-linux.c
==============================================================================
--- trunk/coregrind/m_aspacemgr/aspacemgr-linux.c (original)
+++ trunk/coregrind/m_aspacemgr/aspacemgr-linux.c Wed Feb 8 08:27:34 2017
@@ -2773,6 +2773,9 @@
Bool d;
SysRes sres;
+ /* Be safe with this regardless of return path. */
+ *need_discard = False;
+
if (!VG_IS_PAGE_ALIGNED(start))
goto eINVAL;
|
|
From: Ivo R. <iv...@iv...> - 2017-02-07 13:16:34
|
2017-02-05 20:31 GMT+01:00 <pa...@fr...>: > Hi all > > I'm trying to understand how valgrind resolves replacement functions at runtime. Hi Paul, Have a look at pub_tool_redir.h, mechanics and Z-encoding rules are described there. > GCC 4.8.2 emits > gnm test64_482 | grep _Z > U _ZdlPv > U _Znwm > > > Or demangled > > gnm -C test64_482 | grep operator > U operator delete(void*) > U operator new(unsigned long) > > I see that this corresponds to the following in vg_replace_malloc.c: > > FREE(VG_Z_LIBSTDCXX_SONAME, _ZdaPv, __builtin_vec_delete ); > FREE(SO_SYN_MALLOC, _ZdaPv, __builtin_vec_delete ); > > > At runtime > > valgrind --trace-malloc=yes ./test64_482 > --7974-- _Znwm(4) = 0x7FF760040 > --7974-- _ZdlPv(0x7FF760040) > > So far so good. > > With GCC built from SVN head (but I'd expect the same for any GCC since version 6) this changes a bit. [see also bz 72347] > > GCC emits > gnm test64 | grep _Z > U _ZdlPvm > U _Znwm > > demangled > > gnm -C test64 | grep operator > U operator delete(void*, unsigned long) > U operator new(unsigned long) > > valgrind --trace-malloc=yes ./test64 > --9374-- malloc(72704) = 0x7FF680040 > --9374-- _Znwm(4) = 0x7FF691C80 > --9374-- _ZdlPv(0x7FF691C80) > --9374-- free(0x7FF680040) I think you've already spotted the difference between: _ZdlPv: operator delete(void*) [which is replaced by _ZdaPv: __builtin_vec_delete] and _ZdlPvm: operator delete(void*, unsigned long) So the remaining task becomes finding a replacer for _ZdlPvm and if there is none, providing one. I. |
|
From: <pa...@fr...> - 2017-02-05 19:31:15
|
Hi all
I'm trying to understand how valgrind resolves replacement functions at runtime.
Here's the code that I'm using:
class MyClass
{
int i;
};
int main()
{
MyClass* myClass = new MyClass();
delete myClass;
}
GCC 4.8.2 emits
gnm test64_482 | grep _Z
U _ZdlPv
U _Znwm
Or demangled
gnm -C test64_482 | grep operator
U operator delete(void*)
U operator new(unsigned long)
I see that this corresponds to the following in vg_replace_malloc.c:
FREE(VG_Z_LIBSTDCXX_SONAME, _ZdaPv, __builtin_vec_delete );
FREE(SO_SYN_MALLOC, _ZdaPv, __builtin_vec_delete );
At runtime
valgrind --trace-malloc=yes ./test64_482
--7974-- _Znwm(4) = 0x7FF760040
--7974-- _ZdlPv(0x7FF760040)
So far so good.
With GCC built from SVN head (but I'd expect the same for any GCC since version 6) this changes a bit. [see also bz 72347]
GCC emits
gnm test64 | grep _Z
U _ZdlPvm
U _Znwm
demangled
gnm -C test64 | grep operator
U operator delete(void*, unsigned long)
U operator new(unsigned long)
valgrind --trace-malloc=yes ./test64
--9374-- malloc(72704) = 0x7FF680040
--9374-- _Znwm(4) = 0x7FF691C80
--9374-- _ZdlPv(0x7FF691C80)
--9374-- free(0x7FF680040)
The extra malloc/free are, I guess, artefacts of the newer libstdc++; I get them even with an empty main().
I don't see how (and I haven't found in the Vagrind code) how the call to ZdlPvm resolves to _ZdlPv. Can anyone tell me where to look in the Valgrind code for this?
A+
Paul
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