You can subscribe to this list here.
| 2002 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
(1) |
Oct
(122) |
Nov
(152) |
Dec
(69) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2003 |
Jan
(6) |
Feb
(25) |
Mar
(73) |
Apr
(82) |
May
(24) |
Jun
(25) |
Jul
(10) |
Aug
(11) |
Sep
(10) |
Oct
(54) |
Nov
(203) |
Dec
(182) |
| 2004 |
Jan
(307) |
Feb
(305) |
Mar
(430) |
Apr
(312) |
May
(187) |
Jun
(342) |
Jul
(487) |
Aug
(637) |
Sep
(336) |
Oct
(373) |
Nov
(441) |
Dec
(210) |
| 2005 |
Jan
(385) |
Feb
(480) |
Mar
(636) |
Apr
(544) |
May
(679) |
Jun
(625) |
Jul
(810) |
Aug
(838) |
Sep
(634) |
Oct
(521) |
Nov
(965) |
Dec
(543) |
| 2006 |
Jan
(494) |
Feb
(431) |
Mar
(546) |
Apr
(411) |
May
(406) |
Jun
(322) |
Jul
(256) |
Aug
(401) |
Sep
(345) |
Oct
(542) |
Nov
(308) |
Dec
(481) |
| 2007 |
Jan
(427) |
Feb
(326) |
Mar
(367) |
Apr
(255) |
May
(244) |
Jun
(204) |
Jul
(223) |
Aug
(231) |
Sep
(354) |
Oct
(374) |
Nov
(497) |
Dec
(362) |
| 2008 |
Jan
(322) |
Feb
(482) |
Mar
(658) |
Apr
(422) |
May
(476) |
Jun
(396) |
Jul
(455) |
Aug
(267) |
Sep
(280) |
Oct
(253) |
Nov
(232) |
Dec
(304) |
| 2009 |
Jan
(486) |
Feb
(470) |
Mar
(458) |
Apr
(423) |
May
(696) |
Jun
(461) |
Jul
(551) |
Aug
(575) |
Sep
(134) |
Oct
(110) |
Nov
(157) |
Dec
(102) |
| 2010 |
Jan
(226) |
Feb
(86) |
Mar
(147) |
Apr
(117) |
May
(107) |
Jun
(203) |
Jul
(193) |
Aug
(238) |
Sep
(300) |
Oct
(246) |
Nov
(23) |
Dec
(75) |
| 2011 |
Jan
(133) |
Feb
(195) |
Mar
(315) |
Apr
(200) |
May
(267) |
Jun
(293) |
Jul
(353) |
Aug
(237) |
Sep
(278) |
Oct
(611) |
Nov
(274) |
Dec
(260) |
| 2012 |
Jan
(303) |
Feb
(391) |
Mar
(417) |
Apr
(441) |
May
(488) |
Jun
(655) |
Jul
(590) |
Aug
(610) |
Sep
(526) |
Oct
(478) |
Nov
(359) |
Dec
(372) |
| 2013 |
Jan
(467) |
Feb
(226) |
Mar
(391) |
Apr
(281) |
May
(299) |
Jun
(252) |
Jul
(311) |
Aug
(352) |
Sep
(481) |
Oct
(571) |
Nov
(222) |
Dec
(231) |
| 2014 |
Jan
(185) |
Feb
(329) |
Mar
(245) |
Apr
(238) |
May
(281) |
Jun
(399) |
Jul
(382) |
Aug
(500) |
Sep
(579) |
Oct
(435) |
Nov
(487) |
Dec
(256) |
| 2015 |
Jan
(338) |
Feb
(357) |
Mar
(330) |
Apr
(294) |
May
(191) |
Jun
(108) |
Jul
(142) |
Aug
(261) |
Sep
(190) |
Oct
(54) |
Nov
(83) |
Dec
(22) |
| 2016 |
Jan
(49) |
Feb
(89) |
Mar
(33) |
Apr
(50) |
May
(27) |
Jun
(34) |
Jul
(53) |
Aug
(53) |
Sep
(98) |
Oct
(206) |
Nov
(93) |
Dec
(53) |
| 2017 |
Jan
(65) |
Feb
(82) |
Mar
(102) |
Apr
(86) |
May
(187) |
Jun
(67) |
Jul
(23) |
Aug
(93) |
Sep
(65) |
Oct
(45) |
Nov
(35) |
Dec
(17) |
| 2018 |
Jan
(26) |
Feb
(35) |
Mar
(38) |
Apr
(32) |
May
(8) |
Jun
(43) |
Jul
(27) |
Aug
(30) |
Sep
(43) |
Oct
(42) |
Nov
(38) |
Dec
(67) |
| 2019 |
Jan
(32) |
Feb
(37) |
Mar
(53) |
Apr
(64) |
May
(49) |
Jun
(18) |
Jul
(14) |
Aug
(53) |
Sep
(25) |
Oct
(30) |
Nov
(49) |
Dec
(31) |
| 2020 |
Jan
(87) |
Feb
(45) |
Mar
(37) |
Apr
(51) |
May
(99) |
Jun
(36) |
Jul
(11) |
Aug
(14) |
Sep
(20) |
Oct
(24) |
Nov
(40) |
Dec
(23) |
| 2021 |
Jan
(14) |
Feb
(53) |
Mar
(85) |
Apr
(15) |
May
(19) |
Jun
(3) |
Jul
(14) |
Aug
(1) |
Sep
(57) |
Oct
(73) |
Nov
(56) |
Dec
(22) |
| 2022 |
Jan
(3) |
Feb
(22) |
Mar
(6) |
Apr
(55) |
May
(46) |
Jun
(39) |
Jul
(15) |
Aug
(9) |
Sep
(11) |
Oct
(34) |
Nov
(20) |
Dec
(36) |
| 2023 |
Jan
(79) |
Feb
(41) |
Mar
(99) |
Apr
(169) |
May
(48) |
Jun
(16) |
Jul
(16) |
Aug
(57) |
Sep
(19) |
Oct
|
Nov
|
Dec
|
| S | M | T | W | T | F | S |
|---|---|---|---|---|---|---|
|
1
|
2
|
3
(1) |
4
(1) |
5
|
6
(1) |
7
|
|
8
|
9
(1) |
10
(4) |
11
(3) |
12
(6) |
13
(13) |
14
(1) |
|
15
(1) |
16
(3) |
17
|
18
(1) |
19
(3) |
20
(7) |
21
(5) |
|
22
|
23
(1) |
24
|
25
(3) |
26
|
27
(3) |
28
|
|
29
(1) |
30
(1) |
31
(5) |
|
|
|
|
|
From: Sebastian L. <seb...@fd...> - 2017-01-20 03:40:31
|
On 19.01.2017 20:30, Julian Seward wrote: > > Hi Sebastian, > >> The Valgrind bugtracker also contains three patches I proposed back then. I >> was hoping that this would speed up the process of getting this fixed, but >> unfortunately it didn't help much. At many places Valgrind does not yet >> handle signal registers correctly and doesn't complain - except here, which >> is really unfortunate because even ignoring would be sufficient to make Wine >> happy. > > Sorry this fell through the cracks. One underlying problem is that, some > time back in 2003, I learnt just enough about x86 segment stuff to hack up > what's currently in Valgrind, and then promptly forgot about it. So I'm > not in much of a position to make an informed judgement now. > > That said .. I would be OK with a partial fix which improves Valgrind's > SS handling enough to make Wine work, so long as it doesn't create a > situation where other cases are silently handled incorrectly. That is, > if the fix only moves forwards on the correctness scale, and doesn't > introduce any regressions. > > On rereading https://bugs.kde.org/show_bug.cgi?id=344139#c1 I see that you > have a candidate patch (http://ix.io/gKt, "Correctly handle the SS prefix > when explicitly specified.") which appears to have the abovementioned > properties. Is that correct? > > J > As discussed on IRC, this direction probably makes most sense. In contrast to the other approaches, no special handling for the SS segment is required - nevertheless, we have to initialize some GDT entries to make this work. I have attached a new series which is hopefully less hacky: https://bugs.kde.org/show_bug.cgi?id=344139#c3 (*) https://bugs.kde.org/show_bug.cgi?id=344139#c4 (*) On some systems the segment for DS and SS is the same, but initializing twice shouldn't hurt. For me it fixes the Wine tests (@Austin: Could you confirm?). Please let me know if you have any other suggestions for improvement (either here or on the bugtracker). Thanks! Best regards, Sebastian |
|
From: Julian S. <js...@ac...> - 2017-01-19 19:30:13
|
Hi Sebastian, > The Valgrind bugtracker also contains three patches I proposed back then. I > was hoping that this would speed up the process of getting this fixed, but > unfortunately it didn't help much. At many places Valgrind does not yet > handle signal registers correctly and doesn't complain - except here, which > is really unfortunate because even ignoring would be sufficient to make Wine > happy. Sorry this fell through the cracks. One underlying problem is that, some time back in 2003, I learnt just enough about x86 segment stuff to hack up what's currently in Valgrind, and then promptly forgot about it. So I'm not in much of a position to make an informed judgement now. That said .. I would be OK with a partial fix which improves Valgrind's SS handling enough to make Wine work, so long as it doesn't create a situation where other cases are silently handled incorrectly. That is, if the fix only moves forwards on the correctness scale, and doesn't introduce any regressions. On rereading https://bugs.kde.org/show_bug.cgi?id=344139#c1 I see that you have a candidate patch (http://ix.io/gKt, "Correctly handle the SS prefix when explicitly specified.") which appears to have the abovementioned properties. Is that correct? J |
|
From: Julian S. <js...@ac...> - 2017-01-19 15:53:49
|
> On 13/01/17 23:03, Philippe Waroquiers wrote: > So, no developer, no user, no company person telling anything, > and public information telling the chip will be replaced. I agree, I think this port should be removed. A whole year with absolutely no signs of user or maintainer activity is, in my view, long enough. J |
Author: sewardj
Date: Thu Jan 19 06:53:13 2017
New Revision: 16203
Log:
Connect the v8 FP and SIMD tests to the build system.
Added:
trunk/none/tests/arm/v8fpsimd_a.stderr.exp
trunk/none/tests/arm/v8fpsimd_a.stdout.exp
trunk/none/tests/arm/v8fpsimd_a.vgtest
trunk/none/tests/arm/v8fpsimd_t.c (with props)
trunk/none/tests/arm/v8fpsimd_t.stderr.exp (with props)
trunk/none/tests/arm/v8fpsimd_t.stdout.exp (with props)
trunk/none/tests/arm/v8fpsimd_t.vgtest
Modified:
trunk/none/tests/arm/Makefile.am
trunk/none/tests/arm/v8fpsimd_a.c
Modified: trunk/none/tests/arm/Makefile.am
==============================================================================
--- trunk/none/tests/arm/Makefile.am (original)
+++ trunk/none/tests/arm/Makefile.am Thu Jan 19 06:53:13 2017
@@ -14,6 +14,8 @@
v6media.stdout.exp v6media.stderr.exp v6media.vgtest \
v8crypto_a.stdout.exp v8crypto_a.stderr.exp v8crypto_a.vgtest \
v8crypto_t.stdout.exp v8crypto_t.stderr.exp v8crypto_t.vgtest \
+ v8fpsimd_a.stdout.exp v8fpsimd_a.stderr.exp v8fpsimd_a.vgtest \
+ v8fpsimd_t.stdout.exp v8fpsimd_t.stderr.exp v8fpsimd_t.vgtest \
v8memory_a.stdout.exp v8memory_a.stderr.exp v8memory_a.vgtest \
v8memory_t.stdout.exp v8memory_t.stderr.exp v8memory_t.vgtest \
vcvt_fixed_float_VFP.stdout.exp vcvt_fixed_float_VFP.stderr.exp \
@@ -33,6 +35,8 @@
v6media \
v8crypto_a \
v8crypto_t \
+ v8fpsimd_a \
+ v8fpsimd_t \
v8memory_a \
v8memory_t \
vcvt_fixed_float_VFP \
@@ -60,6 +64,9 @@
v8crypto_a_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -marm
v8crypto_t_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -mthumb
+v8fpsimd_a_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -marm
+v8fpsimd_t_CFLAGS = $(AM_CFLAGS) -g -O0 -mfpu=crypto-neon-fp-armv8 -mthumb
+
v8memory_a_CFLAGS = $(AM_CFLAGS) -g -O0 \
-march=armv8-a -mfpu=crypto-neon-fp-armv8 -marm
v8memory_t_CFLAGS = $(AM_CFLAGS) -g -O0 \
Modified: trunk/none/tests/arm/v8fpsimd_a.c
==============================================================================
--- trunk/none/tests/arm/v8fpsimd_a.c (original)
+++ trunk/none/tests/arm/v8fpsimd_a.c Thu Jan 19 06:53:13 2017
@@ -222,7 +222,7 @@
/* Don't use INSN_PRE in printing, since that differs */ \
/* between ARM and Thumb and hence makes their outputs differ. */ \
printf(INSN " "); \
- UInt fpscr = 0xFFFFFFFF & block[4].u32[0]; \
+ UInt fpscr = 0xFFFFFFE0 & block[4].u32[0]; \
showV128(&block[0]); printf(" "); \
showV128(&block[1]); printf(" "); \
showV128(&block[2]); printf(" "); \
@@ -269,7 +269,7 @@
/* Don't use INSN_PRE in printing, since that differs */ \
/* between ARM and Thumb and hence makes their outputs differ. */ \
printf(INSN " "); \
- UInt fpscr = 0xFFFFFFFF & block[6].u32[0]; \
+ UInt fpscr = 0xFFFFFFE0 & block[6].u32[0]; \
showV128(&block[0]); printf(" "); \
showV128(&block[1]); printf(" "); \
showV128(&block[2]); printf(" "); \
@@ -469,11 +469,11 @@
if (1) DO50( test_vcvtp_u32_f32(TySF) );
if (1) DO50( test_vcvtm_u32_f32(TySF) );
- if (1) DO50( test_vcvtb_f64_f16(TyDF) );
- if (1) DO50( test_vcvtt_f64_f16(TyDF) );
+ if (0) DO50( test_vcvtb_f64_f16(TyDF) );
+ if (0) DO50( test_vcvtt_f64_f16(TyDF) );
- if (1) DO50( test_vcvtb_f16_f64(TyHF) );
- if (1) DO50( test_vcvtt_f16_f64(TyHF) );
+ if (0) DO50( test_vcvtb_f16_f64(TyHF) );
+ if (0) DO50( test_vcvtt_f16_f64(TyHF) );
if (1) DO50( test_vrintzeq_f64_f64(TyDF) );
if (1) DO50( test_vrintzne_f64_f64(TyDF) );
Added: trunk/none/tests/arm/v8fpsimd_a.stderr.exp
==============================================================================
(empty)
Added: trunk/none/tests/arm/v8fpsimd_a.stdout.exp
==============================================================================
--- trunk/none/tests/arm/v8fpsimd_a.stdout.exp (added)
+++ trunk/none/tests/arm/v8fpsimd_a.stdout.exp Thu Jan 19 06:53:13 2017
@@ -0,0 +1,6763 @@
+randV128: doing v->u32[3] = v->u32[2]
+vselge.f32 s15,s16,s20 5175e39d19c9ca1e98f24a4984175700 c5fa956ac5fa956a0d69c3e9a6af27d1 56a044b260b160857d45c48447b8d8c0 a6af27d119c9ca1e98f24a4984175700 c5fa956ac5fa956a0d69c3e9a6af27d1 56a044b260b160857d45c48447b8d8c0 fpscr=00000000
+vselge.f32 s15,s16,s20 d740b80eb7839b97d89998df5035ed36 db56b01a12b0ca1583cb509970b8136c 191fd3a727d1a705f65df9dd4a29f8c0 70b8136cb7839b97d89998df5035ed36 db56b01a12b0ca1583cb509970b8136c 191fd3a727d1a705f65df9dd4a29f8c0 fpscr=00000000
+vselge.f32 s15,s16,s20 b536bbe4da8a369dab4f9465b86ed182 7b8d9035449b06f4e06e2205236eb768 95264321bf3b68b255c2b9e2c95c9810 236eb768da8a369dab4f9465b86ed182 7b8d9035449b06f4e06e2205236eb768 95264321bf3b68b255c2b9e2c95c9810 fpscr=00000000
+vselge.f32 s15,s16,s20 e13dfe910a3e0f7c75cb0842b95ed64d fcb0ebfe6ee98ebd1ca893312a54cae7 5b2d5a70a7920a5f45c55f1c9202b76d 2a54cae70a3e0f7c75cb0842b95ed64d fcb0ebfe6ee98ebd1ca893312a54cae7 5b2d5a70a7920a5f45c55f1c9202b76d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vselge.f32 s15,s16,s20 a86aacf29b0f395c98b463483da65c8c c3ec352e2dac0350f6fd1ca81b6e33c5 e9bf6f37c9e25f72d82e582b73a8f718 1b6e33c59b0f395c98b463483da65c8c c3ec352e2dac0350f6fd1ca81b6e33c5 e9bf6f37c9e25f72d82e582b73a8f718 fpscr=00000000
+vselge.f32 s15,s16,s20 36da9dbf68bc3026343700a654eb2ddd 810e6dc1a1833d8404eb7f0cf4ca6fee b39925ba7d9d67bcff6f850f2c57ea2a f4ca6fee68bc3026343700a654eb2ddd 810e6dc1a1833d8404eb7f0cf4ca6fee b39925ba7d9d67bcff6f850f2c57ea2a fpscr=00000000
+vselge.f32 s15,s16,s20 01737fd22bfa8f668c8b14f436b2a38d 097df30b8daa927a03090dfc6df078b6 6d498492e7e796df010bf4b23b845743 6df078b62bfa8f668c8b14f436b2a38d 097df30b8daa927a03090dfc6df078b6 6d498492e7e796df010bf4b23b845743 fpscr=00000000
+vselge.f32 s15,s16,s20 985e6d08ed19fa045f841810cd8c109e 7bc0131c4a678450562685769ab818a5 8afcb3dfb984aed62671e865e6f21d40 9ab818a5ed19fa045f841810cd8c109e 7bc0131c4a678450562685769ab818a5 8afcb3dfb984aed62671e865e6f21d40 fpscr=00000000
+vselge.f32 s15,s16,s20 c51cdd8f87e12ab4acb722146c6cbfa9 63d7568e3e8a3ac80e048612e51a468e bdf58de2b4a9d799ff5f0c05cb6ebd12 e51a468e87e12ab4acb722146c6cbfa9 63d7568e3e8a3ac80e048612e51a468e bdf58de2b4a9d799ff5f0c05cb6ebd12 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselge.f32 s15,s16,s20 fd8f4d8698c2cb9dfb4ea5d187136489 575775bc3a12029d8e66ea903a12029d e85ef9754842f9c9ba28f82a63b15c68 3a12029d98c2cb9dfb4ea5d187136489 575775bc3a12029d8e66ea903a12029d e85ef9754842f9c9ba28f82a63b15c68 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselge.f32 s15,s16,s20 964fbba0b8d508aebee85fda964fbba0 6809217c310baca0c3837be65197abe2 c0f55f706da71bf2425f9605e2b252c1 5197abe2b8d508aebee85fda964fbba0 6809217c310baca0c3837be65197abe2 c0f55f706da71bf2425f9605e2b252c1 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselge.f32 s15,s16,s20 0c65c22b4ab8778d9ed6d9eb46ea8ca3 82c1007a7d3cd8f54b130cdaa89cef0e 627bb6e12d1f6d4651ef145cb9b83843 a89cef0e4ab8778d9ed6d9eb46ea8ca3 82c1007a7d3cd8f54b130cdaa89cef0e 627bb6e12d1f6d4651ef145cb9b83843 fpscr=00000000
+vselge.f32 s15,s16,s20 3b25bca27a9c69505d14b27d9d16f25b fbbab6a7f19faff0f1798fe3c1699cf0 9f7301c1392d8087d4ba52a206ff21b1 c1699cf07a9c69505d14b27d9d16f25b fbbab6a7f19faff0f1798fe3c1699cf0 9f7301c1392d8087d4ba52a206ff21b1 fpscr=00000000
+vselge.f32 s15,s16,s20 0352a3d92d460a61a5dd0f6f47086cc3 2e9360315bf0177599dbe14b4616559e 3e9e2b92eef2c569453ccd1b0fc40784 4616559e2d460a61a5dd0f6f47086cc3 2e9360315bf0177599dbe14b4616559e 3e9e2b92eef2c569453ccd1b0fc40784 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselge.f32 s15,s16,s20 0facd2b3c4044ef23fb2e22093a48a9d fac555adddf0eb4808f06704c857e949 812abdb289fba268812abdb21e4a9e09 c857e949c4044ef23fb2e22093a48a9d fac555adddf0eb4808f06704c857e949 812abdb289fba268812abdb21e4a9e09 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselge.f32 s15,s16,s20 835e3ede9a220dce0e75e07acb193b9a 3ea20cc00420edac31a0d5992573776d 1e6559138591810713013cc685918107 2573776d9a220dce0e75e07acb193b9a 3ea20cc00420edac31a0d5992573776d 1e6559138591810713013cc685918107 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[0]
+vselge.f32 s15,s16,s20 16ee9afa99500fef6024ba39dce32c23 49e54740570037914d04ab3d57003791 16257132a9f8030aa0dc273ba9f8030a 5700379199500fef6024ba39dce32c23 49e54740570037914d04ab3d57003791 16257132a9f8030aa0dc273ba9f8030a fpscr=00000000
+vselge.f32 s15,s16,s20 865de41295f2db8f44cbbf37e2bc70c3 15ff8f2e73a3a0fae06860b606c7e8c7 4428d9c8833f5b78fb29445f3bc8d7fc 06c7e8c795f2db8f44cbbf37e2bc70c3 15ff8f2e73a3a0fae06860b606c7e8c7 4428d9c8833f5b78fb29445f3bc8d7fc fpscr=00000000
+vselge.f32 s15,s16,s20 f5d7c0f9da7f07e00794eb00b0940ba5 8e212ab7be625608d5abd787f5c90ee7 861576e44fac8dd5bbc503330eb9dd5d f5c90ee7da7f07e00794eb00b0940ba5 8e212ab7be625608d5abd787f5c90ee7 861576e44fac8dd5bbc503330eb9dd5d fpscr=00000000
+vselge.f32 s15,s16,s20 d33d431279cce48fce3d3cc0784c2f85 b1ef0b40d58cb22d00b1125934a781e4 e7467c38bb69a6e1e9a617d4d14e5927 34a781e479cce48fce3d3cc0784c2f85 b1ef0b40d58cb22d00b1125934a781e4 e7467c38bb69a6e1e9a617d4d14e5927 fpscr=00000000
+vselge.f32 s15,s16,s20 b9433f079dacacabeb000208c9029669 20162517609f0f22a1a7a4c9c0a51f6b f763e279a20368bc8bdb3b370954bcbf c0a51f6b9dacacabeb000208c9029669 20162517609f0f22a1a7a4c9c0a51f6b f763e279a20368bc8bdb3b370954bcbf fpscr=00000000
+vselge.f32 s15,s16,s20 60926235021b445ef059e641a1ccb097 136b941e54ffe81c9c7740ef19345795 6930e0fad3ba39c483bd1e68fb03f57b 19345795021b445ef059e641a1ccb097 136b941e54ffe81c9c7740ef19345795 6930e0fad3ba39c483bd1e68fb03f57b fpscr=00000000
+vselge.f32 s15,s16,s20 677f96a350623139cb7207e36cbf75aa 5f927f2b383caf8484c5f3078d2aded7 31aa6a1e5e366d4c1cd56194c94a4e2c 8d2aded750623139cb7207e36cbf75aa 5f927f2b383caf8484c5f3078d2aded7 31aa6a1e5e366d4c1cd56194c94a4e2c fpscr=00000000
+vselge.f32 s15,s16,s20 ed4f4db5a9377eb31749ef710cf75788 924816791f1030333fb8fa4b2feb05cb 99bb3fa4c2385e4166df2141ad63a876 2feb05cba9377eb31749ef710cf75788 924816791f1030333fb8fa4b2feb05cb 99bb3fa4c2385e4166df2141ad63a876 fpscr=00000000
+vselge.f32 s15,s16,s20 8f1ee978efa4b054d2bc36ca100a4a3a b4e706a17746411ab40c9f043af6a1ae 88ae0d34fa174f9ce927c476f140aa41 3af6a1aeefa4b054d2bc36ca100a4a3a b4e706a17746411ab40c9f043af6a1ae 88ae0d34fa174f9ce927c476f140aa41 fpscr=00000000
+vselge.f32 s15,s16,s20 cd123e19cf1e2bb001f1161e946f5ca7 d5f13a9ab645e140698bec649583f5aa 5a5e86033374552e23ce8e2455e0205c 9583f5aacf1e2bb001f1161e946f5ca7 d5f13a9ab645e140698bec649583f5aa 5a5e86033374552e23ce8e2455e0205c fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselge.f32 s15,s16,s20 cf82c7aff819714a711ce1284318b884 a88e7b2818210760c299b42e1fdcc2e9 2ef114ddd37570e82d39fd95a9f5a45d 1fdcc2e9f819714a711ce1284318b884 a88e7b2818210760c299b42e1fdcc2e9 2ef114ddd37570e82d39fd95a9f5a45d fpscr=00000000
+vselge.f32 s15,s16,s20 0a9c61f55fce335d68e1a25652a804a7 1dd493f59184345437d5e366d0e20c30 81c50f1401e45b82d3086a7a39a1e621 d0e20c305fce335d68e1a25652a804a7 1dd493f59184345437d5e366d0e20c30 81c50f1401e45b82d3086a7a39a1e621 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vselge.f32 s15,s16,s20 370813738219ffced22c62cba0822c4c 7c7642a20df9d4ec68f21f468712f7b8 bba1a11cc04c89478209dbbd84d92508 8712f7b88219ffced22c62cba0822c4c 7c7642a20df9d4ec68f21f468712f7b8 bba1a11cc04c89478209dbbd84d92508 fpscr=00000000
+vselge.f32 s15,s16,s20 291541139c8b1cd0d1a11d81326f4e78 44c930c9028972f8733d11f7fa4450de b8ddd8a1cd852d9cd970502d146432e6 fa4450de9c8b1cd0d1a11d81326f4e78 44c930c9028972f8733d11f7fa4450de b8ddd8a1cd852d9cd970502d146432e6 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vselge.f32 s15,s16,s20 470887bfdd3daf94d7265949ca62b46a d3a0a41fce854ae735e7926e777aa43f b3ef9f8c927c405d2fb2ed4ecc1e172d 777aa43fdd3daf94d7265949ca62b46a d3a0a41fce854ae735e7926e777aa43f b3ef9f8c927c405d2fb2ed4ecc1e172d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[2] = v->u32[1]
+vselge.f32 s15,s16,s20 cdc14f0bcdc14f0bf7ba2283e22a3104 4e0cf0fdf0aee1dda4e888e2774acbc1 61e618f30110c432a534d0478d5d7e05 774acbc1cdc14f0bf7ba2283e22a3104 4e0cf0fdf0aee1dda4e888e2774acbc1 61e618f30110c432a534d0478d5d7e05 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+vselge.f32 s15,s16,s20 57805ff098ce3ed14b62bbc77143b71e 0d2c018b8415100484151004ff355bf0 11edd5a106e2d655f9b97953917f469f ff355bf098ce3ed14b62bbc77143b71e 0d2c018b8415100484151004ff355bf0 11edd5a106e2d655f9b97953917f469f fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vselge.f32 s15,s16,s20 d5da99d2eec5040fc700120f62ee9b23 bc58f8b23fcabf6982b029b396ea4f1e 7d2c86fa7c09a37b813bf15120fbc868 96ea4f1eeec5040fc700120f62ee9b23 bc58f8b23fcabf6982b029b396ea4f1e 7d2c86fa7c09a37b813bf15120fbc868 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vselge.f32 s15,s16,s20 c997070e67232e66c997070e860c39c5 5073109cfa471afbe686e2ede96f8809 4df8929c4e1bb03ba56adb474e1bb03b e96f880967232e66c997070e860c39c5 5073109cfa471afbe686e2ede96f8809 4df8929c4e1bb03ba56adb474e1bb03b fpscr=00000000
+vselge.f32 s15,s16,s20 59f634f791559ff8d881612a1f00ed91 1add7938e3067d74917c37833edb866b b3448c8c9a654f1c8c8db3b639e1fba1 3edb866b91559ff8d881612a1f00ed91 1add7938e3067d74917c37833edb866b b3448c8c9a654f1c8c8db3b639e1fba1 fpscr=00000000
+vselge.f32 s15,s16,s20 4cb8e76fcc086aeb0414a9cd126c0869 7b85bbd973ba438b80fdb556878af3ad a6cb98bf6fa194a173e020c0ede3baf2 878af3adcc086aeb0414a9cd126c0869 7b85bbd973ba438b80fdb556878af3ad a6cb98bf6fa194a173e020c0ede3baf2 fpscr=00000000
+vselge.f32 s15,s16,s20 65b86284a1cb27a371a4885bc70f501c 2468a718ec4422710c95a6e59e2a7fab bfaf26fbc229d962e2d7a20cab554a62 9e2a7faba1cb27a371a4885bc70f501c 2468a718ec4422710c95a6e59e2a7fab bfaf26fbc229d962e2d7a20cab554a62 fpscr=00000000
+vselge.f32 s15,s16,s20 ad8f313a964967940f284cfce9a33028 738ec585d726b8f4ecb95e02f1d179e3 af5de4ddb013d258a082f55bbf17ae91 f1d179e3964967940f284cfce9a33028 738ec585d726b8f4ecb95e02f1d179e3 af5de4ddb013d258a082f55bbf17ae91 fpscr=00000000
+vselge.f32 s15,s16,s20 d04c2dd1910bd9cf5599014e9dc435b3 95b85f1c30562ca02ba32b169299fd64 09cb539549408a57d0e8a18b5417adc6 9299fd64910bd9cf5599014e9dc435b3 95b85f1c30562ca02ba32b169299fd64 09cb539549408a57d0e8a18b5417adc6 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselge.f32 s15,s16,s20 4954977124406c74e81e7aa9430469f9 d9438203e383314ed9438203c8655800 aaba95edd88623fc68d5d5d393ccbadd c865580024406c74e81e7aa9430469f9 d9438203e383314ed9438203c8655800 aaba95edd88623fc68d5d5d393ccbadd fpscr=00000000
+vselge.f32 s15,s16,s20 7d1161203b947b8f0a536415b779aada f56dfe15b7e82632fc79b30f1483e79b b34432fe82493fa5c4d84771e518605a 1483e79b3b947b8f0a536415b779aada f56dfe15b7e82632fc79b30f1483e79b b34432fe82493fa5c4d84771e518605a fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: 256 calls, 265 iters
+vselge.f32 s15,s16,s20 36ba0ab0c81fb7053f6b55d4eaedef93 29b247cac4e8bba2bda130508cf3c5a6 9e8fbc053bc4d999db7390839e8fbc05 8cf3c5a6c81fb7053f6b55d4eaedef93 29b247cac4e8bba2bda130508cf3c5a6 9e8fbc053bc4d999db7390839e8fbc05 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselge.f32 s15,s16,s20 8dbd4545a92ebc1d99f6f68da34afe4e f4dd02230b0b9f6018e987aeba97106b 2f35968b0a9d5fe4af824eabd8f8f577 ba97106ba92ebc1d99f6f68da34afe4e f4dd02230b0b9f6018e987aeba97106b 2f35968b0a9d5fe4af824eabd8f8f577 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselge.f32 s15,s16,s20 3951f70edbe25a9a3951f70e8dc88216 5ee9b286181efe1783322bd1f4a0a92e d4a3445ee5f0714d6ed9d5a9ea9b3880 f4a0a92edbe25a9a3951f70e8dc88216 5ee9b286181efe1783322bd1f4a0a92e d4a3445ee5f0714d6ed9d5a9ea9b3880 fpscr=00000000
+vselge.f32 s15,s16,s20 0c4e5ddd66c8f02281b3c8f26eeb8d90 d9407ecd6355d7239077cddd8edc2316 ddf6d8b991ce01deaf4923243fc0b6d3 8edc231666c8f02281b3c8f26eeb8d90 d9407ecd6355d7239077cddd8edc2316 ddf6d8b991ce01deaf4923243fc0b6d3 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselge.f32 s15,s16,s20 fa6db7a39486894259f1290efa6db7a3 e3a4469f24fe98dc158b24fec4bafee7 451c6eb3e447d1587d7aa579647d6dc0 c4bafee79486894259f1290efa6db7a3 e3a4469f24fe98dc158b24fec4bafee7 451c6eb3e447d1587d7aa579647d6dc0 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[1] = v->u32[3]
+vselge.f32 s15,s16,s20 1fc8f3fa1382738f705b685c54d57186 75f5144ccc5e105c99661df92e3cc13e 8597b02c9c423a147ae28aed9c423a14 2e3cc13e1382738f705b685c54d57186 75f5144ccc5e105c99661df92e3cc13e 8597b02c9c423a147ae28aed9c423a14 fpscr=00000000
+vselge.f32 s15,s16,s20 406068505c979f40cdc58392364fbbe2 6feefdf8d22d16a827667197b8d187cb d8c318f5aa57d04b750405c33deba68d b8d187cb5c979f40cdc58392364fbbe2 6feefdf8d22d16a827667197b8d187cb d8c318f5aa57d04b750405c33deba68d fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vselge.f32 s15,s16,s20 9f8c3175b6b243e17860dbd798f8ac48 e87ea00ccf8549bf47029a37d75b1941 02f1b3c72ff97f68cd517cb92b46de01 d75b1941b6b243e17860dbd798f8ac48 e87ea00ccf8549bf47029a37d75b1941 02f1b3c72ff97f68cd517cb92b46de01 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 7dea6f8ae74d5f797dea6f8ae74d5f79 4d15989216cc2891c94f65dfccc66f9e 312d32f1bb069e61ab09c2f3335970be c94f65dfccc66f9e7dea6f8ae74d5f79 4d15989216cc2891c94f65dfccc66f9e 312d32f1bb069e61ab09c2f3335970be fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 20326a7d927f8ecd4a783d658932e026 8b97fa553a6508ac8b97fa553a6508ac 470818041ac5e9b218db305838ff3248 8b97fa553a6508ac4a783d658932e026 8b97fa553a6508ac8b97fa553a6508ac 470818041ac5e9b218db305838ff3248 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 18eb39be527594f68adebded1af4c541 78e95f7a8aed8854faa096b85e32ad5a 699f129680a985484a52397b894a4f49 faa096b85e32ad5a8adebded1af4c541 78e95f7a8aed8854faa096b85e32ad5a 699f129680a985484a52397b894a4f49 fpscr=00000000
+vselge.f64 d7, d8, d10 7c44fda2c4f3ed4e66c03150c383fd2d 1e27c81bff702749760afcca34c46a4a e35ab00b3cdf75747e60035ee161b2dd 760afcca34c46a4a66c03150c383fd2d 1e27c81bff702749760afcca34c46a4a e35ab00b3cdf75747e60035ee161b2dd fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 8f72bc6577b145aeabe876d3472e35c6 28f38b2e093fbce08c1f71338e7c577f 5bc30eedfc43f567c87be936badd6630 8c1f71338e7c577fabe876d3472e35c6 28f38b2e093fbce08c1f71338e7c577f 5bc30eedfc43f567c87be936badd6630 fpscr=00000000
+vselge.f64 d7, d8, d10 95df08065206478d94b3ff795f122865 6c7f80e89ebd80a5e34bca20163ac21e c2e06c5cc8e1357d72cece7967d1f50c e34bca20163ac21e94b3ff795f122865 6c7f80e89ebd80a5e34bca20163ac21e c2e06c5cc8e1357d72cece7967d1f50c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 ac79a338e2ed6bf4b500d2fe8f552735 244c1dcf60e0190c026f4f4108bb97f1 fce910c815b7b5082a07b97ea580d954 026f4f4108bb97f1b500d2fe8f552735 244c1dcf60e0190c026f4f4108bb97f1 fce910c815b7b5082a07b97ea580d954 fpscr=00000000
+vselge.f64 d7, d8, d10 b164b81a015d181eb0d13422c035a6a7 2b0bfdbeddb488c900901dc5368c3595 cf2d05af86747edec1b4c5c4fa8650fe 00901dc5368c3595b0d13422c035a6a7 2b0bfdbeddb488c900901dc5368c3595 cf2d05af86747edec1b4c5c4fa8650fe fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 1d637d751dfa1352e40c986744421113 a6b7393576df5c23d344e7279f0d2317 a06b4f801c40c9e0a06b4f801c40c9e0 d344e7279f0d2317e40c986744421113 a6b7393576df5c23d344e7279f0d2317 a06b4f801c40c9e0a06b4f801c40c9e0 fpscr=00000000
+vselge.f64 d7, d8, d10 c509a7178875c1b1aa5552bf7b541645 e0332c6ed78e2afc4561d270bed6b68a 313cbec68670df4e1ab8e17b2178e568 4561d270bed6b68aaa5552bf7b541645 e0332c6ed78e2afc4561d270bed6b68a 313cbec68670df4e1ab8e17b2178e568 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 9a9e84669a985ec5f0031343f3185309 4ad64de91c16da21aeefac01e48b55d9 fee0b45668b52a09fee0b45668b52a09 aeefac01e48b55d9f0031343f3185309 4ad64de91c16da21aeefac01e48b55d9 fee0b45668b52a09fee0b45668b52a09 fpscr=00000000
+vselge.f64 d7, d8, d10 1a1256ba10a38a2b40833c5f6109ca65 a98a0320fe506fd007449d8620c34d90 310e98e167b9e8f5f99ff99706c8eb8a 07449d8620c34d9040833c5f6109ca65 a98a0320fe506fd007449d8620c34d90 310e98e167b9e8f5f99ff99706c8eb8a fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 8f17393d14b564cbe1d0c0b48a0655b1 d04fb16a4d20867d3a5b4dbd6dd8955f d94d188902284fdfd94d188902284fdf 3a5b4dbd6dd8955fe1d0c0b48a0655b1 d04fb16a4d20867d3a5b4dbd6dd8955f d94d188902284fdfd94d188902284fdf fpscr=00000000
+vselge.f64 d7, d8, d10 442729db00c06ec7a888afd71cbfd9a5 a748e3f1cf4820c03b24f10f9cc602e6 ed8c329e49985ce0a08d4e504c0d1ea8 3b24f10f9cc602e6a888afd71cbfd9a5 a748e3f1cf4820c03b24f10f9cc602e6 ed8c329e49985ce0a08d4e504c0d1ea8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 4ce7b072a07d2e1c4ce7b072a07d2e1c 224c09e6f9f4b7ac224c09e6f9f4b7ac 30603637c27a144a5b20f8ab9814aff9 224c09e6f9f4b7ac4ce7b072a07d2e1c 224c09e6f9f4b7ac224c09e6f9f4b7ac 30603637c27a144a5b20f8ab9814aff9 fpscr=00000000
+vselge.f64 d7, d8, d10 2f46b6a224a9b26dfb35eb12d4ad50bc f46bdce9dd4c503b8c78011defefc04a c3a1b08243033786b7c84ab17d3be225 8c78011defefc04afb35eb12d4ad50bc f46bdce9dd4c503b8c78011defefc04a c3a1b08243033786b7c84ab17d3be225 fpscr=00000000
+vselge.f64 d7, d8, d10 35623ea06909e69bf4ae69f33c480a53 33f2cc7dd6bb9c2cca197db5feb72438 31b5254262bdc16b771596f6d81f3374 ca197db5feb72438f4ae69f33c480a53 33f2cc7dd6bb9c2cca197db5feb72438 31b5254262bdc16b771596f6d81f3374 fpscr=00000000
+vselge.f64 d7, d8, d10 eb0e45f4f7eae27ec0f14ecb50a5fc04 f684562c36ddb9ea8ea8c8d0e79a950e abba23c025e6d5d2e99c2ac801d7a6e2 8ea8c8d0e79a950ec0f14ecb50a5fc04 f684562c36ddb9ea8ea8c8d0e79a950e abba23c025e6d5d2e99c2ac801d7a6e2 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 2c1b224d3e4395de8b5fc46113474bc4 8283f87c7f421f4912638e4626edfac3 beaf642702c9ac2087e109bc0d20ad2c 12638e4626edfac38b5fc46113474bc4 8283f87c7f421f4912638e4626edfac3 beaf642702c9ac2087e109bc0d20ad2c fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 23439e5525914b7f6c80ce6328d14c4f 3b879f7ed58417a23b879f7ed58417a2 4ea3f35b274283763483e142978babb4 3b879f7ed58417a26c80ce6328d14c4f 3b879f7ed58417a23b879f7ed58417a2 4ea3f35b274283763483e142978babb4 fpscr=00000000
+vselge.f64 d7, d8, d10 d5f625fee533c9ac40c2027b6ef50219 26cce3d22e428611c200d10412f69ba3 de0fee83708cf6737d9e7877b9a3b333 c200d10412f69ba340c2027b6ef50219 26cce3d22e428611c200d10412f69ba3 de0fee83708cf6737d9e7877b9a3b333 fpscr=00000000
+vselge.f64 d7, d8, d10 e524262020669f6fdacc5d7113531763 b17d7d8194a0538e824a418418f0b958 2737c8cbeddc2b312ce5ddc92aa7904e 824a418418f0b958dacc5d7113531763 b17d7d8194a0538e824a418418f0b958 2737c8cbeddc2b312ce5ddc92aa7904e fpscr=00000000
+vselge.f64 d7, d8, d10 cd19a8f37bb80620d01d92b83e4c403a 6692a424fc88e808604c7cfc2a781815 38b0aec1474b46a8d94636311f444222 604c7cfc2a781815d01d92b83e4c403a 6692a424fc88e808604c7cfc2a781815 38b0aec1474b46a8d94636311f444222 fpscr=00000000
+vselge.f64 d7, d8, d10 5818643e888b037969929732973d033b 797f021438844d02a38f5943215d8ac5 7b9f006ce9dcecb04919610958335bce a38f5943215d8ac569929732973d033b 797f021438844d02a38f5943215d8ac5 7b9f006ce9dcecb04919610958335bce fpscr=00000000
+vselge.f64 d7, d8, d10 c616893fedf747e7e3b7188215a149fe d247bb0dec2ea57f37c5af844c56a6d2 c282024505efe2bb5e680f8bd808d4a0 37c5af844c56a6d2e3b7188215a149fe d247bb0dec2ea57f37c5af844c56a6d2 c282024505efe2bb5e680f8bd808d4a0 fpscr=00000000
+vselge.f64 d7, d8, d10 20e1106551b53bb68b07cdad1dcc957f 368e1cc3188fca46c4038221f7f38807 ce16f2bacbea6990f0908c45fcf43e06 c4038221f7f388078b07cdad1dcc957f 368e1cc3188fca46c4038221f7f38807 ce16f2bacbea6990f0908c45fcf43e06 fpscr=00000000
+vselge.f64 d7, d8, d10 fcb5b0988ed3ed6fa5a46224d78477c5 debd8d75ea60e0a4508b474b138ad250 4f0c6dd2c295409d0d24fbf1bd35c236 508b474b138ad250a5a46224d78477c5 debd8d75ea60e0a4508b474b138ad250 4f0c6dd2c295409d0d24fbf1bd35c236 fpscr=00000000
+vselge.f64 d7, d8, d10 3bd347680aaab4228a0b10877f5c8727 291397a9ba7f9e19ccd6b6f28eac089f 8eb45934c0c5bf89c26cb8dce73ec9b8 ccd6b6f28eac089f8a0b10877f5c8727 291397a9ba7f9e19ccd6b6f28eac089f 8eb45934c0c5bf89c26cb8dce73ec9b8 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 b10a44033e825486b10a44033e825486 653ab778fcbada2d54bed9dca1146904 9f4d651fe1890b769f4d651fe1890b76 54bed9dca1146904b10a44033e825486 653ab778fcbada2d54bed9dca1146904 9f4d651fe1890b769f4d651fe1890b76 fpscr=00000000
+vselge.f64 d7, d8, d10 c8011cc8a7dc73ed183713208e6e2a22 54ff526986b9c7d9eb61d469d49e0a48 f0846cae958bbf1fe8e9bb56dee959ba eb61d469d49e0a48183713208e6e2a22 54ff526986b9c7d9eb61d469d49e0a48 f0846cae958bbf1fe8e9bb56dee959ba fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 b8782ccb88336084b8782ccb88336084 742ef9b0a22bd197c376de3baf5fdb8c 69c662988b5f5746fb941b276fefe9c6 c376de3baf5fdb8cb8782ccb88336084 742ef9b0a22bd197c376de3baf5fdb8c 69c662988b5f5746fb941b276fefe9c6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 b20c2785c541876db20c2785c541876d 032db762c30b75b069dea946e0b179be 181f0f0b8f5d0353bc2f2ffdc2c55b0f 69dea946e0b179beb20c2785c541876d 032db762c30b75b069dea946e0b179be 181f0f0b8f5d0353bc2f2ffdc2c55b0f fpscr=00000000
+vselge.f64 d7, d8, d10 3c09c110a7a3ccf943504995e94a77e4 d2893ae6ff22b433bbdde4c7ff080c84 f49e747ba1b053546a8f11cbec2196ce bbdde4c7ff080c8443504995e94a77e4 d2893ae6ff22b433bbdde4c7ff080c84 f49e747ba1b053546a8f11cbec2196ce fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 0fa9ad03d399277fd05ca4f26ef8025f 512005ca47f71b72512005ca47f71b72 8f37f9d4b7c27dfe029229e0fac199e9 512005ca47f71b72d05ca4f26ef8025f 512005ca47f71b72512005ca47f71b72 8f37f9d4b7c27dfe029229e0fac199e9 fpscr=00000000
+vselge.f64 d7, d8, d10 fcb4b3e7a908c6d194412d3c5bdb13e5 3155405557892d6649f507b77e997223 aa1a958555027b09baf22fda37cd3760 49f507b77e99722394412d3c5bdb13e5 3155405557892d6649f507b77e997223 aa1a958555027b09baf22fda37cd3760 fpscr=00000000
+randV128: 512 calls, 530 iters
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 d44486b5a6a102107e8ef40422303b1b db5aa202e2121f7aa8d894a9c470d958 326c6c233ef813ba0fe17c5753958e24 a8d894a9c470d9587e8ef40422303b1b db5aa202e2121f7aa8d894a9c470d958 326c6c233ef813ba0fe17c5753958e24 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 d6af490cad91217056d5748db6b4df58 16edd04b278464bc28f0c8ad90647a74 9666b4d4f37549976fb022ffaa75e46d 28f0c8ad90647a7456d5748db6b4df58 16edd04b278464bc28f0c8ad90647a74 9666b4d4f37549976fb022ffaa75e46d fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 ac07cce3ec6d05a4b6a1a4cd9e883257 e901fcadd70937b3956de6fb929444b1 1e83edc02ffa57cb1e83edc02ffa57cb 956de6fb929444b1b6a1a4cd9e883257 e901fcadd70937b3956de6fb929444b1 1e83edc02ffa57cb1e83edc02ffa57cb fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 e04f0d4312973a16fac0656f27a1a7bb 5e17e0b2d6d57a7db0e9535f056177dd b90e2f84fd0f2387b90e2f84fd0f2387 b0e9535f056177ddfac0656f27a1a7bb 5e17e0b2d6d57a7db0e9535f056177dd b90e2f84fd0f2387b90e2f84fd0f2387 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 5e44b0f9e0d5b9fa370241a91527f6b9 011bb2a0f5f10f15717d72120cd2c993 d9dbad27f70c3901ccb48a7230203299 717d72120cd2c993370241a91527f6b9 011bb2a0f5f10f15717d72120cd2c993 d9dbad27f70c3901ccb48a7230203299 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 f7d359b0d13fcfb804169a04d2f81662 6e74cdf571f9829134f3548dd9540466 98627c5eefe64192b7f7857aad810a9a 34f3548dd954046604169a04d2f81662 6e74cdf571f9829134f3548dd9540466 98627c5eefe64192b7f7857aad810a9a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 8d2b6b3e8e322a4ff6b6d1b75f0f9fb4 fe476aa231b0aaf9fe476aa231b0aaf9 fe73fd132e37396917085019174d71f9 fe476aa231b0aaf9f6b6d1b75f0f9fb4 fe476aa231b0aaf9fe476aa231b0aaf9 fe73fd132e37396917085019174d71f9 fpscr=00000000
+vselge.f64 d7, d8, d10 ae6674d2fb42f1655f05df749c5f3646 a78d90ffdc91cea49ae5c06573d83b22 5aaa117e7599eb792f879592071e89e2 9ae5c06573d83b225f05df749c5f3646 a78d90ffdc91cea49ae5c06573d83b22 5aaa117e7599eb792f879592071e89e2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 8de9d387376700458de9d38737670045 5d5cd44e174adb00a0567c2a86afc400 0648ac6426460c1c7493622cfa2597b6 a0567c2a86afc4008de9d38737670045 5d5cd44e174adb00a0567c2a86afc400 0648ac6426460c1c7493622cfa2597b6 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 5a9fef0fb2dc303e71375e2906701b0e 403befabe5870936cd45f72008eb890f 08a2f98312aff067d5f03b44cf58f319 cd45f72008eb890f71375e2906701b0e 403befabe5870936cd45f72008eb890f 08a2f98312aff067d5f03b44cf58f319 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselge.f64 d7, d8, d10 3292b01c28f51c80557c76e23b6d7d67 65ba8b51dadbd02a2efc4a4c3cb79f06 0e442a090e2de0df0e442a090e2de0df 2efc4a4c3cb79f06557c76e23b6d7d67 65ba8b51dadbd02a2efc4a4c3cb79f06 0e442a090e2de0df0e442a090e2de0df fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 018a9ded9a32b2b658bb9dccbe78e080 31d4c3802458c320b8e9ef3655324c69 8bf7d8b25706c5dff7abfe7295d6f441 b8e9ef3655324c6958bb9dccbe78e080 31d4c3802458c320b8e9ef3655324c69 8bf7d8b25706c5dff7abfe7295d6f441 fpscr=00000000
+vselge.f64 d7, d8, d10 dc260bdc0b43237ef922696a0f05c22c f20e1dd4b168dbe16ecc3a09dfbd048c 64b651fc046084577ab57fbffe8986a7 6ecc3a09dfbd048cf922696a0f05c22c f20e1dd4b168dbe16ecc3a09dfbd048c 64b651fc046084577ab57fbffe8986a7 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+vselge.f64 d7, d8, d10 de9f39ff175e45afde9f39ff175e45af 1ec7ef10271064461273cbadb462d8dd 5f256ae7f57a25258fdf807367ff0cd7 1273cbadb462d8ddde9f39ff175e45af 1ec7ef10271064461273cbadb462d8dd 5f256ae7f57a25258fdf807367ff0cd7 fpscr=00000000
+vselge.f64 d7, d8, d10 ff3c4b3f064d8c217557cde51027645d 425df6d73059dd837e3e8527449ee9f4 cb297d14227fde7c0f14944c6efdbc0d 7e3e8527449ee9f47557cde51027645d 425df6d73059dd837e3e8527449ee9f4 cb297d14227fde7c0f14944c6efdbc0d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 1bdf8d327099a8084857c13907f4e2b8 cf8ab30ab9b9dc22f7579b2891a81344 9526bc45f7a76187effcd880ce0be4bb 91a813447099a8084857c13907f4e2b8 cf8ab30ab9b9dc22f7579b2891a81344 9526bc45f7a76187effcd880ce0be4bb fpscr=00000000
+vselgt.f32 s15,s16,s20 c9c0b3124ecb70f79979a7ae01844088 2d3ffa9d1614be74a19641dae470df8a f18c6ed01230ff3e8365b8b6c1363c54 e470df8a4ecb70f79979a7ae01844088 2d3ffa9d1614be74a19641dae470df8a f18c6ed01230ff3e8365b8b6c1363c54 fpscr=00000000
+vselgt.f32 s15,s16,s20 eec0a594220beffe1db4b81f2b597541 085f2ae05c723ca7542a15dacc33b1e8 7bc9cbffb9f9c3f1e39422d258859818 cc33b1e8220beffe1db4b81f2b597541 085f2ae05c723ca7542a15dacc33b1e8 7bc9cbffb9f9c3f1e39422d258859818 fpscr=00000000
+vselgt.f32 s15,s16,s20 2d4071b09e34d197ade8b4986d6b0591 ebd55f51b7352d94362d6f4fc8df6c3a 7f23ae157d67454552a7246adc911c23 c8df6c3a9e34d197ade8b4986d6b0591 ebd55f51b7352d94362d6f4fc8df6c3a 7f23ae157d67454552a7246adc911c23 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[2]
+vselgt.f32 s15,s16,s20 e81f605f6011b79f6011b79f7a8390a6 90a557fdbc7d9bd9764c8b686f3a23b6 0ef0bee102374fafd4e3e2ff7367dd2b 6f3a23b66011b79f6011b79f7a8390a6 90a557fdbc7d9bd9764c8b686f3a23b6 0ef0bee102374fafd4e3e2ff7367dd2b fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 b2aa237461d97084eb06887153eff01a c9cfa6ab4754a2195bd22fb34754a219 895df1dcc89783ffad7ef35a4cf4eb6b 4754a21961d97084eb06887153eff01a c9cfa6ab4754a2195bd22fb34754a219 895df1dcc89783ffad7ef35a4cf4eb6b fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vselgt.f32 s15,s16,s20 70670d2b81b02e0f0a0edcee4d2cc878 18e8bf66df043a12308c280e5e7c1153 7d4ca4d5e89f7a600a82ee30cd29d94c 5e7c115381b02e0f0a0edcee4d2cc878 18e8bf66df043a12308c280e5e7c1153 7d4ca4d5e89f7a600a82ee30cd29d94c fpscr=00000000
+vselgt.f32 s15,s16,s20 d9bdcc893028e602d73eb2831f4bf609 1a6853f6be84f8bb673f4fc8c387756f 6d6a3f50029353f1b5ac7f6f455b745c c387756f3028e602d73eb2831f4bf609 1a6853f6be84f8bb673f4fc8c387756f 6d6a3f50029353f1b5ac7f6f455b745c fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 1e876212d6c92a1344cea455fc4eef9f f57b7629851fcfdef394463cd1c7914d f11f910033957a94279b0a97cbc7ac5e d1c7914dd6c92a1344cea455fc4eef9f f57b7629851fcfdef394463cd1c7914d f11f910033957a94279b0a97cbc7ac5e fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+vselgt.f32 s15,s16,s20 7bcc8918719010b51f8d0a9a7bcc8918 f209e1392f0631401ae5027aa91a00bc 605a3bd8bf3e07b2c2da04a6f33908f3 a91a00bc719010b51f8d0a9a7bcc8918 f209e1392f0631401ae5027aa91a00bc 605a3bd8bf3e07b2c2da04a6f33908f3 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+vselgt.f32 s15,s16,s20 76795aaf7a3a63326053ff312e26dd2d 1cef651c6c49c9b9c3455d9993e4a5f1 753e762872ee82410613768d72ee8241 93e4a5f17a3a63326053ff312e26dd2d 1cef651c6c49c9b9c3455d9993e4a5f1 753e762872ee82410613768d72ee8241 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 0f86961d0dfe0e02951a8f772c44efed 22fc2fbc3120de9c6479e10d450f9d06 7879495083fdabe878794950fd4f567a 450f9d060dfe0e02951a8f772c44efed 22fc2fbc3120de9c6479e10d450f9d06 7879495083fdabe878794950fd4f567a fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vselgt.f32 s15,s16,s20 24672c54caa9aa633342e0b5d4f4aeda 19278d62f4b822f982cef9da2674b1f9 c3e2025a96a7091a1f4f5923c556de8f 2674b1f9caa9aa633342e0b5d4f4aeda 19278d62f4b822f982cef9da2674b1f9 c3e2025a96a7091a1f4f5923c556de8f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 015af8db989c4ca73ffe15972ad99232 3038d0cec7409e243038d0ce7b07f98f 1855d89a262a1b0a53270c4dcc860398 7b07f98f989c4ca73ffe15972ad99232 3038d0cec7409e243038d0ce7b07f98f 1855d89a262a1b0a53270c4dcc860398 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vselgt.f32 s15,s16,s20 2dee1843b5e8784c7c8c4889516eeebe 617c8954617c8954a5cbcde8d1860844 0b85da88ee6240d4fab6c9afe737c931 d1860844b5e8784c7c8c4889516eeebe 617c8954617c8954a5cbcde8d1860844 0b85da88ee6240d4fab6c9afe737c931 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 7908d297e250bfd0beb18ef33bda55a8 c02a0d5fff7bec35055605a42bdaf0c7 3ec6594828ea00ce852ad4015bd9be35 2bdaf0c7e250bfd0beb18ef33bda55a8 c02a0d5fff7bec35055605a42bdaf0c7 3ec6594828ea00ce852ad4015bd9be35 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+vselgt.f32 s15,s16,s20 8811bde81e25ab197c2f544bc3a505c0 5b031ff9e7ae8c119c803647a19ed837 c65eabd1c65eabd1fd787344eab396a5 a19ed8371e25ab197c2f544bc3a505c0 5b031ff9e7ae8c119c803647a19ed837 c65eabd1c65eabd1fd787344eab396a5 fpscr=00000000
+vselgt.f32 s15,s16,s20 9a8034e6e3ed64baedc4d347f131748c 173f4b15840aefbd68c882e0ba868812 92595c78dc164f3e6b0b450ee14a3f63 ba868812e3ed64baedc4d347f131748c 173f4b15840aefbd68c882e0ba868812 92595c78dc164f3e6b0b450ee14a3f63 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 c1646445ad3ed3b57d49d58462983027 4114a950baae5dda57a6295a9c342f97 0c48c120052fffdbd7daec0268b166e8 9c342f97ad3ed3b57d49d58462983027 4114a950baae5dda57a6295a9c342f97 0c48c120052fffdbd7daec0268b166e8 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 4f4243ae39614780efa667b5aedab485 05b02563c9fa6eef4b33b2ee05b02563 fcaee0ded12dca0df26a17d4498d2688 05b0256339614780efa667b5aedab485 05b02563c9fa6eef4b33b2ee05b02563 fcaee0ded12dca0df26a17d4498d2688 fpscr=00000000
+vselgt.f32 s15,s16,s20 de7208c800b715da12557654765782b0 f0d64bb3c491e2964c871592462727ca f3b17280fe8bd0af2574688c737559b2 462727ca00b715da12557654765782b0 f0d64bb3c491e2964c871592462727ca f3b17280fe8bd0af2574688c737559b2 fpscr=00000000
+vselgt.f32 s15,s16,s20 1c44b8009d306bbad4fdc8b28c2e7caa 8a171d1a294d48dac018701d2c9c4cc5 adf8d51b36a1754467de8de308363b05 2c9c4cc59d306bbad4fdc8b28c2e7caa 8a171d1a294d48dac018701d2c9c4cc5 adf8d51b36a1754467de8de308363b05 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 1a8250dd1a8250ddf0ce0ae3dd1fb618 34ff9e689545c592399af877a2488f5a 912f8374159df2f7085589b343d21f25 a2488f5a1a8250ddf0ce0ae3dd1fb618 34ff9e689545c592399af877a2488f5a 912f8374159df2f7085589b343d21f25 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 e0fab6f1097a591efbe94e37d632c5c5 18b62fb46893080a18b62fb42368e72c b80b650cfe693570ed7e83558122a32f 2368e72c097a591efbe94e37d632c5c5 18b62fb46893080a18b62fb42368e72c b80b650cfe693570ed7e83558122a32f fpscr=00000000
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 33bddc2fc7a026fecd171aec33bddc2f b1a4ca4f181791f3d454c04f06a53778 c68c6485c6adf116dec9468c558d9860 06a53778c7a026fecd171aec33bddc2f b1a4ca4f181791f3d454c04f06a53778 c68c6485c6adf116dec9468c558d9860 fpscr=00000000
+vselgt.f32 s15,s16,s20 29a983126fa213d785a320168623013c 5683bcd06b852bf92251cb35169b864d 815ea08ffe762184b4b96d2e26a96f0d 169b864d6fa213d785a320168623013c 5683bcd06b852bf92251cb35169b864d 815ea08ffe762184b4b96d2e26a96f0d fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 c1138d54839bd88d84ce1ec208da666e 5c7e82920db77e6cea21645ba286f1eb 54bf2328bcdbe96673dca83ac0d55211 a286f1eb839bd88d84ce1ec208da666e 5c7e82920db77e6cea21645ba286f1eb 54bf2328bcdbe96673dca83ac0d55211 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+randV128: doing v->u32[2] = v->u32[3]
+randV128: doing v->u32[0] = v->u32[2]
+randV128: doing v->u32[3] = v->u32[1]
+randV128: 768 calls, 799 iters
+vselgt.f32 s15,s16,s20 cf8ff14acf8ff14a5a254e46354122d6 465c83497b47d5b77f61bafe67d20d3b 322ae60a0d6cd20b6d770c50d4ac6c0d 67d20d3bcf8ff14a5a254e46354122d6 465c83497b47d5b77f61bafe67d20d3b 322ae60a0d6cd20b6d770c50d4ac6c0d fpscr=00000000
+vselgt.f32 s15,s16,s20 1fb513253fbf0bbad8c8679e1814cac1 8d162d9b0d5f9d85c79bcbad7f7df9d3 a11e8b73b8f2cb4a028bdedbd8609b86 7f7df9d33fbf0bbad8c8679e1814cac1 8d162d9b0d5f9d85c79bcbad7f7df9d3 a11e8b73b8f2cb4a028bdedbd8609b86 fpscr=00000000
+vselgt.f32 s15,s16,s20 9a660dfbf22d561be6f39a2c0cfb3058 7a7b4e2ba2eb89d3b39f1de9625c24b1 ea603563102a8d410ebd081fb5bb3711 625c24b1f22d561be6f39a2c0cfb3058 7a7b4e2ba2eb89d3b39f1de9625c24b1 ea603563102a8d410ebd081fb5bb3711 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 56ee33f7ac3926cc5df566ae80e65d3a 20e931e49bb2bad46a21352852c83b9f e4841621bb7f912713317dcabb7f9127 52c83b9fac3926cc5df566ae80e65d3a 20e931e49bb2bad46a21352852c83b9f e4841621bb7f912713317dcabb7f9127 fpscr=00000000
+vselgt.f32 s15,s16,s20 eeda52f02c35e59e0949a14bfd2150e7 408c9b2067aa17b9a984144ef62b496d f81b4f5fe03bec2401c8b1f90f4166de f62b496d2c35e59e0949a14bfd2150e7 408c9b2067aa17b9a984144ef62b496d f81b4f5fe03bec2401c8b1f90f4166de fpscr=00000000
+randV128: doing v->u32[2] = v->u32[1]
+randV128: doing v->u32[1] = v->u32[0]
+vselgt.f32 s15,s16,s20 2767dabd36ee9d2036ee9d202debefba 7c7da2b845c144f16c1720c22c991b84 28b1fa34a6deaa2f202ba309356f0684 2c991b8436ee9d2036ee9d202debefba 7c7da2b845c144f16c1720c22c991b84 28b1fa34a6deaa2f202ba309356f0684 fpscr=00000000
+vselgt.f32 s15,s16,s20 e32ad2203fe937d71e545a5fb8b48c3f e604f15032609bb07bb871573e5b1e29 b5f5ec755f52e2ebeaa1e43c6c12f793 3e5b1e293fe937d71e545a5fb8b48c3f e604f15032609bb07bb871573e5b1e29 b5f5ec755f52e2ebeaa1e43c6c12f793 fpscr=00000000
+vselgt.f32 s15,s16,s20 2f9e68b12a89d1a702ab5bb74d390b29 a66de0615ea0d6431181b10449c8c169 dac5cb275692ecb1c505708ac878d540 49c8c1692a89d1a702ab5bb74d390b29 a66de0615ea0d6431181b10449c8c169 dac5cb275692ecb1c505708ac878d540 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+vselgt.f32 s15,s16,s20 cac1d1b9d32d0b7e5bc51a46ecf76376 3d66fcd8901008394c881899882591e9 1ee0af201fb673430704090f5eec3703 882591e9d32d0b7e5bc51a46ecf76376 3d66fcd8901008394c881899882591e9 1ee0af201fb673430704090f5eec3703 fpscr=00000000
+vselgt.f32 s15,s16,s20 efd6c9eeee462c3cb59631d8b85d1010 4f537eee9a86447020bf0b56034fb5f3 c1b02de71711f26e5d3d6fa6ce3475da 034fb5f3ee462c3cb59631d8b85d1010 4f537eee9a86447020bf0b56034fb5f3 c1b02de71711f26e5d3d6fa6ce3475da fpscr=00000000
+randV128: doing v->u32[0] = v->u32[3]
+randV128: doing v->u32[3] = v->u32[0]
+vselgt.f32 s15,s16,s20 b5100402bfc81bac17fee204eeb0cb5c f902c9a2df3e3cb7f382b0f6f902c9a2 087be4a6069c87098acb707f5aac4670 f902c9a2bfc81bac17fee204eeb0cb5c f902c9a2df3e3cb7f382b0f6f902c9a2 087be4a6069c87098acb707f5aac4670 fpscr=00000000
+vselgt.f32 s15,s16,s20 21e7c0a58301ba82fc21ccdd8545b41a d05b994fa60d240d51788bb7e1a16f74 81d0e521e29c6658b2fa89dd9a94fc17 e1a16f748301ba82fc21ccdd8545b41a d05b994fa60d240d51788bb7e1a16f74 81d0e521e29c6658b2fa89dd9a94fc17 fpscr=00000000
+randV128: doing v->u32[2] = v->u32[0]
+vselgt.f32 s15,s16,s20 a724eeacc1578d04928167d0df3f41e1 5f43e64aad74f7bbaf2e023b02afe680 db2e522a3dcd8bb349e538e7dda8ab04 02afe680c1578d04928167d0df3f41e1 5f43e64aad74f7bbaf2e023b02afe680 db2e522a3dcd8bb349e538e7dda8ab04 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+randV128: doing v->u32[0] = v->u32[3]
+vselgt.f32 s15,s16,s20 bc17f33bcf2b9d39f9873247ef89ab93 10fd9f5e8e11ad01dcef0d56315a22fb a4727fdaa4727fda492ed6217b98d440 315a22fbcf2b9d39f9873247ef89ab93 10fd9f5e8e11ad01dcef0d56315a22fb a4727fdaa4727fda492ed6217b98d440 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[1]
+vselgt.f32 s15,s16,s20 deea882120dc114c354a3cedacd46161 5d868c1b95d9e8bc430e287d74b10c3f 56ba6f87ff79947a339de73092581227 74b10c3f20dc114c354a3cedacd46161 5d868c1b95d9e8bc430e287d74b10c3f 56ba6f87ff79947a339de73092581227 fpscr=00000000
+vselgt.f32 s15,s16,s20 273c0d45399c9b122cd84390b7023133 d041932201ece1f76cab44100b00fb70 dd3a9c05382834d243e8102309289f04 0b00fb70399c9b122cd84390b7023133 d041932201ece1f76cab44100b00fb70 dd3a9c05382834d243e8102309289f04 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vselgt.f32 s15,s16,s20 3a753da06a31d380ece50912c7462ffa 1fb72fff96b0fe8e3bae1f8d37e3c323 99ad5ea9a1f602854dcb6e961a321c25 37e3c3236a31d380ece50912c7462ffa 1fb72fff96b0fe8e3bae1f8d37e3c323 99ad5ea9a1f602854dcb6e961a321c25 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[2]
+vselgt.f32 s15,s16,s20 699bc759eb22cacbec75d26340ffddf6 d4b3e72358437eb891e7c38e901fb05a 3513b9ec899de43c17ad36d3ef68f9d7 901fb05aeb22cacbec75d26340ffddf6 d4b3e72358437eb891e7c38e901fb05a 3513b9ec899de43c17ad36d3ef68f9d7 fpscr=00000000
+vselgt.f32 s15,s16,s20 92a297dec2e9e3f6fb6753d7ab516c02 cba562eeb33a849b04af2e6fd3ee34fd 70577cc5c8b316502f90a52952a5b063 d3ee34fdc2e9e3f6fb6753d7ab516c02 cba562eeb33a849b04af2e6fd3ee34fd 70577cc5c8b316502f90a52952a5b063 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[1]
+vselgt.f32 s15,s16,s20 db7c936146eb0499db7c93615aeed631 0b160f8de8964a92b57b5f1836666691 a45c5cba0e542c3521fc5ae2b449f325 3666669146eb0499db7c93615aeed631 0b160f8de8964a92b57b5f1836666691 a45c5cba0e542c3521fc5ae2b449f325 fpscr=00000000
+randV128: doing v->u32[0] = v->u32[2]
+vselgt.f32 s15,s16,s20 c84b61ede9902ac1a3cdc80ab45f90eb 6ffff2e82aa56bb5772724df31a64658 1732c074b63b26eb09d0247b4a28d835 31a64658e9902ac1a3cdc80ab45f90eb 6ffff2e82aa56bb5772724df31a64658 1732c074b63b26eb09d0247b4a28d835 fpscr=00000000
+vselgt.f32 s15,s16,s20 8bc2195ff2ebb5a01b5604b6f74470da c5db529dcff48de39d2cd39e879f7672 90f12aa71dfe62fc52c992dd903d2549 879f7672f2ebb5a01b5604b6f74470da c5db529dcff48de39d2cd39e879f7672 90f12aa71dfe62fc52c992dd903d2549 fpscr=00000000
+vselgt.f32 s15,s16,s20 f8ed04aa9b8d23c1c1a6aef520e286d3 d98c7cf36c568aea8a316fe71b5c2e03 b7bdd5efa809001e348f5988c1f6c82a 1b5c2e039b8d23c1c1a6aef520e286d3 d98c7cf36c568aea8a316fe71b5c2e03 b7bdd5efa809001e348f5988c1f6c82a fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 3f9c61edeb7496cb5e0437a54d260583 1a75ad5ef068bc8f1a75ad5ef068bc8f c9da1823673a07037584747d9f1860e8 1a75ad5ef068bc8f5e0437a54d260583 1a75ad5ef068bc8f1a75ad5ef068bc8f c9da1823673a07037584747d9f1860e8 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 e6136698d2279aa9136d4ada30fb9e4e ee40784b29393714ee40784b29393714 92147f5309d64b4392147f5309d64b43 ee40784b29393714136d4ada30fb9e4e ee40784b29393714ee40784b29393714 92147f5309d64b4392147f5309d64b43 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 65b43f63357ecd40529f337f2d5dda79 608f00c029de3613dbcdea9a46a0b761 4b4c78162e0a6d233614316bfe51ff7d dbcdea9a46a0b761529f337f2d5dda79 608f00c029de3613dbcdea9a46a0b761 4b4c78162e0a6d233614316bfe51ff7d fpscr=00000000
+vselgt.f64 d7, d8, d10 a5fdd4619ca3fbbaaadd3bcfd967e686 dae1eabc617c99524fccee06be57b0cd b602c7a266815d1ae592158f24400e74 4fccee06be57b0cdaadd3bcfd967e686 dae1eabc617c99524fccee06be57b0cd b602c7a266815d1ae592158f24400e74 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 398be9f9968adddb398be9f9968adddb ea0cca19594c6ff82708f45fa473320d 1527459fc84854711527459fc8485471 2708f45fa473320d398be9f9968adddb ea0cca19594c6ff82708f45fa473320d 1527459fc84854711527459fc8485471 fpscr=00000000
+vselgt.f64 d7, d8, d10 c1c79d7644a6cba105d03730bacf1eab 39d0589dbadedc5fb420fa5ec66b8ee2 9473a371e970cd3de35a4e1617453bcb b420fa5ec66b8ee205d03730bacf1eab 39d0589dbadedc5fb420fa5ec66b8ee2 9473a371e970cd3de35a4e1617453bcb fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 0f071e11dcec3cf9516423533673b907 0a24cae5e8b715cc2073569dc2fd10a6 975d9a3a089cacf06c3025f4e8aca8ea 2073569dc2fd10a6516423533673b907 0a24cae5e8b715cc2073569dc2fd10a6 975d9a3a089cacf06c3025f4e8aca8ea fpscr=00000000
+vselgt.f64 d7, d8, d10 7b78995ea148096c521348c82dc23e60 b171946ef6718b834ce1f0729d0b39dd 37ff19ae21793f3502e53752964117a9 4ce1f0729d0b39dd521348c82dc23e60 b171946ef6718b834ce1f0729d0b39dd 37ff19ae21793f3502e53752964117a9 fpscr=00000000
+vselgt.f64 d7, d8, d10 f8cfe8e7d50668236613bf1f9e155c6e e40b49cae43a978153f481b302330083 60f6f31044959089d1fa1c6ad835ba25 53f481b3023300836613bf1f9e155c6e e40b49cae43a978153f481b302330083 60f6f31044959089d1fa1c6ad835ba25 fpscr=00000000
+vselgt.f64 d7, d8, d10 e014b74b3e2d896242658b6cef5c9847 a5dc8513422b757997b8e3e78709360c e9a3c3904619f63f1c4b1b9f42235e7f 97b8e3e78709360c42658b6cef5c9847 a5dc8513422b757997b8e3e78709360c e9a3c3904619f63f1c4b1b9f42235e7f fpscr=00000000
+vselgt.f64 d7, d8, d10 3223bc404be66e836250454c3b390ef5 2920717443688dbee9625eec89f510d5 de7ec0f6e8e8c80e6e12660f94e0c017 e9625eec89f510d56250454c3b390ef5 2920717443688dbee9625eec89f510d5 de7ec0f6e8e8c80e6e12660f94e0c017 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 cba393991642f0124f764588d0158833 ef6f5df4580476feef6f5df4580476fe d9d62b65994cc8a7e6f3a0a57d8b0bb2 ef6f5df4580476fe4f764588d0158833 ef6f5df4580476feef6f5df4580476fe d9d62b65994cc8a7e6f3a0a57d8b0bb2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 4e2f953af06edcdf4e2f953af06edcdf 298bd0f8923b179aed553385d2a045fc 6a50db4f1b9ccfb00ac9f644af6c35b5 ed553385d2a045fc4e2f953af06edcdf 298bd0f8923b179aed553385d2a045fc 6a50db4f1b9ccfb00ac9f644af6c35b5 fpscr=00000000
+vselgt.f64 d7, d8, d10 4ac240cfc8be0f381ae8e01f521ca43e cbcccaa715e279b7db6a963b13c1e3ca 51b853da308a1146e2e32500cd8fd7cb db6a963b13c1e3ca1ae8e01f521ca43e cbcccaa715e279b7db6a963b13c1e3ca 51b853da308a1146e2e32500cd8fd7cb fpscr=00000000
+vselgt.f64 d7, d8, d10 3726b86f381e19ddf1bb3242f811ed9d 5bbc95f9413a82184f5f247e5d780d4a a50633a077162f6cae00d9a9616fd38c 4f5f247e5d780d4af1bb3242f811ed9d 5bbc95f9413a82184f5f247e5d780d4a a50633a077162f6cae00d9a9616fd38c fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 a00a527c7a3e71272144a3295695755d 9a7dff326017a1e19514df37fbf87121 caac6481b790423fcaac6481b790423f 9514df37fbf871212144a3295695755d 9a7dff326017a1e19514df37fbf87121 caac6481b790423fcaac6481b790423f fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 7e63cc59cccbd0a3b1a06db3c73ae0ca 105015f526edba740e2eb08a2a8571c6 e2dc7727337c2dd90fe42aefa4ee5824 0e2eb08a2a8571c6b1a06db3c73ae0ca 105015f526edba740e2eb08a2a8571c6 e2dc7727337c2dd90fe42aefa4ee5824 fpscr=00000000
+vselgt.f64 d7, d8, d10 6340ab234dd474bfd8d4c662fd870459 c41ba68cab6ca586b60aafceb9d47da8 246ebcbf3251632ec2c358364bdd041f b60aafceb9d47da8d8d4c662fd870459 c41ba68cab6ca586b60aafceb9d47da8 246ebcbf3251632ec2c358364bdd041f fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 57d4be27c1a5174d78728950fadd603a 2b62627b86d0bd834973a67642acd16d 38d8d49260898789ecfa86c5322e33ad 4973a67642acd16d78728950fadd603a 2b62627b86d0bd834973a67642acd16d 38d8d49260898789ecfa86c5322e33ad fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 65838ecb00f2cfa75f72d29952a65385 4888ed9f8dfeec004888ed9f8dfeec00 57a35145a25b79f3c74fd35be6ea59de 4888ed9f8dfeec005f72d29952a65385 4888ed9f8dfeec004888ed9f8dfeec00 57a35145a25b79f3c74fd35be6ea59de fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: 1024 calls, 1064 iters
+vselgt.f64 d7, d8, d10 f73708fe5d15565be8ebcc833e0bdb9b 3f4e8875327705273f4e887532770527 5e1fd2dbeff2b0d603a742d668fbec83 3f4e887532770527e8ebcc833e0bdb9b 3f4e8875327705273f4e887532770527 5e1fd2dbeff2b0d603a742d668fbec83 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 e5349918a6f9c50683e46cdc819cfa68 98305776f15e5cf5c8e20f698a92d77d 82daa912c843a17682daa912c843a176 c8e20f698a92d77d83e46cdc819cfa68 98305776f15e5cf5c8e20f698a92d77d 82daa912c843a17682daa912c843a176 fpscr=00000000
+vselgt.f64 d7, d8, d10 7323e8ea339093584e082524b12c5130 01cb88ac89d491f84d4d934bc2448062 46592dddc3c391a4d67da7770a72bf3d 4d4d934bc24480624e082524b12c5130 01cb88ac89d491f84d4d934bc2448062 46592dddc3c391a4d67da7770a72bf3d fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 9e79ad9453d8d768a855ef96dd4b939b a7ea5ccd5933675fd3bd93203fa5ba14 069ba01413e4b550069ba01413e4b550 d3bd93203fa5ba14a855ef96dd4b939b a7ea5ccd5933675fd3bd93203fa5ba14 069ba01413e4b550069ba01413e4b550 fpscr=00000000
+vselgt.f64 d7, d8, d10 e0aecdb528fb1fc3c84278a4d83ca49b 21d698972394a54142cc6e0151dec49a 3fb20d08ace4ab781ce8746b100c316e 42cc6e0151dec49ac84278a4d83ca49b 21d698972394a54142cc6e0151dec49a 3fb20d08ace4ab781ce8746b100c316e fpscr=00000000
+vselgt.f64 d7, d8, d10 c10abff54f770a20112dfaa1871c6200 43583eca9ac1499f50e117ffbffc9fce fbb76d0b454872abd2b6d05e3da6aec2 50e117ffbffc9fce112dfaa1871c6200 43583eca9ac1499f50e117ffbffc9fce fbb76d0b454872abd2b6d05e3da6aec2 fpscr=00000000
+vselgt.f64 d7, d8, d10 55824ec083b68efd935b3cb06092f214 b24784367524062b5f2442f91082ee85 fe6b68441c3cd4473b05d3739b191eb1 5f2442f91082ee85935b3cb06092f214 b24784367524062b5f2442f91082ee85 fe6b68441c3cd4473b05d3739b191eb1 fpscr=00000000
+vselgt.f64 d7, d8, d10 04ec8007dcd8259eb46706a116fb3594 d6cd91b17366b498ce77a62fd04a04e8 f5428bf658d74321fc004f843c995e19 ce77a62fd04a04e8b46706a116fb3594 d6cd91b17366b498ce77a62fd04a04e8 f5428bf658d74321fc004f843c995e19 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 9982253f796c209a63a01da4fc15ddf7 0517b5e37f453a794f416f41aa1f6327 f5beabf0cf43088f88eb2d9268163c40 4f416f41aa1f632763a01da4fc15ddf7 0517b5e37f453a794f416f41aa1f6327 f5beabf0cf43088f88eb2d9268163c40 fpscr=00000000
+vselgt.f64 d7, d8, d10 193d271dfad342faf8217f803d5d7d1f 043f2c2e6dd27b8f0f27d483ca4b472b 2a9ce0d2064f0c52702884ebd899d8ab 0f27d483ca4b472bf8217f803d5d7d1f 043f2c2e6dd27b8f0f27d483ca4b472b 2a9ce0d2064f0c52702884ebd899d8ab fpscr=00000000
+vselgt.f64 d7, d8, d10 856cf8e6fde3d28de790762347678e7a f82ffe4ce70ef4d4efe07d64463843f2 dbd17c208e78e97e546b8297a6ac08f0 efe07d64463843f2e790762347678e7a f82ffe4ce70ef4d4efe07d64463843f2 dbd17c208e78e97e546b8297a6ac08f0 fpscr=00000000
+vselgt.f64 d7, d8, d10 046a7db02c2b212f4fcf7fd0c67407de 15331e31fe3a99b7b1906b87b46c65c6 d760347e7d32ec11688150cc43fe0f57 b1906b87b46c65c64fcf7fd0c67407de 15331e31fe3a99b7b1906b87b46c65c6 d760347e7d32ec11688150cc43fe0f57 fpscr=00000000
+vselgt.f64 d7, d8, d10 ab982ac5668794dba129791b5aa7b376 5bfd7037ca9edd979b2f27a881724708 de8a4e91eaff7c1a9c5cde179ef79e72 9b2f27a881724708a129791b5aa7b376 5bfd7037ca9edd979b2f27a881724708 de8a4e91eaff7c1a9c5cde179ef79e72 fpscr=00000000
+vselgt.f64 d7, d8, d10 55656554181c3df2324141abf98de883 7992362189c698dc26f0f74603b51746 525a4d9725b55308a2d1130289a02676 26f0f74603b51746324141abf98de883 7992362189c698dc26f0f74603b51746 525a4d9725b55308a2d1130289a02676 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 059c7386ba18e2f9059c7386ba18e2f9 2b6e84f65842f7a22b6e84f65842f7a2 d531965e6ba117763d3801f1069d2d32 2b6e84f65842f7a2059c7386ba18e2f9 2b6e84f65842f7a22b6e84f65842f7a2 d531965e6ba117763d3801f1069d2d32 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 2b346b02d6932174c4ec15b4a1525eba 24a53e153c75ce7a38f9d8685cf863ed 5f9c323a3760db545f9c323a3760db54 38f9d8685cf863edc4ec15b4a1525eba 24a53e153c75ce7a38f9d8685cf863ed 5f9c323a3760db545f9c323a3760db54 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 d200cac69e767dba576370b0bec5daf5 64f0f9ad576c11e2ee5740c884baa187 625e27aef3b33e8b625e27aef3b33e8b ee5740c884baa187576370b0bec5daf5 64f0f9ad576c11e2ee5740c884baa187 625e27aef3b33e8b625e27aef3b33e8b fpscr=00000000
+vselgt.f64 d7, d8, d10 fb0650fe99e00077960d0e17e68462d8 80ad135ca102e2518a639b87f45de2a9 36f0caf8fe5634a37a25a79738a666c1 8a639b87f45de2a9960d0e17e68462d8 80ad135ca102e2518a639b87f45de2a9 36f0caf8fe5634a37a25a79738a666c1 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 4493cb3611bde6fb4493cb3611bde6fb 400ead755366854b7848c9e734cbc93e b81cfda24fbfb946c584c4cb1490405e 7848c9e734cbc93e4493cb3611bde6fb 400ead755366854b7848c9e734cbc93e b81cfda24fbfb946c584c4cb1490405e fpscr=00000000
+vselgt.f64 d7, d8, d10 37acd05b093195d4cc196042f3c4d2b3 d486c05060334f93b036e5cc76f58690 f460f6214260184275dda6294ff45552 b036e5cc76f58690cc196042f3c4d2b3 d486c05060334f93b036e5cc76f58690 f460f6214260184275dda6294ff45552 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 d23c65e0374dacd7d0c927f5ca8e84e4 dfef494e68903106cf285ec202de0303 7c3d35077afe6dcd70a6e690ccee61f6 cf285ec202de0303d0c927f5ca8e84e4 dfef494e68903106cf285ec202de0303 7c3d35077afe6dcd70a6e690ccee61f6 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 c31f59eefee506c3c31f59eefee506c3 d4ffb705e1afce6c8f2e9973c7f1b172 cc6139683c60ba304b49a168cb6a8c59 8f2e9973c7f1b172c31f59eefee506c3 d4ffb705e1afce6c8f2e9973c7f1b172 cc6139683c60ba304b49a168cb6a8c59 fpscr=00000000
+vselgt.f64 d7, d8, d10 0f07ab007ed849a4b42f2c62f6de8259 c8c9868974388f35dbeec777eec8e091 e7599c1d7941859f453ecc281e798668 dbeec777eec8e091b42f2c62f6de8259 c8c9868974388f35dbeec777eec8e091 e7599c1d7941859f453ecc281e798668 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 12ae4c89891b611cb72d1badd1706f6d 33ed6394a4e0fdd833ed6394a4e0fdd8 6d48ba65a049044f0a6ec6b4dfc0b99e 33ed6394a4e0fdd8b72d1badd1706f6d 33ed6394a4e0fdd833ed6394a4e0fdd8 6d48ba65a049044f0a6ec6b4dfc0b99e fpscr=00000000
+vselgt.f64 d7, d8, d10 b477b9e7f18bc6c3580edaccddcf5265 8fce0077d9a66558e02da4604c7f08c3 0f85e6ecc939fc5e6297549b24245209 e02da4604c7f08c3580edaccddcf5265 8fce0077d9a66558e02da4604c7f08c3 0f85e6ecc939fc5e6297549b24245209 fpscr=00000000
+vselgt.f64 d7, d8, d10 fccb1fa9e696df458dcfef3ab5d9369f accf209364f8c75664c64e9312a9df38 770f6e4fec8c7dd3e85ce1c95f9e523e 64c64e9312a9df388dcfef3ab5d9369f accf209364f8c75664c64e9312a9df38 770f6e4fec8c7dd3e85ce1c95f9e523e fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 0282cde34cfcd26f0282cde34cfcd26f 3537db92ab191fd44d29f26f8d054574 d69677db647e10777a689d4468d096e9 4d29f26f8d0545740282cde34cfcd26f 3537db92ab191fd44d29f26f8d054574 d69677db647e10777a689d4468d096e9 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 00b3af3be3bd6611a42ecb216f22d818 546f267de84418ad1bee699375639b51 2b58e9fde83fe3f22b58e9fde83fe3f2 1bee699375639b51a42ecb216f22d818 546f267de84418ad1bee699375639b51 2b58e9fde83fe3f22b58e9fde83fe3f2 fpscr=00000000
+randV128: doing v->u64[0] = v->u64[1]
+vselgt.f64 d7, d8, d10 10e8927696ec55e2380329874e749e64 83c10380fea42b07395f10c1d376077a d09d8a5ac2fdb52fd3f7f22009bd1333 395f10c1d376077a380329874e749e64 83c10380fea42b07395f10c1d376077a d09d8a5ac2fdb52fd3f7f22009bd1333 fpscr=00000000
+randV128: doing v->u64[1] = v->u64[0]
+vselgt.f64 d7, d8, d10 527dae5149384fd86c205830e0157e2c ff2b5b221d444be6c3e7231053ca4553 e90fc207f5504bfada812af5642cc57f c3e7231053ca45536c205830e0157e2c ff2b5b221d444be6c3e7231053ca4553 e90fc207f5504bfada812af5642cc57f fpscr=00000000
+vseleq.f32 s15,s16,s20 2a442f7f3f29c72589d06df375f67db0 4ef5d56ceea1424e573c1461d21119cc f5b8fcab8605407346035a66572f9608 572f96083f29c72589d06df375f67db0 4ef5d56ceea1424e573c1461d21119cc f5b8fcab8605407346035a66572f9608 fpscr=00000000
+vseleq.f32 s15,s16,s20 e2c18409b920238bd18b730c72200055 041b20f49f05d205e056a7eaabf2fc5a f159e6804a208c3aef5c7d239c335778 9c335778b920238bd18b730c72200055 041b20f49f05d205e056a7eaabf2fc5a f159e6804a208c3aef5c7d239c335778 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vseleq.f32 s15,s16,s20 341fc0b0da11db6eb000a274a69bab7a d126249134f10473a47ba276512cbad6 7abc1e3f1f44a40d833548a11bad0962 1bad0962da11db6eb000a274a69bab7a d126249134f10473a47ba276512cbad6 7abc1e3f1f44a40d833548a11bad0962 fpscr=00000000
+randV128: doing v->u32[3] = v->u32[2]
+vseleq.f32 s15,s16,s20 66fa978a94423df7150f41089f081300 8d87596f8d87596f5995551c61781273 3a827ce46ded373e3d4d236c40560f95 40560f9594423df7150f41089f081300 8d87596f8d87596f5995551c61781273 3a827ce46ded373e3d4d236c40560f95 fpscr=00000000
+vseleq.f32 s15,s16,s20 f85523d79f9f0c7202154e95a2d3fe26 6380f154c19c1eb005b8c1eecab4c0be 2fe3d2a90bbf9e845e7b26ad220e47f3 220e47f39f9f0c7202154e95a2d3fe26 6380f154c19c1eb005b8c1eecab4c0be 2fe3d2a90bbf9e845e7b26ad220e47f3 fpscr=00000000
+randV128: doing v->u32[1] = v->u32[0]
+randV128: doing v->u32[3] = v->u32[1]
+vseleq.f32 s15,s16,s20 175da80b0a99d02a56b0dc4dc8f82dab 092de5e052d63dfd0158dc0142ab5ad3 6be226f5a384cc8b8c5092f134a93a24 34a93a240a99d02a56b0dc4dc8f82dab 092de5e052d63dfd0158dc0142ab5ad3 6be226f5a384cc8b8c5092f134a93a24 fpscr=00000000
+vseleq.f32 s15,s16,s20 a0d38bbad477182f3a52cc65df7154eb 104228ad24ae708daa8f...
[truncated message content] |
|
From: <sv...@va...> - 2017-01-18 15:03:08
|
Author: sewardj
Date: Wed Jan 18 15:02:55 2017
New Revision: 3297
Log:
Implement:
VCVT{A,N,P,M}{.F32 d_d, .F32 q_q}
VRINT{A,N,P,M,X,Z}{.F32 d_d, .F32 q_q}
Modified:
trunk/priv/guest_arm_toIR.c
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Wed Jan 18 15:02:55 2017
@@ -13857,6 +13857,182 @@
/* else fall through */
}
+ /* ----------- VCVT{A,N,P,M}{.F32 d_d, .F32 q_q} ----------- */
+ /* 31 27 22 21 15 11 9 7 6 5 4 3
+ T1: 1111 11111 D 111011 Vd 00 rm op Q M 0 Vm
+ A1: 1111 00111 D 111011 Vd 00 rm op Q M 0 Vm
+
+ ARM encoding is in NV space.
+ In Thumb mode, we must not be in an IT block.
+ */
+ if (INSN(31,23) == (isT ? BITS9(1,1,1,1,1,1,1,1,1)
+ : BITS9(1,1,1,1,0,0,1,1,1))
+ && INSN(21,16) == BITS6(1,1,1,0,1,1) && INSN(11,10) == BITS2(0,0)
+ && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_Vd = INSN(15,12);
+ UInt fld_rm = INSN(9,8);
+ Bool isU = INSN(7,7) == 1;
+ Bool isQ = INSN(6,6) == 1;
+ UInt bit_M = INSN(5,5);
+ UInt fld_Vm = INSN(3,0);
+
+ /* dd, nn, mm are D-register numbers. */
+ UInt dd = (bit_D << 4) | fld_Vd;
+ UInt mm = (bit_M << 4) | fld_Vm;
+
+ if (! (isQ && ((dd & 1) == 1 || (mm & 1) == 1))) {
+ /* Do this piecewise on f regs. */
+ UInt ddF = dd << 1;
+ UInt mmF = mm << 1;
+
+ if (isT) {
+ gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+ }
+ /* In ARM mode, this is statically unconditional. In Thumb mode,
+ this must be dynamically unconditional, and we've SIGILLd if not.
+ In either case we can create unconditional IR. */
+
+ UChar cvtc = '?';
+ IRRoundingMode rm = Irrm_NEAREST;
+ switch (fld_rm) {
+ /* The use of NEAREST for both the 'a' and 'n' cases is a bit of a
+ kludge since it doesn't take into account the nearest-even vs
+ nearest-away semantics. */
+ case BITS2(0,0): cvtc = 'a'; rm = Irrm_NEAREST; break;
+ case BITS2(0,1): cvtc = 'n'; rm = Irrm_NEAREST; break;
+ case BITS2(1,0): cvtc = 'p'; rm = Irrm_PosINF; break;
+ case BITS2(1,1): cvtc = 'm'; rm = Irrm_NegINF; break;
+ default: vassert(0);
+ }
+
+ IROp cvt = isU ? Iop_F64toI32U : Iop_F64toI32S;
+
+ IRTemp r0 = newTemp(Ity_F32);
+ IRTemp r1 = newTemp(Ity_F32);
+ IRTemp r2 = isQ ? newTemp(Ity_F32) : IRTemp_INVALID;
+ IRTemp r3 = isQ ? newTemp(Ity_F32) : IRTemp_INVALID;
+
+ IRExpr* rmE = mkU32((UInt)rm);
+
+ assign(r0, unop(Iop_ReinterpI32asF32,
+ binop(cvt, rmE, unop(Iop_F32toF64,
+ llGetFReg_up_to_64(mmF+0)))));
+ assign(r1, unop(Iop_ReinterpI32asF32,
+ binop(cvt, rmE, unop(Iop_F32toF64,
+ llGetFReg_up_to_64(mmF+1)))));
+ if (isQ) {
+ assign(r2, unop(Iop_ReinterpI32asF32,
+ binop(cvt, rmE, unop(Iop_F32toF64,
+ llGetFReg_up_to_64(mmF+2)))));
+ assign(r3, unop(Iop_ReinterpI32asF32,
+ binop(cvt, rmE, unop(Iop_F32toF64,
+ llGetFReg_up_to_64(mmF+3)))));
+ }
+
+ llPutFReg_up_to_64(ddF+0, mkexpr(r0));
+ llPutFReg_up_to_64(ddF+1, mkexpr(r1));
+ if (isQ) {
+ llPutFReg_up_to_64(ddF+2, mkexpr(r2));
+ llPutFReg_up_to_64(ddF+3, mkexpr(r3));
+ }
+
+ HChar rch = isQ ? 'q' : 'd';
+ UInt sh = isQ ? 1 : 0;
+ DIP("vcvt%c.%c32.f32 %c%u, %c%u\n",
+ cvtc, isU ? 'u' : 's', rch, dd >> sh, rch, mm >> sh);
+ return True;
+ }
+ /* else fall through */
+ }
+
+ /* ----------- VRINT{A,N,P,M,X,Z}{.F32 d_d, .F32 q_q} ----------- */
+ /* 31 27 22 21 15 11 9 6 5 4 3
+ T1: 1111 11111 D 111010 Vd 01 op Q M 0 Vm
+ A1: 1111 00111 D 111010 Vd 01 op Q M 0 Vm
+
+ ARM encoding is in NV space.
+ In Thumb mode, we must not be in an IT block.
+ */
+ if (INSN(31,23) == (isT ? BITS9(1,1,1,1,1,1,1,1,1)
+ : BITS9(1,1,1,1,0,0,1,1,1))
+ && INSN(21,16) == BITS6(1,1,1,0,1,0) && INSN(11,10) == BITS2(0,1)
+ && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_Vd = INSN(15,12);
+ UInt fld_op = INSN(9,7);
+ Bool isQ = INSN(6,6) == 1;
+ UInt bit_M = INSN(5,5);
+ UInt fld_Vm = INSN(3,0);
+
+ /* dd, nn, mm are D-register numbers. */
+ UInt dd = (bit_D << 4) | fld_Vd;
+ UInt mm = (bit_M << 4) | fld_Vm;
+
+ if (! (fld_op == BITS3(1,0,0) || fld_op == BITS3(1,1,0))
+ && ! (isQ && ((dd & 1) == 1 || (mm & 1) == 1))) {
+ /* Do this piecewise on f regs. */
+ UInt ddF = dd << 1;
+ UInt mmF = mm << 1;
+
+ if (isT) {
+ gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+ }
+ /* In ARM mode, this is statically unconditional. In Thumb mode,
+ this must be dynamically unconditional, and we've SIGILLd if not.
+ In either case we can create unconditional IR. */
+
+ UChar cvtc = '?';
+ IRRoundingMode rm = Irrm_NEAREST;
+ switch (fld_op) {
+ /* Various kludges:
+ - The use of NEAREST for both the 'a' and 'n' cases,
+ since it doesn't take into account the nearest-even vs
+ nearest-away semantics.
+ - For the 'x' case, we don't signal inexactness.
+ */
+ case BITS3(0,1,0): cvtc = 'a'; rm = Irrm_NEAREST; break;
+ case BITS3(0,0,0): cvtc = 'n'; rm = Irrm_NEAREST; break;
+ case BITS3(1,1,1): cvtc = 'p'; rm = Irrm_PosINF; break;
+ case BITS3(1,0,1): cvtc = 'm'; rm = Irrm_NegINF; break;
+ case BITS3(0,1,1): cvtc = 'z'; rm = Irrm_ZERO; break;
+ case BITS3(0,0,1): cvtc = 'x'; rm = Irrm_NEAREST; break;
+ case BITS3(1,0,0):
+ case BITS3(1,1,0):
+ default: vassert(0);
+ }
+
+ IRTemp r0 = newTemp(Ity_F32);
+ IRTemp r1 = newTemp(Ity_F32);
+ IRTemp r2 = isQ ? newTemp(Ity_F32) : IRTemp_INVALID;
+ IRTemp r3 = isQ ? newTemp(Ity_F32) : IRTemp_INVALID;
+
+ IRExpr* rmE = mkU32((UInt)rm);
+ IROp rnd = Iop_RoundF32toInt;
+
+ assign(r0, binop(rnd, rmE, llGetFReg_up_to_64(mmF+0)));
+ assign(r1, binop(rnd, rmE, llGetFReg_up_to_64(mmF+1)));
+ if (isQ) {
+ assign(r2, binop(rnd, rmE, llGetFReg_up_to_64(mmF+2)));
+ assign(r3, binop(rnd, rmE, llGetFReg_up_to_64(mmF+3)));
+ }
+
+ llPutFReg_up_to_64(ddF+0, mkexpr(r0));
+ llPutFReg_up_to_64(ddF+1, mkexpr(r1));
+ if (isQ) {
+ llPutFReg_up_to_64(ddF+2, mkexpr(r2));
+ llPutFReg_up_to_64(ddF+3, mkexpr(r3));
+ }
+
+ HChar rch = isQ ? 'q' : 'd';
+ UInt sh = isQ ? 1 : 0;
+ DIP("vrint%c.f32.f32 %c%u, %c%u\n",
+ cvtc, rch, dd >> sh, rch, mm >> sh);
+ return True;
+ }
+ /* else fall through */
+ }
+
/* ---------- Doesn't match anything. ---------- */
return False;
|
|
From: <sv...@va...> - 2017-01-16 07:15:12
|
Author: sewardj
Date: Mon Jan 16 07:15:04 2017
New Revision: 3296
Log:
Implement V{MAX,MIN}NM{.F32 d_d_d, .F32 q_q_q}.
Modified:
trunk/priv/guest_arm_toIR.c
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Mon Jan 16 07:15:04 2017
@@ -855,7 +855,10 @@
for endianness. Actually this is completely bogus and needs
careful thought. */
Int off;
- vassert(fregNo < 32);
+ /* NB! Limit is 64, not 32, because we might be pulling F32 bits
+ out of SIMD registers, and there are 16 SIMD registers each of
+ 128 bits (4 x F32). */
+ vassert(fregNo < 64);
off = doubleGuestRegOffset(fregNo >> 1);
if (host_endness == VexEndnessLE) {
if (fregNo & 1)
@@ -873,6 +876,12 @@
return IRExpr_Get( floatGuestRegOffset(fregNo), Ity_F32 );
}
+static IRExpr* llGetFReg_up_to_64 ( UInt fregNo )
+{
+ vassert(fregNo < 64);
+ return IRExpr_Get( floatGuestRegOffset(fregNo), Ity_F32 );
+}
+
/* Architected read from a VFP Freg. */
static IRExpr* getFReg ( UInt fregNo ) {
return llGetFReg( fregNo );
@@ -886,6 +895,13 @@
stmt( IRStmt_Put(floatGuestRegOffset(fregNo), e) );
}
+static void llPutFReg_up_to_64 ( UInt fregNo, IRExpr* e )
+{
+ vassert(fregNo < 64);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F32);
+ stmt( IRStmt_Put(floatGuestRegOffset(fregNo), e) );
+}
+
/* Architected write to a VFP Freg. Handles conditional writes to the
register: if guardT == IRTemp_INVALID then the write is
unconditional. */
@@ -13762,6 +13778,85 @@
return True;
}
+ /* ----------- V{MAX,MIN}NM{.F32 d_d_d, .F32 q_q_q} ----------- */
+ /* 31 27 22 21 20 19 15 11 7 6 5 4 3
+ T1: 1111 11110 D op 0 Vn Vd 1111 N 1 M 1 Vm V{MIN,MAX}NM.F32 Qd,Qn,Qm
+ A1: 1111 00110 D op 0 Vn Vd 1111 N 1 M 1 Vm
+
+ T1: 1111 11110 D op 0 Vn Vd 1111 N 0 M 1 Vm V{MIN,MAX}NM.F32 Dd,Dn,Dm
+ A1: 1111 00110 D op 0 Vn Vd 1111 N 0 M 1 Vm
+
+ ARM encoding is in NV space.
+ In Thumb mode, we must not be in an IT block.
+ */
+ if (INSN(31,23) == (isT ? BITS9(1,1,1,1,1,1,1,1,0)
+ : BITS9(1,1,1,1,0,0,1,1,0))
+ && INSN(20,20) == 0 && INSN(11,8) == BITS4(1,1,1,1) && INSN(4,4) == 1) {
+ UInt bit_D = INSN(22,22);
+ Bool isMax = INSN(21,21) == 0;
+ UInt fld_Vn = INSN(19,16);
+ UInt fld_Vd = INSN(15,12);
+ UInt bit_N = INSN(7,7);
+ Bool isQ = INSN(6,6) == 1;
+ UInt bit_M = INSN(5,5);
+ UInt fld_Vm = INSN(3,0);
+
+ /* dd, nn, mm are D-register numbers. */
+ UInt dd = (bit_D << 4) | fld_Vd;
+ UInt nn = (bit_N << 4) | fld_Vn;
+ UInt mm = (bit_M << 4) | fld_Vm;
+
+ if (! (isQ && ((dd & 1) == 1 || (nn & 1) == 1 || (mm & 1) == 1))) {
+ /* Do this piecewise on f regs. This is a bit tricky
+ though because we are dealing with the full 16 x Q == 32 x D
+ register set, so the implied F reg numbers are 0 to 63. But
+ ll{Get,Put}FReg only allow the 0 .. 31 as those are the only
+ architected F regs. */
+ UInt ddF = dd << 1;
+ UInt nnF = nn << 1;
+ UInt mmF = mm << 1;
+
+ if (isT) {
+ gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+ }
+ /* In ARM mode, this is statically unconditional. In Thumb mode,
+ this must be dynamically unconditional, and we've SIGILLd if not.
+ In either case we can create unconditional IR. */
+
+ IROp op = isMax ? Iop_MaxNumF32 : Iop_MinNumF32;
+
+ IRTemp r0 = newTemp(Ity_F32);
+ IRTemp r1 = newTemp(Ity_F32);
+ IRTemp r2 = isQ ? newTemp(Ity_F32) : IRTemp_INVALID;
+ IRTemp r3 = isQ ? newTemp(Ity_F32) : IRTemp_INVALID;
+
+ assign(r0, binop(op, llGetFReg_up_to_64(nnF+0),
+ llGetFReg_up_to_64(mmF+0)));
+ assign(r1, binop(op, llGetFReg_up_to_64(nnF+1),
+ llGetFReg_up_to_64(mmF+1)));
+ if (isQ) {
+ assign(r2, binop(op, llGetFReg_up_to_64(nnF+2),
+ llGetFReg_up_to_64(mmF+2)));
+ assign(r3, binop(op, llGetFReg_up_to_64(nnF+3),
+ llGetFReg_up_to_64(mmF+3)));
+ }
+ llPutFReg_up_to_64(ddF+0, mkexpr(r0));
+ llPutFReg_up_to_64(ddF+1, mkexpr(r1));
+ if (isQ) {
+ llPutFReg_up_to_64(ddF+2, mkexpr(r2));
+ llPutFReg_up_to_64(ddF+3, mkexpr(r3));
+ }
+
+ HChar rch = isQ ? 'q' : 'd';
+ UInt sh = isQ ? 1 : 0;
+ DIP("v%snm.f32 %c%u, %c%u, %c%u\n",
+ isMax ? "max" : "min", rch,
+ dd >> sh, rch, nn >> sh, rch, mm >> sh);
+ return True;
+ }
+ /* else fall through */
+ }
+
/* ---------- Doesn't match anything. ---------- */
return False;
|
|
From: <sv...@va...> - 2017-01-16 05:14:31
|
Author: sewardj
Date: Mon Jan 16 05:14:24 2017
New Revision: 3295
Log:
dis_neon_data_3same: don't silently accept invalid instructions. Instead,
"return False" for any instruction not accepted by this function. Also,
add a few switch default backstops.
Modified:
trunk/priv/guest_arm_toIR.c
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Mon Jan 16 05:14:24 2017
@@ -3392,6 +3392,8 @@
reg_t, dreg, reg_t, nreg, reg_t, mreg);
break;
}
+ default:
+ vassert(0);
}
} else {
switch(C) {
@@ -3489,6 +3491,8 @@
Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
break;
+ default:
+ vassert(0);
}
}
}
@@ -4611,6 +4615,8 @@
DIP("vpadd.i%d %c%u, %c%u, %c%u\n",
8 << size, Q ? 'q' : 'd',
dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+ } else {
+ return False;
}
}
break;
@@ -4768,6 +4774,8 @@
DIP("vacg%c.f32 %c%u, %c%u, %c%u\n", op_bit ? 't' : 'e',
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg,
Q ? 'q' : 'd', mreg);
+ } else {
+ return False;
}
}
break;
@@ -4827,6 +4835,8 @@
DIP("vrsqrts.f32 %c%u, %c%u, %c%u\n", Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
}
+ } else {
+ return False;
}
}
break;
|
|
From: Austin E. <aus...@gm...> - 2017-01-16 03:57:53
|
On Dec 5, 2016 2:23 AM, "Austin English" <aus...@gm...> wrote:
Howdy all,
Several months ago, a patch from Sebastian:
commit 44fbc018eda12bdee5c2c1e2e40dbdc6a81b27fd
Author: Sebastian Lackner <seb...@fd...>
Date: Thu Feb 12 11:09:34 2015 +0100
winebuild: Do not access memory below ESP when restoring thread
contexts.
Based on a patch by John Reiser.
for https://bugs.winehq.org/show_bug.cgi?id=14367
Caused problems for running Wine under Valgrind:
https://bugs.kde.org/show_bug.cgi?id=344139
There are patches floating around for both Wine and Valgrind (see
previous link), but from what I've seen so far, both projects aren't a
fan of the current patches.
Given that Wine developers like using Valgrind to check for problems,
and I know Julian would like to use Wine with Valgrind, I feel like some
solution to this problem can be found. Since my efforts at trying to run
messages between the two projects hasn't solved it yet, I figured an
email thread would work better ;).
--
-Austin
GPG: 14FB D7EA A041 937B
Ping.
--
-Austin
GPG: 14FB D7EA A041 937B
|
|
From: <sv...@va...> - 2017-01-15 18:25:26
|
Author: sewardj
Date: Sun Jan 15 18:25:18 2017
New Revision: 3294
Log:
Implement VRINTX.F64.F64 d_d, VRINTX.F32.F32 s_s.
Modified:
trunk/priv/guest_arm_toIR.c
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Sun Jan 15 18:25:18 2017
@@ -13709,6 +13709,49 @@
return True;
}
+ /* ----------- VRINTX.F64.F64 d_d, VRINTX.F32.F32 s_s ----------- */
+ /* 31 27 22 21 15 11 8 7 5 4 3
+ T1: 1110 11101 D 110111 Vd 101 1 01 M 0 Vm VRINTX<c>.F64.F64 Dd, Dm
+ A1: cond 11101 D 110111 Vd 101 1 01 M 0 Vm
+
+ T1: 1110 11101 D 110111 Vd 101 0 01 M 0 Vm VRINTX<c>.F32.F32 Dd, Dm
+ A1: cond 11101 D 110111 Vd 101 0 01 M 0 Vm
+
+ Like VRINT{Z,R}{.F64.F64, .F32.F32} just above, this can be conditional.
+ This produces the same code as the VRINTR case since we ignore the
+ requirement to signal inexactness.
+ */
+ if ((isT ? (INSN(31,28) == BITS4(1,1,1,0)) : True)
+ && INSN(27,23) == BITS5(1,1,1,0,1) && INSN(21,16) == BITS6(1,1,0,1,1,1)
+ && INSN(11,9) == BITS3(1,0,1) && INSN(7,6) == BITS2(0,1)
+ && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_Vd = INSN(15,12);
+ Bool isF64 = INSN(8,8) == 1;
+ UInt bit_M = INSN(5,5);
+ UInt fld_Vm = INSN(3,0);
+ UInt dd = isF64 ? ((bit_D << 4) | fld_Vd) : ((fld_Vd << 1) | bit_D);
+ UInt mm = isF64 ? ((bit_M << 4) | fld_Vm) : ((fld_Vm << 1) | bit_M);
+
+ if (isT) vassert(condT != IRTemp_INVALID);
+ IRType ty = isF64 ? Ity_F64 : Ity_F32;
+ IRTemp src = newTemp(ty);
+ IRTemp res = newTemp(ty);
+ assign(src, (isF64 ? getDReg : getFReg)(mm));
+
+ IRTemp rm = newTemp(Ity_I32);
+ assign(rm, mkexpr(mk_get_IR_rounding_mode()));
+ assign(res, binop(isF64 ? Iop_RoundF64toInt : Iop_RoundF32toInt,
+ mkexpr(rm), mkexpr(src)));
+ (isF64 ? putDReg : putFReg)(dd, mkexpr(res), condT);
+
+ UChar rch = isF64 ? 'd' : 'f';
+ DIP("vrint%c.%s.%s %c%u, %c%u\n",
+ 'x',
+ isF64 ? "f64" : "f32", isF64 ? "f64" : "f32", rch, dd, rch, mm);
+ return True;
+ }
+
/* ---------- Doesn't match anything. ---------- */
return False;
|
|
From: Petar J. <mip...@gm...> - 2017-01-14 14:41:26
|
On Fri, Jan 13, 2017 at 11:03 PM, Philippe Waroquiers <phi...@sk...> wrote: > Maybe we will receive some information from Mellanox before FOSDEM > in the meantime. > > Maybe we will receive some information from Mellanox before FOSDEM > in the meantime. As I said earlier, I exchanged a few emails with Mellanox engineers. They still maintain Kernel, GCC, binutils, GLIBC, but not Valgrind. The person who originally wrote the code moved to a different company. They also said, quote: "If it makes sense to leave the tilegx port enabled without a current maintainer, great; if it seems like a hassle, I completely understand if you want to let it drop from the tree for the time being." Petar |
|
From: Philippe W. <phi...@sk...> - 2017-01-13 22:03:18
|
Using SETI (Search Extra Tile-gx Information) I tried to find some recent news about tile-gx, such as a newer version of the instruction set, or new processor models or whatever indicating a sign of active development life. I find nothing. To the contrary, what I can find is that the tile-gx architecture is being replaced by tile-mx, which is an ARM based chip. See a.o http://www.mellanox.com/repository/solutions/tile-scm/ and http://www.bdti.com/InsideDSP/2015/03/03/EZchip and various other things such as ezchip roadmap. So, no developer, no user, no company person telling anything, and public information telling the chip will be replaced. So, it looks clear that tile-gx will have to be removed sooner or later. IMO, sooner is better: I spent some effort even very recently on the tile-gx files (as part of a factorisation effort) and it looks like this (evening/week-end) effort was just spent for nothing, while some real users have to wait because their wishes are just put in my TODO list. The above is some additional info for the discussion we can have at FOSDEM2017 valgrind BoF. Maybe we will receive some information from Mellanox before FOSDEM in the meantime. But with the current info, it looks doubtful anybody wants to spend any more effort on maintaining this. Philippe On Fri, 2017-01-13 at 21:59 +0100, Julian Seward wrote: > That's not a fair comparison. The Solaris port has a very active > maintainer and (presumably) also has users. By comparison the Tilegx > port has shown no signs of life for a considerable period of time, > despite attempts by more than one person here to contact both maintainers > and users. In my view it is valid to discuss whether we should continue > to have the Tilegx port in the tree. > > J > > On 13/01/17 21:43, Irek Szczesniak wrote: > > OK, next is to remove the Solaris port of valgrind. OS was > > discontinued, Oracle does not respond to emails and there is no > > emulator. > > > > Please remove. > > > > Irek > > > > On Fri, Jan 13, 2017 at 11:41 AM, Ivo Raisr <iv...@iv...> wrote: > >> > >> > >> 2017-01-12 20:36 GMT+01:00 Philippe Waroquiers > >> <phi...@sk...>: > >>> > >>> On Thu, 2017-01-12 at 13:37 +0100, Roland Mainz wrote: > >>>> On Thu, Jan 12, 2017 at 1:31 PM, Petar Jovanovic <mip...@gm...> > >>>> wrote: > >>>>> On Wed, Jan 4, 2017 at 3:21 PM, Philippe Waroquiers > >>>>> <phi...@sk...> wrote: > >>>>>> No sign of any tilegx user or developer activity since something like > >>>>>> one year. > >>>>>> No reply received for question in > >>>>>> https://sourceforge.net/p/valgrind/mailman/message/35566192/ > >>>>>> > >>>>>> Is there any tilegx user or developer still active ? > >>>>>> Should we consider this platform as dead ? > >>>>>> > >>>>> I have exchanged a few emails with Tilera/Mellanox compiler enigneers, > >>>>> and they say they cannot take care of TileGx port in Valgrind for the > >>>>> time being. > >>>> > >>>> Is there any emulator or other way we can use to test changes ? I > >>>> don't like seeing such a port just disappear... > >>> Well, if there is > >>> no known users, > >>> and no (original) developer doing maintenance > >>> and no reply from (original) developers to simple questions > >>> and no access to a system to test/compile > >>> and no nightly build > >>> and no tests in SVN > >>> and no emulator > >>> then IMO, this platform is a candidate to remove. > >>> as just keeping this compiling forever for no reason will > >>> at the end cost more than just removing it. > >> > >> > >> Agreed here. Although there are regtests under none/tests/tilegx there is no > >> way > >> to run them without any access to the machine or emulator. > >> I. > >> > >> ------------------------------------------------------------------------------ > >> Developer Access Program for Intel Xeon Phi Processors > >> Access to Intel Xeon Phi processor-based developer platforms. > >> With one year of Intel Parallel Studio XE. > >> Training and support from Colfax. > >> Order your platform today. http://sdm.link/xeonphi > >> _______________________________________________ > >> Valgrind-developers mailing list > >> Val...@li... > >> https://lists.sourceforge.net/lists/listinfo/valgrind-developers > >> > > > > > > > > > ------------------------------------------------------------------------------ > Developer Access Program for Intel Xeon Phi Processors > Access to Intel Xeon Phi processor-based developer platforms. > With one year of Intel Parallel Studio XE. > Training and support from Colfax. > Order your platform today. http://sdm.link/xeonphi > _______________________________________________ > Valgrind-developers mailing list > Val...@li... > https://lists.sourceforge.net/lists/listinfo/valgrind-developers |
|
From: Ivo R. <iv...@iv...> - 2017-01-13 21:31:58
|
2017-01-13 22:27 GMT+01:00 Dan Shelton <dan...@gm...>: > On 13 January 2017 at 21:59, Julian Seward <js...@ac...> wrote: > > > > That's not a fair comparison. The Solaris port has a very active > > maintainer and (presumably) also has users. > > Well, given that Mr Irek was part of the Opensolaris community I THINK > he was applying sarcasm and a large grain or whole mine of salt to the > situation. > > Also, even that Solaris is now dead, not only per > http://www.sunhelp.org/ but by the virtue of Oracle having laid off > more than 150 people of the core os team(!!!!!!), there is still > Illumos. > The information at sunhelp.org is heavily outdated (from 1st December 2016). Since then, a lot has happened. Have a look at the source cited at sunhelp.org and you will find much more fresh information which brings this whole situation into reality again. I. |
|
From: Dan S. <dan...@gm...> - 2017-01-13 21:27:57
|
On 13 January 2017 at 21:59, Julian Seward <js...@ac...> wrote: > > That's not a fair comparison. The Solaris port has a very active > maintainer and (presumably) also has users. Well, given that Mr Irek was part of the Opensolaris community I THINK he was applying sarcasm and a large grain or whole mine of salt to the situation. Also, even that Solaris is now dead, not only per http://www.sunhelp.org/ but by the virtue of Oracle having laid off more than 150 people of the core os team(!!!!!!), there is still Illumos. > By comparison the Tilegx > port has shown no signs of life for a considerable period of time, > despite attempts by more than one person here to contact both maintainers > and users. In my view it is valid to discuss whether we should continue > to have the Tilegx port in the tree. Who exactly was contacted? Oracle never bothered to comment on the Solaris port, yet valgrind has that port. Maybe the wrong people were contacted? Dan |
|
From: Julian S. <js...@ac...> - 2017-01-13 21:18:29
|
That's not a fair comparison. The Solaris port has a very active maintainer and (presumably) also has users. By comparison the Tilegx port has shown no signs of life for a considerable period of time, despite attempts by more than one person here to contact both maintainers and users. In my view it is valid to discuss whether we should continue to have the Tilegx port in the tree. J On 13/01/17 21:43, Irek Szczesniak wrote: > OK, next is to remove the Solaris port of valgrind. OS was > discontinued, Oracle does not respond to emails and there is no > emulator. > > Please remove. > > Irek > > On Fri, Jan 13, 2017 at 11:41 AM, Ivo Raisr <iv...@iv...> wrote: >> >> >> 2017-01-12 20:36 GMT+01:00 Philippe Waroquiers >> <phi...@sk...>: >>> >>> On Thu, 2017-01-12 at 13:37 +0100, Roland Mainz wrote: >>>> On Thu, Jan 12, 2017 at 1:31 PM, Petar Jovanovic <mip...@gm...> >>>> wrote: >>>>> On Wed, Jan 4, 2017 at 3:21 PM, Philippe Waroquiers >>>>> <phi...@sk...> wrote: >>>>>> No sign of any tilegx user or developer activity since something like >>>>>> one year. >>>>>> No reply received for question in >>>>>> https://sourceforge.net/p/valgrind/mailman/message/35566192/ >>>>>> >>>>>> Is there any tilegx user or developer still active ? >>>>>> Should we consider this platform as dead ? >>>>>> >>>>> I have exchanged a few emails with Tilera/Mellanox compiler enigneers, >>>>> and they say they cannot take care of TileGx port in Valgrind for the >>>>> time being. >>>> >>>> Is there any emulator or other way we can use to test changes ? I >>>> don't like seeing such a port just disappear... >>> Well, if there is >>> no known users, >>> and no (original) developer doing maintenance >>> and no reply from (original) developers to simple questions >>> and no access to a system to test/compile >>> and no nightly build >>> and no tests in SVN >>> and no emulator >>> then IMO, this platform is a candidate to remove. >>> as just keeping this compiling forever for no reason will >>> at the end cost more than just removing it. >> >> >> Agreed here. Although there are regtests under none/tests/tilegx there is no >> way >> to run them without any access to the machine or emulator. >> I. >> >> ------------------------------------------------------------------------------ >> Developer Access Program for Intel Xeon Phi Processors >> Access to Intel Xeon Phi processor-based developer platforms. >> With one year of Intel Parallel Studio XE. >> Training and support from Colfax. >> Order your platform today. http://sdm.link/xeonphi >> _______________________________________________ >> Valgrind-developers mailing list >> Val...@li... >> https://lists.sourceforge.net/lists/listinfo/valgrind-developers >> > > > |
|
From: Ivo R. <iv...@iv...> - 2017-01-13 21:11:19
|
2017-01-13 21:43 GMT+01:00 Irek Szczesniak <isz...@gm...>: > OK, next is to remove the Solaris port of valgrind. OS was > discontinued, Oracle does not respond to emails and there is no > emulator. You can say remove OS X port of Valgrind as well in this manner. Prove your statements. Who says "[Solaris] OS is discontinued"? If you are running an x86 machine, an "emulator" is right on your machine - get x86/Solaris template for VirtualBox [1]. What are your Valgrind contributions in general which give you a position to say "remove something"? I. [1] http://www.oracle.com/technetwork/server-storage/solaris11/downloads/vm- templates-2245495.html |
|
From: Mark W. <mj...@re...> - 2017-01-13 21:10:09
|
On Fri, Jan 13, 2017 at 09:43:07PM +0100, Irek Szczesniak wrote: > OK, next is to remove the Solaris port of valgrind. OS was > discontinued, Oracle does not respond to emails and there is no > emulator. > > Please remove. You message is inappropriate in this thread. There are no issues with the valgrind solaris port. It is maintained. Reported bugs get fixed. Ivo is one of the most active valgrind developers. And he always makes sure other platforms benefit from his work. Please take your solaris/oracle rants somewhere else. Thanks, Mark |
|
From: Irek S. <isz...@gm...> - 2017-01-13 20:43:14
|
OK, next is to remove the Solaris port of valgrind. OS was discontinued, Oracle does not respond to emails and there is no emulator. Please remove. Irek On Fri, Jan 13, 2017 at 11:41 AM, Ivo Raisr <iv...@iv...> wrote: > > > 2017-01-12 20:36 GMT+01:00 Philippe Waroquiers > <phi...@sk...>: >> >> On Thu, 2017-01-12 at 13:37 +0100, Roland Mainz wrote: >> > On Thu, Jan 12, 2017 at 1:31 PM, Petar Jovanovic <mip...@gm...> >> > wrote: >> > > On Wed, Jan 4, 2017 at 3:21 PM, Philippe Waroquiers >> > > <phi...@sk...> wrote: >> > >> No sign of any tilegx user or developer activity since something like >> > >> one year. >> > >> No reply received for question in >> > >> https://sourceforge.net/p/valgrind/mailman/message/35566192/ >> > >> >> > >> Is there any tilegx user or developer still active ? >> > >> Should we consider this platform as dead ? >> > >> >> > > I have exchanged a few emails with Tilera/Mellanox compiler enigneers, >> > > and they say they cannot take care of TileGx port in Valgrind for the >> > > time being. >> > >> > Is there any emulator or other way we can use to test changes ? I >> > don't like seeing such a port just disappear... >> Well, if there is >> no known users, >> and no (original) developer doing maintenance >> and no reply from (original) developers to simple questions >> and no access to a system to test/compile >> and no nightly build >> and no tests in SVN >> and no emulator >> then IMO, this platform is a candidate to remove. >> as just keeping this compiling forever for no reason will >> at the end cost more than just removing it. > > > Agreed here. Although there are regtests under none/tests/tilegx there is no > way > to run them without any access to the machine or emulator. > I. > > ------------------------------------------------------------------------------ > Developer Access Program for Intel Xeon Phi Processors > Access to Intel Xeon Phi processor-based developer platforms. > With one year of Intel Parallel Studio XE. > Training and support from Colfax. > Order your platform today. http://sdm.link/xeonphi > _______________________________________________ > Valgrind-developers mailing list > Val...@li... > https://lists.sourceforge.net/lists/listinfo/valgrind-developers > -- Irek |
|
From: <pa...@fr...> - 2017-01-13 18:33:07
|
----- Original Message ----- > No sign of any tilegx user or developer activity since something like > one year. > No reply received for question in > https://sourceforge.net/p/valgrind/mailman/message/35566192/ > > Is there any tilegx user or developer still active ? > Should we consider this platform as dead ? > > Philippe Hi Perhaps related to this, the parent company of Tilera, EZchip, was acquired by Mellanox about a year ago: http://www.mellanox.com/page/press_release_item?id=1681 A+ Paul |
|
From: <sv...@va...> - 2017-01-13 18:02:50
|
Author: sewardj
Date: Fri Jan 13 18:02:38 2017
New Revision: 16202
Log:
Add support for Iop_MaxNumF64, Iop_MinNumF64, Iop_MaxNumF32 and
Iop_MinNumF32, as introduced in vex r3293.
Modified:
trunk/memcheck/mc_translate.c
trunk/memcheck/tests/vbit-test/irops.c
Modified: trunk/memcheck/mc_translate.c
==============================================================================
--- trunk/memcheck/mc_translate.c (original)
+++ trunk/memcheck/mc_translate.c Fri Jan 13 18:02:38 2017
@@ -1611,6 +1611,14 @@
return at;
}
+ /* I32 x I32 -> I32 */
+ if (t1 == Ity_I32 && t2 == Ity_I32 && finalVty == Ity_I32) {
+ if (0) VG_(printf)("mkLazy2: I32 x I32 -> I32\n");
+ at = mkUifU(mce, Ity_I32, va1, va2);
+ at = mkPCastTo(mce, Ity_I32, at);
+ return at;
+ }
+
if (0) {
VG_(printf)("mkLazy2 ");
ppIRType(t1);
@@ -3942,6 +3950,16 @@
case Iop_CmpExpD128:
return mkLazy2(mce, Ity_I32, vatom1, vatom2);
+ case Iop_MaxNumF32:
+ case Iop_MinNumF32:
+ /* F32 x F32 -> F32 */
+ return mkLazy2(mce, Ity_I32, vatom1, vatom2);
+
+ case Iop_MaxNumF64:
+ case Iop_MinNumF64:
+ /* F64 x F64 -> F64 */
+ return mkLazy2(mce, Ity_I64, vatom1, vatom2);
+
/* non-FP after here */
case Iop_DivModU64to32:
Modified: trunk/memcheck/tests/vbit-test/irops.c
==============================================================================
--- trunk/memcheck/tests/vbit-test/irops.c (original)
+++ trunk/memcheck/tests/vbit-test/irops.c Fri Jan 13 18:02:38 2017
@@ -295,6 +295,12 @@
{ DEFOP(Iop_RecpExpF64, UNDEF_UNKNOWN), },
{ DEFOP(Iop_RecpExpF32, UNDEF_UNKNOWN), },
+ /* --------- Possibly required by IEEE 754-2008. --------- */
+ { DEFOP(Iop_MaxNumF64, UNDEF_ALL), .arm = 1 },
+ { DEFOP(Iop_MinNumF64, UNDEF_ALL), .arm = 1 },
+ { DEFOP(Iop_MaxNumF32, UNDEF_ALL), .arm = 1 },
+ { DEFOP(Iop_MinNumF32, UNDEF_ALL), .arm = 1 },
+
/* ------------------ 16-bit scalar FP ------------------ */
{ DEFOP(Iop_F16toF64, UNDEF_ALL), .arm64 = 1 },
{ DEFOP(Iop_F64toF16, UNDEF_ALL), .arm64 = 1 },
|
|
From: <sv...@va...> - 2017-01-13 17:59:05
|
Author: sewardj
Date: Fri Jan 13 17:58:57 2017
New Revision: 3293
Log:
Implement
V{MIN,MAX}NM.F64 Dd, Dn, Dm
V{MIN,MAX}NM.F32 Sd, Sn, Sm
Modified:
trunk/priv/guest_arm_toIR.c
trunk/priv/host_arm_defs.c
trunk/priv/host_arm_defs.h
trunk/priv/host_arm_isel.c
trunk/priv/ir_defs.c
trunk/pub/libvex_ir.h
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Fri Jan 13 17:58:57 2017
@@ -13665,6 +13665,50 @@
return True;
}
+ /* ----------- V{MAX,MIN}NM{.F64 d_d_d, .F32 s_s_s} ----------- */
+ /* 31 27 22 21 19 15 11 8 7 6 5 4 3
+ 1111 11101 D 00 Vn Vd 101 1 N op M 0 Vm V{MIN,MAX}NM.F64 Dd, Dn, Dm
+ 1111 11101 D 00 Vn Vd 101 0 N op M 0 Vm V{MIN,MAX}NM.F32 Sd, Sn, Sm
+
+ ARM encoding is in NV space.
+ In Thumb mode, we must not be in an IT block.
+ */
+ if (INSN(31,23) == BITS9(1,1,1,1,1,1,1,0,1) && INSN(21,20) == BITS2(0,0)
+ && INSN(11,9) == BITS3(1,0,1) && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_Vn = INSN(19,16);
+ UInt fld_Vd = INSN(15,12);
+ Bool isF64 = INSN(8,8) == 1;
+ UInt bit_N = INSN(7,7);
+ Bool isMAX = INSN(6,6) == 0;
+ UInt bit_M = INSN(5,5);
+ UInt fld_Vm = INSN(3,0);
+
+ UInt dd = isF64 ? ((bit_D << 4) | fld_Vd) : ((fld_Vd << 1) | bit_D);
+ UInt nn = isF64 ? ((bit_N << 4) | fld_Vn) : ((fld_Vn << 1) | bit_N);
+ UInt mm = isF64 ? ((bit_M << 4) | fld_Vm) : ((fld_Vm << 1) | bit_M);
+
+ if (isT) {
+ gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+ }
+ /* In ARM mode, this is statically unconditional. In Thumb mode,
+ this must be dynamically unconditional, and we've SIGILLd if not.
+ In either case we can create unconditional IR. */
+
+ IROp op = isF64 ? (isMAX ? Iop_MaxNumF64 : Iop_MinNumF64)
+ : (isMAX ? Iop_MaxNumF32 : Iop_MinNumF32);
+ IRExpr* srcN = (isF64 ? llGetDReg : llGetFReg)(nn);
+ IRExpr* srcM = (isF64 ? llGetDReg : llGetFReg)(mm);
+ IRExpr* res = binop(op, srcN, srcM);
+ (isF64 ? llPutDReg : llPutFReg)(dd, res);
+
+ UChar rch = isF64 ? 'd' : 'f';
+ DIP("v%snm.%s %c%u, %c%u, %c%u\n",
+ isMAX ? "max" : "min", isF64 ? "f64" : "f32",
+ rch, dd, rch, nn, rch, mm);
+ return True;
+ }
+
/* ---------- Doesn't match anything. ---------- */
return False;
Modified: trunk/priv/host_arm_defs.c
==============================================================================
--- trunk/priv/host_arm_defs.c (original)
+++ trunk/priv/host_arm_defs.c Fri Jan 13 17:58:57 2017
@@ -1374,6 +1374,18 @@
i->ARMin.VRIntR.src = src;
return i;
}
+ARMInstr* ARMInstr_VMinMaxNum ( Bool isF64, Bool isMax,
+ HReg dst, HReg srcL, HReg srcR )
+{
+ ARMInstr* i = LibVEX_Alloc_inline(sizeof(ARMInstr));
+ i->tag = ARMin_VMinMaxNum;
+ i->ARMin.VMinMaxNum.isF64 = isF64;
+ i->ARMin.VMinMaxNum.isMax = isMax;
+ i->ARMin.VMinMaxNum.dst = dst ;
+ i->ARMin.VMinMaxNum.srcL = srcL;
+ i->ARMin.VMinMaxNum.srcR = srcR;
+ return i;
+}
ARMInstr* ARMInstr_FPSCR ( Bool toFPSCR, HReg iReg ) {
ARMInstr* i = LibVEX_Alloc_inline(sizeof(ARMInstr));
i->tag = ARMin_FPSCR;
@@ -1890,6 +1902,17 @@
ppHRegARM(i->ARMin.VRIntR.src);
return;
}
+ case ARMin_VMinMaxNum: {
+ const HChar* sz = i->ARMin.VMinMaxNum.isF64 ? "f64" : "f32";
+ const HChar* nm = i->ARMin.VMinMaxNum.isMax ? "vmaxnm" : "vminnm";
+ vex_printf("%s.%s ", nm, sz);
+ ppHRegARM(i->ARMin.VMinMaxNum.dst);
+ vex_printf(", ");
+ ppHRegARM(i->ARMin.VMinMaxNum.srcL);
+ vex_printf(", ");
+ ppHRegARM(i->ARMin.VMinMaxNum.srcR);
+ return;
+ }
case ARMin_FPSCR:
if (i->ARMin.FPSCR.toFPSCR) {
vex_printf("fmxr fpscr, ");
@@ -2289,6 +2312,11 @@
addHRegUse(u, HRmWrite, i->ARMin.VRIntR.dst);
addHRegUse(u, HRmRead, i->ARMin.VRIntR.src);
return;
+ case ARMin_VMinMaxNum:
+ addHRegUse(u, HRmWrite, i->ARMin.VMinMaxNum.dst);
+ addHRegUse(u, HRmRead, i->ARMin.VMinMaxNum.srcL);
+ addHRegUse(u, HRmRead, i->ARMin.VMinMaxNum.srcR);
+ return;
case ARMin_FPSCR:
if (i->ARMin.FPSCR.toFPSCR)
addHRegUse(u, HRmRead, i->ARMin.FPSCR.iReg);
@@ -2508,6 +2536,14 @@
i->ARMin.VRIntR.dst = lookupHRegRemap(m, i->ARMin.VRIntR.dst);
i->ARMin.VRIntR.src = lookupHRegRemap(m, i->ARMin.VRIntR.src);
return;
+ case ARMin_VMinMaxNum:
+ i->ARMin.VMinMaxNum.dst
+ = lookupHRegRemap(m, i->ARMin.VMinMaxNum.dst);
+ i->ARMin.VMinMaxNum.srcL
+ = lookupHRegRemap(m, i->ARMin.VMinMaxNum.srcL);
+ i->ARMin.VMinMaxNum.srcR
+ = lookupHRegRemap(m, i->ARMin.VMinMaxNum.srcR);
+ return;
case ARMin_FPSCR:
i->ARMin.FPSCR.iReg = lookupHRegRemap(m, i->ARMin.FPSCR.iReg);
return;
@@ -3900,6 +3936,38 @@
isF64 ? X1011 : X1010, X0100 | (M << 1), Vm);
goto done;
}
+ case ARMin_VMinMaxNum: {
+ Bool isF64 = i->ARMin.VMinMaxNum.isF64;
+ Bool isMax = i->ARMin.VMinMaxNum.isMax;
+ UInt rDst = (isF64 ? dregEnc : fregEnc)(i->ARMin.VMinMaxNum.dst);
+ UInt rSrcL = (isF64 ? dregEnc : fregEnc)(i->ARMin.VMinMaxNum.srcL);
+ UInt rSrcR = (isF64 ? dregEnc : fregEnc)(i->ARMin.VMinMaxNum.srcR);
+ /* The encoding of registers here differs strangely for the
+ F32 and F64 cases. */
+ UInt D, Vd, N, Vn, M, Vm;
+ if (isF64) {
+ D = (rDst >> 4) & 1;
+ Vd = rDst & 0xF;
+ N = (rSrcL >> 4) & 1;
+ Vn = rSrcL & 0xF;
+ M = (rSrcR >> 4) & 1;
+ Vm = rSrcR & 0xF;
+ } else {
+ Vd = (rDst >> 1) & 0xF;
+ D = rDst & 1;
+ Vn = (rSrcL >> 1) & 0xF;
+ N = rSrcL & 1;
+ Vm = (rSrcR >> 1) & 0xF;
+ M = rSrcR & 1;
+ }
+ vassert(D <= 1 && Vd <= 15 && M <= 1 && Vm <= 15 && N <= 1
+ && Vn <= 15);
+ *p++ = XXXXXXXX(X1111,X1110, X1000 | (D << 2), Vn, Vd,
+ X1010 | (isF64 ? 1 : 0),
+ (N << 3) | ((isMax ? 0 : 1) << 2) | (M << 1) | 0,
+ Vm);
+ goto done;
+ }
case ARMin_FPSCR: {
Bool toFPSCR = i->ARMin.FPSCR.toFPSCR;
UInt iReg = iregEnc(i->ARMin.FPSCR.iReg);
Modified: trunk/priv/host_arm_defs.h
==============================================================================
--- trunk/priv/host_arm_defs.h (original)
+++ trunk/priv/host_arm_defs.h Fri Jan 13 17:58:57 2017
@@ -596,6 +596,7 @@
ARMin_VXferS,
ARMin_VCvtID,
ARMin_VRIntR,
+ ARMin_VMinMaxNum,
ARMin_FPSCR,
ARMin_MFence,
ARMin_CLREX,
@@ -861,6 +862,15 @@
HReg dst;
HReg src;
} VRIntR;
+ /* Do Min/Max of F32 or F64 values, propagating the numerical arg
+ if the other is a qNaN. For ARM >= V8 hosts only. */
+ struct {
+ Bool isF64;
+ Bool isMax;
+ HReg dst;
+ HReg srcL;
+ HReg srcR;
+ } VMinMaxNum;
/* Move a 32-bit value to/from the FPSCR (FMXR, FMRX) */
struct {
Bool toFPSCR;
@@ -1016,6 +1026,8 @@
extern ARMInstr* ARMInstr_VCvtID ( Bool iToD, Bool syned,
HReg dst, HReg src );
extern ARMInstr* ARMInstr_VRIntR ( Bool isF64, HReg dst, HReg src );
+extern ARMInstr* ARMInstr_VMinMaxNum ( Bool isF64, Bool isMax,
+ HReg dst, HReg srcL, HReg srcR );
extern ARMInstr* ARMInstr_FPSCR ( Bool toFPSCR, HReg iReg );
extern ARMInstr* ARMInstr_MFence ( void );
extern ARMInstr* ARMInstr_CLREX ( void );
Modified: trunk/priv/host_arm_isel.c
==============================================================================
--- trunk/priv/host_arm_isel.c (original)
+++ trunk/priv/host_arm_isel.c Fri Jan 13 17:58:57 2017
@@ -5618,6 +5618,21 @@
/* not a V8 target, so we can't select insns for this. */
break;
}
+ case Iop_MaxNumF64:
+ case Iop_MinNumF64: {
+ /* Same comments regarding V8 support as for Iop_RoundF64toInt. */
+ if (VEX_ARM_ARCHLEVEL(env->hwcaps) >= 8) {
+ HReg srcL = iselDblExpr(env, e->Iex.Binop.arg1);
+ HReg srcR = iselDblExpr(env, e->Iex.Binop.arg2);
+ HReg dst = newVRegD(env);
+ Bool isMax = e->Iex.Binop.op == Iop_MaxNumF64;
+ addInstr(env, ARMInstr_VMinMaxNum(
+ True/*isF64*/, isMax, dst, srcL, srcR));
+ return dst;
+ }
+ /* not a V8 target, so we can't select insns for this. */
+ break;
+ }
default:
break;
}
@@ -5775,6 +5790,21 @@
/* not a V8 target, so we can't select insns for this. */
break;
}
+ case Iop_MaxNumF32:
+ case Iop_MinNumF32: {
+ /* Same comments regarding V8 support as for Iop_RoundF32toInt. */
+ if (VEX_ARM_ARCHLEVEL(env->hwcaps) >= 8) {
+ HReg srcL = iselFltExpr(env, e->Iex.Binop.arg1);
+ HReg srcR = iselFltExpr(env, e->Iex.Binop.arg2);
+ HReg dst = newVRegF(env);
+ Bool isMax = e->Iex.Binop.op == Iop_MaxNumF32;
+ addInstr(env, ARMInstr_VMinMaxNum(
+ False/*!isF64*/, isMax, dst, srcL, srcR));
+ return dst;
+ }
+ /* not a V8 target, so we can't select insns for this. */
+ break;
+ }
default:
break;
}
Modified: trunk/priv/ir_defs.c
==============================================================================
--- trunk/priv/ir_defs.c (original)
+++ trunk/priv/ir_defs.c Fri Jan 13 17:58:57 2017
@@ -354,6 +354,11 @@
case Iop_RecpExpF64: vex_printf("RecpExpF64"); return;
case Iop_RecpExpF32: vex_printf("RecpExpF32"); return;
+ case Iop_MaxNumF64: vex_printf("MaxNumF64"); return;
+ case Iop_MinNumF64: vex_printf("MinNumF64"); return;
+ case Iop_MaxNumF32: vex_printf("MaxNumF32"); return;
+ case Iop_MinNumF32: vex_printf("MinNumF32"); return;
+
case Iop_F16toF64: vex_printf("F16toF64"); return;
case Iop_F64toF16: vex_printf("F64toF16"); return;
case Iop_F16toF32: vex_printf("F16toF32"); return;
@@ -2838,7 +2843,13 @@
case Iop_RecpExpF32:
BINARY(ity_RMode,Ity_F32, Ity_F32);
- case Iop_CmpF32:
+ case Iop_MaxNumF64: case Iop_MinNumF64:
+ BINARY(Ity_F64,Ity_F64, Ity_F64);
+
+ case Iop_MaxNumF32: case Iop_MinNumF32:
+ BINARY(Ity_F32,Ity_F32, Ity_F32);
+
+ case Iop_CmpF32:
BINARY(Ity_F32,Ity_F32, Ity_I32);
case Iop_CmpF64:
Modified: trunk/pub/libvex_ir.h
==============================================================================
--- trunk/pub/libvex_ir.h (original)
+++ trunk/pub/libvex_ir.h Fri Jan 13 17:58:57 2017
@@ -776,6 +776,13 @@
Iop_RecpExpF64, /* FRECPX d :: IRRoundingMode(I32) x F64 -> F64 */
Iop_RecpExpF32, /* FRECPX s :: IRRoundingMode(I32) x F32 -> F32 */
+ /* --------- Possibly required by IEEE 754-2008. --------- */
+
+ Iop_MaxNumF64, /* max, F64, numerical operand if other is a qNaN */
+ Iop_MinNumF64, /* min, F64, ditto */
+ Iop_MaxNumF32, /* max, F32, ditto */
+ Iop_MinNumF32, /* min, F32, ditto */
+
/* ------------------ 16-bit scalar FP ------------------ */
Iop_F16toF64, /* F16 -> F64 */
|
|
From: <sv...@va...> - 2017-01-13 16:29:21
|
Author: petarj
Date: Fri Jan 13 16:29:15 2017
New Revision: 16201
Log:
mips64: update exp file for test_math
Leave the old exp file that covers cases in which __addtf3 and __subtf3
did not take into account rounding modes. New exp file is the same file
that already exists in mips32 folder, so we just create a symbolic link
to it.
Added:
trunk/none/tests/mips64/test_math.stdout.exp (with props)
trunk/none/tests/mips64/test_math.stdout.exp-older-gcc
- copied unchanged from r16200, trunk/none/tests/mips64/test_math.stdout.exp
Modified:
trunk/none/tests/mips64/Makefile.am
Modified: trunk/none/tests/mips64/Makefile.am
==============================================================================
--- trunk/none/tests/mips64/Makefile.am (original)
+++ trunk/none/tests/mips64/Makefile.am Fri Jan 13 16:29:15 2017
@@ -55,7 +55,8 @@
test_block_size.vgtest \
test_fcsr.stdout.exp test_fcsr.stderr.exp \
test_fcsr.vgtest \
- test_math.stdout.exp test_math.stderr.exp test_math.vgtest \
+ test_math.stdout.exp test_math.stdout.exp-older-gcc \
+ test_math.stderr.exp test_math.vgtest \
unaligned_load.stdout.exp-BE unaligned_load.stdout.exp-LE \
unaligned_load.stderr.exp unaligned_load.vgtest \
unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
Added: trunk/none/tests/mips64/test_math.stdout.exp
==============================================================================
--- trunk/none/tests/mips64/test_math.stdout.exp (added)
+++ trunk/none/tests/mips64/test_math.stdout.exp Fri Jan 13 16:29:15 2017
@@ -0,0 +1 @@
+link ../mips32/test_math.stdout.exp
\ No newline at end of file
|
|
From: <sv...@va...> - 2017-01-13 12:51:37
|
Author: sewardj
Date: Fri Jan 13 12:51:29 2017
New Revision: 3292
Log:
Implement:
VRINT{Z,R}.F64.F64 d_d, VRINT{Z,R}.F32.F32 s_s
VCVT{A,N,P,M}{.S32,.U32}{.F64,.F32}
Modified:
trunk/priv/guest_arm_toIR.c
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Fri Jan 13 12:51:29 2017
@@ -13508,7 +13508,6 @@
nCC(cond), isF64 ? "f64" : "f32", rch, dd, rch, nn, rch, mm);
return True;
}
- /* fall through */
/* -------- VRINT{A,N,P,M}.F64 d_d, VRINT{A,N,P,M}.F32 s_s -------- */
/* 31 22 21 17 15 11 8 7 5 4 3
@@ -13557,11 +13556,114 @@
(isF64 ? llPutDReg : llPutFReg)(dd, res);
UChar rch = isF64 ? 'd' : 'f';
- DIP("vrint%c.%s %c%u, %c%u\n",
- c, isF64 ? "f64" : "f32", rch, dd, rch, mm);
+ DIP("vrint%c.%s.%s %c%u, %c%u\n",
+ c, isF64 ? "f64" : "f32", isF64 ? "f64" : "f32", rch, dd, rch, mm);
+ return True;
+ }
+
+ /* -------- VRINT{Z,R}.F64.F64 d_d, VRINT{Z,R}.F32.F32 s_s -------- */
+ /* 31 27 22 21 15 11 7 6 5 4 3
+ T1: 1110 11101 D 110110 Vd 1011 op 1 M 0 Vm VRINT<r><c>.F64.F64 Dd, Dm
+ A1: cond 11101 D 110110 Vd 1011 op 1 M 0 Vm
+
+ T1: 1110 11101 D 110110 Vd 1010 op 1 M 0 Vm VRINT<r><c>.F32.F32 Sd, Sm
+ A1: cond 11101 D 110110 Vd 1010 op 1 M 0 Vm
+
+ In contrast to the VRINT variants just above, this can be conditional.
+ */
+ if ((isT ? (INSN(31,28) == BITS4(1,1,1,0)) : True)
+ && INSN(27,23) == BITS5(1,1,1,0,1) && INSN(21,16) == BITS6(1,1,0,1,1,0)
+ && INSN(11,9) == BITS3(1,0,1) && INSN(6,6) == 1 && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_Vd = INSN(15,12);
+ Bool isF64 = INSN(8,8) == 1;
+ Bool rToZero = INSN(7,7) == 1;
+ UInt bit_M = INSN(5,5);
+ UInt fld_Vm = INSN(3,0);
+ UInt dd = isF64 ? ((bit_D << 4) | fld_Vd) : ((fld_Vd << 1) | bit_D);
+ UInt mm = isF64 ? ((bit_M << 4) | fld_Vm) : ((fld_Vm << 1) | bit_M);
+
+ if (isT) vassert(condT != IRTemp_INVALID);
+ IRType ty = isF64 ? Ity_F64 : Ity_F32;
+ IRTemp src = newTemp(ty);
+ IRTemp res = newTemp(ty);
+ assign(src, (isF64 ? getDReg : getFReg)(mm));
+
+ IRTemp rm = newTemp(Ity_I32);
+ assign(rm, rToZero ? mkU32(Irrm_ZERO)
+ : mkexpr(mk_get_IR_rounding_mode()));
+ assign(res, binop(isF64 ? Iop_RoundF64toInt : Iop_RoundF32toInt,
+ mkexpr(rm), mkexpr(src)));
+ (isF64 ? putDReg : putFReg)(dd, mkexpr(res), condT);
+
+ UChar rch = isF64 ? 'd' : 'f';
+ DIP("vrint%c.%s.%s %c%u, %c%u\n",
+ rToZero ? 'z' : 'r',
+ isF64 ? "f64" : "f32", isF64 ? "f64" : "f32", rch, dd, rch, mm);
+ return True;
+ }
+
+ /* ----------- VCVT{A,N,P,M}{.S32,.U32}{.F64,.F32} ----------- */
+ /* 31 27 22 21 17 15 11 8 7 6 5 4 3
+ T1/A1: 1111 11101 D 1111 rm Vd 101 sz op 1 M 0 Vm
+ VCVT{A,N,P,M}{.S32,.U32}.F64 Sd, Dm
+ VCVT{A,N,P,M}{.S32,.U32}.F32 Sd, Sm
+
+ ARM encoding is in NV space.
+ In Thumb mode, we must not be in an IT block.
+ */
+ if (INSN(31,23) == BITS9(1,1,1,1,1,1,1,0,1) && INSN(21,18) == BITS4(1,1,1,1)
+ && INSN(11,9) == BITS3(1,0,1) && INSN(6,6) == 1 && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_rm = INSN(17,16);
+ UInt fld_Vd = INSN(15,12);
+ Bool isF64 = INSN(8,8) == 1;
+ Bool isU = INSN(7,7) == 0;
+ UInt bit_M = INSN(5,5);
+ UInt fld_Vm = INSN(3,0);
+
+ UInt dd = (fld_Vd << 1) | bit_D;
+ UInt mm = isF64 ? ((bit_M << 4) | fld_Vm) : ((fld_Vm << 1) | bit_M);
+
+ if (isT) {
+ gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+ }
+ /* In ARM mode, this is statically unconditional. In Thumb mode,
+ this must be dynamically unconditional, and we've SIGILLd if not.
+ In either case we can create unconditional IR. */
+
+ UChar c = '?';
+ IRRoundingMode rm = Irrm_NEAREST;
+ switch (fld_rm) {
+ /* The use of NEAREST for both the 'a' and 'n' cases is a bit of a
+ kludge since it doesn't take into account the nearest-even vs
+ nearest-away semantics. */
+ case BITS2(0,0): c = 'a'; rm = Irrm_NEAREST; break;
+ case BITS2(0,1): c = 'n'; rm = Irrm_NEAREST; break;
+ case BITS2(1,0): c = 'p'; rm = Irrm_PosINF; break;
+ case BITS2(1,1): c = 'm'; rm = Irrm_NegINF; break;
+ default: vassert(0);
+ }
+
+ IRExpr* srcM = (isF64 ? llGetDReg : llGetFReg)(mm);
+ IRTemp res = newTemp(Ity_I32);
+
+ /* The arm back end doesn't support use of Iop_F32toI32U or
+ Iop_F32toI32S, so for those cases we widen the F32 to F64
+ and then follow the F64 route. */
+ if (!isF64) {
+ srcM = unop(Iop_F32toF64, srcM);
+ }
+ assign(res, binop(isU ? Iop_F64toI32U : Iop_F64toI32S,
+ mkU32((UInt)rm), srcM));
+
+ llPutFReg(dd, unop(Iop_ReinterpI32asF32, mkexpr(res)));
+
+ UChar rch = isF64 ? 'd' : 'f';
+ DIP("vcvt%c.%s.%s %c%u, %c%u\n",
+ c, isU ? "u32" : "s32", isF64 ? "f64" : "f32", 's', dd, rch, mm);
return True;
}
- /* fall through */
/* ---------- Doesn't match anything. ---------- */
return False;
|
|
From: Ivo R. <iv...@iv...> - 2017-01-13 10:41:35
|
2017-01-12 20:36 GMT+01:00 Philippe Waroquiers < phi...@sk...>: > On Thu, 2017-01-12 at 13:37 +0100, Roland Mainz wrote: > > On Thu, Jan 12, 2017 at 1:31 PM, Petar Jovanovic <mip...@gm...> > wrote: > > > On Wed, Jan 4, 2017 at 3:21 PM, Philippe Waroquiers > > > <phi...@sk...> wrote: > > >> No sign of any tilegx user or developer activity since something like > > >> one year. > > >> No reply received for question in > > >> https://sourceforge.net/p/valgrind/mailman/message/35566192/ > > >> > > >> Is there any tilegx user or developer still active ? > > >> Should we consider this platform as dead ? > > >> > > > I have exchanged a few emails with Tilera/Mellanox compiler enigneers, > > > and they say they cannot take care of TileGx port in Valgrind for the > > > time being. > > > > Is there any emulator or other way we can use to test changes ? I > > don't like seeing such a port just disappear... > Well, if there is > no known users, > and no (original) developer doing maintenance > and no reply from (original) developers to simple questions > and no access to a system to test/compile > and no nightly build > and no tests in SVN > and no emulator > then IMO, this platform is a candidate to remove. > as just keeping this compiling forever for no reason will > at the end cost more than just removing it. > Agreed here. Although there are regtests under none/tests/tilegx there is no way to run them without any access to the machine or emulator. I. |
|
From: Philippe W. <phi...@sk...> - 2017-01-12 19:36:18
|
On Thu, 2017-01-12 at 13:37 +0100, Roland Mainz wrote: > On Thu, Jan 12, 2017 at 1:31 PM, Petar Jovanovic <mip...@gm...> wrote: > > On Wed, Jan 4, 2017 at 3:21 PM, Philippe Waroquiers > > <phi...@sk...> wrote: > >> No sign of any tilegx user or developer activity since something like > >> one year. > >> No reply received for question in > >> https://sourceforge.net/p/valgrind/mailman/message/35566192/ > >> > >> Is there any tilegx user or developer still active ? > >> Should we consider this platform as dead ? > >> > > I have exchanged a few emails with Tilera/Mellanox compiler enigneers, > > and they say they cannot take care of TileGx port in Valgrind for the > > time being. > > Is there any emulator or other way we can use to test changes ? I > don't like seeing such a port just disappear... Well, if there is no known users, and no (original) developer doing maintenance and no reply from (original) developers to simple questions and no access to a system to test/compile and no nightly build and no tests in SVN and no emulator then IMO, this platform is a candidate to remove. as just keeping this compiling forever for no reason will at the end cost more than just removing it. I will at least put this question as one of the things to discuss in FOSDEM 2017 Valgrind BoF. Also, IMO, for the future, we also have to put some mandatory requirements before accepting new platforms such as e.g. provide an access to a development system, at least for some time ensure a minimum of effort for maintenance/questions, provide tests, ... Philippe |
|
From: <sv...@va...> - 2017-01-12 14:38:05
|
Author: sewardj
Date: Thu Jan 12 14:37:58 2017
New Revision: 3291
Log:
Implement VRINT{A,N,P,M}.F64 d_d, VRINT{A,N,P,M}.F32 s_s.
Modified:
trunk/priv/guest_arm_toIR.c
trunk/priv/host_arm_defs.c
trunk/priv/host_arm_defs.h
trunk/priv/host_arm_isel.c
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Thu Jan 12 14:37:58 2017
@@ -13510,6 +13510,59 @@
}
/* fall through */
+ /* -------- VRINT{A,N,P,M}.F64 d_d, VRINT{A,N,P,M}.F32 s_s -------- */
+ /* 31 22 21 17 15 11 8 7 5 4 3
+ T1/A1: 111111101 D 1110 rm Vd 101 1 01 M 0 Vm VRINT{A,N,P,M}.F64 Dd, Dm
+ T1/A1: 111111101 D 1110 rm Vd 101 0 01 M 0 Vm VRINT{A,N,P,M}.F32 Sd, Sm
+
+ ARM encoding is in NV space.
+ In Thumb mode, we must not be in an IT block.
+ */
+ if (INSN(31,23) == BITS9(1,1,1,1,1,1,1,0,1)
+ && INSN(21,18) == BITS4(1,1,1,0) && INSN(11,9) == BITS3(1,0,1)
+ && INSN(7,6) == BITS2(0,1) && INSN(4,4) == 0) {
+ UInt bit_D = INSN(22,22);
+ UInt fld_rm = INSN(17,16);
+ UInt fld_d = INSN(15,12);
+ Bool isF64 = INSN(8,8) == 1;
+ UInt bit_M = INSN(5,5);
+ UInt fld_m = INSN(3,0);
+
+ UInt dd = isF64 ? ((bit_D << 4) | fld_d) : ((fld_d << 1) | bit_D);
+ UInt mm = isF64 ? ((bit_M << 4) | fld_m) : ((fld_m << 1) | bit_M);
+
+ if (isT) {
+ gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+ }
+ /* In ARM mode, this is statically unconditional. In Thumb mode,
+ this must be dynamically unconditional, and we've SIGILLd if not.
+ In either case we can create unconditional IR. */
+
+ UChar c = '?';
+ IRRoundingMode rm = Irrm_NEAREST;
+ switch (fld_rm) {
+ /* The use of NEAREST for both the 'a' and 'n' cases is a bit of a
+ kludge since it doesn't take into account the nearest-even vs
+ nearest-away semantics. */
+ case BITS2(0,0): c = 'a'; rm = Irrm_NEAREST; break;
+ case BITS2(0,1): c = 'n'; rm = Irrm_NEAREST; break;
+ case BITS2(1,0): c = 'p'; rm = Irrm_PosINF; break;
+ case BITS2(1,1): c = 'm'; rm = Irrm_NegINF; break;
+ default: vassert(0);
+ }
+
+ IRExpr* srcM = (isF64 ? llGetDReg : llGetFReg)(mm);
+ IRExpr* res = binop(isF64 ? Iop_RoundF64toInt : Iop_RoundF32toInt,
+ mkU32((UInt)rm), srcM);
+ (isF64 ? llPutDReg : llPutFReg)(dd, res);
+
+ UChar rch = isF64 ? 'd' : 'f';
+ DIP("vrint%c.%s %c%u, %c%u\n",
+ c, isF64 ? "f64" : "f32", rch, dd, rch, mm);
+ return True;
+ }
+ /* fall through */
+
/* ---------- Doesn't match anything. ---------- */
return False;
Modified: trunk/priv/host_arm_defs.c
==============================================================================
--- trunk/priv/host_arm_defs.c (original)
+++ trunk/priv/host_arm_defs.c Thu Jan 12 14:37:58 2017
@@ -1365,6 +1365,15 @@
i->ARMin.VCvtID.src = src;
return i;
}
+ARMInstr* ARMInstr_VRIntR ( Bool isF64, HReg dst, HReg src )
+{
+ ARMInstr* i = LibVEX_Alloc_inline(sizeof(ARMInstr));
+ i->tag = ARMin_VRIntR;
+ i->ARMin.VRIntR.isF64 = isF64;
+ i->ARMin.VRIntR.dst = dst ;
+ i->ARMin.VRIntR.src = src;
+ return i;
+}
ARMInstr* ARMInstr_FPSCR ( Bool toFPSCR, HReg iReg ) {
ARMInstr* i = LibVEX_Alloc_inline(sizeof(ARMInstr));
i->tag = ARMin_FPSCR;
@@ -1873,6 +1882,14 @@
ppHRegARM(i->ARMin.VCvtID.src);
return;
}
+ case ARMin_VRIntR: {
+ const HChar* sz = i->ARMin.VRIntR.isF64 ? "f64" : "f32";
+ vex_printf("vrintr.%s.%s ", sz, sz);
+ ppHRegARM(i->ARMin.VRIntR.dst);
+ vex_printf(", ");
+ ppHRegARM(i->ARMin.VRIntR.src);
+ return;
+ }
case ARMin_FPSCR:
if (i->ARMin.FPSCR.toFPSCR) {
vex_printf("fmxr fpscr, ");
@@ -2268,6 +2285,10 @@
addHRegUse(u, HRmWrite, i->ARMin.VCvtID.dst);
addHRegUse(u, HRmRead, i->ARMin.VCvtID.src);
return;
+ case ARMin_VRIntR:
+ addHRegUse(u, HRmWrite, i->ARMin.VRIntR.dst);
+ addHRegUse(u, HRmRead, i->ARMin.VRIntR.src);
+ return;
case ARMin_FPSCR:
if (i->ARMin.FPSCR.toFPSCR)
addHRegUse(u, HRmRead, i->ARMin.FPSCR.iReg);
@@ -2483,6 +2504,10 @@
i->ARMin.VCvtID.dst = lookupHRegRemap(m, i->ARMin.VCvtID.dst);
i->ARMin.VCvtID.src = lookupHRegRemap(m, i->ARMin.VCvtID.src);
return;
+ case ARMin_VRIntR:
+ i->ARMin.VRIntR.dst = lookupHRegRemap(m, i->ARMin.VRIntR.dst);
+ i->ARMin.VRIntR.src = lookupHRegRemap(m, i->ARMin.VRIntR.src);
+ return;
case ARMin_FPSCR:
i->ARMin.FPSCR.iReg = lookupHRegRemap(m, i->ARMin.FPSCR.iReg);
return;
@@ -3852,6 +3877,29 @@
/*UNREACHED*/
vassert(0);
}
+ case ARMin_VRIntR: { /* NB: ARM v8 and above only */
+ Bool isF64 = i->ARMin.VRIntR.isF64;
+ UInt rDst = (isF64 ? dregEnc : fregEnc)(i->ARMin.VRIntR.dst);
+ UInt rSrc = (isF64 ? dregEnc : fregEnc)(i->ARMin.VRIntR.src);
+ /* The encoding of registers here differs strangely for the
+ F32 and F64 cases. */
+ UInt D, Vd, M, Vm;
+ if (isF64) {
+ D = (rDst >> 4) & 1;
+ Vd = rDst & 0xF;
+ M = (rSrc >> 4) & 1;
+ Vm = rSrc & 0xF;
+ } else {
+ Vd = (rDst >> 1) & 0xF;
+ D = rDst & 1;
+ Vm = (rSrc >> 1) & 0xF;
+ M = rSrc & 1;
+ }
+ vassert(D <= 1 && Vd <= 15 && M <= 1 && Vm <= 15);
+ *p++ = XXXXXXXX(0xE, X1110, X1011 | (D << 2), X0110, Vd,
+ isF64 ? X1011 : X1010, X0100 | (M << 1), Vm);
+ goto done;
+ }
case ARMin_FPSCR: {
Bool toFPSCR = i->ARMin.FPSCR.toFPSCR;
UInt iReg = iregEnc(i->ARMin.FPSCR.iReg);
Modified: trunk/priv/host_arm_defs.h
==============================================================================
--- trunk/priv/host_arm_defs.h (original)
+++ trunk/priv/host_arm_defs.h Thu Jan 12 14:37:58 2017
@@ -595,6 +595,7 @@
ARMin_VXferD,
ARMin_VXferS,
ARMin_VCvtID,
+ ARMin_VRIntR,
ARMin_FPSCR,
ARMin_MFence,
ARMin_CLREX,
@@ -853,6 +854,13 @@
HReg dst;
HReg src;
} VCvtID;
+ /* Round a F32 or F64 value to the nearest integral value,
+ according to the FPSCR.RM. For ARM >= V8 hosts only. */
+ struct {
+ Bool isF64;
+ HReg dst;
+ HReg src;
+ } VRIntR;
/* Move a 32-bit value to/from the FPSCR (FMXR, FMRX) */
struct {
Bool toFPSCR;
@@ -1007,6 +1015,7 @@
extern ARMInstr* ARMInstr_VXferS ( Bool toS, HReg fD, HReg rLo );
extern ARMInstr* ARMInstr_VCvtID ( Bool iToD, Bool syned,
HReg dst, HReg src );
+extern ARMInstr* ARMInstr_VRIntR ( Bool isF64, HReg dst, HReg src );
extern ARMInstr* ARMInstr_FPSCR ( Bool toFPSCR, HReg iReg );
extern ARMInstr* ARMInstr_MFence ( void );
extern ARMInstr* ARMInstr_CLREX ( void );
Modified: trunk/priv/host_arm_isel.c
==============================================================================
--- trunk/priv/host_arm_isel.c (original)
+++ trunk/priv/host_arm_isel.c Thu Jan 12 14:37:58 2017
@@ -5603,6 +5603,21 @@
addInstr(env, ARMInstr_VUnaryD(ARMvfpu_SQRT, dst, src));
return dst;
}
+ case Iop_RoundF64toInt: {
+ /* We can only generate this on a >= V8 capable target. But
+ that's OK since we should only be asked to generate for V8
+ capable guests, and we assume here that host == guest. */
+ if (VEX_ARM_ARCHLEVEL(env->hwcaps) >= 8) {
+ HReg src = iselDblExpr(env, e->Iex.Binop.arg2);
+ HReg dst = newVRegD(env);
+ set_VFP_rounding_mode(env, e->Iex.Binop.arg1);
+ addInstr(env, ARMInstr_VRIntR(True/*isF64*/, dst, src));
+ set_VFP_rounding_default(env);
+ return dst;
+ }
+ /* not a V8 target, so we can't select insns for this. */
+ break;
+ }
default:
break;
}
@@ -5745,6 +5760,21 @@
set_VFP_rounding_default(env);
return valS;
}
+ case Iop_RoundF32toInt: {
+ /* We can only generate this on a >= V8 capable target. But
+ that's OK since we should only be asked to generate for V8
+ capable guests, and we assume here that host == guest. */
+ if (VEX_ARM_ARCHLEVEL(env->hwcaps) >= 8) {
+ HReg src = iselFltExpr(env, e->Iex.Binop.arg2);
+ HReg dst = newVRegF(env);
+ set_VFP_rounding_mode(env, e->Iex.Binop.arg1);
+ addInstr(env, ARMInstr_VRIntR(False/*!isF64*/, dst, src));
+ set_VFP_rounding_default(env);
+ return dst;
+ }
+ /* not a V8 target, so we can't select insns for this. */
+ break;
+ }
default:
break;
}
|