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Author: carll
Date: Sat Oct 8 00:08:02 2016
New Revision: 16032
Log:
ISA 3.0 BE testsuite fixes
In testing issues with the new ISA 3.0 instructions in BE mode, it was
found that we needed some more unique values in the operands to catch
various errors. The issue is a sigle 32-bit value was replicated four
times for a V128 operand. The result is testing loads and stores where
the word or half word order was swizzled couln't be detected because
they were the same. By making the 32-bit chunks unique we were able
to catch additional errors.
The VEX instruction fixes was committed in VEX commit 3260.
Bugzilla 369175
Added:
trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
trunk/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
Modified:
trunk/none/tests/ppc64/Makefile.am
trunk/none/tests/ppc64/ppc64_helpers.h
trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp
trunk/none/tests/ppc64/test_isa_3_0_other.stdout.exp
Modified: trunk/none/tests/ppc64/Makefile.am
==============================================================================
--- trunk/none/tests/ppc64/Makefile.am (original)
+++ trunk/none/tests/ppc64/Makefile.am Sat Oct 8 00:08:02 2016
@@ -38,8 +38,10 @@
test_touch_tm.stderr.exp test_touch_tm.stdout.exp test_touch_tm.vgtest \
ldst_multiple.stderr.exp ldst_multiple.stdout.exp ldst_multiple.vgtest \
data-cache-instructions.stderr.exp data-cache-instructions.stdout.exp data-cache-instructions.vgtest \
- test_isa_3_0_altivec.stderr.exp test_isa_3_0_altivec.stdout.exp test_isa_3_0_altivec.vgtest \
- test_isa_3_0_other.stderr.exp test_isa_3_0_other.stdout.exp test_isa_3_0_other.vgtest
+ test_isa_3_0_altivec.stderr.exp test_isa_3_0_altivec.stdout.exp \
+ test_isa_3_0_altivec.stdout.exp-LE test_isa_3_0_altivec.vgtest \
+ test_isa_3_0_other.stderr.exp test_isa_3_0_other.stdout.exp \
+ test_isa_3_0_other.stdout.exp-LE test_isa_3_0_other.vgtest
check_PROGRAMS = \
allexec \
Modified: trunk/none/tests/ppc64/ppc64_helpers.h
==============================================================================
--- trunk/none/tests/ppc64/ppc64_helpers.h (original)
+++ trunk/none/tests/ppc64/ppc64_helpers.h Sat Oct 8 00:08:02 2016
@@ -566,12 +566,16 @@
int x;
for (x = 0; x < BUFFER_SIZE; x++)
- switch(t) {
+ /* Don't want each of the 32-bit chunks to be identical. Loads of a
+ * byte from the wrong 32-bit chuck are not detectable if the chunks
+ * are identical.
+ */
+ switch((t+x)%BUFFER_SIZE) {
case 0:
buffer[x] = 0xffffffffffffffff;
break;
case 1:
- buffer[x] = 0xaaaaaaaaaaaaaaaa;
+ buffer[x] = 0x0001020304050607;
break;
case 2:
buffer[x] = 0x5555555555555555;
@@ -595,7 +599,7 @@
unsigned long pattern[PATTERN_SIZE] = {
0xffffffffffffffff,
0xaaaaaaaaaaaaaaaa,
- 0x5555555555555555,
+ 0x5152535455565758,
0x0000000000000000,
0xffaa5599113377cc,
};
Modified: trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp
==============================================================================
--- trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp (original)
+++ trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp Sat Oct 8 00:08:02 2016
@@ -635,1922 +635,1922 @@
xsaddqp 00000000000000000000000000000000 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
xsaddqp 00000000000000000000000000000000 000000000000000000007fffffffffff 00000000000000000000000000000000 => 000000000000000000007fffffffffff FPRF-C FPCC-FG
xsaddqp 00000000000000000000000000000000 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000000007fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 00ff0000000000000000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000000ff000000000000 00000000000000000000000000000000 => 000000000000000000ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 000000000000000000ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000000ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 07ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000007ff000000000000 00000000000000000000000000000000 => 000000000000000007ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000007ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 000000000000000007ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000007ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
-xsaddqp 00000000000000000000000000000000 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
-xsaddqp 00000000000000000000000000000000 00000000000000007fff000000000000 00000000000000000000000000000000 => 00000000000000007fff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007fff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00000000000000007fff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007fff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 80000000000000000000000000000000 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
-xsaddqp 00000000000000000000000000000000 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
-xsaddqp 00000000000000000000000000000000 00000000000000008000000000000000 00000000000000000000000000000000 => 00000000000000008000000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000008000000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
-xsaddqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80007fffffffffff0000000000000000 FPRF-C FPCC-FL
-xsaddqp 00000000000000000000000000000000 000000000000000080007fffffffffff 00000000000000000000000000000000 => 000000000000000080007fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080007fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 80ff0000000000000000000000000000 00000000000000000000000000000000 => 80ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => 000000000000000080ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000080ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 000000000000000080ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => 87ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => 000000000000000087ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000087ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 87ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 000000000000000087ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000087ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
-xsaddqp 00000000000000000000000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
-xsaddqp 00000000000000000000000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffff7fffffffffff FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff0000000000000000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff000000000000 00000000000000000000000000000000 => 000000000000000000ff000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000ff000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 000000000000000000ff7fffffffffff FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000000ff7fffffffffff FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff000000000000 00000000000000000000000000000000 => 000000000000000007ff000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000007ff000000000000 FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 000000000000000007ff7fffffffffff FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000007ff7fffffffffff FPCC-FG
+xsaddqp 00000000000000000000000000000000 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00000000000000007fff000000000000 00000000000000000000000000000000 => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsaddqp 00000000000000000000000000000000 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007fff000000000000 FPCC-FG FPCC-FU
+xsaddqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7fff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsaddqp 00000000000000000000000000000000 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000007fffffffffffffff FPRF-C FPCC-FU
+xsaddqp 00000000000000000000000000000000 80000000000000000000000000000000 00000000000000000000000000000000 => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80000000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 00000000000000008000000000000000 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
+xsaddqp 00000000000000000000000000000000 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
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+xsaddqp 00000000000000000000000000000000 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80007fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000080007fffffffffff 00000000000000000000000000000000 => 000000000000000080007fffffffffff FPRF-C FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080007fffffffffff FPRF-C FPCC-FL
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+xsaddqp 00000000000000000000000000000000 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => 000000000000000080ff000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000080ff000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
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+xsaddqp 00000000000000000000000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080ff7fffffffffff FPCC-FL
+xsaddqp 00000000000000000000000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => 87ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87ff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => 000000000000000087ff000000000000 FPCC-FL
+xsaddqp 00000000000000000000000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000087ff000000000000 FPCC-FL
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+xsaddqp 00000000000000000000000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87ff7fffffffffff0000000000000000 FPRF-C FPCC-FG
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+xsaddqp 00000000000000000000000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000087ff7fffffffffff FPCC-FL
+xsaddqp 00000000000000000000000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => ffff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff0000000000000000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 0000000000000000ffff000000000000 FPCC-FL FPCC-FU
+xsaddqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffff7fffffffffff0000000000000000 FPRF-C FPCC-FG
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
+xsaddqp 00000000000000000000000000000000 0000000000000000ffff7fffffffffff ffffffffffffffffffffffffffffffff => 0000000000000000ffffffffffffffff FPRF-C FPCC-FU
xsaddqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 00000000000000000000000000000000 => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
xsaddqp 00007fffffffffff0000000000000000 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
xsaddqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 00000000000000000000000000000000 => 0000fffffffffffe0000000000000000 FPRF-C FPCC-FG
xsaddqp 00007fffffffffff0000000000000000 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 0000fffffffffffe0000000000000000 FPRF-C FPCC-FG
xsaddqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff 00000000000000000000000000000000 => 00007fffffffffff00007fffffffffff FPRF-C FPCC-FG
xsaddqp 00007fffffffffff0000000000000000 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff00007fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 00000000000000000000000000000000 => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 00000000000000000000000000000000 => 00007fffffffffff00ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff00ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff00ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff00ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 00000000000000000000000000000000 => 07ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 00000000000000000000000000000000 => 00007fffffffffff07ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff07ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 07ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff07ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff07ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 00000000000000000000000000000000 => 00007fffffffffff7fff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff7fff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 00000000000000000000000000000000 => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff7fff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00000000000000007fff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff7fff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 00000000000000000000000000000000 => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff0000000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 00000000000000000000000000000000 => 00007fffffffffff8000000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff8000000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 00000000000000000000000000000000 FPCC-FE
-xsaddqp 00007fffffffffff0000000000000000 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00000000000000000000000000000000 FPCC-FE
-xsaddqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff 00000000000000000000000000000000 => 00007fffffffffff80007fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff80007fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 00000000000000000000000000000000 => 80ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 00000000000000000000000000000000 => 00007fffffffffff80ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff80ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff80ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff80ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 00000000000000000000000000000000 => 87ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87ff0000000000000000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 00000000000000000000000000000000 => 00007fffffffffff87ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff87ff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 87ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffff87ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 00007fffffffffff87ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 00000000000000000000000000000000 => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 ffff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => ffff0000000000000000000000000000 FPCC-FL FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 00000000000000000000000000000000 => 00007fffffffffffffff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffffffff000000000000 FPRF-C FPCC-FG
-xsaddqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 00000000000000000000000000000000 => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 00007fffffffffff0000000000000000 0000000000000000ffff7fffffffffff 00000000000000000000000000000000 => 00007fffffffffffffff7fffffffffff FPRF-C FPCC-FG
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xsaddqp 000000000000000000007fffffffffff 00000000000000000000000000000000 00000000000000000000000000000000 => 000000000000000000007fffffffffff FPRF-C FPCC-FG
xsaddqp 000000000000000000007fffffffffff 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000007fffffffffff FPRF-C FPCC-FG
xsaddqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 00000000000000000000000000000000 => 00007fffffffffff00007fffffffffff FPRF-C FPCC-FG
xsaddqp 000000000000000000007fffffffffff 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff00007fffffffffff FPRF-C FPCC-FG
xsaddqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff 00000000000000000000000000000000 => 00000000000000000000fffffffffffe FPRF-C FPCC-FG
xsaddqp 000000000000000000007fffffffffff 000000000000000000007fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000000000fffffffffffe FPRF-C FPCC-FG
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-xsaddqp 000000000000000000007fffffffffff 00ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 00ff0000000000000000000000000000 FPCC-FG
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-xsaddqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 00ff7fffffffffff0000000000000000 FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 00ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00ff7fffffffffff0000000000000000 FPCC-FG
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-xsaddqp 000000000000000000007fffffffffff 000000000000000000ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000000fffffffffffffe FPRF-C FPCC-FG
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-xsaddqp 000000000000000000007fffffffffff 07ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 07ff0000000000000000000000000000 FPCC-FG
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-xsaddqp 000000000000000000007fffffffffff 000000000000000007ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000007ff7fffffffffff FPRF-C FPCC-FG
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-xsaddqp 000000000000000000007fffffffffff 000000000000000007ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000007fffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 00000000000000000000000000000000 => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
-xsaddqp 000000000000000000007fffffffffff 7fff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 7fff0000000000000000000000000000 FPCC-FG FPCC-FU
-xsaddqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 00000000000000000000000000000000 => 00000000000000007fff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 00000000000000007fff000000000000 ffffffffffffffffffffffffffffffff => 00000000000000007fff7fffffffffff FPRF-C FPCC-FG
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-xsaddqp 000000000000000000007fffffffffff 7fff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 7fffffffffffffff0000000000000000 FPRF-C FPCC-FU
-xsaddqp 000000000000000000007fffffffffff 00000000000000007fff7fffffffffff 00000000000000000000000000000000 => 00000000000000007ffffffffffffffe FPRF-C FPCC-FG
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-xsaddqp 000000000000000000007fffffffffff 80000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000007fffffffffff FPRF-C FPCC-FG
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-xsaddqp 000000000000000000007fffffffffff 00000000000000008000000000000000 ffffffffffffffffffffffffffffffff => 000000000000000080007fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 00000000000000000000000000000000 => 80007ffffffffffeffff800000000001 FPRF-C FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 80007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80007ffffffffffeffff800000000001 FPRF-C FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff 00000000000000000000000000000000 => 00000000000000008000fffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000080007fffffffffff ffffffffffffffffffffffffffffffff => 00000000000000008000fffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 00000000000000000000000000000000 => 80ff0000000000000000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 80ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 80ff0000000000000000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 00000000000000000000000000000000 => 000000000000000080ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000080ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000080ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 00000000000000000000000000000000 => 80ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 80ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 80ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff 00000000000000000000000000000000 => 000000000000000080fffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000080ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000080fffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 00000000000000000000000000000000 => 87ff0000000000000000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 87ff0000000000000000000000000000 ffffffffffffffffffffffffffffffff => 87ff0000000000000000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 00000000000000000000000000000000 => 000000000000000087ff7fffffffffff FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000087ff000000000000 ffffffffffffffffffffffffffffffff => 000000000000000087ff7fffffffffff FPRF-C FPCC-FG
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-xsaddqp 000000000000000000007fffffffffff 87ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 87ff7fffffffffff0000000000000000 FPCC-FL
-xsaddqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff 00000000000000000000000000000000 => 000000000000000087fffffffffffffe FPRF-C FPCC-FG
-xsaddqp 000000000000000000007fffffffffff 000000000000000087ff7fffffffffff ffffffffffffffffffffffffffffffff => 000000000000000087fffffffffffffe FPRF-C FPCC-FG
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-xsaddqp 000000000000000000007fffffffffff ffff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => ffffffffffffffff0000000000000000 FPRF-C FPCC-FU
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-xsaddqp 00ff0000000000000000000000000000 07ff7fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 07ff7fffffffffff0000000000000000 FPCC-FG
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-xsaddqp 000000000000000000ff000000000000 00000000000000000000000000000000 ffffffffffffffffffffffffffffffff => 000000000000000000ff000000000000 FPRF-C FPCC-FG
-xsaddqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 00000000000000000000000000000000 => 00007fffffffffff00ff000000000000 FPRF-C FPCC-FG
-xsaddqp 000000000000000000ff000000000000 00007fffffffffff0000000000000000 ffffffffffffffffffffffffffffffff => 00007fffffffffff00ff000000000000 FPRF-C FPCC-FG
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-xsaddqp 000000000000000000ff00000...
[truncated message content] |
|
From: <sv...@va...> - 2016-10-07 22:54:01
|
Author: carll
Date: Fri Oct 7 23:53:52 2016
New Revision: 3260
Log:
ISA 3.0 BE fixes for various new instructions
This is an additional commit to fix issues found with the
new Power ISA 3.0 instructions for BE mode. The instructions
fixed in this patch include: lxvl, lxvx, lxvwsx, lxvh8x, lxvh16x,
stxvx, stxvh8x, stxvh16x, lxsibzx, lxsihzx, xscvqpdp, xscvqpdp0,
xvcvsphp.
Bugzilla 369175
Modified:
trunk/priv/guest_ppc_toIR.c
trunk/priv/host_ppc_isel.c
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Fri Oct 7 23:53:52 2016
@@ -19166,10 +19166,6 @@
/* only supported on ISA 3.0 and newer */
IRTemp result = newTemp( Ity_V128 );
IRTemp tmp64 = newTemp( Ity_I64 );
- IRTemp f0 = newTemp( Ity_I64 );
- IRTemp f1 = newTemp( Ity_I64 );
- IRTemp f2 = newTemp( Ity_I64 );
- IRTemp f3 = newTemp( Ity_I64 );
if (!allow_isa_3_0) return False;
DIP("xvcvsphp v%d,v%d\n", XT,XB);
@@ -19178,26 +19174,32 @@
* I64 result to the V128 register to store.
*/
assign( tmp64, unop( Iop_F32toF16x4, mkexpr( vB ) ) );
- assign( f0,binop( Iop_And64,
- mkU64( 0xFFFF ), mkexpr( tmp64 ) ) );
- assign( f1, binop( Iop_And64,
- mkU64( 0xFFFF0000 ), mkexpr( tmp64 ) ) );
- assign( f2, binop( Iop_And64,
- mkU64( 0xFFFF00000000 ), mkexpr( tmp64 ) ) );
- assign( f3, binop( Iop_And64,
- mkU64( 0xFFFF000000000000 ), mkexpr( tmp64 ) ) );
- /* Scater 16-bit float values from returned 64-bit value
+ /* Scatter 16-bit float values from returned 64-bit value
* of V128 result.
*/
- assign( result,
- binop( Iop_Perm8x16,
- binop( Iop_64HLtoV128,
- mkU64( 0 ),
- mkexpr( tmp64 ) ),
- binop ( Iop_64HLtoV128,
- mkU64( 0x0000080900000A0B ),
- mkU64( 0x00000C0D00000E0F ) ) ) );
+ if (host_endness == VexEndnessLE)
+ /* Note location 0 may have a valid number in it. Location
+ * 15 should always be zero. Use 0xF to put zeros in the
+ * desired bytes.
+ */
+ assign( result,
+ binop( Iop_Perm8x16,
+ binop( Iop_64HLtoV128,
+ mkexpr( tmp64 ),
+ mkU64( 0 ) ),
+ binop ( Iop_64HLtoV128,
+ mkU64( 0x0F0F00010F0F0203 ),
+ mkU64( 0x0F0F04050F0F0607 ) ) ) );
+ else
+ assign( result,
+ binop( Iop_Perm8x16,
+ binop( Iop_64HLtoV128,
+ mkexpr( tmp64 ),
+ mkU64( 0 ) ),
+ binop ( Iop_64HLtoV128,
+ mkU64( 0x0F0F06070F0F0405 ),
+ mkU64( 0x0F0F02030F0F0001 ) ) ) );
putVSReg( XT, mkexpr( result ) );
} else if ( inst_select == 31 ) {
@@ -19526,31 +19528,43 @@
DIP("lxvx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
- for ( i = 0; i< 4; i++ ) {
- word[i] = newTemp( Ity_I64 );
-
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ if ( host_endness == VexEndnessBE ) {
+ for ( i = 3; i>= 0; i-- ) {
+ word[i] = newTemp( Ity_I64 );
- assign( word[i], unop( Iop_32Uto64,
- load( Ity_I32, irx_addr ) ) );
- ea_off += 4;
- }
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ assign( word[i], unop( Iop_32Uto64,
+ load( Ity_I32, irx_addr ) ) );
+ ea_off += 4;
+ }
- if ( host_endness == VexEndnessBE )
putVSReg( XT, binop( Iop_64HLtoV128,
binop( Iop_Or64,
- mkexpr( word[0] ),
+ mkexpr( word[2] ),
binop( Iop_Shl64,
- mkexpr( word[1] ),
+ mkexpr( word[3] ),
mkU8( 32 ) ) ),
binop( Iop_Or64,
- mkexpr( word[3] ),
+ mkexpr( word[0] ),
binop( Iop_Shl64,
- mkexpr( word[2] ),
+ mkexpr( word[1] ),
mkU8( 32 ) ) ) ) );
+ } else {
+ for ( i = 0; i< 4; i++ ) {
+ word[i] = newTemp( Ity_I64 );
+
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ assign( word[i], unop( Iop_32Uto64,
+ load( Ity_I32, irx_addr ) ) );
+ ea_off += 4;
+ }
- else
putVSReg( XT, binop( Iop_64HLtoV128,
binop( Iop_Or64,
mkexpr( word[2] ),
@@ -19562,6 +19576,7 @@
binop( Iop_Shl64,
mkexpr( word[1] ),
mkU8( 32 ) ) ) ) );
+ }
break;
}
@@ -19619,78 +19634,104 @@
mkU64( 8 ) ) ),
mkexpr( nb_gt16 ) ) );
-
/* fetch all 16 bytes, we will remove what we don't want later */
- for ( i = 0; i < 8; i++ ) {
- byte[i] = newTemp( Ity_I64 );
- tmp_low[i+1] = newTemp( Ity_I64 );
-
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- ea_off += 1;
+ if ( host_endness == VexEndnessBE ) {
+ for ( i = 0; i < 8; i++ ) {
+ byte[i] = newTemp( Ity_I64 );
+ tmp_hi[i+1] = newTemp( Ity_I64 );
+
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 1;
- if ( host_endness == VexEndnessBE )
assign( byte[i], binop( Iop_Shl64,
+ unop( Iop_8Uto64,
+ load( Ity_I8, irx_addr ) ),
+ mkU8( 8 * ( 7 - i ) ) ) );
+
+ assign( tmp_hi[i+1], binop( Iop_Or64,
+ mkexpr( byte[i] ),
+ mkexpr( tmp_hi[i] ) ) );
+ }
+
+ for ( i = 0; i < 8; i++ ) {
+ byte[i+8] = newTemp( Ity_I64 );
+ tmp_low[i+1] = newTemp( Ity_I64 );
+
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 1;
+
+ assign( byte[i+8], binop( Iop_Shl64,
unop( Iop_8Uto64,
load( Ity_I8, irx_addr ) ),
mkU8( 8 * ( 7 - i ) ) ) );
- else
- /* Reverse byte order */
+ assign( tmp_low[i+1], binop( Iop_Or64,
+ mkexpr( byte[i+8] ),
+ mkexpr( tmp_low[i] ) ) );
+ }
+ assign( ld_result, binop( Iop_ShlV128,
+ binop( Iop_ShrV128,
+ binop( Iop_64HLtoV128,
+ mkexpr( tmp_hi[8] ),
+ mkexpr( tmp_low[8] ) ),
+ mkexpr( shift ) ),
+ mkexpr( shift ) ) );
+ } else {
+ for ( i = 0; i < 8; i++ ) {
+ byte[i] = newTemp( Ity_I64 );
+ tmp_low[i+1] = newTemp( Ity_I64 );
+
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 1;
+
assign( byte[i], binop( Iop_Shl64,
unop( Iop_8Uto64,
load( Ity_I8, irx_addr ) ),
mkU8( 8 * i ) ) );
- assign( tmp_low[i+1],
- binop( Iop_Or64,
- mkexpr( byte[i] ), mkexpr( tmp_low[i] ) ) );
- }
-
- for ( i = 0; i < 8; i++ ) {
- byte[i + 8] = newTemp( Ity_I64 );
- tmp_hi[i+1] = newTemp( Ity_I64 );
+ assign( tmp_low[i+1],
+ binop( Iop_Or64,
+ mkexpr( byte[i] ), mkexpr( tmp_low[i] ) ) );
+ }
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- ea_off += 1;
+ for ( i = 0; i < 8; i++ ) {
+ byte[i + 8] = newTemp( Ity_I64 );
+ tmp_hi[i+1] = newTemp( Ity_I64 );
+
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 1;
- if ( host_endness == VexEndnessBE )
- assign( byte[i+8], binop( Iop_Shl64,
- unop( Iop_8Uto64,
- load( Ity_I8, irx_addr ) ),
- mkU8( 8 * ( 7 - i ) ) ) );
-
- else
- /* Reverse byte order */
assign( byte[i+8], binop( Iop_Shl64,
unop( Iop_8Uto64,
load( Ity_I8, irx_addr ) ),
mkU8( 8 * i ) ) );
- assign( tmp_hi[i+1], binop( Iop_Or64,
- mkexpr( byte[i+8] ),
- mkexpr( tmp_hi[i] ) ) );
- }
-
- if ( host_endness == VexEndnessBE )
- assign( ld_result, binop( Iop_ShrV128,
- binop( Iop_64HLtoV128,
- mkexpr( tmp_hi[8] ),
- mkexpr( tmp_low[8] ) ),
- mkexpr( shift ) ) );
- else
+ assign( tmp_hi[i+1], binop( Iop_Or64,
+ mkexpr( byte[i+8] ),
+ mkexpr( tmp_hi[i] ) ) );
+ }
assign( ld_result, binop( Iop_ShrV128,
binop( Iop_ShlV128,
binop( Iop_64HLtoV128,
- mkexpr( tmp_low[8] ),
- mkexpr( tmp_hi[8] ) ),
+ mkexpr( tmp_hi[8] ),
+ mkexpr( tmp_low[8] ) ),
mkexpr( shift ) ),
mkexpr( shift ) ) );
+ }
- /* If nb = 0, make out the calculated load result so the stored
+
+ /* If nb = 0, mask out the calculated load result so the stored
* value is zero.
*/
+
putVSReg( XT, binop( Iop_AndV128,
mkexpr( ld_result ),
binop( Iop_64HLtoV128,
@@ -19808,9 +19849,23 @@
/* The load is a 64-bit fetch that is Endian aware, just want
* the lower 32 bits. */
- assign( data, binop( Iop_And64,
- load( Ity_I64, mkexpr( EA ) ),
- mkU64( 0xFFFFFFFF ) ) );
+ if ( host_endness == VexEndnessBE ) {
+ UInt ea_off = 4;
+ IRExpr* irx_addr;
+
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Sub8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ assign( data, binop( Iop_And64,
+ load( Ity_I64, irx_addr ),
+ mkU64( 0xFFFFFFFF ) ) );
+
+ } else {
+ assign( data, binop( Iop_And64,
+ load( Ity_I64, mkexpr( EA ) ),
+ mkU64( 0xFFFFFFFF ) ) );
+ }
/* Take lower 32-bits and spat across the four word positions */
putVSReg( XT,
@@ -19825,7 +19880,6 @@
binop( Iop_Shl64,
mkexpr( data ),
mkU8( 32 ) ) ) ) );
-
break;
}
@@ -19860,10 +19914,17 @@
case 0x30D: // lxsibzx
{
IRExpr *byte;
+ IRExpr* irx_addr;
DIP("lxsibzx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
- byte = load( Ity_I64, mkexpr( EA ) );
+ if ( host_endness == VexEndnessBE )
+ irx_addr = binop( Iop_Sub64, mkexpr( EA ), mkU64( 7 ) );
+
+ else
+ irx_addr = mkexpr( EA );
+
+ byte = load( Ity_I64, irx_addr );
putVSReg( XT, binop( Iop_64HLtoV128,
binop( Iop_And64,
byte,
@@ -19875,10 +19936,17 @@
case 0x32D: // lxsihzx
{
IRExpr *byte;
+ IRExpr* irx_addr;
DIP("lxsihzx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
- byte = load( Ity_I64, mkexpr( EA ) );
+ if ( host_endness == VexEndnessBE )
+ irx_addr = binop( Iop_Sub64, mkexpr( EA ), mkU64( 6 ) );
+
+ else
+ irx_addr = mkexpr( EA );
+
+ byte = load( Ity_I64, irx_addr );
putVSReg( XT, binop( Iop_64HLtoV128,
binop( Iop_And64,
byte,
@@ -19958,21 +20026,14 @@
ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
ea_off += 2;
- if ( host_endness == VexEndnessBE )
assign( h_word[i], binop( Iop_Shl64,
unop( Iop_16Uto64,
load( Ity_I16, irx_addr ) ),
- mkU8( 16 * i ) ) );
+ mkU8( 16 * ( 3 - i ) ) ) );
- else
- assign( h_word[i], binop( Iop_Shl64,
- unop( Iop_16Uto64,
- load( Ity_I16, irx_addr ) ),
- mkU8( 16 * (3 - i) ) ) );
-
- assign( tmp_low[i+1],
- binop( Iop_Or64,
- mkexpr( h_word[i] ), mkexpr( tmp_low[i] ) ) );
+ assign( tmp_low[i+1],
+ binop( Iop_Or64,
+ mkexpr( h_word[i] ), mkexpr( tmp_low[i] ) ) );
}
for ( i = 0; i < 4; i++ ) {
@@ -19986,7 +20047,8 @@
assign( h_word[i+4], binop( Iop_Shl64,
unop( Iop_16Uto64,
load( Ity_I16, irx_addr ) ),
- mkU8( 16 * (3 - i) ) ) );
+ mkU8( 16 * ( 3 - i ) ) ) );
+
assign( tmp_hi[i+1], binop( Iop_Or64,
mkexpr( h_word[i+4] ),
mkexpr( tmp_hi[i] ) ) );
@@ -20020,17 +20082,10 @@
ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
ea_off += 1;
- if ( host_endness == VexEndnessBE )
- assign( byte[i], binop( Iop_Shl64,
- unop( Iop_8Uto64,
- load( Ity_I8, irx_addr ) ),
- mkU8( 8 * i ) ) );
-
- else
- assign( byte[i], binop( Iop_Shl64,
- unop( Iop_8Uto64,
- load( Ity_I8, irx_addr ) ),
- mkU8( 8 * ( 7 - i ) ) ) );
+ assign( byte[i], binop( Iop_Shl64,
+ unop( Iop_8Uto64,
+ load( Ity_I8, irx_addr ) ),
+ mkU8( 8 * ( 7 - i ) ) ) );
assign( tmp_low[i+1],
binop( Iop_Or64,
@@ -20203,47 +20258,24 @@
unop( Iop_V128to64, mkexpr( vS ) ),
mkU64( 0xFFFFFFFF ) ) );
+ store( mkexpr( EA ), unop( Iop_64to32, mkexpr( word0 ) ) );
- if ( host_endness == VexEndnessBE ) {
- store( mkexpr( EA ), unop( Iop_64to32, mkexpr( word3 ) ) );
-
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
-
- store( irx_addr, unop( Iop_64to32, mkexpr( word2 ) ) );
-
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
-
- store( irx_addr, unop( Iop_64to32, mkexpr( word1 ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
-
- store( irx_addr, unop( Iop_64to32, mkexpr( word0 ) ) );
-
- } else {
- store( mkexpr( EA ), unop( Iop_64to32, mkexpr( word0 ) ) );
-
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32, mkexpr( word1 ) ) );
+ store( irx_addr, unop( Iop_64to32, mkexpr( word1 ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32, mkexpr( word2 ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ store( irx_addr, unop( Iop_64to32, mkexpr( word2 ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32, mkexpr( word3 ) ) );
- }
+ store( irx_addr, unop( Iop_64to32, mkexpr( word3 ) ) );
break;
}
@@ -20849,43 +20881,86 @@
mkU64( 0xFFFF ) ) );
/* Do the 32-bit stores. The store() does an Endian aware store. */
- store( mkexpr( EA ), unop( Iop_64to32,
- binop( Iop_Or64,
- mkexpr( half_word0 ),
- binop( Iop_Shl64,
- mkexpr( half_word1 ),
- mkU8( 16 ) ) ) ) );
+ if ( host_endness == VexEndnessBE ) {
+ store( mkexpr( EA ), unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word1 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word0 ),
+ mkU8( 16 ) ) ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32,
- binop( Iop_Or64,
- mkexpr( half_word2 ),
- binop( Iop_Shl64,
- mkexpr( half_word3 ),
- mkU8( 16 ) ) ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr, unop( Iop_64to32,
- binop( Iop_Or64,
- mkexpr( half_word4 ),
- binop( Iop_Shl64,
- mkexpr( half_word5 ),
- mkU8( 16 ) ) ) ) );
- ea_off += 4;
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ store( irx_addr, unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word3 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word2 ),
+ mkU8( 16 ) ) ) ) );
- store( irx_addr, unop( Iop_64to32,
- binop( Iop_Or64,
- mkexpr( half_word6 ),
- binop( Iop_Shl64,
- mkexpr( half_word7 ),
- mkU8( 16 ) ) ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word5 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word4 ),
+ mkU8( 16 ) ) ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word7 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word6 ),
+ mkU8( 16 ) ) ) ) );
+
+ } else {
+ store( mkexpr( EA ), unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word0 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word1 ),
+ mkU8( 16 ) ) ) ) );
+
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word2 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word3 ),
+ mkU8( 16 ) ) ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word4 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word5 ),
+ mkU8( 16 ) ) ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32,
+ binop( Iop_Or64,
+ mkexpr( half_word6 ),
+ binop( Iop_Shl64,
+ mkexpr( half_word7 ),
+ mkU8( 16 ) ) ) ) );
+ }
break;
}
@@ -20915,27 +20990,54 @@
mkU64( 0xFF ) ) );
}
- for ( i = 0; i < 16; i = i + 4) {
- irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
- ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ if ( host_endness == VexEndnessBE ) {
+ for ( i = 0; i < 16; i = i + 4) {
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
- store( irx_addr,
- unop( Iop_64to32,
- binop( Iop_Or64,
- binop( Iop_Or64,
- mkexpr( byte[i] ),
- binop( Iop_Shl64,
- mkexpr( byte[i+1] ),
- mkU8( 8 ) ) ),
- binop( Iop_Or64,
- binop( Iop_Shl64,
- mkexpr( byte[i+2] ),
- mkU8( 16 ) ),
- binop( Iop_Shl64,
- mkexpr( byte[i+3] ),
- mkU8( 24 ) ) ) ) ) );
+ store( irx_addr,
+ unop( Iop_64to32,
+ binop( Iop_Or64,
+ binop( Iop_Or64,
+ mkexpr( byte[i+3] ),
+ binop( Iop_Shl64,
+ mkexpr( byte[i+2] ),
+ mkU8( 8 ) ) ),
+ binop( Iop_Or64,
+ binop( Iop_Shl64,
+ mkexpr( byte[i+1] ),
+ mkU8( 16 ) ),
+ binop( Iop_Shl64,
+ mkexpr( byte[i] ),
+ mkU8( 24 ) ) ) ) ) );
+ ea_off += 4;
+ }
- ea_off += 4;
+ } else {
+ for ( i = 0; i < 16; i = i + 4) {
+ irx_addr =
+ binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr,
+ unop( Iop_64to32,
+ binop( Iop_Or64,
+ binop( Iop_Or64,
+ mkexpr( byte[i] ),
+ binop( Iop_Shl64,
+ mkexpr( byte[i+1] ),
+ mkU8( 8 ) ) ),
+ binop( Iop_Or64,
+ binop( Iop_Shl64,
+ mkexpr( byte[i+2] ),
+ mkU8( 16 ) ),
+ binop( Iop_Shl64,
+ mkexpr( byte[i+3] ),
+ mkU8( 24 ) ) ) ) ) );
+
+ ea_off += 4;
+ }
}
break;
}
@@ -21314,13 +21416,20 @@
/* store 64-bit float in upper 64-bits of 128-bit register,
* lower 64-bits are zero.
*/
- assign( vT,
- binop( Iop_F64HLtoF128,
- mkexpr( ftmp ),
- unop( Iop_ReinterpI64asF64, mkU64( 0 ) ) ) );
+ if (host_endness == VexEndnessLE)
+ assign( vT,
+ binop( Iop_F64HLtoF128,
+ mkexpr( ftmp ),
+ unop( Iop_ReinterpI64asF64, mkU64( 0 ) ) ) );
+ else
+ assign( vT,
+ binop( Iop_F64HLtoF128,
+ unop( Iop_ReinterpI64asF64, mkU64( 0 ) ),
+ mkexpr( ftmp ) ) );
assign( tmp, unop( Iop_ReinterpF64asI64,
unop( Iop_F128HItoF64, mkexpr( vT ) ) ) );
+
generate_store_FPRF( Ity_I64, tmp );
break;
}
Modified: trunk/priv/host_ppc_isel.c
==============================================================================
--- trunk/priv/host_ppc_isel.c (original)
+++ trunk/priv/host_ppc_isel.c Fri Oct 7 23:53:52 2016
@@ -2349,7 +2349,8 @@
HReg r2 = newVRegI(env); /* I16*/
HReg r3 = newVRegI(env); /* I16*/
HReg vsrc = iselVecExpr(env, e->Iex.Unop.arg, IEndianess);
- PPCAMode *am_off0, *am_off2, *am_off4, *am_off6, *am_off8, *am_off12;
+ PPCAMode *am_off0, *am_off2, *am_off4, *am_off6, *am_off8;
+ PPCAMode *am_off10, *am_off12, *am_off14;
HReg r_aligned16;
sub_from_sp( env, 32 ); // Move SP down
@@ -2364,23 +2365,26 @@
am_off4 = PPCAMode_IR( 4, r_aligned16 );
am_off6 = PPCAMode_IR( 6, r_aligned16 );
am_off8 = PPCAMode_IR( 8, r_aligned16 );
+ am_off10 = PPCAMode_IR( 10, r_aligned16 );
am_off12 = PPCAMode_IR( 12, r_aligned16 );
+ am_off14 = PPCAMode_IR( 14, r_aligned16 );
/* Store v128 result to stack. */
+ addInstr(env, PPCInstr_AvLdSt(False/*store*/, 16, vdst, am_off0));
+
+ /* fetch four I16 from V128, store into contiguous I64 via stack, */
if (IEndianess == Iend_LE) {
- addInstr(env, PPCInstr_AvLdSt(False/*store*/, 16, vdst, am_off0));
+ addInstr(env, PPCInstr_Load( 2, r3, am_off12, mode64));
+ addInstr(env, PPCInstr_Load( 2, r2, am_off8, mode64));
+ addInstr(env, PPCInstr_Load( 2, r1, am_off4, mode64));
+ addInstr(env, PPCInstr_Load( 2, r0, am_off0, mode64));
} else {
- addInstr(env, PPCInstr_AvLdSt(False/*store*/, 16, vdst, am_off8));
+ addInstr(env, PPCInstr_Load( 2, r0, am_off14, mode64));
+ addInstr(env, PPCInstr_Load( 2, r1, am_off10, mode64));
+ addInstr(env, PPCInstr_Load( 2, r2, am_off6, mode64));
+ addInstr(env, PPCInstr_Load( 2, r3, am_off2, mode64));
}
- /* fetch four I16 from V128, store into contiguous I64 via stack, */
-
- /* get 16-bit values */
- addInstr(env, PPCInstr_Load( 2, r3, am_off12, mode64));
- addInstr(env, PPCInstr_Load( 2, r2, am_off8, mode64));
- addInstr(env, PPCInstr_Load( 2, r1, am_off4, mode64));
- addInstr(env, PPCInstr_Load( 2, r0, am_off0, mode64));
-
/* store in contiguous 64-bit values */
addInstr(env, PPCInstr_Store( 2, am_off6, r3, mode64));
addInstr(env, PPCInstr_Store( 2, am_off4, r2, mode64));
@@ -2388,11 +2392,8 @@
addInstr(env, PPCInstr_Store( 2, am_off0, r0, mode64));
/* Fetch I64 */
- if (IEndianess == Iend_LE) {
- addInstr(env, PPCInstr_Load(8, dst, am_off0, mode64));
- } else {
- addInstr(env, PPCInstr_Load(8, dst, am_off8, mode64));
- }
+ addInstr(env, PPCInstr_Load(8, dst, am_off0, mode64));
+
add_to_sp( env, 32 ); // Reset SP
return dst;
}
@@ -4197,7 +4198,12 @@
*/
sub_from_sp( env, 16 );
addInstr(env, PPCInstr_AvLdSt(False/*store*/, 16, tmp, zero_r1));
- addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_dst, eight_r1));
+ if (IEndianess == Iend_LE)
+ addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_dst, eight_r1));
+ else
+ /* High 64-bits stored at lower address */
+ addInstr(env, PPCInstr_FpLdSt(True/*load*/, 8, fr_dst, zero_r1));
+
add_to_sp( env, 16 );
return fr_dst;
|
|
From: osjup <dam...@gm...> - 2016-10-07 20:40:49
|
Julian Seward-2 wrote > Details of what's new in 3.12.0 will be in the NEWS file, > although that is somewhat incomplete at present. Some of the > highlights are: > ... > - Preliminary support for macOS 10.12 (Sierra) Preliminary support means I should already be able to use it, with the 'risk' of having some bugs right? Or it's not yet the point? Because when I'm trying just to configure it on my 10.12 I get this error: > configure: error: Valgrind works on Darwin 10.x, 11.x, 12.x, 13.x, 14.x > and 15.x (Mac OS X 10.6/7/8/9/10/11) Not sure whether it was meant to be like that in this beta, or not, so I thought I would just let you know. -- View this message in context: http://valgrind.10908.n7.nabble.com/Valgrind-3-12-0-BETA-is-available-for-testing-tp56801p56860.html Sent from the Valgrind - Dev mailing list archive at Nabble.com. |
|
From: <sv...@va...> - 2016-10-07 17:04:46
|
Author: petarj
Date: Fri Oct 7 18:04:33 2016
New Revision: 16031
Log:
mips32: add pselect6 to the list of supported syscalls
Add pselect6 to the list of supported syscalls on MIPS32.
It fixes:
none/tests/pselect_alarm (stderr)
none/tests/pselect_sigmask_null (stderr)
on mips32 platforms.
Patch by Aleksandra Karadzic.
Modified:
trunk/coregrind/m_syswrap/syswrap-mips32-linux.c
Modified: trunk/coregrind/m_syswrap/syswrap-mips32-linux.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-mips32-linux.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-mips32-linux.c Fri Oct 7 18:04:33 2016
@@ -1138,7 +1138,7 @@
LINX_ (__NR_readlinkat, sys_readlinkat), // 298
LINX_ (__NR_fchmodat, sys_fchmodat), // 299
LINX_ (__NR_faccessat, sys_faccessat), // 300
- //..
+ LINXY (__NR_pselect6, sys_pselect6), // 301
LINXY (__NR_ppoll, sys_ppoll), // 302
//..
LINX_ (__NR_set_robust_list, sys_set_robust_list), // 309
|
|
From: <sv...@va...> - 2016-10-07 07:58:07
|
Author: cborntra
Date: Fri Oct 7 08:58:00 2016
New Revision: 16030
Log:
fix building the dfp testcase
Modified:
trunk/configure.ac
Modified: trunk/configure.ac
==============================================================================
--- trunk/configure.ac (original)
+++ trunk/configure.ac Fri Oct 7 08:58:00 2016
@@ -1435,8 +1435,12 @@
AC_MSG_CHECKING([that assembler knows DFP])
AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[
]], [[
+ #ifdef __s390__
+ __asm__ __volatile__("adtr 1, 2, 3")
+ #else
__asm__ __volatile__("dadd 1, 2, 3");
__asm__ __volatile__("dcffix 1, 2");
+ #endif
]])], [
ac_asm_have_dfp=yes
AC_MSG_RESULT([yes])
@@ -1449,8 +1453,12 @@
CFLAGS="-mhard-dfp -Werror"
AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[
]], [[
+ #ifdef __s390__
+ __asm__ __volatile__("adtr 1, 2, 3")
+ #else
__asm__ __volatile__("dadd 1, 2, 3");
__asm__ __volatile__("dcffix 1, 2");
+ #endif
]])], [
ac_compiler_have_dfp=yes
AC_MSG_RESULT([yes])
@@ -1475,7 +1483,7 @@
AC_MSG_RESULT([no])
])
AM_CONDITIONAL(BUILD_DFP_TESTS, test x$ac_compiler_have_dfp_type = xyes \
- -a xHWCAP_$HAS_DFP = xyes )
+ -a x$HWCAP_HAS_DFP = xyes )
# HTM (Hardware Transactional Memory)
|
|
From: <sv...@va...> - 2016-10-07 07:20:15
|
Author: cborntra
Date: Fri Oct 7 08:20:08 2016
New Revision: 16029
Log:
actually test high-word by providing the plumbing...
Added:
trunk/none/tests/s390x/high-word.stderr.exp
trunk/none/tests/s390x/high-word.stdout.exp
trunk/none/tests/s390x/high-word.vgtest
Added: trunk/none/tests/s390x/high-word.stderr.exp
==============================================================================
--- trunk/none/tests/s390x/high-word.stderr.exp (added)
+++ trunk/none/tests/s390x/high-word.stderr.exp Fri Oct 7 08:20:08 2016
@@ -0,0 +1,2 @@
+
+
Added: trunk/none/tests/s390x/high-word.stdout.exp
==============================================================================
--- trunk/none/tests/s390x/high-word.stdout.exp (added)
+++ trunk/none/tests/s390x/high-word.stdout.exp Fri Oct 7 08:20:08 2016
@@ -0,0 +1,19 @@
+brcth 5 x 3 (cnt=0x500000003): ...+...+...+...+...+ (cnt=0x0)
+brcth 1 x 30 (cnt=0x10000001e): ..............................+ (cnt=0x0)
+brcth 16 x 1 (cnt=0x1000000001): .+.+.+.+.+.+.+.+.+.+.+.+.+.+.+.+ (cnt=0x0)
+RISBLG r1(==3a41e0a2afde1559),r2(==765487c11cd04ac4),0x00,0x1f,0x00 = 3a41e0a21cd04ac4
+RISBLG r1(==765487c11cd04ac4),r2(==3a41e0a2afde1559),0x00,0x9f,0x00 = 765487c1afde1559
+RISBLG r1(==765487c11cd04ac4),r2(==3a41e0a2afde1559),0x00,0x1f,0x20 = 765487c13a41e0a2
+RISBLG r1(==3a41e0a2afde1559),r2(==765487c11cd04ac4),0x00,0x9f,0x20 = 3a41e0a2765487c1
+RISBHG r1(==b9cd1bdd399bef32),r2(==f8efadb884334ddd),0x00,0x1f,0x00 = f8efadb8399bef32
+RISBHG r1(==f8efadb884334ddd),r2(==b9cd1bdd399bef32),0x00,0x9f,0x00 = b9cd1bdd84334ddd
+RISBHG r1(==f8efadb884334ddd),r2(==b9cd1bdd399bef32),0x00,0x1f,0x20 = 399bef3284334ddd
+RISBHG r1(==b9cd1bdd399bef32),r2(==f8efadb884334ddd),0x00,0x9f,0x20 = 84334ddd399bef32
+RISBLG r1(==b9cd1bdd399bef32),r2(==3a41e0a2afde1559),0x0b,0x13,0x05 = b9cd1bdd3982af32
+RISBLG r1(==b9cd1bdd399bef32),r2(==3a41e0a2afde1559),0x0b,0x93,0x05 = b9cd1bdd0002a000
+RISBHG r1(==3a41e0a2afde1559),r2(==b9cd1bdd399bef32),0x03,0x0c,0x25 = 3379e0a2afde1559
+RISBHG r1(==3a41e0a2afde1559),r2(==b9cd1bdd399bef32),0x03,0x8c,0x25 = 13780000afde1559
+RISBLG r1(==765487c11cd04ac4),r2(==f8efadb884334ddd),0x1d,0x07,0x0c = 765487c134d04ac6
+RISBLG r1(==765487c11cd04ac4),r2(==f8efadb884334ddd),0x1d,0x87,0x0c = 765487c134000006
+RISBHG r1(==f8efadb884334ddd),r2(==765487c11cd04ac4),0x0c,0x03,0x25 = 98e9588e84334ddd
+RISBHG r1(==f8efadb884334ddd),r2(==765487c11cd04ac4),0x0c,0x83,0x25 = 9009588e84334ddd
Added: trunk/none/tests/s390x/high-word.vgtest
==============================================================================
--- trunk/none/tests/s390x/high-word.vgtest (added)
+++ trunk/none/tests/s390x/high-word.vgtest Fri Oct 7 08:20:08 2016
@@ -0,0 +1,2 @@
+prog: high-word
+prereq: ../../../tests/s390x_features 's390x-highw'
|
|
From: <sv...@va...> - 2016-10-07 07:13:30
|
Author: cborntra
Date: Fri Oct 7 08:13:24 2016
New Revision: 16028
Log:
s390/highword fix compile warning with some compilers
Modified:
trunk/none/tests/s390x/high-word.c
Modified: trunk/none/tests/s390x/high-word.c
==============================================================================
--- trunk/none/tests/s390x/high-word.c (original)
+++ trunk/none/tests/s390x/high-word.c Fri Oct 7 08:13:24 2016
@@ -5,8 +5,8 @@
#define BRASLCLOBBER "0","1","2","3","4","5","14", \
"f0","f1","f2","f3","f4","f5","f6","f7","memory","cc"
-static void inner_iter() { putchar('.'); }
-static void outer_iter() { putchar('+'); }
+void inner_iter() { putchar('.'); }
+void outer_iter() { putchar('+'); }
static void
check_brcth(int m, int n)
|
|
From: <sv...@va...> - 2016-10-07 07:09:51
|
Author: cborntra
Date: Fri Oct 7 08:09:40 2016
New Revision: 16027
Log:
s390: support RISBLG/RISBHG, MVCIN, LDE/LDER
patch by Andreas Arnez <ar...@li...>
Added:
trunk/none/tests/s390x/high-word.c
Modified:
trunk/NEWS
trunk/docs/internals/s390-opcodes.csv
trunk/none/tests/s390x/Makefile.am
trunk/none/tests/s390x/bfp-2.c
trunk/none/tests/s390x/bfp-2.stdout.exp
trunk/none/tests/s390x/mvc.c
trunk/none/tests/s390x/mvc.stdout.exp
trunk/none/tests/s390x/opcodes.h
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Fri Oct 7 08:09:40 2016
@@ -189,6 +189,7 @@
369402 Bad set/get_thread_area pointer crashes valgrind
369441 bad lvec argument crashes process_vm_readv/writev syscall wrappers
369446 valgrind crashes on unknown fcntl command
+369439 S390x: Unhandled insns RISBLG/RISBHG and LDE/LDER
n-i-bz Fix incorrect (or infinite loop) unwind on RHEL7 x86 and amd64
n-i-bz massif --pages-as-heap=yes does not report peak caused by mmap+munmap
Modified: trunk/docs/internals/s390-opcodes.csv
==============================================================================
--- trunk/docs/internals/s390-opcodes.csv (original)
+++ trunk/docs/internals/s390-opcodes.csv Fri Oct 7 08:09:40 2016
@@ -68,7 +68,7 @@
epair,"extract primary ASN and instance",N/A,"privileged instruction"
ereg,"extract stacked registers","not implemented",
esar,"extract secondary ASN",N/A,"privileged instruction",
-esair,"extract secondary ASN and instance,N/A,"privileged instruction",
+esair,"extract secondary ASN and instance",N/A,"privileged instruction",
esta,"extract stacked state","not implemented",
ex,execute,implemented,
hdr,"halve (long)","won't do","hfp instruction"
@@ -125,7 +125,7 @@
msta,"modify stacked state","not implemented",
mvc,move,implemented,
mvcdk,"move with destination key",N/A,"privileged instruction"
-mvcin,"move inverse","not implemented",
+mvcin,"move inverse",implemented,
mvck,"move with key",N/A,"privileged instruction"
mvcl,"move long",implemented,
mvcp,"move to primary",N/A,"privileged instruction"
@@ -548,8 +548,8 @@
lxd,"load lengthened long to extended hfp","won't do","hfp instruction"
lxer,"load lengthened short to extended hfp","won't do","hfp instruction"
lxe,"load lengthened short to extended hfp","won't do","hfp instruction"
-lder,"load lengthened short to long hfp","won't do","hfp instruction"
-lde,"load lengthened short to long hfp","won't do","hfp instruction"
+lder,"load lengthened short to long hfp",implemented,"hfp instruction"
+lde,"load lengthened short to long hfp",implemented,"hfp instruction"
lnxr,"load negative extended hfp","won't do","hfp instruction"
lpxr,"load positive extended hfp","won't do","hfp instruction"
lexr,"load rounded extended to short hfp","won't do","hfp instruction"
@@ -840,7 +840,7 @@
alhhlr,"add logical high low",implemented,
alsih,"add logical with signed immediate high with cc",implemented,
alsihn,"add logical with signed immediate high no cc",implemented,
-brcth,"branch relative on count high","not implemented",
+brcth,"branch relative on count high",implemented,
chhr,"compare high high",implemented,
chlr,"compare high low",implemented,
chf,"compare high",implemented,
@@ -854,8 +854,8 @@
lfh,"load high",implemented,
llch,"load logical character high",implemented,
llhh,"load logical halfword high",implemented,
-risbhg,"rotate then insert selected bits high","not implemented",
-risblg,"rotate then insert selected bits low","not implemented",
+risbhg,"rotate then insert selected bits high",implemented,
+risblg,"rotate then insert selected bits low",implemented,
stch,"store character high",implemented,
sthh,"store halfword high",implemented,
stfh,"store high",implemented,
@@ -980,3 +980,520 @@
cxzt,"convert from zoned extended","not implemented",zEC12,
czdt,"convert to zoned long","not implemented",zEC12,
czxt,"convert to zoned extended","not implemented",zEC12,
+vfsdb,"vector fp subtract","not implemented",z13
+vlpf,"vector load positive word","not implemented",z13
+verllh,"vector element rotate left logical mem halfword","not implemented",z13
+vzero,"vector set to zero","not implemented",z13
+vmalof,"vector multiply and add logical odd word","not implemented",z13
+vleif,"vector load word element immediate","not implemented",z13
+vlpb,"vector load positive byte","not implemented",z13
+vmxlh,"vector maximum logical halfword","not implemented",z13
+vpksfs,"vector pack saturate word","not implemented",z13
+vfenezh,"vector find element not equal halfword","not implemented",z13
+vecl,"vector element compare logical","not implemented",z13
+verimb,"vector element rotate and insert under mask byte","not implemented",z13
+vaccq,"vector add compute carry quadword","not implemented",z13
+vleh,"vector load halfword element","not implemented",z13
+vst,"vector store","not implemented",z13
+vsteg,"vector store double word element","not implemented",z13
+vmnf,"vector minimum word","not implemented",z13
+vavgl,"vector average logical","not implemented",z13
+vfpsodb,"vector fp perform sign operation","not implemented",z13
+llzrgf,"load logical and zero rightmost bytes 32->64","not implemented",z13
+vledb,"vector fp load rounded","not implemented",z13
+vldeb,"vector fp load lengthened","not implemented",z13
+vclzg,"vector count leading zeros doubleword","not implemented",z13
+vecg,"vector element compare double word","not implemented",z13
+vpksgs,"vector pack saturate double word","not implemented",z13
+vsel,"vector select","not implemented",z13
+vllezb,"vector load logical byte element and zero","not implemented",z13
+vfaezh,"vector find any element equal","not implemented",z13
+vftci,"vector fp test data class immediate","not implemented",z13
+veclb,"vector element compare logical byte","not implemented",z13
+vuplhw,"vector unpack low halfword","not implemented",z13
+veslvb,"vector element shift left reg byte","not implemented",z13
+vuplh,"vector unpack logical high","not implemented",z13
+vlde,"vector fp load lengthened","not implemented",z13
+vmoh,"vector multiply odd halfword","not implemented",z13
+vfaehs,"vector find any element equal","not implemented",z13
+vftcidb,"vector fp test data class immediate","not implemented",z13
+vaq,"vector add quad word","not implemented",z13
+vlgvh,"vector load gr from vr halfword element","not implemented",z13
+vchlg,"vector compare high logical double word","not implemented",z13
+vlvgp,"vector load VR from GRs disjoint","not implemented",z13
+vceqg,"vector compare equal double word","not implemented",z13
+vfeezh,"vector find element equal halfword","not implemented",z13
+vlvgf,"vector load VR word element from GR","not implemented",z13
+vsteb,"vector store byte element","not implemented",z13
+vgmb,"vector generate mask byte","not implemented",z13
+vpklsf,"vector pack logical saturate word","not implemented",z13
+vmao,"vector multiply and add odd","not implemented",z13
+vchf,"vector compare high word","not implemented",z13
+vesraf,"vector element shift right arithmetic mem word","not implemented",z13
+vsbiq,"vector subtract with borrow indication quadword","not implemented",z13
+vuphb,"vector unpack high byte","not implemented",z13
+vgfmb,"vector galois field multiply sum byte","not implemented",z13
+vrepih,"vector replicate immediate halfword","not implemented",z13
+vcdlg,"vector fp convert from logical 64 bit","not implemented",z13
+cxpt,"convert from packed to extended dfp","not implemented",z13
+vceqb,"vector compare equal byte","not implemented",z13
+vstrczfs,"vector string range compare word","not implemented",z13
+vpklshs,"vector pack logical saturate halfword","not implemented",z13
+vlvgb,"vector load VR byte element from GR","not implemented",z13
+lcbb,"load count to block boundary","not implemented",z13
+vlcf,"vector load complement word","not implemented",z13
+vlvg,"vector load VR element from GR","not implemented",z13
+vmalef,"vector multiply and add logical even word","not implemented",z13
+vn,"vector and","not implemented",z13
+vmae,"vector multiply and add even","not implemented",z13
+vstrc,"vector string range compare","not implemented",z13
+vfcedb,"vector fp compare equal","not implemented",z13
+vgfm,"vector galois field multiply sum","not implemented",z13
+vlrepb,"vector load and replicate byte elements","not implemented",z13
+vgfmag,"vector galois field multiply sum and accumulate doubleword","not implemented",z13
+vflndb,"vector fp perform sign operation","not implemented",z13
+vmaeb,"vector multiply and add even byte","not implemented",z13
+vpkg,"vector pack double word","not implemented",z13
+vsb,"vector subtract byte","not implemented",z13
+vchl,"vector compare high logical","not implemented",z13
+vlvgh,"vector load VR halfword element from GR","not implemented",z13
+locghi,"load halfword immediate on condition into 64 bit gpr","not implemented",z13
+vmalb,"vector multiply and add low byte","not implemented",z13
+vchlgs,"vector compare high logical double word","not implemented",z13
+vstef,"vector store word element","not implemented",z13
+lzrf,"load and zero rightmost byte 32->32","not implemented",z13
+vmrlh,"vector merge low halfword","not implemented",z13
+vchbs,"vector compare high byte","not implemented",z13
+vesrlf,"vector element shift right logical mem word","not implemented",z13
+vmxf,"vector maximum word","not implemented",z13
+vgmh,"vector generate mask halfword","not implemented",z13
+vfenezb,"vector find element not equal byte","not implemented",z13
+vpklsgs,"vector pack logical saturate double word","not implemented",z13
+vpksg,"vector pack saturate double word","not implemented",z13
+vfaeh,"vector find any element equal halfword","not implemented",z13
+vmlof,"vector multiply logical odd word","not implemented",z13
+vmahh,"vector multiply and add high halfword","not implemented",z13
+vx,"vector exclusive or","not implemented",z13
+vchlfs,"vector compare high logical word","not implemented",z13
+vacccq,"vector add with carry compute carry quadword","not implemented",z13
+vchb,"vector compare high byte","not implemented",z13
+vmaloh,"vector multiply and add logical odd halfword","not implemented",z13
+vmleh,"vector multiply logical even halfword","not implemented",z13
+verimh,"vector element rotate and insert under mask halfword","not implemented",z13
+vlrepf,"vector load and replicate word elements","not implemented",z13
+vgfmg,"vector galois field multiply sum doubleword","not implemented",z13
+vpklsg,"vector pack logical saturate double word","not implemented",z13
+vesrlvf,"vector element shift right logical reg word","not implemented",z13
+vrepg,"vector replicate double word","not implemented",z13
+vmalob,"vector multiply and add logical odd byte","not implemented",z13
+vmxb,"vector maximum byte","not implemented",z13
+vmnl,"vector minimum logical","not implemented",z13
+vmng,"vector minimum doubleword","not implemented",z13
+vchlb,"vector compare high logical byte","not implemented",z13
+wfadb,"vector fp add","not implemented",z13
+vmrl,"vector merge low","not implemented",z13
+wfk,"vector fp compare and signal scalar","not implemented",z13
+vno,"vector nor","not implemented",z13
+vstrcf,"vector string range compare word","not implemented",z13
+vfmsdb,"vector fp multiply and subtract","not implemented",z13
+vavgh,"vector average half word","not implemented",z13
+vchlhs,"vector compare high logical half word","not implemented",z13
+vah,"vector add halfword","not implemented",z13
+vmalhh,"vector multiply and add logical high halfword","not implemented",z13
+wldeb,"vector fp load lengthened","not implemented",z13
+vmrh,"vector merge high","not implemented",z13
+vclgdb,"vector fp convert to logical 64 bit","not implemented",z13
+wfsqdb,"vector fp square root","not implemented",z13
+vpopct,"vector population count","not implemented",z13
+vfenef,"vector find element not equal word","not implemented",z13
+vgfmf,"vector galois field multiply sum word","not implemented",z13
+vgmf,"vector generate mask word","not implemented",z13
+vleg,"vector load double word element","not implemented",z13
+vmn,"vector minimum","not implemented",z13
+vrepi,"vector replicate immediate","not implemented",z13
+vsegb,"vector sign extend byte to double word","not implemented",z13
+cpxt,"convert from extended dfp to packed","not implemented",z13
+wftcidb,"vector fp test data class immediate","not implemented",z13
+wfchedbs,"vector fp compare high or equal","not implemented",z13
+vpks,"vector pack saturate","not implemented",z13
+veslg,"vector element shift left mem doubleword","not implemented",z13
+vupllb,"vector unpack logical low byte","not implemented",z13
+vscbig,"vector subtract compute borrow indication doubleword","not implemented",z13
+vsegh,"vector sign extend halfword to double word","not implemented",z13
+vsumb,"vector sum across word - byte elements","not implemented",z13
+vgeg,"vector gather element 8 byte elements","not implemented",z13
+vcgd,"vector fp convert to fixed 64 bit","not implemented",z13
+vuplhb,"vector unpack logical high byte","not implemented",z13
+verllv,"vector element rotate left logical reg","not implemented",z13
+vavgb,"vector average byte","not implemented",z13
+veclh,"vector element compare logical half word","not implemented",z13
+vfmadb,"vector fp multiply and add","not implemented",z13
+vesravb,"vector element shift right arithmetic reg byte","not implemented",z13
+vmaleb,"vector multiply and add logical even byte","not implemented",z13
+vuplf,"vector unpack low word","not implemented",z13
+vsbi,"vector subtract with borrow indication","not implemented",z13
+vupll,"vector unpack logical low","not implemented",z13
+vmrhh,"vector merge high halfword","not implemented",z13
+vfenezbs,"vector find element not equal byte","not implemented",z13
+vmhb,"vector multiply high byte","not implemented",z13
+vfmdb,"vector fp multiply","not implemented",z13
+vesrlg,"vector element shift right logical mem doubleword","not implemented",z13
+vmahb,"vector multiply and add high byte","not implemented",z13
+vstrczf,"vector string range compare word","not implemented",z13
+wfcedb,"vector fp compare equal","not implemented",z13
+vscbih,"vector subtract compute borrow indication halfword","not implemented",z13
+vlch,"vector load complement halfword","not implemented",z13
+vfenebs,"vector find element not equal byte","not implemented",z13
+vpklsh,"vector pack logical saturate halfword","not implemented",z13
+vlgv,"vector load gr from vr element","not implemented",z13
+vchfs,"vector compare high word","not implemented",z13
+vctzb,"vector count trailing zeros byte","not implemented",z13
+vfaef,"vector find any element equal word","not implemented",z13
+vstrch,"vector string range compare halfword","not implemented",z13
+wfidb,"vector load fp integer","not implemented",z13
+vmrhb,"vector merge high byte","not implemented",z13
+vuph,"vector unpack high","not implemented",z13
+vperm,"vector permute","not implemented",z13
+vrep,"vector replicate","not implemented",z13
+vmalhb,"vector multiply and add logical high byte","not implemented",z13
+vleib,"vector load byte element immediate","not implemented",z13
+vavg,"vector average","not implemented",z13
+vfenefs,"vector find element not equal word","not implemented",z13
+vsumh,"vector sum across word - halfword elements","not implemented",z13
+vchh,"vector compare high half word","not implemented",z13
+wcdgb,"vector fp convert from fixed 64 bit","not implemented",z13
+verllvb,"vector element rotate left logical reg byte","not implemented",z13
+vec,"vector element compare","not implemented",z13
+vpdi,"vector permute double word immediate","not implemented",z13
+vfchedb,"vector fp compare high or equal","not implemented",z13
+vchlh,"vector compare high logical half word","not implemented",z13
+vmaleh,"vector multiply and add logical even halfword","not implemented",z13
+vstrcb,"vector string range compare byte","not implemented",z13
+vsumqg,"vector sum across quadword - doubleword elements","not implemented",z13
+vlc,"vector load complement","not implemented",z13
+vlreph,"vector load and replicate halfword elements","not implemented",z13
+vistrb,"vector isolate string byte","not implemented",z13
+vmo,"vector multiply odd","not implemented",z13
+vmxg,"vector maximum doubleword","not implemented",z13
+vsrab,"vector shift right arithmetic by byte","not implemented",z13
+vsbcbiq,"vector subtract with borrow compute borrow indication quadword","not implemented",z13
+wfchdb,"vector fp compare high","not implemented",z13
+vmlhf,"vector multiply logical high word","not implemented",z13
+vesra,"vector element shift right arithmetic mem","not implemented",z13
+vmnh,"vector minimum halfword","not implemented",z13
+vled,"vector fp load rounded","not implemented",z13
+vstrczbs,"vector string range compare byte","not implemented",z13
+vaccb,"vector add compute carry byte","not implemented",z13
+vmahf,"vector multiply and add high word","not implemented",z13
+wfcedbs,"vector fp compare equal","not implemented",z13
+vmeh,"vector multiply even halfword","not implemented",z13
+vclzb,"vector count leading zeros byte","not implemented",z13
+vmh,"vector multiply high","not implemented",z13
+vllez,"vector load logical element and zero","not implemented",z13
+vnc,"vector and with complement","not implemented",z13
+vesrlvg,"vector element shift right logical reg doubleword","not implemented",z13
+vrepif,"vector replicate immediate word","not implemented",z13
+vfd,"vector fp divide","not implemented",z13
+vesrlb,"vector element shift right logical mem byte","not implemented",z13
+vavglg,"vector average logical double word","not implemented",z13
+vpksh,"vector pack saturate halfword","not implemented",z13
+veslv,"vector element shift left reg","not implemented",z13
+vone,"vector set to ones","not implemented",z13
+vsrl,"vector shift right logical","not implemented",z13
+vcdg,"vector fp convert from fixed 64 bit","not implemented",z13
+vmlhw,"vector multiply low halfword","not implemented",z13
+vscbib,"vector subtract compute borrow indication byte","not implemented",z13
+vrepib,"vector replicate immediate byte","not implemented",z13
+vpk,"vector pack","not implemented",z13
+vmhh,"vector multiply high halfword","not implemented",z13
+vfaezhs,"vector find any element equal","not implemented",z13
+vaf,"vector add word","not implemented",z13
+vmalh,"vector multiply and add logical high","not implemented",z13
+vgmg,"vector generate mask double word","not implemented",z13
+vstrczh,"vector string range compare halfword","not implemented",z13
+vag,"vector add double word","not implemented",z13
+vllezf,"vector load logical word element and zero","not implemented",z13
+vistrbs,"vector isolate string byte","not implemented",z13
+vstm,"vector store multiple","not implemented",z13
+vgfmh,"vector galois field multiply sum halfword","not implemented",z13
+verllvf,"vector element rotate left logical reg word","not implemented",z13
+vsra,"vector shift right arithmetic","not implemented",z13
+vslb,"vector shift left by byte","not implemented",z13
+vesravf,"vector element shift right arithmetic reg word","not implemented",z13
+vfcedbs,"vector fp compare equal","not implemented",z13
+vceqbs,"vector compare equal byte","not implemented",z13
+vsbcbi,"vector subtract with borrow compute borrow indication","not implemented",z13
+vmle,"vector multiply logical even","not implemented",z13
+vfaezfs,"vector find any element equal","not implemented",z13
+vsumg,"vector sum across doubleword","not implemented",z13
+vfaeb,"vector find any element equal byte","not implemented",z13
+vleih,"vector load halfword element immediate","not implemented",z13
+vmlob,"vector multiply logical odd byte","not implemented",z13
+vllezh,"vector load logical halfword element and zero","not implemented",z13
+vmalo,"vector multiply and add logical odd","not implemented",z13
+vclzh,"vector count leading zeros halfword","not implemented",z13
+vesravh,"vector element shift right arithmetic reg halfword","not implemented",z13
+vceqfs,"vector compare equal word","not implemented",z13
+vlp,"vector load positive","not implemented",z13
+wfmsdb,"vector fp multiply and subtract","not implemented",z13
+vstrcbs,"vector string range compare byte","not implemented",z13
+vaccg,"vector add compute carry doubleword","not implemented",z13
+wfsdb,"vector fp subtract","not implemented",z13
+vfee,"vector find element equal","not implemented",z13
+vmxh,"vector maximum halfword","not implemented",z13
+vtm,"vector test under mask","not implemented",z13
+vctzf,"vector count trailing zeros word","not implemented",z13
+vfms,"vector fp multiply and subtract","not implemented",z13
+vavgg,"vector average double word","not implemented",z13
+vistr,"vector isolate string","not implemented",z13
+vesrlvb,"vector element shift right logical reg byte","not implemented",z13
+vesrl,"vector element shift right logical mem","not implemented",z13
+vmah,"vector multiply and add high","not implemented",z13
+vesrlvh,"vector element shift right logical reg halfword","not implemented",z13
+vesrah,"vector element shift right arithmetic mem halfword","not implemented",z13
+vrepig,"vector replicate immediate double word","not implemented",z13
+wfddb,"vector fp divide","not implemented",z13
+vmhf,"vector multiply high word","not implemented",z13
+vupllf,"vector unpack logical low word","not implemented",z13
+veslf,"vector element shift left mem word","not implemented",z13
+wflpdb,"vector fp perform sign operation","not implemented",z13
+vscbi,"vector subtract compute borrow indication","not implemented",z13
+vmnlb,"vector minimum logical byte","not implemented",z13
+veslh,"vector element shift left mem halfword","not implemented",z13
+vfaebs,"vector find any element equal","not implemented",z13
+vleb,"vector load byte element","not implemented",z13
+vfaezb,"vector find any element equal","not implemented",z13
+vlbb,"vector load to block boundary","not implemented",z13
+vflcdb,"vector fp perform sign operation","not implemented",z13
+vmlo,"vector multiply logical odd","not implemented",z13
+vlgvf,"vector load gr from vr word element","not implemented",z13
+vavgf,"vector average word","not implemented",z13
+veslvh,"vector element shift left reg halfword","not implemented",z13
+vacch,"vector add compute carry halfword","not implemented",z13
+vsumgh,"vector sum across doubleword - halfword","not implemented",z13
+vmaeh,"vector multiply and add even halfword","not implemented",z13
+vmnlh,"vector minimum logical halfword","not implemented",z13
+vstl,"vector store with length","not implemented",z13
+wfmadb,"vector fp multiply and add","not implemented",z13
+vme,"vector multiply even","not implemented",z13
+wfmdb,"vector fp multiply","not implemented",z13
+wflcdb,"vector fp perform sign operation","not implemented",z13
+vreph,"vector replicate halfword","not implemented",z13
+vclgd,"vector fp convert to logical 64 bit","not implemented",z13
+vpkls,"vector pack logical saturate","not implemented",z13
+vsf,"vector subtract word","not implemented",z13
+vflpdb,"vector fp perform sign operation","not implemented",z13
+vesrlv,"vector element shift right logical reg","not implemented",z13
+vpklsfs,"vector pack logical saturate word","not implemented",z13
+vcdgb,"vector fp convert from fixed 64 bit","not implemented",z13
+verll,"vector element rotate left logical mem","not implemented",z13
+vfeezf,"vector find element equal word","not implemented",z13
+wclgdb,"vector fp convert to logical 64 bit","not implemented",z13
+vgfma,"vector galois field multiply sum and accumulate","not implemented",z13
+vmob,"vector multiply odd byte","not implemented",z13
+vfeneb,"vector find element not equal byte","not implemented",z13
+vfene,"vector find element not equal","not implemented",z13
+vfenezfs,"vector find element not equal word","not implemented",z13
+vmal,"vector multiply and add low","not implemented",z13
+vfchdb,"vector fp compare high","not implemented",z13
+vfeezb,"vector find element equal byte","not implemented",z13
+vfae,"vector find any element equal","not implemented",z13
+vfchdbs,"vector fp compare high","not implemented",z13
+vsceg,"vector scatter element 8 byte","not implemented",z13
+vfeezfs,"vector find element equal word","not implemented",z13
+vsumgf,"vector sum across doubleword - word","not implemented",z13
+vmnb,"vector minimum byte","not implemented",z13
+vlef,"vector load word element","not implemented",z13
+vceqgs,"vector compare equal double word","not implemented",z13
+vech,"vector element compare half word","not implemented",z13
+vctz,"vector count trailing zeros","not implemented",z13
+vmloh,"vector multiply logical odd halfword","not implemented",z13
+vaccc,"vector add with carry compute carry","not implemented",z13
+vmale,"vector multiply and add logical even","not implemented",z13
+vsteh,"vector store halfword element","not implemented",z13
+vceq,"vector compare equal","not implemented",z13
+vfchedbs,"vector fp compare high or equal","not implemented",z13
+vesl,"vector element shift left mem","not implemented",z13
+vesrav,"vector element shift right arithmetic reg","not implemented",z13
+vfma,"vector fp multiply and add","not implemented",z13
+vmnlg,"vector minimum logical doubleword","not implemented",z13
+vclz,"vector count leading zeros","not implemented",z13
+vmrlf,"vector merge low word","not implemented",z13
+vistrh,"vector isolate string halfword","not implemented",z13
+vmxlb,"vector maximum logical byte","not implemented",z13
+vfs,"vector fp subtract","not implemented",z13
+vfm,"vector fp multiply","not implemented",z13
+vll,"vector load with length","not implemented",z13
+vleig,"vector load double word element immediate","not implemented",z13
+vfaezbs,"vector find any element equal","not implemented",z13
+veslvg,"vector element shift left reg doubleword","not implemented",z13
+locfh,"load high on condition from memory","not implemented",z13
+vfeeb,"vector find element equal byte","not implemented",z13
+vsumq,"vector sum across quadword","not implemented",z13
+vmleb,"vector multiply logical even byte","not implemented",z13
+vesrag,"vector element shift right arithmetic mem doubleword","not implemented",z13
+vceqh,"vector compare equal half word","not implemented",z13
+vmalf,"vector multiply and add low word","not implemented",z13
+vstrchs,"vector string range compare halfword","not implemented",z13
+vcgdb,"vector fp convert to fixed 64 bit","not implemented",z13
+vsq,"vector subtract quadword","not implemented",z13
+vnot,"vector not","not implemented",z13
+vfch,"vector fp compare high","not implemented",z13
+lochi,"load halfword immediate on condition into 32 bit gpr","not implemented",z13
+verllvh,"vector element rotate left logical reg halfword","not implemented",z13
+cpdt,"convert from long dfp to packed","not implemented",z13
+vrepb,"vector replicate byte","not implemented",z13
+ppno,"perform pseudorandom number operation","not implemented",z13
+vfeef,"vector find element equal word","not implemented",z13
+vac,"vector add with carry","not implemented",z13
+verimf,"vector element rotate and insert under mask word","not implemented",z13
+vfi,"vector load fp integer","not implemented",z13
+vistrfs,"vector isolate string word","not implemented",z13
+vecf,"vector element compare word","not implemented",z13
+vfeezbs,"vector find element equal byte","not implemented",z13
+wflndb,"vector fp perform sign operation","not implemented",z13
+vscbif,"vector subtract compute borrow indication word","not implemented",z13
+vchhs,"vector compare high half word","not implemented",z13
+vmlb,"vector multiply low byte","not implemented",z13
+veslvf,"vector element shift left reg word","not implemented",z13
+vfaefs,"vector find any element equal","not implemented",z13
+vlrep,"vector load and replicate","not implemented",z13
+vaccf,"vector add compute carry word","not implemented",z13
+vpksf,"vector pack saturate word","not implemented",z13
+vavglf,"vector average logical word","not implemented",z13
+vmef,"vector multiply even word","not implemented",z13
+vuplhh,"vector unpack logical high halfword","not implemented",z13
+vmxl,"vector maximum logical","not implemented",z13
+vgfmah,"vector galois field multiply sum and accumulate halfword","not implemented",z13
+vmalhf,"vector multiply and add logical high word","not implemented",z13
+vsh,"vector subtract halfword","not implemented",z13
+vuplb,"vector unpack low byte","not implemented",z13
+vsegf,"vector sign extend word to double word","not implemented",z13
+vmxlf,"vector maximum logical word","not implemented",z13
+wcdlgb,"vector fp convert from logical 64 bit","not implemented",z13
+vstrczb,"vector string range compare byte","not implemented",z13
+vsldb,"vector shift left double by byte","not implemented",z13
+vesrlh,"vector element shift right logical mem halfword","not implemented",z13
+cdpt,"convert from packed to long dfp","not implemented",z13
+vlcb,"vector load complement byte","not implemented",z13
+wfpsodb,"vector fp perform sign operation","not implemented",z13
+vsum,"vector sum across word","not implemented",z13
+vfeehs,"vector find element equal halfword","not implemented",z13
+vml,"vector multiply low","not implemented",z13
+vuphh,"vector unpack high halfword","not implemented",z13
+vavglb,"vector average logical byte","not implemented",z13
+vmlf,"vector multiply low word","not implemented",z13
+wledb,"vector fp load rounded","not implemented",z13
+vstrcfs,"vector string range compare word","not implemented",z13
+wcgdb,"vector fp convert to fixed 64 bit","not implemented",z13
+vlph,"vector load positive halfword","not implemented",z13
+vfenezf,"vector find element not equal word","not implemented",z13
+vseg,"vector sign extend to double word","not implemented",z13
+vcksm,"vector checksum","not implemented",z13
+vsrlb,"vector shift right logical by byte","not implemented",z13
+verimg,"vector element rotate and insert under mask doubleword","not implemented",z13
+vesravg,"vector element shift right arithmetic reg doubleword","not implemented",z13
+vmlhh,"vector multiply logical high halfword","not implemented",z13
+vfaezf,"vector find any element equal","not implemented",z13
+vfenehs,"vector find element not equal halfword","not implemented",z13
+vlr,"vector register load","not implemented",z13
+vgbm,"vector generate byte mask","not implemented",z13
+vmnlf,"vector minimum logical word","not implemented",z13
+vlm,"vector load multiple","not implemented",z13
+vmrlb,"vector merge low byte","not implemented",z13
+vavglh,"vector average logical half word","not implemented",z13
+wfkdb,"vector fp compare and signal scalar","not implemented",z13
+veslb,"vector element shift left mem byte","not implemented",z13
+wfchedb,"vector fp compare high or equal","not implemented",z13
+vllezg,"vector load logical double word element and zero","not implemented",z13
+vmaob,"vector multiply and add odd byte","not implemented",z13
+vmrhf,"vector merge high word","not implemented",z13
+vchg,"vector compare high double word","not implemented",z13
+locfhr,"load high on condition from gpr","not implemented",z13
+vlpg,"vector load positive doubleword","not implemented",z13
+vcdlgb,"vector fp convert from logical 64 bit","not implemented",z13
+vstrczhs,"vector string range compare halfword","not implemented",z13
+vecb,"vector element compare byte","not implemented",z13
+vmxlg,"vector maximum logical doubleword","not implemented",z13
+vfpso,"vector fp perform sign operation","not implemented",z13
+verim,"vector element rotate and insert under mask","not implemented",z13
+vsumqf,"vector sum across quadword - word elements","not implemented",z13
+vfeefs,"vector find element equal word","not implemented",z13
+vfche,"vector fp compare high or equal","not implemented",z13
+vistrhs,"vector isolate string halfword","not implemented",z13
+vsl,"vector shift left","not implemented",z13
+vfenezhs,"vector find element not equal halfword","not implemented",z13
+vsg,"vector subtract doubleword","not implemented",z13
+vclzf,"vector count leading zeros word","not implemented",z13
+wfcdb,"vector fp compare scalar","not implemented",z13
+vmaoh,"vector multiply and add odd halfword","not implemented",z13
+vchgs,"vector compare high double word","not implemented",z13
+vchlf,"vector compare high logical word","not implemented",z13
+va,"vector add","not implemented",z13
+vmrlg,"vector merge low double word","not implemented",z13
+vlcg,"vector load complement doubleword","not implemented",z13
+vceqf,"vector compare equal word","not implemented",z13
+vacq,"vector add with carry quadword","not implemented",z13
+vmaof,"vector multiply and add odd word","not implemented",z13
+vfadb,"vector fp add","not implemented",z13
+vmlef,"vector multiply logical even word","not implemented",z13
+wfc,"vector fp compare scalar","not implemented",z13
+vmx,"vector maximum","not implemented",z13
+vmlh,"vector multiply logical high","not implemented",z13
+vmeb,"vector multiply even byte","not implemented",z13
+vfddb,"vector fp divide","not implemented",z13
+vpkshs,"vector pack saturate halfword","not implemented",z13
+vpkf,"vector pack word","not implemented",z13
+vlrepg,"vector load and replicate double word elements","not implemented",z13
+vmaef,"vector multiply and add even word","not implemented",z13
+vfeneh,"vector find element not equal halfword","not implemented",z13
+vgfmaf,"vector galois field multiply sum and accumulate word","not implemented",z13
+vctzg,"vector count trailing zeros doubleword","not implemented",z13
+lzrg,"load and zero rightmost byte 64->64","not implemented",z13
+vmof,"vector multiply odd word","not implemented",z13
+vfsqdb,"vector fp square root","not implemented",z13
+vlgvg,"vector load gr from vr double word element","not implemented",z13
+verllf,"vector element rotate left logical mem word","not implemented",z13
+verllg,"vector element rotate left logical mem doubleword","not implemented",z13
+vrepf,"vector replicate word","not implemented",z13
+vfeezhs,"vector find element equal halfword","not implemented",z13
+wfchdbs,"vector fp compare high","not implemented",z13
+lochhi,"load halfword high immediate on condition","not implemented",z13
+vmalhw,"vector multiply and add low halfword","not implemented",z13
+vmlhb,"vector multiply logical high byte","not implemented",z13
+vfeeh,"vector find element equal halfword","not implemented",z13
+vgm,"vector generate mask","not implemented",z13
+vgfmab,"vector galois field multiply sum and accumulate byte","not implemented",z13
+vmrhg,"vector merge high double word","not implemented",z13
+veclg,"vector element compare logical double word","not implemented",z13
+vl,"vector memory load","not implemented",z13
+vctzh,"vector count trailing zeros halfword","not implemented",z13
+vuplhf,"vector unpack logical high word","not implemented",z13
+verllvg,"vector element rotate left logical reg doubleword","not implemented",z13
+vupl,"vector unpack low","not implemented",z13
+vlgvb,"vector load gr from vr byte element","not implemented",z13
+vab,"vector add byte","not implemented",z13
+vch,"vector compare high","not implemented",z13
+veclf,"vector element compare logical word","not implemented",z13
+vgef,"vector gather element 4 byte elements","not implemented",z13
+vscbiq,"vector subtract compute borrow indication quadword","not implemented",z13
+cdgtr,"convert from fixed long dfp","not implemented",z13
+vesrab,"vector element shift right arithmetic mem byte","not implemented",z13
+vfsq,"vector fp square root","not implemented",z13
+vscef,"vector scatter element 4 byte","not implemented",z13
+vpkh,"vector pack halfword","not implemented",z13
+vfa,"vector fp add","not implemented",z13
+vo,"vector or","not implemented",z13
+verllb,"vector element rotate left logical mem byte","not implemented",z13
+stocfh,"store high on condition","not implemented",z13
+vchlbs,"vector compare high logical byte","not implemented",z13
+vuphf,"vector unpack high word","not implemented",z13
+vacc,"vector add compute carry","not implemented",z13
+vistrf,"vector isolate string word","not implemented",z13
+vceqhs,"vector compare equal half word","not implemented",z13
+vfidb,"vector load fp integer","not implemented",z13
+vupllh,"vector unpack logical low halfword","not implemented",z13
+vfce,"vector fp compare equal","not implemented",z13
+vs,"vector subtract","not implemented",z13
+vfeebs,"vector find element equal byte","not implemented",z13
+vlvgg,"vector load VR double word element from GR","not implemented",z13
Modified: trunk/none/tests/s390x/Makefile.am
==============================================================================
--- trunk/none/tests/s390x/Makefile.am (original)
+++ trunk/none/tests/s390x/Makefile.am Fri Oct 7 08:09:40 2016
@@ -12,6 +12,7 @@
rounding-1 rounding-2 rounding-3 rounding-4 rounding-5 bfp-1 \
bfp-2 bfp-3 bfp-4 srnm srnmb comp-1 comp-2 exrl tmll tm stmg \
ex clst mvc test_fork test_sig rounding-6 rxsbg popcnt \
+ high-word \
spechelper-alr spechelper-algr \
spechelper-slr spechelper-slgr \
spechelper-cr spechelper-clr \
Modified: trunk/none/tests/s390x/bfp-2.c
==============================================================================
--- trunk/none/tests/s390x/bfp-2.c (original)
+++ trunk/none/tests/s390x/bfp-2.c Fri Oct 7 08:09:40 2016
@@ -71,6 +71,26 @@
printf("lcdbr %f -> %f\n", in, out);
}
+void lder(double prev, float in)
+{
+ unsigned long out;
+
+ __asm__ volatile("lder %[prev],%[in]\n\t"
+ "std %[prev],%[out]" :
+ [out]"=R"(out) : [prev]"f"(prev), [in]"f"(in));
+ printf("lder %f -> %lx\n", in, out);
+}
+
+void lde(double prev, float in)
+{
+ unsigned long out;
+
+ __asm__ volatile("lde %[prev],%[in]\n\t"
+ "std %[prev],%[out]" :
+ [out]"=R"(out) : [prev]"f"(prev), [in]"R"(in));
+ printf("lde %f -> %lx\n", in, out);
+}
+
int main(void)
{
// square root
@@ -98,5 +118,11 @@
lcdbr(-17.5); // 8 byte values
lcdbr(234.5); // 8 byte values
+ // load lengthened
+ lder(0.2, 321.5f);
+ lder(0.9, -8388607.f);
+ lde(0.2, -321.5f);
+ lde(0.9, 8388607.f);
+
return 0;
}
Modified: trunk/none/tests/s390x/bfp-2.stdout.exp
==============================================================================
--- trunk/none/tests/s390x/bfp-2.stdout.exp (original)
+++ trunk/none/tests/s390x/bfp-2.stdout.exp Fri Oct 7 08:09:40 2016
@@ -12,3 +12,7 @@
lcebr 123.500000 -> -123.500000
lcdbr -17.500000 -> 17.500000
lcdbr 234.500000 -> -234.500000
+lder 321.500000 -> 43a0c00000000000
+lder -8388607.000000 -> cafffffe00000000
+lde -321.500000 -> c3a0c00000000000
+lde 8388607.000000 -> 4afffffe00000000
Added: trunk/none/tests/s390x/high-word.c
==============================================================================
--- trunk/none/tests/s390x/high-word.c (added)
+++ trunk/none/tests/s390x/high-word.c Fri Oct 7 08:09:40 2016
@@ -0,0 +1,84 @@
+#include <stdio.h>
+#include <stdint.h>
+#include "opcodes.h"
+
+#define BRASLCLOBBER "0","1","2","3","4","5","14", \
+ "f0","f1","f2","f3","f4","f5","f6","f7","memory","cc"
+
+static void inner_iter() { putchar('.'); }
+static void outer_iter() { putchar('+'); }
+
+static void
+check_brcth(int m, int n)
+{
+ unsigned long cnt = ((unsigned long) m << 32) | n;
+
+ printf("brcth %d x %d (cnt=0x%lx): ", m, n, cnt);
+ fflush(stdout);
+ asm volatile("1: lr %[cnt],%[n]\n\t"
+ "2: brasl 14,inner_iter\n\t"
+ "brct %[cnt],2b\n\t"
+ "brasl 14,outer_iter\n\t"
+ ".insn ril,0xcc0600000000,%[cnt],1b\n\t" // BRCTH
+ : [cnt]"+r" (cnt)
+ : [n]"r" (n)
+ : BRASLCLOBBER);
+ printf(" (cnt=0x%lx)\n", cnt);
+}
+
+#define DO_RISBXG(insn, _r1, _r2, i3, i4, i5) \
+ ({ \
+ register unsigned long r1 asm ("1") = _r1; \
+ register unsigned long r2 asm ("2") = _r2; \
+ asm volatile(insn(1,2, i3, i4, i5) \
+ : "+d" (r1) \
+ : "d" (r1), "d" (r2)); \
+ printf(#insn " r1(==%16.16lx),r2(==%16.16lx),0x" #i3 ",0x" #i4 \
+ ",0x" #i5 " = %16.16lx\n", _r1, _r2, r1); \
+ })
+
+/* Some "random" 64-bit numbers. */
+
+#define VAL_A 0x3a41e0a2afde1559
+#define VAL_B 0x765487c11cd04ac4
+#define VAL_C 0xb9cd1bdd399bef32
+#define VAL_D 0xf8efadb884334ddd
+
+static void
+check_risbxg(void)
+{
+ /* Full copy low -> low */
+ DO_RISBXG(RISBLG, VAL_A, VAL_B, 00, 1f, 00);
+ DO_RISBXG(RISBLG, VAL_B, VAL_A, 00, 9f, 00);
+ /* Full copy high -> low */
+ DO_RISBXG(RISBLG, VAL_B, VAL_A, 00, 1f, 20);
+ DO_RISBXG(RISBLG, VAL_A, VAL_B, 00, 9f, 20);
+ /* Full copy high -> high */
+ DO_RISBXG(RISBHG, VAL_C, VAL_D, 00, 1f, 00);
+ DO_RISBXG(RISBHG, VAL_D, VAL_C, 00, 9f, 00);
+ /* Full copy low -> high */
+ DO_RISBXG(RISBHG, VAL_D, VAL_C, 00, 1f, 20);
+ DO_RISBXG(RISBHG, VAL_C, VAL_D, 00, 9f, 20);
+ /* Middle copy */
+ DO_RISBXG(RISBLG, VAL_C, VAL_A, 0b, 13, 05);
+ DO_RISBXG(RISBLG, VAL_C, VAL_A, 0b, 93, 05);
+ DO_RISBXG(RISBHG, VAL_A, VAL_C, 03, 0c, 25);
+ DO_RISBXG(RISBHG, VAL_A, VAL_C, 03, 8c, 25);
+ /* "Outer" copy (start > end) */
+ DO_RISBXG(RISBLG, VAL_B, VAL_D, 1d, 07, 0c);
+ DO_RISBXG(RISBLG, VAL_B, VAL_D, 1d, 87, 0c);
+ DO_RISBXG(RISBHG, VAL_D, VAL_B, 0c, 03, 25);
+ DO_RISBXG(RISBHG, VAL_D, VAL_B, 0c, 83, 25);
+}
+
+/* Test high-word facility instructions. */
+
+int main()
+{
+ check_brcth(5, 3);
+ check_brcth(1, 30);
+ check_brcth(16, 1);
+
+ check_risbxg();
+ return 0;
+}
Modified: trunk/none/tests/s390x/mvc.c
==============================================================================
--- trunk/none/tests/s390x/mvc.c (original)
+++ trunk/none/tests/s390x/mvc.c Fri Oct 7 08:09:40 2016
@@ -57,6 +57,13 @@
asm volatile( "mvc 0(5,%0),10(%1)\n"
::"a" (buf),"a" (buf): "memory");
printf("after: buf = |%s|\n", buf);
-
+ printf("\n");
+
+ /* Move inverse (mvcin) */
+ printf("------- Move inverse 17 bytes from BUFFER to TARGET\n");
+ printf("before: target = |%s|\n", target);
+ asm volatile( "mvcin 0(17,%0),0(%1)\n"
+ ::"a" (target),"a" (buffer + 16): "memory");
+ printf("after: target = |%s|\n", target);
return 0;
}
Modified: trunk/none/tests/s390x/mvc.stdout.exp
==============================================================================
--- trunk/none/tests/s390x/mvc.stdout.exp (original)
+++ trunk/none/tests/s390x/mvc.stdout.exp Fri Oct 7 08:09:40 2016
@@ -15,3 +15,7 @@
------- Non-destructive overlap buf[0:4] = buf[10:14]
before: buf = |0123456789abcde|
after: buf = |abcde56789abcde|
+
+------- Move inverse 17 bytes from BUFFER to TARGET
+before: target = |-xxx-----------------|
+after: target = |Xfedcba9876543210----|
Modified: trunk/none/tests/s390x/opcodes.h
==============================================================================
--- trunk/none/tests/s390x/opcodes.h (original)
+++ trunk/none/tests/s390x/opcodes.h Fri Oct 7 08:09:40 2016
@@ -330,6 +330,8 @@
#define ROSBG(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,56)
#define RXSBG(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,57)
#define RISBGN(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,59)
+#define RISBHG(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,5d)
+#define RISBLG(r1,r2,i3,i4,i5) RIE_RRUUU(ec,r1,r2,i3,i4,i5,51)
#define SFPC(r1) RRE_R0(b384,r1)
#define SGRK(r3,r1,r2) RRF_R0RR2(b9e9,r3,0,r1,r2)
#define SHHHR(r3,r1,r2) RRF_R0RR2(b9c9,r3,0,r1,r2)
|
|
From: <sv...@va...> - 2016-10-07 07:07:20
|
Author: cborntra
Date: Fri Oct 7 08:07:10 2016
New Revision: 3259
Log:
s390: support RISBLG/RISBHG, MVCIN, LDE/LDER
patch by Andreas Arnez
Modified:
trunk/priv/guest_s390_toIR.c
Modified: trunk/priv/guest_s390_toIR.c
==============================================================================
--- trunk/priv/guest_s390_toIR.c (original)
+++ trunk/priv/guest_s390_toIR.c Fri Oct 7 08:07:10 2016
@@ -3831,6 +3831,16 @@
}
static const HChar *
+s390_irgen_BRCTH(UChar r1, UInt i2)
+{
+ put_gpr_w0(r1, binop(Iop_Sub32, get_gpr_w0(r1), mkU32(1)));
+ if_condition_goto(binop(Iop_CmpNE32, get_gpr_w0(r1), mkU32(0)),
+ guest_IA_curr_instr + ((ULong)(Long)(Short)i2 << 1));
+
+ return "brcth";
+}
+
+static const HChar *
s390_irgen_BRCTG(UChar r1, UShort i2)
{
put_gpr_dw0(r1, binop(Iop_Sub64, get_gpr_dw0(r1), mkU64(1)));
@@ -7633,6 +7643,65 @@
return s390_irgen_RISBGx(r1, r2, i3, i4, i5, False);
}
+static IRExpr *
+s390_irgen_RISBxG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5,
+ Bool high)
+{
+ UChar from;
+ UChar to;
+ UChar rot;
+ UChar z_bit;
+ UInt mask;
+ UInt maskc;
+ IRTemp op2 = newTemp(Ity_I32);
+
+ from = i3 & 31;
+ to = i4 & 31;
+ rot = i5 & 63;
+ z_bit = i4 & 128;
+ if (rot == 0) {
+ assign(op2, high ? get_gpr_w0(r2) : get_gpr_w1(r2));
+ } else if (rot == 32) {
+ assign(op2, high ? get_gpr_w1(r2) : get_gpr_w0(r2));
+ } else {
+ assign(op2,
+ unop(high ? Iop_64HIto32 : Iop_64to32,
+ binop(Iop_Or64,
+ binop(Iop_Shl64, get_gpr_dw0(r2), mkU8(rot)),
+ binop(Iop_Shr64, get_gpr_dw0(r2), mkU8(64 - rot)))));
+ }
+ if (from <= to) {
+ mask = ~0U;
+ mask = (mask >> from) & (mask << (31 - to));
+ maskc = ~mask;
+ } else {
+ maskc = ~0U;
+ maskc = (maskc >> (to + 1)) & (maskc << (32 - from));
+ mask = ~maskc;
+ }
+ if (z_bit) {
+ return binop(Iop_And32, mkexpr(op2), mkU32(mask));
+ }
+ return binop(Iop_Or32,
+ binop(Iop_And32, high ? get_gpr_w0(r1) : get_gpr_w1(r1),
+ mkU32(maskc)),
+ binop(Iop_And32, mkexpr(op2), mkU32(mask)));
+}
+
+static const HChar *
+s390_irgen_RISBHG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5)
+{
+ put_gpr_w0(r1, s390_irgen_RISBxG(r1, r2, i3, i4, i5, True));
+ return "risbhg";
+}
+
+static const HChar *
+s390_irgen_RISBLG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5)
+{
+ put_gpr_w1(r1, s390_irgen_RISBxG(r1, r2, i3, i4, i5, False));
+ return "risblg";
+}
+
static const HChar *
s390_irgen_SAR(UChar r1, UChar r2)
{
@@ -8770,6 +8839,15 @@
}
static const HChar *
+s390_irgen_LDER(UChar r1, UChar r2)
+{
+ put_fpr_dw0(r1, mkF64i(0x0));
+ put_fpr_w0(r1, get_fpr_w0(r2));
+
+ return "lder";
+}
+
+static const HChar *
s390_irgen_LXR(UChar r1, UChar r2)
{
put_fpr_dw0(r1, get_fpr_dw0(r2));
@@ -8795,6 +8873,15 @@
}
static const HChar *
+s390_irgen_LDE(UChar r1, IRTemp op2addr)
+{
+ put_fpr_dw0(r1, mkF64i(0x0));
+ put_fpr_w0(r1, load(Ity_F32, mkexpr(op2addr)));
+
+ return "lde";
+}
+
+static const HChar *
s390_irgen_LEY(UChar r1, IRTemp op2addr)
{
put_fpr_w0(r1, load(Ity_F32, mkexpr(op2addr)));
@@ -10911,6 +10998,22 @@
}
static void
+s390_irgen_MVCIN_EX(IRTemp length, IRTemp start1, IRTemp start2)
+{
+ IRTemp counter = newTemp(Ity_I64);
+
+ assign(counter, get_counter_dw0());
+
+ store(binop(Iop_Add64, mkexpr(start1), mkexpr(counter)),
+ load(Ity_I8, binop(Iop_Sub64, mkexpr(start2), mkexpr(counter))));
+
+ /* Check for end of field */
+ put_counter_dw0(binop(Iop_Add64, mkexpr(counter), mkU64(1)));
+ iterate_if(binop(Iop_CmpNE64, mkexpr(counter), mkexpr(length)));
+ put_counter_dw0(mkU64(0));
+}
+
+static void
s390_irgen_TR_EX(IRTemp length, IRTemp start1, IRTemp start2)
{
IRTemp op = newTemp(Ity_I8);
@@ -11043,6 +11146,11 @@
s390_irgen_EX_SS(r1, addr2, s390_irgen_TR_EX, 64);
return "ex@tr";
+ case 0xe800000000000000ULL:
+ /* special case MVCIN */
+ s390_irgen_EX_SS(r1, addr2, s390_irgen_MVCIN_EX, 64);
+ return "ex@mvcin";
+
default:
{
/* everything else will get a self checking prefix that also checks the
@@ -11487,6 +11595,17 @@
}
static const HChar *
+s390_irgen_MVCIN(UChar length, IRTemp start1, IRTemp start2)
+{
+ IRTemp len = newTemp(Ity_I64);
+
+ assign(len, mkU64(length));
+ s390_irgen_MVCIN_EX(len, start1, start2);
+
+ return "mvcin";
+}
+
+static const HChar *
s390_irgen_MVCL(UChar r1, UChar r2)
{
IRTemp addr1 = newTemp(Ity_I64);
@@ -14560,7 +14679,8 @@
ovl.fmt.RRF.r3, ovl.fmt.RRF.r2); goto ok;
case 0xb31f: s390_format_RRF_F0FF(s390_irgen_MSDBR, ovl.fmt.RRF.r1,
ovl.fmt.RRF.r3, ovl.fmt.RRF.r2); goto ok;
- case 0xb324: /* LDER */ goto unimplemented;
+ case 0xb324: s390_format_RRE_FF(s390_irgen_LDER, ovl.fmt.RRE.r1,
+ ovl.fmt.RRE.r2); goto ok;
case 0xb325: /* LXDR */ goto unimplemented;
case 0xb326: /* LXER */ goto unimplemented;
case 0xb32e: /* MAER */ goto unimplemented;
@@ -16046,7 +16166,13 @@
case 0xec0000000045ULL: s390_format_RIE_RRP(s390_irgen_BRXLG, ovl.fmt.RIE.r1,
ovl.fmt.RIE.r3, ovl.fmt.RIE.i2);
goto ok;
- case 0xec0000000051ULL: /* RISBLG */ goto unimplemented;
+ case 0xec0000000051ULL: s390_format_RIE_RRUUU(s390_irgen_RISBLG,
+ ovl.fmt.RIE_RRUUU.r1,
+ ovl.fmt.RIE_RRUUU.r2,
+ ovl.fmt.RIE_RRUUU.i3,
+ ovl.fmt.RIE_RRUUU.i4,
+ ovl.fmt.RIE_RRUUU.i5);
+ goto ok;
case 0xec0000000054ULL: s390_format_RIE_RRUUU(s390_irgen_RNSBG,
ovl.fmt.RIE_RRUUU.r1,
ovl.fmt.RIE_RRUUU.r2,
@@ -16082,7 +16208,13 @@
ovl.fmt.RIE_RRUUU.i4,
ovl.fmt.RIE_RRUUU.i5);
goto ok;
- case 0xec000000005dULL: /* RISBHG */ goto unimplemented;
+ case 0xec000000005dULL: s390_format_RIE_RRUUU(s390_irgen_RISBHG,
+ ovl.fmt.RIE_RRUUU.r1,
+ ovl.fmt.RIE_RRUUU.r2,
+ ovl.fmt.RIE_RRUUU.i3,
+ ovl.fmt.RIE_RRUUU.i4,
+ ovl.fmt.RIE_RRUUU.i5);
+ goto ok;
case 0xec0000000064ULL: s390_format_RIE_RRPU(s390_irgen_CGRJ,
ovl.fmt.RIE_RRPU.r1,
ovl.fmt.RIE_RRPU.r2,
@@ -16245,7 +16377,10 @@
ovl.fmt.RXF.r3, ovl.fmt.RXF.x2,
ovl.fmt.RXF.b2, ovl.fmt.RXF.d2,
ovl.fmt.RXF.r1); goto ok;
- case 0xed0000000024ULL: /* LDE */ goto unimplemented;
+ case 0xed0000000024ULL: s390_format_RXE_FRRD(s390_irgen_LDE,
+ ovl.fmt.RXE.r1, ovl.fmt.RXE.x2,
+ ovl.fmt.RXE.b2,
+ ovl.fmt.RXE.d2); goto ok;
case 0xed0000000025ULL: /* LXD */ goto unimplemented;
case 0xed0000000026ULL: /* LXE */ goto unimplemented;
case 0xed000000002eULL: /* MAE */ goto unimplemented;
@@ -16421,7 +16556,8 @@
case 0xc802ULL: /* CSST */ goto unimplemented;
case 0xc804ULL: /* LPD */ goto unimplemented;
case 0xc805ULL: /* LPDG */ goto unimplemented;
- case 0xcc06ULL: /* BRCTH */ goto unimplemented;
+ case 0xcc06ULL: s390_format_RIL_RP(s390_irgen_BRCTH, ovl.fmt.RIL.r1,
+ ovl.fmt.RIL.i2); goto ok;
case 0xcc08ULL: s390_format_RIL_RI(s390_irgen_AIH, ovl.fmt.RIL.r1,
ovl.fmt.RIL.i2); goto ok;
case 0xcc0aULL: s390_format_RIL_RI(s390_irgen_ALSIH, ovl.fmt.RIL.r1,
@@ -16471,7 +16607,9 @@
case 0xdfULL: /* EDMK */ goto unimplemented;
case 0xe1ULL: /* PKU */ goto unimplemented;
case 0xe2ULL: /* UNPKU */ goto unimplemented;
- case 0xe8ULL: /* MVCIN */ goto unimplemented;
+ case 0xe8ULL: s390_format_SS_L0RDRD(s390_irgen_MVCIN, ovl.fmt.SS.l,
+ ovl.fmt.SS.b1, ovl.fmt.SS.d1,
+ ovl.fmt.SS.b2, ovl.fmt.SS.d2); goto ok;
case 0xe9ULL: /* PKA */ goto unimplemented;
case 0xeaULL: /* UNPKA */ goto unimplemented;
case 0xeeULL: /* PLO */ goto unimplemented;
|
|
From: Julian S. <js...@ac...> - 2016-10-07 05:28:21
|
Philippe, thanks for looking at this more. I think this needs to be clarified with the original author of the feature, and I am not sure he (Ruurd) is on the mailing list. Cc-ing therefore. For reference, the tracking bug is https://bugs.kde.org/show_bug.cgi?id=367995 J On 06/10/16 21:59, Philippe Waroquiers wrote: > I am a little bit lost in the documentation and/or semantic > of the recently added meta mempool feature. > > First, valgrind.h tells: > ... When the VALGRIND_MEMPOOL_AUTO_FREE > is passed, a MEMPOOL_DELETE will auto-free all chunks (so not reported as > leaks) for allocators that assume that destroying a pool destroys all > objects in the pool. > ... > > But this operation MEMPOOL_DELETE does not exist. > This looks to be rather VALGRIND_MEMPOOL_FREE. > In the manual, the description is somewhat different. > > > Second thing confusing me: > The user manual tells for META mempool first describe the auto free flag: > ... > This indicates that items allocated from this memory pool are automatically > freed when VALGRIND_MEMPOOL_FREE is used on a block. > ... > > But of course, when calling VALGRIND_MEMPOOL_FREE, by definition, the addr > given as argument is supposed to be a chunk of the pool, and is released. > So, this flag is by itself useless, unless it is combined with > VALGRIND_MEMPOOL_METAPOOL. > Do I miss something ? > > Assuming I did not miss something, then we now have a new macro > VALGRIND_CREATE_META_MEMPOOL(pool, rzB, is_zeroed, flags) > which in its names indicates it is a meta pool. > So, it is unclear why we ask the user to specify VALGRIND_MEMPOOL_METAPOOL > and/or allows the user to specify VALGRIND_MEMPOOL_AUTO_FREE, > as this will be useless unless the pool is a real meta pool. > (checking the code, effectively, the only thing an AUTO_FREE pool does > is to release automatically the '2nd level smaller blocks' when a 'first level > pool bigger block' is released with VALGRIND_MEMPOOL_FREE > > > The second flag documented is also somewhat confusingly described: > ... > This indicates that memory that has been marked as being allocated with > VALGRIND_MALLOCLIKE_BLOCK is used by a custom allocator to pass out memory > to an application (again marked with VALGRIND_MALLOCLIKE_BLOCK). > ... > > I do not see anything in tests and/or code that would implement something > like a double level of VALGRIND_MALLOCLIKE_BLOCK. > As I understand, we have a first level of blocks which are described > with VALGRIND_MEMPOOL_ALLOC > Then, such first level blocks can be split and allocated > using VALGRIND_MALLOCLIKE_BLOCK. > > > I think it would be better to clarify the documentation and maybe > remove this (useless for the user) VALGRIND_MEMPOOL_METAPOOL : > The underlying (internal) client request might effectively be > the same (and so have an 'internal' flag VALGRIND_MEMPOOL_METAPOOL > but it looks to me that describing this flag to the user is just > confusing. > > Philippe > > > > ------------------------------------------------------------------------------ > Check out the vibrant tech community on one of the world's most > engaging tech sites, SlashDot.org! http://sdm.link/slashdot > _______________________________________________ > Valgrind-developers mailing list > Val...@li... > https://lists.sourceforge.net/lists/listinfo/valgrind-developers > |