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From: <sv...@va...> - 2016-10-12 18:58:46
|
Author: petarj
Date: Wed Oct 12 19:58:36 2016
New Revision: 16040
Log:
mips32: add the test cases for luxc1/suxc1 instructions
Add the tests cases (in none/tests/mips32/vfp.c) that expose the error
with luxc1/suxc1 that was fixed by VEX r3262.
Patch by Aleksandra Karadzic.
Added:
trunk/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-BE
trunk/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-LE
Modified:
trunk/none/tests/mips32/Makefile.am
trunk/none/tests/mips32/vfp.c
Modified: trunk/none/tests/mips32/Makefile.am
==============================================================================
--- trunk/none/tests/mips32/Makefile.am (original)
+++ trunk/none/tests/mips32/Makefile.am Wed Oct 12 19:58:36 2016
@@ -6,10 +6,13 @@
EXTRA_DIST = \
block_size.stdout.exp block_size.stderr.exp block_size.vgtest \
branches.stdout.exp branches.stderr.exp branches.vgtest \
+ bug320057-mips32.stdout.exp bug320057-mips32.stderr.exp \
+ bug320057-mips32.vgtest \
change_fp_mode.stdout.exp change_fp_mode.stdout.exp-fpu32 \
- change_fp_mode.stderr.exp change_fp_mode.vgtest \
+ change_fp_mode.stderr.exp change_fp_mode.vgtest \
FPUarithmetic.stdout.exp FPUarithmetic.stdout.exp-mips32 \
FPUarithmetic.stderr.exp FPUarithmetic.vgtest \
+ fpu_branches.stdout.exp fpu_branches.stderr.exp fpu_branches.vgtest \
LoadStore.stdout.exp LoadStore.stdout.exp-BE LoadStore.stderr.exp \
LoadStore.vgtest \
LoadStore1.stdout.exp LoadStore1.stdout.exp-LE LoadStore1.stderr.exp \
@@ -18,27 +21,25 @@
MIPS32int.stdout.exp-mips32-BE MIPS32int.stdout.exp-mips32r2-BE \
MIPS32int.stdout.exp-mips32-LE MIPS32int.stdout.exp-mips32r2-LE \
MIPS32int.stderr.exp MIPS32int.vgtest \
+ mips32_dsp.stdout.exp-LE mips32_dsp.stdout.exp-BE \
+ mips32_dsp.stderr.exp mips32_dsp.vgtest \
+ mips32_dspr2.stdout.exp mips32_dspr2.stderr.exp \
+ mips32_dspr2.vgtest \
MoveIns.stdout.exp MoveIns.stdout.exp-BE \
MoveIns.stdout.exp-mips32r2-BE MoveIns.stdout.exp-mips32r2-LE \
MoveIns.stderr.exp MoveIns.vgtest \
+ round_fpu64.stdout.exp round_fpu64.stdout.exp-fpu32 \
+ round_fpu64.stderr.exp round_fpu64.vgtest \
round.stdout.exp round.stderr.exp round.vgtest \
- vfp.stdout.exp-mips32-BE vfp.stdout.exp-mips32r2-BE \
- vfp.stdout.exp-mips32-LE vfp.stdout.exp-mips32r2-LE vfp.stderr.exp \
- vfp.vgtest \
SignalException.stderr.exp SignalException.vgtest \
- bug320057-mips32.stdout.exp bug320057-mips32.stderr.exp \
- bug320057-mips32.vgtest \
- mips32_dsp.stdout.exp-LE mips32_dsp.stdout.exp-BE \
- mips32_dsp.stderr.exp mips32_dsp.vgtest \
- mips32_dspr2.stdout.exp mips32_dspr2.stderr.exp \
- mips32_dspr2.vgtest \
- unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
- unaligned_load_store.stderr.exp unaligned_load_store.vgtest \
test_fcsr.stdout.exp test_fcsr.stderr.exp test_fcsr.vgtest \
test_math.stdout.exp test_math.stderr.exp test_math.vgtest \
- round_fpu64.stdout.exp round_fpu64.stdout.exp-fpu32 \
- round_fpu64.stderr.exp round_fpu64.vgtest \
- fpu_branches.stdout.exp fpu_branches.stderr.exp fpu_branches.vgtest
+ unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
+ unaligned_load_store.stderr.exp unaligned_load_store.vgtest \
+ vfp.stdout.exp-mips32-BE vfp.stdout.exp-mips32r2-BE \
+ vfp.stdout.exp-mips32-LE vfp.stdout.exp-mips32r2-LE vfp.stderr.exp \
+ vfp.stdout.exp-mips32r2-fpu_64-BE vfp.stdout.exp-mips32r2-fpu_64-LE \
+ vfp.vgtest
check_PROGRAMS = \
allexec \
Modified: trunk/none/tests/mips32/vfp.c
==============================================================================
--- trunk/none/tests/mips32/vfp.c (original)
+++ trunk/none/tests/mips32/vfp.c Wed Oct 12 19:58:36 2016
@@ -1,5 +1,6 @@
#if defined(__mips_hard_float)
-
+#include <setjmp.h>
+#include <signal.h>
#include <stdint.h>
#include <stdio.h>
@@ -15,6 +16,18 @@
0x3FBF9ADD, 0x3746F65F
};
+long long meml[] = {
+ 0x236457894095A266, 0x7777777766666666,
+ 0xBFF00000aaaaccde, 0x0004563217800000,
+ 0x3FF0556644770000, 0x0002255889900000,
+ 0x25254123698a2e2b, 0x21a2b3d6f62d2d2a,
+ 0xFFaabb22ccFFFFFF, 0x542698eeFFFFFFFF,
+ 0x41D2658041D26580, 0xB487E5C9B487E5C9,
+ 0x420774411aa26580, 0xaabbccddB750E388,
+ 0xffffeeee3E45798E, 0xccccccccE2308C3A,
+ 0x123abb983FBF9ADD, 0x002255443746F65F
+};
+
float fs_f[] = {
0, 456.2489562, 3, -1,
1384.6, -7.2945676, 1000000000, -5786.47,
@@ -118,6 +131,22 @@
instruction, (uint32_t)out, (uint32_t)(out >> 32)); \
}
+// luxc1 $f0, $a3($v0)
+#define TESTINSN6LOADlu(instruction, indexVal, fd, index, base) \
+{ \
+ uint64_t out; \
+ __asm__ volatile( \
+ "move $" #base ", %0\n\t" \
+ "li $" #index ", " #indexVal"\n\t" \
+ instruction "\n\t" \
+ "sdc1 $"#fd ", 0(%1)" \
+ : : "r" (meml), "r" (&out) \
+ : #base, #index, "$"#fd, "memory" \
+ ); \
+ printf("%s :: ft lo: 0x%x, ft hi: 0x%x\n", \
+ instruction, (uint32_t)out, (uint32_t)(out >> 32)); \
+}
+
// sdc1 $f0, 0($t0)
#define TESTINST1(offset) \
{ \
@@ -158,6 +187,28 @@
out, out1); \
}
+// SUXC1 $f0, $t2($t0)
+#define TESTINST1b(offset, unligned_offset) \
+{ \
+ unsigned int out; \
+ unsigned int out1; \
+ __asm__ volatile( \
+ "move $t0, %2\n\t" \
+ "move $t1, %3\n\t" \
+ "li $t2, "#unligned_offset"\n\t" \
+ "ldc1 $f0, "#offset"($t1)\n\t" \
+ "suxc1 $f0, $t2($t0) \n\t" \
+ "lw %0, "#offset"($t0)\n\t" \
+ "addi $t0, $t0, 4 \n\t" \
+ "lw %1, "#offset"($t0)\n\t" \
+ : "=r" (out), "=r" (out1) \
+ : "r" (mem1), "r" (fs_d) \
+ : "t2", "t1", "t0", "$f0", "memory" \
+ ); \
+ printf("suxc1 $f0, #t2($t0) :: out: 0x%x : out1: 0x%x\n", \
+ out, out1); \
+}
+
// swc1 $f0, 0($t0)
#define TESTINST2(offset) \
{ \
@@ -195,6 +246,19 @@
out); \
}
+#define TEST_FPU64 \
+ __asm__ __volatile__( \
+ "cvt.l.s $f0, $f0" "\n\t" \
+ : \
+ : \
+ : "$f0" \
+ );
+
+static void handler(int sig)
+{
+ exit(0);
+}
+
void ppMem(double *m, int len)
{
int i;
@@ -405,6 +469,66 @@
ppMemF(mem1f, 16);
#endif
+#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_fpr==64 || __mips_fpr==xx)
+ signal(SIGILL, handler);
+ /* Test fpu64 mode. */
+ TEST_FPU64;
+
+ printf("luxc1\n");
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 40, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 48, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 56, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 64, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 40, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 48, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 56, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 64, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 40, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 48, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 56, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 64, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 0, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 8, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 16, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 24, f0, a3, v0);
+ TESTINSN6LOADlu("luxc1 $f0, $a3($v0)", 32, f0, a3, v0);
+
+ printf("SUXC1\n");
+ TESTINST1b(0, 0);
+ TESTINST1b(0, 1);
+ TESTINST1b(8, 8);
+ TESTINST1b(8, 9);
+ TESTINST1b(16, 16);
+ TESTINST1b(16, 17);
+ TESTINST1b(24, 24);
+ TESTINST1b(24, 25);
+ TESTINST1b(32, 32);
+ TESTINST1b(32, 35);
+ TESTINST1b(40, 40);
+ TESTINST1b(40, 42);
+ TESTINST1b(48, 48);
+ TESTINST1b(48, 50);
+ TESTINST1b(56, 56);
+ TESTINST1b(56, 60);
+ TESTINST1b(64, 64);
+ TESTINST1b(64, 67);
+ ppMem(mem1, 16);
+#endif
return 0;
}
#else
Added: trunk/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-BE
==============================================================================
--- trunk/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-BE (added)
+++ trunk/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-BE Wed Oct 12 19:58:36 2016
@@ -0,0 +1,239 @@
+LDC1
+ldc1 $f0, 0($t1) :: ft 0x666666664095a266
+ldc1 $f0, 8($t1) :: ft 0x0bff00000
+ldc1 $f0, 16($t1) :: ft 0x03ff00000
+ldc1 $f0, 24($t1) :: ft 0x262d2d2a252a2e2b
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0xb487e5c941d26580
+ldc1 $f0, 48($t1) :: ft 0xb750e38842026580
+ldc1 $f0, 56($t1) :: ft 0xe2308c3a3e45798e
+ldc1 $f0, 64($t1) :: ft 0x3746f65f3fbf9add
+ldc1 $f0, 0($t1) :: ft 0x666666664095a266
+ldc1 $f0, 8($t1) :: ft 0x0bff00000
+ldc1 $f0, 16($t1) :: ft 0x03ff00000
+ldc1 $f0, 24($t1) :: ft 0x262d2d2a252a2e2b
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0xb487e5c941d26580
+ldc1 $f0, 48($t1) :: ft 0xb750e38842026580
+ldc1 $f0, 56($t1) :: ft 0xe2308c3a3e45798e
+ldc1 $f0, 0($t1) :: ft 0x666666664095a266
+ldc1 $f0, 8($t1) :: ft 0x0bff00000
+ldc1 $f0, 16($t1) :: ft 0x03ff00000
+ldc1 $f0, 24($t1) :: ft 0x262d2d2a252a2e2b
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0xb487e5c941d26580
+ldc1 $f0, 48($t1) :: ft 0xb750e38842026580
+ldc1 $f0, 56($t1) :: ft 0xe2308c3a3e45798e
+ldc1 $f0, 64($t1) :: ft 0x3746f65f3fbf9add
+ldc1 $f0, 0($t1) :: ft 0x666666664095a266
+LWC1
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+lwc1 $f0, 4($t1) :: ft 0x66666666
+lwc1 $f0, 8($t1) :: ft 0xbff00000
+lwc1 $f0, 12($t1) :: ft 0x0
+lwc1 $f0, 16($t1) :: ft 0x3ff00000
+lwc1 $f0, 20($t1) :: ft 0x0
+lwc1 $f0, 24($t1) :: ft 0x252a2e2b
+lwc1 $f0, 28($t1) :: ft 0x262d2d2a
+lwc1 $f0, 32($t1) :: ft 0xffffffff
+lwc1 $f0, 36($t1) :: ft 0xffffffff
+lwc1 $f0, 40($t1) :: ft 0x41d26580
+lwc1 $f0, 44($t1) :: ft 0xb487e5c9
+lwc1 $f0, 48($t1) :: ft 0x42026580
+lwc1 $f0, 52($t1) :: ft 0xb750e388
+lwc1 $f0, 56($t1) :: ft 0x3e45798e
+lwc1 $f0, 60($t1) :: ft 0xe2308c3a
+lwc1 $f0, 64($t1) :: ft 0x3fbf9add
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+lwc1 $f0, 8($t1) :: ft 0xbff00000
+lwc1 $f0, 16($t1) :: ft 0x3ff00000
+lwc1 $f0, 24($t1) :: ft 0x252a2e2b
+lwc1 $f0, 32($t1) :: ft 0xffffffff
+lwc1 $f0, 40($t1) :: ft 0x41d26580
+lwc1 $f0, 48($t1) :: ft 0x42026580
+lwc1 $f0, 56($t1) :: ft 0x3e45798e
+lwc1 $f0, 64($t1) :: ft 0x3fbf9add
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+LWXC1
+lwxc1 $f0, $a3($v0) :: ft 0x4095a266
+lwxc1 $f0, $a3($v0) :: ft 0x66666666
+lwxc1 $f0, $a3($v0) :: ft 0xbff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x3ff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+lwxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0x41d26580
+lwxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+lwxc1 $f0, $a3($v0) :: ft 0x42026580
+lwxc1 $f0, $a3($v0) :: ft 0xb750e388
+lwxc1 $f0, $a3($v0) :: ft 0x3e45798e
+lwxc1 $f0, $a3($v0) :: ft 0xe2308c3a
+lwxc1 $f0, $a3($v0) :: ft 0x3fbf9add
+lwxc1 $f0, $a3($v0) :: ft 0x4095a266
+lwxc1 $f0, $a3($v0) :: ft 0x66666666
+lwxc1 $f0, $a3($v0) :: ft 0xbff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x3ff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+lwxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0x41d26580
+lwxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+lwxc1 $f0, $a3($v0) :: ft 0x42026580
+lwxc1 $f0, $a3($v0) :: ft 0xb750e388
+lwxc1 $f0, $a3($v0) :: ft 0x3e45798e
+LDXC1
+ldxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x4095a266
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0xbff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0x3ff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x262d2d2a, ft hi: 0x252a2e2b
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft lo: 0xb487e5c9, ft hi: 0x41d26580
+ldxc1 $f0, $a3($v0) :: ft lo: 0xb750e388, ft hi: 0x42026580
+ldxc1 $f0, $a3($v0) :: ft lo: 0xe2308c3a, ft hi: 0x3e45798e
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3746f65f, ft hi: 0x3fbf9add
+ldxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x4095a266
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0xbff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0x3ff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x262d2d2a, ft hi: 0x252a2e2b
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft lo: 0xb487e5c9, ft hi: 0x41d26580
+ldxc1 $f0, $a3($v0) :: ft lo: 0xb750e388, ft hi: 0x42026580
+ldxc1 $f0, $a3($v0) :: ft lo: 0xe2308c3a, ft hi: 0x3e45798e
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3746f65f, ft hi: 0x3fbf9add
+ldxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x4095a266
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0xbff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0x3ff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x262d2d2a, ft hi: 0x252a2e2b
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft lo: 0xb487e5c9, ft hi: 0x41d26580
+ldxc1 $f0, $a3($v0) :: ft lo: 0xb750e388, ft hi: 0x42026580
+ldxc1 $f0, $a3($v0) :: ft lo: 0xe2308c3a, ft hi: 0x3e45798e
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3746f65f, ft hi: 0x3fbf9add
+ldxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x4095a266
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0xbff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x0, ft hi: 0x3ff00000
+ldxc1 $f0, $a3($v0) :: ft lo: 0x262d2d2a, ft hi: 0x252a2e2b
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+SDC1
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x407c83fb
+sdc1 $f0, 0($t0) :: out: 0x40080000
+sdc1 $f0, 0($t0) :: out: 0xbff00000
+sdc1 $f0, 0($t0) :: out: 0x4095a266
+sdc1 $f0, 0($t0) :: out: 0xc01d2da3
+sdc1 $f0, 0($t0) :: out: 0x41cdcd65
+sdc1 $f0, 0($t0) :: out: 0xc0b69a78
+sdc1 $f0, 0($t0) :: out: 0x409b6000
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
+SDXC1
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0x407c83fb : out1: 0xb97f122f
+sdc1 $f0, #t2($t0) :: out: 0x40080000 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0xbff00000 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0x4095a266 : out1: 0x66666666
+sdc1 $f0, #t2($t0) :: out: 0xc01d2da3 : out1: 0x2101d847
+sdc1 $f0, #t2($t0) :: out: 0x41cdcd65 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0xc0b69a78 : out1: 0x51eb851f
+sdc1 $f0, #t2($t0) :: out: 0x409b6000 : out1: 0x0
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
+SWC1
+swc1 $f0, 0($t0) :: out: 0x0
+swc1 $f0, 0($t0) :: out: 0x40400000
+swc1 $f0, 0($t0) :: out: 0x44ad1333
+swc1 $f0, 0($t0) :: out: 0x4e6e6b28
+swc1 $f0, 0($t0) :: out: 0x44db0000
+swc1 $f0, 0($t0) :: out: 0x322bcc77
+swc1 $f0, 0($t0) :: out: 0xc732da7a
+swc1 $f0, 0($t0) :: out: 0x42080079
+swc1 $f0, 0($t0) :: out: 0x49d5e008
+MEM1:
+0.000000, 0.000000, 3.000000, 0.000000
+1384.599976, 0.000000, 1000000000.000000, 0.000000
+1752.000000, 0.000000, 0.000000, 0.000000
+-45786.476562, 0.000000, 34.000462, 0.000000
+SWXC1
+swxc1 $f0, 0($t0) :: out: 0x0
+swxc1 $f0, 0($t0) :: out: 0x40400000
+swxc1 $f0, 0($t0) :: out: 0x44ad1333
+swxc1 $f0, 0($t0) :: out: 0x4e6e6b28
+swxc1 $f0, 0($t0) :: out: 0x44db0000
+swxc1 $f0, 0($t0) :: out: 0x322bcc77
+swxc1 $f0, 0($t0) :: out: 0xc732da7a
+swxc1 $f0, 0($t0) :: out: 0x42080079
+swxc1 $f0, 0($t0) :: out: 0x49d5e008
+MEM1:
+0.000000, 0.000000, 3.000000, 0.000000
+1384.599976, 0.000000, 1000000000.000000, 0.000000
+1752.000000, 0.000000, 0.000000, 0.000000
+-45786.476562, 0.000000, 34.000462, 0.000000
+luxc1
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+luxc1 $f0, $a3($v0) :: ft lo: 0x89900000, ft hi: 0x22558
+luxc1 $f0, $a3($v0) :: ft lo: 0x698a2e2b, ft hi: 0x25254123
+luxc1 $f0, $a3($v0) :: ft lo: 0xf62d2d2a, ft hi: 0x21a2b3d6
+luxc1 $f0, $a3($v0) :: ft lo: 0xccffffff, ft hi: 0xffaabb22
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+luxc1 $f0, $a3($v0) :: ft lo: 0x89900000, ft hi: 0x22558
+luxc1 $f0, $a3($v0) :: ft lo: 0x698a2e2b, ft hi: 0x25254123
+luxc1 $f0, $a3($v0) :: ft lo: 0xf62d2d2a, ft hi: 0x21a2b3d6
+luxc1 $f0, $a3($v0) :: ft lo: 0xccffffff, ft hi: 0xffaabb22
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+luxc1 $f0, $a3($v0) :: ft lo: 0x89900000, ft hi: 0x22558
+luxc1 $f0, $a3($v0) :: ft lo: 0x698a2e2b, ft hi: 0x25254123
+luxc1 $f0, $a3($v0) :: ft lo: 0xf62d2d2a, ft hi: 0x21a2b3d6
+luxc1 $f0, $a3($v0) :: ft lo: 0xccffffff, ft hi: 0xffaabb22
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+SUXC1
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0x407c83fb : out1: 0xb97f122f
+suxc1 $f0, #t2($t0) :: out: 0x407c83fb : out1: 0xb97f122f
+suxc1 $f0, #t2($t0) :: out: 0x40080000 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0x40080000 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0xbff00000 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0xbff00000 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0x4095a266 : out1: 0x66666666
+suxc1 $f0, #t2($t0) :: out: 0x4095a266 : out1: 0x66666666
+suxc1 $f0, #t2($t0) :: out: 0xc01d2da3 : out1: 0x2101d847
+suxc1 $f0, #t2($t0) :: out: 0xc01d2da3 : out1: 0x2101d847
+suxc1 $f0, #t2($t0) :: out: 0x41cdcd65 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0x41cdcd65 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0xc0b69a78 : out1: 0x51eb851f
+suxc1 $f0, #t2($t0) :: out: 0xc0b69a78 : out1: 0x51eb851f
+suxc1 $f0, #t2($t0) :: out: 0x409b6000 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0x409b6000 : out1: 0x0
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
\ No newline at end of file
Added: trunk/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-LE
==============================================================================
--- trunk/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-LE (added)
+++ trunk/none/tests/mips32/vfp.stdout.exp-mips32r2-fpu_64-LE Wed Oct 12 19:58:36 2016
@@ -0,0 +1,239 @@
+LDC1
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+ldc1 $f0, 8($t1) :: ft 0xbff000000
+ldc1 $f0, 16($t1) :: ft 0x3ff000000
+ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
+ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
+ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
+ldc1 $f0, 64($t1) :: ft 0x3fbf9add3746f65f
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+ldc1 $f0, 8($t1) :: ft 0xbff000000
+ldc1 $f0, 16($t1) :: ft 0x3ff000000
+ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
+ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
+ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+ldc1 $f0, 8($t1) :: ft 0xbff000000
+ldc1 $f0, 16($t1) :: ft 0x3ff000000
+ldc1 $f0, 24($t1) :: ft 0x252a2e2b262d2d2a
+ldc1 $f0, 32($t1) :: ft 0xffffffffffffffff
+ldc1 $f0, 40($t1) :: ft 0x41d26580b487e5c9
+ldc1 $f0, 48($t1) :: ft 0x42026580b750e388
+ldc1 $f0, 56($t1) :: ft 0x3e45798ee2308c3a
+ldc1 $f0, 64($t1) :: ft 0x3fbf9add3746f65f
+ldc1 $f0, 0($t1) :: ft 0x4095a26666666666
+LWC1
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+lwc1 $f0, 4($t1) :: ft 0x66666666
+lwc1 $f0, 8($t1) :: ft 0xbff00000
+lwc1 $f0, 12($t1) :: ft 0x0
+lwc1 $f0, 16($t1) :: ft 0x3ff00000
+lwc1 $f0, 20($t1) :: ft 0x0
+lwc1 $f0, 24($t1) :: ft 0x252a2e2b
+lwc1 $f0, 28($t1) :: ft 0x262d2d2a
+lwc1 $f0, 32($t1) :: ft 0xffffffff
+lwc1 $f0, 36($t1) :: ft 0xffffffff
+lwc1 $f0, 40($t1) :: ft 0x41d26580
+lwc1 $f0, 44($t1) :: ft 0xb487e5c9
+lwc1 $f0, 48($t1) :: ft 0x42026580
+lwc1 $f0, 52($t1) :: ft 0xb750e388
+lwc1 $f0, 56($t1) :: ft 0x3e45798e
+lwc1 $f0, 60($t1) :: ft 0xe2308c3a
+lwc1 $f0, 64($t1) :: ft 0x3fbf9add
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+lwc1 $f0, 8($t1) :: ft 0xbff00000
+lwc1 $f0, 16($t1) :: ft 0x3ff00000
+lwc1 $f0, 24($t1) :: ft 0x252a2e2b
+lwc1 $f0, 32($t1) :: ft 0xffffffff
+lwc1 $f0, 40($t1) :: ft 0x41d26580
+lwc1 $f0, 48($t1) :: ft 0x42026580
+lwc1 $f0, 56($t1) :: ft 0x3e45798e
+lwc1 $f0, 64($t1) :: ft 0x3fbf9add
+lwc1 $f0, 0($t1) :: ft 0x4095a266
+LWXC1
+lwxc1 $f0, $a3($v0) :: ft 0x4095a266
+lwxc1 $f0, $a3($v0) :: ft 0x66666666
+lwxc1 $f0, $a3($v0) :: ft 0xbff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x3ff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+lwxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0x41d26580
+lwxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+lwxc1 $f0, $a3($v0) :: ft 0x42026580
+lwxc1 $f0, $a3($v0) :: ft 0xb750e388
+lwxc1 $f0, $a3($v0) :: ft 0x3e45798e
+lwxc1 $f0, $a3($v0) :: ft 0xe2308c3a
+lwxc1 $f0, $a3($v0) :: ft 0x3fbf9add
+lwxc1 $f0, $a3($v0) :: ft 0x4095a266
+lwxc1 $f0, $a3($v0) :: ft 0x66666666
+lwxc1 $f0, $a3($v0) :: ft 0xbff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x3ff00000
+lwxc1 $f0, $a3($v0) :: ft 0x0
+lwxc1 $f0, $a3($v0) :: ft 0x252a2e2b
+lwxc1 $f0, $a3($v0) :: ft 0x262d2d2a
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0xffffffff
+lwxc1 $f0, $a3($v0) :: ft 0x41d26580
+lwxc1 $f0, $a3($v0) :: ft 0xb487e5c9
+lwxc1 $f0, $a3($v0) :: ft 0x42026580
+lwxc1 $f0, $a3($v0) :: ft 0xb750e388
+lwxc1 $f0, $a3($v0) :: ft 0x3e45798e
+LDXC1
+ldxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x66666666
+ldxc1 $f0, $a3($v0) :: ft lo: 0xbff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3ff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x252a2e2b, ft hi: 0x262d2d2a
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft lo: 0x41d26580, ft hi: 0xb487e5c9
+ldxc1 $f0, $a3($v0) :: ft lo: 0x42026580, ft hi: 0xb750e388
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3e45798e, ft hi: 0xe2308c3a
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3fbf9add, ft hi: 0x3746f65f
+ldxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x66666666
+ldxc1 $f0, $a3($v0) :: ft lo: 0xbff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3ff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x252a2e2b, ft hi: 0x262d2d2a
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft lo: 0x41d26580, ft hi: 0xb487e5c9
+ldxc1 $f0, $a3($v0) :: ft lo: 0x42026580, ft hi: 0xb750e388
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3e45798e, ft hi: 0xe2308c3a
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3fbf9add, ft hi: 0x3746f65f
+ldxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x66666666
+ldxc1 $f0, $a3($v0) :: ft lo: 0xbff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3ff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x252a2e2b, ft hi: 0x262d2d2a
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+ldxc1 $f0, $a3($v0) :: ft lo: 0x41d26580, ft hi: 0xb487e5c9
+ldxc1 $f0, $a3($v0) :: ft lo: 0x42026580, ft hi: 0xb750e388
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3e45798e, ft hi: 0xe2308c3a
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3fbf9add, ft hi: 0x3746f65f
+ldxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x66666666
+ldxc1 $f0, $a3($v0) :: ft lo: 0xbff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x3ff00000, ft hi: 0x0
+ldxc1 $f0, $a3($v0) :: ft lo: 0x252a2e2b, ft hi: 0x262d2d2a
+ldxc1 $f0, $a3($v0) :: ft lo: 0xffffffff, ft hi: 0xffffffff
+SDC1
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0xb97f122f
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x66666666
+sdc1 $f0, 0($t0) :: out: 0x2101d847
+sdc1 $f0, 0($t0) :: out: 0x0
+sdc1 $f0, 0($t0) :: out: 0x51eb851f
+sdc1 $f0, 0($t0) :: out: 0x0
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
+SDXC1
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x0
+sdc1 $f0, #t2($t0) :: out: 0xb97f122f : out1: 0x407c83fb
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x40080000
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0xbff00000
+sdc1 $f0, #t2($t0) :: out: 0x66666666 : out1: 0x4095a266
+sdc1 $f0, #t2($t0) :: out: 0x2101d847 : out1: 0xc01d2da3
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x41cdcd65
+sdc1 $f0, #t2($t0) :: out: 0x51eb851f : out1: 0xc0b69a78
+sdc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x409b6000
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
+SWC1
+swc1 $f0, 0($t0) :: out: 0x0
+swc1 $f0, 0($t0) :: out: 0x40400000
+swc1 $f0, 0($t0) :: out: 0x44ad1333
+swc1 $f0, 0($t0) :: out: 0x4e6e6b28
+swc1 $f0, 0($t0) :: out: 0x44db0000
+swc1 $f0, 0($t0) :: out: 0x322bcc77
+swc1 $f0, 0($t0) :: out: 0xc732da7a
+swc1 $f0, 0($t0) :: out: 0x42080079
+swc1 $f0, 0($t0) :: out: 0x49d5e008
+MEM1:
+0.000000, 0.000000, 3.000000, 0.000000
+1384.599976, 0.000000, 1000000000.000000, 0.000000
+1752.000000, 0.000000, 0.000000, 0.000000
+-45786.476562, 0.000000, 34.000462, 0.000000
+SWXC1
+swxc1 $f0, 0($t0) :: out: 0x0
+swxc1 $f0, 0($t0) :: out: 0x40400000
+swxc1 $f0, 0($t0) :: out: 0x44ad1333
+swxc1 $f0, 0($t0) :: out: 0x4e6e6b28
+swxc1 $f0, 0($t0) :: out: 0x44db0000
+swxc1 $f0, 0($t0) :: out: 0x322bcc77
+swxc1 $f0, 0($t0) :: out: 0xc732da7a
+swxc1 $f0, 0($t0) :: out: 0x42080079
+swxc1 $f0, 0($t0) :: out: 0x49d5e008
+MEM1:
+0.000000, 0.000000, 3.000000, 0.000000
+1384.599976, 0.000000, 1000000000.000000, 0.000000
+1752.000000, 0.000000, 0.000000, 0.000000
+-45786.476562, 0.000000, 34.000462, 0.000000
+luxc1
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+luxc1 $f0, $a3($v0) :: ft lo: 0x89900000, ft hi: 0x22558
+luxc1 $f0, $a3($v0) :: ft lo: 0x698a2e2b, ft hi: 0x25254123
+luxc1 $f0, $a3($v0) :: ft lo: 0xf62d2d2a, ft hi: 0x21a2b3d6
+luxc1 $f0, $a3($v0) :: ft lo: 0xccffffff, ft hi: 0xffaabb22
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+luxc1 $f0, $a3($v0) :: ft lo: 0x89900000, ft hi: 0x22558
+luxc1 $f0, $a3($v0) :: ft lo: 0x698a2e2b, ft hi: 0x25254123
+luxc1 $f0, $a3($v0) :: ft lo: 0xf62d2d2a, ft hi: 0x21a2b3d6
+luxc1 $f0, $a3($v0) :: ft lo: 0xccffffff, ft hi: 0xffaabb22
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+luxc1 $f0, $a3($v0) :: ft lo: 0x89900000, ft hi: 0x22558
+luxc1 $f0, $a3($v0) :: ft lo: 0x698a2e2b, ft hi: 0x25254123
+luxc1 $f0, $a3($v0) :: ft lo: 0xf62d2d2a, ft hi: 0x21a2b3d6
+luxc1 $f0, $a3($v0) :: ft lo: 0xccffffff, ft hi: 0xffaabb22
+luxc1 $f0, $a3($v0) :: ft lo: 0x4095a266, ft hi: 0x23645789
+luxc1 $f0, $a3($v0) :: ft lo: 0x66666666, ft hi: 0x77777777
+luxc1 $f0, $a3($v0) :: ft lo: 0xaaaaccde, ft hi: 0xbff00000
+luxc1 $f0, $a3($v0) :: ft lo: 0x17800000, ft hi: 0x45632
+luxc1 $f0, $a3($v0) :: ft lo: 0x44770000, ft hi: 0x3ff05566
+SUXC1
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x0
+suxc1 $f0, #t2($t0) :: out: 0xb97f122f : out1: 0x407c83fb
+suxc1 $f0, #t2($t0) :: out: 0xb97f122f : out1: 0x407c83fb
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x40080000
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x40080000
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0xbff00000
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0xbff00000
+suxc1 $f0, #t2($t0) :: out: 0x66666666 : out1: 0x4095a266
+suxc1 $f0, #t2($t0) :: out: 0x66666666 : out1: 0x4095a266
+suxc1 $f0, #t2($t0) :: out: 0x2101d847 : out1: 0xc01d2da3
+suxc1 $f0, #t2($t0) :: out: 0x2101d847 : out1: 0xc01d2da3
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x41cdcd65
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x41cdcd65
+suxc1 $f0, #t2($t0) :: out: 0x51eb851f : out1: 0xc0b69a78
+suxc1 $f0, #t2($t0) :: out: 0x51eb851f : out1: 0xc0b69a78
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x409b6000
+suxc1 $f0, #t2($t0) :: out: 0x0 : out1: 0x409b6000
+MEM1:
+0.000000, 456.248956, 3.000000, -1.000000
+1384.600000, -7.294568, 1000000000.000000, -5786.470000
+1752.000000, 0.000000, 0.000000, 0.000000
+0.000000, 0.000000, 0.000000, 0.000000
|
|
From: <sv...@va...> - 2016-10-12 15:25:52
|
Author: petarj
Date: Wed Oct 12 16:25:45 2016
New Revision: 3262
Log:
mips: fix incorrect implementation of luxc1/suxc1 instructions
Support correct execution of luxc1 and suxc1 instructions on MIPS32
and MIPS64 platforms with the respect for FPU mode.
Patch by Aleksandra Karadzic.
Modified:
trunk/priv/guest_mips_toIR.c
Modified: trunk/priv/guest_mips_toIR.c
==============================================================================
--- trunk/priv/guest_mips_toIR.c (original)
+++ trunk/priv/guest_mips_toIR.c Wed Oct 12 16:25:45 2016
@@ -13530,14 +13530,22 @@
}
case 0x5: /* Load Doubleword Indexed Unaligned to Floating Point - LUXC1;
- MIPS32r2 */
+ MIPS32r2 and MIPS64 */
DIP("luxc1 f%u, r%u(r%u)", fd, rt, rs);
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- assign(t0, binop(Iop_Add64, getIReg(rs), getIReg(rt)));
- assign(t1, binop(Iop_And64, mkexpr(t0),
- mkU64(0xfffffffffffffff8ULL)));
- putFReg(fd, load(Ity_F64, mkexpr(t1)));
+ if ((mode64 || VEX_MIPS_CPU_HAS_MIPS32R2(archinfo->hwcaps))
+ && fp_mode64) {
+ t0 = newTemp(ty);
+ t1 = newTemp(ty);
+ assign(t0, binop(mode64 ? Iop_Add64 : Iop_Add32,
+ getIReg(rs), getIReg(rt)));
+ assign(t1, binop(mode64 ? Iop_Add64 : Iop_And32,
+ mkexpr(t0),
+ mode64 ? mkU64(0xfffffffffffffff8ULL)
+ : mkU32(0xfffffff8ULL)));
+ putFReg(fd, load(Ity_F64, mkexpr(t1)));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
case 0x8: { /* Store Word Indexed from Floating Point - SWXC1 */
@@ -13563,11 +13571,20 @@
case 0xD: /* Store Doubleword Indexed Unaligned from Floating Point -
SUXC1; MIPS64 MIPS32r2 */
DIP("suxc1 f%u, r%u(r%u)", fd, rt, rs);
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I64);
- assign(t0, binop(Iop_Add64, getIReg(rs), getIReg(rt)));
- assign(t1, binop(Iop_And64, mkexpr(t0), mkU64(0xfffffffffffffff8ULL)));
- store(mkexpr(t1), getFReg(fs));
+ if ((mode64 || VEX_MIPS_CPU_HAS_MIPS32R2(archinfo->hwcaps))
+ && fp_mode64) {
+ t0 = newTemp(ty);
+ t1 = newTemp(ty);
+ assign(t0, binop(mode64 ? Iop_Add64 : Iop_Add32,
+ getIReg(rs), getIReg(rt)));
+ assign(t1, binop(mode64 ? Iop_Add64 : Iop_And32,
+ mkexpr(t0),
+ mode64 ? mkU64(0xfffffffffffffff8ULL)
+ : mkU32(0xfffffff8ULL)));
+ store(mkexpr(t1), getFReg(fs));
+ } else {
+ ILLEGAL_INSTRUCTON;
+ }
break;
case 0x0F: {
|
|
From: <sv...@va...> - 2016-10-12 15:13:34
|
Author: petarj
Date: Wed Oct 12 16:13:27 2016
New Revision: 16039
Log:
mips: allow Valgrind to be compiled for soft-float
Force "hardfloat" mode for inline assembly that uses FPU instructions,
but pop original mode at the end of the assembly. Unhandled FPU
instructions will be handled by the signal handler (env_unsup_insn).
Skip MIPS specific tests for FPU if the code gets compiled for soft-
float.
This should allow Valgrind to be compiled as a soft-float binary, but
that executable should be used for soft-float systems only.
Related VEX change - r3261.
Related issue - BZ#351282.
Patch by Aleksandar Rikalo.
Modified:
trunk/coregrind/m_machine.c
trunk/none/tests/mips32/FPUarithmetic.c
trunk/none/tests/mips32/FPUarithmetic.vgtest
trunk/none/tests/mips32/MoveIns.c
trunk/none/tests/mips32/MoveIns.vgtest
trunk/none/tests/mips32/change_fp_mode.c
trunk/none/tests/mips32/change_fp_mode.vgtest
trunk/none/tests/mips32/fpu_branches.c
trunk/none/tests/mips32/fpu_branches.vgtest
trunk/none/tests/mips32/round.c
trunk/none/tests/mips32/round.vgtest
trunk/none/tests/mips32/round_fpu64.c
trunk/none/tests/mips32/round_fpu64.vgtest
trunk/none/tests/mips32/test_fcsr.c
trunk/none/tests/mips32/test_fcsr.vgtest
trunk/none/tests/mips32/vfp.c
trunk/none/tests/mips32/vfp.vgtest
trunk/none/tests/mips64/change_fp_mode.c
trunk/none/tests/mips64/change_fp_mode.vgtest
Modified: trunk/coregrind/m_machine.c
==============================================================================
--- trunk/coregrind/m_machine.c (original)
+++ trunk/coregrind/m_machine.c Wed Oct 12 16:13:27 2016
@@ -1738,10 +1738,6 @@
}
}
- VG_(convert_sigaction_fromK_to_toK)(&saved_sigill_act, &tmp_sigill_act);
- VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL);
- VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);
-
# if defined(VGP_mips32_linux)
Int fpmode = VG_(prctl)(VKI_PR_GET_FP_MODE);
# else
@@ -1752,25 +1748,33 @@
/* prctl(PR_GET_FP_MODE) is not supported by Kernel,
we are using alternative way to determine FP mode */
ULong result = 0;
- __asm__ volatile (
- ".set push\n\t"
- ".set noreorder\n\t"
- ".set oddspreg\n\t"
- "lui $t0, 0x3FF0\n\t"
- "ldc1 $f0, %0\n\t"
- "mtc1 $t0, $f1\n\t"
- "sdc1 $f0, %0\n\t"
- ".set pop\n\t"
- : "+m"(result)
- :
- : "t0", "$f0", "$f1", "memory");
- fpmode = (result != 0x3FF0000000000000ull);
+ if (!VG_MINIMAL_SETJMP(env_unsup_insn)) {
+ __asm__ volatile (
+ ".set push\n\t"
+ ".set noreorder\n\t"
+ ".set oddspreg\n\t"
+ ".set hardfloat\n\t"
+ "lui $t0, 0x3FF0\n\t"
+ "ldc1 $f0, %0\n\t"
+ "mtc1 $t0, $f1\n\t"
+ "sdc1 $f0, %0\n\t"
+ ".set pop\n\t"
+ : "+m"(result)
+ :
+ : "t0", "$f0", "$f1", "memory");
+
+ fpmode = (result != 0x3FF0000000000000ull);
+ }
}
if (fpmode != 0)
vai.hwcaps |= VEX_MIPS_HOST_FR;
+ VG_(convert_sigaction_fromK_to_toK)(&saved_sigill_act, &tmp_sigill_act);
+ VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL);
+ VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);
+
VG_(debugLog)(1, "machine", "hwcaps = 0x%x\n", vai.hwcaps);
VG_(machine_get_cache_info)(&vai);
Modified: trunk/none/tests/mips32/FPUarithmetic.c
==============================================================================
--- trunk/none/tests/mips32/FPUarithmetic.c (original)
+++ trunk/none/tests/mips32/FPUarithmetic.c Wed Oct 12 16:13:27 2016
@@ -1,3 +1,5 @@
+#if defined(__mips_hard_float)
+
#include <stdio.h>
#include <stdlib.h>
@@ -235,4 +237,8 @@
return 0;
}
-
+#else
+int main() {
+ return 0;
+}
+#endif
Modified: trunk/none/tests/mips32/FPUarithmetic.vgtest
==============================================================================
--- trunk/none/tests/mips32/FPUarithmetic.vgtest (original)
+++ trunk/none/tests/mips32/FPUarithmetic.vgtest Wed Oct 12 16:13:27 2016
@@ -1,2 +1,3 @@
prog: FPUarithmetic
+prereq: ../../../tests/mips_features fpu
vgopts: -q
Modified: trunk/none/tests/mips32/MoveIns.c
==============================================================================
--- trunk/none/tests/mips32/MoveIns.c (original)
+++ trunk/none/tests/mips32/MoveIns.c Wed Oct 12 16:13:27 2016
@@ -1,3 +1,5 @@
+#if defined(__mips_hard_float)
+
#include <stdint.h>
#include <stdio.h>
@@ -661,3 +663,8 @@
return 0;
}
+#else
+int main() {
+ return 0;
+}
+#endif
Modified: trunk/none/tests/mips32/MoveIns.vgtest
==============================================================================
--- trunk/none/tests/mips32/MoveIns.vgtest (original)
+++ trunk/none/tests/mips32/MoveIns.vgtest Wed Oct 12 16:13:27 2016
@@ -1,2 +1,3 @@
prog: MoveIns
+prereq: ../../../tests/mips_features fpu
vgopts: -q
Modified: trunk/none/tests/mips32/change_fp_mode.c
==============================================================================
--- trunk/none/tests/mips32/change_fp_mode.c (original)
+++ trunk/none/tests/mips32/change_fp_mode.c Wed Oct 12 16:13:27 2016
@@ -1,3 +1,5 @@
+#if defined(__mips_hard_float)
+
#include <elf.h>
#include <stdio.h>
#include <stdlib.h>
@@ -76,3 +78,8 @@
return 0;
}
+#else
+int main() {
+ return 0;
+}
+#endif
Modified: trunk/none/tests/mips32/change_fp_mode.vgtest
==============================================================================
--- trunk/none/tests/mips32/change_fp_mode.vgtest (original)
+++ trunk/none/tests/mips32/change_fp_mode.vgtest Wed Oct 12 16:13:27 2016
@@ -1,2 +1,3 @@
prog: change_fp_mode
+prereq: ../../../tests/mips_features fpu
vgopts: -q
Modified: trunk/none/tests/mips32/fpu_branches.c
==============================================================================
--- trunk/none/tests/mips32/fpu_branches.c (original)
+++ trunk/none/tests/mips32/fpu_branches.c Wed Oct 12 16:13:27 2016
@@ -1,3 +1,5 @@
+#if defined(__mips_hard_float)
+
#include <stdio.h>
#define MAX_ARR 24
@@ -314,4 +316,8 @@
}
return 0;
}
-
+#else
+int main() {
+ return 0;
+}
+#endif
Modified: trunk/none/tests/mips32/fpu_branches.vgtest
==============================================================================
--- trunk/none/tests/mips32/fpu_branches.vgtest (original)
+++ trunk/none/tests/mips32/fpu_branches.vgtest Wed Oct 12 16:13:27 2016
@@ -1,2 +1,3 @@
prog: fpu_branches
+prereq: ../../../tests/mips_features fpu
vgopts: -q
Modified: trunk/none/tests/mips32/round.c
==============================================================================
--- trunk/none/tests/mips32/round.c (original)
+++ trunk/none/tests/mips32/round.c Wed Oct 12 16:13:27 2016
@@ -1,3 +1,5 @@
+#if defined(__mips_hard_float)
+
#include <stdio.h>
typedef enum {
@@ -289,4 +291,9 @@
}
return 0;
}
+#else
+int main() {
+ return 0;
+}
+#endif
Modified: trunk/none/tests/mips32/round.vgtest
==============================================================================
--- trunk/none/tests/mips32/round.vgtest (original)
+++ trunk/none/tests/mips32/round.vgtest Wed Oct 12 16:13:27 2016
@@ -1,2 +1,3 @@
prog: round
+prereq: ../../../tests/mips_features fpu
vgopts: -q
Modified: trunk/none/tests/mips32/round_fpu64.c
==============================================================================
--- trunk/none/tests/mips32/round_fpu64.c (original)
+++ trunk/none/tests/mips32/round_fpu64.c Wed Oct 12 16:13:27 2016
@@ -1,3 +1,5 @@
+#if defined(__mips_hard_float)
+
#include <stdio.h>
#include <stdlib.h>
#include <signal.h>
@@ -202,3 +204,8 @@
#endif
return 0;
}
+#else
+int main() {
+ return 0;
+}
+#endif
Modified: trunk/none/tests/mips32/round_fpu64.vgtest
==============================================================================
--- trunk/none/tests/mips32/round_fpu64.vgtest (original)
+++ trunk/none/tests/mips32/round_fpu64.vgtest Wed Oct 12 16:13:27 2016
@@ -1,2 +1,3 @@
prog: round_fpu64
+prereq: ../../../tests/mips_features fpu
vgopts: -q
Modified: trunk/none/tests/mips32/test_fcsr.c
==============================================================================
--- trunk/none/tests/mips32/test_fcsr.c (original)
+++ trunk/none/tests/mips32/test_fcsr.c Wed Oct 12 16:13:27 2016
@@ -1,3 +1,5 @@
+#if defined(__mips_hard_float)
+
#include <stdio.h>
int main ()
@@ -23,3 +25,8 @@
printf("FCSR::1: 0x%x, 2: 0x%x\n", out[0], out[1]);
return 0;
}
+#else
+int main() {
+ return 0;
+}
+#endif
Modified: trunk/none/tests/mips32/test_fcsr.vgtest
==============================================================================
--- trunk/none/tests/mips32/test_fcsr.vgtest (original)
+++ trunk/none/tests/mips32/test_fcsr.vgtest Wed Oct 12 16:13:27 2016
@@ -1,2 +1,3 @@
prog: test_fcsr
+prereq: ../../../tests/mips_features fpu
vgopts: -q
Modified: trunk/none/tests/mips32/vfp.c
==============================================================================
--- trunk/none/tests/mips32/vfp.c (original)
+++ trunk/none/tests/mips32/vfp.c Wed Oct 12 16:13:27 2016
@@ -1,3 +1,5 @@
+#if defined(__mips_hard_float)
+
#include <stdint.h>
#include <stdio.h>
@@ -405,4 +407,8 @@
return 0;
}
-
+#else
+int main() {
+ return 0;
+}
+#endif
Modified: trunk/none/tests/mips32/vfp.vgtest
==============================================================================
--- trunk/none/tests/mips32/vfp.vgtest (original)
+++ trunk/none/tests/mips32/vfp.vgtest Wed Oct 12 16:13:27 2016
@@ -1,2 +1,3 @@
prog: vfp
+prereq: ../../../tests/mips_features fpu
vgopts: -q
Modified: trunk/none/tests/mips64/change_fp_mode.c
==============================================================================
--- trunk/none/tests/mips64/change_fp_mode.c (original)
+++ trunk/none/tests/mips64/change_fp_mode.c Wed Oct 12 16:13:27 2016
@@ -1,3 +1,5 @@
+#if defined(__mips_hard_float)
+
#include <elf.h>
#include <stdio.h>
#include <stdlib.h>
@@ -257,3 +259,8 @@
return 0;
}
+#else
+int main() {
+ return 0;
+}
+#endif
Modified: trunk/none/tests/mips64/change_fp_mode.vgtest
==============================================================================
--- trunk/none/tests/mips64/change_fp_mode.vgtest (original)
+++ trunk/none/tests/mips64/change_fp_mode.vgtest Wed Oct 12 16:13:27 2016
@@ -1,2 +1,3 @@
prog: change_fp_mode
+prereq: ../../../tests/mips_features fpu
vgopts: -q
|
|
From: <sv...@va...> - 2016-10-12 15:02:17
|
Author: petarj
Date: Wed Oct 12 16:02:10 2016
New Revision: 3261
Log:
mips: allow VEX to be compiled for soft-float
Force "hardfloat" mode for inline assembly that uses FPU instructions,
but pop original mode at the end of the assembly.
This should allow Valgrind to be compiled as a soft-float binary, but
that executable should be used for soft-float systems only.
Related issue - BZ#351282.
Patch by Aleksandar Rikalo.
Modified:
trunk/priv/guest_mips_helpers.c
Modified: trunk/priv/guest_mips_helpers.c
==============================================================================
--- trunk/priv/guest_mips_helpers.c (original)
+++ trunk/priv/guest_mips_helpers.c Wed Oct 12 16:02:10 2016
@@ -459,75 +459,93 @@
#endif
#define ASM_VOLATILE_UNARY32(inst) \
- __asm__ volatile("cfc1 $t0, $31" "\n\t" \
+ __asm__ volatile(".set push" "\n\t" \
+ ".set hardfloat" "\n\t" \
+ "cfc1 $t0, $31" "\n\t" \
"ctc1 %2, $31" "\n\t" \
"mtc1 %1, $f20" "\n\t" \
#inst" $f20, $f20" "\n\t" \
"cfc1 %0, $31" "\n\t" \
"ctc1 $t0, $31" "\n\t" \
+ ".set pop" "\n\t" \
: "=r" (ret) \
: "r" (loFsVal), "r" (fcsr) \
: "t0", "$f20" \
);
#define ASM_VOLATILE_UNARY32_DOUBLE(inst) \
- __asm__ volatile("cfc1 $t0, $31" "\n\t" \
+ __asm__ volatile(".set push" "\n\t" \
+ ".set hardfloat" "\n\t" \
+ "cfc1 $t0, $31" "\n\t" \
"ctc1 %2, $31" "\n\t" \
"ldc1 $f20, 0(%1)" "\n\t" \
#inst" $f20, $f20" "\n\t" \
"cfc1 %0, $31" "\n\t" \
"ctc1 $t0, $31" "\n\t" \
+ ".set pop" "\n\t" \
: "=r" (ret) \
: "r" (&fsVal), "r" (fcsr) \
: "t0", "$f20", "$f21" \
);
#define ASM_VOLATILE_UNARY64(inst) \
- __asm__ volatile("cfc1 $t0, $31" "\n\t" \
+ __asm__ volatile(".set push" "\n\t" \
+ ".set hardfloat" "\n\t" \
+ "cfc1 $t0, $31" "\n\t" \
"ctc1 %2, $31" "\n\t" \
"ldc1 $f24, 0(%1)" "\n\t" \
#inst" $f24, $f24" "\n\t" \
"cfc1 %0, $31" "\n\t" \
"ctc1 $t0, $31" "\n\t" \
+ ".set pop" "\n\t" \
: "=r" (ret) \
: "r" (&(addr[fs])), "r" (fcsr) \
: "t0", "$f24" \
);
#define ASM_VOLATILE_BINARY32(inst) \
- __asm__ volatile("cfc1 $t0, $31" "\n\t" \
+ __asm__ volatile(".set push" "\n\t" \
+ ".set hardfloat" "\n\t" \
+ "cfc1 $t0, $31" "\n\t" \
"ctc1 %3, $31" "\n\t" \
"mtc1 %1, $f20" "\n\t" \
"mtc1 %2, $f22" "\n\t" \
#inst" $f20, $f20, $f22" "\n\t" \
"cfc1 %0, $31" "\n\t" \
"ctc1 $t0, $31" "\n\t" \
+ ".set pop" "\n\t" \
: "=r" (ret) \
: "r" (loFsVal), "r" (loFtVal), "r" (fcsr) \
: "t0", "$f20", "$f22" \
);
#define ASM_VOLATILE_BINARY32_DOUBLE(inst) \
- __asm__ volatile("cfc1 $t0, $31" "\n\t" \
+ __asm__ volatile(".set push" "\n\t" \
+ ".set hardfloat" "\n\t" \
+ "cfc1 $t0, $31" "\n\t" \
"ctc1 %3, $31" "\n\t" \
"ldc1 $f20, 0(%1)" "\n\t" \
"ldc1 $f22, 0(%2)" "\n\t" \
#inst" $f20, $f20, $f22" "\n\t" \
"cfc1 %0, $31" "\n\t" \
"ctc1 $t0, $31" "\n\t" \
+ ".set pop" "\n\t" \
: "=r" (ret) \
: "r" (&fsVal), "r" (&ftVal), "r" (fcsr) \
: "t0", "$f20", "$f21", "$f22", "$f23" \
);
#define ASM_VOLATILE_BINARY64(inst) \
- __asm__ volatile("cfc1 $t0, $31" "\n\t" \
+ __asm__ volatile(".set push" "\n\t" \
+ ".set hardfloat" "\n\t" \
+ "cfc1 $t0, $31" "\n\t" \
"ctc1 %3, $31" "\n\t" \
"ldc1 $f24, 0(%1)" "\n\t" \
"ldc1 $f26, 0(%2)" "\n\t" \
#inst" $f24, $f24, $f26" "\n\t" \
"cfc1 %0, $31" "\n\t" \
"ctc1 $t0, $31" "\n\t" \
+ ".set pop" "\n\t" \
: "=r" (ret) \
: "r" (&(addr[fs])), "r" (&(addr[ft])), "r" (fcsr) \
: "t0", "$f24", "$f26" \
|
|
From: <sv...@va...> - 2016-10-12 14:16:17
|
Author: petarj
Date: Wed Oct 12 15:16:08 2016
New Revision: 16038
Log:
mips: clear fcc bits in fcsr after calling printf()
Clear floating point condition codes in the test after calling external
function (in this case printf), as it might have clobbered fcc bits in
fcsr.
This resolves none/tests/mips64/round.c failure on some systems.
Patch by Aleksandra Karadzic.
Modified:
trunk/none/tests/mips32/round.c
trunk/none/tests/mips64/round.c
trunk/none/tests/mips64/rounding_mode.h
Modified: trunk/none/tests/mips32/round.c
==============================================================================
--- trunk/none/tests/mips32/round.c (original)
+++ trunk/none/tests/mips32/round.c Wed Oct 12 15:16:08 2016
@@ -149,12 +149,24 @@
}
}
+void clear_fcc(){
+ __asm__ __volatile__(
+ "cfc1 $t0, $31" "\n\t"
+ "and $t0, $t0, 0x17FFFFF" "\n\t"
+ "ctc1 $t0, $31" "\n\t"
+ :
+ :
+ : "t0"
+ );
+}
+
int directedRoundingMode(flt_dir_op_t op) {
int fd_w = 0;
int i;
int fcsr = 0;
round_mode_t rm = TO_NEAREST;
for (i = 0; i < 24; i++) {
+ clear_fcc();
set_rounding_mode(rm);
switch(op) {
case CEILWS:
@@ -217,6 +229,7 @@
set_rounding_mode(rm);
printf("roundig mode: %s\n", round_mode_name[rm]);
for (i = 0; i < 24; i++) {
+ clear_fcc();
set_rounding_mode(rm);
switch(op1) {
case CVTDS:
Modified: trunk/none/tests/mips64/round.c
==============================================================================
--- trunk/none/tests/mips64/round.c (original)
+++ trunk/none/tests/mips64/round.c Wed Oct 12 15:16:08 2016
@@ -9,6 +9,7 @@
int i;
int fcsr = 0;
for (i = 0; i < MAX_ARR; i++) {
+ clear_fcc();
switch(op) {
case CEILWS:
UNOPfw("ceil.w.s");
@@ -111,6 +112,7 @@
set_rounding_mode(rm);
printf("roundig mode: %s\n", round_mode_name[rm]);
for (i = 0; i < MAX_ARR; i++) {
+ clear_fcc();
set_rounding_mode(rm);
switch(op1) {
case CVTDS:
Modified: trunk/none/tests/mips64/rounding_mode.h
==============================================================================
--- trunk/none/tests/mips64/rounding_mode.h (original)
+++ trunk/none/tests/mips64/rounding_mode.h Wed Oct 12 15:16:08 2016
@@ -60,4 +60,15 @@
break;
}
}
+
+void clear_fcc(){
+ __asm__ __volatile__(
+ "cfc1 $t0, $31" "\n\t"
+ "and $t0, $t0, 0x17FFFFF" "\n\t"
+ "ctc1 $t0, $31" "\n\t"
+ :
+ :
+ : "t0"
+ );
+}
#endif
|