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From: <sv...@va...> - 2016-08-06 13:04:39
|
Author: sewardj
Date: Sat Aug 6 14:04:32 2016
New Revision: 3240
Log:
Fix UBSAN reported complaints about left shifts of signed values
in the arm32 front and back ends.
Modified:
trunk/priv/guest_arm_toIR.c
trunk/priv/host_arm_defs.c
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Sat Aug 6 14:04:32 2016
@@ -1598,8 +1598,9 @@
IRTemp regT, /* value to clamp - Ity_I32 */
UInt imm5 ) /* saturation ceiling */
{
- UInt ceil = (1 << imm5) - 1; // (2^imm5)-1
- UInt floor = 0;
+ ULong ceil64 = (1ULL << imm5) - 1; // (2^imm5)-1
+ UInt ceil = (UInt)ceil64;
+ UInt floor = 0;
IRTemp nd0 = newTemp(Ity_I32);
IRTemp nd1 = newTemp(Ity_I32);
@@ -1642,8 +1643,10 @@
IRTemp* res, /* OUT - Ity_I32 */
IRTemp* resQ ) /* OUT - Ity_I32 */
{
- Int ceil = (1 << (imm5-1)) - 1; // (2^(imm5-1))-1
- Int floor = -(1 << (imm5-1)); // -(2^(imm5-1))
+ Long ceil64 = (1LL << (imm5-1)) - 1; // (2^(imm5-1))-1
+ Long floor64 = -(1LL << (imm5-1)); // -(2^(imm5-1))
+ Int ceil = (Int)ceil64;
+ Int floor = (Int)floor64;
IRTemp nd0 = newTemp(Ity_I32);
IRTemp nd1 = newTemp(Ity_I32);
@@ -8874,8 +8877,8 @@
&& INSN(27,24) == BITS4(1,1,1,1)) {
// Thumb, DP
UInt reformatted = INSN(23,0);
- reformatted |= (INSN(28,28) << 24); // U bit
- reformatted |= (BITS7(1,1,1,1,0,0,1) << 25);
+ reformatted |= (((UInt)INSN(28,28)) << 24); // U bit
+ reformatted |= (((UInt)BITS7(1,1,1,1,0,0,1)) << 25);
return dis_neon_data_processing(reformatted, condT);
}
@@ -8889,7 +8892,7 @@
}
if (isT && INSN(31,24) == BITS8(1,1,1,1,1,0,0,1)) {
UInt reformatted = INSN(23,0);
- reformatted |= (BITS8(1,1,1,1,0,1,0,0) << 24);
+ reformatted |= (((UInt)BITS8(1,1,1,1,0,1,0,0)) << 24);
return dis_neon_load_or_store(reformatted, isT, condT);
}
@@ -14542,7 +14545,7 @@
IRExpr* rm = mkU32(Irrm_NEAREST);
IRTemp scale = newTemp(Ity_F64);
- assign(scale, unop(Iop_I32UtoF64, mkU32( 1 << (frac_bits-1) )));
+ assign(scale, unop(Iop_I32UtoF64, mkU32( ((UInt)1) << (frac_bits-1) )));
if (frac_bits >= 1 && frac_bits <= 32 && !to_fixed && !dp_op
&& size == 32) {
@@ -14719,8 +14722,9 @@
// and set CPSR.T = 1, that is, switch to Thumb mode
if (INSN(31,25) == BITS7(1,1,1,1,1,0,1)) {
UInt bitH = INSN(24,24);
- Int uimm24 = INSN(23,0);
- Int simm24 = (((uimm24 << 8) >> 8) << 2) + (bitH << 1);
+ UInt uimm24 = INSN(23,0); uimm24 <<= 8;
+ Int simm24 = (Int)uimm24; simm24 >>= 8;
+ simm24 = (((UInt)simm24) << 2) + (bitH << 1);
/* Now this is a bit tricky. Since we're decoding an ARM insn,
it is implies that CPSR.T == 0. Hence the current insn's
address is guaranteed to be of the form X--(30)--X00. So, no
@@ -15756,10 +15760,9 @@
//
if (BITS8(1,0,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0))) {
UInt link = (insn >> 24) & 1;
- UInt uimm24 = insn & ((1<<24)-1);
- Int simm24 = (Int)uimm24;
- UInt dst = guest_R15_curr_instr_notENC + 8
- + (((simm24 << 8) >> 8) << 2);
+ UInt uimm24 = insn & ((1<<24)-1); uimm24 <<= 8;
+ Int simm24 = (Int)uimm24; simm24 >>= 8;
+ UInt dst = guest_R15_curr_instr_notENC + 8 + (((UInt)simm24) << 2);
IRJumpKind jk = link ? Ijk_Call : Ijk_Boring;
if (link) {
putIRegA(14, mkU32(guest_R15_curr_instr_notENC + 4),
@@ -16539,7 +16542,7 @@
IRTemp src = newTemp(Ity_I32);
IRTemp olddst = newTemp(Ity_I32);
IRTemp newdst = newTemp(Ity_I32);
- UInt mask = 1 << (msb - lsb);
+ UInt mask = ((UInt)1) << (msb - lsb);
mask = (mask - 1) + mask;
vassert(mask != 0); // guaranteed by "msb < lsb" check above
mask <<= lsb;
@@ -19353,8 +19356,8 @@
case BITS5(1,1,1,0,0): {
/* ---------------- B #simm11 ---------------- */
- Int simm11 = INSN0(10,0);
- simm11 = (simm11 << 21) >> 20;
+ UInt uimm11 = INSN0(10,0); uimm11 <<= 21;
+ Int simm11 = (Int)uimm11; simm11 >>= 20;
UInt dst = simm11 + guest_R15_curr_instr_notENC + 4;
/* Only allowed outside or last-in IT block; SIGILL if not so. */
gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate);
@@ -19383,8 +19386,8 @@
case BITS4(1,1,0,1): {
/* ---------------- Bcond #simm8 ---------------- */
UInt cond = INSN0(11,8);
- Int simm8 = INSN0(7,0);
- simm8 = (simm8 << 24) >> 23;
+ UInt uimm8 = INSN0(7,0); uimm8 <<= 24;
+ Int simm8 = (Int)uimm8; simm8 >>= 23;
UInt dst = simm8 + guest_R15_curr_instr_notENC + 4;
if (cond != ARMCondAL && cond != ARMCondNV) {
/* Not allowed in an IT block; SIGILL if so. */
@@ -19472,13 +19475,15 @@
UInt bJ2 = INSN1(11,11);
UInt bI1 = 1 ^ (bJ1 ^ bS);
UInt bI2 = 1 ^ (bJ2 ^ bS);
- Int simm25
+ UInt uimm25
= (bS << (1 + 1 + 10 + 11 + 1))
| (bI1 << (1 + 10 + 11 + 1))
| (bI2 << (10 + 11 + 1))
| (INSN0(9,0) << (11 + 1))
| (INSN1(10,0) << 1);
- simm25 = (simm25 << 7) >> 7;
+ uimm25 <<= 7;
+ Int simm25 = (Int)uimm25;
+ simm25 >>= 7;
vassert(0 == (guest_R15_curr_instr_notENC & 1));
UInt dst = simm25 + guest_R15_curr_instr_notENC + 4;
@@ -20900,13 +20905,15 @@
&& INSN1(12,12) == 0) {
UInt cond = INSN0(9,6);
if (cond != ARMCondAL && cond != ARMCondNV) {
- Int simm21
+ UInt uimm21
= (INSN0(10,10) << (1 + 1 + 6 + 11 + 1))
| (INSN1(11,11) << (1 + 6 + 11 + 1))
| (INSN1(13,13) << (6 + 11 + 1))
| (INSN0(5,0) << (11 + 1))
| (INSN1(10,0) << 1);
- simm21 = (simm21 << 11) >> 11;
+ uimm21 <<= 11;
+ Int simm21 = (Int)uimm21;
+ simm21 >>= 11;
vassert(0 == (guest_R15_curr_instr_notENC & 1));
UInt dst = simm21 + guest_R15_curr_instr_notENC + 4;
@@ -20944,13 +20951,15 @@
UInt bJ2 = INSN1(11,11);
UInt bI1 = 1 ^ (bJ1 ^ bS);
UInt bI2 = 1 ^ (bJ2 ^ bS);
- Int simm25
+ UInt uimm25
= (bS << (1 + 1 + 10 + 11 + 1))
| (bI1 << (1 + 10 + 11 + 1))
| (bI2 << (10 + 11 + 1))
| (INSN0(9,0) << (11 + 1))
| (INSN1(10,0) << 1);
- simm25 = (simm25 << 7) >> 7;
+ uimm25 <<= 7;
+ Int simm25 = (Int)uimm25;
+ simm25 >>= 7;
vassert(0 == (guest_R15_curr_instr_notENC & 1));
UInt dst = simm25 + guest_R15_curr_instr_notENC + 4;
@@ -21392,7 +21401,7 @@
IRTemp src = newTemp(Ity_I32);
IRTemp olddst = newTemp(Ity_I32);
IRTemp newdst = newTemp(Ity_I32);
- UInt mask = 1 << (msb - lsb);
+ UInt mask = ((UInt)1) << (msb - lsb);
mask = (mask - 1) + mask;
vassert(mask != 0); // guaranteed by "msb < lsb" check above
mask <<= lsb;
Modified: trunk/priv/host_arm_defs.c
==============================================================================
--- trunk/priv/host_arm_defs.c (original)
+++ trunk/priv/host_arm_defs.c Sat Aug 6 14:04:32 2016
@@ -2776,33 +2776,38 @@
#define X1111 BITS4(1,1,1,1)
#define XXXXX___(zzx7,zzx6,zzx5,zzx4,zzx3) \
- ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \
+ (((((UInt)(zzx7)) & 0xF) << 28) | \
+ (((zzx6) & 0xF) << 24) | \
(((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \
(((zzx3) & 0xF) << 12))
#define XXXXXX__(zzx7,zzx6,zzx5,zzx4,zzx3,zzx2) \
- ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \
+ (((((UInt)(zzx7)) & 0xF) << 28) | \
+ (((zzx6) & 0xF) << 24) | \
(((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \
(((zzx3) & 0xF) << 12) | (((zzx2) & 0xF) << 8))
#define XXXXX__X(zzx7,zzx6,zzx5,zzx4,zzx3,zzx0) \
- ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \
+ (((((UInt)(zzx7)) & 0xF) << 28) | \
+ (((zzx6) & 0xF) << 24) | \
(((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \
(((zzx3) & 0xF) << 12) | (((zzx0) & 0xF) << 0))
#define XXX___XX(zzx7,zzx6,zzx5,zzx1,zzx0) \
- ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \
+ (((((UInt)(zzx7)) & 0xF) << 28) | \
+ (((zzx6) & 0xF) << 24) | \
(((zzx5) & 0xF) << 20) | (((zzx1) & 0xF) << 4) | \
(((zzx0) & 0xF) << 0))
#define XXXXXXXX(zzx7,zzx6,zzx5,zzx4,zzx3,zzx2,zzx1,zzx0) \
- ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24) | \
+ (((((UInt)(zzx7)) & 0xF) << 28) | \
+ (((zzx6) & 0xF) << 24) | \
(((zzx5) & 0xF) << 20) | (((zzx4) & 0xF) << 16) | \
(((zzx3) & 0xF) << 12) | (((zzx2) & 0xF) << 8) | \
(((zzx1) & 0xF) << 4) | (((zzx0) & 0xF) << 0))
#define XX______(zzx7,zzx6) \
- ((((zzx7) & 0xF) << 28) | (((zzx6) & 0xF) << 24))
+ (((((UInt)(zzx7)) & 0xF) << 28) | (((zzx6) & 0xF) << 24))
/* Generate a skeletal insn that involves an a RI84 shifter operand.
Returns a word which is all zeroes apart from bits 25 and 11..0,
@@ -4838,8 +4843,11 @@
/* And make the modifications. */
if (shortOK) {
- Int simm24 = (Int)(delta >> 2);
- vassert(simm24 == ((simm24 << 8) >> 8));
+ UInt uimm24 = (UInt)(delta >> 2);
+ UInt uimm24_shl8 = uimm24 << 8;
+ Int simm24 = (Int)uimm24_shl8;
+ simm24 >>= 8;
+ vassert(uimm24 == simm24);
p[0] = 0xEA000000 | (simm24 & 0x00FFFFFF);
p[1] = 0xFF000000;
p[2] = 0xFF000000;
|
|
From: <sv...@va...> - 2016-08-06 12:34:06
|
Author: sewardj
Date: Sat Aug 6 13:33:59 2016
New Revision: 15932
Log:
Fix uses of CPSR in these tests, so that (1) the relevant fields are
initialised properly before the test, and (2) after the test, we don't
print implementation-defined parts of the resulting CPSR.
Modified:
trunk/none/tests/arm/v6intARM.c
trunk/none/tests/arm/v6intThumb.c
trunk/none/tests/arm/v6media.c
Modified: trunk/none/tests/arm/v6intARM.c
==============================================================================
--- trunk/none/tests/arm/v6intARM.c (original)
+++ trunk/none/tests/arm/v6intARM.c Sat Aug 6 13:33:59 2016
@@ -13,8 +13,8 @@
\
__asm__ volatile( \
"movs %3,%3;" \
- "msrne cpsr_f,#(1<<29);" \
- "msreq cpsr_f,#0;" \
+ "msrne cpsr_fs,#(1<<29);" \
+ "msreq cpsr_fs,#0;" \
"mov " #RM ",%2;" \
/* set #RD to 0x55555555 so we can see which parts get overwritten */ \
"mov " #RD ", #0x55" "\n\t" \
@@ -30,7 +30,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, RMval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -45,8 +45,8 @@
\
__asm__ volatile( \
"movs %4,%4;" \
- "msrne cpsr_f,#(1<<29);" \
- "msreq cpsr_f,#0;" \
+ "msrne cpsr_fs,#(1<<29);" \
+ "msreq cpsr_fs,#0;" \
"mov " #RM ",%2;" \
"mov " #RN ",%3;" \
instruction ";" \
@@ -59,7 +59,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, RMval, RNval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -74,8 +74,8 @@
\
__asm__ volatile( \
"movs %5,%5;" \
- "msrne cpsr_f,#(1<<29);" \
- "msreq cpsr_f,#0;" \
+ "msrne cpsr_fs,#(1<<29);" \
+ "msreq cpsr_fs,#0;" \
"mov " #RM ",%2;" \
"mov " #RN ",%3;" \
"mov " #RS ",%4;" \
@@ -89,7 +89,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, RMval, RNval, RSval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -105,8 +105,8 @@
\
__asm__ volatile( \
"movs %7,%7;" \
- "msrne cpsr_f,#(1<<29);" \
- "msreq cpsr_f,#0;" \
+ "msrne cpsr_fs,#(1<<29);" \
+ "msreq cpsr_fs,#0;" \
"mov " #RD ",%3;" \
"mov " #RD2 ",%4;" \
"mov " #RM ",%5;" \
@@ -122,7 +122,7 @@
printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, out2, RMval, RSval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
Modified: trunk/none/tests/arm/v6intThumb.c
==============================================================================
--- trunk/none/tests/arm/v6intThumb.c (original)
+++ trunk/none/tests/arm/v6intThumb.c Sat Aug 6 13:33:59 2016
@@ -22,7 +22,7 @@
unsigned int cpsr; \
\
__asm__ volatile( \
- "msr cpsr_f, %2;" \
+ "msr cpsr_fs, %2;" \
instruction ";" \
"mov %0," #RD ";" \
"mrs %1,cpsr;" \
@@ -33,7 +33,7 @@
printf("%s :: rd 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -50,7 +50,7 @@
unsigned int cpsr; \
\
__asm__ volatile( \
- "msr cpsr_f, %2;" \
+ "msr cpsr_fs, %2;" \
"mov " #RD ",%3;" \
instruction ";" \
"mov %0," #RD ";" \
@@ -62,7 +62,7 @@
printf("%s :: rd 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -77,7 +77,7 @@
unsigned int cpsr; \
\
__asm__ volatile( \
- "msr cpsr_f, %3;" \
+ "msr cpsr_fs, %3;" \
"mov " #RM ",%2;" \
/* set #RD to 0x55555555 so we can see which parts get overwritten */ \
"mov " #RD ", #0x55" "\n\t" \
@@ -93,7 +93,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, RMval, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -109,7 +109,7 @@
unsigned int cpsr; \
\
__asm__ volatile( \
- "msr cpsr_f, %3;" \
+ "msr cpsr_fs, %3;" \
"mov " #RM ",%2;" \
"mov " #RD ",%4;" \
instruction ";" \
@@ -122,7 +122,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, RMval, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -138,7 +138,7 @@
unsigned int cpsr; \
\
__asm__ volatile( \
- "msr cpsr_f, %4;" \
+ "msr cpsr_fs, %4;" \
"mov " #RM ",%2;" \
"mov " #RN ",%3;" \
instruction ";" \
@@ -151,7 +151,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, RMval, RNval, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -165,7 +165,7 @@
unsigned int cpsr; \
\
__asm__ volatile( \
- "msr cpsr_f, %5;" \
+ "msr cpsr_fs, %5;" \
"mov " #RM ",%2;" \
"mov " #RN ",%3;" \
"mov " #RS ",%4;" \
@@ -179,7 +179,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, RMval, RNval, RSval, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -194,7 +194,7 @@
unsigned int cpsr; \
\
__asm__ volatile( \
- "msr cpsr_f, %7;" \
+ "msr cpsr_fs, %7;" \
"mov " #RD ",%3;" \
"mov " #RD2 ",%4;" \
"mov " #RM ",%5;" \
@@ -210,7 +210,7 @@
printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, out2, RMval, RSval, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -225,7 +225,7 @@
unsigned int cpsr; \
__asm__ volatile(\
".align 4;" \
- "msr cpsr_f, %2;" \
+ "msr cpsr_fs, %2;" \
"mov " #RD ", #0;" \
".align 2;" \
".thumb;" \
@@ -248,7 +248,7 @@
); \
printf("%s :: rd 0x%08x, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -264,7 +264,7 @@
unsigned int cpsr; \
__asm__ volatile(\
".align 4;" \
- "msr cpsr_f, %3;" \
+ "msr cpsr_fs, %3;" \
".align 2;" \
".thumb;" \
".syntax unified;" \
@@ -287,7 +287,7 @@
); \
printf("%s :: s0 0x%08x s1 0x%08x, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, out2, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -302,7 +302,7 @@
unsigned int cpsr; \
__asm__ volatile(\
".align 4;" \
- "msr cpsr_f, %3;" \
+ "msr cpsr_fs, %3;" \
"mov " #RD ", #0;" \
"mov " #RD2 ", #0;" \
".align 2;" \
@@ -327,7 +327,7 @@
); \
printf("%s :: rd 0x%08x rd2 0x%08x, cpsr 0x%08x %c%c%c%c\n", \
instruction, out, out2, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -358,7 +358,7 @@
__asm__ volatile(
".thumb;\n"
".syntax unified ;\n"
- "msr cpsr_f, %3 ;\n"
+ "msr cpsr_fs, %3 ;\n"
"mov r9, %2 ;\n"
"movw r2, #:lower16:.ldrwpclabel1 ;\n"
"movt r2, #:upper16:.ldrwpclabel1 ;\n"
@@ -386,7 +386,7 @@
"cpsr 0x%08x %c%c%c%c\n", \
out, \
cvin, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
Modified: trunk/none/tests/arm/v6media.c
==============================================================================
--- trunk/none/tests/arm/v6media.c (original)
+++ trunk/none/tests/arm/v6media.c Sat Aug 6 13:33:59 2016
@@ -37,7 +37,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \
instruction, out, RMval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -66,7 +66,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \
instruction, out, RMval, RNval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -96,7 +96,7 @@
printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \
instruction, out, RMval, RNval, RSval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
@@ -129,7 +129,7 @@
printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c%c ge[3:0]=%d%d%d%d\n", \
instruction, out, out2, RMval, RSval, \
carryin ? 1 : 0, \
- cpsr & 0xffff0000, \
+ cpsr & 0xff0f0000, \
((1<<31) & cpsr) ? 'N' : ' ', \
((1<<30) & cpsr) ? 'Z' : ' ', \
((1<<29) & cpsr) ? 'C' : ' ', \
|
|
From: <sv...@va...> - 2016-08-06 12:32:44
|
Author: sewardj
Date: Sat Aug 6 13:32:37 2016
New Revision: 15931
Log:
do_vldm_vstm_check: don't use caller saved FP ('s') registers to hold
data that we expect to stay alive over calls to printf. Fixes erratic
failures of this test.
Modified:
trunk/none/tests/arm/vfp.c
Modified: trunk/none/tests/arm/vfp.c
==============================================================================
--- trunk/none/tests/arm/vfp.c (original)
+++ trunk/none/tests/arm/vfp.c Sat Aug 6 13:32:37 2016
@@ -848,55 +848,55 @@
printf("do_vldm_vstm_check:\n");
__asm__ volatile(
"mov r1, %0\n\t"
- "vldmia r1!, {s0, s1, s2, s3}\n\t"
+ "vldmia r1!, {s16, s17, s18, s19}\n\t"
"mov r0, %1\n\t"
"sub r1, r1, %0\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s2\n\t"
+ "vmov r1, s18\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s3\n\t"
+ "vmov r1, s19\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s0\n\t"
+ "vmov r1, s16\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
/* --- */
"add r1, %0, #32\n\t"
- "vldmdb r1!, {s5, s6}\n\t"
+ "vldmdb r1!, {s25, s26}\n\t"
"mov r0, %1\n\t"
"sub r1, r1, %0\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s5\n\t"
+ "vmov r1, s25\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s6\n\t"
+ "vmov r1, s26\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
/* --- */
"add r1, %0, #4\n\t"
- "vldmia r1, {s0, s1, s2, s3}\n\t"
+ "vldmia r1, {s20, s21, s22, s23}\n\t"
"mov r0, %1\n\t"
"sub r1, r1, %0\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s2\n\t"
+ "vmov r1, s22\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s3\n\t"
+ "vmov r1, s23\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
"mov r0, %1\n\t"
- "vmov r1, s0\n\t"
+ "vmov r1, s20\n\t"
"mov r3, r1\n\t"
"bl printf\n\t"
/* --- */
@@ -970,15 +970,15 @@
"bl printf\n\t"
/* --- */
"mov r0, #0x55\n\t"
- "vmov s0, r0\n\t"
+ "vmov s20, r0\n\t"
"mov r0, #0x56\n\t"
- "vmov s1, r0\n\t"
+ "vmov s21, r0\n\t"
"mov r0, #0x57\n\t"
- "vmov s2, r0\n\t"
+ "vmov s22, r0\n\t"
"mov r0, #0x58\n\t"
- "vmov s3, r0\n\t"
+ "vmov s23, r0\n\t"
"add r1, %0, #0\n\t"
- "vstmia r1!, {s0, s1, s2, s3}\n\t"
+ "vstmia r1!, {s20, s21, s22, s23}\n\t"
"mov r0, %1\n\t"
"sub r1, r1, %0\n\t"
"mov r3, r1\n\t"
@@ -1044,7 +1044,8 @@
:
: "r" (data), "r" (format), "r"(&res)
: "r0", "r1", "r2", "r3", "r5", "r12", "r14", "memory",
- "s0", "s1", "s2", "s3", "s5", "s6", "s16", "s17",
+ "s0", "s1", "s2", "s3", "s5", "s6", "s16", "s17", "s18", "s19",
+ "s20", "s21", "s22", "s23", "s25", "s26",
"d10", "d30", "d31"
);
printf("data:\n");
|
|
From: <sv...@va...> - 2016-08-06 07:15:38
|
Author: sewardj
Date: Sat Aug 6 08:15:30 2016
New Revision: 15930
Log:
Fix invalid code caught by Ubsan, in which we compute the address
of "cgs->events[-1]", even though it isn't dereferenced.
Modified:
trunk/cachegrind/cg_main.c
trunk/callgrind/main.c
Modified: trunk/cachegrind/cg_main.c
==============================================================================
--- trunk/cachegrind/cg_main.c (original)
+++ trunk/cachegrind/cg_main.c Sat Aug 6 08:15:30 2016
@@ -914,7 +914,6 @@
static
void addEvent_Dw ( CgState* cgs, InstrInfo* inode, Int datasize, IRAtom* ea )
{
- Event* lastEvt;
Event* evt;
tl_assert(isIRAtom(ea));
@@ -924,15 +923,16 @@
return;
/* Is it possible to merge this write with the preceding read? */
- lastEvt = &cgs->events[cgs->events_used-1];
- if (cgs->events_used > 0
- && lastEvt->tag == Ev_Dr
- && lastEvt->Ev.Dr.szB == datasize
- && lastEvt->inode == inode
- && eqIRAtom(lastEvt->Ev.Dr.ea, ea))
- {
- lastEvt->tag = Ev_Dm;
- return;
+ if (cgs->events_used > 0) {
+ Event* lastEvt = &cgs->events[cgs->events_used-1];
+ if ( lastEvt->tag == Ev_Dr
+ && lastEvt->Ev.Dr.szB == datasize
+ && lastEvt->inode == inode
+ && eqIRAtom(lastEvt->Ev.Dr.ea, ea))
+ {
+ lastEvt->tag = Ev_Dm;
+ return;
+ }
}
/* No. Add as normal. */
Modified: trunk/callgrind/main.c
==============================================================================
--- trunk/callgrind/main.c (original)
+++ trunk/callgrind/main.c Sat Aug 6 08:15:30 2016
@@ -637,7 +637,6 @@
static
void addEvent_Dw ( ClgState* clgs, InstrInfo* inode, Int datasize, IRAtom* ea )
{
- Event* lastEvt;
Event* evt;
tl_assert(isIRAtom(ea));
tl_assert(datasize >= 1);
@@ -645,15 +644,16 @@
tl_assert(datasize <= CLG_(min_line_size));
/* Is it possible to merge this write with the preceding read? */
- lastEvt = &clgs->events[clgs->events_used-1];
- if (clgs->events_used > 0
- && lastEvt->tag == Ev_Dr
- && lastEvt->Ev.Dr.szB == datasize
- && lastEvt->inode == inode
- && eqIRAtom(lastEvt->Ev.Dr.ea, ea))
- {
- lastEvt->tag = Ev_Dm;
- return;
+ if (clgs->events_used > 0) {
+ Event* lastEvt = &clgs->events[clgs->events_used-1];
+ if ( lastEvt->tag == Ev_Dr
+ && lastEvt->Ev.Dr.szB == datasize
+ && lastEvt->inode == inode
+ && eqIRAtom(lastEvt->Ev.Dr.ea, ea))
+ {
+ lastEvt->tag = Ev_Dm;
+ return;
+ }
}
/* No. Add as normal. */
|