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From: <sv...@va...> - 2016-07-19 07:09:03
|
Author: sewardj
Date: Tue Jul 19 08:08:56 2016
New Revision: 15909
Log:
Update w/ recent arm64 insn emulation fixes.
Modified:
trunk/NEWS
trunk/docs/internals/3_11_BUGSTATUS.txt
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Tue Jul 19 08:08:56 2016
@@ -86,6 +86,7 @@
== 363497
== 364497
356817 valgrind.h triggers compiler errors on MSVC when defining NVALGRIND
+357338 Unhandled instruction for SHA instructions libcrypto Boring SSL
357833 Setting RLIMIT_DATA to zero breaks with linux 4.5+
357871 pthread_spin_destroy not properly wrapped
357887 Calls to VG_(fclose) do not close the file descriptor
@@ -102,11 +103,13 @@
359767 Valgrind does not support the IBM POWER ISA 3.0 instructions
359829 Power PC test suite none/tests/ppc64/test_isa_2_07.c uses
uninitialized data
+359838 arm64: Unhandled instruction 0xD5033F5F (clrex)
359871 Incorrect mask handling in ppoll
360008 Contents of Power vr registers contents is not printed correctly when
the --vgdb-shadow-registers=yes option is used
360035 POWER PC instruction bcdadd and bcdsubtract generate result with
non-zero shadow bits
+360378 arm64: Unhandled instruction 0x5E280844 (sha1h s4, s2)
360425 arm64 unsupported instruction ldpsw
== 364435
360519 none/tests/arm64/memory.vgtest might fail with newer gcc
Modified: trunk/docs/internals/3_11_BUGSTATUS.txt
==============================================================================
--- trunk/docs/internals/3_11_BUGSTATUS.txt (original)
+++ trunk/docs/internals/3_11_BUGSTATUS.txt Tue Jul 19 08:08:56 2016
@@ -8,6 +8,7 @@
351491 Unrecognised instruction in library compiled with -mavx -ffast-math -O3
351726 vex amd64->IR: 0xC5 0xF3 0xC2 0x15 0xEB 0x7C 0x2 0x0
[JRS: potentially serious, miscalculated next %RIP]
+ [can't repro]
352549 Valgrind (whether with memchek or callgrind) crashes with
"unhandled instruction bytes"
[Probably invalid]
@@ -43,10 +44,6 @@
=== VEX/arm64 ==========================================================
-357338 Unhandled instruction for SHA instructions libcrypto Boring SSL
-359838 arm64: Unhandled instruction 0xD5033F5F (clrex)
-360378 arm64: Unhandled instruction 0x5E280844 (sha1h s4, s2)
-
=== VEX/x86 ============================================================
355231 Unhandled Instruction Bytes (SSE4, vmovdqu, "0xC5 0xFA 0x6F 0x2")
|
|
From: <sv...@va...> - 2016-07-19 07:05:41
|
Author: sewardj
Date: Tue Jul 19 08:05:34 2016
New Revision: 3227
Log:
Implement CLREX. Fixes #359838.
Modified:
trunk/priv/guest_arm64_toIR.c
trunk/priv/host_arm64_defs.c
trunk/priv/host_arm64_defs.h
trunk/priv/host_arm64_isel.c
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Tue Jul 19 08:05:34 2016
@@ -6952,7 +6952,21 @@
return True;
}
- //fail:
+ /* ------------------- CLREX ------------------ */
+ /* 31 23 15 11 7
+ 1101 0101 0000 0011 0011 m 0101 1111 CLREX CRm
+ CRm is apparently ignored.
+ */
+ if ((INSN(31,0) & 0xFFFFF0FF) == 0xD503305F) {
+ UInt mm = INSN(11,8);
+ /* AFAICS, this simply cancels a (all?) reservations made by a
+ (any?) preceding LDREX(es). Arrange to hand it through to
+ the back end. */
+ stmt( IRStmt_MBE(Imbe_CancelReservation) );
+ DIP("clrex #%u\n", mm);
+ return True;
+ }
+
vex_printf("ARM64 front end: branch_etc\n");
return False;
# undef INSN
Modified: trunk/priv/host_arm64_defs.c
==============================================================================
--- trunk/priv/host_arm64_defs.c (original)
+++ trunk/priv/host_arm64_defs.c Tue Jul 19 08:05:34 2016
@@ -1010,6 +1010,11 @@
i->tag = ARM64in_MFence;
return i;
}
+ARM64Instr* ARM64Instr_ClrEX ( void ) {
+ ARM64Instr* i = LibVEX_Alloc_inline(sizeof(ARM64Instr));
+ i->tag = ARM64in_ClrEX;
+ return i;
+}
ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) {
ARM64Instr* i = LibVEX_Alloc_inline(sizeof(ARM64Instr));
i->tag = ARM64in_VLdStH;
@@ -1567,6 +1572,9 @@
case ARM64in_MFence:
vex_printf("(mfence) dsb sy; dmb sy; isb");
return;
+ case ARM64in_ClrEX:
+ vex_printf("clrex #15");
+ return;
case ARM64in_VLdStH:
if (i->ARM64in.VLdStH.isLoad) {
vex_printf("ldr ");
@@ -2058,6 +2066,8 @@
return;
case ARM64in_MFence:
return;
+ case ARM64in_ClrEX:
+ return;
case ARM64in_VLdStH:
addHRegUse(u, HRmRead, i->ARM64in.VLdStH.rN);
if (i->ARM64in.VLdStH.isLoad) {
@@ -2318,6 +2328,8 @@
return;
case ARM64in_MFence:
return;
+ case ARM64in_ClrEX:
+ return;
case ARM64in_VLdStH:
i->ARM64in.VLdStH.hD = lookupHRegRemap(m, i->ARM64in.VLdStH.hD);
i->ARM64in.VLdStH.rN = lookupHRegRemap(m, i->ARM64in.VLdStH.rN);
@@ -3797,12 +3809,10 @@
*p++ = 0xD5033FDF; /* ISB */
goto done;
}
- //case ARM64in_CLREX: {
- // //ATC, but believed to be correct
- // goto bad;
- // *p++ = 0xD5033F5F; /* clrex */
- // goto done;
- //}
+ case ARM64in_ClrEX: {
+ *p++ = 0xD5033F5F; /* clrex #15 */
+ goto done;
+ }
case ARM64in_VLdStH: {
/* 01 111101 01 imm12 n t LDR Ht, [Xn|SP, #imm12 * 2]
01 111101 00 imm12 n t STR Ht, [Xn|SP, #imm12 * 2]
Modified: trunk/priv/host_arm64_defs.h
==============================================================================
--- trunk/priv/host_arm64_defs.h (original)
+++ trunk/priv/host_arm64_defs.h Tue Jul 19 08:05:34 2016
@@ -482,6 +482,7 @@
ARM64in_LdrEX,
ARM64in_StrEX,
ARM64in_MFence,
+ ARM64in_ClrEX,
/* ARM64in_V*: scalar ops involving vector registers */
ARM64in_VLdStH, /* ld/st to/from low 16 bits of vec reg, imm offset */
ARM64in_VLdStS, /* ld/st to/from low 32 bits of vec reg, imm offset */
@@ -673,6 +674,9 @@
total nuclear overkill, but better safe than sorry. */
struct {
} MFence;
+ /* A CLREX instruction. */
+ struct {
+ } ClrEX;
/* --- INSTRUCTIONS INVOLVING VECTOR REGISTERS --- */
/* ld/st to/from low 16 bits of vec reg, imm offset */
struct {
@@ -909,6 +913,7 @@
extern ARM64Instr* ARM64Instr_LdrEX ( Int szB );
extern ARM64Instr* ARM64Instr_StrEX ( Int szB );
extern ARM64Instr* ARM64Instr_MFence ( void );
+extern ARM64Instr* ARM64Instr_ClrEX ( void );
extern ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN,
UInt uimm12 /* 0 .. 8190, 0 % 2 */ );
extern ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN,
Modified: trunk/priv/host_arm64_isel.c
==============================================================================
--- trunk/priv/host_arm64_isel.c (original)
+++ trunk/priv/host_arm64_isel.c Tue Jul 19 08:05:34 2016
@@ -3839,6 +3839,9 @@
case Imbe_Fence:
addInstr(env, ARM64Instr_MFence());
return;
+ case Imbe_CancelReservation:
+ addInstr(env, ARM64Instr_ClrEX());
+ return;
default:
break;
}
|
|
From: <sv...@va...> - 2016-07-19 05:33:00
|
Author: sewardj
Date: Tue Jul 19 06:32:50 2016
New Revision: 3226
Log:
dis_pc_relative, case 0x002: remove a path that cannot be taken. That
stops gcc -Og complaining. It complains because at that relatively
low level of optimisation, its flow analysis is apparently too weak to
see that the removed path cannot be taken and so it complains
(wrongly) about a possibly uninitialised use of |result|. No
functional change.
Modified:
trunk/priv/guest_ppc_toIR.c
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Tue Jul 19 06:32:50 2016
@@ -7603,13 +7603,11 @@
if ( ty == Ity_I32 ) {
result = binop( Iop_Add32, nia, mkU32( D << 16 ) );
-
- } else if ( ty == Ity_I64 ) {
- result = binop( Iop_Add64, nia, mkU64( D << 16 ) );
-
} else {
- vex_printf("dis_pc_relative(unsupported type)\n");
+ vassert( ty == Ity_I64 );
+ result = binop( Iop_Add64, nia, mkU64( D << 16 ) );
}
+
putIReg( rT_addr, result);
}
break;
|