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From: <sv...@va...> - 2016-07-20 17:02:02
|
Author: sewardj
Date: Wed Jul 20 18:01:55 2016
New Revision: 3229
Log:
If an instruction can't be decoded, print the first 10 bytes at RSP
rather than 8. 8 is not enough to disambiguate the instruction in
some situations, in particular where there is a control immediate byte
at the end of the instruction.
Modified:
trunk/priv/guest_amd64_toIR.c
Modified: trunk/priv/guest_amd64_toIR.c
==============================================================================
--- trunk/priv/guest_amd64_toIR.c (original)
+++ trunk/priv/guest_amd64_toIR.c Wed Jul 20 18:01:55 2016
@@ -32077,7 +32077,7 @@
/* All decode failures end up here. */
if (sigill_diag) {
vex_printf("vex amd64->IR: unhandled instruction bytes: "
- "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+ "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
getUChar(delta_start+0),
getUChar(delta_start+1),
getUChar(delta_start+2),
@@ -32085,7 +32085,9 @@
getUChar(delta_start+4),
getUChar(delta_start+5),
getUChar(delta_start+6),
- getUChar(delta_start+7) );
+ getUChar(delta_start+7),
+ getUChar(delta_start+8),
+ getUChar(delta_start+9) );
vex_printf("vex amd64->IR: REX=%d REX.W=%d REX.R=%d REX.X=%d REX.B=%d\n",
haveREX(pfx) ? 1 : 0, getRexW(pfx), getRexR(pfx),
getRexX(pfx), getRexB(pfx));
|
|
From: <sv...@va...> - 2016-07-20 16:37:16
|
Author: sewardj
Date: Wed Jul 20 17:37:09 2016
New Revision: 15910
Log:
Add test cases for PCMPxSTRx cases 0x70 and 0x19. Pertains to #359952.
Modified:
trunk/none/tests/amd64/pcmpstr64.c
trunk/none/tests/amd64/pcmpstr64.stdout.exp
trunk/none/tests/amd64/pcmpstr64w.c
trunk/none/tests/amd64/pcmpstr64w.stdout.exp
Modified: trunk/none/tests/amd64/pcmpstr64.c
==============================================================================
--- trunk/none/tests/amd64/pcmpstr64.c (original)
+++ trunk/none/tests/amd64/pcmpstr64.c Wed Jul 20 17:37:09 2016
@@ -207,6 +207,7 @@
case 0x12: case 0x14: case 0x18: case 0x1A:
case 0x30: case 0x34: case 0x38: case 0x3A:
case 0x40: case 0x42: case 0x44: case 0x46: case 0x4A:
+ case 0x70:
break;
default:
return False;
@@ -1971,6 +1972,86 @@
//////////////////////////////////////////////////////////
// //
+// ISTRI_70 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_70 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x70, %%xmm2, %%xmm11" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_70 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x70, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_70 ( void )
+{
+ char* wot = "70";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_70;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_70;
+
+ try_istri(wot,h,s, "abcdacbdabcdabcd", "000000000000000a");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000000b");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "00000000000000ab");
+ try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd");
+
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0bcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcda0cd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdab0d", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdabc0", "000000000000abcd");
+
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000a0cd");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000ab0d");
+ try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abc0");
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000bbbb");
+ try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000baba");
+
+ try_istri(wot,h,s, "0000abcdabcdabcd", "00000000000baba0");
+
+ try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe");
+ try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe");
+}
+
+
+//////////////////////////////////////////////////////////
+// //
// main //
// //
//////////////////////////////////////////////////////////
@@ -1995,5 +2076,6 @@
istri_0E();
istri_14();
istri_34();
+ istri_70();
return 0;
}
Modified: trunk/none/tests/amd64/pcmpstr64.stdout.exp
==============================================================================
--- trunk/none/tests/amd64/pcmpstr64.stdout.exp (original)
+++ trunk/none/tests/amd64/pcmpstr64.stdout.exp Wed Jul 20 17:37:09 2016
@@ -458,3 +458,25 @@
istri 34 fc937cbfbf53f8e2 0d136bcb024d3fb7 -> 08810000 08810000
istri 34 2ca34182c29a82ab 302ebd646775ab54 -> 08810000 08810000
istri 34 3f2987608c11be6f a9ecb661f8e0a8cb -> 08c10000 08c10000
+istri 70 abcdacbdabcdabcd 000000000000000a -> 0881000e 0881000e
+istri 70 abcdabcdabcdabcd 000000000000000b -> 0881000f 0881000f
+istri 70 abcdabcdabcdabcd 00000000000000ab -> 0881000d 0881000d
+istri 70 abcdabc0abcdabcd 000000000000abcd -> 00c00010 00c00010
+istri 70 abcdabcdabcdabcd 000000000000abcd -> 00800010 00800010
+istri 70 0bcdabcdabcdabcd 000000000000abcd -> 00c00010 00c00010
+istri 70 abcdabcdabcda0cd 000000000000abcd -> 00c00010 00c00010
+istri 70 abcdabcdabcdab0d 000000000000abcd -> 00c00010 00c00010
+istri 70 abcdabcdabcdabc0 000000000000abcd -> 00c00010 00c00010
+istri 70 abcdabcdabcdabcd 000000000000abcd -> 00800010 00800010
+istri 70 abcdabcdabcdabcd 000000000000a0cd -> 0081000f 0081000f
+istri 70 abcdabcdabcdabcd 000000000000ab0d -> 0081000f 0081000f
+istri 70 abcdabcdabcdabcd 000000000000abc0 -> 0881000f 0881000f
+istri 70 0000000000000000 0000000000000000 -> 00c00010 00c00010
+istri 70 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000010 00000010
+istri 70 0000abcdabcdabcd 000000000000abcd -> 00c00010 00c00010
+istri 70 0000abcdabcdabcd 000000000000dcba -> 00c00010 00c00010
+istri 70 0000abcdabcdabcd 000000000000bbbb -> 08c1000b 08c1000b
+istri 70 0000abcdabcdabcd 000000000000baba -> 08c10009 08c10009
+istri 70 0000abcdabcdabcd 00000000000baba0 -> 08c1000b 08c1000b
+istri 70 0ddc0ffeebadf00d 00000000cafebabe -> 08c10000 08c10000
+istri 70 0ddc0ffeebadfeed 00000000cafebabe -> 08c10004 08c10004
Modified: trunk/none/tests/amd64/pcmpstr64w.c
==============================================================================
--- trunk/none/tests/amd64/pcmpstr64w.c (original)
+++ trunk/none/tests/amd64/pcmpstr64w.c Wed Jul 20 17:37:09 2016
@@ -209,7 +209,7 @@
unvalidated cases in the code base. */
switch (imm8) {
case 0x01: case 0x03: case 0x09: case 0x0B: case 0x0D:
- case 0x13: case 0x1B:
+ case 0x13: case 0x19: case 0x1B:
case 0x39: case 0x3B:
case 0x45: case 0x4B:
break;
@@ -1255,6 +1255,99 @@
//////////////////////////////////////////////////////////
// //
+// ISTRI_19 //
+// //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_19 ( V128* argL, V128* argR )
+{
+ V128 block[2];
+ memcpy(&block[0], argL, sizeof(V128));
+ memcpy(&block[1], argR, sizeof(V128));
+ ULong res, flags;
+ __asm__ __volatile__(
+ "subq $1024, %%rsp" "\n\t"
+ "movdqu 0(%2), %%xmm2" "\n\t"
+ "movdqu 16(%2), %%xmm11" "\n\t"
+ "pcmpistri $0x19, %%xmm2, %%xmm11" "\n\t"
+ "pushfq" "\n\t"
+ "popq %%rdx" "\n\t"
+ "movq %%rcx, %0" "\n\t"
+ "movq %%rdx, %1" "\n\t"
+ "addq $1024, %%rsp" "\n\t"
+ : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+ : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+ );
+ return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_19 ( V128* argLU, V128* argRU )
+{
+ V128 resV;
+ UInt resOSZACP, resECX;
+ Bool ok
+ = pcmpXstrX_WRK_wide( &resV, &resOSZACP, argLU, argRU,
+ zmask_from_V128(argLU),
+ zmask_from_V128(argRU),
+ 0x19, False/*!isSTRM*/
+ );
+ assert(ok);
+ resECX = resV.uInt[0];
+ return (resOSZACP << 16) | resECX;
+}
+
+void istri_19 ( void )
+{
+ char* wot = "19";
+ UInt(*h)(V128*,V128*) = h_pcmpistri_19;
+ UInt(*s)(V128*,V128*) = s_pcmpistri_19;
+
+ try_istri(wot,h,s, "0000000000000000", "0000000000000000");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa");
+ try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa00aa");
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaa00aa");
+
+ try_istri(wot,h,s, "aaaaaaaa00aaaaaa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa00aa");
+ try_istri(wot,h,s, "aaaaaaaa00aaaaaa", "aaaaaaaaaaaa00aa");
+
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaa00aa", "aaaaaaaa00aaaaaa");
+
+ try_istri(wot,h,s, "0000000000000000", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "8000000000000000", "aaaaaaaa00aaaaaa");
+ try_istri(wot,h,s, "0000000000000001", "aaaaaaaa00aaaaaa");
+
+ try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa");
+ try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000");
+}
+
+
+
+//////////////////////////////////////////////////////////
+// //
// main //
// //
//////////////////////////////////////////////////////////
@@ -1271,5 +1364,6 @@
istri_45();
istri_01();
istri_39();
+ istri_19();
return 0;
}
Modified: trunk/none/tests/amd64/pcmpstr64w.stdout.exp
==============================================================================
--- trunk/none/tests/amd64/pcmpstr64w.stdout.exp (original)
+++ trunk/none/tests/amd64/pcmpstr64w.stdout.exp Wed Jul 20 17:37:09 2016
@@ -258,3 +258,33 @@
istri 39 0000000000000001 aaaaaaaa00aaaaaa -> 08c10000 08c10000
istri 39 0000000000000000 aaaaaaaaaaaaaaaa -> 00400008 00400008
istri 39 aaaaaaaaaaaaaaaa 0000000000000000 -> 08810000 08810000
+istri 19 0000000000000000 0000000000000000 -> 00c00008 00c00008
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 19 aaaa2aaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010005 00010005
+istri 19 aaaaaaaaa2aaaaaa aaaaaaaaaaaaaaaa -> 00010003 00010003
+istri 19 aaaaaaaaaaaaa2aa aaaaaaaaaaaaaaaa -> 00010001 00010001
+istri 19 aaaaaaaaaaaaaaaa aaaa2aaaaaaaaaaa -> 00010005 00010005
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaaa2aaaaaa -> 00010003 00010003
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaa2a -> 08010000 08010000
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 19 baaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010007 00010007
+istri 19 b9aaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010007 00010007
+istri 19 b9baaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010006 00010006
+istri 19 b9baaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00010006 00010006
+istri 19 b9baaaaaaaaaaaaa aaaaaaaaaaaa7aaa -> 00010001 00010001
+istri 19 b9baaaaaaaaaaaaa aaaaaaaa2aaa4aaa -> 00010001 00010001
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -> 00000008 00000008
+istri 19 aaaaaaaaaaaa00aa aaaaaaaaaaaaaaaa -> 00410001 00410001
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaaaaaa00aa -> 00810001 00810001
+istri 19 aaaaaaaaaaaa00aa aaaaaaaaaaaa00aa -> 00c00008 00c00008
+istri 19 aaaaaaaa00aaaaaa aaaaaaaaaaaaaaaa -> 00410003 00410003
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaaaaaa00aa -> 00810001 00810001
+istri 19 aaaaaaaa00aaaaaa aaaaaaaaaaaa00aa -> 00c10001 00c10001
+istri 19 aaaaaaaaaaaa00aa aaaaaaaaaaaaaaaa -> 00410001 00410001
+istri 19 aaaaaaaaaaaaaaaa aaaaaaaa00aaaaaa -> 00810003 00810003
+istri 19 aaaaaaaaaaaa00aa aaaaaaaa00aaaaaa -> 00c10001 00c10001
+istri 19 0000000000000000 aaaaaaaa00aaaaaa -> 08c10000 08c10000
+istri 19 8000000000000000 aaaaaaaa00aaaaaa -> 08c10000 08c10000
+istri 19 0000000000000001 aaaaaaaa00aaaaaa -> 08c10000 08c10000
+istri 19 0000000000000000 aaaaaaaaaaaaaaaa -> 08410000 08410000
+istri 19 aaaaaaaaaaaaaaaa 0000000000000000 -> 08810000 08810000
|
|
From: <sv...@va...> - 2016-07-20 16:36:03
|
Author: sewardj
Date: Wed Jul 20 17:35:55 2016
New Revision: 3228
Log:
Enable PCMPxSTRx cases 0x70 and 0x19. Fixes #359952.
Modified:
trunk/priv/guest_amd64_toIR.c
trunk/priv/guest_generic_x87.c
Modified: trunk/priv/guest_amd64_toIR.c
==============================================================================
--- trunk/priv/guest_amd64_toIR.c (original)
+++ trunk/priv/guest_amd64_toIR.c Wed Jul 20 17:35:55 2016
@@ -18671,10 +18671,11 @@
case 0x12: case 0x14: case 0x18: case 0x1A:
case 0x30: case 0x34: case 0x38: case 0x3A:
case 0x40: case 0x42: case 0x44: case 0x46: case 0x4A:
+ case 0x70:
break;
// the 16-bit character versions of the above
case 0x01: case 0x03: case 0x09: case 0x0B: case 0x0D:
- case 0x13: case 0x1B:
+ case 0x13: case 0x19: case 0x1B:
case 0x39: case 0x3B:
case 0x45: case 0x4B:
break;
Modified: trunk/priv/guest_generic_x87.c
==============================================================================
--- trunk/priv/guest_generic_x87.c (original)
+++ trunk/priv/guest_generic_x87.c Wed Jul 20 17:35:55 2016
@@ -799,6 +799,7 @@
case 0x12: case 0x14: case 0x18: case 0x1A:
case 0x30: case 0x34: case 0x38: case 0x3A:
case 0x40: case 0x42: case 0x44: case 0x46: case 0x4A:
+ case 0x70:
break;
default:
return False;
@@ -1047,7 +1048,7 @@
unvalidated cases in the code base. */
switch (imm8) {
case 0x01: case 0x03: case 0x09: case 0x0B: case 0x0D:
- case 0x13: case 0x1B:
+ case 0x13: case 0x19: case 0x1B:
case 0x39: case 0x3B:
case 0x45: case 0x4B:
break;
|
|
From: <sv...@va...> - 2016-07-19 07:09:03
|
Author: sewardj
Date: Tue Jul 19 08:08:56 2016
New Revision: 15909
Log:
Update w/ recent arm64 insn emulation fixes.
Modified:
trunk/NEWS
trunk/docs/internals/3_11_BUGSTATUS.txt
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Tue Jul 19 08:08:56 2016
@@ -86,6 +86,7 @@
== 363497
== 364497
356817 valgrind.h triggers compiler errors on MSVC when defining NVALGRIND
+357338 Unhandled instruction for SHA instructions libcrypto Boring SSL
357833 Setting RLIMIT_DATA to zero breaks with linux 4.5+
357871 pthread_spin_destroy not properly wrapped
357887 Calls to VG_(fclose) do not close the file descriptor
@@ -102,11 +103,13 @@
359767 Valgrind does not support the IBM POWER ISA 3.0 instructions
359829 Power PC test suite none/tests/ppc64/test_isa_2_07.c uses
uninitialized data
+359838 arm64: Unhandled instruction 0xD5033F5F (clrex)
359871 Incorrect mask handling in ppoll
360008 Contents of Power vr registers contents is not printed correctly when
the --vgdb-shadow-registers=yes option is used
360035 POWER PC instruction bcdadd and bcdsubtract generate result with
non-zero shadow bits
+360378 arm64: Unhandled instruction 0x5E280844 (sha1h s4, s2)
360425 arm64 unsupported instruction ldpsw
== 364435
360519 none/tests/arm64/memory.vgtest might fail with newer gcc
Modified: trunk/docs/internals/3_11_BUGSTATUS.txt
==============================================================================
--- trunk/docs/internals/3_11_BUGSTATUS.txt (original)
+++ trunk/docs/internals/3_11_BUGSTATUS.txt Tue Jul 19 08:08:56 2016
@@ -8,6 +8,7 @@
351491 Unrecognised instruction in library compiled with -mavx -ffast-math -O3
351726 vex amd64->IR: 0xC5 0xF3 0xC2 0x15 0xEB 0x7C 0x2 0x0
[JRS: potentially serious, miscalculated next %RIP]
+ [can't repro]
352549 Valgrind (whether with memchek or callgrind) crashes with
"unhandled instruction bytes"
[Probably invalid]
@@ -43,10 +44,6 @@
=== VEX/arm64 ==========================================================
-357338 Unhandled instruction for SHA instructions libcrypto Boring SSL
-359838 arm64: Unhandled instruction 0xD5033F5F (clrex)
-360378 arm64: Unhandled instruction 0x5E280844 (sha1h s4, s2)
-
=== VEX/x86 ============================================================
355231 Unhandled Instruction Bytes (SSE4, vmovdqu, "0xC5 0xFA 0x6F 0x2")
|
|
From: <sv...@va...> - 2016-07-19 07:05:41
|
Author: sewardj
Date: Tue Jul 19 08:05:34 2016
New Revision: 3227
Log:
Implement CLREX. Fixes #359838.
Modified:
trunk/priv/guest_arm64_toIR.c
trunk/priv/host_arm64_defs.c
trunk/priv/host_arm64_defs.h
trunk/priv/host_arm64_isel.c
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Tue Jul 19 08:05:34 2016
@@ -6952,7 +6952,21 @@
return True;
}
- //fail:
+ /* ------------------- CLREX ------------------ */
+ /* 31 23 15 11 7
+ 1101 0101 0000 0011 0011 m 0101 1111 CLREX CRm
+ CRm is apparently ignored.
+ */
+ if ((INSN(31,0) & 0xFFFFF0FF) == 0xD503305F) {
+ UInt mm = INSN(11,8);
+ /* AFAICS, this simply cancels a (all?) reservations made by a
+ (any?) preceding LDREX(es). Arrange to hand it through to
+ the back end. */
+ stmt( IRStmt_MBE(Imbe_CancelReservation) );
+ DIP("clrex #%u\n", mm);
+ return True;
+ }
+
vex_printf("ARM64 front end: branch_etc\n");
return False;
# undef INSN
Modified: trunk/priv/host_arm64_defs.c
==============================================================================
--- trunk/priv/host_arm64_defs.c (original)
+++ trunk/priv/host_arm64_defs.c Tue Jul 19 08:05:34 2016
@@ -1010,6 +1010,11 @@
i->tag = ARM64in_MFence;
return i;
}
+ARM64Instr* ARM64Instr_ClrEX ( void ) {
+ ARM64Instr* i = LibVEX_Alloc_inline(sizeof(ARM64Instr));
+ i->tag = ARM64in_ClrEX;
+ return i;
+}
ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) {
ARM64Instr* i = LibVEX_Alloc_inline(sizeof(ARM64Instr));
i->tag = ARM64in_VLdStH;
@@ -1567,6 +1572,9 @@
case ARM64in_MFence:
vex_printf("(mfence) dsb sy; dmb sy; isb");
return;
+ case ARM64in_ClrEX:
+ vex_printf("clrex #15");
+ return;
case ARM64in_VLdStH:
if (i->ARM64in.VLdStH.isLoad) {
vex_printf("ldr ");
@@ -2058,6 +2066,8 @@
return;
case ARM64in_MFence:
return;
+ case ARM64in_ClrEX:
+ return;
case ARM64in_VLdStH:
addHRegUse(u, HRmRead, i->ARM64in.VLdStH.rN);
if (i->ARM64in.VLdStH.isLoad) {
@@ -2318,6 +2328,8 @@
return;
case ARM64in_MFence:
return;
+ case ARM64in_ClrEX:
+ return;
case ARM64in_VLdStH:
i->ARM64in.VLdStH.hD = lookupHRegRemap(m, i->ARM64in.VLdStH.hD);
i->ARM64in.VLdStH.rN = lookupHRegRemap(m, i->ARM64in.VLdStH.rN);
@@ -3797,12 +3809,10 @@
*p++ = 0xD5033FDF; /* ISB */
goto done;
}
- //case ARM64in_CLREX: {
- // //ATC, but believed to be correct
- // goto bad;
- // *p++ = 0xD5033F5F; /* clrex */
- // goto done;
- //}
+ case ARM64in_ClrEX: {
+ *p++ = 0xD5033F5F; /* clrex #15 */
+ goto done;
+ }
case ARM64in_VLdStH: {
/* 01 111101 01 imm12 n t LDR Ht, [Xn|SP, #imm12 * 2]
01 111101 00 imm12 n t STR Ht, [Xn|SP, #imm12 * 2]
Modified: trunk/priv/host_arm64_defs.h
==============================================================================
--- trunk/priv/host_arm64_defs.h (original)
+++ trunk/priv/host_arm64_defs.h Tue Jul 19 08:05:34 2016
@@ -482,6 +482,7 @@
ARM64in_LdrEX,
ARM64in_StrEX,
ARM64in_MFence,
+ ARM64in_ClrEX,
/* ARM64in_V*: scalar ops involving vector registers */
ARM64in_VLdStH, /* ld/st to/from low 16 bits of vec reg, imm offset */
ARM64in_VLdStS, /* ld/st to/from low 32 bits of vec reg, imm offset */
@@ -673,6 +674,9 @@
total nuclear overkill, but better safe than sorry. */
struct {
} MFence;
+ /* A CLREX instruction. */
+ struct {
+ } ClrEX;
/* --- INSTRUCTIONS INVOLVING VECTOR REGISTERS --- */
/* ld/st to/from low 16 bits of vec reg, imm offset */
struct {
@@ -909,6 +913,7 @@
extern ARM64Instr* ARM64Instr_LdrEX ( Int szB );
extern ARM64Instr* ARM64Instr_StrEX ( Int szB );
extern ARM64Instr* ARM64Instr_MFence ( void );
+extern ARM64Instr* ARM64Instr_ClrEX ( void );
extern ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN,
UInt uimm12 /* 0 .. 8190, 0 % 2 */ );
extern ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN,
Modified: trunk/priv/host_arm64_isel.c
==============================================================================
--- trunk/priv/host_arm64_isel.c (original)
+++ trunk/priv/host_arm64_isel.c Tue Jul 19 08:05:34 2016
@@ -3839,6 +3839,9 @@
case Imbe_Fence:
addInstr(env, ARM64Instr_MFence());
return;
+ case Imbe_CancelReservation:
+ addInstr(env, ARM64Instr_ClrEX());
+ return;
default:
break;
}
|
|
From: <sv...@va...> - 2016-07-19 05:33:00
|
Author: sewardj
Date: Tue Jul 19 06:32:50 2016
New Revision: 3226
Log:
dis_pc_relative, case 0x002: remove a path that cannot be taken. That
stops gcc -Og complaining. It complains because at that relatively
low level of optimisation, its flow analysis is apparently too weak to
see that the removed path cannot be taken and so it complains
(wrongly) about a possibly uninitialised use of |result|. No
functional change.
Modified:
trunk/priv/guest_ppc_toIR.c
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Tue Jul 19 06:32:50 2016
@@ -7603,13 +7603,11 @@
if ( ty == Ity_I32 ) {
result = binop( Iop_Add32, nia, mkU32( D << 16 ) );
-
- } else if ( ty == Ity_I64 ) {
- result = binop( Iop_Add64, nia, mkU64( D << 16 ) );
-
} else {
- vex_printf("dis_pc_relative(unsupported type)\n");
+ vassert( ty == Ity_I64 );
+ result = binop( Iop_Add64, nia, mkU64( D << 16 ) );
}
+
putIReg( rT_addr, result);
}
break;
|
|
From: <sv...@va...> - 2016-07-18 06:35:25
|
Author: sewardj
Date: Mon Jul 18 07:35:13 2016
New Revision: 15908
Log:
Add test cases for: SHA1C SHA1H SHA1M SHA1P SHA1SU0 SHA1SU1 SHA256H2 SHA256H
SHA256SU0 SHA256SU1.
Increase the number of iterations from 10 to 50 for AESD AESE AESIMC AESMC.
Modified:
trunk/none/tests/arm64/fp_and_simd.c
trunk/none/tests/arm64/fp_and_simd.stdout.exp
Modified: trunk/none/tests/arm64/fp_and_simd.c
==============================================================================
--- trunk/none/tests/arm64/fp_and_simd.c (original)
+++ trunk/none/tests/arm64/fp_and_simd.c Mon Jul 18 07:35:13 2016
@@ -4548,7 +4548,6 @@
int main ( void )
{
- int i;
assert(sizeof(V128) == 16);
// ======================== FP ========================
@@ -7382,22 +7381,14 @@
// ======================== CRYPTO ========================
- // By default each test only runs once. That seems a bit too minimal
- // for the crypto ones. So here's an extra run multiplication factor.
- const int CRYPTO_ITER_MULTIPLIER = 10;
-
// aesd 16b (aes single round decryption)
// aese 16b (aes single round encryption)
// aesimc 16b (aes inverse mix columns)
// aesmc 16b (aes mix columns)
- if (1) for (i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
- test_aesd_16b_16b(TyNONE);
- if (1) for (i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
- test_aese_16b_16b(TyNONE);
- if (1) for (i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
- test_aesimc_16b_16b(TyNONE);
- if (1) for (i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
- test_aesmc_16b_16b(TyNONE);
+ if (1) DO50( test_aesd_16b_16b(TyNONE) );
+ if (1) DO50( test_aese_16b_16b(TyNONE) );
+ if (1) DO50( test_aesimc_16b_16b(TyNONE) );
+ if (1) DO50( test_aesmc_16b_16b(TyNONE) );
// sha1c q_s_4s
// sha1h s_s
@@ -7405,21 +7396,21 @@
// sha1p q_s_4s
// sha1su0 4s_4s_4s
// sha1su1 4s_4s
- if (0) test_sha1c_q_s_4s(TyNONE);
- if (0) test_sha1h_s_s(TyNONE);
- if (0) test_sha1m_q_s_4s(TyNONE);
- if (0) test_sha1p_q_s_4s(TyNONE);
- if (0) test_sha1su0_4s_4s_4s(TyNONE);
- if (0) test_sha1su1_4s_4s(TyNONE);
+ if (1) DO50( test_sha1c_q_s_4s(TyNONE) );
+ if (1) DO50( test_sha1h_s_s(TyNONE) );
+ if (1) DO50( test_sha1m_q_s_4s(TyNONE) );
+ if (1) DO50( test_sha1p_q_s_4s(TyNONE) );
+ if (1) DO50( test_sha1su0_4s_4s_4s(TyNONE) );
+ if (1) DO50( test_sha1su1_4s_4s(TyNONE) );
// sha256h2 q_q_4s
// sha256h q_q_4s
// sha256su0 4s_4s
// sha256su1 4s_4s_4s
- if (0) test_sha256h2_q_q_4s(TyNONE);
- if (0) test_sha256h_q_q_4s(TyNONE);
- if (0) test_sha256su0_4s_4s(TyNONE);
- if (0) test_sha256su1_4s_4s_4s(TyNONE);
+ if (1) DO50( test_sha256h2_q_q_4s(TyNONE) );
+ if (1) DO50( test_sha256h_q_q_4s(TyNONE) );
+ if (1) DO50( test_sha256su0_4s_4s(TyNONE) );
+ if (1) DO50( test_sha256su1_4s_4s_4s(TyNONE) );
return 0;
}
Modified: trunk/none/tests/arm64/fp_and_simd.stdout.exp
==============================================================================
--- trunk/none/tests/arm64/fp_and_simd.stdout.exp (original)
+++ trunk/none/tests/arm64/fp_and_simd.stdout.exp Mon Jul 18 07:35:13 2016
@@ -28804,33 +28804,706 @@
aesd v6.16b, v27.16b f1c1dfa3d544fa8282dbb866eb3ffabf 1fbf7c61e1fb553637d8cad404a8656e 61d51ba899851ec6288a6e3ed2f47151 1fbf7c61e1fb553637d8cad404a8656e fpsr=00000000
aesd v6.16b, v27.16b 63a2c958e164ebbf9c4236ea0219f31b 4d0558a11b2bc6b7ca346ecc3614c467 280ffa69c3f35ebf1489b223b992ac01 4d0558a11b2bc6b7ca346ecc3614c467 fpsr=00000000
aesd v6.16b, v27.16b a809c00f4a7ae2a0fdf11394aa6f0600 e6c8191bcaca96943cd14b23127395a0 9a54ca9bb6c45e283add2220ddfce547 e6c8191bcaca96943cd14b23127395a0 fpsr=00000000
-aese v6.16b, v27.16b 21d523a77167400406cab144441f944c 4ae71eaf4fb825acee8fc0b7f7a538f9 b26e91309bf427c26d234d0d7f9ea3d5 4ae71eaf4fb825acee8fc0b7f7a538f9 fpsr=00000000
-aese v6.16b, v27.16b 2de55201b50b64cd16ab70da2f0afce0 da44c73d09d5d2e13f4d2e6a458a0e52 658e89eba5cd2a7102324ee7681d5837 da44c73d09d5d2e13f4d2e6a458a0e52 fpsr=00000000
-aese v6.16b, v27.16b 2c1aaefe7646afda8e76af36cb0f9f9b f5be75a45901fd128fedf41a5d01768b 15141ebe7cabb9e89049007135a039ca f5be75a45901fd128fedf41a5d01768b fpsr=00000000
-aese v6.16b, v27.16b 7f54967c15f8800acd09ce377910db5f fb3487c69e1b061e3f4e72a89eecd084 3da02bf489b082fa94d044db5f1165b9 fb3487c69e1b061e3f4e72a89eecd084 fpsr=00000000
-aese v6.16b, v27.16b 85736a5cf101373e33452dbf98ec130b 4d875d8138044ee6ae4f08f468297d1c dd679fc15ea69a618cbfb6b3e86b3ff0 4d875d8138044ee6ae4f08f468297d1c fpsr=00000000
-aese v6.16b, v27.16b 9e578b7e6a403556210a2dac8882a47e 4b9758b7889d344a3dd118de1c99dc34 98b9bcdd9caf669c22ba7c4003c196d6 4b9758b7889d344a3dd118de1c99dc34 fpsr=00000000
-aese v6.16b, v27.16b 2be058c1e196d933f6382ee0aab3f099 5344d746edc4192a4bb4ff46191c4ead fe64ae177a7973d46d49ba24bc003e18 5344d746edc4192a4bb4ff46191c4ead fpsr=00000000
-aese v6.16b, v27.16b 8bee3107b5e483b213af8e395d5f573d c76e3b0fc85a5c6638d81f0bc0923265 fff54d30f1bd67485ecd9e2329ae816a c76e3b0fc85a5c6638d81f0bc0923265 fpsr=00000000
-aese v6.16b, v27.16b 1f60772e460894b6d74faf9802663748 07f5e3f2783f5dde651dd70f70dbe83d b2009e86377a2245402add88ad9abc9d 07f5e3f2783f5dde651dd70f70dbe83d fpsr=00000000
-aese v6.16b, v27.16b 45188918f5e36b1ea2f7f1dcf8a8f39b 71b82fcf5d527d723163873089d6d115 c222930edcf32450a3e047ce18c83819 71b82fcf5d527d723163873089d6d115 fpsr=00000000
-aesimc v6.16b, v27.16b 60f4c8a3225569c9d589b3e79f05e815 68998085d8751b01fd8a904f6c654ccd 31052aea28879e86b2c2944c11453ae6 68998085d8751b01fd8a904f6c654ccd fpsr=00000000
-aesimc v6.16b, v27.16b cdd593b02b3dec99cfe35598585d7898 497635f64887986d2871524c7866b944 9a6305009e763ae85a7eaecd93688f97 497635f64887986d2871524c7866b944 fpsr=00000000
-aesimc v6.16b, v27.16b ee9b4a1f727d576cf0e637ce828f0203 7630ae000d67539412f92b070eba795c 3e952d6ef5e0ea527944d52f180956d6 7630ae000d67539412f92b070eba795c fpsr=00000000
-aesimc v6.16b, v27.16b 23264ed057f407239972ba6b7e7de735 4ea84c8588f6ac571b037d608c41ebf3 8787dbf47c7949c943892fe0d219041a 4ea84c8588f6ac571b037d608c41ebf3 fpsr=00000000
-aesimc v6.16b, v27.16b cb56fea238815e9e29673e4daa05860f 32bb6f6318140396a46da83755db70ea 3e3e72f74e0f7ca47947d9b110ac1db5 32bb6f6318140396a46da83755db70ea fpsr=00000000
-aesimc v6.16b, v27.16b 460abb777805bcbd00a5215569083f71 814c757b1da1b9310d180b6bc6686721 12907b3a6c3ba0c32915c58c48f9227b 814c757b1da1b9310d180b6bc6686721 fpsr=00000000
-aesimc v6.16b, v27.16b f424e42e746080607f0bc5631866733c 9b3ac0adf87d2e08b4e406de41c83079 76ffaeebba6f31473a08833974a99e83 9b3ac0adf87d2e08b4e406de41c83079 fpsr=00000000
-aesimc v6.16b, v27.16b 3682d9a68e720a67067b8a5719ff814d e165afd90888c1fafbb0f96e25db2ccf 919320d0ea544e4ba41505683b9908b7 e165afd90888c1fafbb0f96e25db2ccf fpsr=00000000
-aesimc v6.16b, v27.16b 6c05fbc0251bbab1f3d3cf11ccb3c987 b2aca3deaea1d2e9425e45fcd380ba06 7815afa1440b502bc32295d10bdea79d b2aca3deaea1d2e9425e45fcd380ba06 fpsr=00000000
-aesimc v6.16b, v27.16b f48da95c9a3bf120a8f5f4708f61acc9 6ff0fb9e49aac1b3e8cc4968aa993afd 9b1de09cc56674466c0fc7a1676104f6 6ff0fb9e49aac1b3e8cc4968aa993afd fpsr=00000000
-aesmc v6.16b, v27.16b 30fa435a4cb20e9285bf5956c4eb89f2 771218f73981ef394ddc66920b040d93 e65286b857845de08d806c04b18b8e25 771218f73981ef394ddc66920b040d93 fpsr=00000000
-aesmc v6.16b, v27.16b 2af058cadf07bb5bd26cfb5a54a292aa 8da508d99c81ec6f2bc5ac931bae0d0e dc0cb099ff25a8ec91d3af3c8769e6be 8da508d99c81ec6f2bc5ac931bae0d0e fpsr=00000000
-aesmc v6.16b, v27.16b e96b1ef89a1d86f9d65d69a0e8532a20 ed42b59f0c84ce7fcea9779b8f0ee08f 8c82c54ed3b6633fefec5bd361f9c9bf ed42b59f0c84ce7fcea9779b8f0ee08f fpsr=00000000
-aesmc v6.16b, v27.16b 1363c75fcba1aff3b98f0e4324f734d6 51541fd8086f65a2e8c65239c5da7d08 9a9c4b8fe701d19714df24aa2e8e4288 51541fd8086f65a2e8c65239c5da7d08 fpsr=00000000
-aesmc v6.16b, v27.16b 18bba562f32113bad9fc9d4d1cf04559 edbb5450e210bfa0636ed3536fcefb29 de45c30a8b0217738ef93fc590e4e2e5 edbb5450e210bfa0636ed3536fcefb29 fpsr=00000000
-aesmc v6.16b, v27.16b 075ffc9cdbded89459b649b57785a713 504f4555819aa491ea5603b2501943f1 557e5e7a8f82f6d55738a4c6f2700c75 504f4555819aa491ea5603b2501943f1 fpsr=00000000
-aesmc v6.16b, v27.16b dd1059319baa20f37ecfc98578bf954d f37ed68061f18e9e5a3eabc01f1e79f2 cea446f7044af03e7af9951954963d75 f37ed68061f18e9e5a3eabc01f1e79f2 fpsr=00000000
-aesmc v6.16b, v27.16b 4a92530d7e9e5eb0f1cf93555fffa9da 4f2b9966be5424d760f6b995600539c3 86787d187582dd332b7b9d77a250deb3 4f2b9966be5424d760f6b995600539c3 fpsr=00000000
-aesmc v6.16b, v27.16b b56b1ddc388375a510e91c4f709a338b de707d888fd16358600e91cc74bad158 296c3c225f08794b10e187456b7a4016 de707d888fd16358600e91cc74bad158 fpsr=00000000
-aesmc v6.16b, v27.16b 92e993cdf07e325e166ca690b3d078e3 7752e50575dda055df864181d3827c4e 56dd551b68cb07f9faad4d839143f849 7752e50575dda055df864181d3827c4e fpsr=00000000
+aesd v6.16b, v27.16b 21d523a77167400406cab144441f944c 4ae71eaf4fb825acee8fc0b7f7a538f9 4b68bcbf05c02c6fd1a1aa7ec8ef8bd2 4ae71eaf4fb825acee8fc0b7f7a538f9 fpsr=00000000
+aesd v6.16b, v27.16b 2de55201b50b64cd16ab70da2f0afce0 da44c73d09d5d2e13f4d2e6a458a0e52 58f5796d263a9d4278f104fc4c9cad3e da44c73d09d5d2e13f4d2e6a458a0e52 fpsr=00000000
+aesd v6.16b, v27.16b 2c1aaefe7646afda8e76af36cb0f9f9b f5be75a45901fd128fedf41a5d01768b 35e84846e5d757b14e1deb4209169f7c f5be75a45901fd128fedf41a5d01768b fpsr=00000000
+aesd v6.16b, v27.16b 7f54967c15f8800acd09ce377910db5f fb3487c69e1b061e3f4e72a89eecd084 b016dcc04f55789bce909e6e044de39f fb3487c69e1b061e3f4e72a89eecd084 fpsr=00000000
+aesd v6.16b, v27.16b 85736a5cf101373e33452dbf98ec130b 4d875d8138044ee6ae4f08f468297d1c 17a3afc9b107c22d12ba45cc7536b287 4d875d8138044ee6ae4f08f468297d1c fpsr=00000000
+aesd v6.16b, v27.16b 9e578b7e6a403556210a2dac8882a47e 4b9758b7889d344a3dd118de1c99dc34 e79f0912b544d9c43b1fc11ec4c9a95c 4b9758b7889d344a3dd118de1c99dc34 fpsr=00000000
+aesd v6.16b, v27.16b 2be058c1e196d933f6382ee0aab3f099 5344d746edc4192a4bb4ff46191c4ead 4bf01feac11b518e811d5ac5cd487328 5344d746edc4192a4bb4ff46191c4ead fpsr=00000000
+aesd v6.16b, v27.16b 8bee3107b5e483b213af8e395d5f573d c76e3b0fc85a5c6638d81f0bc0923265 7502efbf5d80ac19133abca10b5aa35e c76e3b0fc85a5c6638d81f0bc0923265 fpsr=00000000
+aesd v6.16b, v27.16b 1f60772e460894b6d74faf9802663748 07f5e3f2783f5dde651dd70f70dbe83d 1e48129334cdc1f7d1adef853eb2e73f 07f5e3f2783f5dde651dd70f70dbe83d fpsr=00000000
+aesd v6.16b, v27.16b 45188918f5e36b1ea2f7f1dcf8a8f39b 71b82fcf5d527d723163873089d6d115 2ce7ff0d288a0fb86f4794832256c5e6 71b82fcf5d527d723163873089d6d115 fpsr=00000000
+aesd v6.16b, v27.16b 60f4c8a3225569c9d589b3e79f05e815 68998085d8751b01fd8a904f6c654ccd 7ed51e23bf9032b114b31d6fee54d42d 68998085d8751b01fd8a904f6c654ccd fpsr=00000000
+aesd v6.16b, v27.16b cdd593b02b3dec99cfe35598585d7898 497635f64887986d2871524c7866b944 5474ca984f4938ba0071dd19b0c0c593 497635f64887986d2871524c7866b944 fpsr=00000000
+aesd v6.16b, v27.16b ee9b4a1f727d576cf0e637ce828f0203 7630ae000d67539412f92b070eba795c f0cb30cbe2d9c4e16b0e03123b43ae84 7630ae000d67539412f92b070eba795c fpsr=00000000
+aesd v6.16b, v27.16b 23264ed057f407239972ba6b7e7de735 4ea84c8588f6ac571b037d608c41ebf3 042c0eedb36d31caefe6819e116a6ac7 4ea84c8588f6ac571b037d608c41ebf3 fpsr=00000000
+aesd v6.16b, v27.16b cb56fea238815e9e29673e4daa05860f 32bb6f6318140396a46da83755db70ea 7da38ddd699c35bf5453d6bdb4adac2a 32bb6f6318140396a46da83755db70ea fpsr=00000000
+aesd v6.16b, v27.16b 460abb777805bcbd00a5215569083f71 814c757b1da1b9310d180b6bc6686721 1bcd3681319095f0bc985ed1f31dec6c 814c757b1da1b9310d180b6bc6686721 fpsr=00000000
+aesd v6.16b, v27.16b f424e42e746080607f0bc5631866733c 9b3ac0adf87d2e08b4e406de41c83079 1561be4106be33f7f0e964cd59dea668 9b3ac0adf87d2e08b4e406de41c83079 fpsr=00000000
+aesd v6.16b, v27.16b 3682d9a68e720a67067b8a5719ff814d e165afd90888c1fafbb0f96e25db2ccf 6d59596b0da68f75dcb0185b21140f11 e165afd90888c1fafbb0f96e25db2ccf fpsr=00000000
+aesd v6.16b, v27.16b 6c05fbc0251bbab1f3d3cf11ccb3c987 b2aca3deaea1d2e9425e45fcd380ba06 cbb4f7e99c66cf5eceb78f5356c05e91 b2aca3deaea1d2e9425e45fcd380ba06 fpsr=00000000
+aesd v6.16b, v27.16b f48da95c9a3bf120a8f5f4708f61acc9 6ff0fb9e49aac1b3e8cc4968aa993afd c25b08a8e8e1cd22a913353472ac4828 6ff0fb9e49aac1b3e8cc4968aa993afd fpsr=00000000
+aesd v6.16b, v27.16b 30fa435a4cb20e9285bf5956c4eb89f2 771218f73981ef394ddc66920b040d93 5f00e0181661250e3fc84f88b16657d8 771218f73981ef394ddc66920b040d93 fpsr=00000000
+aesd v6.16b, v27.16b 2af058cadf07bb5bd26cfb5a54a292aa 8da508d99c81ec6f2bc5ac931bae0d0e 92b7da828981da2864ed6e1269dc6c1d 8da508d99c81ec6f2bc5ac931bae0d0e fpsr=00000000
+aesd v6.16b, v27.16b e96b1ef89a1d86f9d65d69a0e8532a20 ed42b59f0c84ce7fcea9779b8f0ee08f 0abad40a308de9dc354c104934f90e1b ed42b59f0c84ce7fcea9779b8f0ee08f fpsr=00000000
+aesd v6.16b, v27.16b 1363c75fcba1aff3b98f0e4324f734d6 51541fd8086f65a2e8c65239c5da7d08 e0a410eaf6faa77033b2a4bd70ec2d9c 51541fd8086f65a2e8c65239c5da7d08 fpsr=00000000
+aesd v6.16b, v27.16b 18bba562f32113bad9fc9d4d1cf04559 edbb5450e210bfa0636ed3536fcefb29 8f74aaa177d1b643e3525ae9c02e2bd0 edbb5450e210bfa0636ed3536fcefb29 fpsr=00000000
+aesd v6.16b, v27.16b 075ffc9cdbded89459b649b57785a713 504f4555819aa491ea5603b2501943f1 3da00112da1c5c36467cae384b86db3b 504f4555819aa491ea5603b2501943f1 fpsr=00000000
+aesd v6.16b, v27.16b dd1059319baa20f37ecfc98578bf954d f37ed68061f18e9e5a3eabc01f1e79f2 0a2bbe56c3f1abb314458368a65773f4 f37ed68061f18e9e5a3eabc01f1e79f2 fpsr=00000000
+aesd v6.16b, v27.16b 4a92530d7e9e5eb0f1cf93555fffa9da 4f2b9966be5424d760f6b995600539c3 255bbd053614950a1fdb961fac10108e 4f2b9966be5424d760f6b995600539c3 fpsr=00000000
+aesd v6.16b, v27.16b b56b1ddc388375a510e91c4f709a338b de707d888fd16358600e91cc74bad158 30b0fffd0554b42120443b41d04890a9 de707d888fd16358600e91cc74bad158 fpsr=00000000
+aesd v6.16b, v27.16b 92e993cdf07e325e166ca690b3d078e3 7752e50575dda055df864181d3827c4e 90bb74b12a48b09e67fe30e312710f18 7752e50575dda055df864181d3827c4e fpsr=00000000
+aesd v6.16b, v27.16b 44eb16c00571f5bb63388ff68782d8c3 7cb131bbd0583cae3d3f2a93da3d9983 8d38120376f4292fb546f8bc9d4c3d72 7cb131bbd0583cae3d3f2a93da3d9983 fpsr=00000000
+aesd v6.16b, v27.16b 28530594d83a1f9c582d39624d8eb10b 4d6dc28b01229743db18abe4ebcb88d8 c5d997cbbc6874efe5d15bdc413431a9 4d6dc28b01229743db18abe4ebcb88d8 fpsr=00000000
+aesd v6.16b, v27.16b a0ffc02ac7ba0fe0552a04b464d5669b 4865f854671b10f318f32552660caa2d 6ae5cb8ac8e57b82473727f565f17679 4865f854671b10f318f32552660caa2d fpsr=00000000
+aesd v6.16b, v27.16b 0bd0a76335d12669b8114fcb2c365453 d07b31f8632207a054aff7bea9df5e61 675a7be89feb9a12b90ea33f837e35a1 d07b31f8632207a054aff7bea9df5e61 fpsr=00000000
+aesd v6.16b, v27.16b caa71b1d7f5ec315e3c07a890693dd13 428dd0565419dc28f02b810816260456 7c3ccbcc97d2638b0b95e59182165968 428dd0565419dc28f02b810816260456 fpsr=00000000
+aesd v6.16b, v27.16b 3c627c39074346c53618e5cc51cb60ba 36eb1351c08c8ca54b99e1a6df4e0e6b e69110f7a367309031f24558135f0651 36eb1351c08c8ca54b99e1a6df4e0e6b fpsr=00000000
+aesd v6.16b, v27.16b 6928b9be9652a24cc6e73fb6ed8ba9ff 2a4129a4d9f77dbf4db3025708d21c52 2afdef4364158b7e92e4d2e0ce299618 2a4129a4d9f77dbf4db3025708d21c52 fpsr=00000000
+aesd v6.16b, v27.16b de71c48aa75553a8c0e632da166a6673 c02c9d891e69c40d6625d2bd93e19652 673385d5e9cea029db8d170ac56d157b c02c9d891e69c40d6625d2bd93e19652 fpsr=00000000
+aesd v6.16b, v27.16b be37b48f2ec7626099265e5be83c9627 5a8cccdff1c1c26ff6d0b3b9df5bd949 b2d6476cae0a53fbeffe923b06a5c145 5a8cccdff1c1c26ff6d0b3b9df5bd949 fpsr=00000000
+aesd v6.16b, v27.16b 695ae8ae89882f54b287221bc4e198fb 57411888b1e1d6c55e95042b4c1f4718 97396923d10c23ac7644ef0883e4174d 57411888b1e1d6c55e95042b4c1f4718 fpsr=00000000
+aese v6.16b, v27.16b 40bac0c61b781b646ae9dff80a38cdcf 182be162bfa760eefc5126f23b0e3f9f 496c89499005fd7ec78121676a9e9953 182be162bfa760eefc5126f23b0e3f9f fpsr=00000000
+aese v6.16b, v27.16b a2369db94177856f222bf4d318239483 fc2a864e7af5c1cc33e778f00b0922bd e24b4e6882e5af0a7d9c1b26581364b2 fc2a864e7af5c1cc33e778f00b0922bd fpsr=00000000
+aese v6.16b, v27.16b f0afde665d64ce57392fc18c50804ef7 631e672c42a9583d60365a041cee4f54 c0d47cd6cb9f560229c890c4dcbd140a 631e672c42a9583d60365a041cee4f54 fpsr=00000000
+aese v6.16b, v27.16b 8906e3accf2054fa0fd3a6031230590a aee6e4dc78a48522e61e2d0dcf9e2742 a9bdf3511ee4c561c1e13eabcc5f3d52 aee6e4dc78a48522e61e2d0dcf9e2742 fpsr=00000000
+aese v6.16b, v27.16b cd190d6cf58c7a3904f80418bd13189e 3c635e3e7bc6a95b227e50ec83f80869 1944ca00f7e9edaab2da66bfa1d62068 3c635e3e7bc6a95b227e50ec83f80869 fpsr=00000000
+aese v6.16b, v27.16b 1cc9bb8732869df4797e3babb109e891 6d753531abef23c87637248299de54a7 ee3b654e760e19eb3465aea5a3f9c005 6d753531abef23c87637248299de54a7 fpsr=00000000
+aese v6.16b, v27.16b d7f64edbe3ef1f0bce45aa9c4ef22bc4 a2fdc79769fe5449412a07ad702f6bdd 7ea8092973c1a72cb22bb3c79d8295d4 a2fdc79769fe5449412a07ad702f6bdd fpsr=00000000
+aese v6.16b, v27.16b 5e7f25496aa7605e612db1caf5ae4017 3bd8764e14d59bbee4355c4e68caaceb f3adcec59743ede15e5c0f5f4d4055b0 3bd8764e14d59bbee4355c4e68caaceb fpsr=00000000
+aese v6.16b, v27.16b 1046a0b0268dbecc9516b016061d886a 96e9a2380d535807bd398044e19177b1 f11516c43464771f94798e00441d04b9 96e9a2380d535807bd398044e19177b1 fpsr=00000000
+aese v6.16b, v27.16b 4d2920f278839c37c7e00861df1e629d 150faa33b357ec032f15d5713d622d0f 1fe684789b107e1898f751ca6a48c14f 150faa33b357ec032f15d5713d622d0f fpsr=00000000
+aese v6.16b, v27.16b 750a04eebf67577d596a1989e2932f8f 172aee2066c2b69397abbbb4d91e2de4 3578778b8b5d8728e2b7f827aa063a7f 172aee2066c2b69397abbbb4d91e2de4 fpsr=00000000
+aese v6.16b, v27.16b fd19cedf8774169858da90ec17a5d712 fd2e982d2758730db83eadcf07934a2d e0695e89e105b12aca9a4d2663712775 fd2e982d2758730db83eadcf07934a2d fpsr=00000000
+aese v6.16b, v27.16b 26bdab4f754d6df0cf81b7fa56d78c77 56fbbb4e78c65f8d9d1ecef5155af893 d7db927c005dcaff1a5a2376513db669 56fbbb4e78c65f8d9d1ecef5155af893 fpsr=00000000
+aese v6.16b, v27.16b f3f7e552902d1a7c5e828dbef693abf4 eb5413380eb2f9f93050780a9d2569ca 0bb525029f4e42977f0a118daddbe6b2 eb5413380eb2f9f93050780a9d2569ca fpsr=00000000
+aese v6.16b, v27.16b c3a5dac739f47e1b64bb741858bb956a 1a1bfecc49fea131d3b20aedfed2fcb0 5101f92ba9f936e524ae9ee63567f357 1a1bfecc49fea131d3b20aedfed2fcb0 fpsr=00000000
+aese v6.16b, v27.16b f6a8ec8dcf81f8af420dcbe8dc2da9b7 452edfea8988b714e626e47d99421226 5af1ea8549a8c3ea6e44842a6d011581 452edfea8988b714e626e47d99421226 fpsr=00000000
+aese v6.16b, v27.16b eddf7b85b3b6e8175658f30ee0cb47bb cc6e13712f319c84c88a679bcd550a0c deb5e3bf0b0b45dcd8c8922afd1722a9 cc6e13712f319c84c88a679bcd550a0c fpsr=00000000
+randV128: 9984 calls, 10317 iters
+aese v6.16b, v27.16b 062ce68f4471af32037c4b6ac673d058 0ebbfc439bd9b060d9bff227faeb4441 9e2e224b5746a200eb88c0e330c256d4 0ebbfc439bd9b060d9bff227faeb4441 fpsr=00000000
+aese v6.16b, v27.16b a46e8d8ce293ace2a65833dbee06a36d 6bf5f93f2b60518779a5e50181e420a7 dd54ec6d9e98924da81454578a0df674 6bf5f93f2b60518779a5e50181e420a7 fpsr=00000000
+aese v6.16b, v27.16b 2584d059eefc4005a2ce0c43b76420d9 44fb6b4441a6e1da091ca109c120ff1c 79b59ea4621bea9e38d232d6efbe95a6 44fb6b4441a6e1da091ca109c120ff1c fpsr=00000000
+aese v6.16b, v27.16b e94f10d9c78cc97c54bc3580816da87e f8afb1333d8bc039e803851f1b7e4182 2d081e87657d326eb8e101db82c5e7b0 f8afb1333d8bc039e803851f1b7e4182 fpsr=00000000
+aese v6.16b, v27.16b 50b0adebce23aa271e040f73ac019a3a e7ef2bec7eee4d84773cf223eee045b7 e7079ec5f9f8440a2ccf9453a9bd545d e7ef2bec7eee4d84773cf223eee045b7 fpsr=00000000
+aese v6.16b, v27.16b bb85056e61a140e65f84f9fc99ff57ee 729c3a4f64b0e89b15a547f49a246b9c 6bfdebfdd6b975ff7bd4c230dd82ae40 729c3a4f64b0e89b15a547f49a246b9c fpsr=00000000
+aese v6.16b, v27.16b 89af7a44e3e5ed98781d53fba7493e7a f8973d3c4fb2f15e231fe4747f2b1311 9177d8bc39aaa0b461079c73a35ba97f f8973d3c4fb2f15e231fe4747f2b1311 fpsr=00000000
+aese v6.16b, v27.16b 1b0d6c4bb1d1111fc7af7d5037bdafbe 6b07214774db1d78622b6fe10ddd898b a65ff7fe06d0e3858067fec85167c996 6b07214774db1d78622b6fe10ddd898b fpsr=00000000
+aese v6.16b, v27.16b 76f2a134b6f1cf670cc778fc77026b2a 9679213d6a4586a079f7a65a13965e46 860496019d22cdc6433d3b24e18d1d50 9679213d6a4586a079f7a65a13965e46 fpsr=00000000
+aese v6.16b, v27.16b 2e12c1fef2ef646da7b42ec54992db8f 74d00d959e05d5cdb86b1e5a8a292eea 509ee67fc0ea4be02e25c8dbbe87044d 74d00d959e05d5cdb86b1e5a8a292eea fpsr=00000000
+aese v6.16b, v27.16b 620056d2b3ace79f3231adbcd4654d03 65ec462f70fd6bdd7d6836bfd3785755 2ecba25484a4ca2cc5ce647bc5d114b1 65ec462f70fd6bdd7d6836bfd3785755 fpsr=00000000
+aese v6.16b, v27.16b 719bbf915a07b9dd0c2055c1785a2168 caac2beb3e0ba7b12ace4e6a4d613b69 4328a2daf7e22250969a7262eafeaf7c caac2beb3e0ba7b12ace4e6a4d613b69 fpsr=00000000
+aese v6.16b, v27.16b bbc25c1945e23807966084b39653b89c 02f21da96b11e9291f7cc73b58c53a04 319c13e7a79083318b043ec4560d1a46 02f21da96b11e9291f7cc73b58c53a04 fpsr=00000000
+aese v6.16b, v27.16b a1568e4bd71bc7fd2fd09c748d2e7180 6e9d7b4854ed9224bb5400125484b207 ec5f2e7b22ace635351ffc338a42de17 6e9d7b4854ed9224bb5400125484b207 fpsr=00000000
+aese v6.16b, v27.16b 8237b4076d94c39f3751fce2beccadf4 6d8ca5a95b8001845e3559cfa27e0552 0543c2e4f93782af9cea25d8dffa0624 6d8ca5a95b8001845e3559cfa27e0552 fpsr=00000000
+aese v6.16b, v27.16b be452e2c692b8ecc0fc405de880dcbd8 5fa0fbaddfaa962869fe3352a29393c5 4e806a0c330b0369e5d9ad64f80c05a4 5fa0fbaddfaa962869fe3352a29393c5 fpsr=00000000
+aese v6.16b, v27.16b b6605d9c2ac18766160716494bd12b0c a5b9de32414ab2ef3b90ed7bb3a3bb3f 7f8860e4d840eca7413596237d3d0fc3 a5b9de32414ab2ef3b90ed7bb3a3bb3f fpsr=00000000
+aese v6.16b, v27.16b c968a13511360f4badfb900168f82e6f 9eb7ae19e042b5ba34cbe829358ddda2 a1040d71ee9d76a14c9ef4345b92bcbd 9eb7ae19e042b5ba34cbe829358ddda2 fpsr=00000000
+aese v6.16b, v27.16b 583d58d97d6a855c337fd2e63e6233e3 aa7aca411c71fd69b58f833d88335acc ef8cf94644d14f964ea0bcb989afd115 aa7aca411c71fd69b58f833d88335acc fpsr=00000000
+aese v6.16b, v27.16b c2bee466cf3c4a7908753cda2eee9a46 2ae2928c56b6ecdd1dbc1e980d73919f eedd2b87595e3849264a242c9b7e9335 2ae2928c56b6ecdd1dbc1e980d73919f fpsr=00000000
+aese v6.16b, v27.16b 67cda5bd658ebc828dbc2ebc977ec479 7dcf66d9edf2e2f3cc321a18232ee2f9 c419f74383532ea38d775849a21018cd 7dcf66d9edf2e2f3cc321a18232ee2f9 fpsr=00000000
+aese v6.16b, v27.16b a848f9bea23e3e572133096bd9f0105c 0420a70742053d8e23d1d69e2b44aebb e198ae56778d583589457be691e29e94 0420a70742053d8e23d1d69e2b44aebb fpsr=00000000
+aese v6.16b, v27.16b e4104349e32e2dd824bb2dc95525decf 1db7b4f8b4cf608d8278b20a849554c5 5b2e7ec824e768fc3e5ce32e99f8db67 1db7b4f8b4cf608d8278b20a849554c5 fpsr=00000000
+aese v6.16b, v27.16b 2b72ee8aa330a8cf47090f3b8e0134f6 67271c86c2e4e605cce14b456c3c8bb3 ef9b08fe3d27897498fc2ff329481b6e 67271c86c2e4e605cce14b456c3c8bb3 fpsr=00000000
+aese v6.16b, v27.16b 8b32b49e70087736d4624c13aa67af30 fca38dbdb5a56dc74a8868299b0da3a2 a687fe260b0212a1c781a280f595364f fca38dbdb5a56dc74a8868299b0da3a2 fpsr=00000000
+aese v6.16b, v27.16b 9fd766147a372ca08964ca7037a92452 dcfcc18ffd34334687cf9ccb53300e31 1762e514abee5c8e43f1c0ea1a7bb1fb dcfcc18ffd34334687cf9ccb53300e31 fpsr=00000000
+aese v6.16b, v27.16b c74165cc219c28eec4efe83495a5f43b 67121adafb729760e498490bf5862b3f 57f59e47b726d219d0ed0875e02832f2 67121adafb729760e498490bf5862b3f fpsr=00000000
+aese v6.16b, v27.16b 625010a5c619ca00e7e3063d253d7ecc fec5f77f0e40faf6c0c1cfc8e0ef5bad e8933f57ccb59442a62a04e6decbddef fec5f77f0e40faf6c0c1cfc8e0ef5bad fpsr=00000000
+aese v6.16b, v27.16b d0e3c881c88c72b65220856c474f22e6 00f5b95e967cbbe87b2b8de4754bfd5b 582b9e9ea5f2a3582347ddc4708c307a 00f5b95e967cbbe87b2b8de4754bfd5b fpsr=00000000
+aese v6.16b, v27.16b 71dceb3e87d681f06485c4a159bc4167 cd82bf57f4063a1576b6e33d137a7129 8fc304f9c9b420d9d658eade6570cc2f cd82bf57f4063a1576b6e33d137a7129 fpsr=00000000
+aese v6.16b, v27.16b a619dcbe64d7568e7df423bcbd643a30 c64b694a87c0d85f104131b51a5b18f7 11d593bf3c75d53e5c001901d0f0c9c6 c64b694a87c0d85f104131b51a5b18f7 fpsr=00000000
+aese v6.16b, v27.16b cf7bf8dfbf6f526ffe4b039dd2276e20 4a321817b089f4a4a9aed82aebd051a5 76d975e85b68e11f123b24a9978eb997 4a321817b089f4a4a9aed82aebd051a5 fpsr=00000000
+aese v6.16b, v27.16b 4ae2a182f67ed475466cc323f9e43b19 b9152b9dce40eec6a2db387de5b77c13 07a9a0c069ed7e6d9c6880580db20f67 b9152b9dce40eec6a2db387de5b77c13 fpsr=00000000
+aesimc v6.16b, v27.16b 792e37876be33c7eb535c430917d04fa 74d502be41c727a35aaaaf8e68f1fa20 cdce819f0f496d2913c25f5febdcff8b 74d502be41c727a35aaaaf8e68f1fa20 fpsr=00000000
+aesimc v6.16b, v27.16b bc3f18ce7e80eb6bac8765a2fbd026a2 db53fe586afcff1c32f99f3dd55e2aae 17316e6614966b9ca245dd5385c96427 db53fe586afcff1c32f99f3dd55e2aae fpsr=00000000
+aesimc v6.16b, v27.16b 72f5a6378d33401c8a42065a96be03f2 4c6d7e4ca8c0d41189a9686a8bde6d9b 0f201b2798cba55bd4e17166d2b769af 4c6d7e4ca8c0d41189a9686a8bde6d9b fpsr=00000000
+aesimc v6.16b, v27.16b fb3041a1fbde9b71b0460838c228fbca 2903e37a5cf30862bf9a68f4eb5122c8 d6f461f0dc7319735e75e072428a2bb3 2903e37a5cf30862bf9a68f4eb5122c8 fpsr=00000000
+aesimc v6.16b, v27.16b b7cf48ee255f5d4a7c72ca1cdfec6c0b d2f78cc2e575fbef35ac02bd5497a915 8f77079441d84c51efcc9491a59ea6e2 d2f78cc2e575fbef35ac02bd5497a915 fpsr=00000000
+aesimc v6.16b, v27.16b 07b41bfc6d97e58651a8ace64eebb892 a528d904a3250b974abf93a326906362 f17f2df397060b807d893504d97ae9fd a528d904a3250b974abf93a326906362 fpsr=00000000
+aesimc v6.16b, v27.16b 4bbd1bac326694078cc60f766f043f42 05752b20f6e59a3c5fb27d87c21baf8f 7954a1f7b8e0a548d308df1387a403d9 05752b20f6e59a3c5fb27d87c21baf8f fpsr=00000000
+aesimc v6.16b, v27.16b e1cba7ded5abc8ab8fad52aca01960fa 4fc0e1f53f9408bcd2671f49871aed7b 813e0226199e10885c144ce784f7f880 4fc0e1f53f9408bcd2671f49871aed7b fpsr=00000000
+aesimc v6.16b, v27.16b 2bbe1f72b548e454ba3dd66744087b99 e5e75b65de11b4f906bcdac9d56b7e08 f71a31e0dde7a810488addb63c491ca1 e5e75b65de11b4f906bcdac9d56b7e08 fpsr=00000000
+aesimc v6.16b, v27.16b 8976e448321b45e06b57fa88b8b3f101 26cbfa4e323dfed158920de70defc114 0c8f62b8c985452949e95cdcb66514f0 26cbfa4e323dfed158920de70defc114 fpsr=00000000
+aesimc v6.16b, v27.16b 59d35540ad064d3005d81ef05ef82110 734c1d919bf847252aca18838e861781 53374097a86e76b125a0e11fc0887ea8 734c1d919bf847252aca18838e861781 fpsr=00000000
+aesimc v6.16b, v27.16b feb4d23985e75c24e5a3a37d95b86ba7 2b4a250e7922eed5dc425c7cb910df2d 75afef7f1d284a1f88a46ffdbc186c93 2b4a250e7922eed5dc425c7cb910df2d fpsr=00000000
+aesimc v6.16b, v27.16b d5fbbc151b9fd19c6d97e810bed330a6 aea471a52d9b53c0ccda38b4ed6d79f9 9dc0e566198d2d9ce7733c32a3103784 aea471a52d9b53c0ccda38b4ed6d79f9 fpsr=00000000
+aesimc v6.16b, v27.16b 408673b2ce0e0c77fc934d893829cfed 5d3c61361643d7c85c740d098a7c46c5 e64bb62db4dfe1c0fe9cf7b9f9a9dffa 5d3c61361643d7c85c740d098a7c46c5 fpsr=00000000
+aesimc v6.16b, v27.16b 9e3655f1fe146d97f37933c7639aa85c 97f156a195f9d9cbecef3a5cf11fa570 a7135f7aa14a118482739e0a5b87799e 97f156a195f9d9cbecef3a5cf11fa570 fpsr=00000000
+aesimc v6.16b, v27.16b 50ecc4b30c9155dab127f9aca0061cd3 bda2afc5099fb9abdb2a1f8d8134f6dc f5eb0d6668b0cb971c2f1e4ef7c3a50e bda2afc5099fb9abdb2a1f8d8134f6dc fpsr=00000000
+aesimc v6.16b, v27.16b b5861fd657652421967e00164e4c8a31 2e30cc84d213d84689071d7c9a9c9ae8 143a5a225854ecbfc821999f87a26f3e 2e30cc84d213d84689071d7c9a9c9ae8 fpsr=00000000
+aesimc v6.16b, v27.16b 2ee4c73a3f6f384d035ea7e7cd4e5358 4a7b0ebc5137967d566493099d37f073 41df1805b141770a4e30c0168f09b01f 4a7b0ebc5137967d566493099d37f073 fpsr=00000000
+aesimc v6.16b, v27.16b 19e81bc12590f33c57a74efd7eead626 7263d54ee5e95130a322e114e9e5595e 1643be619a90f4933c1a96c439749fd9 7263d54ee5e95130a322e114e9e5595e fpsr=00000000
+aesimc v6.16b, v27.16b d9717c4a68a9b5cff3395639c001737c 05c87f1aef0a6b3fd021687cdf863489 57b3662a3c41c10dc93ba0b7778d4f51 05c87f1aef0a6b3fd021687cdf863489 fpsr=00000000
+aesimc v6.16b, v27.16b cb5e49b46998dce535f41e7bf4738b3a 638a6e00ce7a448a3c418723defae1d4 428e5a11df63a167936381a8af93b29f 638a6e00ce7a448a3c418723defae1d4 fpsr=00000000
+aesimc v6.16b, v27.16b 5191e2e0863ecb6080b706a379207d40 ed8801e0e2183af047629fe74621c11f a2315d4a20d19859d289b0b6d8113646 ed8801e0e2183af047629fe74621c11f fpsr=00000000
+aesimc v6.16b, v27.16b cae8a8af227bdf1f31636f91afe8aa6e 02a4999a8bc6af5351630fa978da334a 89f1439efe70a39c815aeca372aa9497 02a4999a8bc6af5351630fa978da334a fpsr=00000000
+aesimc v6.16b, v27.16b 9744faff9a2f7a01aad9b824f7aa70a4 02bc950d2a620391bb263749d3079835 7b24a0d9b343351ff81aa9a8afe01620 02bc950d2a620391bb263749d3079835 fpsr=00000000
+aesimc v6.16b, v27.16b 178538b15039fbe74bf7423eb04832c1 4eb1561b1fce958ce48978a7b7864ebf d19fb64aeeb6ef7f71be92eff49a9638 4eb1561b1fce958ce48978a7b7864ebf fpsr=00000000
+aesimc v6.16b, v27.16b aa8bc3a5a47bc3b1729e6cbd3ba04da7 46643aa2c8e8c5222d6d31a38538b8ca 630870a196080e5742e0e1910251ba26 46643aa2c8e8c5222d6d31a38538b8ca fpsr=00000000
+aesimc v6.16b, v27.16b 48b3a4838891f434f5b2c21d9dfd3334 7edfc4381afe34f6feb33985451dc240 afb4afe96c000e4401c93f0635921d60 7edfc4381afe34f6feb33985451dc240 fpsr=00000000
+aesimc v6.16b, v27.16b b67ef19ebca981a29c388cf45db521de 73497c08c0b579a1826a94497b821131 b12a22f762bd9ae8d1abade217dad4c0 73497c08c0b579a1826a94497b821131 fpsr=00000000
+aesimc v6.16b, v27.16b 3100fc6309c2421992aea89fda27f0f2 7794749d59f7277d6c1586526eaabe9f ee37f92ae7bb6ac227528c5476617785 7794749d59f7277d6c1586526eaabe9f fpsr=00000000
+aesimc v6.16b, v27.16b d50cc09d5758a4e426b121e8fa754e7d ced212e49d99e99e4886c3d254ee4378 3cc92f30964b04aa00372ec6b50abb85 ced212e49d99e99e4886c3d254ee4378 fpsr=00000000
+aesimc v6.16b, v27.16b b6d547c3818437207cc28f15a6075d6d 200f93cda4dee4707359677d7d91d185 cfa09e80d37b54129436e0721f0dd872 200f93cda4dee4707359677d7d91d185 fpsr=00000000
+randV128: 10240 calls, 10580 iters
+aesimc v6.16b, v27.16b 476bf72ac340e9c91743ea4a2d279a8f c0bd400f881de94f524f48da153ec7f4 ca002ed632cf35fbaa8cb51c71b5934f c0bd400f881de94f524f48da153ec7f4 fpsr=00000000
+aesimc v6.16b, v27.16b 19847f0098518dbedbafe6b5c5f01718 5cc09807b9650bbedc76898f37ffe791 ccc90e08458b25828e4b98f134ee83e7 5cc09807b9650bbedc76898f37ffe791 fpsr=00000000
+aesimc v6.16b, v27.16b f73a8b3082f12e2f1e7bbb9ea8cca501 9b584c9117b484617ef57bfabb4b7145 1022fbd7c1d0de89239e3285e736beab 9b584c9117b484617ef57bfabb4b7145 fpsr=00000000
+aesimc v6.16b, v27.16b 406d7b9ae2002efc4088c8e4339ba62b 8b8b774b9b2780cb831d9111d69440dd 0a618ed959d7b7ce1ae434d4d352e0be 8b8b774b9b2780cb831d9111d69440dd fpsr=00000000
+aesimc v6.16b, v27.16b 84c74ad9dce6f7c3887fef7266034475 e9bd93b0dfe1218669cf46081453804a 4ac3de2085275269fe401a4c4730d228 e9bd93b0dfe1218669cf46081453804a fpsr=00000000
+aesimc v6.16b, v27.16b ee5e5359038ab241b049323f4e2f4eb1 a21c027f88b991cc1d72a48eebb5a327 346d099345358498a92a9a5c0327e41a a21c027f88b991cc1d72a48eebb5a327 fpsr=00000000
+aesimc v6.16b, v27.16b 7b0a39ead7b444746feba54117664185 17882697f6902f7f02e60a81bb9a0854 8d94e0d72b509ed30588d3313c757541 17882697f6902f7f02e60a81bb9a0854 fpsr=00000000
+aesimc v6.16b, v27.16b a7e15eda8a465c7d750bd9c2e5e210b0 632cb1cf4c0a735b3c900ef47d6748c9 e7b15730adea4e67af883140f5f2ed71 632cb1cf4c0a735b3c900ef47d6748c9 fpsr=00000000
+aesimc v6.16b, v27.16b b3060b26a3bb77a7d8c17031c86c1a1d 2c8001e175baa063d9c53ed21d6e0a2d 0346b6bf4c1a81db4f90537ce35d5cb6 2c8001e175baa063d9c53ed21d6e0a2d fpsr=00000000
+aesimc v6.16b, v27.16b 9ad98c5ca1cee1dd8ae82fadc51a8679 6979ff159c80742f5f636ef5ef0f8638 9499ed1a257b435a3c9d585e7d90a81b 6979ff159c80742f5f636ef5ef0f8638 fpsr=00000000
+aesimc v6.16b, v27.16b bc38415ce561f8ffec5f76183bcab5a5 79f7084a203e4f9f2b4aff3e522b1ccb 36c4c4fa0654ee72ab9424bbf1ddf87a 79f7084a203e4f9f2b4aff3e522b1ccb fpsr=00000000
+aesimc v6.16b, v27.16b 7a058b06ce521fed5d08a6518a5e0681 bdd97e6262d290939f5a508da7a22dc6 ac5e9f1522eaadd672628d85a4fce95f bdd97e6262d290939f5a508da7a22dc6 fpsr=00000000
+aesimc v6.16b, v27.16b 331ec93abd83b3873dc11f3713b4daed 9400c03bc11d97ea1a72c1c24d541809 a0e52a000a91053fee4ae32cc241870c 9400c03bc11d97ea1a72c1c24d541809 fpsr=00000000
+aesimc v6.16b, v27.16b 47645cd811d216aced6b40ab35ad90c9 5e4d2fb69dffc486fd73b3bda4213e74 fc1c82e8effff6c6b28de758ac92b342 5e4d2fb69dffc486fd73b3bda4213e74 fpsr=00000000
+aesimc v6.16b, v27.16b 17b7a3c02a20a73ecce6698d502988f5 7c9e2ab356577845a73e855d0de9fee6 347b94a00fda59b0bfff1f1e7c5b6cb7 7c9e2ab356577845a73e855d0de9fee6 fpsr=00000000
+aesimc v6.16b, v27.16b 02f7fed1694dc71b3b12fabdc5082250 4dd411124d07120978b19884e78bb841 beeecd074d44b0e811cb404f8607e8fc 4dd411124d07120978b19884e78bb841 fpsr=00000000
+aesimc v6.16b, v27.16b 6903ceed2d39d52499cf541bf329bfbc 31cf45b3e2eef3b0d1ad4b1093e9cc63 ad8bc9e703948c541293c6602824c61f 31cf45b3e2eef3b0d1ad4b1093e9cc63 fpsr=00000000
+aesimc v6.16b, v27.16b abbd72f2d6c3323946fdd6873a6ebf17 896e257674eb7a1b1112fee270e19b2e 89b856d3dd6c347b9a1e4bd052d6f151 896e257674eb7a1b1112fee270e19b2e fpsr=00000000
+aesimc v6.16b, v27.16b b493113b63df082a99c012dade548580 dbf1d8fa34d7519911cf872de79078ac ddc1ceda9241a159fe34803ef7423523 dbf1d8fa34d7519911cf872de79078ac fpsr=00000000
+aesmc v6.16b, v27.16b 131d6ae10faafbbcc796e6d83d22e83a a64f531cbf23f560690bb28f126072f3 6f20cd2413094b58e19084aa3877a519 a64f531cbf23f560690bb28f126072f3 fpsr=00000000
+aesmc v6.16b, v27.16b 05eb9049d92cb5b3fe76dabcee2b273c 9bea7238809eb8436047d60fa7e39d3a fd336297f847114b40f711586588828c 9bea7238809eb8436047d60fa7e39d3a fpsr=00000000
+aesmc v6.16b, v27.16b eadee154214596ee9b3e4f66514f9f66 1ca1962ed527f9215665528e04f85c61 7dc5fd400cf274a012ecd3c20fdaceda 1ca1962ed527f9215665528e04f85c61 fpsr=00000000
+aesmc v6.16b, v27.16b 23d6bfe045d5fd4c00cfa4b6c46db297 89551edd20a019dbac4386ea8b810c47 3ee9975f8ff93206a30594b149d44c90 89551edd20a019dbac4386ea8b810c47 fpsr=00000000
+aesmc v6.16b, v27.16b 0fb38acea7bc4aae8d0a3a8baa67bfb1 41e76a27c1e77752c1c3d3049c5c0fce 665b8056ffa84f1b8512266439c6a856 41e76a27c1e77752c1c3d3049c5c0fce fpsr=00000000
+aesmc v6.16b, v27.16b 0e55a0fda7d9def4a0cd70c6601b2792 a435dbea16dd7364f6c398bb966ac4d4 98acbc282e8ce8967abf38ebfe656f18 a435dbea16dd7364f6c398bb966ac4d4 fpsr=00000000
+aesmc v6.16b, v27.16b 1320d00781636ef2aa2435f1d98b8c3a 0313746b1f2601730e0cd0282c220e25 dc3cb55a8c1f04dcb8f289391b1b7356 0313746b1f2601730e0cd0282c220e25 fpsr=00000000
+aesmc v6.16b, v27.16b ed88aa5e6256c7dc3dc60b85c59fc6e1 17950d93cc81c987d899dab7125edb8e 18963aa859185a182a37704128dfd33d 17950d93cc81c987d899dab7125edb8e fpsr=00000000
+aesmc v6.16b, v27.16b 924cc8cf1899de0110897956bb86d2a7 8f6cc30e66a3a78f7a3f56ba1ae4d3cf b89fa8a142df4232481c2dd049e15f15 8f6cc30e66a3a78f7a3f56ba1ae4d3cf fpsr=00000000
+aesmc v6.16b, v27.16b 634e8a3a030b1443824de0451b1f116c c978f6ba4d6bfb6a53dea114a29655c8 d2fc0cdfb49077e4e5e7675ddf576140 c978f6ba4d6bfb6a53dea114a29655c8 fpsr=00000000
+aesmc v6.16b, v27.16b bf6c517f848cc881f3f19f33434ce212 27990578e2ba26fac3561da40c52c259 5a3de541568e81dd214ba7e1632b3cb1 27990578e2ba26fac3561da40c52c259 fpsr=00000000
+aesmc v6.16b, v27.16b 07887c7dfafb5a9ac45716fe95eba578 08ae50288571871d2b872a49b8f97962 96276906c0ec1e5c200ba4404d21380e 08ae50288571871d2b872a49b8f97962 fpsr=00000000
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+aesmc v6.16b, v27.16b d656943ae78ed41641f6a755fb65ab0d 301558db14ceabf1f3027f3a7342bdb3 5bf9646045e1e1c5ce4f3104d71f6790 301558db14ceabf1f3027f3a7342bdb3 fpsr=00000000
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+aesmc v6.16b, v27.16b 03eabab4de30073c7c8a01f4e7141c97 184607206c264312e4d54cf61928dd6b 1183fc178ba992ab4b3cee127acdab9b 184607206c264312e4d54cf61928dd6b fpsr=00000000
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+aesmc v6.16b, v27.16b f3effa9dd1ae772de62e4f4c15f95af6 cdf2373324636999fed7bd984913d58e 11b79d00f25acad53e8965dedda64339 cdf2373324636999fed7bd984913d58e fpsr=00000000
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+aesmc v6.16b, v27.16b 8cab0f89e97c2d28b6b280e5c91bb65e d2bb04d94d57b480330a903e68dc1014 70ddd5cce24d47c6beef28ee201f23ac d2bb04d94d57b480330a903e68dc1014 fpsr=00000000
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+aesmc v6.16b, v27.16b 8386fcb2e453a1263f997f54261c505f 8c1e3a2bd87f71f45f74df98437b8a1e 5aa2f18aa2084fc7a64efe7a55a7df81 8c1e3a2bd87f71f45f74df98437b8a1e fpsr=00000000
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+aesmc v6.16b, v27.16b f10fdbf281f172f57b92f7ce5b41cde7 1300c921d6a8acdba70bdc6c8d2f0522 8cddbb11c55dad3c3654750b4df5d4e9 1300c921d6a8acdba70bdc6c8d2f0522 fpsr=00000000
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+randV128: 10496 calls, 10841 iters
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[truncated message content] |
|
From: <sv...@va...> - 2016-07-18 06:34:00
|
Author: sewardj
Date: Mon Jul 18 07:33:52 2016
New Revision: 3225
Log:
Implement: SHA1C SHA1H SHA1M SHA1P SHA1SU0 SHA1SU1 SHA256H2 SHA256H
SHA256SU0 SHA256SU1. Fixes #357338.
Modified:
trunk/priv/guest_arm64_defs.h
trunk/priv/guest_arm64_helpers.c
trunk/priv/guest_arm64_toIR.c
Modified: trunk/priv/guest_arm64_defs.h
==============================================================================
--- trunk/priv/guest_arm64_defs.h (original)
+++ trunk/priv/guest_arm64_defs.h Mon Jul 18 07:33:52 2016
@@ -124,6 +124,38 @@
extern void arm64g_dirtyhelper_AESIMC ( /*OUT*/V128* res,
ULong argHi, ULong argLo );
+extern
+void arm64g_dirtyhelper_SHA1C ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo, ULong mHi, ULong mLo );
+extern
+void arm64g_dirtyhelper_SHA1H ( /*OUT*/V128* res,
+ ULong nHi, ULong nLo );
+extern
+void arm64g_dirtyhelper_SHA1M ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo, ULong mHi, ULong mLo );
+extern
+void arm64g_dirtyhelper_SHA1P ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo, ULong mHi, ULong mLo );
+extern
+void arm64g_dirtyhelper_SHA1SU0 ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo, ULong mHi, ULong mLo );
+extern
+void arm64g_dirtyhelper_SHA1SU1 ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo );
+extern
+void arm64g_dirtyhelper_SHA256H2 ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo, ULong mHi, ULong mLo );
+extern
+void arm64g_dirtyhelper_SHA256H ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo, ULong mHi, ULong mLo );
+extern
+void arm64g_dirtyhelper_SHA256SU0 ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo );
+extern
+void arm64g_dirtyhelper_SHA256SU1 ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo,
+ ULong mHi, ULong mLo );
+
/*---------------------------------------------------------*/
/*--- Condition code stuff ---*/
Modified: trunk/priv/guest_arm64_helpers.c
==============================================================================
--- trunk/priv/guest_arm64_helpers.c (original)
+++ trunk/priv/guest_arm64_helpers.c Mon Jul 18 07:33:52 2016
@@ -692,6 +692,10 @@
}
+/*---------------------------------------------------------------*/
+/*--- Crypto instruction helpers ---*/
+/*---------------------------------------------------------------*/
+
/* DIRTY HELPERS for doing AES support:
* AESE (SubBytes, then ShiftRows)
* AESD (InvShiftRows, then InvSubBytes)
@@ -916,6 +920,254 @@
}
+/* DIRTY HELPERS for SHA instruction support. As with the AES helpers
+ above, these are actually pure functions and are only dirty because
+ clean helpers can't return a V128. */
+
+static inline UInt ROL32 ( UInt x, UInt sh ) {
+ vassert(sh > 0 && sh < 32);
+ return (x << sh) | (x >> (32 - sh));
+}
+
+static inline UInt ROR32 ( UInt x, UInt sh ) {
+ vassert(sh > 0 && sh < 32);
+ return (x >> sh) | (x << (32 - sh));
+}
+
+static inline UInt SHAchoose ( UInt x, UInt y, UInt z ) {
+ return ((y ^ z) & x) ^ z;
+}
+
+static inline UInt SHAmajority ( UInt x, UInt y, UInt z ) {
+ return (x & y) | ((x | y) & z);
+}
+
+static inline UInt SHAparity ( UInt x, UInt y, UInt z ) {
+ return x ^ y ^ z;
+}
+
+static inline UInt SHAhashSIGMA0 ( UInt x ) {
+ return ROR32(x, 2) ^ ROR32(x, 13) ^ ROR32(x, 22);
+}
+
+static inline UInt SHAhashSIGMA1 ( UInt x ) {
+ return ROR32(x, 6) ^ ROR32(x, 11) ^ ROR32(x, 25);
+}
+
+static void SHA256hash ( /*MOD*/V128* X, /*MOD*/V128* Y, const V128* W )
+{
+ UInt e;
+ for (e = 0; e <= 3; e++) {
+ UInt chs = SHAchoose(Y->w32[0], Y->w32[1], Y->w32[2]);
+ UInt maj = SHAmajority(X->w32[0], X->w32[1], X->w32[2]);
+ UInt t = Y->w32[3] + SHAhashSIGMA1(Y->w32[0]) + chs + W->w32[e];
+ X->w32[3] = t + X->w32[3];
+ Y->w32[3] = t + SHAhashSIGMA0(X->w32[0]) + maj;
+ UInt ts = Y->w32[3];
+ Y->w32[3] = Y->w32[2];
+ Y->w32[2] = Y->w32[1];
+ Y->w32[1] = Y->w32[0];
+ Y->w32[0] = X->w32[3];
+ X->w32[3] = X->w32[2];
+ X->w32[2] = X->w32[1];
+ X->w32[1] = X->w32[0];
+ X->w32[0] = ts;
+ }
+}
+
+/* CALLED FROM GENERATED CODE */
+void arm64g_dirtyhelper_SHA1C ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo, ULong mHi, ULong mLo )
+{
+ vassert(nHi == 0);
+ vassert((nLo >> 32) == 0);
+ V128 X; X.w64[1] = dHi; X.w64[0] = dLo;
+ UInt Y; Y = (UInt)nLo;
+ V128 W; W.w64[1] = mHi; W.w64[0] = mLo;
+ UInt e;
+ for (e = 0; e <= 3; e++) {
+ UInt t = SHAchoose(X.w32[1], X.w32[2], X.w32[3]);
+ Y = Y + ROL32(X.w32[0], 5) + t + W.w32[e];
+ X.w32[1] = ROL32(X.w32[1], 30);
+ UInt oldY = Y;
+ Y = X.w32[3];
+ X.w32[3] = X.w32[2];
+ X.w32[2] = X.w32[1];
+ X.w32[1] = X.w32[0];
+ X.w32[0] = oldY;
+ }
+ res->w64[1] = X.w64[1];
+ res->w64[0] = X.w64[0];
+}
+
+/* CALLED FROM GENERATED CODE */
+void arm64g_dirtyhelper_SHA1H ( /*OUT*/V128* res, ULong nHi, ULong nLo )
+{
+ vassert(nHi == 0);
+ vassert((nLo >> 32) == 0);
+ res->w32[3] = res->w32[2] = res->w32[1] = 0;
+ res->w32[0] = ROL32((UInt)nLo, 30);
+}
+
+/* CALLED FROM GENERATED CODE */
+void arm64g_dirtyhelper_SHA1M ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo, ULong mHi, ULong mLo )
+{
+ vassert(nHi == 0);
+ vassert((nLo >> 32) == 0);
+ V128 X; X.w64[1] = dHi; X.w64[0] = dLo;
+ UInt Y; Y = (UInt)nLo;
+ V128 W; W.w64[1] = mHi; W.w64[0] = mLo;
+ UInt e;
+ for (e = 0; e <= 3; e++) {
+ UInt t = SHAmajority(X.w32[1], X.w32[2], X.w32[3]);
+ Y = Y + ROL32(X.w32[0], 5) + t + W.w32[e];
+ X.w32[1] = ROL32(X.w32[1], 30);
+ UInt oldY = Y;
+ Y = X.w32[3];
+ X.w32[3] = X.w32[2];
+ X.w32[2] = X.w32[1];
+ X.w32[1] = X.w32[0];
+ X.w32[0] = oldY;
+ }
+ res->w64[1] = X.w64[1];
+ res->w64[0] = X.w64[0];
+}
+
+/* CALLED FROM GENERATED CODE */
+void arm64g_dirtyhelper_SHA1P ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo, ULong mHi, ULong mLo )
+{
+ vassert(nHi == 0);
+ vassert((nLo >> 32) == 0);
+ V128 X; X.w64[1] = dHi; X.w64[0] = dLo;
+ UInt Y; Y = (UInt)nLo;
+ V128 W; W.w64[1] = mHi; W.w64[0] = mLo;
+ UInt e;
+ for (e = 0; e <= 3; e++) {
+ UInt t = SHAparity(X.w32[1], X.w32[2], X.w32[3]);
+ Y = Y + ROL32(X.w32[0], 5) + t + W.w32[e];
+ X.w32[1] = ROL32(X.w32[1], 30);
+ UInt oldY = Y;
+ Y = X.w32[3];
+ X.w32[3] = X.w32[2];
+ X.w32[2] = X.w32[1];
+ X.w32[1] = X.w32[0];
+ X.w32[0] = oldY;
+ }
+ res->w64[1] = X.w64[1];
+ res->w64[0] = X.w64[0];
+}
+
+/* CALLED FROM GENERATED CODE */
+void arm64g_dirtyhelper_SHA1SU0 ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo, ULong mHi, ULong mLo )
+{
+ res->w64[1] = nLo;
+ res->w64[0] = dHi;
+ res->w64[1] ^= dHi ^ mHi;
+ res->w64[0] ^= dLo ^ mLo;
+}
+
+/* CALLED FROM GENERATED CODE */
+void arm64g_dirtyhelper_SHA1SU1 ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo )
+{
+ /* This computes "T = Vd ^ (Vn >>u 32)" */
+ V128 T; T.w64[1] = nHi; T.w64[0] = nLo;
+ T.w32[0] = T.w32[1];
+ T.w32[1] = T.w32[2];
+ T.w32[2] = T.w32[3];
+ T.w32[3] = 0;
+ T.w64[1] ^= dHi;
+ T.w64[0] ^= dLo;
+ /* */
+ res->w32[0] = ROL32(T.w32[0], 1);
+ res->w32[1] = ROL32(T.w32[1], 1);
+ res->w32[2] = ROL32(T.w32[2], 1);
+ res->w32[3] = ROL32(T.w32[3], 1) ^ ROL32(T.w32[0], 2);
+}
+
+/* CALLED FROM GENERATED CODE */
+void arm64g_dirtyhelper_SHA256H2 ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo, ULong mHi, ULong mLo )
+{
+ V128 X; X.w64[1] = nHi; X.w64[0] = nLo;
+ V128 Y; Y.w64[1] = dHi; Y.w64[0] = dLo;
+ V128 W; W.w64[1] = mHi; W.w64[0] = mLo;
+ SHA256hash(&X, &Y, &W);
+ res->w64[1] = Y.w64[1];
+ res->w64[0] = Y.w64[0];
+}
+
+/* CALLED FROM GENERATED CODE */
+void arm64g_dirtyhelper_SHA256H ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo, ULong mHi, ULong mLo )
+{
+ V128 X; X.w64[1] = dHi; X.w64[0] = dLo;
+ V128 Y; Y.w64[1] = nHi; Y.w64[0] = nLo;
+ V128 W; W.w64[1] = mHi; W.w64[0] = mLo;
+ SHA256hash(&X, &Y, &W);
+ res->w64[1] = X.w64[1];
+ res->w64[0] = X.w64[0];
+}
+
+/* CALLED FROM GENERATED CODE */
+void arm64g_dirtyhelper_SHA256SU0 ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo )
+
+{
+ res->w64[1] = res->w64[0] = 0;
+ V128 op1; op1.w64[1] = dHi; op1.w64[0] = dLo;
+ V128 op2; op2.w64[1] = nHi; op2.w64[0] = nLo;
+ V128 T;
+ T.w32[3] = op2.w32[0];
+ T.w32[2] = op1.w32[3];
+ T.w32[1] = op1.w32[2];
+ T.w32[0] = op1.w32[1];
+ UInt e;
+ for (e = 0; e <= 3; e++) {
+ UInt elt = T.w32[e];
+ elt = ROR32(elt, 7) ^ ROR32(elt, 18) ^ (elt >> 3);
+ res->w32[e] = elt + op1.w32[e];
+ }
+}
+
+/* CALLED FROM GENERATED CODE */
+void arm64g_dirtyhelper_SHA256SU1 ( /*OUT*/V128* res, ULong dHi, ULong dLo,
+ ULong nHi, ULong nLo,
+ ULong mHi, ULong mLo )
+{
+ res->w64[0] = res->w64[1] = 0;
+ V128 op1; op1.w64[1] = dHi; op1.w64[0] = dLo;
+ V128 op2; op2.w64[1] = nHi; op2.w64[0] = nLo;
+ V128 op3; op3.w64[1] = mHi; op3.w64[0] = mLo;
+ V128 T0;
+ T0.w32[3] = op3.w32[0];
+ T0.w32[2] = op2.w32[3];
+ T0.w32[1] = op2.w32[2];
+ T0.w32[0] = op2.w32[1];
+ UInt T1[2];
+ UInt e;
+ T1[1] = op3.w32[3];
+ T1[0] = op3.w32[2];
+ for (e = 0; e <= 1; e++) {
+ UInt elt = T1[e];
+ elt = ROR32(elt, 17) ^ ROR32(elt, 19) ^ (elt >> 10);
+ elt = elt + op1.w32[e] + T0.w32[e];
+ res->w32[e] = elt;
+ }
+ T1[1] = res->w32[1];
+ T1[0] = res->w32[0];
+ for (e = 2; e <= 3; e++) {
+ UInt elt = T1[e-2];
+ elt = ROR32(elt, 17) ^ ROR32(elt, 19) ^ (elt >> 10);
+ elt = elt + op1.w32[e] + T0.w32[e];
+ res->w32[e] = elt;
+ }
+}
+
+
/*---------------------------------------------------------------*/
/*--- Flag-helpers translation-time function specialisers. ---*/
/*--- These help iropt specialise calls the above run-time ---*/
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Mon Jul 18 07:33:52 2016
@@ -12937,7 +12937,102 @@
static
Bool dis_AdvSIMD_crypto_three_reg_sha(/*MB_OUT*/DisResult* dres, UInt insn)
{
+ /* 31 28 23 21 20 15 14 11 9 4
+ 0101 1110 sz 0 m 0 opc 00 n d
+ Decode fields are: sz,opc
+ */
# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,24) != BITS8(0,1,0,1,1,1,1,0) || INSN(21,21) != 0
+ || INSN(15,15) != 0 || INSN(11,10) != BITS2(0,0)) {
+ return False;
+ }
+ UInt sz = INSN(23,22);
+ UInt mm = INSN(20,16);
+ UInt opc = INSN(14,12);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+ if (sz == BITS2(0,0) && opc <= BITS3(1,1,0)) {
+ /* -------- 00,000 SHA1C Qd, Sn, Vm.4S -------- */
+ /* -------- 00,001 SHA1P Qd, Sn, Vm.4S -------- */
+ /* -------- 00,010 SHA1M Qd, Sn, Vm.4S -------- */
+ /* -------- 00,011 SHA1SU0 Vd.4S, Vn.4S, Vm.4S -------- */
+ /* -------- 00,100 SHA256H Qd, Qn, Vm.4S -------- */
+ /* -------- 00,101 SHA256H2 Qd, Qn, Vm.4S -------- */
+ /* -------- 00,110 SHA256SU1 Vd.4S, Vn.4S, Vm.4S -------- */
+ vassert(opc < 7);
+ const HChar* inames[7]
+ = { "sha1c", "sha1p", "sha1m", "sha1su0",
+ "sha256h", "sha256h2", "sha256su1" };
+ void(*helpers[7])(V128*,ULong,ULong,ULong,ULong,ULong,ULong)
+ = { &arm64g_dirtyhelper_SHA1C, &arm64g_dirtyhelper_SHA1P,
+ &arm64g_dirtyhelper_SHA1M, &arm64g_dirtyhelper_SHA1SU0,
+ &arm64g_dirtyhelper_SHA256H, &arm64g_dirtyhelper_SHA256H2,
+ &arm64g_dirtyhelper_SHA256SU1 };
+ const HChar* hnames[7]
+ = { "arm64g_dirtyhelper_SHA1C", "arm64g_dirtyhelper_SHA1P",
+ "arm64g_dirtyhelper_SHA1M", "arm64g_dirtyhelper_SHA1SU0",
+ "arm64g_dirtyhelper_SHA256H", "arm64g_dirtyhelper_SHA256H2",
+ "arm64g_dirtyhelper_SHA256SU1" };
+ IRTemp vD = newTemp(Ity_V128);
+ IRTemp vN = newTemp(Ity_V128);
+ IRTemp vM = newTemp(Ity_V128);
+ IRTemp vDhi = newTemp(Ity_I64);
+ IRTemp vDlo = newTemp(Ity_I64);
+ IRTemp vNhiPre = newTemp(Ity_I64);
+ IRTemp vNloPre = newTemp(Ity_I64);
+ IRTemp vNhi = newTemp(Ity_I64);
+ IRTemp vNlo = newTemp(Ity_I64);
+ IRTemp vMhi = newTemp(Ity_I64);
+ IRTemp vMlo = newTemp(Ity_I64);
+ assign(vD, getQReg128(dd));
+ assign(vN, getQReg128(nn));
+ assign(vM, getQReg128(mm));
+ assign(vDhi, unop(Iop_V128HIto64, mkexpr(vD)));
+ assign(vDlo, unop(Iop_V128to64, mkexpr(vD)));
+ assign(vNhiPre, unop(Iop_V128HIto64, mkexpr(vN)));
+ assign(vNloPre, unop(Iop_V128to64, mkexpr(vN)));
+ assign(vMhi, unop(Iop_V128HIto64, mkexpr(vM)));
+ assign(vMlo, unop(Iop_V128to64, mkexpr(vM)));
+ /* Mask off any bits of the N register operand that aren't actually
+ needed, so that Memcheck doesn't complain unnecessarily. */
+ switch (opc) {
+ case BITS3(0,0,0): case BITS3(0,0,1): case BITS3(0,1,0):
+ assign(vNhi, mkU64(0));
+ assign(vNlo, unop(Iop_32Uto64, unop(Iop_64to32, mkexpr(vNloPre))));
+ break;
+ case BITS3(0,1,1): case BITS3(1,0,0):
+ case BITS3(1,0,1): case BITS3(1,1,0):
+ assign(vNhi, mkexpr(vNhiPre));
+ assign(vNlo, mkexpr(vNloPre));
+ break;
+ default:
+ vassert(0);
+ }
+ IRTemp res = newTemp(Ity_V128);
+ IRDirty* di
+ = unsafeIRDirty_1_N( res, 0/*regparms*/, hnames[opc], helpers[opc],
+ mkIRExprVec_7(
+ IRExpr_VECRET(),
+ mkexpr(vDhi), mkexpr(vDlo), mkexpr(vNhi),
+ mkexpr(vNlo), mkexpr(vMhi), mkexpr(vMlo)));
+ stmt(IRStmt_Dirty(di));
+ putQReg128(dd, mkexpr(res));
+ switch (opc) {
+ case BITS3(0,0,0): case BITS3(0,0,1): case BITS3(0,1,0):
+ DIP("%s q%u, s%u, v%u.4s\n", inames[opc], dd, nn, mm);
+ break;
+ case BITS3(0,1,1): case BITS3(1,1,0):
+ DIP("%s v%u.4s, v%u.4s, v%u.4s\n", inames[opc], dd, nn, mm);
+ break;
+ case BITS3(1,0,0): case BITS3(1,0,1):
+ DIP("%s q%u, q%u, v%u.4s\n", inames[opc], dd, nn, mm);
+ break;
+ default:
+ vassert(0);
+ }
+ return True;
+ }
+
return False;
# undef INSN
}
@@ -12946,7 +13041,91 @@
static
Bool dis_AdvSIMD_crypto_two_reg_sha(/*MB_OUT*/DisResult* dres, UInt insn)
{
+ /* 31 28 23 21 16 11 9 4
+ 0101 1110 sz 10100 opc 10 n d
+ Decode fields are: sz,opc
+ */
# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,24) != BITS8(0,1,0,1,1,1,1,0)
+ || INSN(21,17) != BITS5(1,0,1,0,0) || INSN(11,10) != BITS2(1,0)) {
+ return False;
+ }
+ UInt sz = INSN(23,22);
+ UInt opc = INSN(16,12);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+ if (sz == BITS2(0,0) && opc <= BITS5(0,0,0,1,0)) {
+ /* -------- 00,00000 SHA1H Sd, Sn -------- */
+ /* -------- 00,00001 SHA1SU1 Vd.4S, Vn.4S -------- */
+ /* -------- 00,00010 SHA256SU0 Vd.4S, Vn.4S -------- */
+ vassert(opc < 3);
+ const HChar* inames[3] = { "sha1h", "sha1su1", "sha256su0" };
+ IRTemp vD = newTemp(Ity_V128);
+ IRTemp vN = newTemp(Ity_V128);
+ IRTemp vDhi = newTemp(Ity_I64);
+ IRTemp vDlo = newTemp(Ity_I64);
+ IRTemp vNhi = newTemp(Ity_I64);
+ IRTemp vNlo = newTemp(Ity_I64);
+ assign(vD, getQReg128(dd));
+ assign(vN, getQReg128(nn));
+ assign(vDhi, unop(Iop_V128HIto64, mkexpr(vD)));
+ assign(vDlo, unop(Iop_V128to64, mkexpr(vD)));
+ assign(vNhi, unop(Iop_V128HIto64, mkexpr(vN)));
+ assign(vNlo, unop(Iop_V128to64, mkexpr(vN)));
+ /* Mask off any bits of the N register operand that aren't actually
+ needed, so that Memcheck doesn't complain unnecessarily. Also
+ construct the calls, given that the helper functions don't take
+ the same number of arguments. */
+ IRDirty* di = NULL;
+ IRTemp res = newTemp(Ity_V128);
+ switch (opc) {
+ case BITS5(0,0,0,0,0): {
+ IRExpr* vNloMasked = unop(Iop_32Uto64,
+ unop(Iop_64to32, mkexpr(vNlo)));
+ di = unsafeIRDirty_1_N( res, 0/*regparms*/,
+ "arm64g_dirtyhelper_SHA1H",
+ &arm64g_dirtyhelper_SHA1H,
+ mkIRExprVec_3(
+ IRExpr_VECRET(),
+ mkU64(0), vNloMasked) );
+ break;
+ }
+ case BITS5(0,0,0,0,1):
+ di = unsafeIRDirty_1_N( res, 0/*regparms*/,
+ "arm64g_dirtyhelper_SHA1SU1",
+ &arm64g_dirtyhelper_SHA1SU1,
+ mkIRExprVec_5(
+ IRExpr_VECRET(),
+ mkexpr(vDhi), mkexpr(vDlo),
+ mkexpr(vNhi), mkexpr(vNlo)) );
+ break;
+ case BITS5(0,0,0,1,0):
+ di = unsafeIRDirty_1_N( res, 0/*regparms*/,
+ "arm64g_dirtyhelper_SHA256SU0",
+ &arm64g_dirtyhelper_SHA256SU0,
+ mkIRExprVec_5(
+ IRExpr_VECRET(),
+ mkexpr(vDhi), mkexpr(vDlo),
+ mkexpr(vNhi), mkexpr(vNlo)) );
+ break;
+ default:
+ vassert(0);
+ }
+ stmt(IRStmt_Dirty(di));
+ putQReg128(dd, mkexpr(res));
+ switch (opc) {
+ case BITS5(0,0,0,0,0):
+ DIP("%s s%u, s%u\n", inames[opc], dd, nn);
+ break;
+ case BITS5(0,0,0,0,1): case BITS5(0,0,0,1,0):
+ DIP("%s v%u.4s, v%u.4s\n", inames[opc], dd, nn);
+ break;
+ default:
+ vassert(0);
+ }
+ return True;
+ }
+
return False;
# undef INSN
}
|
|
From: Roland M. <rol...@nr...> - 2016-07-17 20:11:46
|
On Sun, Jul 17, 2016 at 10:07 PM, Ivo Raisr <iv...@iv...> wrote: > as you may be aware, we are currently working on sparcv9 support [snip] Totally off-topic: 1. Thank you very much... :-) 2. Don't forget to implement 128bit floating-point support ---- Bye, Roland -- __ . . __ (o.\ \/ /.o) rol...@nr... \__\/\/__/ MPEG specialist, C&&JAVA&&Sun&&Unix programmer /O /==\ O\ TEL +49 641 3992797 (;O/ \/ \O;) |
|
From: Ivo R. <iv...@iv...> - 2016-07-17 20:07:40
|
Dear developers,
as you may be aware, we are currently working on sparcv9 support
for Valgrind [1]. Part of the ISA are crypto instructions, such as md5,
sha256, AES, Camelia, Montgmery multiplication and squaring, and others [2].
Some of these instructions can have inputs of up to several kilobytes,
utilizing sparc register windows and floating-point registers.
We have some doubts about the best way of implementing support for these
complex instructions in the VEX frontend and eventually backend (isel).
So far we have come up with 3 possible approaches:
1. Describe a crypto instruction with IR opcodes.
Pros: clean approach, does not require any isel support, works for
cross-arch analysis
Cons: bloated IR tree, especially after a tool instrumentation, expecting
slow processing
2. Utilize a clean helper function which will compute required output.
Pros: IR tree will be small, instrumentation relatively fast
Cons: unclear how to pass effectively inputs and outputs from the helper,
logic is "hidden" behind the helper
3. Add a new IR opcode for a crypto instruction.
Pros: clear intent, smallest IR tree
Cons: need to add support to VEX isel and all tools,
unclear how to effectively allocate virtual/host registers
I would like to hear your thoughts, comments, suggestions.
Thank you,
I.
[1] https://bitbucket.org/iraisr/valgrind-solaris
[2]
http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-architecture-2015-2868130.pdf
|
|
From: <sv...@va...> - 2016-07-16 21:50:53
|
Author: mjw
Date: Sat Jul 16 22:50:45 2016
New Revision: 15907
Log:
Fix arm64/fp_and_simd.c compile error.
Older GCC don't default to GNU11 and will produce:
error: ‘for’ loop initial declarations are only allowed in C99 mode
Move int i declaration to top of main.
Modified:
trunk/none/tests/arm64/fp_and_simd.c
Modified: trunk/none/tests/arm64/fp_and_simd.c
==============================================================================
--- trunk/none/tests/arm64/fp_and_simd.c (original)
+++ trunk/none/tests/arm64/fp_and_simd.c Sat Jul 16 22:50:45 2016
@@ -4548,6 +4548,7 @@
int main ( void )
{
+ int i;
assert(sizeof(V128) == 16);
// ======================== FP ========================
@@ -7389,13 +7390,13 @@
// aese 16b (aes single round encryption)
// aesimc 16b (aes inverse mix columns)
// aesmc 16b (aes mix columns)
- if (1) for (int i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
+ if (1) for (i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
test_aesd_16b_16b(TyNONE);
- if (1) for (int i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
+ if (1) for (i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
test_aese_16b_16b(TyNONE);
- if (1) for (int i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
+ if (1) for (i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
test_aesimc_16b_16b(TyNONE);
- if (1) for (int i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
+ if (1) for (i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
test_aesmc_16b_16b(TyNONE);
// sha1c q_s_4s
|
|
From: <sv...@va...> - 2016-07-15 10:33:28
|
Author: sewardj
Date: Fri Jul 15 11:33:20 2016
New Revision: 15906
Log:
Enable test cases for: AESE AESD AESMC AESIMC.
Modified:
trunk/none/tests/arm64/fp_and_simd.c
trunk/none/tests/arm64/fp_and_simd.stdout.exp
Modified: trunk/none/tests/arm64/fp_and_simd.c
==============================================================================
--- trunk/none/tests/arm64/fp_and_simd.c (original)
+++ trunk/none/tests/arm64/fp_and_simd.c Fri Jul 15 11:33:20 2016
@@ -4523,10 +4523,6 @@
// ======================== CRYPTO ========================
-// These tests are believed to be correct but are disabled because
-// GNU assembler (GNU Binutils) 2.24.0.20140311 Linaro 2014.03
-// cannot be persuaded to accept those instructions (AFAICT).
-
GEN_TWOVEC_TEST(aesd_16b_16b, "aesd v6.16b, v27.16b", 6, 27)
GEN_TWOVEC_TEST(aese_16b_16b, "aese v6.16b, v27.16b", 6, 27)
GEN_TWOVEC_TEST(aesimc_16b_16b, "aesimc v6.16b, v27.16b", 6, 27)
@@ -7385,14 +7381,22 @@
// ======================== CRYPTO ========================
+ // By default each test only runs once. That seems a bit too minimal
+ // for the crypto ones. So here's an extra run multiplication factor.
+ const int CRYPTO_ITER_MULTIPLIER = 10;
+
// aesd 16b (aes single round decryption)
// aese 16b (aes single round encryption)
// aesimc 16b (aes inverse mix columns)
// aesmc 16b (aes mix columns)
- if (0) test_aesd_16b_16b(TyNONE);
- if (0) test_aese_16b_16b(TyNONE);
- if (0) test_aesimc_16b_16b(TyNONE);
- if (0) test_aesmc_16b_16b(TyNONE);
+ if (1) for (int i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
+ test_aesd_16b_16b(TyNONE);
+ if (1) for (int i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
+ test_aese_16b_16b(TyNONE);
+ if (1) for (int i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
+ test_aesimc_16b_16b(TyNONE);
+ if (1) for (int i = 0; i < CRYPTO_ITER_MULTIPLIER; i++)
+ test_aesmc_16b_16b(TyNONE);
// sha1c q_s_4s
// sha1h s_s
Modified: trunk/none/tests/arm64/fp_and_simd.stdout.exp
==============================================================================
--- trunk/none/tests/arm64/fp_and_simd.stdout.exp (original)
+++ trunk/none/tests/arm64/fp_and_simd.stdout.exp Fri Jul 15 11:33:20 2016
@@ -28793,3 +28793,44 @@
xtn2 v8.8h, v7.4s84dc03eb98680d7370a20b36262e4d85 03eb0d730b364d8567181415788bf1b7 fpsr=00000000
xtn v8.8b, v7.8h2ca8635ab8c96385922e6ada920bfd94 0000000000000000a85ac9852eda0b94 fpsr=00000000
xtn2 v8.16b, v7.8hcb1fb88391120d19091694424470869f 1f8312191642709f078822ac5f050d24 fpsr=00000000
+aesd v6.16b, v27.16b ad3c6e02b07fb70d9fd77489491a1302 739d536739e995431983556db1388e96 e1fd94bc9c947bb6f2f175aedc358be7 739d536739e995431983556db1388e96 fpsr=00000000
+aesd v6.16b, v27.16b 6a5ead74eeb3b9815ad00525782dec40 9d5c678e38c8da85c06cb0684f364ebb b27800142644d2304a6a1a6537031063 9d5c678e38c8da85c06cb0684f364ebb fpsr=00000000
+aesd v6.16b, v27.16b c1ec8190d147c9c125fb7f908222e72f fb81e698f37f844b0e7dcb69dd8f8948 84dc65bfa218c6cf94b345690b760a0a fb81e698f37f844b0e7dcb69dd8f8948 fpsr=00000000
+randV128: 9728 calls, 10055 iters
+aesd v6.16b, v27.16b ecea3363ccecf67463980750bd239e1d 1a0877230e10be492570ec1c59f5e287 aec8d472d64a3c8ba83b015d98558637 1a0877230e10be492570ec1c59f5e287 fpsr=00000000
+aesd v6.16b, v27.16b d079abd022ef8de2209bc2fd4fd2ed1a 5a1a823b3344761afa896f5da6563841 eb39633ccf4f18e1e300b5477a0e4c57 5a1a823b3344761afa896f5da6563841 fpsr=00000000
+aesd v6.16b, v27.16b 080cb0c0566aab73a4675f4ff17bd71e 862af10e4d680dc72f62aa7c1c297fbb 5336c5ece64877c644236f66ce6af829 862af10e4d680dc72f62aa7c1c297fbb fpsr=00000000
+aesd v6.16b, v27.16b f384a210c73caf094fdd3b280500bb0b fd16247abc5ae23123ddfe591b4f19d4 e9526558d792077603741a2cb8d3dcef fd16247abc5ae23123ddfe591b4f19d4 fpsr=00000000
+aesd v6.16b, v27.16b f1c1dfa3d544fa8282dbb866eb3ffabf 1fbf7c61e1fb553637d8cad404a8656e 61d51ba899851ec6288a6e3ed2f47151 1fbf7c61e1fb553637d8cad404a8656e fpsr=00000000
+aesd v6.16b, v27.16b 63a2c958e164ebbf9c4236ea0219f31b 4d0558a11b2bc6b7ca346ecc3614c467 280ffa69c3f35ebf1489b223b992ac01 4d0558a11b2bc6b7ca346ecc3614c467 fpsr=00000000
+aesd v6.16b, v27.16b a809c00f4a7ae2a0fdf11394aa6f0600 e6c8191bcaca96943cd14b23127395a0 9a54ca9bb6c45e283add2220ddfce547 e6c8191bcaca96943cd14b23127395a0 fpsr=00000000
+aese v6.16b, v27.16b 21d523a77167400406cab144441f944c 4ae71eaf4fb825acee8fc0b7f7a538f9 b26e91309bf427c26d234d0d7f9ea3d5 4ae71eaf4fb825acee8fc0b7f7a538f9 fpsr=00000000
+aese v6.16b, v27.16b 2de55201b50b64cd16ab70da2f0afce0 da44c73d09d5d2e13f4d2e6a458a0e52 658e89eba5cd2a7102324ee7681d5837 da44c73d09d5d2e13f4d2e6a458a0e52 fpsr=00000000
+aese v6.16b, v27.16b 2c1aaefe7646afda8e76af36cb0f9f9b f5be75a45901fd128fedf41a5d01768b 15141ebe7cabb9e89049007135a039ca f5be75a45901fd128fedf41a5d01768b fpsr=00000000
+aese v6.16b, v27.16b 7f54967c15f8800acd09ce377910db5f fb3487c69e1b061e3f4e72a89eecd084 3da02bf489b082fa94d044db5f1165b9 fb3487c69e1b061e3f4e72a89eecd084 fpsr=00000000
+aese v6.16b, v27.16b 85736a5cf101373e33452dbf98ec130b 4d875d8138044ee6ae4f08f468297d1c dd679fc15ea69a618cbfb6b3e86b3ff0 4d875d8138044ee6ae4f08f468297d1c fpsr=00000000
+aese v6.16b, v27.16b 9e578b7e6a403556210a2dac8882a47e 4b9758b7889d344a3dd118de1c99dc34 98b9bcdd9caf669c22ba7c4003c196d6 4b9758b7889d344a3dd118de1c99dc34 fpsr=00000000
+aese v6.16b, v27.16b 2be058c1e196d933f6382ee0aab3f099 5344d746edc4192a4bb4ff46191c4ead fe64ae177a7973d46d49ba24bc003e18 5344d746edc4192a4bb4ff46191c4ead fpsr=00000000
+aese v6.16b, v27.16b 8bee3107b5e483b213af8e395d5f573d c76e3b0fc85a5c6638d81f0bc0923265 fff54d30f1bd67485ecd9e2329ae816a c76e3b0fc85a5c6638d81f0bc0923265 fpsr=00000000
+aese v6.16b, v27.16b 1f60772e460894b6d74faf9802663748 07f5e3f2783f5dde651dd70f70dbe83d b2009e86377a2245402add88ad9abc9d 07f5e3f2783f5dde651dd70f70dbe83d fpsr=00000000
+aese v6.16b, v27.16b 45188918f5e36b1ea2f7f1dcf8a8f39b 71b82fcf5d527d723163873089d6d115 c222930edcf32450a3e047ce18c83819 71b82fcf5d527d723163873089d6d115 fpsr=00000000
+aesimc v6.16b, v27.16b 60f4c8a3225569c9d589b3e79f05e815 68998085d8751b01fd8a904f6c654ccd 31052aea28879e86b2c2944c11453ae6 68998085d8751b01fd8a904f6c654ccd fpsr=00000000
+aesimc v6.16b, v27.16b cdd593b02b3dec99cfe35598585d7898 497635f64887986d2871524c7866b944 9a6305009e763ae85a7eaecd93688f97 497635f64887986d2871524c7866b944 fpsr=00000000
+aesimc v6.16b, v27.16b ee9b4a1f727d576cf0e637ce828f0203 7630ae000d67539412f92b070eba795c 3e952d6ef5e0ea527944d52f180956d6 7630ae000d67539412f92b070eba795c fpsr=00000000
+aesimc v6.16b, v27.16b 23264ed057f407239972ba6b7e7de735 4ea84c8588f6ac571b037d608c41ebf3 8787dbf47c7949c943892fe0d219041a 4ea84c8588f6ac571b037d608c41ebf3 fpsr=00000000
+aesimc v6.16b, v27.16b cb56fea238815e9e29673e4daa05860f 32bb6f6318140396a46da83755db70ea 3e3e72f74e0f7ca47947d9b110ac1db5 32bb6f6318140396a46da83755db70ea fpsr=00000000
+aesimc v6.16b, v27.16b 460abb777805bcbd00a5215569083f71 814c757b1da1b9310d180b6bc6686721 12907b3a6c3ba0c32915c58c48f9227b 814c757b1da1b9310d180b6bc6686721 fpsr=00000000
+aesimc v6.16b, v27.16b f424e42e746080607f0bc5631866733c 9b3ac0adf87d2e08b4e406de41c83079 76ffaeebba6f31473a08833974a99e83 9b3ac0adf87d2e08b4e406de41c83079 fpsr=00000000
+aesimc v6.16b, v27.16b 3682d9a68e720a67067b8a5719ff814d e165afd90888c1fafbb0f96e25db2ccf 919320d0ea544e4ba41505683b9908b7 e165afd90888c1fafbb0f96e25db2ccf fpsr=00000000
+aesimc v6.16b, v27.16b 6c05fbc0251bbab1f3d3cf11ccb3c987 b2aca3deaea1d2e9425e45fcd380ba06 7815afa1440b502bc32295d10bdea79d b2aca3deaea1d2e9425e45fcd380ba06 fpsr=00000000
+aesimc v6.16b, v27.16b f48da95c9a3bf120a8f5f4708f61acc9 6ff0fb9e49aac1b3e8cc4968aa993afd 9b1de09cc56674466c0fc7a1676104f6 6ff0fb9e49aac1b3e8cc4968aa993afd fpsr=00000000
+aesmc v6.16b, v27.16b 30fa435a4cb20e9285bf5956c4eb89f2 771218f73981ef394ddc66920b040d93 e65286b857845de08d806c04b18b8e25 771218f73981ef394ddc66920b040d93 fpsr=00000000
+aesmc v6.16b, v27.16b 2af058cadf07bb5bd26cfb5a54a292aa 8da508d99c81ec6f2bc5ac931bae0d0e dc0cb099ff25a8ec91d3af3c8769e6be 8da508d99c81ec6f2bc5ac931bae0d0e fpsr=00000000
+aesmc v6.16b, v27.16b e96b1ef89a1d86f9d65d69a0e8532a20 ed42b59f0c84ce7fcea9779b8f0ee08f 8c82c54ed3b6633fefec5bd361f9c9bf ed42b59f0c84ce7fcea9779b8f0ee08f fpsr=00000000
+aesmc v6.16b, v27.16b 1363c75fcba1aff3b98f0e4324f734d6 51541fd8086f65a2e8c65239c5da7d08 9a9c4b8fe701d19714df24aa2e8e4288 51541fd8086f65a2e8c65239c5da7d08 fpsr=00000000
+aesmc v6.16b, v27.16b 18bba562f32113bad9fc9d4d1cf04559 edbb5450e210bfa0636ed3536fcefb29 de45c30a8b0217738ef93fc590e4e2e5 edbb5450e210bfa0636ed3536fcefb29 fpsr=00000000
+aesmc v6.16b, v27.16b 075ffc9cdbded89459b649b57785a713 504f4555819aa491ea5603b2501943f1 557e5e7a8f82f6d55738a4c6f2700c75 504f4555819aa491ea5603b2501943f1 fpsr=00000000
+aesmc v6.16b, v27.16b dd1059319baa20f37ecfc98578bf954d f37ed68061f18e9e5a3eabc01f1e79f2 cea446f7044af03e7af9951954963d75 f37ed68061f18e9e5a3eabc01f1e79f2 fpsr=00000000
+aesmc v6.16b, v27.16b 4a92530d7e9e5eb0f1cf93555fffa9da 4f2b9966be5424d760f6b995600539c3 86787d187582dd332b7b9d77a250deb3 4f2b9966be5424d760f6b995600539c3 fpsr=00000000
+aesmc v6.16b, v27.16b b56b1ddc388375a510e91c4f709a338b de707d888fd16358600e91cc74bad158 296c3c225f08794b10e187456b7a4016 de707d888fd16358600e91cc74bad158 fpsr=00000000
+aesmc v6.16b, v27.16b 92e993cdf07e325e166ca690b3d078e3 7752e50575dda055df864181d3827c4e 56dd551b68cb07f9faad4d839143f849 7752e50575dda055df864181d3827c4e fpsr=00000000
|
|
From: <sv...@va...> - 2016-07-15 10:31:47
|
Author: sewardj
Date: Fri Jul 15 11:31:34 2016
New Revision: 3224
Log:
Implement arm64 instructions: AESE AESD AESMC AESIMC. n-i-bz.
Modified:
trunk/priv/guest_arm64_defs.h
trunk/priv/guest_arm64_helpers.c
trunk/priv/guest_arm64_toIR.c
Modified: trunk/priv/guest_arm64_defs.h
==============================================================================
--- trunk/priv/guest_arm64_defs.h (original)
+++ trunk/priv/guest_arm64_defs.h Fri Jul 15 11:31:34 2016
@@ -115,6 +115,15 @@
extern ULong arm64g_dirtyhelper_MRS_CNTVCT_EL0 ( void );
+extern void arm64g_dirtyhelper_AESE ( /*OUT*/V128* res,
+ ULong argHi, ULong argLo );
+extern void arm64g_dirtyhelper_AESD ( /*OUT*/V128* res,
+ ULong argHi, ULong argLo );
+extern void arm64g_dirtyhelper_AESMC ( /*OUT*/V128* res,
+ ULong argHi, ULong argLo );
+extern void arm64g_dirtyhelper_AESIMC ( /*OUT*/V128* res,
+ ULong argHi, ULong argLo );
+
/*---------------------------------------------------------*/
/*--- Condition code stuff ---*/
Modified: trunk/priv/guest_arm64_helpers.c
==============================================================================
--- trunk/priv/guest_arm64_helpers.c (original)
+++ trunk/priv/guest_arm64_helpers.c Fri Jul 15 11:31:34 2016
@@ -692,6 +692,230 @@
}
+/* DIRTY HELPERS for doing AES support:
+ * AESE (SubBytes, then ShiftRows)
+ * AESD (InvShiftRows, then InvSubBytes)
+ * AESMC (MixColumns)
+ * AESIMC (InvMixColumns)
+ These don't actually have to be dirty helpers -- they could be
+ clean, but for the fact that they return a V128 and a clean helper
+ can't do that.
+
+ The ARMv8 manual seems to imply that AESE first performs ShiftRows,
+ then SubBytes. This seems to contradict FIPS 197, so the
+ implementation below is consistent with FIPS 197. One can observe
+ that the two transformations commute -- the order in which they
+ happen makes no difference to the result. So the ambiguity doesn't
+ actually matter, but it is confusing. The v8 manual looks correct
+ about AESD, though.
+
+ The three functions rj_xtime, aesMixColumn and aesInvMixColumn only,
+ are taken from "A byte-oriented AES-256 implementation" and are subject
+ to the following usage terms:
+
+ Byte-oriented AES-256 implementation.
+ All lookup tables replaced with 'on the fly' calculations.
+
+ Copyright (c) 2007-2011 Ilya O. Levin, http://www.literatecode.com
+ Other contributors: Hal Finney
+
+ Permission to use, copy, modify, and distribute this software for any
+ purpose with or without fee is hereby granted, provided that the above
+ copyright notice and this permission notice appear in all copies.
+
+ THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+*/
+
+const UChar aesMapSubBytes[256]
+ = { 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5,
+ 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
+ 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0,
+ 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
+ 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc,
+ 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
+ 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a,
+ 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
+ 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0,
+ 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
+ 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b,
+ 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
+ 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85,
+ 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
+ 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5,
+ 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
+ 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17,
+ 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
+ 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88,
+ 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
+ 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c,
+ 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
+ 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9,
+ 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
+ 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6,
+ 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
+ 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e,
+ 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
+ 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94,
+ 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
+ 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68,
+ 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
+ };
+
+const UChar aesMapInvSubBytes[256]
+ = { 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38,
+ 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,
+ 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87,
+ 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb,
+ 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d,
+ 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e,
+ 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2,
+ 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25,
+ 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16,
+ 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92,
+ 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda,
+ 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84,
+ 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a,
+ 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06,
+ 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02,
+ 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b,
+ 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea,
+ 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73,
+ 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85,
+ 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e,
+ 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89,
+ 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b,
+ 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20,
+ 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4,
+ 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31,
+ 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,
+ 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d,
+ 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,
+ 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0,
+ 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61,
+ 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26,
+ 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
+ };
+
+static inline UChar rj_xtime ( UChar x )
+{
+ UChar y = (UChar)(x << 1);
+ return (x & 0x80) ? (y ^ 0x1b) : y;
+}
+
+static void aesMixColumn ( /*MOD*/UChar* r )
+{
+ UChar a = r[0];
+ UChar b = r[1];
+ UChar c = r[2];
+ UChar d = r[3];
+ UChar e = a ^ b ^ c ^ d;
+ r[0] ^= e ^ rj_xtime(a ^ b);
+ r[1] ^= e ^ rj_xtime(b ^ c);
+ r[2] ^= e ^ rj_xtime(c ^ d);
+ r[3] ^= e ^ rj_xtime(d ^ a);
+}
+
+static void aesInvMixColumn ( /*MOD*/UChar* r )
+{
+ UChar a = r[0];
+ UChar b = r[1];
+ UChar c = r[2];
+ UChar d = r[3];
+ UChar e = a ^ b ^ c ^ d;
+ UChar z = rj_xtime(e);
+ UChar x = e ^ rj_xtime(rj_xtime(z ^ a ^ c));
+ UChar y = e ^ rj_xtime(rj_xtime(z ^ b ^ d));
+ r[0] ^= x ^ rj_xtime(a ^ b);
+ r[1] ^= y ^ rj_xtime(b ^ c);
+ r[2] ^= x ^ rj_xtime(c ^ d);
+ r[3] ^= y ^ rj_xtime(d ^ a);
+}
+
+
+/* CALLED FROM GENERATED CODE */
+void arm64g_dirtyhelper_AESE ( /*OUT*/V128* res, ULong argHi, ULong argLo )
+{
+ res->w64[1] = argHi;
+ res->w64[0] = argLo;
+
+ /* First do SubBytes on the State. */
+ UInt i;
+ for (i = 0; i < 16; i++) {
+ res->w8[i] = aesMapSubBytes[res->w8[i] & 0xFF];
+ }
+
+ /* Then do ShiftRows on the State. */
+# define XX(_ix) res->w8[_ix]
+ { UChar old1 = XX(1);
+ XX(1) = XX(5); XX(5) = XX(9); XX(9) = XX(13); XX(13) = old1;
+ }
+ { UChar old2 = XX(2); UChar old6 = XX(6);
+ XX(2) = XX(10); XX(6) = XX(14); XX(10) = old2; XX(14) = old6;
+ }
+ { UChar old15 = XX(15);
+ XX(15) = XX(11); XX(11) = XX(7); XX(7) = XX(3); XX(3) = old15;
+ }
+# undef XX
+}
+
+
+/* CALLED FROM GENERATED CODE */
+void arm64g_dirtyhelper_AESD ( /*OUT*/V128* res, ULong argHi, ULong argLo )
+{
+ res->w64[1] = argHi;
+ res->w64[0] = argLo;
+
+ /* First do InvShiftRows on the State. */
+# define XX(_ix) res->w8[_ix]
+ { UChar old13 = XX(13);
+ XX(13) = XX(9); XX(9) = XX(5); XX(5) = XX(1); XX(1) = old13;
+ }
+ { UChar old14 = XX(14); UChar old10 = XX(10);
+ XX(14) = XX(6); XX(10) = XX(2); XX(6) = old14; XX(2) = old10;
+ }
+ { UChar old3 = XX(3);
+ XX(3) = XX(7); XX(7) = XX(11); XX(11) = XX(15); XX(15) = old3;
+ }
+# undef XX
+
+/* Then do InvSubBytes on the State. */
+ UInt i;
+ for (i = 0; i < 16; i++) {
+ res->w8[i] = aesMapInvSubBytes[res->w8[i] & 0xFF];
+ }
+}
+
+
+/* CALLED FROM GENERATED CODE */
+void arm64g_dirtyhelper_AESMC ( /*OUT*/V128* res, ULong argHi, ULong argLo )
+{
+ res->w64[1] = argHi;
+ res->w64[0] = argLo;
+ aesMixColumn(&res->w8[0]);
+ aesMixColumn(&res->w8[4]);
+ aesMixColumn(&res->w8[8]);
+ aesMixColumn(&res->w8[12]);
+}
+
+
+/* CALLED FROM GENERATED CODE */
+void arm64g_dirtyhelper_AESIMC ( /*OUT*/V128* res, ULong argHi, ULong argLo )
+{
+ res->w64[1] = argHi;
+ res->w64[0] = argLo;
+ aesInvMixColumn(&res->w8[0]);
+ aesInvMixColumn(&res->w8[4]);
+ aesInvMixColumn(&res->w8[8]);
+ aesInvMixColumn(&res->w8[12]);
+}
+
+
/*---------------------------------------------------------------*/
/*--- Flag-helpers translation-time function specialisers. ---*/
/*--- These help iropt specialise calls the above run-time ---*/
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Fri Jul 15 11:31:34 2016
@@ -12860,7 +12860,75 @@
static
Bool dis_AdvSIMD_crypto_aes(/*MB_OUT*/DisResult* dres, UInt insn)
{
+ /* 31 23 21 16 11 9 4
+ 0100 1110 size 10100 opcode 10 n d
+ Decode fields are: size,opcode
+ Size is always 00 in ARMv8, it appears.
+ */
# define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
+ if (INSN(31,24) != BITS8(0,1,0,0,1,1,1,0)
+ || INSN(21,17) != BITS5(1,0,1,0,0) || INSN(11,10) != BITS2(1,0)) {
+ return False;
+ }
+ UInt size = INSN(23,22);
+ UInt opcode = INSN(16,12);
+ UInt nn = INSN(9,5);
+ UInt dd = INSN(4,0);
+
+ if (size == BITS2(0,0)
+ && (opcode == BITS5(0,0,1,0,0) || opcode == BITS5(0,0,1,0,1))) {
+ /* -------- 00,00100: AESE Vd.16b, Vn.16b -------- */
+ /* -------- 00,00101: AESD Vd.16b, Vn.16b -------- */
+ Bool isD = opcode == BITS5(0,0,1,0,1);
+ IRTemp op1 = newTemp(Ity_V128);
+ IRTemp op2 = newTemp(Ity_V128);
+ IRTemp xord = newTemp(Ity_V128);
+ IRTemp res = newTemp(Ity_V128);
+ void* helper = isD ? &arm64g_dirtyhelper_AESD
+ : &arm64g_dirtyhelper_AESE;
+ const HChar* hname = isD ? "arm64g_dirtyhelper_AESD"
+ : "arm64g_dirtyhelper_AESE";
+ assign(op1, getQReg128(dd));
+ assign(op2, getQReg128(nn));
+ assign(xord, binop(Iop_XorV128, mkexpr(op1), mkexpr(op2)));
+ IRDirty* di
+ = unsafeIRDirty_1_N( res, 0/*regparms*/, hname, helper,
+ mkIRExprVec_3(
+ IRExpr_VECRET(),
+ unop(Iop_V128HIto64, mkexpr(xord)),
+ unop(Iop_V128to64, mkexpr(xord)) ) );
+ stmt(IRStmt_Dirty(di));
+ putQReg128(dd, mkexpr(res));
+ DIP("aes%c %s.16b, %s.16b\n", isD ? 'd' : 'e',
+ nameQReg128(dd), nameQReg128(nn));
+ return True;
+ }
+
+ if (size == BITS2(0,0)
+ && (opcode == BITS5(0,0,1,1,0) || opcode == BITS5(0,0,1,1,1))) {
+ /* -------- 00,00110: AESMC Vd.16b, Vn.16b -------- */
+ /* -------- 00,00111: AESIMC Vd.16b, Vn.16b -------- */
+ Bool isI = opcode == BITS5(0,0,1,1,1);
+ IRTemp src = newTemp(Ity_V128);
+ IRTemp res = newTemp(Ity_V128);
+ void* helper = isI ? &arm64g_dirtyhelper_AESIMC
+ : &arm64g_dirtyhelper_AESMC;
+ const HChar* hname = isI ? "arm64g_dirtyhelper_AESIMC"
+ : "arm64g_dirtyhelper_AESMC";
+ assign(src, getQReg128(nn));
+ IRDirty* di
+ = unsafeIRDirty_1_N( res, 0/*regparms*/, hname, helper,
+ mkIRExprVec_3(
+ IRExpr_VECRET(),
+ unop(Iop_V128HIto64, mkexpr(src)),
+ unop(Iop_V128to64, mkexpr(src)) ) );
+ stmt(IRStmt_Dirty(di));
+ putQReg128(dd, mkexpr(res));
+ DIP("aes%s %s.16b, %s.16b\n", isI ? "imc" : "mc",
+ nameQReg128(dd), nameQReg128(nn));
+ return True;
+ }
+
return False;
# undef INSN
}
|
|
From: <sv...@va...> - 2016-07-12 21:50:24
|
Author: philippe
Date: Tue Jul 12 21:49:05 2016
New Revision: 3223
Log:
Fix n-i-bz amd64: memcheck false positive with shr %edx
False positive analysis and fix by Julian.
Thanks
Modified:
trunk/priv/guest_amd64_helpers.c
Modified: trunk/priv/guest_amd64_helpers.c
==============================================================================
--- trunk/priv/guest_amd64_helpers.c (original)
+++ trunk/priv/guest_amd64_helpers.c Tue Jul 12 21:49:05 2016
@@ -1604,6 +1604,15 @@
mkU64(0)));
}
+ /*---------------- SHRL ----------------*/
+
+ if (isU64(cc_op, AMD64G_CC_OP_SHRL) && isU64(cond, AMD64CondZ)) {
+ /* SHRL, then Z --> test dep1 == 0 */
+ return unop(Iop_1Uto64,
+ binop(Iop_CmpEQ32, unop(Iop_64to32, cc_dep1),
+ mkU32(0)));
+ }
+
/*---------------- COPY ----------------*/
/* This can happen, as a result of amd64 FP compares: "comisd ... ;
jbe" for example. */
|
Author: philippe
Date: Tue Jul 12 21:48:31 2016
New Revision: 15905
Log:
Regression test for n-i-bz amd64: memcheck false positive with shr %edx
Valgrind side : reproducer for the false positive memcheck
+ announce the fix (VEX side in next commit)
Added:
trunk/memcheck/tests/amd64/shr_edx.c
trunk/memcheck/tests/amd64/shr_edx.stderr.exp
trunk/memcheck/tests/amd64/shr_edx.stdout.exp
trunk/memcheck/tests/amd64/shr_edx.vgtest
Modified:
trunk/NEWS
trunk/memcheck/tests/amd64/Makefile.am
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Tue Jul 12 21:48:31 2016
@@ -136,7 +136,7 @@
n-i-bz Document brk segment limitation, reference manual in limit reached msg.
n-i-bz Fix clobber list in none/tests/amd64/xacq_xrel.c [valgrind r15737]
n-i-bz Bump allowed shift value for "add.w reg, sp, reg, lsl #N" [vex r3206]
-
+n-i-bz amd64: memcheck false positive with shr %edx
Release 3.11.0 (22 September 2015)
Modified: trunk/memcheck/tests/amd64/Makefile.am
==============================================================================
--- trunk/memcheck/tests/amd64/Makefile.am (original)
+++ trunk/memcheck/tests/amd64/Makefile.am Tue Jul 12 21:48:31 2016
@@ -30,6 +30,7 @@
sh-mem-vec256-plo-yes.vgtest \
sh-mem-vec256-plo-yes.stderr.exp \
sh-mem-vec256-plo-yes.stdout.exp \
+ shr_edx.stderr.exp shr_edx.stdout.exp shr_edx.vgtest \
sse_memory.stderr.exp sse_memory.stdout.exp sse_memory.vgtest \
xor-undef-amd64.stderr.exp xor-undef-amd64.stdout.exp \
xor-undef-amd64.vgtest \
@@ -43,6 +44,7 @@
insn-bsfl \
insn-pmovmskb \
sh-mem-vec128 \
+ shr_edx \
sse_memory \
xor-undef-amd64
if BUILD_AVX_TESTS
Added: trunk/memcheck/tests/amd64/shr_edx.c
==============================================================================
--- trunk/memcheck/tests/amd64/shr_edx.c (added)
+++ trunk/memcheck/tests/amd64/shr_edx.c Tue Jul 12 21:48:31 2016
@@ -0,0 +1,54 @@
+#include <stdio.h>
+#include <stdlib.h>
+typedef unsigned long long int ULong;
+
+ULong data;
+ULong result;
+
+
+extern void shrl32_with_0x10 ( void );
+asm("\n"
+"shrl32_with_0x10:\n"
+"\tpushq %rdx\n"
+"\tmovq data, %rdx\n"
+"\tshr $0x10, %edx\n"
+"\tjne shrl32_with_0x10_jump\n"
+"\tshrl32_with_0x10_cont:\n"
+"\tmovq %rdx, result\n"
+"\tpopq %rdx\n"
+"\tret\n"
+"\tshrl32_with_0x10_jump:\n"
+"\tmov $0xdeaddead, %edx\n"
+"\tjmp shrl32_with_0x10_cont\n"
+);
+
+
+int main ( void )
+{
+ char *p;
+
+ printf("\nshrl 0x10 with unitialised bits\n");
+ ULong *notinitialised = malloc(sizeof(ULong)); // Not initialised data.
+ data = *notinitialised;
+ p = (char*) &data;
+ p[0] = 0x11;
+ // p[1] = 0x22;
+ p[2] = 0x33;
+ p[3] = 0x44;
+
+ shrl32_with_0x10();
+
+ printf("non zero jump on p[2..3] 0x%016llx\n", result);
+
+ data = *notinitialised;
+ p = (char*) &data;
+ p[0] = 0x00;
+ // p[1] = 0x00;
+ p[2] = 0x00;
+ p[3] = 0x00;
+
+ shrl32_with_0x10();
+
+ printf("zero jump on p[2..3] 0x%016llx\n", result);
+ return 0;
+}
Added: trunk/memcheck/tests/amd64/shr_edx.stderr.exp
==============================================================================
(empty)
Added: trunk/memcheck/tests/amd64/shr_edx.stdout.exp
==============================================================================
--- trunk/memcheck/tests/amd64/shr_edx.stdout.exp (added)
+++ trunk/memcheck/tests/amd64/shr_edx.stdout.exp Tue Jul 12 21:48:31 2016
@@ -0,0 +1,4 @@
+
+shrl 0x10 with unitialised bits
+non zero jump on p[2..3] 0x00000000deaddead
+zero jump on p[2..3] 0x0000000000000000
Added: trunk/memcheck/tests/amd64/shr_edx.vgtest
==============================================================================
--- trunk/memcheck/tests/amd64/shr_edx.vgtest (added)
+++ trunk/memcheck/tests/amd64/shr_edx.vgtest Tue Jul 12 21:48:31 2016
@@ -0,0 +1,2 @@
+prog: shr_edx
+vgopts: -q
|
|
From: <sv...@va...> - 2016-07-11 21:10:54
|
Author: iraisr
Date: Mon Jul 11 22:10:47 2016
New Revision: 15904
Log:
Ignore pselect_sigmask_null executable.
Part of fix for BZ#364413.
Modified:
trunk/none/tests/ (props changed)
trunk/none/tests/pselect_sigmask_null.c
Modified: trunk/none/tests/pselect_sigmask_null.c
==============================================================================
--- trunk/none/tests/pselect_sigmask_null.c (original)
+++ trunk/none/tests/pselect_sigmask_null.c Mon Jul 11 22:10:47 2016
@@ -1,5 +1,5 @@
/* Make sure handling of NULL sigmask is correct.
- https://bugs.kde.org/show_bug.cgi?id=XXX
+ https://bugs.kde.org/show_bug.cgi?id=364413
We might try to make a copy and adjust the mask.
Testcase provided by Paul Eggert <eg...@cs...> */
|
|
From: <sv...@va...> - 2016-07-11 21:05:10
|
Author: iraisr
Date: Mon Jul 11 22:05:03 2016
New Revision: 15903
Log:
Set executable protection on schedctl pages only when necessary.
n-i-bz
Modified:
trunk/configure.ac
trunk/coregrind/m_syswrap/syswrap-solaris.c
Modified: trunk/configure.ac
==============================================================================
--- trunk/configure.ac (original)
+++ trunk/configure.ac Mon Jul 11 22:05:03 2016
@@ -3604,6 +3604,51 @@
[Define to 1 if fpregset_t defines struct _fpchip_state])
fi
+
+# Solaris-specific check determining if schedctl page shared between kernel
+# and userspace program is executable (illumos, older Solaris) or not (newer
+# Solaris).
+#
+# C-level symbol: SOLARIS_SCHEDCTL_PAGE_EXEC
+# Automake-level symbol: none
+#
+AC_MSG_CHECKING([if schedctl page is executable (Solaris-specific)])
+AC_RUN_IFELSE([AC_LANG_PROGRAM([[
+#include <assert.h>
+#include <fcntl.h>
+#include <procfs.h>
+#include <schedctl.h>
+#include <stdio.h>
+#include <unistd.h>
+]], [[
+ schedctl_t *scp = schedctl_init();
+ if (scp == NULL)
+ return 1;
+
+ int fd = open("/proc/self/map", O_RDONLY);
+ assert(fd >= 0);
+
+ prmap_t map;
+ ssize_t rd;
+ while ((rd = read(fd, &map, sizeof(map))) == sizeof(map)) {
+ if (map.pr_vaddr == ((uintptr_t) scp & PAGEMASK)) {
+ fprintf(stderr, "%#lx [%zu] %s\n", map.pr_vaddr, map.pr_size,
+ (map.pr_mflags & MA_EXEC) ? "x" : "no-x");
+ return (map.pr_mflags & MA_EXEC);
+ }
+ }
+
+ return 1;
+]])], [
+solaris_schedctl_page_exec=no
+AC_MSG_RESULT([no])
+], [
+solaris_schedctl_page_exec=yes
+AC_MSG_RESULT([yes])
+AC_DEFINE([SOLARIS_SCHEDCTL_PAGE_EXEC], 1,
+ [Define to 1 if you have the schedctl page executable.])
+])
+
else
AM_CONDITIONAL(SOLARIS_SUN_STUDIO_AS, false)
AM_CONDITIONAL(SOLARIS_XPG_SYMBOLS_PRESENT, false)
Modified: trunk/coregrind/m_syswrap/syswrap-solaris.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-solaris.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-solaris.c Mon Jul 11 22:05:03 2016
@@ -9427,7 +9427,10 @@
/* Returned address points to a block in a mapped page. */
if (!VG_(am_find_anon_segment)(a)) {
Addr page = VG_PGROUNDDN(a);
- UInt prot = VKI_PROT_READ | VKI_PROT_WRITE | VKI_PROT_EXEC;
+ UInt prot = VKI_PROT_READ | VKI_PROT_WRITE;
+# if defined(SOLARIS_SCHEDCTL_PAGE_EXEC)
+ prot |= VKI_PROT_EXEC;
+# endif /* SOLARIS_SCHEDCTL_PAGE_EXEC */
UInt flags = VKI_MAP_ANONYMOUS;
/* The kernel always allocates one page for the sc_shared struct. */
SizeT size = VKI_PAGE_SIZE;
|
|
From: <sv...@va...> - 2016-07-10 21:18:06
|
Author: philippe
Date: Sun Jul 10 22:17:58 2016
New Revision: 15902
Log:
Fix 365273 - Invalid write to stack location reported after signal handler runs
Analysis and patch by Earl Chew
Tested on x86/amd64/ppc64
Modified:
trunk/NEWS
trunk/coregrind/m_signals.c
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Sun Jul 10 22:17:58 2016
@@ -127,6 +127,7 @@
364413 pselect sycallwrapper mishandles NULL sigmask
364728 Power PC, missing support for several HW registers in
get_otrack_shadow_offset_wrk()
+365273 Invalid write to stack location reported after signal handler runs
n-i-bz Fix incorrect (or infinite loop) unwind on RHEL7 x86 and amd64
n-i-bz massif --pages-as-heap=yes does not report peak caused by mmap+munmap
Modified: trunk/coregrind/m_signals.c
==============================================================================
--- trunk/coregrind/m_signals.c (original)
+++ trunk/coregrind/m_signals.c Sun Jul 10 22:17:58 2016
@@ -2519,6 +2519,7 @@
Bool VG_(extend_stack)(ThreadId tid, Addr addr)
{
SizeT udelta;
+ Addr new_stack_base;
/* Get the segment containing addr. */
const NSegment* seg = VG_(am_find_nsegment)(addr);
@@ -2536,14 +2537,15 @@
vg_assert(seg_next != NULL);
udelta = VG_PGROUNDUP(seg_next->start - addr);
+ new_stack_base = seg_next->start - udelta;
VG_(debugLog)(1, "signals",
- "extending a stack base 0x%lx down by %lu\n",
- seg_next->start, udelta);
+ "extending a stack base 0x%lx down by %lu"
+ " new base 0x%lx to cover 0x%lx\n",
+ seg_next->start, udelta, new_stack_base, addr);
Bool overflow;
if (! VG_(am_extend_into_adjacent_reservation_client)
( seg_next->start, -(SSizeT)udelta, &overflow )) {
- Addr new_stack_base = seg_next->start - udelta;
if (overflow)
VG_(umsg)("Stack overflow in thread #%u: can't grow stack to %#lx\n",
tid, new_stack_base);
@@ -2555,7 +2557,7 @@
/* When we change the main stack, we have to let the stack handling
code know about it. */
- VG_(change_stack)(VG_(clstk_id), addr, VG_(clstk_end));
+ VG_(change_stack)(VG_(clstk_id), new_stack_base, VG_(clstk_end));
if (VG_(clo_sanity_level) > 2)
VG_(sanity_check_general)(False);
|
|
From: Rhys K. <rhy...@gm...> - 2016-07-10 17:11:17
|
Hello Julian, I gather from your recent commits to valgrind updating the bug status tracker, you are preparing for the typical September annual major release. Accordingly, I've opened a meta tracker bug for macOS Sierra (10.12) support. This is Apple's next major operating system release, with a publicly communicated release date in the northern hemisphere's fall 2016. https://bugs.kde.org/show_bug.cgi?id=365327 Whilst we aren't at full support for previous OS X releases, at least this time around my prior experience bringing up valgrind in a basic way on new macOS release(s) at or soon after public release of the OS should be beneficial. Let's continue to watch that Bugzilla report and discuss through September 2016. Regards, Rhys |
|
From: Rich C. <rc...@wi...> - 2016-07-05 16:35:13
|
On Mon, 4 Jul 2016 09:13:28 -0700 "Earl Chew" <ear...@ya...> wrote: > > I believe I have found a problem with handling of signals in a > > multithreaded program. > > Here is a candidate patch against 3.11, though I'm unsure if it's taking > the right approach: The best thing to do is to open a bug and attach your testcase and patch to it as attachments. With a working testcase anyone can duplicate your results and comment on your proposed fix. Rich -- Rich Coe rc...@wi... |
|
From: Lionel C. <lio...@gm...> - 2016-07-05 14:36:10
|
Why duplicate so much code when you could do: armv7*|arm) Also, arm* always overrides armv7*, so armv7 never gets a match. Lionel On 5 July 2016 at 08:20, Heinrich Schuchardt <xyp...@gm...> wrote: > Both Debian and OpenWRT may have value host_cpu="arm" for armhf > systems, cf. > > http://anonscm.debian.org/cgit/collab-maint/valgrind.git/tree/debian/patches/09_fix-armhf-detect.patch > > Signed-off-by: Heinrich Schuchardt <xyp...@gm...> > --- > configure.ac | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/configure.ac b/configure.ac > index dd4fcb9..ceb88ee 100644 > --- a/configure.ac > +++ b/configure.ac > @@ -234,6 +234,11 @@ case "${host_cpu}" in > ARCH_MAX="s390x" > ;; > > + arm*) > + AC_MSG_RESULT([ok (${host_cpu})]) > + ARCH_MAX="arm" > + ;; > + > armv7*) > AC_MSG_RESULT([ok (${host_cpu})]) > ARCH_MAX="arm" > -- > 2.1.4 > > > ------------------------------------------------------------------------------ > Attend Shape: An AT&T Tech Expo July 15-16. Meet us at AT&T Park in San > Francisco, CA to explore cutting-edge tech and listen to tech luminaries > present their vision of the future. This family event has something for > everyone, including kids. Get more information and register today. > http://sdm.link/attshape > _______________________________________________ > Valgrind-developers mailing list > Val...@li... > https://lists.sourceforge.net/lists/listinfo/valgrind-developers -- Lionel |
|
From: <sv...@va...> - 2016-07-05 08:41:15
|
Author: sewardj
Date: Tue Jul 5 09:41:07 2016
New Revision: 15901
Log:
Finish first-pass classification of bugs reported up to 4 July 2016.
Modified:
trunk/NEWS
trunk/docs/internals/3_11_BUGSTATUS.txt
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Tue Jul 5 09:41:07 2016
@@ -75,12 +75,16 @@
354392 unhandled amd64-solaris syscall: 171
354797 Vbit test does not include Iops for Power 8 instruction support
354883 tst->os_state.pthread - magic_delta assertion failure on OSX 10.11
+ == 361351
+ == 362920
354933 Fix documentation of --kernel-variant=android-no-hw-tls option
355188 valgrind should intercept all malloc related global functions
355454 do not intercept malloc related symbols from the runtime linker
355455 stderr.exp of test cases wrapmalloc and wrapmallocstatic overconstrained
356044 Dwarf line info reader misinterprets is_stmt register
356393 valgrind (vex) crashes because isZeroU happened
+ == 363497
+ == 364497
356817 valgrind.h triggers compiler errors on MSVC when defining NVALGRIND
357833 Setting RLIMIT_DATA to zero breaks with linux 4.5+
357871 pthread_spin_destroy not properly wrapped
@@ -95,27 +99,33 @@
359703 s390: wire up separate socketcalls system calls
359724 getsockname might crash - deref_UInt should call safe_to_deref
359733 amd64 implement ld.so strchr/index override like x86
-359829 PowerPC test none/tests/ppc64/test_isa_2_07.c uninitialized memory
- references was fixed.
+359767 Valgrind does not support the IBM POWER ISA 3.0 instructions
+359829 Power PC test suite none/tests/ppc64/test_isa_2_07.c uses
+ uninitialized data
359871 Incorrect mask handling in ppoll
360008 Contents of Power vr registers contents is not printed correctly when
the --vgdb-shadow-registers=yes option is used
+360035 POWER PC instruction bcdadd and bcdsubtract generate result with
+ non-zero shadow bits
360425 arm64 unsupported instruction ldpsw
+ == 364435
360519 none/tests/arm64/memory.vgtest might fail with newer gcc
360749 kludge for multiple .rodata sections on Solaris no longer needed
360752 raise the number of reserved fds in m_main.c from 10 to 12
+361207 Valgrind does not support the IBM POWER ISA 3.0 instructions, part 2
361354 ppc64[le]: wire up separate socketcalls system calls
361226 s390x: risbgn (EC59) not implemented
361926 Unhandled Solaris syscall: sysfs(84)
362009 Valgrind dumps core on unimplemented functionality before threads are created
+362329 Valgrind does not support the IBM POWER ISA 3.0 instructions, part 3
362894 missing (broken) support for wbit field on mtfsfi instruction (ppc64)
-360035 POWER PC instruction bcdadd and bcdsubtract generate result with non-zero shadow bits
363680 add renameat2() support
363705 arm64 missing syscall name_to_handle_at and open_by_handle_at
363714 ppc64 missing syscalls sync, waitid and name_to/open_by_handle_at
+363858 Add IBM ISA 3.0 support, patch set 4
364058 clarify in manual limitations of array overruns detections
364413 pselect sycallwrapper mishandles NULL sigmask
-364728 Power PC, missing support for several HW registrs in
+364728 Power PC, missing support for several HW registers in
get_otrack_shadow_offset_wrk()
n-i-bz Fix incorrect (or infinite loop) unwind on RHEL7 x86 and amd64
Modified: trunk/docs/internals/3_11_BUGSTATUS.txt
==============================================================================
--- trunk/docs/internals/3_11_BUGSTATUS.txt (original)
+++ trunk/docs/internals/3_11_BUGSTATUS.txt Tue Jul 5 09:41:07 2016
@@ -26,6 +26,8 @@
357873 libstdc++ unhandled instruction: 0xF 0xC7 0xF0 0x89
[== 353370, fixed, RDRAND ?]
357932 vex amd64->IR: 0xF2 0x49 0xF 0x5D and 0xF2 0x49 0xF 0x5F
+359952 Unrecognised PCMPESTRM variants
+360415 amd64 instructions ADCX and ADOX are not implemented in VEX
=== VEX/arm ============================================================
@@ -37,16 +39,20 @@
356823 Unsupported ARM instruction: stlex
357673 crash if I try to run valgrind with a binary link with libcurl
[IR sanity check failure]
+362934 [AsusWRT] Arm v7 illegal instruction
=== VEX/arm64 ==========================================================
357338 Unhandled instruction for SHA instructions libcrypto Boring SSL
+359838 arm64: Unhandled instruction 0xD5033F5F (clrex)
+360378 arm64: Unhandled instruction 0x5E280844 (sha1h s4, s2)
=== VEX/x86 ============================================================
355231 Unhandled Instruction Bytes (SSE4, vmovdqu, "0xC5 0xFA 0x6F 0x2")
357059 x86: SSE cvtpi2ps with memory source does transition to MMX state
[Also relevant for amd64. Not sure this is really a bug.]
+358856 unhandled instruction bytes: 0xC4 0xE2 0x7B 0xF7
=== VEX/mips ===========================================================
@@ -54,8 +60,13 @@
=== VEX/ppc ============================================================
+361405 disInstr(ppc): unhandled instruction: 0xFF81010C
+364948 Add IBM ISA 3.0 support, patch set 5
+
=== VEX/s390x ==========================================================
+361226 s390x: risbgn (EC59) not implemented
+
=== VEX general ========================================================
=== Syscalls/ioctls on Linux ===========================================
@@ -74,6 +85,21 @@
[== 345414, still open]
358620 WARNING: unhandled syscall: 357
[arm32, 3.7.0, also an unhandled insn]
+359705 memcheck causes segfault on a dynamically-linked test from
+ rustlang's test suite on i686
+360429 Warning: noted but unhandled ioctl 0x530d with no size/direction hints.
+360574 Wrong parameter type for an ashmem ioctl() call on Android and ARM64
+361615 Inconsistent termination when an instrumented multithreaded process
+ is terminated by signal
+361726 WARNING:unhandled syscall on ppc64
+361770 Missing F_ADD_SEALS
+362892 test apk in android5.0.2,after fix the bug 344802,android log
+ "Unable to create protected region in stack for implicit overflow
+ check. Reason: Out of memory size: 4096"
+362939 test apk in android 5.0 or most,at 0x6A23AB4:
+ art::Thread::InstallImplicitProtection() (in /system/lib/libart.so)
+ [initimg problems on Android]
+364359 Valgrind crashes on fcntl(F_SETFL, O_NONBLOCK, fd)
=== Syscalls/ioctls on OSX =============================================
@@ -85,11 +111,16 @@
353192 Debug info/data section not detected on AMD64
355197 Too strong assert in variable debug info code
+359181 Buffer Overflow during Demangling
=== Tools/Memcheck =====================================================
352364 ppc64: --expensive-definedness-checks=yes is not quite working here
353282 False uninitialised memory after bittwiddling
+358980 32 byte leak reported when code uses dlopen and links against pthread
+361504 dlopen()/dlclose() and shared object usage check [wishlist]
+361810 valgrind duplicate stdin after fork
+364279 False "Uninitialized" on atomic_compare_exchange
=== Tools/DRD ==========================================================
@@ -101,6 +132,9 @@
358213 helgrind bar_bad testcase hangs
with new glibc pthread barrier implementation
[Also DRD is affected]
+360557 helgrind reports data race which I can't see (involves rwlocks)
+ [probably a legit bug]
+363740 Possible data race in vgPlain_amd64_linux_REDIR_FOR_vgettimeofday
=== Tools/SGCheck ======================================================
@@ -125,13 +159,19 @@
=== other/arm ==========================================================
+362935 [AsusWRT] Assertion 'sizeof(TTEntryC) <= 88' failed
+364533 Process terminating with default action of signal 4 (SIGILL): dumping
+ core, : at 0x4000E7C: ??? (in /lib/ld-uClibc.so.0)
+
=== other/s390 =========================================================
+361253 [s390x] ex_clone.c:42: undefined reference to `pthread_create'
+
=== other/tilegx =======================================================
=== other/Android ======================================================
-=== other/OS X ========================================================
+=== other/OS X =========================================================
351855 Possible false positive on OS X with setlocale
352384 mmap-FIXED failed in UME (load_segment2)
@@ -143,8 +183,12 @@
== 258140 [still open]
354809 Error message for unsupported platform is unhelpful
356122 Apparent infinite loop calling GLib g_get_user_special_dir() function
+359264 Memcheck shows 2,064 bytes possibly lost and 20,036 suppressed bytes
+ in simplistic program on OS X El Capitan
+363123 SIGSEGV on Mac OS with very simple threaded code
+ == 349128 [still open]
-=== other/Win32 =======================================================
+=== other/Win32 ========================================================
=== GDB server =========================================================
@@ -157,29 +201,37 @@
352395 Please provide SVN revision info in --version
358569 Unhandled instructions cause creation of "orphan" stack traces
in XML output
+359645 [patch] "You need libc6-dbg" help message could be more helpful
+ with 32-bit target on-64-bit arch
=== MPI ================================================================
=== Documentation ======================================================
+362953 Request for an update to the Valgrind Developers page
+
=== Uncategorised/run ==================================================
351692 Dumps created by valgrind are not readable by gdb
356457 valgrind: m_mallocfree.c:2042 (vgPlain_arena_free):
Assertion 'blockSane(a, b)' failed.
[Possible V memory corruption?]
+359249 valgrind unable to load 64-bit linux executable
+ linked with -mcmodel=medium
+360571 Error about the Android Runtime reading below the stack pointer on ARM
+362223 valgrind: m_commandline.c:79 (read_dot_valgrindrc):
+ Assertion 'n >= 0 && n <= stat_buf.size+1' failed.
+362680 --error-exitcode not honored when file descriptor leaks are found
-=== Uncategorised/build=================================================
-
-========================================================================
-========================================================================
-========================================================================
+=== Uncategorised/build ================================================
-========================================================================
-========================================================================
-========================================================================
+358697 valgrind.h: Some code remains even when defining NVALGRIND
+359202 Add musl libc configure/compile
+359920 Configure fails with relative DESTDIR
+362033 undeclared identifier build failures for getpid(), usleep(),
+ and getuid() [Valkyrie]
-Wed 2 Dec 16:01:07 CET 2015
+=== Intel Compiler problems ============================================
357010 drd regression tests fail to compile with Intel compiler
357011 Memcheck regression tests do not generate expected frame numbers
@@ -188,115 +240,11 @@
if compiled with intel compiler
357014 Helgrind regression tests do not match expected results
if compiled with intel compiler
-357033 VALGRIND_DO_QUICK_LEAK_CHECK reports leaked and dubious memory
- as reachable in intel-compiled
-357034 Inlined functions are not reported for intel-compiled applications.
-357035 Uninitialized variable of type double is reported twice
- in intel-compiled application.
-357037 Line numbers are occasionally displayed incorrectly
- in intel-compiled applications
-
-Thu 28 Jan 13:20:02 CET 2016
-358697 valgrind.h: Some code remains even when defining NVALGRIND
-358856 unhandled instruction bytes: 0xC4 0xE2 0x7B 0xF7
-358980 32 byte leak reported when code uses dlopen and links against pthread
-358988 rdrand support missing: 0x48 0xF 0xC7 0xF1 ...
-359133 m_deduppoolalloc.c:258 (vgPlain_allocEltDedupPA):
- Assertion 'eltSzB <= ddpa->poolSzB' failed.
-359181 Buffer Overflow during Demangling
-359201 futex syscall "skips" argument 5 if op is FUTEXT_WAIT_BITSET
-359202 Add musl libc configure/compile
-359249 valgrind unable to load 64-bit linux executable
- linked with -mcmodel=medium
-359264 Memcheck shows 2,064 bytes possibly lost and 20,036 suppressed bytes
- in simplistic program on OS X El Capitan
-359289 s390x: popcnt (B9E1) not implemented
-359472 The Power PC vsubuqm instruction doesn't always give the correct result.
-359503 Add missing syscalls for aarch64 (arm64)
-359524 bt, btc, btr and bts instruction improperly translated by VEX on x86-64
-359645 [patch] "You need libc6-dbg" help message could be more helpful
- with 32-bit target on-64-bit arch
-359703 s390: wire up separate socketcalls system calls
-359705 memcheck causes segfault on a dynamically-linked test from
- rustlang's test suite on i686
-359724 getsockname syscall might crash - deref_UInt should check make
- sure it is safe to deref
-359733 amd64 implement strchr/index override to avoid need for suppression
- and redirection like x86
-359767 Valgrind does not support the IBM POWER ISA 3.0 instructions
-359829 Power PC test suite none/tests/ppc64/test_isa_2_07.c uses
- uninitialzed data
-359838 arm64: Unhandled instruction 0xD5033F5F (clrex)
-359871 Incorrect mask handling in ppoll
-359920 Configure fails with relative DESTDIR
-359950 Wrong result comparing doubles on x87
-359952 Unrecognised PCMPESTRM variants
-360008 Contents of Power vr registers contents is not printed correctly
- when the --vgdb-shadow-registers=yes option is used.
-360035 POWER PC instruction bcdadd and bcdsubtract generate result with
- non-zero shadow bits
-360188 Valgrind does not build
-360378 arm64: Unhandled instruction 0x5E280844 (sha1h s4, s2)
-360415 amd64 instructions ADCX and ADOX are not implemented in VEX
-360425 arm64 unsupported instruction ldpsw
-360429 Warning: noted but unhandled ioctl 0x530d with no size/direction hints.
-360519 none/tests/arm64/memory.vgtest might fail with newer gcc
-360557 helgrind reports data race which I can't see (involves rwlocks)
-360571 Error about the Android Runtime reading below the stack pointer on ARM
-360574 Wrong parameter type for an ashmem ioctl() call on Android and ARM64
-360749 kludge for multiple .rodata sections on Solaris no longer needed
-360752 raise the number of reserved fds in m_main.c from 10 to 12
-361207 Valgrind does not support the IBM POWER ISA 3.0 instructions, part 2
-361226 s390x: risbgn (EC59) not implemented
-361253 [s390x] ex_clone.c:42: undefined reference to `pthread_create'
-361351 Assertion failure analyzing SDL_Init()
-361354 ppc64[le]: wire up separate socketcalls system calls
-361405 disInstr(ppc): unhandled instruction: 0xFF81010C
-361504 dlopen()/dlclose() and shared object usage check
-361615 Inconsistent termination when an instrumented multithreaded process
- is terminated by signal
-361726 WARNING:unhandled syscall on ppc64
-361770 Missing F_ADD_SEALS
-361810 valgrind duplicate stdin after fork
-361926 unhandled x86-solaris syscall: 84
-362009 Valgrind dumps core on unimplemented functionality before threads
- are created
-362033 undeclared identifier build failures for getpid(), usleep(),
- and getuid()
-362223 valgrind: m_commandline.c:79 (read_dot_valgrindrc):
- Assertion 'n >= 0 && n <= stat_buf.size+1' failed.
-362329 Valgrind does not support the IBM POWER ISA 3.0 instructions, part 3
-362680 --error-exitcode not honored when file descriptor leaks are found
-362892 test apk in android5.0.2,after fix the bug 344802,android log
- "Unable to create protected region in stack for implicit overflow
- check. Reason: Out of memory size: 4096"
-362894 missing (broken) support for wbit field on mtfsfi instruction (ppc64)
-362920 valgrind refuses to execute pkcs11-tool binary from OpenSC:
- assertion 'tst->os_state.pthread - magic_delta == self' failed
-362934 [AsusWRT] Arm v7 illegal instruction
-362935 [AsusWRT] Assertion 'sizeof(TTEntryC) <= 88' failed
-362939 test apk in android 5.0 or most,at 0x6A23AB4:
- art::Thread::InstallImplicitProtection() (in /system/lib/libart.so)
-362953 Request for an update to the Valgrind Developers page
-363123 SIGSEGV on Mac OS with very simple threaded code
-363497 Crash if i run valgrind on any working program -> valgrind:
- the 'impossible' happened: LibVEX called failure_exit()
-363680 add renameat2() support
-363705 arm64 missing syscall name_to_handle_at and open_by_handle_at
-363714 ppc64 missing syscalls sync, waitid and name_to/open_by_handle_at
-363740 Possible data race in vgPlain_amd64_linux_REDIR_FOR_vgettimeofday
-363858 Add IBM ISA 3.0 support, patch set 4
-364058 array overruns are not detected
-364279 False "Uninitialized" on atomic_compare_exchange
-364359 Valgrind crashes on fcntl(F_SETFL, O_NONBLOCK, fd)
-364413 pselect sycallwrapper mishandles NULL sigmask
-364435 Crash - Unrecognized instruction for Arm64 LDPSW
-364497 Run valgrind on nginx
-364533 Process terminating with default action of signal 4 (SIGILL): dumping
- core, : at 0x4000E7C: ??? (in /lib/ld-uClibc.so.0)
-364728 Power PC, missing support for several HW registrs i
- n get_otrack_shadow_offset_wrk()
-364948 Add IBM ISA 3.0 support, patch set 5
+========================================================================
+========================================================================
+========================================================================
+========================================================================
+========================================================================
Mon 4 Jul 13:10:42 CEST 2016
|
|
From: Heinrich S. <xyp...@gm...> - 2016-07-05 06:20:57
|
Both Debian and OpenWRT may have value host_cpu="arm" for armhf systems, cf. http://anonscm.debian.org/cgit/collab-maint/valgrind.git/tree/debian/patches/09_fix-armhf-detect.patch Signed-off-by: Heinrich Schuchardt <xyp...@gm...> --- configure.ac | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configure.ac b/configure.ac index dd4fcb9..ceb88ee 100644 --- a/configure.ac +++ b/configure.ac @@ -234,6 +234,11 @@ case "${host_cpu}" in ARCH_MAX="s390x" ;; + arm*) + AC_MSG_RESULT([ok (${host_cpu})]) + ARCH_MAX="arm" + ;; + armv7*) AC_MSG_RESULT([ok (${host_cpu})]) ARCH_MAX="arm" -- 2.1.4 |
|
From: <sv...@va...> - 2016-07-04 16:57:44
|
Author: sewardj
Date: Mon Jul 4 17:57:36 2016
New Revision: 15900
Log:
Initial triage of a bunch of bugs from Oct 2015 to Feb 2016, roughly.
Modified:
trunk/NEWS
trunk/docs/internals/3_11_BUGSTATUS.txt
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Mon Jul 4 17:57:36 2016
@@ -59,28 +59,34 @@
303877 valgrind doesn't support compressed debuginfo sections.
345307 Warning about "still reachable" memory when using libstdc++ from gcc 5
348345 Assertion fails for negative lineno
+351804 Crash on generating suppressions for "printf" call on OS X 10.10
353083 arm64 doesn't implement various xattr system calls
353084 arm64 doesn't support sigpending system call
+353137 www: update info for Supported Platforms
+353138 www: update "The Valgrind Developers" page
353370 don't advertise RDRAND in cpuid for Core-i7-4910-like avx2 machine
353398 WARNING: unhandled amd64-solaris syscall: 207
353660 XML in auxwhat tag not escaping reserved symbols properly
353680 s390x: Crash with certain glibc versions due to non-implemented TBEGIN
+353802 ELF debug info reader confused with multiple .rodata sections
353891 Assert 'bad_scanned_addr < VG_ROUNDDN(start+len, sizeof(Addr))' failed
353917 unhandled amd64-solaris syscall fchdir(120)
353920 unhandled amd64-solaris syscall: 170
354392 unhandled amd64-solaris syscall: 171
-354797 Added vbit tester support for PPC 64 isa 2.07 iops
+354797 Vbit test does not include Iops for Power 8 instruction support
354883 tst->os_state.pthread - magic_delta assertion failure on OSX 10.11
354933 Fix documentation of --kernel-variant=android-no-hw-tls option
355188 valgrind should intercept all malloc related global functions
-355455 stderr.exp of test cases wrapmalloc and wrapmallocstatic overconstrained
355454 do not intercept malloc related symbols from the runtime linker
+355455 stderr.exp of test cases wrapmalloc and wrapmallocstatic overconstrained
356044 Dwarf line info reader misinterprets is_stmt register
+356393 valgrind (vex) crashes because isZeroU happened
356817 valgrind.h triggers compiler errors on MSVC when defining NVALGRIND
357833 Setting RLIMIT_DATA to zero breaks with linux 4.5+
357871 pthread_spin_destroy not properly wrapped
-357887 Fix a file handle leak. VG_(fclose) did not close the file
+357887 Calls to VG_(fclose) do not close the file descriptor
358030 support direct socket calls on x86 32bit (new in linux 4.3)
+358478 drd/tests/std_thread.cpp doesn't build with GCC6
359133 Assertion 'eltSzB <= ddpa->poolSzB' failed
359201 futex syscall "skips" argument 5 if op is FUTEX_WAIT_BITSET
359289 s390x: popcnt (B9E1) not implemented
@@ -117,6 +123,10 @@
n-i-bz false positive leaks due to aspacemgr merging non heap segments with heap segments.
n-i-bz Fix ppoll_alarm exclusion on OS X
n-i-bz Document brk segment limitation, reference manual in limit reached msg.
+n-i-bz Fix clobber list in none/tests/amd64/xacq_xrel.c [valgrind r15737]
+n-i-bz Bump allowed shift value for "add.w reg, sp, reg, lsl #N" [vex r3206]
+
+
Release 3.11.0 (22 September 2015)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -499,8 +509,7 @@
351140 arm64 syscalls setuid (146) and setresgid (149) not implemented
351386 Solaris: Cannot run ld.so.1 under Valgrind
351474 Fix VG_(iseqsigset) as obvious
-351534 Fix incorrect header guard
-351632 Fix UNKNOWN fcntl 97 on OS X 10.11
+351531 Typo in /include/vki/vki-xen-physdev.h header guard
351756 Intercept platform_memchr$VARIANT$Haswell on OS X
351858 ldsoexec support on Solaris
351873 Newer gcc doesn't allow __builtin_tabortdc[i] in ppc32 mode
Modified: trunk/docs/internals/3_11_BUGSTATUS.txt
==============================================================================
--- trunk/docs/internals/3_11_BUGSTATUS.txt (original)
+++ trunk/docs/internals/3_11_BUGSTATUS.txt Mon Jul 4 17:57:36 2016
@@ -5,40 +5,122 @@
=== VEX/amd64 ==========================================================
+351491 Unrecognised instruction in library compiled with -mavx -ffast-math -O3
+351726 vex amd64->IR: 0xC5 0xF3 0xC2 0x15 0xEB 0x7C 0x2 0x0
+ [JRS: potentially serious, miscalculated next %RIP]
+352549 Valgrind (whether with memchek or callgrind) crashes with
+ "unhandled instruction bytes"
+ [Probably invalid]
+353384 unhandled instruction bytes: 0x66 0xF 0x3A 0x62 0xD1 0x62 0x41 0x3B
+ __intel_sse4_strpbrk
+353727 unhandled instruction bytes: 0x66 0xF 0x3A 0x62 0xD1 0x72 0x45 0x3B
+ __intel_sse4_strspn
+354931 Analyze of qt app results in incompatible processor message
+ [Gentoo stupidity]
+356138 vex amd64->IR: 0x8F 0xEA 0x78 0x10 0xD2 0x6 0x6 0x0
+356392 FPU control word not updated on FYL2X with ST(0) = 0
+ [Also relevant for x86]
+356611 vex amd64->IR: 0x8F 0xEA 0xF8 0x10 0xC9 0x3 0x1D 0x0
+ [== 328357, still open]
+356715 vex amd64->IR: 0xC4 0xE2 0x7D 0x13 0x4 0x4A 0xC5 0xFC
+357873 libstdc++ unhandled instruction: 0xF 0xC7 0xF0 0x89
+ [== 353370, fixed, RDRAND ?]
+357932 vex amd64->IR: 0xF2 0x49 0xF 0x5D and 0xF2 0x49 0xF 0x5F
+
=== VEX/arm ============================================================
+352630 valgrind: Unrecognised instruction at address 0x4fc4d33.
+354274 arm: unhandled instruction: 0xEBAD 0x0AC1 (sub.w sl, sp, r1, lsl #3)
+355526 disInstr(arm): unhandled instruction: 0x1823E91
+n-i-bz Remove limit on strd's negative immediates
+ [dev@, Michael Daniels, 19 Nov 2015, easy fix, should land]
+356823 Unsupported ARM instruction: stlex
+357673 crash if I try to run valgrind with a binary link with libcurl
+ [IR sanity check failure]
+
=== VEX/arm64 ==========================================================
+357338 Unhandled instruction for SHA instructions libcrypto Boring SSL
+
=== VEX/x86 ============================================================
+355231 Unhandled Instruction Bytes (SSE4, vmovdqu, "0xC5 0xFA 0x6F 0x2")
+357059 x86: SSE cvtpi2ps with memory source does transition to MMX state
+ [Also relevant for amd64. Not sure this is really a bug.]
+
=== VEX/mips ===========================================================
+356112 mips: replace addi with addiu
+
=== VEX/ppc ============================================================
=== VEX/s390x ==========================================================
=== VEX general ========================================================
-=== Syscalls/ioctls ====================================================
+=== Syscalls/ioctls on Linux ===========================================
+
+351632 UNKNOWN fcntl 97 on OS X 10.11
+352742 Custom allocator using sbrk() fails after about 800MB when running
+ under memcheck
+352767 Wine/valgrind: Warning: noted but unhandled ioctl 0x5307 with
+ no size/direction hints. (CDROMSTOP)
+355803 Add Lustre's IOC_MDC_GETFILESTRIPE ioctl [has patch]
+356676 Unhandled arm64-linux syscalls: 125 and 126 (sched_get_priority_max/min)
+ [may already be fixed by 359503]
+356678 unhandled arm64-linux syscall: 232 (mincore)
+ [may already be fixed by 359503]
+357781 unhandled amd64-linux syscall: 317
+ [== 345414, still open]
+358620 WARNING: unhandled syscall: 357
+ [arm32, 3.7.0, also an unhandled insn]
+
+=== Syscalls/ioctls on OSX =============================================
+
+352021 Signals are ignored in OS X 10.10
+353346 WARNING: unhandled amd64-darwin syscall: unix:330
+ == 211362 [not fixed]
=== Debuginfo reader ===================================================
+353192 Debug info/data section not detected on AMD64
+355197 Too strong assert in variable debug info code
+
=== Tools/Memcheck =====================================================
+352364 ppc64: --expensive-definedness-checks=yes is not quite working here
+353282 False uninitialised memory after bittwiddling
+
=== Tools/DRD ==========================================================
+356374 Assertion 'DRD_(g_threadinfo)[tid].pt_threadid
+ != INVALID_POSIX_THREADID' failed
+
=== Tools/Helgrind =====================================================
+358213 helgrind bar_bad testcase hangs
+ with new glibc pthread barrier implementation
+ [Also DRD is affected]
+
=== Tools/SGCheck ======================================================
=== Tools/Massif =======================================================
=== Tools/Cachegrind ===================================================
+=== Tools/Callgrind ====================================================
+
+356675 callgrind test apk in android 5.0.2
+ [Unclear what this is. Might also be ARM or Android specific]
+
=== Tools/Lackey =======================================================
=== other/mips =========================================================
+351282 valgrind 3.10.1 MIPS softfloat build broken with GCC 4.9.3 /
+ binutils 2.25.1
+352197 mips: mmap2() not wrapped correctly for page size > 4096
+
=== other/ppc ==========================================================
=== other/arm ==========================================================
@@ -51,18 +133,42 @@
=== other/OS X ========================================================
+351855 Possible false positive on OS X with setlocale
+352384 mmap-FIXED failed in UME (load_segment2)
+352567 Assertion tres.status == VexTransOK failed in m_translate.c
+ vgPlain_translate
+353470 memcheck/tests/execve2 fails on OS X 10.11
+353471 memcheck/tests/x86/xor-undef-x86 fails on OS X 10.11
+354428 Bad report memory leak in OS X 10.11
+ == 258140 [still open]
+354809 Error message for unsupported platform is unhelpful
+356122 Apparent infinite loop calling GLib g_get_user_special_dir() function
+
=== other/Win32 =======================================================
=== GDB server =========================================================
+351792 vgdb doesn't support remote file transfers
+356174 Enhance the embedded gdbserver to allow LLDB to use it
+
=== Output =============================================================
+351857 confusing error message about valid command line option
+352395 Please provide SVN revision info in --version
+358569 Unhandled instructions cause creation of "orphan" stack traces
+ in XML output
+
=== MPI ================================================================
=== Documentation ======================================================
=== Uncategorised/run ==================================================
+351692 Dumps created by valgrind are not readable by gdb
+356457 valgrind: m_mallocfree.c:2042 (vgPlain_arena_free):
+ Assertion 'blockSane(a, b)' failed.
+ [Possible V memory corruption?]
+
=== Uncategorised/build=================================================
========================================================================
@@ -73,120 +179,8 @@
========================================================================
========================================================================
-351140 arm64 syscalls setuid (146) and setresgid (149) not implemented
-351282 valgrind 3.10.1 MIPS softfloat build broken with GCC 4.9.3 /
- binutils 2.25.1
-351386 Cannot run ld.so.1 under Valgrind
-351391 Some blog CSS does not render properly under Firefox or Safari
-351474 coregrind/m_libcsignal.c:134: bad test ?
-351491 Unrecognised instruction in library compiled with -mavx -ffast-math -O3
-351531 Typo in /include/vki/vki-xen-physdev.h header guard
-351536 Valgrind should track map areas of unloaded libraries
-351632 UNKNOWN fcntl 97 on OS X 10.11
-351692 Dumps created by valgrind are not readable by gdb
-351726 vex amd64->IR: 0xC5 0xF3 0xC2 0x15 0xEB 0x7C 0x2 0x0
-351742 jump to illegal address without stack backtrace
-351756 Spurious errors on OS X 10.10.5 using Valgrind 3.11 SVN
-351792 vgdb doesn't support remote file transfers
-351804 Crash on generating suppressions for `printf`
- call on OS X 10.10 / Valgrind 3.11 SVN
-351848 Option for showing addresses of memory leaks?
-351855 Possible false positive on OS X with setlocale
-351857 confusing error message about valid command line option
-351858 ldsoexec support on Solaris
-351873 Newer gcc doesn't allow __builtin_tabortdc[i] in ppc32 mode
-352021 Signals are ignored in OS X 10.10
-352059 Fix unhandled sysarch cmd 132 (AMD64_GET_XFPUSTATE) on FreeBSD/amd64
-352130 helgrind reports false races for printfs using mempcpy
- manipulating FILE* state
-352183 s390x: none/tests/s390x/fpext is failing
-352197 mips: mmap2() not wrapped correctly for page size > 4096
-352284 s390 Conditional jump or move depends on uninitialised value(s)
- in vfprintf
-352320 arm64 crash on none/tests/nestedfs
-352364 ppc64: --expensive-definedness-checks=yes is not quite working here
-352384 mmap-FIXED failed in UME (load_segment2)
-352395 Please provide SVN revision info in --version
-352549 Valgrind (whether with memchek or callgrind) crashes with
- "unhandled instruction bytes"
-352567 Assertion tres.status == VexTransOK failed in m_translate.c
- vgPlain_translate
-352586 Missing emulation of the PowerPC "mbar" instruction
-352630 valgrind: Unrecognised instruction at address 0x4fc4d33.
-352742 Custom allocator using sbrk() fails after about 800MB when running
- under memcheck
-352765 Vbit test fails on Power 6
-352767 Wine/valgrind: Warning: noted but unhandled ioctl 0x5307 with
- no size/direction hints. (CDROMSTOP)
-352768 The mbar instruction is missing from the Power PC support
-352769 Power PC program priority register (PPR) is not supported
-353083 arm64 doesn't implement various xattr system calls
-353084 arm64 doesn't support sigpending system call
-353137 www: update info for Supported Platforms
-353138 www: update "The Valgrind Developers" page
-353192 Debug info/data section not detected on AMD64
-353282 False uninitialised memory after bittwiddling
-353346 WARNING: unhandled amd64-darwin syscall: unix:330
-353370 amd64->IR: 0x48 0xF 0xC7 0xF0 0x72 0x4 0xFF 0xC9
-353384 unhandled instruction bytes: 0x66 0xF 0x3A 0x62 0xD1 0x62 0x41 0x3B
- __intel_sse4_strpbrk
-353470 memcheck/tests/execve2 fails on OS X 10.11
-353471 memcheck/tests/x86/xor-undef-x86 fails on OS X 10.11
-353660 XML in auxwhat tag not escaping ampersand properly
-353680 s390x: Crash with certain glibc versions due to non-implemented TBEGIN
-353727 unhandled instruction bytes: 0x66 0xF 0x3A 0x62 0xD1 0x72 0x45 0x3B
- __intel_sse4_strspn
-353802 ELF debug info reader confused with multiple .rodata sections
-353891 testcase memcheck/tests/leak-segv-jmp: Memcheck: mc_leakcheck.c:1045
- (lc_scan_memory): Assertion 'bad_scanned_addr < VG_ROUNDDN(start+len,
- sizeof(Addr))' failed.
-353920 unhandled amd64-solaris syscall: 170
-354274 arm: unhandled instruction: 0xEBAD 0x0AC1 (sub.w sl, sp, r1, lsl #3)
-354392 unhandled amd64-solaris syscall: 171
-354428 Bad report memory leak in OS X 10.11
-354797 Vbit test does not include Iops for Power 8 instruction support
-354809 Error message for unsupported platform is unhelpful
-354882 Valgrind 3.11.0 (and 3.12.0-SVN) fails to build on OSX 10.11 El Capitan
-354883 Assertion failure with valgrind-3.11.0 on OSX 10.11
-354909 strlen() provokes false positives on icc -O2 (Linux)
-354931 Analyze of qt app results in incompatible processor message
-354933 Android READMEs talk of --kernel-variant=android-emulator-no-hw-tls,
- which doesn't exist
-
-Mon 9 Nov 21:57:00 CET 2015
-
-355188 valgrind should intercept all malloc related global functions by default
-355197 Too strong assert in variable debug info code
-355231 Unhandled Instruction Bytes (SSE4, vmovdqu, "0xC5 0xFA 0x6F 0x2")
-355454 do not intercept malloc related symbols from the runtime linker
-355455 expected stderr of test cases wrapmalloc and wrapmallocstatic
- overconstrained
-355526 disInstr(arm): unhandled instruction: 0x1823E91
-355803 Add Lustre's IOC_MDC_GETFILESTRIPE ioctl
-356044 Dwarf line info reader misinterprets is_stmt register
-n-i-bz [PATCH] Fix clobber list in none/tests/amd64/xacq_xrel.c
-n-i-bz [PATCH][VEX] Bump allowed shift value for "add.w reg, sp, reg, lsl #N"
-n-i-bz [PATCH][VEX] Remove limit on strd's negative immediates
-356112 mips: replace addi with addiu
-356122 Apparent infinite loop calling the GLib g_get_user_special_dir() function
-356138 vex amd64->IR: 0x8F 0xEA 0x78 0x10 0xD2 0x6 0x6 0x0
-356174 Enhance the embedded gdbserver to allow LLDB to use it
-
Wed 2 Dec 16:01:07 CET 2015
-356374 Assertion 'DRD_(g_threadinfo)[tid].pt_threadid
- != INVALID_POSIX_THREADID' failed
-356392 FPU control word not updated on FYL2X with ST(0) = 0
-356393 valgrind (vex) crashes because isZeroU happened
-356457 valgrind: m_mallocfree.c:2042 (vgPlain_arena_free):
- Assertion 'blockSane(a, b)' failed.
-356611 vex amd64->IR: 0x8F 0xEA 0xF8 0x10 0xC9 0x3 0x1D 0x0
-356675 callgrind test apk in android 5.0.2
-356676 Unhandled arm64-linux syscalls: 125 and 126 (sched_get_priority_max/min)
-356678 unhandled arm64-linux syscall: 232 (mincore)
-356715 vex amd64->IR: 0xC4 0xE2 0x7D 0x13 0x4 0x4A 0xC5 0xFC
-356817 valgrind.h triggers compiler errors on MSVC when defining NVALGRIND
-356823 Unsupported ARM instruction: stlex
357010 drd regression tests fail to compile with Intel compiler
357011 Memcheck regression tests do not generate expected frame numbers
if compiled with intel compiler
@@ -201,26 +195,6 @@
in intel-compiled application.
357037 Line numbers are occasionally displayed incorrectly
in intel-compiled applications
-357059 x86: SSE cvtpi2ps with memory source does transition to MMX state
-357294 cannot start valgrind with tool dhat
-357338 Unhandled instruction for SHA instructions libcrypto Boring SSL
-357673 crash if I try to run valgrind with a binary link with libcurl
-357734 "unhandled instruction 0x1AC12D8C" for ARM64/AARCH64
-357781 unhandled amd64-linux syscall: 317
-357833 Valgrind is broken on recent linux kernel
-357871 pthread_spin_destroy not properly
-357873 libstdc++ unhandled instruction: 0xF 0xC7 0xF0 0x89
-357887 Calls to VG_(fclose) does not close the file descriptor
-357928 Thread 1: status = VgTs_Runnable
-357932 vex amd64->IR: 0xF2 0x49 0xF 0x5D and 0xF2 0x49 0xF 0x5F
-358030 support direct socket calls on x86 32bit (new in linux 4.3)
-358213 helgrind bar_bad testcase hangs
- with new glibc pthread barrier implementation
-358478 drd/tests/std_thread.cpp doesn't build with GCC6
-358569 Unhandled instructions cause creation of "orphan" stack traces
- in XML output
-358620 WARNING: unhandled syscall: 357
-358637 produces invalid xml
Thu 28 Jan 13:20:02 CET 2016
|
|
From: Earl C. <ear...@ya...> - 2016-07-04 16:13:38
|
> I believe I have found a problem with handling of signals in a
> multithreaded program.
Here is a candidate patch against 3.11, though I'm unsure if it's taking
the right approach:
+ /home/earl/bin/git diff coregrind/m_signals.c
diff --git a/coregrind/m_signals.c b/coregrind/m_signals.c
index e105afa..66fffa9 100644
--- a/coregrind/m_signals.c
+++ b/coregrind/m_signals.c
@@ -2515,10 +2515,11 @@ Bool VG_(extend_stack)(ThreadId tid, Addr addr)
VG_(debugLog)(1, "signals",
"extending a stack base 0x%lx down by %lu\n",
seg_next->start, udelta);
+
+ Addr new_stack_base = seg_next->start - udelta;
Bool overflow;
if (! VG_(am_extend_into_adjacent_reservation_client)
( seg_next->start, -(SSizeT)udelta, &overflow )) {
- Addr new_stack_base = seg_next->start - udelta;
if (overflow)
VG_(umsg)("Stack overflow in thread #%u: can't grow stack to
%#lx\n",
tid, new_stack_base);
@@ -2530,7 +2531,7 @@ Bool VG_(extend_stack)(ThreadId tid, Addr addr)
/* When we change the main stack, we have to let the stack handling
code know about it. */
- VG_(change_stack)(VG_(clstk_id), addr, VG_(clstk_end));
+ VG_(change_stack)(VG_(clstk_id), new_stack_base, VG_(clstk_end));
if (VG_(clo_sanity_level) > 2)
VG_(sanity_check_general)(False);
Earl
|