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From: <sv...@va...> - 2016-06-04 15:35:05
|
Author: rhyskidd
Date: Sat Jun 4 16:34:56 2016
New Revision: 15891
Log:
Fix tst->os_state.pthread - magic_delta assertion failure on OSX 10.11
bz#354883
Whilst I’ve seen different magic_delta values on one of my older development machines (Intel Nehalem-based), enough other users have reported success with this change.
If this causes regressions, please report your hardware details in our Bugzilla.
Regression test output on OS X 10.11
Before:
== 601 tests, 223 stderr failures, 12 stdout failures, 0 stderrB failures, 0 stdoutB failures, 31 post failures ==
After:
== 601 tests, 223 stderr failures, 12 stdout failures, 0 stderrB failures, 0 stdoutB failures, 31 post failures ==
Modified:
trunk/NEWS
trunk/coregrind/m_syswrap/syswrap-amd64-darwin.c
trunk/coregrind/m_syswrap/syswrap-x86-darwin.c
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Sat Jun 4 16:34:56 2016
@@ -70,6 +70,7 @@
353920 unhandled amd64-solaris syscall: 170
354392 unhandled amd64-solaris syscall: 171
354797 Added vbit tester support for PPC 64 isa 2.07 iops
+354883 tst->os_state.pthread - magic_delta assertion failure on OSX 10.11
354933 Fix documentation of --kernel-variant=android-no-hw-tls option
355188 valgrind should intercept all malloc related global functions
355455 stderr.exp of test cases wrapmalloc and wrapmallocstatic overconstrained
Modified: trunk/coregrind/m_syswrap/syswrap-amd64-darwin.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-amd64-darwin.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-amd64-darwin.c Sat Jun 4 16:34:56 2016
@@ -479,10 +479,8 @@
UWord magic_delta = 0;
# elif DARWIN_VERS == DARWIN_10_7 || DARWIN_VERS == DARWIN_10_8
UWord magic_delta = 0x60;
-# elif DARWIN_VERS == DARWIN_10_9 || DARWIN_VERS == DARWIN_10_10
+# elif DARWIN_VERS == DARWIN_10_9 || DARWIN_VERS == DARWIN_10_10 || DARWIN_VERS == DARWIN_10_11
UWord magic_delta = 0xE0;
-# elif DARWIN_VERS == DARWIN_10_11
- UWord magic_delta = 0x100;
# else
# error "magic_delta: to be computed on new OS version"
// magic_delta = tst->os_state.pthread - self
Modified: trunk/coregrind/m_syswrap/syswrap-x86-darwin.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-x86-darwin.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-x86-darwin.c Sat Jun 4 16:34:56 2016
@@ -427,10 +427,8 @@
UWord magic_delta = 0;
# elif DARWIN_VERS == DARWIN_10_7 || DARWIN_VERS == DARWIN_10_8
UWord magic_delta = 0x48;
-# elif DARWIN_VERS == DARWIN_10_9 || DARWIN_VERS == DARWIN_10_10
+# elif DARWIN_VERS == DARWIN_10_9 || DARWIN_VERS == DARWIN_10_10 || DARWIN_VERS == DARWIN_10_11
UWord magic_delta = 0xB0;
-# elif DARWIN_VERS == DARWIN_10_11
- UWord magic_delta = 0x100;
# else
# error "magic_delta: to be computed on new OS version"
// magic_delta = tst->os_state.pthread - self
|
|
From: Matthias S. <zz...@ge...> - 2016-06-01 18:22:52
|
Am 01.06.2016 um 13:06 schrieb Yasushi SHOJI:
> Hi list,
>
> On Fri, 29 Apr 2016 00:52:02 +0900,
> svn...@pu... wrote:
>>
>> Author: sewardj
>> Date: Thu Apr 28 16:52:01 2016
>> New Revision: 15875
>>
>> Log:
>> Un-break ppc32-linux following r15784. It appears that ppc32-ELF
>> layout constraints are different from x86-ELF and so the assertion on
>> the sizeof(TTEntryC) fails on ppc32-linux.
>>
>> Modified:
>> trunk/coregrind/m_transtab.c
>>
>> Modified: trunk/coregrind/m_transtab.c
>> ==============================================================================
>> --- trunk/coregrind/m_transtab.c (original)
>> +++ trunk/coregrind/m_transtab.c Thu Apr 28 16:52:01 2016
>> @@ -2448,10 +2448,18 @@
>> if (sizeof(HWord) == 8) {
>> vg_assert(sizeof(TTEntryH) <= 32);
>> vg_assert(sizeof(TTEntryC) <= 112);
>> - } else if (sizeof(HWord) == 4) {
>> + }
>> + else if (sizeof(HWord) == 4) {
>> vg_assert(sizeof(TTEntryH) <= 20);
>> +# if defined(VGP_ppc32_linux)
>> + /* ppc32-linux is weird. It thinks alignof(ULong) == 8 and so the
>> + structure is larger than on other 32 bit targets. */
>
> It's also 8 bytes on my armhf debian sid as I checked.
>
> I noticed this when I built trunk r15889 on my 32 ARM board. When I
> run, it failed with:
>
> ./vg-in-place true
> ==7907== Memcheck, a memory error detector
> ==7907== Copyright (C) 2002-2015, and GNU GPL'd, by Julian Seward et al.
> ==7907== Using Valgrind-3.12.0.SVN and LibVEX; rerun with -h for copyright info
> ==7907== Command: true
> ==7907==
>
> valgrind: m_transtab.c:2462 (vgPlain_init_tt_tc): Assertion 'sizeof(TTEntryC) <= 88' failed.
> Segmentation fault
>
Maybe some of these asserts should be re-written to be checked at
compile time. There are some versions of a STATIC_ASSERT macro that
could be used.
Regards
Matthias
|
Author: carll
Date: Wed Jun 1 19:13:19 2016
New Revision: 15890
Log:
Power PC Add test suite support for ISA 3.0, part 3
The test suite support for the Power PC ISA 3.0 instructions added in
VEX commit 3220 is added in this commit.
Note, this is part 2 of 5. The NEWS file will be updated when the ISA 3.0
support is complete.
valgrind bugzilla 362329
Modified:
trunk/none/tests/ppc64/Makefile.am
trunk/none/tests/ppc64/ppc64_helpers.h
trunk/none/tests/ppc64/test_isa_3_0.c
trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp
trunk/none/tests/ppc64/test_isa_3_0_altivec.vgtest
Modified: trunk/none/tests/ppc64/Makefile.am
==============================================================================
--- trunk/none/tests/ppc64/Makefile.am (original)
+++ trunk/none/tests/ppc64/Makefile.am Wed Jun 1 19:13:19 2016
@@ -136,7 +136,7 @@
test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_2_07_FLAG) \
@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
test_isa_3_0_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_0_FLAG) \
- @FLAG_M64@ $( $(BUILD_FLAGS_ISA_3_0)
+ @FLAG_M64@ $(BUILD_FLAGS_ISA_3_0)
test_isa_2_06_part3_LDADD = -lm
test_dfp1_LDADD = -lm
Modified: trunk/none/tests/ppc64/ppc64_helpers.h
==============================================================================
--- trunk/none/tests/ppc64/ppc64_helpers.h (original)
+++ trunk/none/tests/ppc64/ppc64_helpers.h Wed Jun 1 19:13:19 2016
@@ -181,6 +181,24 @@
printf("%s(SO)", verbose ? " 0x8=Overflow" : "");
}
+/* Extract one CR field */
+static int extract_cr_rn(unsigned long local_cr,unsigned long rn) {
+ unsigned int masked_cr;
+ unsigned long shifted_value;
+
+ shifted_value = local_cr >> ( ( (7 - rn) * 4 ) );
+ masked_cr = shifted_value & 0xf;
+ return masked_cr;
+}
+
+/* Display one CR field */
+static void dissect_cr_rn(unsigned long local_cr, unsigned long rn) {
+ unsigned int masked_cr;
+
+ masked_cr = extract_cr_rn(local_cr, rn);
+ __dissect_cr(masked_cr);
+}
+
/* dissect the fpscr bits that are valid under valgrind.
* Valgrind itself only tracks the C and FPCC fields from the
* FPSCR.
@@ -259,6 +277,41 @@
0 0 1 0 1 +Infinity
*/
+static void dissect_fpscr_result_value_class(unsigned long local_fpscr) {
+ if (local_fpscr & FPCC_C_BIT) {
+ if (local_fpscr & FPCC_FL_BIT)
+ printf("-Denormalized");
+
+ else if (local_fpscr & FPCC_FG_BIT)
+ printf("+Denormalized");
+
+ else if (local_fpscr & FPCC_FE_BIT)
+ printf("-Zero ");
+
+ else if (local_fpscr & FPCC_FU_BIT)
+ printf("Quiet NaN ");
+
+ } else {
+ if (local_fpscr & FPCC_FL_BIT) {
+ if (local_fpscr & FPCC_FU_BIT)
+ printf("-Infinity ");
+
+ else
+ printf("-Normalized ");
+
+ } else if (local_fpscr & FPCC_FG_BIT) {
+ if (local_fpscr & FPCC_FU_BIT)
+ printf("+Infinity ");
+
+ else
+ printf("+Normalized ");
+
+ if (local_fpscr & FPCC_FE_BIT)
+ printf("+Zero ");
+ }
+ }
+}
+
/* Interpret the fields in the FPCC as they apply to the DCMX checks.
* The 'Match' indicator will typically be evaluated by the caller.
*
@@ -274,6 +327,20 @@
* 7 0x7f ALL bits set.
*/
+static void dissect_fpscr_dcmx_indicator(unsigned long local_fpscr) {
+ if (verbose > 2) printf("fpscr_cc:%lx ", local_fpscr & (FPCC_FPRF_MASK) );
+
+ // See if the data class of the src value matches the set DCMX bits.
+ if (verbose > 1) printf("%s ", (local_fpscr&FPCC_FE_BIT) ? "Match":"");
+
+ // Display the sign bit of the src value.
+ if (verbose > 1) printf("SRC sign:%s ", (local_fpscr&FPCC_FL_BIT) ? "-" : "+");
+
+ // The src value can be either a SP or DP value, this indicates
+ // if it is a valid SP value.
+ if (verbose > 1) printf("%s ", (local_fpscr&FPCC_FE_BIT) ? "SP" : "");
+}
+
/* DFP helpers for bcd-to-dpd, dpd-to-bcd, misc.
* pulled from vex/.../host_generic_simd64.c
*/
@@ -1406,6 +1473,35 @@
printf("\n");
}
+static void print_dcmx_field(unsigned long local_dcmx) {
+ /* Note - this splats out the local_dxmc field from the form used to
+ * globally pass it, with a single set bit, into the functions that use
+ * it. The actual DCMX field is a bit-field from 0x00 to 0x3f. If
+ * multiple bits are ever set, this function and the way it is passed
+ * into the users will need to be updated. This does not handle
+ * multiple bits being set.
+ */
+
+ printf(" DCMX=[");
+
+ switch(local_dcmx) {
+ case 0: printf("ALL"); break;
+ case 1: printf("NaN"); break;
+ case 2: printf("+inf"); break;
+ case 3: printf("-inf"); break;
+ case 4: printf("+zero"); break;
+ case 5: printf("-zero"); break;
+ case 6: printf("+denormal"); break;
+ case 7: printf("-denormal"); break;
+ default: printf("other"); break;
+ }
+
+ if (verbose > 3)
+ printf(" %lx", local_dcmx);
+
+ printf("] ");
+}
+
#define MAX_CHAR_ARGS_ARRAY_SIZE 128
static unsigned char * char_args;
Modified: trunk/none/tests/ppc64/test_isa_3_0.c
==============================================================================
--- trunk/none/tests/ppc64/test_isa_3_0.c (original)
+++ trunk/none/tests/ppc64/test_isa_3_0.c Wed Jun 1 19:13:19 2016
@@ -210,6 +210,8 @@
/* Family */
PPC_INTEGER = 0x00010000,
PPC_ALTIVEC = 0x00030000,
+ PPC_ALTIVEC_QUAD = 0x00040000,
+ PPC_ALTIVEC_DOUBLE = 0x00050000,
PPC_MISC = 0x00080000,
PPC_FAMILY_MASK = 0x000F0000,
@@ -416,6 +418,14 @@
__asm__ __volatile__ ("vrldnm %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
}
+static void test_xviexpdp(void) {
+ __asm__ __volatile__ ("xviexpdp %0, %1, %2 " : "+wa" (vec_xt): "wa" (vec_xa), "wa" (vec_xb));
+}
+
+static void test_xviexpsp(void) {
+ __asm__ __volatile__ ("xviexpsp %0, %1, %2 " : "+wa" (vec_xt): "wa" (vec_xa), "wa" (vec_xb));
+}
+
static test_list_t testgroup_vsx_absolute[] = {
{ &test_vabsdub , "vabsdub" },
{ &test_vabsduh , "vabsduh" },
@@ -437,6 +447,8 @@
{ &test_vrldnm , "vrldnm" },
{ &test_vrldmi , "vrldmi" },
{ &test_vbpermd , "vbpermd" },
+ { &test_xviexpdp , "xviexpdp" },
+ { &test_xviexpsp , "xviexpsp" },
{ NULL , NULL },
};
@@ -752,11 +764,41 @@
__asm__ __volatile__ ("xxbrq %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
}
+static void test_xvxexpdp(void) {
+ __asm__ __volatile__ ("xvxexpdp %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static void test_xvxexpsp(void) {
+ __asm__ __volatile__ ("xvxexpsp %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static void test_xvxsigdp(void) {
+ __asm__ __volatile__ ("xvxsigdp %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static void test_xvxsigsp(void) {
+ __asm__ __volatile__ ("xvxsigsp %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static void test_xsxexpdp(void) {
+ __asm__ __volatile__ ("xsxexpdp %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
+static void test_xsxsigdp(void) {
+ __asm__ __volatile__ ("xsxsigdp %x0, %x1 " : "=wa" (vec_xt) : "wa" (vec_xa));
+}
+
static test_list_t testgroup_vector_logical_one[] = {
{ &test_xxbrh , "xxbrh" },
{ &test_xxbrw , "xxbrw" },
{ &test_xxbrd , "xxbrd" },
{ &test_xxbrq , "xxbrq" },
+ { &test_xvxexpdp, "xvxexpdp" },
+ { &test_xvxexpsp, "xvxexpsp" },
+ { &test_xvxsigdp, "xvxsigdp" },
+ { &test_xvxsigsp, "xvxsigsp" },
+ { &test_xsxexpdp, "xsxexpdp" },
+ { &test_xsxsigdp, "xsxsigdp" },
{ NULL , NULL },
};
@@ -823,6 +865,55 @@
__asm__ __volatile__ ("stxsihx %x0, 14, 15" : "=wa" (vec_xt));
}
+/* d-form vsx load/store */
+static void test_lxsd_0(void) {
+ __asm__ __volatile__ ("lxsd %0, 0(%1) " : "=v"(vec_xt) : "r"(r14));
+}
+
+static void test_stxsd_0(void) {
+ __asm__ __volatile__ ("stxsd %0, 0(%1)" : "=v"(vec_xt) : "r"(r14));
+}
+
+static void test_lxsd_16(void) {
+ __asm__ __volatile__ ("lxsd %0, 16(%1)" : "=v"(vec_xt) : "r"(r14));
+}
+
+static void test_stxsd_16(void) {
+ __asm__ __volatile__ ("stxsd %0, 16(%1)" : "=v"(vec_xt) : "r"(r14));
+}
+
+static void test_lxssp_0(void) {
+ __asm__ __volatile__ ("lxssp %0, 0(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static void test_stxssp_0(void) {
+ __asm__ __volatile__ ("stxssp %0, 0(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static void test_lxssp_16(void) {
+ __asm__ __volatile__ ("lxssp %0, 16(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static void test_stxssp_16(void) {
+ __asm__ __volatile__ ("stxssp %0, 16(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static void test_lxv_0(void) {
+ __asm__ __volatile__ ("lxv %0, 0(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static void test_stxv_0(void) {
+ __asm__ __volatile__ ("stxv %0, 0(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static void test_lxv_16(void) {
+ __asm__ __volatile__ ("lxv %0, 16(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
+static void test_stxv_16(void) {
+ __asm__ __volatile__ ("stxv %0, 16(%1)" : "=wa"(vec_xt) : "r"(r14));
+}
+
static test_list_t testgroup_vector_scalar_loadstore_length[] = {
{ &test_lxvl , "lxvl " },
{ &test_lxsibzx , "lxsibzx " },
@@ -830,6 +921,18 @@
{ &test_stxvl , "stxvl " },
{ &test_stxsibx , "stxsibx " },
{ &test_stxsihx , "stxsihx " },
+ { &test_lxsd_0 , "lxsd 0 " },
+ { &test_stxsd_0 , "stxsd 0 " },
+ { &test_lxsd_16 , "lxsd 16 " },
+ { &test_stxsd_16 , "stxsd 16 " },
+ { &test_lxssp_0 , "lxssp 0 " },
+ { &test_stxssp_0 , "stxssp 0 " },
+ { &test_lxssp_16 , "lxssp 16 " },
+ { &test_stxssp_16, "stxssp 16" },
+ { &test_lxv_0 , "lxv 0 " },
+ { &test_stxv_0 , "stxv 0 " },
+ { &test_lxv_16 , "lxv 16 " },
+ { &test_stxv_16 , "stxv 16 " },
{ NULL , NULL },
};
@@ -966,6 +1069,281 @@
{ NULL , NULL },
};
+#define XSCMPEXPDP(x) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xscmpexpdp %0, %1, %2"::"i"(x), "v"(vec_xa), "v"(vec_xb));\
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+static void test_xscmpexpdp(void) {
+ switch(x_index) {
+ case 0: XSCMPEXPDP(0); break;
+ case 1: XSCMPEXPDP(1); break;
+ case 2: XSCMPEXPDP(2); break;
+ case 3: XSCMPEXPDP(3); break;
+ case 4: XSCMPEXPDP(4); break;
+ case 5: XSCMPEXPDP(5); break;
+ case 6: XSCMPEXPDP(6); break;
+ case 7: XSCMPEXPDP(7); break;
+ default:
+ printf("Unhandled shift value for %s %x\n", __FUNCTION__, x_index);
+ };
+}
+
+static test_list_t testgroup_vector_scalar_compare_exp_double[] = {
+ { &test_xscmpexpdp , "xscmpexpdp " },
+ { NULL , NULL },
+};
+
+#define XSTSTDCQP(R,DCMX) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xststdcqp %0, %1, %2":: "i"(R), "wa"(vec_xb), "i"(DCMX)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+#define XSTSTDCDP(R,DCMX) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xststdcdp %0, %1, %2":: "i"(R), "wa"(vec_xb), "i"(DCMX)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+#define XSTSTDCSP(R,DCMX) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xststdcsp %0, %1, %2":: "i"(R), "wa"(vec_xb), "i"(DCMX)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+#define XVTSTDCDP(R,DCMX) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xvtstdcdp %0, %1, %2": "=wa"(vec_xt) : "wa"(vec_xb), "i"(DCMX)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+#define XVTSTDCSP(R,DCMX) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xvtstdcsp %0, %1, %2": "=wa"(vec_xt) : "wa"(vec_xb), "i"(DCMX)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+static void test_xststdcqp(void) {
+ switch(x_index) {
+ case 1: XSTSTDCQP(3, 0x01); break; /* NaN */
+ case 2: XSTSTDCQP(3, 0x02); break; /* +inf */
+ case 3: XSTSTDCQP(3, 0x04); break; /* -inf */
+ case 4: XSTSTDCQP(3, 0x08); break; /* +zero */
+ case 5: XSTSTDCQP(3, 0x10); break; /* -zero */
+ case 6: XSTSTDCQP(3, 0x20); break; /* +denormal */
+ case 7: XSTSTDCQP(3, 0x40); break; /* -denormal */
+ case 0: XSTSTDCQP(3, 0x7f); break; /* all of the above */
+ }
+}
+
+static void test_xststdcdp(void) {
+ switch(x_index) {
+ case 1: XSTSTDCDP(3, 0x01); break; /* NaN */
+ case 2: XSTSTDCDP(3, 0x02); break; /* +inf */
+ case 3: XSTSTDCDP(3, 0x04); break; /* -inf */
+ case 4: XSTSTDCDP(3, 0x08); break; /* +zero */
+ case 5: XSTSTDCDP(3, 0x10); break; /* -zero */
+ case 6: XSTSTDCDP(3, 0x20); break; /* +denormal */
+ case 7: XSTSTDCDP(3, 0x40); break; /* -denormal */
+ case 0: XSTSTDCDP(3, 0x7f); break; /* all of the above */
+ }
+}
+
+static void test_xststdcsp(void) {
+ switch(x_index) {
+ case 1: XSTSTDCSP(3, 0x01); break; /* NaN */
+ case 2: XSTSTDCSP(3, 0x02); break; /* +inf */
+ case 3: XSTSTDCSP(3, 0x04); break; /* -inf */
+ case 4: XSTSTDCSP(3, 0x08); break; /* +zero */
+ case 5: XSTSTDCSP(3, 0x10); break; /* -zero */
+ case 6: XSTSTDCSP(3, 0x20); break; /* +denormal */
+ case 7: XSTSTDCSP(3, 0x40); break; /* -denormal */
+ case 0: XSTSTDCSP(3, 0x7f); break; /* all of the above */
+ }
+}
+
+static void test_xvtstdcdp(void) {
+ switch(x_index) {
+ case 1: XVTSTDCDP(3, 0x01); break; /* NaN */
+ case 2: XVTSTDCDP(3, 0x02); break; /* +inf */
+ case 3: XVTSTDCDP(3, 0x04); break; /* -inf */
+ case 4: XVTSTDCDP(3, 0x08); break; /* +zero */
+ case 5: XVTSTDCDP(3, 0x10); break; /* -zero */
+ case 6: XVTSTDCDP(3, 0x20); break; /* +denormal */
+ case 7: XVTSTDCDP(3, 0x40); break; /* -denormal */
+ case 0: XVTSTDCDP(3, 0x7f); break; /* all of the above */
+ }
+}
+
+/* Note: Due to the test groupings, the input for the xvtstdcsp test is
+ * actually 'double'. It is good enough for this test, but may wish to break
+ * this one out eventually.
+ */
+static void test_xvtstdcsp(void) {
+ switch(x_index) {
+ case 1: XVTSTDCSP(3, 0x01); break; /* NaN */
+ case 2: XVTSTDCSP(3, 0x02); break; /* +inf */
+ case 3: XVTSTDCSP(3, 0x04); break; /* -inf */
+ case 4: XVTSTDCSP(3, 0x08); break; /* +zero */
+ case 5: XVTSTDCSP(3, 0x10); break; /* -zero */
+ case 6: XVTSTDCSP(3, 0x20); break; /* +denormal */
+ case 7: XVTSTDCSP(3, 0x40); break; /* -denormal */
+ case 0: XVTSTDCSP(3, 0x7f); break; /* all of the above */
+ }
+}
+
+static test_list_t testgroup_vector_scalar_data_class[] = {
+ { &test_xststdcqp, "xststdcqp " },
+ { &test_xststdcdp, "xststdcdp " },
+ { &test_xststdcsp, "xststdcsp " },
+ { &test_xvtstdcdp, "xvtstdcdp " },
+ { &test_xvtstdcsp, "xvtstdcsp " },
+ { NULL , NULL },
+};
+
+static void test_xsiexpdp(void) {
+ __asm__ __volatile__ ("xsiexpdp %0, %1, %2 " : "+wa" (vec_xt): "r" (r14), "r" (r15));
+}
+
+static test_list_t testgroup_vector_scalar_two_double[] = {
+ { &test_xsiexpdp, "xsiexpdp" },
+ { NULL , NULL },
+};
+
+static void test_xsabsqp(void) {
+ __asm__ __volatile__ ("xsabsqp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xsxexpqp(void) {
+ __asm__ __volatile__ ("xsxexpqp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xsxsigqp(void) {
+ __asm__ __volatile__ ("xsxsigqp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xsnegqp(void) {
+ __asm__ __volatile__ ("xsnegqp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_xsnabsqp(void) {
+ __asm__ __volatile__ ("xsnabsqp %0, %1" : "+v"(vec_xt) : "v"(vec_xb));
+}
+
+static test_list_t testgroup_vector_scalar_two_quad[] = {
+ { &test_xsabsqp , "xsabsqp " },
+ { &test_xsxexpqp , "xsxexpqp " },
+ { &test_xsxsigqp , "xsxsigqp " },
+ { &test_xsnegqp , "xsnegqp " },
+ { &test_xsnabsqp , "xsnabsqp " },
+ { NULL , NULL },
+};
+
+static void test_xscpsgnqp(void) {
+ __asm__ __volatile__ ("xscpsgnqp %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static void test_xsiexpqp(void) {
+ __asm__ __volatile__ ("xsiexpqp %0, %1, %2" : "+v"(vec_xt) : "v"(vec_xa), "v"(vec_xb));
+}
+
+static test_list_t testgroup_vector_three_quad[] = {
+ { &test_xscpsgnqp , "xscpsgnqp " },
+ { &test_xsiexpqp , "xsiexpqp " },
+ { NULL , NULL },
+};
+
+#define XSCMPEXPQP(x) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xscmpexpqp %0, %1, %2" :: "i"(x), "v"(vec_xa), "v"(vec_xb)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+#define XSCMPOQP(x) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xscmpoqp %0, %1, %2" :: "i"(x), "v"(vec_xa), "v"(vec_xb)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+#define XSCMPUQP(x) \
+ SET_FPSCR_ZERO \
+ SET_CR_ZERO \
+ __asm__ __volatile__ \
+ ("xscmpuqp %0, %1, %2"::"i"(x), "v"(vec_xa), "v"(vec_xb)); \
+ GET_CR(local_cr); \
+ GET_FPSCR(local_fpscr);
+
+static void test_xscmpexpqp(void) {
+ switch(x_index) {
+ case 0: XSCMPEXPQP(0); break;
+ case 1: XSCMPEXPQP(1); break;
+ case 2: XSCMPEXPQP(2); break;
+ case 3: XSCMPEXPQP(3); break;
+ case 4: XSCMPEXPQP(4); break;
+ case 5: XSCMPEXPQP(5); break;
+ case 6: XSCMPEXPQP(6); break;
+ case 7: XSCMPEXPQP(7); break;
+ default:
+ printf("Unhandled shift value for %s %x\n", __FUNCTION__, x_index);
+ };
+}
+
+static void test_xscmpoqp(void) {
+ switch(x_index) {
+ case 0: XSCMPOQP(0); break;
+ case 1: XSCMPOQP(1); break;
+ case 2: XSCMPOQP(2); break;
+ case 3: XSCMPOQP(3); break;
+ case 4: XSCMPOQP(4); break;
+ case 5: XSCMPOQP(5); break;
+ case 6: XSCMPOQP(6); break;
+ case 7: XSCMPOQP(7); break;
+ default:
+ printf("Unhandled shift value for %s %x\n", __FUNCTION__, x_index);
+ };
+}
+
+static void test_xscmpuqp(void) {
+ switch(x_index) {
+ case 0: XSCMPUQP(0); break;
+ case 1: XSCMPUQP(1); break;
+ case 2: XSCMPUQP(2); break;
+ case 3: XSCMPUQP(3); break;
+ case 4: XSCMPUQP(4); break;
+ case 5: XSCMPUQP(5); break;
+ case 6: XSCMPUQP(6); break;
+ case 7: XSCMPUQP(7); break;
+ default:
+ printf("Unhandled shift value for %s %x\n", __FUNCTION__, x_index);
+ };
+}
+
+static test_list_t testgroup_vector_scalar_compare_quads[] = {
+ { &test_xscmpexpqp, "xscmpexpqp" },
+ { &test_xscmpoqp , "xscmpoqp " },
+ { &test_xscmpuqp , "xscmpuqp " },
+ { NULL , NULL },
+};
+
+
/* ###### begin all_tests table. */
/* table containing all of the instruction groups */
@@ -1009,6 +1387,21 @@
PPC_ALTIVEC | PPC_LOGICAL | PPC_TWO_ARGS,
},
{
+ testgroup_vector_three_quad,
+ "ppc vector three quad",
+ PPC_ALTIVEC | PPC_LOGICAL | PPC_THREE_ARGS,
+ },
+ {
+ testgroup_vector_scalar_two_quad,
+ "ppc vector scalar quad",
+ PPC_ALTIVEC_QUAD | PPC_LOGICAL | PPC_TWO_ARGS,
+ },
+ {
+ testgroup_vector_scalar_compare_quads,
+ "ppc vector scalar compare exponents quads",
+ PPC_ALTIVEC_QUAD | PPC_COMPARE,
+ },
+ {
testgroup_vsx_xxpermute,
"ppc vector permutes",
PPC_ALTIVEC | PPC_PERMUTE | PPC_THREE_ARGS,
@@ -1053,6 +1446,21 @@
"ppc one argument plus shift",
PPC_MISC | PPC_THREE_ARGS,
},
+ {
+ testgroup_vector_scalar_compare_exp_double,
+ "ppc vector scalar compare exponents doubles",
+ PPC_ALTIVEC_DOUBLE | PPC_COMPARE | PPC_COMPARE_ARGS,
+ },
+ {
+ testgroup_vector_scalar_data_class,
+ "ppc vector scalar test data class tests",
+ PPC_ALTIVEC_DOUBLE | PPC_COMPARE | PPC_ONE_ARG,
+ },
+ {
+ testgroup_vector_scalar_two_double,
+ "ppc vector scalar tests against float double two args ",
+ PPC_ALTIVEC_DOUBLE | PPC_COMPARE | PPC_TWO_ARGS,
+ },
{ NULL, NULL, 0x00000000, },
};
@@ -1515,20 +1923,18 @@
printf("%s ", instruction_name);
printf("%016lx %016lx ", vec_xt[1], vec_xt[0] );
if (uses_bits_0to7(instruction_name)) {
- printf(" &0x%lx l = 0x%2lx ",
- (long unsigned)r14, (long unsigned)r15>>56 );
+ printf(" 0x%2lx ", (long unsigned)r15>>56 );
} else {
- printf(" &0x%lx l = 0x%2lx ",
- (long unsigned)r14, (long unsigned)r15 );
+ printf(" l = 0x%2lx ", (long unsigned)r15 );
}
dump_small_buffer();
(*test_function)();
- printf("=> %016lx %016lx & %16lx %16lx", vec_xt[1], vec_xt[0],
- (long unsigned)r14, (long unsigned)r15 );
+ printf("=> %016lx %016lx & %16lx", vec_xt[1], vec_xt[0],
+ (long unsigned)r15 );
printf("\n");
}
}
@@ -1728,6 +2134,354 @@
printf("\n");
}
+#define uses_half_precision_input(instruction_name) ( \
+ (strncmp(instruction_name, "xscvhpdp", 8) == 0) || \
+ (strncmp(instruction_name, "xvcvhpsp", 8) == 0) )
+
+#define uses_single_precision_input(instruction_name) ( \
+ (strncmp(instruction_name, "xvcvsphp", 8) == 0) )
+
+#define uses_double_precision_input(instruction_name) ( \
+ (strncmp(instruction_name, "xscvdphp", 8) == 0) )
+
+#define uses_half_precision_output(instruction_name) ( \
+ (strncmp(instruction_name, "xscvdphp", 8) == 0) || \
+ (strncmp(instruction_name, "xvcvsphp", 8) == 0) )
+
+#define is_half_precision_instruction(instruction_name) ( \
+ uses_half_precision_input(instruction_name) || \
+ uses_half_precision_output(instruction_name) )
+
+/* Helper for those instructions with an unused second dword, indicating
+ * the outer loop can be short-circuited after one pass.
+ */
+#define unused_second_dword(instruction_name) ( \
+ (strncmp(instruction_name, "xscvhpdp", 8) == 0) || \
+ (strncmp(instruction_name, "xscvdphp", 8) == 0) )
+
+static void testfunction_vector_scalar_two_quad (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_flags)
+{
+ int i;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 2) {
+ if (uses_half_precision_input(instruction_name)) {
+ vec_xb = (vector unsigned long){binary16_float_vsxargs[i],
+ binary16_float_vsxargs[i+1]};
+ } else {
+ vec_xb = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ }
+
+ vec_xt = (vector unsigned long){0, 0};
+
+ printf("%s ", instruction_name);
+ printf("%016lx %016lx ", vec_xb[1], vec_xb[0]);
+
+ SET_FPSCR_ZERO
+
+ (*test_function)();
+
+ GET_FPSCR(local_fpscr);
+
+ printf("=> %016lx %016lx", vec_xt[1], vec_xt[0]);
+ dissect_fpscr(local_fpscr);
+ printf("\n");
+ }
+}
+
+static void
+testfunction_vector_scalar_compare_exp_double (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags){
+ int i,j;
+ /* Uses global variable x_index */
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_float_vsxargs - 1; i++) {
+ for (j = 0; j < nb_float_vsxargs - 1; j++) {
+ for (x_index = 2; x_index < 3; x_index++) {
+
+ /* TODO FIXME- there was a casting issue below. This incantation
+ * works, but I suspect can be simplified...
+ */
+ vec_xa = (vector unsigned long){(unsigned long)binary64_float_vsxargs[i+1], (unsigned long)binary64_float_vsxargs[i]};
+
+ vec_xb = (vector unsigned long){(unsigned long)binary64_float_vsxargs[j], (unsigned long)binary64_float_vsxargs[j+1]};
+
+ /* run each test against cleared CR and FPSCR */
+ /* Note that the SET_*_ZERO calls are not actually sufficient here,
+ * due to infrastructure between here and there that also set some
+ * of the CR bits. The condition regs are cleared here, but are
+ * also both cleared and read within the to-be-tested asm chunk to
+ * get accurate results.
+ */
+ SET_CR_ZERO
+ SET_FPSCR_ZERO
+
+ printf("%s %016lx %016lx %016lx %016lx",
+ instruction_name,
+ vec_xa[0], vec_xa[1],
+ vec_xb[0], vec_xb[1]);
+
+ if (verbose) printf(" cr#%d ", x_index);
+
+ printf(" => ");
+
+ (*test_function)();
+
+ dissect_fpscr(local_fpscr);
+ dissect_fpscr_result_value_class(local_fpscr);
+ dissect_cr_rn(local_cr, x_index);
+ printf("\n");
+ }
+ }
+ }
+}
+
+/* These instructions set the floating point condition codes. */
+/* verify logic reversal */
+#define does_not_set_floating_point_cc(instruction_name) \
+ (strncmp(instruction_name, "xvtstdcdp", 9) == 0) | \
+ (strncmp(instruction_name, "xvtstdcsp", 9) == 0)
+
+static void
+testfunction_vector_scalar_data_class (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags) {
+ int j;
+ /* x_index is used as a key into the DCMX value.
+ *
+ * BF, XB, DCMX
+ * For instruction tests called through this function, note that we are only
+ * utilizing bf (condition register) #3; where 3 was mostly randomly
+ * chosen, and has no special meaning.
+ */
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (j = 0; j < nb_float_vsxargs - 1; j++) {
+ /* for dcmx field, start with x_index=1 to skip the 'all' dcmx entry. */
+ for (x_index = 1; x_index < 8; x_index++) {
+ vec_xb[0] = float_vsxargs[j];
+ vec_xb[1] = float_vsxargs[j+1];
+ vec_xt[0] = 0x0a0a0a0a0a0a0a0a;
+ vec_xt[1] = 0x0505050505050505;
+ SET_CR_ZERO
+ SET_FPSCR_ZERO
+
+ dcmx_match = 0;
+
+ (*test_function)();
+
+ /* the local_fpscr value is gathered within the test_function call. */
+ dcmx_match = (local_fpscr & FPCC_FE_BIT);
+
+ if (dcmx_match || (verbose>2)) {
+ printf("%s %016lx, %016lx ",
+ instruction_name, vec_xb[1], vec_xb[0]);
+
+ print_dcmx_field(x_index);
+
+ if (dcmx_match)
+ printf(" => Match. ");
+
+ printf(" %016lx, %016lx ", vec_xt[1], vec_xt[0]);
+
+ dissect_cr_rn(local_cr,3);
+ dissect_fpscr_dcmx_indicator(local_fpscr);
+ printf("\n");
+ }
+
+ printf("%s %016lx, %016lx => ",
+ instruction_name, vec_xb[1], vec_xb[0]);
+
+ printf(" %016lx, %016lx\n", vec_xt[1], vec_xt[0]);
+ }
+ }
+}
+
+static void testfunction_vector_scalar_compare_quads (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags) {
+ /* Uses global variable x_index */
+ int i,j;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_float_vsxargs - 1; i++) {
+ for (j = 0; j < nb_float_vsxargs - 1; j++) {
+ for (x_index = 0; x_index < 3 ; x_index++) {
+ vec_xa[0] = float_vsxargs[i];
+ vec_xa[1] = float_vsxargs[i+1];
+ vec_xb[0] = float_vsxargs[j];
+ vec_xb[1] = float_vsxargs[j+1];
+
+ /* run each test against cleared CR and FPSCR */
+ /* Note that the SET_*_ZERO calls are not actually sufficient here,
+ * due to infrastructure between here and there that also set some
+ * of the CR bits. The condition regs are cleared here, but are
+ * also both cleared and read within the to-be-tested asm chunk
+ * to get accurate results.
+ */
+ printf("%s %016lx%016lx %016lx%016lx (cr#%d) => ",
+ instruction_name,
+ vec_xa[1], vec_xa[0],
+ vec_xb[1], vec_xb[0],
+ x_index);
+
+ SET_CR_ZERO
+ SET_FPSCR_ZERO
+
+ (*test_function)();
+
+ GET_CR(local_cr);
+ GET_FPSCR(local_fpscr);
+
+ dissect_fpscr(local_fpscr);
+ dissect_cr_rn(local_cr, x_index);
+ printf("\n");
+ }
+ }
+ }
+}
+
+static void testfunction_vector_three_special (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags){
+ /* Notes:
+ * vector instructions with two inputs, one output.
+ * vrt, vra, vrb
+ */
+ int i, j;
+ int t;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_float_vsxargs - 1; i++) {
+ for (j = 0; j < nb_float_vsxargs - 1; j++) {
+ vec_xa[0] = float_vsxargs[i];
+ vec_xa[1] = float_vsxargs[i+1];
+ vec_xb[0] = float_vsxargs[j];
+ vec_xb[1] = float_vsxargs[j+1];
+
+ for (t = 0; t < 2; t++) {
+ vec_xt[0] = (t == 0) ? 0 : 0xffffffffffffffff;
+ vec_xt[1] = (t == 0) ? 0 : 0xffffffffffffffff;
+
+ SET_FPSCR_ZERO;
+ printf("%s %016lx%016lx %016lx%016lx %016lx%016lx => ",
+ instruction_name,
+ vec_xa[1], vec_xa[0],
+ vec_xb[1], vec_xb[0],
+ vec_xt[1], vec_xt[0]);
+
+ (*test_function)();
+
+ GET_FPSCR(local_fpscr);
+
+ printf(" %016lx%016lx", vec_xt[1], vec_xt[0]);
+ dissect_fpscr(local_fpscr);
+ printf("\n");
+ }
+ }
+ }
+}
+
+#define vector_instruction_is_xvcvhpsp(instruction_name) \
+ (strncmp(instruction_name, "xvcvhpsp", 8) == 0)
+
+static void testfunction_vector_scalar_two_double(const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_test_flags) {
+ /* Notes:
+ * iterate across double values stored in xa, xb.
+ * Or, on half-word values in vec_xb.
+ * Results are in vec_xt.
+ */
+ int i, j;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_float_vsxargs - 1; i += 2) {
+ for (j = 0; j < nb_float_vsxargs - 1; j += 2) {
+ /* vec_xb is only used by the convert instructions, the other callers
+ * use the r14, r15 fields.
+ * The 16-bit converts reference every other half-word in the vector.
+ * For this reason, populate the input field with a cross-section of
+ * values.
+ */
+ printf("%s ",instruction_name);
+
+ if (uses_half_precision_input(instruction_name)) {
+ vec_xb = (vector unsigned long) {
+ binary16_float_vsxargs[i] |
+ binary16_float_vsxargs[j] << 16 |
+ binary16_float_vsxargs[i+1] << 32 |
+ binary16_float_vsxargs[j+1] << 48,
+ binary16_float_vsxargs[(nb_float_vsxargs - 1) - j - 1 ] |
+ binary16_float_vsxargs[(nb_float_vsxargs - 1) - i - 1] << 16 |
+
+ binary16_float_vsxargs[(nb_float_vsxargs - 1) - j ] << 32 |
+ binary16_float_vsxargs[(nb_float_vsxargs - 1) - i ] << 48
+ };
+ printf(" vec_xb[1] = 0x%lx, vec_xb[0] = 0x%lx ",
+ vec_xb[1], vec_xb[0]);
+
+ } else if (uses_single_precision_input(instruction_name)) {
+ vec_xb = (vector unsigned long) {
+ binary32_float_vsxargs[i] |
+ binary32_float_vsxargs[i+1] << 32,
+ binary32_float_vsxargs[nb_float_vsxargs - 1 - j ] |
+ binary32_float_vsxargs[nb_float_vsxargs - 1 - j ] << 32
+ };
+ printf(" vec_xb[1] = 0x%lx, vec_xb[0] = 0x%lx ",
+ vec_xb[1], vec_xb[0]);
+
+ } else { /* uses double */
+ r14 = binary64_float_vsxargs[i];
+ r15 = binary64_float_vsxargs[j];
+ printf(" r14 = 0x%lx, r15 = 0x%lx ", r14, r15);
+ }
+
+ vec_xt = (vector unsigned long){0, 0};
+
+ printf("%016lx %016lx ", vec_xb[1], vec_xb[0] );
+
+ if ((verbose > 2) && uses_double_precision_input(instruction_name)) {
+ dissect_binary64_float(vec_xb[1]);
+ dissect_binary64_float(vec_xb[0]);
+ }
+
+ printf(" => ");
+ SET_FPSCR_ZERO
+
+ (*test_function)();
+
+ GET_FPSCR(local_fpscr);
+ printf(" %016lx %016lx", vec_xt[1], vec_xt[0]);
+
+ if ((verbose > 2) && uses_half_precision_output(instruction_name)) {
+ dissect_double_as_16s(vec_xt[1]);
+ dissect_double_as_16s(vec_xt[0]);
+ }
+
+ /* The xvcvhpsp instruction does not set the C and FPCC fields */
+ if (!vector_instruction_is_xvcvhpsp(instruction_name))
+ dissect_fpscr(local_fpscr);
+
+ printf("\n");
+ } // j
+
+ /* If we are doing half precision conversions, the i-loop can be
+ * short-circuited to avoid duplicate input values. */
+ if (unused_second_dword(instruction_name))
+ i = nb_float_vsxargs+1;
+ } // i
+}
/* ######## begin grand testing loops. */
typedef struct insn_sel_flags_t_struct {
@@ -1788,6 +2542,8 @@
family = all_tests[i].flags & PPC_FAMILY_MASK;
if ((family == PPC_INTEGER && !seln_flags.integer) ||
(family == PPC_ALTIVEC && !seln_flags.altivec) ||
+ (family == PPC_ALTIVEC_DOUBLE && !seln_flags.altivec_double) ||
+ (family == PPC_ALTIVEC_QUAD && !seln_flags.altivec_quad) ||
(family == PPC_MISC && !seln_flags.misc))
continue;
@@ -1853,6 +2609,10 @@
group_function = &testfunction_vector_extend_sign;
break;
+ case PPC_THREE_ARGS:
+ group_function = &testfunction_vector_three_special;
+ break;
+
case PPC_FOUR_ARGS:
group_function = &testfunction_vector_logical_four;
break;
@@ -1860,7 +2620,7 @@
default:
printf("ERROR: PPC_ALTIVEC, PPC_LOGICAL, unhandled number of arguments. 0x%08x\n", nb_args);
continue;
- } /* switch(PPC_LOGICAL, nb_args) */
+ } /* switch(PPC_INSERTEXTRACT, nb_args) */
break;
case PPC_INSERTEXTRACT:
@@ -1876,7 +2636,7 @@
default:
printf("ERROR: PPC_ALTIVEC, PPC_INSERTEXTRACT, unhandled number of arguments. 0x%08x\n", nb_args);
continue;
- } /* switch(PPC_ALTIVEC, nb_args) */
+ } /* switch(PPC_INSERTEXTRACT, nb_args) */
break;
case PPC_PERMUTE:
@@ -1926,6 +2686,53 @@
break;
+ case PPC_ALTIVEC_QUAD:
+ switch(type) {
+ case PPC_LOGICAL:
+ switch(nb_args) {
+ case PPC_TWO_ARGS:
+ group_function = &testfunction_vector_scalar_two_quad;
+ break;
+
+ default:
+ printf("ERROR: PPC_ALTIVEC_QUAD, PPC_LOGICAL, unhandled number of arguments. 0x%08x\n", nb_args);
+ continue;
+ } /* switch(PPC_LOGICAL, nb_args) */
+ break;
+
+ case PPC_COMPARE:
+ group_function = &testfunction_vector_scalar_compare_quads;
+ break;
+
+ default:
+ printf("ERROR: PPC_ALTIVEC_QUAD, unhandled type. %d\n", type);
+ continue;
+ } /* switch(type) */
+ break;
+
+ case PPC_ALTIVEC_DOUBLE:
+ switch(type) {
+ case PPC_COMPARE:
+ switch(nb_args) {
+ case PPC_ONE_ARG:
+ group_function = &testfunction_vector_scalar_data_class;
+ break;
+
+ case PPC_TWO_ARGS:
+ group_function = &testfunction_vector_scalar_two_double;
+ break;
+
+ case PPC_COMPARE_ARGS:
+ group_function = &testfunction_vector_scalar_compare_exp_double;
+ break;
+
+ default:
+ printf("ERROR: PPC_ALTIVEC_DOUBLE, PPC_COMPARE, unhandled number of arguments. 0x%08x\n", nb_args);
+ continue;
+ } /* switch(PPC_COMPARE, nb_args) */
+ } /* switch(type) */
+ break;
+
default:
printf("ERROR: unknown instruction family %08x\n", family);
continue;
@@ -1957,6 +2764,8 @@
"Usage: test_isa_3_0 [OPTIONS]\n"
"\t-i: test integer instructions (default)\n"
"\t-a: test altivec instructions\n"
+ "\t-d: test altivec double instructions\n"
+ "\t-q: test altivec quad instructions\n"
"\t-m: test miscellaneous instructions\n"
"\t-v: be verbose\n"
"\t-h: display this help and exit\n"
@@ -1995,6 +2804,8 @@
flags.integer = 0;
flags.misc = 0;
flags.altivec = 0;
+ flags.altivec_double = 0;
+ flags.altivec_quad = 0;
// Flags
flags.cr = 2;
@@ -2009,6 +2820,14 @@
flags.altivec = 1;
break;
+ case 'd':
+ flags.altivec_double = 1;
+ break;
+
+ case 'q':
+ flags.altivec_quad = 1;
+ break;
+
case 'm':
flags.misc = 1;
break;
@@ -2068,6 +2887,8 @@
printf(" family: \n");
printf(" integer = %d\n", flags.integer);
printf(" altivec = %d\n", flags.altivec);
+ printf(" altivec double = %d\n", flags.altivec_double);
+ printf(" altivec quad = %d\n", flags.altivec_quad);
printf(" misc = %d\n", flags.misc);
printf(" cr update: \n");
printf(" cr = %d\n", flags.cr);
Modified: trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp
==============================================================================
--- trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp (original)
+++ trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp Wed Jun 1 19:13:19 2016
@@ -740,7 +740,81 @@
vbpermd xa:00001f0800001f10 00001f0000001f02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:0000000000000000 0000000000000000 (00000000)
vbpermd xa:00001f0800001f10 00001f0000001f02 xb:5555555555555555 5555555555555555 => xt:0000000000000000 0000000000000000 (00000000)
-All done. Tested 20 different instructions
+xviexpdp xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+xviexpdp xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:7080000000000000 7080000000000000 (00000000)
+xviexpdp xa:0000000000000000 0000000000000000 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:2aa0000000000000 2aa0000000000000 (00000000)
+xviexpdp xa:0000000000000000 0000000000000000 xb:5555555555555555 5555555555555555 => xt:5550000000000000 5550000000000000 (00000000)
+xviexpdp xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0000000000000000 0000000000000000 => xt:800aaaaaaaaaaaaa 800aaaaaaaaaaaaa (00000000)
+xviexpdp xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0102030405060708 0102030405060708 => xt:f08aaaaaaaaaaaaa f08aaaaaaaaaaaaa (00000000)
+xviexpdp xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa (00000000)
+xviexpdp xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:5555555555555555 5555555555555555 => xt:d55aaaaaaaaaaaaa d55aaaaaaaaaaaaa (00000000)
+xviexpdp xa:0102010201020102 08090a0b0c0d0e0f xb:0000000000000000 0000000000000000 => xt:00090a0b0c0d0e0f 0002010201020102 (00000000)
+xviexpdp xa:0102010201020102 08090a0b0c0d0e0f xb:0102030405060708 0102030405060708 => xt:70890a0b0c0d0e0f 7082010201020102 (00000000)
+xviexpdp xa:0102010201020102 08090a0b0c0d0e0f xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:2aa90a0b0c0d0e0f 2aa2010201020102 (00000000)
+xviexpdp xa:0102010201020102 08090a0b0c0d0e0f xb:5555555555555555 5555555555555555 => xt:55590a0b0c0d0e0f 5552010201020102 (00000000)
+xviexpdp xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0000000000000000 0000000000000000 => xt:0001a5a7abadb0ba 000d111d1e555e70 (00000000)
+xviexpdp xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0102030405060708 0102030405060708 => xt:7081a5a7abadb0ba 708d111d1e555e70 (00000000)
+xviexpdp xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:2aa1a5a7abadb0ba 2aad111d1e555e70 (00000000)
+xviexpdp xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:5555555555555555 5555555555555555 => xt:5551a5a7abadb0ba 555d111d1e555e70 (00000000)
+xviexpdp xa:ced0deede5ecef00 00115e7eadbabec0 xb:0000000000000000 0000000000000000 => xt:00015e7eadbabec0 8000deede5ecef00 (00000000)
+xviexpdp xa:ced0deede5ecef00 00115e7eadbabec0 xb:0102030405060708 0102030405060708 => xt:70815e7eadbabec0 f080deede5ecef00 (00000000)
+xviexpdp xa:ced0deede5ecef00 00115e7eadbabec0 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:2aa15e7eadbabec0 aaa0deede5ecef00 (00000000)
+xviexpdp xa:ced0deede5ecef00 00115e7eadbabec0 xb:5555555555555555 5555555555555555 => xt:55515e7eadbabec0 d550deede5ecef00 (00000000)
+xviexpdp xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0001223344556677 8009aabbccddeeff (00000000)
+xviexpdp xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:7081223344556677 f089aabbccddeeff (00000000)
+xviexpdp xa:8899aabbccddeeff 0011223344556677 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:2aa1223344556677 aaa9aabbccddeeff (00000000)
+xviexpdp xa:8899aabbccddeeff 0011223344556677 xb:5555555555555555 5555555555555555 => xt:5551223344556677 d559aabbccddeeff (00000000)
+xviexpdp xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010 (00000000)
+xviexpdp xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:7080100000001002 7080100800001010 (00000000)
+xviexpdp xa:0000100800001010 0000100000001002 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:2aa0100000001002 2aa0100800001010 (00000000)
+xviexpdp xa:0000100800001010 0000100000001002 xb:5555555555555555 5555555555555555 => xt:5550100000001002 5550100800001010 (00000000)
+xviexpdp xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10 (00000000)
+xviexpdp xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:70801c0000001c02 70801c0800001c10 (00000000)
+xviexpdp xa:00001c0800001c10 00001c0000001c02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:2aa01c0000001c02 2aa01c0800001c10 (00000000)
+xviexpdp xa:00001c0800001c10 00001c0000001c02 xb:5555555555555555 5555555555555555 => xt:55501c0000001c02 55501c0800001c10 (00000000)
+xviexpdp xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10 (00000000)
+xviexpdp xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:70801f0000001f02 70801f0800001f10 (00000000)
+xviexpdp xa:00001f0800001f10 00001f0000001f02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:2aa01f0000001f02 2aa01f0800001f10 (00000000)
+xviexpdp xa:00001f0800001f10 00001f0000001f02 xb:5555555555555555 5555555555555555 => xt:55501f0000001f02 55501f0800001f10 (00000000)
+
+xviexpsp xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+xviexpsp xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:0200000004000000 0200000004000000 (00000000)
+xviexpsp xa:0000000000000000 0000000000000000 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:5500000055000000 5500000055000000 (00000000)
+xviexpsp xa:0000000000000000 0000000000000000 xb:5555555555555555 5555555555555555 => xt:2a8000002a800000 2a8000002a800000 (00000000)
+xviexpsp xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0000000000000000 0000000000000000 => xt:802aaaaa802aaaaa 802aaaaa802aaaaa (00000000)
+xviexpsp xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0102030405060708 0102030405060708 => xt:822aaaaa842aaaaa 822aaaaa842aaaaa (00000000)
+xviexpsp xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:d52aaaaad52aaaaa d52aaaaad52aaaaa (00000000)
+xviexpsp xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:5555555555555555 5555555555555555 => xt:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa (00000000)
+xviexpsp xa:0102010201020102 08090a0b0c0d0e0f xb:0000000000000000 0000000000000000 => xt:00090a0b000d0e0f 0002010200020102 (00000000)
+xviexpsp xa:0102010201020102 08090a0b0c0d0e0f xb:0102030405060708 0102030405060708 => xt:02090a0b040d0e0f 0202010204020102 (00000000)
+xviexpsp xa:0102010201020102 08090a0b0c0d0e0f xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:55090a0b550d0e0f 5502010255020102 (00000000)
+xviexpsp xa:0102010201020102 08090a0b0c0d0e0f xb:5555555555555555 5555555555555555 => xt:2a890a0b2a8d0e0f 2a8201022a820102 (00000000)
+xviexpsp xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0000000000000000 0000000000000000 => xt:0021a5a7802db0ba 000d111d00555e70 (00000000)
+xviexpsp xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0102030405060708 0102030405060708 => xt:0221a5a7842db0ba 020d111d04555e70 (00000000)
+xviexpsp xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:5521a5a7d52db0ba 550d111d55555e70 (00000000)
+xviexpsp xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:5555555555555555 5555555555555555 => xt:2aa1a5a7aaadb0ba 2a8d111d2ad55e70 (00000000)
+xviexpsp xa:ced0deede5ecef00 00115e7eadbabec0 xb:0000000000000000 0000000000000000 => xt:00115e7e803abec0 8050deed806cef00 (00000000)
+xviexpsp xa:ced0deede5ecef00 00115e7eadbabec0 xb:0102030405060708 0102030405060708 => xt:02115e7e843abec0 8250deed846cef00 (00000000)
+xviexpsp xa:ced0deede5ecef00 00115e7eadbabec0 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:55115e7ed53abec0 d550deedd56cef00 (00000000)
+xviexpsp xa:ced0deede5ecef00 00115e7eadbabec0 xb:5555555555555555 5555555555555555 => xt:2a915e7eaababec0 aad0deedaaecef00 (00000000)
+xviexpsp xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:0011223300556677 8019aabb805deeff (00000000)
+xviexpsp xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:0211223304556677 8219aabb845deeff (00000000)
+xviexpsp xa:8899aabbccddeeff 0011223344556677 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:5511223355556677 d519aabbd55deeff (00000000)
+xviexpsp xa:8899aabbccddeeff 0011223344556677 xb:5555555555555555 5555555555555555 => xt:2a9122332ad56677 aa99aabbaaddeeff (00000000)
+xviexpsp xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000100000001002 0000100800001010 (00000000)
+xviexpsp xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:0200100004001002 0200100804001010 (00000000)
+xviexpsp xa:0000100800001010 0000100000001002 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:5500100055001002 5500100855001010 (00000000)
+xviexpsp xa:0000100800001010 0000100000001002 xb:5555555555555555 5555555555555555 => xt:2a8010002a801002 2a8010082a801010 (00000000)
+xviexpsp xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:00001c0000001c02 00001c0800001c10 (00000000)
+xviexpsp xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:02001c0004001c02 02001c0804001c10 (00000000)
+xviexpsp xa:00001c0800001c10 00001c0000001c02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:55001c0055001c02 55001c0855001c10 (00000000)
+xviexpsp xa:00001c0800001c10 00001c0000001c02 xb:5555555555555555 5555555555555555 => xt:2a801c002a801c02 2a801c082a801c10 (00000000)
+xviexpsp xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:00001f0000001f02 00001f0800001f10 (00000000)
+xviexpsp xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:02001f0004001f02 02001f0804001f10 (00000000)
+xviexpsp xa:00001f0800001f10 00001f0000001f02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:55001f0055001f02 55001f0855001f10 (00000000)
+xviexpsp xa:00001f0800001f10 00001f0000001f02 xb:5555555555555555 5555555555555555 => xt:2a801f002a801f02 2a801f082a801f10 (00000000)
+
+All done. Tested 22 different instructions
ppc vector logical immediate:
Test instruction group [ppc vector logical immediate]
xxspltib 0000000000000000 0000000000000000 [ 0] => 0000000000000000 0000000000000000
@@ -754,7 +828,7 @@
xxspltib 0000000000000000 0000000000000000 [ff] => ffffffffffffffff ffffffffffffffff
xxspltib ffffffffffffffff ffffffffffffffff [ff] => ffffffffffffffff ffffffffffffffff
-All done. Tested 21 different instructions
+All done. Tested 23 different instructions
ppc vector logical one:
Test instruction group [ppc vector logical one]
xxbrh xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
@@ -905,7 +979,229 @@
xxbrq xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:101f1000081f1000 021f1000001f1000
xxbrq xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:101f1000081f1000 021f1000001f1000
-All done. Tested 25 different instructions
+xvxexpdp xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpdp xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpdp xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0000000000000010 0000000000000010
+xvxexpdp xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000010 0000000000000010
+xvxexpdp xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xt:0000000000000000 0000000000000000 => xt:00000000000002aa 00000000000002aa
+xvxexpdp xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xt:ffffffffffffffff ffffffffffffffff => xt:00000000000002aa 00000000000002aa
+xvxexpdp xa:5555555555555555 5555555555555555 xt:0000000000000000 0000000000000000 => xt:0000000000000555 0000000000000555
+xvxexpdp xa:5555555555555555 5555555555555555 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000555 0000000000000555
+xvxexpdp xa:08090a0b0c0d0e0f 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0000000000000080 0000000000000010
+xvxexpdp xa:08090a0b0c0d0e0f 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000080 0000000000000010
+xvxexpdp xa:f0f1f2f3f4f5f6f7 f8f9fafbfcfdfeff xt:0000000000000000 0000000000000000 => xt:000000000000070f 000000000000078f
+xvxexpdp xa:f0f1f2f3f4f5f6f7 f8f9fafbfcfdfeff xt:ffffffffffffffff ffffffffffffffff => xt:000000000000070f 000000000000078f
+xvxexpdp xa:7ea1a5a7abadb0ba 070d111d1e555e70 xt:0000000000000000 0000000000000000 => xt:00000000000007ea 0000000000000070
+xvxexpdp xa:7ea1a5a7abadb0ba 070d111d1e555e70 xt:ffffffffffffffff ffffffffffffffff => xt:00000000000007ea 0000000000000070
+xvxexpdp xa:e5e7ecedeff0f1fa beb1c0caced0dbde xt:0000000000000000 0000000000000000 => xt:000000000000065e 00000000000003eb
+xvxexpdp xa:e5e7ecedeff0f1fa beb1c0caced0dbde xt:ffffffffffffffff ffffffffffffffff => xt:000000000000065e 00000000000003eb
+xvxexpdp xa:00115e7eadbabec0 ced0deede5ecef00 xt:0000000000000000 0000000000000000 => xt:0000000000000001 00000000000004ed
+xvxexpdp xa:00115e7eadbabec0 ced0deede5ecef00 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000001 00000000000004ed
+xvxexpdp xa:00111e7ea5abadb1 becad0deedeffe00 xt:0000000000000000 0000000000000000 => xt:0000000000000001 00000000000003ec
+xvxexpdp xa:00111e7ea5abadb1 becad0deedeffe00 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000001 00000000000003ec
+xvxexpdp xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:0000000000000001 0000000000000089
+xvxexpdp xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000001 0000000000000089
+xvxexpdp xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:000000000000070e 0000000000000706
+xvxexpdp xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:000000000000070e 0000000000000706
+xvxexpdp xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpdp xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpdp xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0000000000000001 0000000000000001
+xvxexpdp xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000001 0000000000000001
+xvxexpdp xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpdp xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpdp xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:0000000000000001 0000000000000001
+xvxexpdp xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000001 0000000000000001
+xvxexpdp xa:00001f0000001f02 00001f0800001f10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpdp xa:00001f0000001f02 00001f0800001f10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpdp xa:00101f0000101f02 00101f0800101f10 xt:0000000000000000 0000000000000000 => xt:0000000000000001 0000000000000001
+xvxexpdp xa:00101f0000101f02 00101f0800101f10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000001 0000000000000001
+
+xvxexpsp xa:0000000000000000 0000000000000000 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0000000000000000 0000000000000000 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0102030405060708 0102010201020102 xt:0000000000000000 0000000000000000 => xt:000000020000000a 0000000200000002
+xvxexpsp xa:0102030405060708 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:000000020000000a 0000000200000002
+xvxexpsp xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xt:0000000000000000 0000000000000000 => xt:0000005500000055 0000005500000055
+xvxexpsp xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xt:ffffffffffffffff ffffffffffffffff => xt:0000005500000055 0000005500000055
+xvxexpsp xa:5555555555555555 5555555555555555 xt:0000000000000000 0000000000000000 => xt:000000aa000000aa 000000aa000000aa
+xvxexpsp xa:5555555555555555 5555555555555555 xt:ffffffffffffffff ffffffffffffffff => xt:000000aa000000aa 000000aa000000aa
+xvxexpsp xa:08090a0b0c0d0e0f 0102010201020102 xt:0000000000000000 0000000000000000 => xt:0000001000000018 0000000200000002
+xvxexpsp xa:08090a0b0c0d0e0f 0102010201020102 xt:ffffffffffffffff ffffffffffffffff => xt:0000001000000018 0000000200000002
+xvxexpsp xa:f0f1f2f3f4f5f6f7 f8f9fafbfcfdfeff xt:0000000000000000 0000000000000000 => xt:000000e1000000e9 000000f1000000f9
+xvxexpsp xa:f0f1f2f3f4f5f6f7 f8f9fafbfcfdfeff xt:ffffffffffffffff ffffffffffffffff => xt:000000e1000000e9 000000f1000000f9
+xvxexpsp xa:7ea1a5a7abadb0ba 070d111d1e555e70 xt:0000000000000000 0000000000000000 => xt:000000fd00000057 0000000e0000003c
+xvxexpsp xa:7ea1a5a7abadb0ba 070d111d1e555e70 xt:ffffffffffffffff ffffffffffffffff => xt:000000fd00000057 0000000e0000003c
+xvxexpsp xa:e5e7ecedeff0f1fa beb1c0caced0dbde xt:0000000000000000 0000000000000000 => xt:000000cb000000df 0000007d0000009d
+xvxexpsp xa:e5e7ecedeff0f1fa beb1c0caced0dbde xt:ffffffffffffffff ffffffffffffffff => xt:000000cb000000df 0000007d0000009d
+xvxexpsp xa:00115e7eadbabec0 ced0deede5ecef00 xt:0000000000000000 0000000000000000 => xt:000000000000005b 0000009d000000cb
+xvxexpsp xa:00115e7eadbabec0 ced0deede5ecef00 xt:ffffffffffffffff ffffffffffffffff => xt:000000000000005b 0000009d000000cb
+xvxexpsp xa:00111e7ea5abadb1 becad0deedeffe00 xt:0000000000000000 0000000000000000 => xt:000000000000004b 0000007d000000db
+xvxexpsp xa:00111e7ea5abadb1 becad0deedeffe00 xt:ffffffffffffffff ffffffffffffffff => xt:000000000000004b 0000007d000000db
+xvxexpsp xa:0011223344556677 8899aabbccddeeff xt:0000000000000000 0000000000000000 => xt:0000000000000088 0000001100000099
+xvxexpsp xa:0011223344556677 8899aabbccddeeff xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000088 0000001100000099
+xvxexpsp xa:f0e0d0c0b0a09080 7060504030201000 xt:0000000000000000 0000000000000000 => xt:000000e100000061 000000e000000060
+xvxexpsp xa:f0e0d0c0b0a09080 7060504030201000 xt:ffffffffffffffff ffffffffffffffff => xt:000000e100000061 000000e000000060
+xvxexpsp xa:0000100000001002 0000100800001010 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0000100000001002 0000100800001010 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0010100000101002 0010100800101010 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:0010100000101002 0010100800101010 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00001c0000001c02 00001c0800001c10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00001c0000001c02 00001c0800001c10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00101c0000101c02 00101c0800101c10 xt:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00101c0000101c02 00101c0800101c10 xt:ffffffffffffffff ffffffffffffffff => xt:0000000000000000 0000000000000000
+xvxexpsp xa:00001f0000001f02 0000...
[truncated message content] |
|
From: <sv...@va...> - 2016-06-01 18:12:42
|
Author: carll
Date: Wed Jun 1 19:12:31 2016
New Revision: 3220
Log:
Power PC Add support for ISA 3.0, part 3
Added support to emulate lxsd, lxssp, lxv, stxsd, stxssp, and stxv
xscpsgnqp, xscmpoqp, xscmpuqp, xscmpexpqp, xststdcqp, xsabsqp,
xsxexpqp, xsnabsqp, xsnegqp, xsxsigqp, xsiexpqp, xsxexpdp, xsxsigdp,
xscmpexpdp, xststdcdp, xsiexpdp, xsxtdcsp, xvxexpdp, xvxexpsp,
xvxsigdp, xvxsigsp, xviexpsp, xviexpdp, xvtstdcsp, xvtstdcdp
instructions.
valgrind bugzilla 362329
Modified:
trunk/priv/guest_ppc_toIR.c
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Wed Jun 1 19:12:31 2016
@@ -325,6 +325,11 @@
return IFIELD( instr, 1, 5 );
}
+/* Extract 2-bit secondary opcode, instr[1:0] */
+static UInt ifieldOPC0o2 ( UInt instr) {
+ return IFIELD( instr, 0, 2 );
+}
+
/* Extract RD (destination register) field, instr[25:21] */
static UChar ifieldRegDS( UInt instr ) {
return toUChar( IFIELD( instr, 21, 5 ) );
@@ -721,6 +726,12 @@
binop( Iop_OrV128, ( t2 ), ( t3 ) ) );
}
+static IRExpr* mkNOT1 ( IRExpr* arg1 )
+{
+ vassert(typeOfIRExpr(irsb->tyenv, arg1) == Ity_I1);
+ return unop(Iop_32to1, unop(Iop_Not32, unop(Iop_1Uto32, arg1) ) );
+}
+
/* expand V128_8Ux16 to 2x V128_16Ux8's */
static void expand8Ux16( IRExpr* vIn,
/*OUTs*/ IRTemp* vEvn, IRTemp* vOdd )
@@ -2059,6 +2070,73 @@
}
+static IRExpr * create_DCM ( IRType size, IRTemp NaN, IRTemp inf, IRTemp zero,
+ IRTemp dnorm, IRTemp pos)
+{
+ /* This is a general function for creating the DCM for a 32-bit or
+ 64-bit expression based on the passes size.
+ */
+ IRTemp neg;
+ IROp opAND, opOR, opSHL, opXto1, op1UtoX;
+
+ vassert( ( size == Ity_I32 ) || ( size == Ity_I64 ) );
+
+ if ( size == Ity_I32 ) {
+ opSHL = Iop_Shl32;
+ opAND = Iop_And32;
+ opOR = Iop_Or32;
+ opXto1 = Iop_32to1;
+ op1UtoX = Iop_1Uto32;
+ neg = newTemp( Ity_I32 );
+
+ } else {
+ opSHL = Iop_Shl64;
+ opAND = Iop_And64;
+ opOR = Iop_Or64;
+ opXto1 = Iop_64to1;
+ op1UtoX = Iop_1Uto64;
+ neg = newTemp( Ity_I64 );
+ }
+
+ assign( neg, unop( op1UtoX, mkNOT1( unop( opXto1,
+ mkexpr ( pos ) ) ) ) );
+
+ return binop( opOR,
+ binop( opSHL, mkexpr( NaN ), mkU8( 6 ) ),
+ binop( opOR,
+ binop( opOR,
+ binop( opOR,
+ binop( opSHL,
+ binop( opAND,
+ mkexpr( pos ),
+ mkexpr( inf ) ),
+ mkU8( 5 ) ),
+ binop( opSHL,
+ binop( opAND,
+ mkexpr( neg ),
+ mkexpr( inf ) ),
+ mkU8( 4 ) ) ),
+ binop( opOR,
+ binop( opSHL,
+ binop( opAND,
+ mkexpr( pos ),
+ mkexpr( zero ) ),
+ mkU8( 3 ) ),
+ binop( opSHL,
+ binop( opAND,
+ mkexpr( neg ),
+ mkexpr( zero ) ),
+ mkU8( 2 ) ) ) ),
+ binop( opOR,
+ binop( opSHL,
+ binop( opAND,
+ mkexpr( pos ),
+ mkexpr( dnorm ) ),
+ mkU8( 1 ) ),
+ binop( opAND,
+ mkexpr( neg ),
+ mkexpr( dnorm ) ) ) ) );
+}
/*------------------------------------------------------------*/
/*--- Helpers for XER flags. ---*/
@@ -3319,6 +3397,32 @@
mkU32( 0 ) ) );
}
+/* Quad precision floating point number is infinit:
+ * exp is 32767 and fraction is zero; sign = 0/1
+ */
+static IRExpr * is_Inf_V128 ( IRTemp src )
+{
+ IRExpr * frac_part_hi, * frac_part_low, *Inf_exp;
+
+ Inf_exp = binop( Iop_CmpEQ64,
+ binop( Iop_And64,
+ binop( Iop_Shr64,
+ unop( Iop_V128HIto64,
+ mkexpr( src ) ),
+ mkU8( 48 ) ),
+ mkU64( 0x7FFF ) ),
+ mkU64( 0x7FFF ) );
+
+ frac_part_hi = binop( Iop_And64,
+ unop( Iop_V128HIto64, mkexpr( src ) ),
+ mkU64( 0x0000FFFFFFFFFFFF ) );
+ frac_part_low = unop( Iop_V128to64, mkexpr( src ) );
+
+ return mkAND1( Inf_exp,
+ mkAND1( binop( Iop_CmpEQ64, frac_part_hi, mkU64( 0 ) ),
+ binop( Iop_CmpEQ64, frac_part_low, mkU64( 0 ) ) ) );
+}
+
static IRExpr * is_Zero_sp(IRTemp src)
{
IRTemp sign_less_part = newTemp(Ity_I32);
@@ -3343,6 +3447,21 @@
mkU32( 0 ) );
}
+/* Quad precision floating point number is Zero:
+ exp is zero and fraction is zero; sign = 0/1 */
+static IRExpr * is_Zero_V128 ( IRTemp src )
+{
+ IRExpr * hi64, * low64;
+
+ hi64 = binop( Iop_And64,
+ unop( Iop_V128HIto64, mkexpr( src ) ),
+ mkU64( 0x7FFFFFFFFFFFFFFF ) );
+ low64 = unop( Iop_V128to64, mkexpr( src ) );
+ return binop( Iop_CmpEQ64,
+ binop( Iop_Or64, hi64, low64 ),
+ mkU64( 0 ) );
+}
+
/* SNAN: s = 1/0; exp = 0x7ff; fraction is nonzero, with highest bit '1'
* QNAN: s = 1/0; exp = 0x7ff; fraction is nonzero, with highest bit '0'
* This function returns an IRExpr value of '1' for any type of NaN.
@@ -3363,8 +3482,7 @@
}
/* This function returns an IRExpr value of '1' for any type of NaN.
- * The passed 'src' argument is assumed to be Ity_I32.
- */
+ The passed 'src' argument is assumed to be Ity_I32. */
static IRExpr * is_NaN_32(IRTemp src)
{
#define NONZERO_FRAC_MASK32 0x007fffffULL
@@ -3381,11 +3499,113 @@
return mkAND1( NaN_exp, binop( Iop_CmpNE32, frac_part, mkU32( 0 ) ) );
}
-/* This function takes an Ity_I32 input argument interpreted
- * as a single-precision floating point value. If src is a
- * SNaN, it is changed to a QNaN and returned; otherwise,
- * the original value is returned.
+/* This function returns an IRExpr value of '1' for any type of NaN.
+ * The passed 'src' argument is assumed to be a quad precisiion
+ * floating point number stored in an Ity_V128.
*/
+static IRExpr * is_NaN_V128 ( IRTemp src )
+{
+
+ /* ignore top fractional bit */
+#define NONZERO_FRAC_MASK64Hi 0x0000ffffffffffffULL
+#define EXP_MASK 0x7fff
+
+ IRExpr * frac_part_hi = binop( Iop_And64,
+ unop( Iop_V128HIto64,
+ mkexpr ( src ) ),
+ mkU64( NONZERO_FRAC_MASK64Hi ) );
+
+ IRExpr * frac_part_lo = unop( Iop_V128to64, mkexpr ( src ) );
+
+ IRExpr * exp_part = binop( Iop_And64,
+ binop( Iop_Shr64,
+ unop( Iop_V128HIto64,
+ mkexpr( src ) ),
+ mkU8( 48 ) ),
+ mkU64( EXP_MASK ) );
+ IRExpr * NaN_exp = binop( Iop_CmpEQ64, exp_part, mkU64( EXP_MASK ) );
+
+ return mkAND1( NaN_exp,
+ mkOR1( binop( Iop_CmpNE64, frac_part_hi, mkU64( 0 ) ),
+ binop( Iop_CmpNE64, frac_part_lo, mkU64( 0 ) ) ) );
+}
+
+static IRExpr * is_Denorm ( IRType size, IRTemp src )
+{
+ /* Denormalized number has a zero exponent and non zero fraction.
+ Takes a 32bit or 64-bit floating point number and returns 1-bit result.
+ */
+ IROp opAND, opSHR, opCmpEQ, opCmpNE;
+ IRExpr *shift_by, *mask1, *mask2;
+ IRTemp zero = newTemp( size );
+
+ vassert( ( size == Ity_I32 ) || ( size == Ity_I64 ) );
+
+ if( size == Ity_I32 ) {
+ opAND = Iop_And32;
+ opSHR = Iop_Shr32;
+ opCmpEQ = Iop_CmpEQ32;
+ opCmpNE = Iop_CmpNE32;
+ shift_by = mkU8( 23 );
+ mask1 = mkU32( 0xFF );
+ mask2 = mkU32( 0x007fffff );
+ assign( zero , mkU32( 0 ) );
+
+ } else {
+ opAND = Iop_And64;
+ opSHR = Iop_Shr64;
+ opCmpEQ = Iop_CmpEQ64;
+ opCmpNE = Iop_CmpNE64;
+ shift_by = mkU8( 52 );
+ mask1 = mkU64( 0x7FF );
+ mask2 = mkU64( 0x000fffffffffffffULL );
+ assign( zero, mkU64( 0 ) );
+ }
+
+ IRExpr * exp_part = binop( opAND,
+ binop( opSHR,
+ mkexpr( src ),
+ shift_by ),
+ mask1 );
+ IRExpr * frac = binop( opAND,
+ mkexpr( src ),
+ mask2 );
+
+ return mkAND1( binop( opCmpEQ, exp_part, mkexpr( zero ) ),
+ binop( opCmpNE,
+ frac,
+ mkexpr( zero ) ) );
+}
+
+static IRExpr * is_Denorm_V128 ( IRTemp src )
+{
+ /* Denormalized number has a zero exponent and non zero fraction.
+ * Takes a 128-bit floating point number and returns 1-bit result.
+ */
+ IRExpr * exp_part = binop( Iop_And64,
+ binop( Iop_Shr64,
+ unop( Iop_V128HIto64,
+ mkexpr( src ) ),
+ mkU8( 48 ) ),
+ mkU64( 0x7FFF ) );
+ IRExpr * frac_hi = binop( Iop_And64,
+ unop( Iop_V128HIto64, mkexpr( src ) ),
+ mkU64( 0x0000ffffffffffffULL ) );
+ IRExpr * frac_lo = unop( Iop_V128to64, mkexpr( src ) );
+ return mkAND1( binop( Iop_CmpEQ64, exp_part, mkU64( 0 ) ),
+ mkOR1( binop( Iop_CmpNE64,
+ frac_hi,
+ mkU64( 0 ) ),
+ binop( Iop_CmpNE64,
+ frac_lo,
+ mkU64( 0 ) ) ) );
+}
+
+
+/* This function takes an Ity_I32 input argument interpreted
+ as a single-precision floating point value. If src is a
+ SNaN, it is changed to a QNaN and returned; otherwise,
+ the original value is returned. */
static IRExpr * handle_SNaN_to_QNaN_32(IRExpr * src)
{
#define SNAN_MASK32 0x00400000
@@ -3496,6 +3716,124 @@
return negatedResult;
}
+/* This function takes two quad_precision floating point numbers of type
+ V128 and return 1 if src_A > src_B, 0 otherwise. */
+static IRExpr * Quad_precision_gt ( IRTemp src_A, IRTemp src_B )
+{
+#define FRAC_MASK64Hi 0x0000ffffffffffffULL
+#define MASK 0x7FFFFFFFFFFFFFFFULL /* exclude sign bit in upper 64 bits */
+#define EXP_MASK 0x7fff
+
+ IRType ty = Ity_I64;
+ IRTemp sign_A = newTemp( ty );
+ IRTemp sign_B = newTemp( ty );
+ IRTemp exp_A = newTemp( ty );
+ IRTemp exp_B = newTemp( ty );
+ IRTemp frac_A_hi = newTemp( ty );
+ IRTemp frac_B_hi = newTemp( ty );
+ IRTemp frac_A_lo = newTemp( ty );
+ IRTemp frac_B_lo = newTemp( ty );
+
+
+ /* extract exponents, and fractional parts so they can be compared */
+ assign( sign_A, binop( Iop_Shr64,
+ unop( Iop_V128HIto64, mkexpr( src_A ) ),
+ mkU8( 63 ) ) );
+ assign( sign_B, binop( Iop_Shr64,
+ unop( Iop_V128HIto64, mkexpr( src_B ) ),
+ mkU8( 63 ) ) );
+ assign( exp_A, binop( Iop_And64,
+ binop( Iop_Shr64,
+ unop( Iop_V128HIto64, mkexpr( src_A ) ),
+ mkU8( 48 ) ),
+ mkU64( EXP_MASK ) ) );
+ assign( exp_B, binop( Iop_And64,
+ binop( Iop_Shr64,
+ unop( Iop_V128HIto64, mkexpr( src_B ) ),
+ mkU8( 48 ) ),
+ mkU64( EXP_MASK ) ) );
+ assign( frac_A_hi, binop( Iop_And64,
+ unop( Iop_V128HIto64, mkexpr( src_A ) ),
+ mkU64( FRAC_MASK64Hi ) ) );
+ assign( frac_B_hi, binop( Iop_And64,
+ unop( Iop_V128HIto64, mkexpr( src_B ) ),
+ mkU64( FRAC_MASK64Hi ) ) );
+ assign( frac_A_lo, unop( Iop_V128to64, mkexpr( src_A ) ) );
+ assign( frac_B_lo, unop( Iop_V128to64, mkexpr( src_B ) ) );
+
+ IRExpr * A_zero = mkAND1( binop( Iop_CmpEQ64,
+ binop( Iop_And64,
+ unop( Iop_V128HIto64,
+ mkexpr( src_A ) ),
+ mkU64( MASK ) ),
+ mkU64( 0 ) ),
+ binop( Iop_CmpEQ64,
+ unop( Iop_V128to64, mkexpr( src_A ) ),
+ mkU64( 0 ) ) );
+ IRExpr * B_zero = mkAND1( binop( Iop_CmpEQ64,
+ binop( Iop_And64,
+ unop( Iop_V128HIto64,
+ mkexpr( src_B ) ),
+ mkU64( MASK ) ),
+ mkU64( 0 ) ),
+ binop( Iop_CmpEQ64,
+ unop( Iop_V128to64, mkexpr( src_B ) ),
+ mkU64( 0 ) ) );
+ IRExpr * A_B_zero = mkAND1( A_zero, B_zero );
+
+ /* Compare numbers */
+ IRExpr * both_pos = mkAND1( binop( Iop_CmpEQ64, mkexpr( sign_A ),
+ mkU64( 0 ) ),
+ binop( Iop_CmpEQ64, mkexpr( sign_B ),
+ mkU64( 0 ) ) );
+ IRExpr * both_neg = mkAND1( binop( Iop_CmpEQ64, mkexpr( sign_A ),
+ mkU64( 1 ) ),
+ binop( Iop_CmpEQ64, mkexpr( sign_B ),
+ mkU64( 1 ) ) );
+ IRExpr * sign_eq = binop( Iop_CmpEQ64, mkexpr( sign_A ), mkexpr( sign_B ) );
+ IRExpr * sign_gt = binop( Iop_CmpLT64U, mkexpr( sign_A ),
+ mkexpr( sign_B ) ); /* A pos, B neg */
+
+ IRExpr * exp_eq = binop( Iop_CmpEQ64, mkexpr( exp_A ), mkexpr( exp_B ) );
+ IRExpr * exp_gt = binop( Iop_CmpLT64U, mkexpr( exp_B ), mkexpr( exp_A ) );
+ IRExpr * exp_lt = binop( Iop_CmpLT64U, mkexpr( exp_A ), mkexpr( exp_B ) );
+
+ IRExpr * frac_hi_eq = binop( Iop_CmpEQ64, mkexpr( frac_A_hi),
+ mkexpr( frac_B_hi ) );
+ IRExpr * frac_hi_gt = binop( Iop_CmpLT64U, mkexpr( frac_B_hi ),
+ mkexpr( frac_A_hi ) );
+ IRExpr * frac_hi_lt = binop( Iop_CmpLT64U, mkexpr( frac_A_hi ),
+ mkexpr( frac_B_hi ) );
+
+ IRExpr * frac_lo_gt = binop( Iop_CmpLT64U, mkexpr( frac_B_lo ),
+ mkexpr( frac_A_lo ) );
+ IRExpr * frac_lo_lt = binop( Iop_CmpLT64U, mkexpr( frac_A_lo ),
+ mkexpr( frac_B_lo ) );
+
+ /* src_A and src_B both positive */
+ IRExpr *pos_cmp = mkOR1( exp_gt,
+ mkAND1( exp_eq,
+ mkOR1( frac_hi_gt,
+ mkAND1( frac_hi_eq, frac_lo_gt ) )
+ ) );
+
+ /* src_A and src_B both negative */
+ IRExpr *neg_cmp = mkOR1( exp_lt,
+ mkAND1( exp_eq,
+ mkOR1( frac_hi_lt,
+ mkAND1( frac_hi_eq, frac_lo_lt ) )
+ ) );
+
+ /* Need to check the case where one value is a positive
+ * zero and the other value is a negative zero
+ */
+ return mkAND1( mkNOT1( A_B_zero ),
+ mkOR1( sign_gt,
+ mkAND1( sign_eq,
+ mkOR1( mkAND1( both_pos, pos_cmp ),
+ mkAND1( both_neg, neg_cmp ) ) ) ) );
+}
+
/*------------------------------------------------------------*/
/* Transactional memory helpers
*
@@ -9796,15 +10134,152 @@
}
assign( EA_hi, ea_rAor0_idxd( rA_addr, rB_addr ) );
break;
- case 0x39: // lfdp (FP Load Double Pair DS-form, ISA 2.05 p125)
- DIP("lfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr);
- assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
- is_load = 1;
- break;
- case 0x3d: // stfdp (FP Store Double Pair DS-form, ISA 2.05 p125)
- DIP("stfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr);
- assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
+ case 0x39:
+ {
+ UInt DS = IFIELD( theInstr, 2, 14);
+ UChar vRT = ifieldRegDS(theInstr);
+ IRTemp EA = newTemp( ty );
+
+ opc2 = ifieldOPC0o2(theInstr);
+
+ switch(opc2) {
+ case 0x0: // lfdp (FP Load Double Pair DS-form, ISA 2.05 p125)
+ DIP("lfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr);
+ assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
+ is_load = 1;
+ break;
+
+ case 0x2: // lxsd (Load VSX Scalar Doubleword)
+ DIP("lxsd v%u,%d(r%u)\n", vRT, DS, rA_addr);
+
+ assign( EA, ea_rAor0_simm( rA_addr, DS<<2 ) );
+
+ putVSReg( vRT+32, binop( Iop_64HLtoV128,
+ load( Ity_I64, mkexpr( EA ) ),
+ mkU64( 0 ) ) );
+ return True;
+
+ case 0x3: // lxssp (Load VSX Scalar Single)
+ DIP("lxssp v%u,%d(r%u)\n", vRT, DS, rA_addr);
+
+ assign( EA, ea_rAor0_simm( rA_addr, DS<<2 ) );
+
+ putVSReg( vRT+32, binop( Iop_64HLtoV128,
+ binop( Iop_32HLto64,
+ load( Ity_I32, mkexpr( EA ) ),
+ mkU32( 0 ) ),
+ mkU64( 0 ) ) );
+ return True;
+
+ default:
+ vex_printf("dis_fp_pair(ppc) : DS-form wrong opc2\n");
+ return False;
+ }
break;
+ }
+ case 0x3d:
+ {
+ UInt DS = IFIELD( theInstr, 2, 14);
+ UChar vRS = ifieldRegDS(theInstr);
+ IRTemp EA = newTemp( ty );
+
+ opc2 = ifieldOPC0o2(theInstr);
+
+ switch(opc2) {
+ case 0x0:
+ // stfdp (FP Store Double Pair DS-form, ISA 2.05 p125)
+ DIP("stfdp fr%u,%d(r%u)\n", frT_hi_addr, simm16, rA_addr);
+ assign( EA_hi, ea_rAor0_simm( rA_addr, simm16 ) );
+ break;
+
+ case 0x1:
+ {
+ UInt ea_off = 8;
+ IRTemp word[2];
+ IRExpr* irx_addr;
+ UInt T = IFIELD( theInstr, 21, 5); // T or S depending on inst
+ UInt TX = IFIELD( theInstr, 3, 1); // TX or SX field
+
+ word[0] = newTemp(Ity_I64);
+ word[1] = newTemp(Ity_I64);
+ DS = IFIELD( theInstr, 4, 11); // DQ in the instruction definition
+ assign( EA, ea_rAor0_simm( rA_addr, DS<<4 ) );
+
+ if ( IFIELD( theInstr, 0, 3) == 1) {
+ // lxv (Load VSX Vector)
+ DIP("lxv v%u,%d(r%u)\n", vRS, DS, rA_addr);
+
+ assign( word[0], load( Ity_I64, mkexpr( EA ) ) );
+
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ assign( word[1], load( Ity_I64, irx_addr ) );
+
+ if (host_endness == VexEndnessBE)
+ putVSReg( TX*32+T, binop( Iop_64HLtoV128,
+ mkexpr( word[0] ),
+ mkexpr( word[1] ) ) );
+ else
+ putVSReg( TX*32+T, binop( Iop_64HLtoV128,
+ mkexpr( word[1] ),
+ mkexpr( word[0] ) ) );
+ return True;
+
+ } else if ( IFIELD( theInstr, 0, 3) == 5) {
+ // stxv (Store VSX Vector)
+ DIP("stxv v%u,%d(r%u)\n", vRS, DS, rA_addr);
+
+ if (host_endness == VexEndnessBE) {
+ store( mkexpr(EA), unop( Iop_V128HIto64,
+ getVSReg( TX*32+T ) ) );
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ store( irx_addr, unop( Iop_V128to64,
+ getVSReg( TX*32+T ) ) );
+ } else {
+ store( mkexpr(EA), unop( Iop_V128to64,
+ getVSReg( TX*32+T ) ) );
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ store( irx_addr, unop( Iop_V128HIto64,
+ getVSReg( TX*32+T ) ) );
+ }
+ return True;
+
+ } else {
+ vex_printf("dis_fp_pair vector load/store (ppc) : DS-form wrong opc2\n");
+ return False;
+ }
+ break;
+ }
+ case 0x2:
+ // stxsd (Store VSX Scalar Doubleword)
+ DIP("stxsd v%u,%d(r%u)\n", vRS, DS, rA_addr);
+
+ assign( EA, ea_rAor0_simm( rA_addr, DS<<2 ) );
+
+ store( mkexpr(EA), unop( Iop_V128HIto64,
+ getVSReg( vRS+32 ) ) );
+ return True;
+
+ case 0x3:
+ // stxssp (Store VSX Scalar Single)
+ DIP("stxssp v%u,%d(r%u)\n", vRS, DS, rA_addr);
+
+ assign( EA, ea_rAor0_simm( rA_addr, DS<<2 ) );
+
+ store( mkexpr(EA), unop( Iop_64HIto32,
+ unop( Iop_V128HIto64,
+ getVSReg( vRS+32 ) ) ) );
+ return True;
+
+ default:
+ vex_printf("dis_fp_pair(ppc) : DS-form wrong opc2\n");
+ return False;
+ }
+ break;
+ }
default: // immediate offset
vex_printf("dis_fp_pair(ppc)(instr)\n");
return False;
@@ -13501,7 +13976,7 @@
UInt i;
UInt num_words;
UInt word_size;
- unsigned long word_mask;
+ unsigned long long word_mask;
if ( opc1 != 0x4 ) {
vex_printf("dis_av_rotate(ppc)(instr)\n");
@@ -13529,7 +14004,7 @@
assign( field_mask, binop( Iop_64HLtoV128,
mkU64( 0 ),
mkU64( 0x3F ) ) );
- word_mask = 0xFFFFFFFF;
+ word_mask = 0xFFFFFFFFFFFFFFFFULL;
break;
default:
vex_printf("dis_av_rotate(ppc)(opc2)\n");
@@ -16480,6 +16955,72 @@
}
switch ( opc2 ) {
+ case 0x0ec: // xscmpexpdp (VSX Scalar Compare Exponents Double-Precision)
+ {
+ IRExpr *bit4, *bit5, *bit6, *bit7;
+ UInt BF = IFIELD( theInstr, 23, 3 );
+ IRTemp eq_lt_gt = newTemp( Ity_I32 );
+ IRTemp CC = newTemp( Ity_I32 );
+ IRTemp vA_hi = newTemp( Ity_I64 );
+ IRTemp vB_hi = newTemp( Ity_I64 );
+ UChar rA_addr = ifieldRegA(theInstr);
+ UChar rB_addr = ifieldRegB(theInstr);
+
+ DIP("xscmpexpdp %d,v%d,v%d\n", BF, rA_addr, rB_addr);
+
+ assign( vA_hi, unop( Iop_V128HIto64, mkexpr( vA ) ) );
+ assign( vB_hi, unop( Iop_V128HIto64, mkexpr( vB ) ) );
+
+ /* A exp < B exp */
+ bit4 = binop( Iop_CmpLT64U,
+ binop( Iop_And64,
+ mkexpr( vA_hi ),
+ mkU64( 0x7FFF0000000000 ) ),
+ binop( Iop_And64,
+ mkexpr( vB_hi ),
+ mkU64( 0x7FFF0000000000 ) ) );
+ /* A exp > B exp */
+ bit5 = binop( Iop_CmpLT64U,
+ binop( Iop_And64,
+ mkexpr( vB_hi ),
+ mkU64( 0x7FFF00000000000 ) ),
+ binop( Iop_And64,
+ mkexpr( vA_hi ),
+ mkU64( 0x7FFF00000000000 ) ) );
+ /* test equal */
+ bit6 = binop( Iop_CmpEQ64,
+ binop( Iop_And64,
+ mkexpr( vA_hi ),
+ mkU64( 0x7FFF00000000000 ) ),
+ binop( Iop_And64,
+ mkexpr( vB_hi ),
+ mkU64( 0x7FFF00000000000 ) ) );
+
+ /* exp A or exp B is NaN */
+ bit7 = mkOR1( is_NaN_V128( vA ),
+ is_NaN_V128( vB ) );
+
+ assign( eq_lt_gt, binop( Iop_Or32,
+ binop( Iop_Shl32,
+ unop( Iop_1Uto32, bit4 ),
+ mkU8( 3) ),
+ binop( Iop_Or32,
+ binop( Iop_Shl32,
+ unop( Iop_1Uto32, bit5 ),
+ mkU8( 2) ),
+ binop( Iop_Shl32,
+ unop( Iop_1Uto32, bit6 ),
+ mkU8( 1 ) ) ) ) );
+ assign(CC, binop( Iop_Or32,
+ mkexpr( eq_lt_gt ) ,
+ unop( Iop_1Uto32, bit7 ) ) );
+
+ putGST_field( PPC_GST_CR, mkexpr( CC ), BF );
+ putFPCC( mkexpr( CC ) );
+ return True;
+ }
+ break;
+
case 0x14A: // xxextractuw (VSX Vector Extract Unsigned Word)
{
UInt uim = IFIELD( theInstr, 16, 4 );
@@ -16530,6 +17071,7 @@
mkexpr( tmp ) ) );
break;
}
+
case 0x2B2: // xsabsdp (VSX scalar absolute value double-precision
{
/* Move abs val of dw 0 of VSX[XB] to dw 0 of VSX[XT]. */
@@ -16552,6 +17094,146 @@
putVSReg(XT, mkexpr(absVal));
break;
}
+
+ case 0x2b6: // xsxexpdp (VSX Scalar Extract Exponent Double-Precision)
+ // xsxsigdp (VSX Scalar Extract Significand Doulbe-Precision)
+ {
+ IRTemp rT = newTemp( Ity_I64 );
+ UInt inst_select = IFIELD( theInstr, 16, 5);
+
+ if (inst_select == 0) {
+ DIP("xsxexpd %d,v%d\n", (UInt)XT, (UInt)XB);
+
+ assign( rT, binop( Iop_Shr64,
+ binop( Iop_And64,
+ unop( Iop_V128HIto64, mkexpr( vB ) ),
+ mkU64( 0x7FF0000000000000 ) ),
+ mkU8 ( 52 ) ) );
+ } else if (inst_select == 1) {
+ IRExpr *normal;
+ IRTemp tmp = newTemp(Ity_I64);
+
+ DIP("xsxsigdp v%d,v%d\n", (UInt)XT, (UInt)XB);
+
+ assign( tmp, unop( Iop_V128HIto64, mkexpr( vB ) ) );
+
+ /* Value is normal if it isn't infinite, zero or denormalized */
+ normal = mkNOT1( mkOR1(
+ mkOR1( is_NaN( tmp ), is_Inf( tmp, False ) ),
+ mkOR1( is_Zero( tmp, False ),
+ is_Denorm( Ity_I64, tmp ) ) ) );
+
+ assign( rT, binop( Iop_Or64,
+ binop( Iop_And64,
+ mkexpr( tmp ),
+ mkU64( 0xFFFFFFFFFFFFF ) ),
+ binop( Iop_Shl64,
+ unop( Iop_1Uto64, normal),
+ mkU8( 52 ) ) ) );
+ } else {
+ vex_printf( "dis_vxv_scalar_extract_exp_sig invalid inst_select (ppc)(opc2)\n" );
+ return False;
+ }
+ putIReg( XT, mkexpr(rT));
+ }
+ break;
+
+ case 0x254: // xststdcsp (VSX Scalar Test Data Class Single-Precision)
+ case 0x2D4: // xststdcdp (VSX Scalar Test Data Class Double-Precision)
+ {
+ /* These instructions only differ in that the single precision
+ instruction, xststdcsp, has the additional constraint on the
+ denormal test that the exponent be greater then zero and
+ less then 0x381. */
+ IRTemp vB_hi = newTemp( Ity_I64 );
+ UInt BF = IFIELD( theInstr, 23, 3 );
+ UInt DCMX_mask = IFIELD( theInstr, 16, 7 );
+ IRTemp NaN = newTemp( Ity_I64 );
+ IRTemp inf = newTemp( Ity_I64 );
+ IRTemp zero = newTemp( Ity_I64 );
+ IRTemp dnorm = newTemp( Ity_I64 );
+ IRTemp pos = newTemp( Ity_I64 );
+ IRTemp not_sp = newTemp( Ity_I64 );
+ IRTemp DCM = newTemp( Ity_I64 );
+ IRTemp CC = newTemp( Ity_I64 );
+ IRTemp exponent = newTemp( Ity_I64 );
+ IRTemp tmp = newTemp( Ity_I64 );
+
+ assign( vB_hi, unop( Iop_V128HIto64, mkexpr( vB ) ) );
+
+ assign( pos, unop( Iop_1Uto64,
+ binop( Iop_CmpEQ64,
+ binop( Iop_Shr64,
+ mkexpr( vB_hi ),
+ mkU8( 63 ) ),
+ mkU64( 0 ) ) ) );
+
+ assign( NaN, unop( Iop_1Uto64, is_NaN( vB_hi ) ) );
+ assign( inf, unop( Iop_1Uto64, is_Inf( vB_hi, False ) ) );
+ assign( zero, unop( Iop_1Uto64, is_Zero( vB_hi, False ) ) );
+
+ if (opc2 == 0x254) {
+ DIP("xststdcsp %d,v%d,%d\n", BF, (UInt)XB, DCMX_mask);
+
+ /* The least significant bit of the CC is set to 1 if the double
+ precision value is not representable as a single precision
+ value. The spec says the bit is set if:
+ src != convert_SPtoDP(convert_DPtoSP(src))
+ */
+ assign( tmp,
+ unop( Iop_ReinterpF64asI64,
+ unop( Iop_F32toF64,
+ unop( Iop_TruncF64asF32,
+ unop( Iop_ReinterpI64asF64,
+ mkexpr( vB_hi ) ) ) ) ) );
+ assign( not_sp, unop( Iop_1Uto64,
+ mkNOT1( binop( Iop_CmpEQ64,
+ mkexpr( vB_hi ),
+ mkexpr( tmp ) ) ) ) );
+ assign( exponent,
+ binop( Iop_Shr64,
+ binop( Iop_And64,
+ mkexpr( vB_hi ),
+ mkU64( 0x7ff0000000000000 ) ),
+ mkU8( 52 ) ) );
+ assign( dnorm, unop( Iop_1Uto64,
+ mkOR1( is_Denorm( Ity_I64, vB_hi ),
+ mkAND1( binop( Iop_CmpLT64U,
+ mkexpr( exponent ),
+ mkU64( 0x381 ) ),
+ binop( Iop_CmpNE64,
+ mkexpr( exponent ),
+ mkU64( 0x0 ) ) ) ) ) );
+
+ } else {
+ DIP("xststdcdp %d,v%d,%d\n", BF, (UInt)XB, DCMX_mask);
+ assign( not_sp, mkU64( 0 ) );
+ assign( dnorm, unop( Iop_1Uto64, is_Denorm( Ity_I64, vB_hi ) ) );
+ }
+
+ assign( DCM, create_DCM( Ity_I64, NaN, inf, zero, dnorm, pos ) );
+ assign( CC,
+ binop( Iop_Or64,
+ binop( Iop_And64, /* vB sign bit */
+ binop( Iop_Shr64,
+ mkexpr( vB_hi ),
+ mkU8( 60 ) ),
+ mkU64( 0x8 ) ),
+ binop( Iop_Or64,
+ binop( Iop_Shl64,
+ unop( Iop_1Uto64,
+ binop( Iop_CmpNE64,
+ binop( Iop_And64,
+ mkexpr( DCM ),
+ mkU64( DCMX_mask ) ),
+ mkU64( 0 ) ) ),
+ mkU8( 1 ) ),
+ mkexpr( not_sp ) ) ) );
+ putGST_field( PPC_GST_CR, unop( Iop_64to32, mkexpr( CC ) ), BF );
+ putFPCC( unop( Iop_64to32, mkexpr( CC ) ) );
+ }
+ return True;
+
case 0x2C0: // xscpsgndp
{
/* Scalar copy sign double-precision */
@@ -16739,9 +17421,252 @@
mkU64( 0 ) ) );
break;
}
- case 0x3B6: // xxbrh, xxbrw, xxbrd, xxbrq
+
+ case 0x354: // xvtstdcsp (VSX Test Data Class Single-Precision)
+ {
+ UInt DX_mask = IFIELD( theInstr, 16, 5 );
+ UInt DC_mask = IFIELD( theInstr, 6, 1 );
+ UInt DM_mask = IFIELD( theInstr, 2, 1 );
+ UInt DCMX_mask = (DC_mask << 6) | (DM_mask << 5) | DX_mask;
+
+ IRTemp match_value[4];
+ IRTemp value[4];
+ IRTemp NaN[4];
+ IRTemp inf[4];
+ IRTemp pos[4];
+ IRTemp DCM[4];
+ IRTemp zero[4];
+ IRTemp dnorm[4];
+ Int i;
+
+ DIP("xvtstdcsp v%d,v%d,%d\n", (UInt)XT, (UInt)XB, DCMX_mask);
+
+ for (i = 0; i < 4; i++) {
+ NaN[i] = newTemp(Ity_I32);
+ inf[i] = newTemp(Ity_I32);
+ pos[i] = newTemp(Ity_I32);
+ DCM[i] = newTemp(Ity_I32);
+ zero[i] = newTemp(Ity_I32);
+ dnorm[i] = newTemp(Ity_I32);
+
+ value[i] = newTemp(Ity_I32);
+ match_value[i] = newTemp(Ity_I32);
+
+ assign( value[i],
+ unop( Iop_64to32,
+ unop( Iop_V128to64,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ mkexpr( vB ),
+ mkU8( (3-i)*32 ) ),
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( 0xFFFFFFFF ) ) ) ) ) );
+
+ assign( pos[i], unop( Iop_1Uto32,
+ binop( Iop_CmpEQ32,
+ binop( Iop_Shr32,
+ mkexpr( value[i] ),
+ mkU8( 31 ) ),
+ mkU32( 0 ) ) ) );
+
+ assign( NaN[i], unop( Iop_1Uto32, is_NaN_32( value[i] ) ));
+ assign( inf[i], unop( Iop_1Uto32, is_Inf( value[i], True ) ) );
+ assign( zero[i], unop( Iop_1Uto32, is_Zero( value[i], True ) ) );
+
+ assign( dnorm[i], unop( Iop_1Uto32, is_Denorm( Ity_I32,
+ value[i] ) ) );
+ assign( DCM[i], create_DCM( Ity_I32, NaN[i], inf[i], zero[i],
+ dnorm[i], pos[i] ) );
+
+ assign( match_value[i],
+ unop( Iop_1Sto32,
+ binop( Iop_CmpNE32,
+ binop( Iop_And32,
+ mkU32( DCMX_mask ),
+ mkexpr( DCM[i] ) ),
+ mkU32( 0 ) ) ) );
+ }
+
+ putVSReg( XT, binop( Iop_64HLtoV128,
+ binop( Iop_32HLto64,
+ mkexpr( match_value[0] ),
+ mkexpr( match_value[1] ) ),
+ binop( Iop_32HLto64,
+ mkexpr( match_value[2] ),
+ mkexpr( match_value[3] ) ) ) );
+ }
+ break;
+
+ case 0x360: // xviexpsp (VSX Vector Insert Exponent Single-Precision)
+ {
+ Int i;
+ IRTemp new_XT[5];
+ IRTemp A_value[4];
+ IRTemp B_value[4];
+ IRExpr *sign[4], *expr[4], *fract[4];
+
+ DIP("xviexpsp v%d,v%d\n", XT, XB);
+ new_XT[0] = newTemp(Ity_V128);
+ assign( new_XT[0], binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( 0x0 ) ) );
+
+ for (i = 0; i < 4; i++) {
+ A_value[i] = newTemp(Ity_I32);
+ B_value[i] = newTemp(Ity_I32);
+
+ assign( A_value[i],
+ unop( Iop_64to32,
+ unop( Iop_V128to64,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ mkexpr( vA ),
+ mkU8( (3-i)*32 ) ),
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( 0xFFFFFFFF ) ) ) ) ) );
+ assign( B_value[i],
+ unop( Iop_64to32,
+ unop( Iop_V128to64,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ mkexpr( vB ),
+ mkU8( (3-i)*32 ) ),
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( 0xFFFFFFFF ) ) ) ) ) );
+
+ sign[i] = binop( Iop_And32, mkexpr( A_value[i] ),
+ mkU32( 0x80000000 ) );
+ expr[i] = binop( Iop_Shl32,
+ binop( Iop_And32, mkexpr( B_value[i] ),
+ mkU32( 0xFF ) ),
+ mkU8( 23 ) );
+ fract[i] = binop( Iop_And32, mkexpr( A_value[i] ),
+ mkU32( 0x007FFFFF ) );
+
+ new_XT[i+1] = newTemp(Ity_V128);
+ assign( new_XT[i+1],
+ binop( Iop_OrV128,
+ binop( Iop_ShlV128,
+ binop( Iop_64HLtoV128,
+ mkU64( 0 ),
+ binop( Iop_32HLto64,
+ mkU32( 0 ),
+ binop( Iop_Or32,
+ binop( Iop_Or32,
+ sign[i],
+ expr[i] ),
+ fract[i] ) ) ),
+ mkU8( (3-i)*32 ) ),
+ mkexpr( new_XT[i] ) ) );
+ }
+ putVSReg( XT, mkexpr( new_XT[4] ) );
+ }
+ break;
+
+ case 0x396: // xsiexpdp (VSX Scalar Insert Exponent Double-Precision)
+ {
+ IRExpr *sign, *expr, *fract;
+ UChar rA_addr = ifieldRegA(theInstr);
+ UChar rB_addr = ifieldRegB(theInstr);
+ IRTemp rA = newTemp( Ity_I64 );
+ IRTemp rB = newTemp( Ity_I64 );
+
+ DIP("xsiexpdp v%d,%d,%d\n", (UInt)XT, (UInt)rA_addr, (UInt)rB_addr);
+ assign( rA, getIReg(rA_addr));
+ assign( rB, getIReg(rB_addr));
+
+ sign = binop( Iop_And64, mkexpr( rA ), mkU64( 0x8000000000000000 ) );
+ expr = binop( Iop_Shl64,
+ binop( Iop_And64, mkexpr( rB ), mkU64( 0x7FF ) ),
+ mkU8( 52 ) );
+ fract = binop( Iop_And64, mkexpr( rA ), mkU64( 0x000FFFFFFFFFFFFF ) );
+
+ putVSReg( XT, binop( Iop_64HLtoV128,
+ binop( Iop_Or64,
+ binop( Iop_Or64, sign, expr ),
+ fract ),
+ mkU64( 0 ) ) );
+ }
+ break;
+
+ case 0x3B6: // xvxexpdp (VSX Vector Extract Exponent Double-Precision)
+ // xvxsigdp (VSX Vector Extract Significand Double-Precision)
+ // xxbrh
+ // xvxexpsp (VSX Vector Extract Exponent Single-Precision)
+ // xvxsigsp (VSX Vector Extract Significand Single-Precision)
+ // xxbrw
+ // xxbrd
+ // xxbrq
{
- if ( IFIELD( theInstr, 16, 5 ) == 7 ) {
+ UInt inst_select = IFIELD( theInstr, 16, 5);
+
+ if (inst_select == 0) {
+ DIP("xvxexpdp v%d,v%d\n", XT, XB);
+
+ putVSReg( XT, binop( Iop_ShrV128,
+ binop( Iop_AndV128,
+ mkexpr( vB ),
+ binop( Iop_64HLtoV128,
+ mkU64( 0x7FF0000000000000 ),
+ mkU64( 0x7FF0000000000000 ) ) ),
+ mkU8( 52 ) ) );
+
+ } else if (inst_select == 1) {
+ Int i;
+ IRExpr *normal[2];
+ IRTemp value[2];
+ IRTemp new_XT[3];
+
+ DIP("xvxsigdp v%d,v%d\n", XT, XB);
+ new_XT[0] = newTemp(Ity_V128);
+ assign( new_XT[0], binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( 0x0 ) ) );
+
+ for (i = 0; i < 2; i++) {
+ value[i] = newTemp(Ity_I64);
+ assign( value[i],
+ unop( Iop_V128to64,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ mkexpr( vB ),
+ mkU8( (1-i)*64 ) ),
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( 0xFFFFFFFFFFFFFFFF ) ) ) ) );
+
+ new_XT[i+1] = newTemp(Ity_V128);
+
+ /* Value is normal if it isn't infinite, zero or denormalized */
+ normal[i] = mkNOT1( mkOR1(
+ mkOR1( is_NaN( value[i] ),
+ is_Inf( value[i], False ) ),
+ mkOR1( is_Zero( value[i], False ),
+ is_Denorm( Ity_I64,
+ value[i] ) ) ) );
+
+ assign( new_XT[i+1],
+ binop( Iop_OrV128,
+ binop( Iop_ShlV128,
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ binop( Iop_Or64,
+ binop( Iop_And64,
+ mkexpr( value[i] ),
+ mkU64( 0xFFFFFFFFFFFFF ) ),
+ binop( Iop_Shl64,
+ unop( Iop_1Uto64,
+ normal[i]),
+ mkU8( 52 ) ) ) ),
+ mkU8( (1-i)*64 ) ),
+ mkexpr( new_XT[i] ) ) );
+ }
+ putVSReg( XT, mkexpr( new_XT[2] ) );
+
+ } else if (inst_select == 7) {
IRTemp sub_element0 = newTemp( Ity_V128 );
IRTemp sub_element1 = newTemp( Ity_V128 );
@@ -16768,7 +17693,76 @@
mkexpr( sub_element1 ),
mkexpr( sub_element0 ) ) );
- } else if ( IFIELD( theInstr, 16, 5 ) == 15 ) {
+ } else if (inst_select == 8) {
+ DIP("xvxexpsp v%d,v%d\n", XT, XB);
+
+ putVSReg( XT, binop( Iop_ShrV128,
+ binop( Iop_AndV128,
+ mkexpr( vB ),
+ binop( Iop_64HLtoV128,
+ mkU64( 0x7F8000007F800000 ),
+ mkU64( 0x7F8000007F800000 ) ) ),
+ mkU8( 23 ) ) );
+ } else if (inst_select == 9) {
+ Int i;
+ IRExpr *normal[4];
+ IRTemp value[4];
+ IRTemp new_value[4];
+ IRTemp new_XT[5];
+
+ DIP("xvxsigsp v%d,v%d\n", XT, XB);
+ new_XT[0] = newTemp(Ity_V128);
+ assign( new_XT[0], binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( 0x0 ) ) );
+
+ for (i = 0; i < 4; i++) {
+ value[i] = newTemp(Ity_I32);
+ assign( value[i],
+ unop( Iop_64to32,
+ unop( Iop_V128to64,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ mkexpr( vB ),
+ mkU8( (3-i)*32 ) ),
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( 0xFFFFFFFF ) ) ) ) ) );
+
+ new_XT[i+1] = newTemp(Ity_V128);
+
+ /* Value is normal if it isn't infinite, zero or denormalized */
+ normal[i] = mkNOT1( mkOR1(
+ mkOR1( is_NaN_32( value[i] ),
+ is_Inf( value[i], True ) ),
+ mkOR1( is_Zero( value[i], True ),
+ is_Denorm( Ity_I32,
+ value[i] ) ) ) );
+ new_value[i] = newTemp(Ity_I32);
+ assign( new_value[i],
+ binop( Iop_Or32,
+ binop( Iop_And32,
+ mkexpr( value[i] ),
+ mkU32( 0x7FFFFF ) ),
+ binop( Iop_Shl32,
+ unop( Iop_1Uto32,
+ normal[i]),
+ mkU8( 23 ) ) ) );
+
+ assign( new_XT[i+1],
+ binop( Iop_OrV128,
+ binop( Iop_ShlV128,
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ binop( Iop_32HLto64,
+ mkU32( 0x0 ),
+ mkexpr( new_value[i] ) ) ),
+ mkU8( (3-i)*32 ) ),
+ mkexpr( new_XT[i] ) ) );
+ }
+ putVSReg( XT, mkexpr( new_XT[4] ) );
+
+ } else if (inst_select == 15) {
IRTemp sub_element0 = newTemp( Ity_V128 );
IRTemp sub_element1 = newTemp( Ity_V128 );
IRTemp sub_element2 = newTemp( Ity_V128 );
@@ -16818,7 +17812,7 @@
mkexpr( sub_element1 ),
mkexpr( sub_element0 ) ) ) );
- } else if (IFIELD( theInstr, 16, 5) == 23) {
+ } else if (inst_select == 23) {
DIP("xxbrd v%d, v%d\n", (UInt)XT, (UInt)XB);
int i;
@@ -16865,7 +17859,7 @@
putVSReg( XT, mkexpr( new_xT[4] ) );
- } else if ( IFIELD( theInstr, 16, 5 ) == 31 ) {
+ } else if ( inst_select == 31 ) {
int i;
int shift_left = 8;
int shift_right = 120;
@@ -16915,11 +17909,141 @@
putVSReg( XT, mkexpr( new_xT[8] ) );
} else {
- vex_printf("dis_vxs_misc(ppc) Invalid Byte-Reverse instruction\n");
+ vex_printf("dis_vxs_misc(ppc) Invalid instruction selection\n");
return False;
}
break;
}
+
+ case 0x3D4: // xvtstdcdp (VSX Test Data Class Double-Precision)
+ {
+ UInt DX_mask = IFIELD( theInstr, 16, 5 );
+ UInt DC_mask = IFIELD( theInstr, 6, 1 );
+ UInt DM_mask = IFIELD( theInstr, 2, 1 );
+ UInt DCMX_mask = (DC_mask << 6) | (DM_mask << 5) | DX_mask;
+
+ IRTemp NaN[2], inf[2], zero[2], dnorm[2], pos[2], DCM[2];
+ IRTemp match_value[2];
+ IRTemp value[2];
+ Int i;
+
+ DIP("xvtstdcdp v%d,v%d,%d\n", (UInt)XT, (UInt)XB, DCMX_mask);
+
+ for (i = 0; i < 2; i++) {
+ NaN[i] = newTemp(Ity_I64);
+ inf[i] = newTemp(Ity_I64);
+ pos[i] = newTemp(Ity_I64);
+ DCM[i] = newTemp(Ity_I64);
+ zero[i] = newTemp(Ity_I64);
+ dnorm[i] = newTemp(Ity_I64);
+
+ value[i] = newTemp(Ity_I64);
+ match_value[i] = newTemp(Ity_I64);
+
+ assign( value[i],
+ unop( Iop_V128to64,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ mkexpr( vB ),
+ mkU8( (1-i)*64 ) ),
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( 0xFFFFFFFFFFFFFFFF ) ) ) ) );
+
+ assign( pos[i], unop( Iop_1Uto64,
+ binop( Iop_CmpEQ64,
+ binop( Iop_Shr64,
+ mkexpr( value[i] ),
+ mkU8( 63 ) ),
+ mkU64( 0 ) ) ) );
+
+ assign( NaN[i], unop( Iop_1Uto64, is_NaN( value[i] ) ) );
+ assign( inf[i], unop( Iop_1Uto64, is_Inf( value[i], False ) ) );
+ assign( zero[i], unop( Iop_1Uto64, is_Zero( value[i], False ) ) );
+ assign( dnorm[i], unop( Iop_1Uto64, is_Denorm( Ity_I64,
+ value[i] ) ) );
+
+ assign( DCM[i], create_DCM( Ity_I64, NaN[i], inf[i], zero[i],
+ dnorm[i], pos[i] ) );
+
+ assign( match_value[i],
+ unop( Iop_1Sto64,
+ binop( Iop_CmpNE64,
+ binop( Iop_And64,
+ mkU64( DCMX_mask ),
+ mkexpr( DCM[i] ) ),
+ mkU64( 0 ) ) ) );
+ }
+ putVSReg( XT, binop( Iop_64HLtoV128,
+ mkexpr( match_value[0] ),
+ mkexpr( match_value[1] ) ) );
+ }
+ break;
+
+ case 0x3E0: // xviexpdp (VSX Vector Insert Exponent Double-Precision)
+ {
+ Int i;
+ IRTemp new_XT[3];
+ IRTemp A_value[2];
+ IRTemp B_value[2];
+ IRExpr *sign[2], *expr[2], *fract[2];
+
+ DIP("xviexpdp v%d,v%d\n", XT, XB);
+ new_XT[0] = newTemp(Ity_V128);
+ assign( new_XT[0], binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( 0x0 ) ) );
+
+ for (i = 0; i < 2; i++) {
+ A_value[i] = newTemp(Ity_I64);
+ B_value[i] = newTemp(Ity_I64);
+
+ assign( A_value[i],
+ unop( Iop_V128to64,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ mkexpr( vA ),
+ mkU8( (1-i)*64 ) ),
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( 0xFFFFFFFFFFFFFFFF ) ) ) ) );
+ assign( B_value[i],
+ unop( Iop_V128to64,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ mkexpr( vB ),
+ mkU8( (1-i)*64 ) ),
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( 0xFFFFFFFFFFFFFFFF ) ) ) ) );
+
+ sign[i] = binop( Iop_And64, mkexpr( A_value[i] ),
+ mkU64( 0x8000000000000000 ) );
+ expr[i] = binop( Iop_Shl64,
+ binop( Iop_And64, mkexpr( B_value[i] ),
+ mkU64( 0x7FF ) ),
+ mkU8( 52 ) );
+ fract[i] = binop( Iop_And64, mkexpr( A_value[i] ),
+ mkU64( 0x000FFFFFFFFFFFFF ) );
+
+ new_XT[i+1] = newTemp(Ity_V128);
+ assign( new_XT[i+1],
+ binop( Iop_OrV128,
+ binop( Iop_ShlV128,
+ binop( Iop_64HLtoV128,
+ mkU64( 0 ),
+ binop( Iop_Or64,
+ binop( Iop_Or64,
+ sign[i],
+ expr[i] ),
+ fract[i] ) ),
+ mkU8( (1-i)*64 ) ),
+ mkexpr( new_XT[i] ) ) );
+ }
+ putVSReg( XT, mkexpr( new_XT[2] ) );
+ }
+ break;
+
default:
vex_printf( "dis_vxs_misc(ppc)(opc2)\n" );
return False;
@@ -18120,6 +19244,408 @@
return True;
}
+/* VSX Scalar Quad-Precision instructions */
+static Bool
+dis_vx_scalar_quad_precision ( UInt theInstr )
+{
+ /* XX1-Form */
+ UChar opc1 = ifieldOPC( theInstr );
+ UInt opc2 = ifieldOPClo10( theInstr );
+ UChar vT_addr = ifieldRegDS( theInstr ) + 32;
+ UChar vA_addr = ifieldRegA( theInstr ) + 32;
+ UChar vB_addr = ifieldRegB( theInstr ) + 32;
+ IRTemp vA = newTemp( Ity_V128 );
+ IRTemp vB = newTemp( Ity_V128 );
+ IRTemp vT = newTemp( Ity_V128 );
+
+ assign( vB, getVSReg(vB_addr));
+
+ if (opc1 != 0x3F) {
+ vex_printf( "dis_vx_scalar_quad_precision(ppc)(instr)\n" );
+ return False;
+ }
+
+ switch (opc2) {
+
+ case 0x064: // xscpsgnqp (VSX Scalar Copy Sign Quad-Precision)
+ {
+ IRTemp sign_vA = newTemp( Ity_I64 );
+ IRTemp vB_hi = newTemp( Ity_I64 );
+
+ DIP("xscpsgnqp v%d,v%d,v%d\n", vT_addr, vA_addr, vB_addr);
+
+ assign( vA, getVSReg(vA_addr) );
+
+ assign( sign_vA, binop( Iop_And64,
+ unop( Iop_V128HIto64,
+ mkexpr( vA ) ),
+ mkU64( 0x8000000000000000ULL ) ) );
+ assign( vB_hi, binop( Iop_Or64,
+ binop( Iop_And64,
+ unop( Iop_V128HIto64,
+ mkexpr( vB ) ),
+ mkU64( 0x7FFFFFFFFFFFFFFFULL ) ),
+ mkexpr( sign_vA ) ) );
+ assign( vT, binop( Iop_64HLtoV128,
+ mkexpr( vB_hi ),
+ unop( Iop_V128to64, mkexpr( vB ) ) ) );
+ break;
+ }
+
+ case 0x084: // xscmpoqp (VSX Scalar Compare Ordered Quad-Precision)
+ case 0x284: // xscmpuqp (VSX Scalar Compare Unrdered Quad-Precision)
+ {
+ /* Note, only differece between xscmoqp and xscmpuqp is the
+ exception flag settings which are not supported anyway. */
+ IRExpr *bit4, *bit5, *bit6, *bit7;
+ IRExpr *bit_zero, *bit_inf, *same_sign;
+ UInt BF = IFIELD( theInstr, 23, 3 );
+
+ IRTemp eq_lt_gt = newTemp( Ity_I32 );
+ IRTemp CC = newTemp( Ity_I32 );
+
+ if (opc2 == 0x084) {
+ DIP("xscmpoqp %d,v%d,v%d\n", BF, vA_addr, vB_addr);
+ } else {
+ DIP("xscmpuqp %d,v%d,v%d\n", BF, vA_addr, vB_addr);
+ }
+
+ assign( vA, getVSReg(vA_addr));
+
+ /* A and B have the same sign */
+ same_sign = binop( Iop_CmpEQ64,
+ binop( Iop_Shr64,
+ unop( Iop_V128HIto64,
+ mkexpr( vA ) ),
+ mkU8( 63 ) ),
+ binop( Iop_Shr64,
+ unop( Iop_V128HIto64,
+ mkexpr( vB ) ),
+ mkU8( 63 ) ) );
+
+ /* A < B */
+ bit4 = Quad_precision_gt( vB, vA );
+
+ /* A > B */
+ bit5 = Quad_precision_gt( vA, vB );
+
+ /* A equal B */
+ bit6 = mkAND1( binop( Iop_CmpEQ64,
+ unop( Iop_V128HIto64,
+ mkexpr( vA ) ),
+ unop( Iop_V128HIto64,
+ mkexpr( vB ) ) ),
+ binop( Iop_CmpEQ64,
+ unop( Iop_V128to64,
+ mkexpr( vA ) ),
+ unop( Iop_V128to64,
+ mkexpr( vB ) ) ) );
+
+ /* test both zero don't care about sign */
+ bit_zero = mkAND1( is_Zero_V128( vA ), is_Zero_V128( vB ) );
+
+ /* test both infinit don't care about sign */
+ bit_inf = mkAND1(
+ mkAND1( is_Inf_V128( vA ), is_Inf_V128( vB ) ),
+ binop( Iop_CmpEQ64,
+ binop( Iop_And64,
+ unop( Iop_V128to64,
+ mkexpr( vA ) ),
+ mkU64( 0x80000000) ),
+ binop( Iop_And64,
+ unop( Iop_V128to64,
+ mkexpr( vB ) ),
+ mkU64( 0x80000000) ) ) );
+
+ /* exp A or exp B is NaN */
+ bit7 = mkOR1( is_NaN_V128( vA ),
+ is_NaN_V128( vB ) );
+
+ assign( eq_lt_gt, binop( Iop_Or32,
+ binop( Iop_Or32,
+ binop( Iop_Shl32,
+ unop( Iop_1Uto32, bit4 ),
+ ...
[truncated message content] |
|
From: Yasushi S. <ya...@at...> - 2016-06-01 11:25:42
|
Hi list,
On Fri, 29 Apr 2016 00:52:02 +0900,
svn...@pu... wrote:
>
> Author: sewardj
> Date: Thu Apr 28 16:52:01 2016
> New Revision: 15875
>
> Log:
> Un-break ppc32-linux following r15784. It appears that ppc32-ELF
> layout constraints are different from x86-ELF and so the assertion on
> the sizeof(TTEntryC) fails on ppc32-linux.
>
> Modified:
> trunk/coregrind/m_transtab.c
>
> Modified: trunk/coregrind/m_transtab.c
> ==============================================================================
> --- trunk/coregrind/m_transtab.c (original)
> +++ trunk/coregrind/m_transtab.c Thu Apr 28 16:52:01 2016
> @@ -2448,10 +2448,18 @@
> if (sizeof(HWord) == 8) {
> vg_assert(sizeof(TTEntryH) <= 32);
> vg_assert(sizeof(TTEntryC) <= 112);
> - } else if (sizeof(HWord) == 4) {
> + }
> + else if (sizeof(HWord) == 4) {
> vg_assert(sizeof(TTEntryH) <= 20);
> +# if defined(VGP_ppc32_linux)
> + /* ppc32-linux is weird. It thinks alignof(ULong) == 8 and so the
> + structure is larger than on other 32 bit targets. */
It's also 8 bytes on my armhf debian sid as I checked.
I noticed this when I built trunk r15889 on my 32 ARM board. When I
run, it failed with:
./vg-in-place true
==7907== Memcheck, a memory error detector
==7907== Copyright (C) 2002-2015, and GNU GPL'd, by Julian Seward et al.
==7907== Using Valgrind-3.12.0.SVN and LibVEX; rerun with -h for copyright info
==7907== Command: true
==7907==
valgrind: m_transtab.c:2462 (vgPlain_init_tt_tc): Assertion 'sizeof(TTEntryC) <= 88' failed.
Segmentation fault
Something like this, obviously, works for me. But, not sure what arch
is weird and what's not; given that ppc, misp, and arm seems to have
the same alignment.
Index: coregrind/m_transtab.c
===================================================================
--- coregrind/m_transtab.c (revision 15889)
+++ coregrind/m_transtab.c (working copy)
@@ -2451,7 +2451,7 @@
}
else if (sizeof(HWord) == 4) {
vg_assert(sizeof(TTEntryH) <= 20);
-# if defined(VGP_ppc32_linux) || defined(VGP_mips32_linux)
+# if defined(VGP_ppc32_linux) || defined(VGP_mips32_linux) || defined(VGP_arm_linux)
/* On PPC32 and MIPS32 platforms alignof(ULong) == 8, so the
structure is larger than on other 32 bit targets. */
vg_assert(sizeof(TTEntryC) <= 96);
--
yashi
|