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From: <sv...@va...> - 2016-04-26 20:05:20
|
Author: carll
Date: Tue Apr 26 21:05:13 2016
New Revision: 15872
Log:
Power PC Fix V bit error in 128-bit BCD add and subtract instructions
Update the NEWS file for this bug
VEX commit 3218
Valgrind commit 15871
Bugzilla 360035
Modified:
trunk/NEWS
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Tue Apr 26 21:05:13 2016
@@ -101,6 +101,7 @@
361226 s390x: risbgn (EC59) not implemented
361926 Unhandled Solaris syscall: sysfs(84)
362009 Valgrind dumps core on unimplemented functionality before threads are created
+360035 POWER PC instruction bcdadd and bcdsubtract generate result with non-zero shadow bits
n-i-bz Fix incorrect (or infinite loop) unwind on RHEL7 x86 and amd64
n-i-bz massif --pages-as-heap=yes does not report peak caused by mmap+munmap
|
|
From: <sv...@va...> - 2016-04-26 19:54:02
|
Author: carll
Date: Tue Apr 26 20:53:56 2016
New Revision: 15871
Log:
Power PC Fix V bit error in 128-bit BCD add and subtract instructions
The original code was using the bcdadd / bcdsub instruction on the operand
shadow bits to calculate the shadow bits for the result. This introduced
non-zero bits shadow bits in the result. The shadow bits for these
instructions should be set to all valid or all invalid. If one of the
argument shadow bits was one, then all of the shadow bits of the result should
be one. Otherwise the result shadow bits should be zero.
This patch fixes the above bug in memcheck/mc_translate.c
Fixing the above bug broke the v-bit test. The issue is the v-bit tester
assumes the shadow bits for the operands of a given Iop can be set to one
for testing purposes. The implementation of the bcdadd and bcdsub was passing
a constant value for the variable ps. The ps value is an argument to the
instruction that specifies how to set the sign code of the result. The
implementation of the instructions was changed to issue the instruction with
ps=0. Then the result of the instruction is updated in the VEX code if ps=1.
This changed also results in cleaning up the vbit test code.
This patch also fixes the issues with the v-bit test program.
Valgrind commit 3218
Bugzilla 360035
Modified:
trunk/memcheck/mc_translate.c
trunk/memcheck/tests/vbit-test/irops.c
trunk/memcheck/tests/vbit-test/main.c
trunk/memcheck/tests/vbit-test/ternary.c
Modified: trunk/memcheck/mc_translate.c
==============================================================================
--- trunk/memcheck/mc_translate.c (original)
+++ trunk/memcheck/mc_translate.c Tue Apr 26 20:53:56 2016
@@ -852,6 +852,17 @@
unop(Iop_CmpNEZ64, tmp4));
break;
}
+ case Ity_V128: {
+ /* Chop it in half, OR the halves together, and compare that
+ * with zero.
+ */
+ IRAtom* tmp2 = assignNew('V', mce, Ity_I64, unop(Iop_V128HIto64, vbits));
+ IRAtom* tmp3 = assignNew('V', mce, Ity_I64, unop(Iop_V128to64, vbits));
+ IRAtom* tmp4 = assignNew('V', mce, Ity_I64, binop(Iop_Or64, tmp2, tmp3));
+ tmp1 = assignNew('V', mce, Ity_I1,
+ unop(Iop_CmpNEZ64, tmp4));
+ break;
+ }
default:
ppIRType(src_ty);
VG_(tool_panic)("mkPCastTo(1)");
@@ -2888,11 +2899,6 @@
case Iop_SetElem32x2:
complainIfUndefined(mce, atom2, NULL);
return assignNew('V', mce, Ity_I64, triop(op, vatom1, atom2, vatom3));
- /* BCDIops */
- case Iop_BCDAdd:
- case Iop_BCDSub:
- complainIfUndefined(mce, atom3, NULL);
- return assignNew('V', mce, Ity_V128, triop(op, vatom1, vatom2, atom3));
/* Vector FP with rounding mode as the first arg */
case Iop_Add64Fx2:
@@ -3723,6 +3729,10 @@
complainIfUndefined(mce, atom2, NULL);
return assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2));
+ case Iop_BCDAdd:
+ case Iop_BCDSub:
+ return mkLazy2(mce, Ity_V128, vatom1, vatom2);
+
/* SHA Iops */
case Iop_SHA256:
case Iop_SHA512:
Modified: trunk/memcheck/tests/vbit-test/irops.c
==============================================================================
--- trunk/memcheck/tests/vbit-test/irops.c (original)
+++ trunk/memcheck/tests/vbit-test/irops.c Tue Apr 26 20:53:56 2016
@@ -1066,8 +1066,8 @@
{ DEFOP(Iop_Min32Fx8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Max64Fx4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Min64Fx4, UNDEF_UNKNOWN), },
- { DEFOP(Iop_BCDAdd, UNDEF_SOME), .ppc64 = 1, .ppc32 = 1 },
- { DEFOP(Iop_BCDSub, UNDEF_SOME), .ppc64 = 1, .ppc32 = 1 },
+ { DEFOP(Iop_BCDAdd, UNDEF_ALL), .ppc64 = 1, .ppc32 = 1 },
+ { DEFOP(Iop_BCDSub, UNDEF_ALL), .ppc64 = 1, .ppc32 = 1 },
{ DEFOP(Iop_PolynomialMulAdd8x16, UNDEF_ALL_8x16), .ppc64 = 1, .ppc32 = 1 },
{ DEFOP(Iop_PolynomialMulAdd16x8, UNDEF_ALL_16x8), .ppc64 = 1, .ppc32 = 1 },
{ DEFOP(Iop_PolynomialMulAdd32x4, UNDEF_ALL_32x4), .ppc64 = 1, .ppc32 = 1 },
Modified: trunk/memcheck/tests/vbit-test/main.c
==============================================================================
--- trunk/memcheck/tests/vbit-test/main.c (original)
+++ trunk/memcheck/tests/vbit-test/main.c Tue Apr 26 20:53:56 2016
@@ -119,18 +119,6 @@
tmp->immediate_index = 2;
tmp->immediate_type = Ity_I8;
}
-
- tmp = get_irop(Iop_BCDAdd);
- if (tmp) {
- tmp->immediate_index = 3;
- tmp->immediate_type = Ity_I8;
- }
-
- tmp = get_irop(Iop_BCDSub);
- if (tmp) {
- tmp->immediate_index = 3;
- tmp->immediate_type = Ity_I8;
- }
#endif
}
Modified: trunk/memcheck/tests/vbit-test/ternary.c
==============================================================================
--- trunk/memcheck/tests/vbit-test/ternary.c (original)
+++ trunk/memcheck/tests/vbit-test/ternary.c Tue Apr 26 20:53:56 2016
@@ -51,15 +51,6 @@
break;
case UNDEF_SOME:
- /* The result of the Iop_BCDAdd and the Iop_BCDSub has some result
- * vbits set. Not sure how the vbit propagation works on these Iops.
- * for now, just make sure there are some vbits set in the result.
- *
- * The Iop_BCDAdd and Iop_BCDSub iops have one immediate value in the
- * third operand.
- *
- * TODO, figure out details of vbit propagation for these Iops.
- */
expected_vbits.num_bits = result->vbits.num_bits;
if ((result->vbits.bits.u128[0] != 0) ||
|
|
From: <sv...@va...> - 2016-04-26 19:53:04
|
Author: carll
Date: Tue Apr 26 20:52:56 2016
New Revision: 3218
Log:
Power PC Fix V bit error in 128-bit BCD add and subtract instructions
The original code was using the bcdadd / bcdsub instruction on the operand
shadow bits to calculate the shadow bits for the result. This introduced
non-zero bits shadow bits in the result. The shadow bits for these
instructions should be set to all valid or all invalid. If one of the
argument shadow bits was one, then all of the shadow bits of the result should
be one. Otherwise the result shadow bits should be zero.
This patch fixes the above bug in memcheck/mc_translate.c
Fixing the above bug broke the v-bit test. The issue is the v-bit tester
assumes the shadow bits for the operands of a given Iop can be set to one
for testing purposes. The implementation of the bcdadd and bcdsub was passing
a constant value for the variable ps. The ps value is an argument to the
instruction that specifies how to set the sign code of the result. The
implementation of the instructions was changed to issue the instruction with
ps=0. Then the result of the instruction is updated in the VEX code if ps=1.
This changed also results in cleaning up the vbit test code.
This patch also fixes the issues with the v-bit test program.
Bugzilla 360035
Modified:
trunk/priv/guest_ppc_toIR.c
trunk/priv/host_ppc_defs.c
trunk/priv/host_ppc_defs.h
trunk/priv/host_ppc_isel.c
trunk/priv/ir_defs.c
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Tue Apr 26 20:52:56 2016
@@ -21297,6 +21297,43 @@
return True;
}
+static IRExpr * bcd_sign_code_adjust( UInt ps, IRExpr * tmp)
+{
+ /* The Iop_BCDAdd and Iop_BCDSub will result in the corresponding Power PC
+ * instruction being issued with ps = 0. If ps = 1, the sign code, which
+ * is in the least significant four bits of the result, needs to be updated
+ * per the ISA:
+ *
+ * If PS=0, the sign code of the result is set to 0b1100.
+ * If PS=1, the sign code of the result is set to 0b1111.
+ *
+ * Note, the ps value is NOT being passed down to the instruction issue
+ * because passing a constant via triop() breaks the vbit-test test. The
+ * vbit-tester assumes it can set non-zero shadow bits for the triop()
+ * arguments. Thus they have to be expressions not a constant.
+ */
+ IRTemp mask = newTemp(Ity_I64);
+ IRExpr *rtn;
+
+ if ( ps == 0 ) {
+ /* sign code is correct, just return it. */
+ rtn = tmp;
+
+ } else {
+ /* check if lower four bits are 0b1100, if so, change to 0b1111 */
+ assign( mask, unop( Iop_1Sto64,
+ binop( Iop_CmpEQ64, mkU64( 0xC ),
+ binop( Iop_And64, mkU64( 0xF ),
+ unop( Iop_V128to64, tmp ) ) ) ) );
+ rtn = binop( Iop_64HLtoV128,
+ unop( Iop_V128HIto64, tmp ),
+ binop( Iop_Or64,
+ binop( Iop_And64, mkU64( 0xF ), mkexpr( mask ) ),
+ unop( Iop_V128to64, tmp ) ) );
+ }
+
+ return rtn;
+}
/*
AltiVec BCD Arithmetic instructions.
@@ -21329,15 +21366,19 @@
switch (opc2) {
case 0x1: // bcdadd
DIP("bcdadd. v%d,v%d,v%d,%u\n", vRT_addr, vRA_addr, vRB_addr, ps);
- assign( dst, triop( Iop_BCDAdd, mkexpr( vA ),
- mkexpr( vB ), mkU8( ps ) ) );
+ assign( dst, bcd_sign_code_adjust( ps,
+ binop( Iop_BCDAdd,
+ mkexpr( vA ),
+ mkexpr( vB ) ) ) );
putVReg( vRT_addr, mkexpr(dst));
return True;
case 0x41: // bcdsub
DIP("bcdsub. v%d,v%d,v%d,%u\n", vRT_addr, vRA_addr, vRB_addr, ps);
- assign( dst, triop( Iop_BCDSub, mkexpr( vA ),
- mkexpr( vB ), mkU8( ps ) ) );
+ assign( dst, bcd_sign_code_adjust( ps,
+ binop( Iop_BCDSub,
+ mkexpr( vA ),
+ mkexpr( vB ) ) ) );
putVReg( vRT_addr, mkexpr(dst));
return True;
Modified: trunk/priv/host_ppc_defs.c
==============================================================================
--- trunk/priv/host_ppc_defs.c (original)
+++ trunk/priv/host_ppc_defs.c Tue Apr 26 20:52:56 2016
@@ -1415,15 +1415,14 @@
i->Pin.AvHashV128Binary.s_field = s_field;
return i;
}
-PPCInstr* PPCInstr_AvBCDV128Trinary ( PPCAvOp op, HReg dst,
- HReg src1, HReg src2, PPCRI* ps ) {
+PPCInstr* PPCInstr_AvBCDV128Binary ( PPCAvOp op, HReg dst,
+ HReg src1, HReg src2 ) {
PPCInstr* i = LibVEX_Alloc_inline(sizeof(PPCInstr));
- i->tag = Pin_AvBCDV128Trinary;
- i->Pin.AvBCDV128Trinary.op = op;
- i->Pin.AvBCDV128Trinary.dst = dst;
- i->Pin.AvBCDV128Trinary.src1 = src1;
- i->Pin.AvBCDV128Trinary.src2 = src2;
- i->Pin.AvBCDV128Trinary.ps = ps;
+ i->tag = Pin_AvBCDV128Binary;
+ i->Pin.AvBCDV128Binary.op = op;
+ i->Pin.AvBCDV128Binary.dst = dst;
+ i->Pin.AvBCDV128Binary.src1 = src1;
+ i->Pin.AvBCDV128Binary.src2 = src2;
return i;
}
@@ -2038,15 +2037,13 @@
ppPPCRI(i->Pin.AvHashV128Binary.s_field);
return;
- case Pin_AvBCDV128Trinary:
- vex_printf("%s(w) ", showPPCAvOp(i->Pin.AvBCDV128Trinary.op));
- ppHRegPPC(i->Pin.AvBCDV128Trinary.dst);
+ case Pin_AvBCDV128Binary:
+ vex_printf("%s(w) ", showPPCAvOp(i->Pin.AvBCDV128Binary.op));
+ ppHRegPPC(i->Pin.AvBCDV128Binary.dst);
vex_printf(",");
- ppHRegPPC(i->Pin.AvBCDV128Trinary.src1);
+ ppHRegPPC(i->Pin.AvBCDV128Binary.src1);
vex_printf(",");
- ppHRegPPC(i->Pin.AvBCDV128Trinary.src2);
- vex_printf(",");
- ppPPCRI(i->Pin.AvBCDV128Trinary.ps);
+ ppHRegPPC(i->Pin.AvBCDV128Binary.src2);
return;
case Pin_Dfp64Unary:
@@ -2511,11 +2508,10 @@
addHRegUse(u, HRmRead, i->Pin.AvHashV128Binary.src);
addRegUsage_PPCRI(u, i->Pin.AvHashV128Binary.s_field);
return;
- case Pin_AvBCDV128Trinary:
- addHRegUse(u, HRmWrite, i->Pin.AvBCDV128Trinary.dst);
- addHRegUse(u, HRmRead, i->Pin.AvBCDV128Trinary.src1);
- addHRegUse(u, HRmRead, i->Pin.AvBCDV128Trinary.src2);
- addRegUsage_PPCRI(u, i->Pin.AvBCDV128Trinary.ps);
+ case Pin_AvBCDV128Binary:
+ addHRegUse(u, HRmWrite, i->Pin.AvBCDV128Binary.dst);
+ addHRegUse(u, HRmRead, i->Pin.AvBCDV128Binary.src1);
+ addHRegUse(u, HRmRead, i->Pin.AvBCDV128Binary.src2);
return;
case Pin_Dfp64Unary:
addHRegUse(u, HRmWrite, i->Pin.Dfp64Unary.dst);
@@ -2844,11 +2840,10 @@
mapReg(m, &i->Pin.AvHashV128Binary.dst);
mapReg(m, &i->Pin.AvHashV128Binary.src);
return;
- case Pin_AvBCDV128Trinary:
- mapReg(m, &i->Pin.AvBCDV128Trinary.dst);
- mapReg(m, &i->Pin.AvBCDV128Trinary.src1);
- mapReg(m, &i->Pin.AvBCDV128Trinary.src2);
- mapRegs_PPCRI(m, i->Pin.AvBCDV128Trinary.ps);
+ case Pin_AvBCDV128Binary:
+ mapReg(m, &i->Pin.AvBCDV128Binary.dst);
+ mapReg(m, &i->Pin.AvBCDV128Binary.src1);
+ mapReg(m, &i->Pin.AvBCDV128Binary.src2);
return;
case Pin_Dfp64Unary:
mapReg(m, &i->Pin.Dfp64Unary.dst);
@@ -5104,20 +5099,22 @@
p = mkFormVX( p, 4, v_dst, v_src, s_field->Pri.Imm, opc2, endness_host );
goto done;
}
- case Pin_AvBCDV128Trinary: {
- UInt v_dst = vregEnc(i->Pin.AvBCDV128Trinary.dst);
- UInt v_src1 = vregEnc(i->Pin.AvBCDV128Trinary.src1);
- UInt v_src2 = vregEnc(i->Pin.AvBCDV128Trinary.src2);
- PPCRI* ps = i->Pin.AvBCDV128Trinary.ps;
+ case Pin_AvBCDV128Binary: {
+ UInt v_dst = vregEnc(i->Pin.AvBCDV128Binary.dst);
+ UInt v_src1 = vregEnc(i->Pin.AvBCDV128Binary.src1);
+ UInt v_src2 = vregEnc(i->Pin.AvBCDV128Binary.src2);
+ UInt ps = 0; /* Issue the instruction with ps=0. The IR code will
+ * fix up the result if ps=1.
+ */
UInt opc2;
- switch (i->Pin.AvBCDV128Trinary.op) {
+ switch (i->Pin.AvBCDV128Binary.op) {
case Pav_BCDAdd: opc2 = 1; break; // bcdadd
case Pav_BCDSub: opc2 = 65; break; // bcdsub
default:
goto bad;
}
p = mkFormVXR( p, 4, v_dst, v_src1, v_src2,
- 0x1, (ps->Pri.Imm << 9) | opc2, endness_host );
+ 0x1, ps | opc2, endness_host );
goto done;
}
case Pin_AvBin32Fx4: {
Modified: trunk/priv/host_ppc_defs.h
==============================================================================
--- trunk/priv/host_ppc_defs.h (original)
+++ trunk/priv/host_ppc_defs.h Tue Apr 26 20:52:56 2016
@@ -499,7 +499,7 @@
Pin_AvCipherV128Unary, /* AV Vector unary Cipher */
Pin_AvCipherV128Binary, /* AV Vector binary Cipher */
Pin_AvHashV128Binary, /* AV Vector binary Hash */
- Pin_AvBCDV128Trinary, /* BCD Arithmetic */
+ Pin_AvBCDV128Binary, /* BCD Arithmetic */
Pin_Dfp64Unary, /* DFP64 unary op */
Pin_Dfp128Unary, /* DFP128 unary op */
Pin_DfpShift, /* Decimal floating point shift by immediate value */
@@ -867,8 +867,7 @@
HReg dst;
HReg src1;
HReg src2;
- PPCRI* ps;
- } AvBCDV128Trinary;
+ } AvBCDV128Binary;
struct {
PPCAvOp op;
HReg dst;
@@ -1063,9 +1062,8 @@
HReg srcL, HReg srcR );
extern PPCInstr* PPCInstr_AvHashV128Binary ( PPCAvOp op, HReg dst,
HReg src, PPCRI* s_field );
-extern PPCInstr* PPCInstr_AvBCDV128Trinary ( PPCAvOp op, HReg dst,
- HReg src1, HReg src2,
- PPCRI* ps );
+extern PPCInstr* PPCInstr_AvBCDV128Binary ( PPCAvOp op, HReg dst,
+ HReg src1, HReg src2 );
extern PPCInstr* PPCInstr_Dfp64Unary ( PPCFpOp op, HReg dst, HReg src );
extern PPCInstr* PPCInstr_Dfp64Binary ( PPCFpOp op, HReg dst, HReg srcL,
HReg srcR );
Modified: trunk/priv/host_ppc_isel.c
==============================================================================
--- trunk/priv/host_ppc_isel.c (original)
+++ trunk/priv/host_ppc_isel.c Tue Apr 26 20:52:56 2016
@@ -5392,25 +5392,25 @@
addInstr(env, PPCInstr_AvHashV128Binary(op, dst, arg1, s_field));
return dst;
}
- default:
- break;
- } /* switch (e->Iex.Binop.op) */
- } /* if (e->tag == Iex_Binop) */
- if (e->tag == Iex_Triop) {
- IRTriop *triop = e->Iex.Triop.details;
- switch (triop->op) {
case Iop_BCDAdd:op = Pav_BCDAdd; goto do_AvBCDV128;
case Iop_BCDSub:op = Pav_BCDSub; goto do_AvBCDV128;
do_AvBCDV128: {
- HReg arg1 = iselVecExpr(env, triop->arg1, IEndianess);
- HReg arg2 = iselVecExpr(env, triop->arg2, IEndianess);
+ HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1, IEndianess);
+ HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2, IEndianess);
HReg dst = newVRegV(env);
- PPCRI* ps = iselWordExpr_RI(env, triop->arg3, IEndianess);
- addInstr(env, PPCInstr_AvBCDV128Trinary(op, dst, arg1, arg2, ps));
+ addInstr(env, PPCInstr_AvBCDV128Binary(op, dst, arg1, arg2));
return dst;
}
+ default:
+ break;
+ } /* switch (e->Iex.Binop.op) */
+ } /* if (e->tag == Iex_Binop) */
+
+ if (e->tag == Iex_Triop) {
+ IRTriop *triop = e->Iex.Triop.details;
+ switch (triop->op) {
case Iop_Add32Fx4: fpop = Pavfp_ADDF; goto do_32Fx4_with_rm;
case Iop_Sub32Fx4: fpop = Pavfp_SUBF; goto do_32Fx4_with_rm;
case Iop_Mul32Fx4: fpop = Pavfp_MULF; goto do_32Fx4_with_rm;
Modified: trunk/priv/ir_defs.c
==============================================================================
--- trunk/priv/ir_defs.c (original)
+++ trunk/priv/ir_defs.c Tue Apr 26 20:52:56 2016
@@ -3122,7 +3122,8 @@
case Iop_BCDAdd:
case Iop_BCDSub:
- TERNARY(Ity_V128,Ity_V128, Ity_I8, Ity_V128);
+ BINARY(Ity_V128, Ity_V128, Ity_V128);
+
case Iop_QDMull16Sx4: case Iop_QDMull32Sx2:
BINARY(Ity_I64, Ity_I64, Ity_V128);
|
|
From: <sv...@va...> - 2016-04-26 17:37:21
|
Author: carll
Date: Tue Apr 26 18:37:05 2016
New Revision: 15870
Log:
Power PC Add test suite support for ISA 3.0, part 2
The test suite support for the Power PC ISA 3.0 instructions added in
VEX commit 3217 is added in this commit.
Note, this is part 2 of 5. The NEWS file will be updated when the ISA 3.0
support is complete.
valgrind bugzilla 359767
Modified:
trunk/none/tests/ppc64/test_isa_3_0.c
trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp
trunk/none/tests/ppc64/test_isa_3_0_other.stdout.exp
Modified: trunk/none/tests/ppc64/test_isa_3_0.c
==============================================================================
--- trunk/none/tests/ppc64/test_isa_3_0.c (original)
+++ trunk/none/tests/ppc64/test_isa_3_0.c Tue Apr 26 18:37:05 2016
@@ -177,6 +177,9 @@
/* global variable, ... vector insert functions. */
volatile int x_index;
+/* global variable, used to pass shift info down to the test functions.*/
+volatile int x_shift;
+
/* groups of instruction tests, calling individual tests */
typedef void (*test_group_t) (const char *name, test_func_t func,
unsigned int test_flags);
@@ -281,6 +284,57 @@
{ NULL , NULL },
};
+static void test_dotted_extswsli (void)
+{
+#define EXTSWSLI_dotted_SHIFT(SH_X) \
+ __asm__ __volatile__ ("extswsli. %0,%1,%2" : "=r" (r17) : "r" (r14), "i" (SH_X) );
+ switch(x_shift) {
+ case SH_0:
+ EXTSWSLI_dotted_SHIFT(SH_0);
+ break;
+ case SH_1:
+ EXTSWSLI_dotted_SHIFT(SH_1);
+ break;
+ case SH_2:
+ EXTSWSLI_dotted_SHIFT(SH_2);
+ break;
+ case SH_3:
+ EXTSWSLI_dotted_SHIFT(SH_3);
+ break;
+ default:
+ printf("Unhandled shift value for extswsli. %d\n",x_shift);
+ }
+}
+
+static void test_extswsli (void)
+{
+#define EXTSWSLI_SHIFT(x) \
+ __asm__ __volatile__ ("extswsli %0,%1,%2":"=r" (r17):"r" (r14),"i"(x));
+
+ switch(x_shift) {
+ case SH_0:
+ EXTSWSLI_SHIFT(SH_0);
+ break;
+ case SH_1:
+ EXTSWSLI_SHIFT(SH_1);
+ break;
+ case SH_2:
+ EXTSWSLI_SHIFT(SH_2);
+ break;
+ case SH_3:
+ EXTSWSLI_SHIFT(SH_3);
+ break;
+ default:
+ printf("Unhandled shift value for extswsli %d\n",x_shift);
+ }
+}
+
+static test_list_t testgroup_shifted_one[] = {
+ { &test_extswsli, "extswsli ",},
+ { &test_dotted_extswsli, "extswsli.",},
+ { NULL, NULL,},
+};
+
static void test_vabsdub(void) {
__asm__ __volatile__ ("vabsdub %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
}
@@ -293,10 +347,96 @@
__asm__ __volatile__ ("vabsduw %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
}
+static void test_vcmpneb(void) {
+ __asm__ __volatile__ ("vcmpneb %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_dotted_vcmpneb(void) {
+ __asm__ __volatile__ ("vcmpneb. %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vcmpnezb(void) {
+ __asm__ __volatile__ ("vcmpnezb %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_dotted_vcmpnezb(void) {
+ __asm__ __volatile__ ("vcmpnezb. %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vcmpneh(void) {
+ __asm__ __volatile__ ("vcmpneh %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_dotted_vcmpneh(void) {
+ __asm__ __volatile__ ("vcmpneh. %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vcmpnezh(void) {
+ __asm__ __volatile__ ("vcmpnezh %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_dotted_vcmpnezh(void) {
+ __asm__ __volatile__ ("vcmpnezh. %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vcmpnew(void) {
+ __asm__ __volatile__ ("vcmpnew %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_dotted_vcmpnew(void) {
+ __asm__ __volatile__ ("vcmpnew. %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vcmpnezw(void) {
+ __asm__ __volatile__ ("vcmpnezw %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_dotted_vcmpnezw(void) {
+ __asm__ __volatile__ ("vcmpnezw. %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vrlwmi(void) {
+ __asm__ __volatile__ ("vrlwmi %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vrldmi(void) {
+ __asm__ __volatile__ ("vrldmi %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vbpermd(void) {
+/* vector bit permute doubleword */
+ __asm__ __volatile__ ("vbpermd %0, %1, %2 " : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vrlwnm(void) {
+ __asm__ __volatile__ ("vrlwnm %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
+static void test_vrldnm(void) {
+ __asm__ __volatile__ ("vrldnm %0, %1, %2" : "+v" (vec_xt): "v" (vec_xa), "v" (vec_xb));
+}
+
static test_list_t testgroup_vsx_absolute[] = {
{ &test_vabsdub , "vabsdub" },
{ &test_vabsduh , "vabsduh" },
{ &test_vabsduw , "vabsduw" },
+ { &test_vcmpneb , "vcmpneb" },
+ { &test_dotted_vcmpneb , "vcmpneb." },
+ { &test_vcmpnezb , "vcmpnezb" },
+ { &test_dotted_vcmpnezb, "vcmpnezb." },
+ { &test_vcmpneh , "vcmpneh" },
+ { &test_dotted_vcmpneh , "vcmpneh." },
+ { &test_vcmpnezh , "vcmpnezh" },
+ { &test_dotted_vcmpnezh, "vcmpnezh." },
+ { &test_vcmpnew , "vcmpnew" },
+ { &test_dotted_vcmpnew , "vcmpnew." },
+ { &test_vcmpnezw , "vcmpnezw" },
+ { &test_dotted_vcmpnezw, "vcmpnezw." },
+ { &test_vrlwnm , "vrlwnm" },
+ { &test_vrlwmi , "vrlwmi" },
+ { &test_vrldnm , "vrldnm" },
+ { &test_vrldmi , "vrldmi" },
+ { &test_vbpermd , "vbpermd" },
{ NULL , NULL },
};
@@ -659,6 +799,40 @@
{ NULL , NULL },
};
+static void test_lxvl(void) {
+ __asm__ __volatile__ ("lxvl %0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_stxvl(void) {
+ __asm__ __volatile__ ("stxvl %0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_lxsibzx(void) {
+ __asm__ __volatile__ ("lxsibzx %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_lxsihzx(void) {
+ __asm__ __volatile__ ("lxsihzx %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_stxsibx(void) {
+ __asm__ __volatile__ ("stxsibx %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+static void test_stxsihx(void) {
+ __asm__ __volatile__ ("stxsihx %x0, 14, 15" : "=wa" (vec_xt));
+}
+
+static test_list_t testgroup_vector_scalar_loadstore_length[] = {
+ { &test_lxvl , "lxvl " },
+ { &test_lxsibzx , "lxsibzx " },
+ { &test_lxsihzx , "lxsihzx " },
+ { &test_stxvl , "stxvl " },
+ { &test_stxsibx , "stxsibx " },
+ { &test_stxsihx , "stxsihx " },
+ { NULL , NULL },
+};
+
/* move from/to VSR */
static void test_mfvsrld (void)
{
@@ -684,6 +858,113 @@
{ NULL , NULL },
};
+/* vector count {leading, trailing} zero least-significant bits byte.
+ * roughly... how many leading/trailing bytes are even. */
+static void test_vclzlsbb(void) {
+ __asm__ __volatile__ ("vclzlsbb %0, %1" : "=r"(r14) : "v"(vec_xb));
+}
+
+static void test_vctzlsbb(void) {
+ __asm__ __volatile__ ("vctzlsbb %0, %1" : "=r"(r14) : "v"(vec_xb));
+}
+
+static test_list_t testgroup_vector_count_bytes[] = {
+ { &test_vclzlsbb, "vclzlsbb" },
+ { &test_vctzlsbb, "vctzlsbb" },
+ { NULL , NULL },
+};
+
+static void test_vextsb2w(void) {
+ __asm__ __volatile__ ("vextsb2w %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vextsb2d(void) {
+ __asm__ __volatile__ ("vextsb2d %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vextsh2w(void) {
+ __asm__ __volatile__ ("vextsh2w %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vextsh2d(void) {
+ __asm__ __volatile__ ("vextsh2d %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vextsw2d(void) {
+ __asm__ __volatile__ ("vextsw2d %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vnegw(void) {
+ __asm__ __volatile__ ("vnegw %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vnegd(void) {
+ __asm__ __volatile__ ("vnegd %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vprtybw(void) {
+ __asm__ __volatile__ ("vprtybw %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vprtybd(void) {
+ __asm__ __volatile__ ("vprtybd %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static void test_vprtybq(void) {
+ __asm__ __volatile__ ("vprtybq %0, %1" : "=v"(vec_xt) : "v"(vec_xb));
+}
+
+static test_list_t testgroup_vector_extend_sign[] = {
+ { &test_vextsb2w, "vextsb2w" },
+ { &test_vextsb2d, "vextsb2d" },
+ { &test_vextsh2w, "vextsh2w" },
+ { &test_vextsh2d, "vextsh2d" },
+ { &test_vextsw2d, "vextsw2d" },
+ { &test_vnegw , "vnegw " },
+ { &test_vnegd , "vnegd " },
+ { &test_vprtybw , "vprtybw " },
+ { &test_vprtybd , "vprtybd " },
+ { &test_vprtybq , "vprtybq " },
+ { NULL , NULL },
+};
+
+static void test_vextublx(void) {
+ __asm__ __volatile__ ("vextublx %0, %1, %2" : "=r"(r14) : "r" (r15), "v" (vec_xb));
+}
+
+static void test_vextubrx(void) {
+ __asm__ __volatile__ ("vextubrx %0, %1, %2" : "=r"(r14) : "r"(r15), "v"(vec_xb));
+}
+
+static void test_vextuhlx(void) {
+ if (r15 > 14) return; // limit to 14 halfwords
+ __asm__ __volatile__ ("vextuhlx %0, %1, %2" : "=r"(r14) : "r"(r15), "v"(vec_xb));
+}
+
+static void test_vextuhrx(void) {
+ if (r15 > 14) return; // limit to 14 halfwords
+ __asm__ __volatile__ ("vextuhrx %0, %1, %2" : "=r"(r14) : "r"(r15), "v"(vec_xb));
+}
+
+static void test_vextuwlx(void) {
+ if (r15 > 12) return; // limit to 12 words
+ __asm__ __volatile__ ("vextuwlx %0, %1, %2" : "=r"(r14) : "r"(r15), "v"(vec_xb));
+}
+
+static void test_vextuwrx(void) {
+ if (r15 > 12) return; // limit to 12 words
+ __asm__ __volatile__ ("vextuwrx %0, %1, %2" : "=r"(r14) : "r"(r15), "v"(vec_xb));
+}
+
+static test_list_t testgroup_vector_extract[] = {
+ { &test_vextublx, "vextublx" },
+ { &test_vextubrx, "vextubrx" },
+ { &test_vextuhlx, "vextuhlx" },
+ { &test_vextuhrx, "vextuhrx" },
+ { &test_vextuwlx, "vextuwlx" },
+ { &test_vextuwrx, "vextuwrx" },
+ { NULL , NULL },
+};
/* ###### begin all_tests table. */
@@ -723,6 +1004,11 @@
PPC_ALTIVEC | PPC_LOGICAL | PPC_ONE_ARG,
},
{
+ testgroup_vector_extend_sign,
+ "ppc vector extend sign",
+ PPC_ALTIVEC | PPC_LOGICAL | PPC_TWO_ARGS,
+ },
+ {
testgroup_vsx_xxpermute,
"ppc vector permutes",
PPC_ALTIVEC | PPC_PERMUTE | PPC_THREE_ARGS,
@@ -738,6 +1024,21 @@
PPC_ALTIVEC | PPC_INSERTEXTRACT | PPC_ONE_IMM,
},
{
+ testgroup_vector_extract,
+ "ppc vector extract from vector to reg",
+ PPC_ALTIVEC | PPC_INSERTEXTRACT | PPC_TWO_ARGS,
+ },
+ {
+ testgroup_vector_count_bytes,
+ "ppc vector count leading/trailing bytes",
+ PPC_ALTIVEC | PPC_POPCNT,
+ },
+ {
+ testgroup_vector_scalar_loadstore_length,
+ "ppc vector load/store",
+ PPC_ALTIVEC | PPC_LDST | PPC_ONE_IMM,
+ },
+ {
testgroup_vector_loadstore,
"ppc vector load/store",
PPC_ALTIVEC | PPC_LDST | PPC_TWO_ARGS,
@@ -745,7 +1046,12 @@
{
testgroup_vectorscalar_move_tofrom,
"ppc vector scalar move to/from",
- PPC_MISC,
+ PPC_MISC | PPC_TWO_ARGS,
+ },
+ {
+ testgroup_shifted_one,
+ "ppc one argument plus shift",
+ PPC_MISC | PPC_THREE_ARGS,
},
{ NULL, NULL, 0x00000000, },
};
@@ -1153,13 +1459,147 @@
(*test_function)();
- printf("=> %016lx %016lx %lx %016lx ", vec_xt[1], vec_xt[0],
+ printf("=> %016lx %016lx %lx %016lx", vec_xt[1], vec_xt[0],
(long unsigned)r14, (long unsigned)r15 );
printf("\n");
}
}
}
+/* Some of the load/store vector instructions use a length value that
+ * is stored in bits 0:7 of RB. */
+#define uses_bits_0to7(instruction_name) ( \
+ (strncmp(instruction_name, "lxvl " ,5) == 0) || \
+ (strncmp(instruction_name, "lxvll " ,6) == 0) || \
+ (strncmp(instruction_name, "stxvl " ,6) == 0) || \
+ (strncmp(instruction_name, "stxvll ",7) == 0) )
+
+static void testfunction_vector_scalar_loadstore_length (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_flags) {
+ /* exercises vector loads from memory, and vector stores from memory.
+ * with length specification.
+ * <load or store instruction> XS, RA, RB
+ * For these tests, RA (i.e. EA) is address of source/dest and can
+ * not be zero.
+ * The length value is in rb. For a subset of these instructions,
+ * the length is stored in bits 0:7, versus 56:63 of r15.
+ */
+ int i;
+ unsigned long l;
+ int buffer_pattern;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 2) {
+ for (l = 0; l <= 16; l += 4) {
+
+ for (buffer_pattern = 0; buffer_pattern < MAX_BUFFER_PATTERNS;
+ buffer_pattern++) {
+
+ /* set patterns on both ends */
+ vec_xt = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ r14 = (unsigned long) & buffer;
+
+ if (uses_bits_0to7(instruction_name)) {
+ /* length is stored in bits 0:7 of gpr[r15]. */
+ r15 = (unsigned long)((0xff & l) << 56);
+
+ } else {
+ /* length is stored in gpr[r15]. */
+ r15 = l;
+ }
+
+ initialize_buffer(buffer_pattern);
+
+ printf("%s ", instruction_name);
+ printf("%016lx %016lx ", vec_xt[1], vec_xt[0] );
+ if (uses_bits_0to7(instruction_name)) {
+ printf(" &0x%lx l = 0x%2lx ",
+ (long unsigned)r14, (long unsigned)r15>>56 );
+
+ } else {
+ printf(" &0x%lx l = 0x%2lx ",
+ (long unsigned)r14, (long unsigned)r15 );
+ }
+
+ dump_small_buffer();
+
+ (*test_function)();
+
+ printf("=> %016lx %016lx & %16lx %16lx", vec_xt[1], vec_xt[0],
+ (long unsigned)r14, (long unsigned)r15 );
+ printf("\n");
+ }
+ }
+ }
+}
+
+static void testfunction_vector_count_bytes (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_flags)
+{
+ int i;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 2) {
+ vec_xb = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ r14 = 0;
+
+ printf("%s ", instruction_name);
+ printf("%016lx %016lx %2d ", vec_xb[1], vec_xb[0], (unsigned)r14);
+
+ (*test_function)();
+
+ printf("=> %2d\n", (unsigned)r14 );
+ }
+}
+
+static void testfunction_vector_extract (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_flags)
+{
+ int i;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 2) {
+ vec_xb = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ for (r15 = 0; r15 < 16; r15++) {
+ r14 = 0;
+
+ printf("%s ", instruction_name);
+ printf("%016lx %016lx %2d ", vec_xb[1], vec_xb[0], (unsigned)r15);
+
+ (*test_function)();
+
+ printf("=> %16lx\n", (long unsigned)r14 );
+ }
+ }
+}
+
+static void testfunction_vector_extend_sign (const char* instruction_name,
+ test_func_t test_function,
+ unsigned int ignore_flags)
+{
+ int i;
+
+ VERBOSE_FUNCTION_CALLOUT
+
+ for (i = 0; i < nb_vargs; i += 2) {
+ vec_xb = (vector unsigned long){vsxargs[i], vsxargs[i+1]};
+ vec_xt = (vector unsigned long){0, 0};
+
+ printf("%s ", instruction_name);
+ printf("%016lx %016lx ", vec_xb[1], vec_xb[0]);
+
+ (*test_function)();
+
+ printf("=> %016lx %016lx\n", vec_xt[1], vec_xt[0]);
+ }
+}
+
/* packed binary decimal misc */
#define convert_from_zoned(instruction_name) (strncmp(instruction_name, "bcdcfz", 6) ==0 )
@@ -1288,6 +1728,7 @@
printf("\n");
}
+
/* ######## begin grand testing loops. */
typedef struct insn_sel_flags_t_struct {
int one_arg, two_args, three_args, four_args, cmp_args;
@@ -1408,6 +1849,10 @@
group_function = &testfunction_vector_logical_one;
break;
+ case PPC_TWO_ARGS:
+ group_function = &testfunction_vector_extend_sign;
+ break;
+
case PPC_FOUR_ARGS:
group_function = &testfunction_vector_logical_four;
break;
@@ -1424,6 +1869,10 @@
group_function = &testfunction_vector_insert_or_extract_immediate;
break;
+ case PPC_TWO_ARGS:
+ group_function = testfunction_vector_extract;
+ break;
+
default:
printf("ERROR: PPC_ALTIVEC, PPC_INSERTEXTRACT, unhandled number of arguments. 0x%08x\n", nb_args);
continue;
@@ -1436,6 +1885,11 @@
case PPC_LDST:
switch(nb_args) {
+ case PPC_ONE_IMM:
+ /* Register holds immediate length value */
+ group_function = &testfunction_vector_scalar_loadstore_length;
+ break;
+
case PPC_TWO_ARGS:
/* Register holds address of buffer */
group_function = &testfunction_vector_loadstore;
@@ -1447,8 +1901,8 @@
} /* switch(PPC_LDST, nb_args) */
break;
- case PPC_MISC:
- group_function = &testfunction_vectorscalar_move_tofrom;
+ case PPC_POPCNT:
+ group_function = &testfunction_vector_count_bytes;
break;
default:
@@ -1457,6 +1911,21 @@
} /* switch (PPC_ALTIVEC, type) */
break;
+ case PPC_MISC:
+ switch(nb_args) {
+ case PPC_TWO_ARGS:
+ group_function = &testfunction_vectorscalar_move_tofrom;
+ break;
+ case PPC_THREE_ARGS:
+ group_function = &testfunction_one_arg_with_shift;
+ break;
+ default:
+ printf("ERROR: PPC_MISC, unhandled number of arguments. 0x%08x\n", nb_args);
+ continue;
+ } /* switch(PPC_MISC, nb_args) */
+
+ break;
+
default:
printf("ERROR: unknown instruction family %08x\n", family);
continue;
Modified: trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp
==============================================================================
--- trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp (original)
+++ trunk/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp Tue Apr 26 18:37:05 2016
@@ -111,7 +111,636 @@
vabsduw xa:00001f0800001f10 00001f0000001f02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:aaaa8baaaaaa8ba8 aaaa8ba2aaaa8b9a (00000000)
vabsduw xa:00001f0800001f10 00001f0000001f02 xb:5555555555555555 5555555555555555 => xt:5555365555553653 5555364d55553645 (00000000)
-All done. Tested 3 different instructions
+vcmpneb xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vcmpneb xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:0000000000000000 0000000000000000 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:0000000000000000 0000000000000000 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:0000000000000000 0000000000000000 (00000000)
+vcmpneb xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:0102010201020102 08090a0b0c0d0e0f xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:0102010201020102 08090a0b0c0d0e0f xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff 0000ffffffffffff (00000000)
+vcmpneb xa:0102010201020102 08090a0b0c0d0e0f xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:0102010201020102 08090a0b0c0d0e0f xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffff00ffff (00000000)
+vcmpneb xa:ced0deede5ecef00 00115e7eadbabec0 xb:0000000000000000 0000000000000000 => xt:00ffffffffffffff ffffffffffffff00 (00000000)
+vcmpneb xa:ced0deede5ecef00 00115e7eadbabec0 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:ced0deede5ecef00 00115e7eadbabec0 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:ced0deede5ecef00 00115e7eadbabec0 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:00ffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:8899aabbccddeeff 0011223344556677 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffff00ffffffffff (00000000)
+vcmpneb xa:8899aabbccddeeff 0011223344556677 xb:5555555555555555 5555555555555555 => xt:ffffffffff00ffff ffffffffffffffff (00000000)
+vcmpneb xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000ff000000ffff 0000ffff0000ffff (00000000)
+vcmpneb xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:0000100800001010 0000100000001002 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:0000100800001010 0000100000001002 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:0000ff000000ffff 0000ffff0000ffff (00000000)
+vcmpneb xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:00001c0800001c10 00001c0000001c02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:00001c0800001c10 00001c0000001c02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:0000ff000000ffff 0000ffff0000ffff (00000000)
+vcmpneb xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:00001f0800001f10 00001f0000001f02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneb xa:00001f0800001f10 00001f0000001f02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+
+vcmpneb. xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000020)
+vcmpneb. xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:0000000000000000 0000000000000000 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:0000000000000000 0000000000000000 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:0000000000000000 0000000000000000 (00000020)
+vcmpneb. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:0102010201020102 08090a0b0c0d0e0f xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:0102010201020102 08090a0b0c0d0e0f xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff 0000ffffffffffff (00000000)
+vcmpneb. xa:0102010201020102 08090a0b0c0d0e0f xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:0102010201020102 08090a0b0c0d0e0f xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffff00ffff (00000000)
+vcmpneb. xa:ced0deede5ecef00 00115e7eadbabec0 xb:0000000000000000 0000000000000000 => xt:00ffffffffffffff ffffffffffffff00 (00000000)
+vcmpneb. xa:ced0deede5ecef00 00115e7eadbabec0 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:ced0deede5ecef00 00115e7eadbabec0 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:ced0deede5ecef00 00115e7eadbabec0 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:00ffffffffffffff ffffffffffffffff (00000000)
+vcmpneb. xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:8899aabbccddeeff 0011223344556677 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffff00ffffffffff (00000000)
+vcmpneb. xa:8899aabbccddeeff 0011223344556677 xb:5555555555555555 5555555555555555 => xt:ffffffffff00ffff ffffffffffffffff (00000000)
+vcmpneb. xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000ff000000ffff 0000ffff0000ffff (00000000)
+vcmpneb. xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:0000100800001010 0000100000001002 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:0000100800001010 0000100000001002 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:0000ff000000ffff 0000ffff0000ffff (00000000)
+vcmpneb. xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:00001c0800001c10 00001c0000001c02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:00001c0800001c10 00001c0000001c02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:0000ff000000ffff 0000ffff0000ffff (00000000)
+vcmpneb. xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:00001f0800001f10 00001f0000001f02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneb. xa:00001f0800001f10 00001f0000001f02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+
+vcmpnezb xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:0000000000000000 0000000000000000 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:0000000000000000 0000000000000000 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:0000000000000000 0000000000000000 (00000000)
+vcmpnezb xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:0102010201020102 08090a0b0c0d0e0f xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:0102010201020102 08090a0b0c0d0e0f xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff 0000ffffffffffff (00000000)
+vcmpnezb xa:0102010201020102 08090a0b0c0d0e0f xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:0102010201020102 08090a0b0c0d0e0f xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffff00ffff (00000000)
+vcmpnezb xa:ced0deede5ecef00 00115e7eadbabec0 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:ced0deede5ecef00 00115e7eadbabec0 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:ced0deede5ecef00 00115e7eadbabec0 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:ced0deede5ecef00 00115e7eadbabec0 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:8899aabbccddeeff 0011223344556677 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffff00ffffffffff (00000000)
+vcmpnezb xa:8899aabbccddeeff 0011223344556677 xb:5555555555555555 5555555555555555 => xt:ffffffffff00ffff ffffffffffffffff (00000000)
+vcmpnezb xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:0000100800001010 0000100000001002 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:0000100800001010 0000100000001002 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:00001c0800001c10 00001c0000001c02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:00001c0800001c10 00001c0000001c02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:00001f0800001f10 00001f0000001f02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezb xa:00001f0800001f10 00001f0000001f02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+
+vcmpnezb. xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:0000000000000000 0000000000000000 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:0000000000000000 0000000000000000 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:0000000000000000 0000000000000000 (00000020)
+vcmpnezb. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:0102010201020102 08090a0b0c0d0e0f xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:0102010201020102 08090a0b0c0d0e0f xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff 0000ffffffffffff (00000000)
+vcmpnezb. xa:0102010201020102 08090a0b0c0d0e0f xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:0102010201020102 08090a0b0c0d0e0f xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffff00ffff (00000000)
+vcmpnezb. xa:ced0deede5ecef00 00115e7eadbabec0 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:ced0deede5ecef00 00115e7eadbabec0 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:ced0deede5ecef00 00115e7eadbabec0 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:ced0deede5ecef00 00115e7eadbabec0 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:8899aabbccddeeff 0011223344556677 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffff00ffffffffff (00000000)
+vcmpnezb. xa:8899aabbccddeeff 0011223344556677 xb:5555555555555555 5555555555555555 => xt:ffffffffff00ffff ffffffffffffffff (00000000)
+vcmpnezb. xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:0000100800001010 0000100000001002 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:0000100800001010 0000100000001002 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:00001c0800001c10 00001c0000001c02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:00001c0800001c10 00001c0000001c02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:00001f0800001f10 00001f0000001f02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezb. xa:00001f0800001f10 00001f0000001f02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+
+vcmpneh xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vcmpneh xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:0000000000000000 0000000000000000 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:0000000000000000 0000000000000000 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:0000000000000000 0000000000000000 (00000000)
+vcmpneh xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:0102010201020102 08090a0b0c0d0e0f xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:0102010201020102 08090a0b0c0d0e0f xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff 0000ffffffffffff (00000000)
+vcmpneh xa:0102010201020102 08090a0b0c0d0e0f xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:0102010201020102 08090a0b0c0d0e0f xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:ced0deede5ecef00 00115e7eadbabec0 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:ced0deede5ecef00 00115e7eadbabec0 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:ced0deede5ecef00 00115e7eadbabec0 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:ced0deede5ecef00 00115e7eadbabec0 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:8899aabbccddeeff 0011223344556677 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:8899aabbccddeeff 0011223344556677 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000ffff0000ffff 0000ffff0000ffff (00000000)
+vcmpneh xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:0000100800001010 0000100000001002 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:0000100800001010 0000100000001002 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:0000ffff0000ffff 0000ffff0000ffff (00000000)
+vcmpneh xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:00001c0800001c10 00001c0000001c02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:00001c0800001c10 00001c0000001c02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:0000ffff0000ffff 0000ffff0000ffff (00000000)
+vcmpneh xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:00001f0800001f10 00001f0000001f02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpneh xa:00001f0800001f10 00001f0000001f02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+
+vcmpneh. xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000020)
+vcmpneh. xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:0000000000000000 0000000000000000 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:0000000000000000 0000000000000000 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:0000000000000000 0000000000000000 (00000020)
+vcmpneh. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:0102010201020102 08090a0b0c0d0e0f xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:0102010201020102 08090a0b0c0d0e0f xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff 0000ffffffffffff (00000000)
+vcmpneh. xa:0102010201020102 08090a0b0c0d0e0f xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:0102010201020102 08090a0b0c0d0e0f xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:ced0deede5ecef00 00115e7eadbabec0 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:ced0deede5ecef00 00115e7eadbabec0 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:ced0deede5ecef00 00115e7eadbabec0 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:ced0deede5ecef00 00115e7eadbabec0 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:8899aabbccddeeff 0011223344556677 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:8899aabbccddeeff 0011223344556677 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:0000ffff0000ffff 0000ffff0000ffff (00000000)
+vcmpneh. xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:0000100800001010 0000100000001002 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:0000100800001010 0000100000001002 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:0000ffff0000ffff 0000ffff0000ffff (00000000)
+vcmpneh. xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:00001c0800001c10 00001c0000001c02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:00001c0800001c10 00001c0000001c02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:0000ffff0000ffff 0000ffff0000ffff (00000000)
+vcmpneh. xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:00001f0800001f10 00001f0000001f02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpneh. xa:00001f0800001f10 00001f0000001f02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+
+vcmpnezh xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:0000000000000000 0000000000000000 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:0000000000000000 0000000000000000 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:0000000000000000 0000000000000000 (00000000)
+vcmpnezh xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:0102010201020102 08090a0b0c0d0e0f xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:0102010201020102 08090a0b0c0d0e0f xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff 0000ffffffffffff (00000000)
+vcmpnezh xa:0102010201020102 08090a0b0c0d0e0f xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:0102010201020102 08090a0b0c0d0e0f xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:ced0deede5ecef00 00115e7eadbabec0 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:ced0deede5ecef00 00115e7eadbabec0 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:ced0deede5ecef00 00115e7eadbabec0 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:ced0deede5ecef00 00115e7eadbabec0 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:8899aabbccddeeff 0011223344556677 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:8899aabbccddeeff 0011223344556677 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:0000100800001010 0000100000001002 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:0000100800001010 0000100000001002 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:00001c0800001c10 00001c0000001c02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:00001c0800001c10 00001c0000001c02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:00001f0800001f10 00001f0000001f02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnezh xa:00001f0800001f10 00001f0000001f02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+
+vcmpnezh. xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:0000000000000000 0000000000000000 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:0000000000000000 0000000000000000 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:0000000000000000 0000000000000000 (00000020)
+vcmpnezh. xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:0102010201020102 08090a0b0c0d0e0f xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:0102010201020102 08090a0b0c0d0e0f xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff 0000ffffffffffff (00000000)
+vcmpnezh. xa:0102010201020102 08090a0b0c0d0e0f xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:0102010201020102 08090a0b0c0d0e0f xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:070d111d1e555e70 7ea1a5a7abadb0ba xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:ced0deede5ecef00 00115e7eadbabec0 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:ced0deede5ecef00 00115e7eadbabec0 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:ced0deede5ecef00 00115e7eadbabec0 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:ced0deede5ecef00 00115e7eadbabec0 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:8899aabbccddeeff 0011223344556677 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:8899aabbccddeeff 0011223344556677 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:8899aabbccddeeff 0011223344556677 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:8899aabbccddeeff 0011223344556677 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:0000100800001010 0000100000001002 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:0000100800001010 0000100000001002 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:0000100800001010 0000100000001002 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:0000100800001010 0000100000001002 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:00001c0800001c10 00001c0000001c02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:00001c0800001c10 00001c0000001c02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:00001c0800001c10 00001c0000001c02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:00001c0800001c10 00001c0000001c02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:00001f0800001f10 00001f0000001f02 xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:00001f0800001f10 00001f0000001f02 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:00001f0800001f10 00001f0000001f02 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000080)
+vcmpnezh. xa:00001f0800001f10 00001f0000001f02 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000080)
+
+vcmpnew xa:0000000000000000 0000000000000000 xb:0000000000000000 0000000000000000 => xt:0000000000000000 0000000000000000 (00000000)
+vcmpnew xa:0000000000000000 0000000000000000 xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:0000000000000000 0000000000000000 xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:0000000000000000 0000000000000000 xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa => xt:0000000000000000 0000000000000000 (00000000)
+vcmpnew xa:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa xb:5555555555555555 5555555555555555 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:0102010201020102 08090a0b0c0d0e0f xb:0000000000000000 0000000000000000 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:0102010201020102 08090a0b0c0d0e0f xb:0102030405060708 0102030405060708 => xt:ffffffffffffffff ffffffffffffffff (00000000)
+vcmpnew xa:0102010201020102 08090a0b0c0d0e0f xb:aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa ...
[truncated message content] |
|
From: <sv...@va...> - 2016-04-26 17:31:58
|
Author: carll
Date: Tue Apr 26 18:31:47 2016
New Revision: 3217
Log:
Power PC Add support for ISA 3.0, part 2
Added support to emulate the lxvl, stxvl, vcmpneb, vcmpnezb,
vcmpneh, vcmpnezh, vcmpnew, vcmpnezw, vctzlsbb, vclzlsbb,
vextublx, vextuhlx, vextuhrx, vextuhlx, vextuwrx, vextuwlx,
vextsb2w, vextsh2w, vextsb2d, vextsh2d, vextsw2d, vnegw,
vnegd, vrlwnm, vrlwmi, vrldnm, vrldmi, vprtybw, vprtybd,
vprtybq, vbpermd, lxsibzx, lxsihzx, stxsibx, stxsihx instructions.
valgrind bugzilla 359767
Modified:
trunk/priv/guest_ppc_toIR.c
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Tue Apr 26 18:31:47 2016
@@ -689,6 +689,38 @@
unop(Iop_1Uto32, arg2)));
}
+static inline IRExpr* mkXOr4_32( IRTemp t0, IRTemp t1, IRTemp t2,
+ IRTemp t3 )
+{
+ return binop( Iop_Xor32,
+ binop( Iop_Xor32, mkexpr( t0 ), mkexpr( t1 ) ),
+ binop( Iop_Xor32, mkexpr( t2 ), mkexpr( t3 ) ) );
+}
+
+static inline IRExpr* mkOr3_V128( IRTemp t0, IRTemp t1, IRTemp t2 )
+{
+ return binop( Iop_OrV128,
+ mkexpr( t0 ),
+ binop( Iop_OrV128, mkexpr( t1 ), mkexpr( t2 ) ) );
+}
+
+static inline IRExpr* mkOr4_V128( IRTemp t0, IRTemp t1, IRTemp t2,
+ IRTemp t3 )
+{
+ return binop( Iop_OrV128,
+ binop( Iop_OrV128, mkexpr( t0 ), mkexpr( t1 ) ),
+ binop( Iop_OrV128, mkexpr( t2 ), mkexpr( t3 ) ) );
+}
+
+static inline IRExpr* mkOr4_V128_expr( IRExpr* t0, IRExpr* t1, IRExpr* t2,
+ IRExpr* t3 )
+{
+ /* arguments are already expressions */
+ return binop( Iop_OrV128,
+ binop( Iop_OrV128, ( t0 ), ( t1 ) ),
+ binop( Iop_OrV128, ( t2 ), ( t3 ) ) );
+}
+
/* expand V128_8Ux16 to 2x V128_16Ux8's */
static void expand8Ux16( IRExpr* vIn,
/*OUTs*/ IRTemp* vEvn, IRTemp* vOdd )
@@ -889,6 +921,20 @@
);
}
+static IRExpr* extract_field_from_vector( IRTemp vB, IRExpr* index, UInt mask)
+{
+ /* vB is a vector, extract bits starting at index to size of mask */
+ return unop( Iop_V128to64,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ mkexpr( vB ),
+ unop( Iop_64to8,
+ binop( Iop_Mul64, index,
+ mkU64( 8 ) ) ) ),
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( mask ) ) ) );
+}
/* Signed saturating narrow 64S to 32 */
static IRExpr* mkQNarrow64Sto32 ( IRExpr* t64 )
@@ -13138,6 +13184,598 @@
}
/*
+Vector Extend Sign Instructions
+*/
+static Bool dis_av_extend_sign_count_zero ( UInt theInstr, UInt allow_isa_3_0 )
+{
+ /* VX-Form, sort of, the A register field is used to select the specific
+ * sign extension instruction or count leading/trailing zero LSB
+ * instruction.
+ */
+
+ UChar opc1 = ifieldOPC( theInstr );
+ UChar rT_addr = ifieldRegDS (theInstr );
+ UChar rA_addr = ifieldRegA( theInstr );
+ UChar vB_addr = ifieldRegB( theInstr );
+ UInt opc2 = IFIELD( theInstr, 0, 11 );
+
+ IRTemp vB = newTemp( Ity_V128 );
+ IRTemp vT = newTemp( Ity_V128 );
+
+ assign( vB, getVReg ( vB_addr ) );
+
+ if ( ( opc1 != 0x4 ) && ( opc2 != 0x602 ) ) {
+ vex_printf("dis_av_extend_sign(ppc)(instr)\n");
+ return False;
+ }
+
+ switch ( rA_addr ) {
+ case 0:
+ case 1:
+ {
+ UInt i;
+ IRTemp count[17];
+ IRTemp bit_zero[16];
+ IRTemp byte_mask[17];
+
+ /* These instructions store the result in the general purpose
+ * register in the rT_addr field.
+ */
+
+ byte_mask[0] = newTemp( Ity_I32 );
+ count[0] = newTemp( Ity_I32 );
+ assign( count[0], mkU32( 0 ) );
+ assign( byte_mask[0], mkU32( 0x1 ) );
+
+ if ( rA_addr == 0 ) {
+ // vclzlsbb (Vector Count Leading Zero Least-Significant Bits Byte)
+ DIP("vclzlsbb %d,v%d\n", rT_addr, vB_addr);
+
+ } else {
+ // vctzlsbb (Vector Count Trailing Zero Least-Significant Bits Byte)
+ DIP("vctzlsbb %d,v%d\n", rT_addr, vB_addr);
+ }
+
+ for( i = 0; i < 16; i++ ) {
+ byte_mask[i+1] = newTemp( Ity_I32 );
+ count[i+1] = newTemp( Ity_I32 );
+ bit_zero[i] = newTemp( Ity_I1 );
+
+ /* bit_zero[i] = 0x0 until the first 1 bit is found in lsb of
+ * byte. When the first 1 bit is found it causes the byte_mask
+ * to change from 0x1 to 0x0. Thus the AND of the lsb and byte_mask
+ * will be zero which will be equal to the zero byte_mask causing
+ * the value of bit_zero[i] to be equal to 0x1 for all remaining bits.
+ */
+
+ if ( rA_addr == 0 )
+ /* leading zero bit in byte count,
+ work bytes from left to right
+ */
+ assign( bit_zero[i],
+ binop( Iop_CmpEQ32,
+ binop( Iop_And32,
+ unop( Iop_V128to32,
+ binop( Iop_ShrV128,
+ mkexpr( vB ),
+ mkU8( ( 15 - i) * 8 ) ) ),
+ mkexpr( byte_mask[i] ) ),
+ mkexpr( byte_mask[i] ) ) );
+
+ else if ( rA_addr == 1 )
+ /* trailing zero bit in byte count,
+ * work bytes from right to left
+ */
+ assign( bit_zero[i],
+ binop( Iop_CmpEQ32,
+ binop( Iop_And32,
+ unop( Iop_V128to32,
+ binop( Iop_ShrV128,
+ mkexpr( vB ),
+ mkU8( i * 8 ) ) ),
+ mkexpr( byte_mask[i] ) ),
+ mkexpr( byte_mask[i] ) ) );
+
+ /* Increment count as long as bit_zero = 0 */
+ assign( count[i+1], binop( Iop_Add32,
+ mkexpr( count[i] ),
+ unop( Iop_1Uto32,
+ unop( Iop_Not1,
+ mkexpr( bit_zero[i] ) ) ) ) );
+
+ /* If comparison fails to find a zero bit, set the byte_mask to zero
+ * for all future comparisons so there will be no more matches.
+ */
+ assign( byte_mask[i+1],
+ binop( Iop_And32,
+ unop( Iop_1Uto32,
+ unop( Iop_Not1,
+ mkexpr( bit_zero[i] ) ) ),
+ mkexpr( byte_mask[i] ) ) );
+ }
+ putIReg( rT_addr, unop( Iop_32Uto64, mkexpr( count[16] ) ) );
+ return True;
+ }
+
+ case 6: // vnegw, Vector Negate Word
+ DIP("vnegw v%d,%d,v%d", rT_addr, rA_addr, vB_addr);
+
+ /* multiply each word by -1 */
+ assign( vT, binop( Iop_Mul32x4, mkexpr( vB ), mkV128( 0xFFFF ) ) );
+ break;
+
+ case 7: // vnegd, Vector Negate Doubleword
+ DIP("vnegd v%d,%d,v%d", rT_addr, rA_addr, vB_addr);
+
+ /* multiply each word by -1 */
+ assign( vT, binop( Iop_64HLtoV128,
+ binop( Iop_Mul64,
+ unop( Iop_V128HIto64,
+ mkexpr( vB ) ),
+ mkU64( 0xFFFFFFFFFFFFFFFF ) ),
+ binop( Iop_Mul64,
+ unop( Iop_V128to64,
+ mkexpr( vB ) ),
+ mkU64( 0xFFFFFFFFFFFFFFFF ) ) ) );
+ break;
+
+ case 8: // vprtybw, Vector Parity Byte Word
+ case 9: // vprtybd, Vector Parity Byte Doubleword
+ case 10: // vprtybq, Vector Parity Byte Quadword
+ {
+ UInt i;
+ IRTemp bit_in_byte[16];
+ IRTemp word_parity[4];
+
+ for( i = 0; i < 16; i++ ) {
+ bit_in_byte[i] = newTemp( Ity_I32 );
+ assign( bit_in_byte[i],
+ binop( Iop_And32,
+ unop( Iop_V128to32,
+ binop( Iop_ShrV128,
+ mkexpr( vB ),
+ mkU8( ( 15 - i ) * 8 ) ) ),
+ mkU32( 0x1 ) ) );
+ }
+
+ for( i = 0; i < 4; i++ ) {
+ word_parity[i] = newTemp(Ity_I32);
+ assign( word_parity[i],
+ mkXOr4_32( bit_in_byte[0 + i * 4],
+ bit_in_byte[1 + i * 4],
+ bit_in_byte[2 + i * 4],
+ bit_in_byte[3 + i * 4] ) );
+ }
+
+ if ( rA_addr == 8 ) {
+ DIP("vprtybw v%d,v%d", rT_addr, vB_addr);
+
+ assign( vT, mkV128from32( word_parity[0], word_parity[1],
+ word_parity[2], word_parity[3] ) );
+
+ } else if ( rA_addr == 9 ) {
+ DIP("vprtybd v%d,v%d", rT_addr, vB_addr);
+
+ assign( vT,
+ binop( Iop_64HLtoV128,
+ binop( Iop_32HLto64,
+ mkU32( 0 ),
+ binop( Iop_Xor32,
+ mkexpr( word_parity[0] ),
+ mkexpr( word_parity[1] ) ) ),
+ binop( Iop_32HLto64,
+ mkU32( 0 ),
+ binop( Iop_Xor32,
+ mkexpr( word_parity[2] ),
+ mkexpr( word_parity[3] ) ) ) ) );
+
+ } else if ( rA_addr == 10 ) {
+ DIP("vprtybq v%d,v%d", rT_addr, vB_addr);
+
+ assign( vT,
+ binop( Iop_64HLtoV128,
+ mkU64( 0 ),
+ unop( Iop_32Uto64,
+ mkXOr4_32( word_parity[0],
+ word_parity[1],
+ word_parity[2],
+ word_parity[3] ) ) ) );
+ }
+ }
+ break;
+
+ case 16: // vextsb2w, Vector Extend Sign Byte to Word
+ DIP("vextsb2w v%d,%d,v%d", rT_addr, rA_addr, vB_addr);
+
+ /* Iop_MullEven8Sx16 does a signed widening multiplication of byte to
+ * two byte sign extended result. Then do a two byte to four byte sign
+ * extended multiply. Note contents of upper three bytes in word are
+ * "over written". So just take source and multiply by 1.
+ */
+ assign( vT, binop( Iop_MullEven16Sx8,
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0000000100000001 ),
+ mkU64( 0x0000000100000001 ) ),
+ binop( Iop_MullEven8Sx16,
+ mkexpr( vB ),
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0001000100010001 ),
+ mkU64( 0x0001000100010001 ) ) ) ) );
+ break;
+
+ case 17: // vextsh2w, Vector Extend Sign Halfword to Word
+ DIP("vextsh2w v%d,%d,v%d", rT_addr, rA_addr, vB_addr);
+
+ /* Iop_MullEven16Sx8 does a signed widening multiply of four byte
+ * 8 bytes. Note contents of upper two bytes in word are
+ * "over written". So just take source and multiply by 1.
+ */
+ assign( vT, binop( Iop_MullEven16Sx8,
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0000000100000001 ),
+ mkU64( 0x0000000100000001 ) ),
+ mkexpr( vB ) ) );
+
+ break;
+
+ case 24: // vextsb2d, Vector Extend Sign Byte to Doubleword
+ DIP("vextsb2d v%d,%d,v%d", rT_addr, rA_addr, vB_addr);
+
+ /* Iop_MullEven8Sx16 does a signed widening multiplication of byte to
+ * two byte sign extended result. Then do a two byte to four byte sign
+ * extended multiply. Then do four byte to eight byte multiply.
+ */
+ assign( vT, binop( Iop_MullEven32Sx4,
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0000000000000001 ),
+ mkU64( 0x0000000000000001 ) ),
+ binop( Iop_MullEven16Sx8,
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0000000100000001 ),
+ mkU64( 0x0000000100000001 ) ),
+ binop( Iop_MullEven8Sx16,
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0001000100010001 ),
+ mkU64( 0x0001000100010001 ) ),
+ mkexpr( vB ) ) ) ) );
+ break;
+
+ case 25: // vextsh2d, Vector Extend Sign Halfword to Doubleword
+ DIP("vextsh2d v%d,%d,v%d", rT_addr, rA_addr, vB_addr);
+
+ assign( vT, binop( Iop_MullEven32Sx4,
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0000000000000001 ),
+ mkU64( 0x0000000000000001 ) ),
+ binop( Iop_MullEven16Sx8,
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0000000100000001 ),
+ mkU64( 0x0000000100000001 ) ),
+ mkexpr( vB ) ) ) );
+ break;
+
+ case 26: // vextsw2d, Vector Extend Sign Word to Doubleword
+ DIP("vextsw2d v%d,%d,v%d", rT_addr, rA_addr, vB_addr);
+
+ assign( vT, binop( Iop_MullEven32Sx4,
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0000000000000001 ),
+ mkU64( 0x0000000000000001 ) ),
+ mkexpr( vB ) ) );
+ break;
+
+ default:
+ vex_printf("dis_av_extend_sign(ppc)(Unsupported vector extend sign instruction)\n");
+ return False;
+ }
+
+ putVReg( rT_addr, mkexpr( vT) );
+ return True;
+}
+
+/*
+Vector Rotate Instructions
+*/
+static Bool dis_av_rotate ( UInt theInstr )
+{
+ /* VX-Form */
+
+ UChar opc1 = ifieldOPC( theInstr );
+ UChar vT_addr = ifieldRegDS( theInstr );
+ UChar vA_addr = ifieldRegA( theInstr );
+ UChar vB_addr = ifieldRegB( theInstr );
+ UInt opc2 = IFIELD( theInstr, 0, 11 );
+
+ IRTemp vA = newTemp( Ity_V128 );
+ IRTemp vB = newTemp( Ity_V128 );
+ IRTemp src3 = newTemp( Ity_V128 );
+ IRTemp vT = newTemp( Ity_V128 );
+ IRTemp field_mask = newTemp( Ity_V128 );
+ IRTemp mask128 = newTemp( Ity_V128 );
+ IRTemp vA_word[4];
+ IRTemp left_bits[4];
+ IRTemp right_bits[4];
+ IRTemp shift[4];
+ IRTemp mask[4];
+ IRTemp tmp128[4];
+ UInt i;
+ UInt num_words;
+ UInt word_size;
+ unsigned long word_mask;
+
+ if ( opc1 != 0x4 ) {
+ vex_printf("dis_av_rotate(ppc)(instr)\n");
+ return False;
+ }
+
+ assign( vA, getVReg( vA_addr ) );
+ assign( vB, getVReg( vB_addr ) );
+
+ switch (opc2) {
+ case 0x85: // vrlwmi, Vector Rotate Left Word then Mask Insert
+ case 0x185: // vrlwnm, Vector Rotate Left Word then AND with Mask
+ num_words = 4;
+ word_size = 32;
+ assign( field_mask, binop( Iop_64HLtoV128,
+ mkU64( 0 ),
+ mkU64( 0x1F ) ) );
+ word_mask = 0xFFFFFFFF;
+ break;
+
+ case 0x0C5: // vrldmi, Vector Rotate Left Doubleword then Mask Insert
+ case 0x1C5: // vrldnm, Vector Rotate Left Doubleword then AND with Mask
+ num_words = 2;
+ word_size = 64;
+ assign( field_mask, binop( Iop_64HLtoV128,
+ mkU64( 0 ),
+ mkU64( 0x3F ) ) );
+ word_mask = 0xFFFFFFFF;
+ break;
+ default:
+ vex_printf("dis_av_rotate(ppc)(opc2)\n");
+ return False;
+ }
+
+ for( i = 0; i < num_words; i++ ) {
+ left_bits[i] = newTemp( Ity_I8 );
+ right_bits[i] = newTemp( Ity_I8 );
+ shift[i] = newTemp( Ity_I8 );
+ mask[i] = newTemp( Ity_V128 );
+ tmp128[i] = newTemp( Ity_V128 );
+ vA_word[i] = newTemp( Ity_V128 );
+
+ assign( shift[i],
+ unop( Iop_64to8,
+ unop( Iop_V128to64,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ mkexpr( vB ),
+ mkU8( (num_words - 1 - i )
+ * word_size ) ),
+ mkexpr( field_mask ) ) ) ) );
+
+ /* left_bits = 63 - mb. Tells us how many bits to the left
+ * of mb to clear. Note for a word left_bits = 32+mb, for a double
+ * word left_bits = mb
+ */
+ assign( left_bits[i],
+ unop( Iop_64to8,
+ binop( Iop_Add64,
+ mkU64( 64 - word_size ),
+ unop( Iop_V128to64,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ mkexpr( vB ),
+ mkU8( ( num_words - 1 - i )
+ * word_size + 16 ) ),
+ mkexpr( field_mask ) ) ) ) ) );
+ /* right_bits = 63 - me. Tells us how many bits to the right
+ * of me to clear. Note for a word, left_bits = me+32, for a double
+ * word left_bits = me
+ */
+ assign( right_bits[i],
+ unop( Iop_64to8,
+ binop( Iop_Sub64,
+ mkU64( word_size - 1 ),
+ unop( Iop_V128to64,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ mkexpr( vB ),
+ mkU8( ( num_words - 1 - i )
+ * word_size + 8 ) ),
+ mkexpr( field_mask ) ) ) ) ) );
+
+ /* create mask for 32-bit word or 64-bit word */
+ assign( mask[i],
+ binop( Iop_64HLtoV128,
+ mkU64( 0 ),
+ binop( Iop_Shl64,
+ binop( Iop_Shr64,
+ binop( Iop_Shr64,
+ binop( Iop_Shl64,
+ mkU64( 0xFFFFFFFFFFFFFFFF ),
+ mkexpr( left_bits[i] ) ),
+ mkexpr( left_bits[i] ) ),
+ mkexpr( right_bits[i] ) ),
+ mkexpr( right_bits[i] ) ) ) );
+
+ /* Need to rotate vA using a left and right shift of vA OR'd together
+ * then ANDed with the mask.
+ */
+ assign( vA_word[i], binop( Iop_AndV128,
+ mkexpr( vA ),
+ binop( Iop_ShlV128,
+ binop( Iop_64HLtoV128,
+ mkU64( 0 ),
+ mkU64( word_mask ) ),
+ mkU8( ( num_words - 1 - i )
+ * word_size ) ) ) );
+ assign( tmp128[i],
+ binop( Iop_AndV128,
+ binop( Iop_ShlV128,
+ mkexpr( mask[i] ),
+ mkU8( ( num_words - 1 - i) * word_size ) ),
+ binop( Iop_OrV128,
+ binop( Iop_ShlV128,
+ mkexpr( vA_word[i] ),
+ mkexpr( shift[i] ) ),
+ binop( Iop_ShrV128,
+ mkexpr( vA_word[i] ),
+ unop( Iop_32to8,
+ binop(Iop_Sub32,
+ mkU32( word_size ),
+ unop( Iop_8Uto32,
+ mkexpr( shift[i] ) ) )
+ ) ) ) ) );
+ }
+
+ switch (opc2) {
+ case 0x85: // vrlwmi, Vector Rotate Left Word then Mask Insert
+ DIP("vrlwmi %d,%d,v%d", vT_addr, vA_addr, vB_addr);
+
+ assign( src3, getVReg( vT_addr ) );
+ assign( mask128, unop( Iop_NotV128,
+ mkOr4_V128_expr( binop( Iop_ShlV128,
+ mkexpr( mask[0] ),
+ mkU8( 96 ) ),
+ binop( Iop_ShlV128,
+ mkexpr( mask[1] ),
+ mkU8( 64 ) ),
+ binop( Iop_ShlV128,
+ mkexpr( mask[2] ),
+ mkU8( 32 ) ),
+ mkexpr( mask[3] ) ) ) );
+ assign( vT, binop( Iop_OrV128,
+ binop( Iop_AndV128,
+ mkexpr( src3 ),
+ mkexpr( mask128 ) ),
+ mkOr4_V128( tmp128[0], tmp128[1],
+ tmp128[2], tmp128[3] ) ) );
+ break;
+
+ case 0xC5: // vrldmi, Vector Rotate Left Double word then Mask Insert
+ DIP("vrldmi %d,%d,v%d", vT_addr, vA_addr, vB_addr);
+
+ assign( src3, getVReg( vT_addr ) );
+ assign( mask128, unop( Iop_NotV128,
+ binop( Iop_OrV128,
+ binop( Iop_ShlV128,
+ mkexpr( mask[0] ),
+ mkU8( 64 ) ),
+ mkexpr( mask[1] ) ) ) );
+
+ assign( vT, binop( Iop_OrV128,
+ binop( Iop_AndV128,
+ mkexpr( src3 ),
+ mkexpr( mask128 ) ),
+ binop( Iop_OrV128,
+ mkexpr( tmp128[0] ),
+ mkexpr( tmp128[1] ) ) ) );
+ break;
+
+ case 0x185: // vrlwnm, Vector Rotate Left Word then AND with Mask
+ DIP("vrlwnm %d,%d,v%d", vT_addr, vA_addr, vB_addr);
+ assign( vT, mkOr4_V128( tmp128[0], tmp128[1], tmp128[2], tmp128[3] ) );
+ break;
+
+ case 0x1C5: // vrldnm, Vector Rotate Left Doubleword then AND with Mask
+ DIP("vrldnm %d,%d,v%d", vT_addr, vA_addr, vB_addr);
+ assign( vT, binop( Iop_OrV128,
+ mkexpr( tmp128[0] ),
+ mkexpr( tmp128[1] ) ) );
+ break;
+ }
+
+ putVReg( vT_addr, mkexpr( vT ) );
+ return True;
+}
+
+/*
+ AltiVec Vector Extract Element Instructions
+*/
+static Bool dis_av_extract_element ( UInt theInstr )
+{
+ /* VX-Form,
+ * sorta destination and first source are GPR not vector registers
+ */
+
+ UChar opc1 = ifieldOPC( theInstr );
+ UChar rT_addr = ifieldRegDS( theInstr );
+ UChar rA_addr = ifieldRegA( theInstr );
+ UChar vB_addr = ifieldRegB( theInstr );
+ UInt opc2 = IFIELD( theInstr, 0, 11 );
+
+ IRTemp vB = newTemp( Ity_V128 );
+ IRTemp rA = newTemp( Ity_I64 );
+ IRTemp rT = newTemp( Ity_I64 );
+
+ assign( vB, getVReg( vB_addr ) );
+ assign( rA, getIReg( rA_addr ) );
+
+ if ( opc1 != 0x4 ) {
+ vex_printf("dis_av_extract_element(ppc)(instr)\n");
+ return False;
+ }
+
+ switch ( opc2 ) {
+ case 0x60D: // vextublx, vector extract unsigned Byte Left-indexed
+ DIP("vextublx %d,%d,v%d", rT_addr, rA_addr, vB_addr);
+
+ assign( rT, extract_field_from_vector( vB,
+ binop( Iop_Sub64,
+ mkU64( 15 ),
+ mkexpr( rA ) ),
+ 0xFF ) );
+
+ break;
+
+ case 0x64D: // vextuhlx, vector extract unsigned Halfword Left-indexed
+ DIP("vextuhlx %d,%d,v%d", rT_addr, rA_addr, vB_addr);
+
+ assign( rT, extract_field_from_vector( vB,
+ binop( Iop_Sub64,
+ mkU64( 14 ),
+ mkexpr( rA ) ),
+ 0xFFFF ) );
+ break;
+
+ case 0x68D: // vextuwlx, vector extract unsigned Word Left-indexed
+ DIP("vextuwlx %d,%d,v%d", rT_addr, rA_addr, vB_addr);
+
+ assign( rT, extract_field_from_vector( vB,
+ binop( Iop_Sub64,
+ mkU64( 12 ),
+ mkexpr( rA ) ),
+ 0xFFFFFFFF ) );
+ break;
+
+ case 0x70D: // vextubrx, vector extract unsigned Byte Right-indexed
+ DIP("vextubrx %d,%d,v%d", rT_addr, rA_addr, vB_addr);
+
+ assign( rT, extract_field_from_vector( vB, mkexpr( rA ), 0xFF ) );
+ break;
+
+ case 0x74D: // vextuhrx, vector extract unsigned Halfword Right-indexed
+ DIP("vextuhrx %d,%d,v%d", rT_addr, rA_addr, vB_addr);
+
+ assign( rT, extract_field_from_vector( vB, mkexpr( rA ), 0xFFFF ) );
+ break;
+
+ case 0x78D: // vextuwrx, vector extract unsigned Word Right-indexed
+ DIP("vextuwrx %d,%d,v%d", rT_addr, rA_addr, vB_addr);
+
+ assign( rT, extract_field_from_vector( vB, mkexpr( rA ), 0xFFFFFFFF ) );
+ break;
+
+ default:
+ vex_printf("dis_av_extract_element(ppc)(opc2)\n");
+ return False;
+ }
+ putIReg( rT_addr, mkexpr( rT ) );
+ return True;
+}
+
+/*
* VSX scalar and vector convert instructions
*/
static Bool
@@ -14362,6 +15000,116 @@
putVReg( vRT_addr, unop( Iop_PwBitMtxXpose64x2, mkexpr( vB ) ) );
break;
+ case 0x5CC: // vbpermd Vector Bit Permute Doubleword
+ {
+ UChar vRA_addr = ifieldRegA( theInstr );
+ IRTemp vA = newTemp( Ity_V128 );
+ UInt j;
+ IRTemp index_dword_hi[8]; // index in double word
+ IRTemp index_dword_lo[8];
+ IRTemp index_dword_hi_valid[8];
+ IRTemp index_dword_lo_valid[8];
+ IRTemp pb_dword_hi[8]; // permute bit
+ IRTemp pb_dword_lo[8];
+ IRTemp tmp_hi[9];
+ IRTemp tmp_lo[9];
+
+ DIP("vbpermd v%d,v%d,v%d\n", vRT_addr, vRA_addr, vRB_addr);
+
+ tmp_hi[0] = newTemp( Ity_I64 );
+ tmp_lo[0] = newTemp( Ity_I64 );
+
+ assign( vA, getVReg(vRA_addr) );
+ assign( tmp_hi[0], mkU64( 0 ) );
+ assign( tmp_lo[0], mkU64( 0 ) );
+
+ for (j=0; j<8; j++) {
+ index_dword_hi[j] = newTemp( Ity_I64 );
+ index_dword_lo[j] = newTemp( Ity_I64 );
+ index_dword_hi_valid[j] = newTemp( Ity_I64 );
+ index_dword_lo_valid[j] = newTemp( Ity_I64 );
+ pb_dword_hi[j] = newTemp( Ity_I64 );
+ pb_dword_lo[j] = newTemp( Ity_I64 );
+ tmp_hi[j+1] = newTemp( Ity_I64 );
+ tmp_lo[j+1] = newTemp( Ity_I64 );
+
+ assign( index_dword_hi[j],
+ binop( Iop_And64,
+ binop( Iop_Shr64,
+ unop( Iop_V128HIto64,
+ mkexpr( vB ) ),
+ mkU8( ( 7 - j ) * 8 ) ),
+ mkU64( 0xFF ) ) );
+
+ assign( index_dword_lo[j],
+ binop( Iop_And64,
+ binop( Iop_Shr64,
+ unop( Iop_V128to64,
+ mkexpr( vB ) ),
+ mkU8( ( 7 - j ) * 8 ) ),
+ mkU64( 0xFF ) ) );
+
+ assign( index_dword_hi_valid[j],
+ unop( Iop_1Sto64,
+ binop( Iop_CmpLT64U,
+ mkexpr( index_dword_hi[j] ),
+ mkU64( 64 ) ) ) );
+
+ assign( index_dword_lo_valid[j],
+ unop( Iop_1Sto64,
+ binop( Iop_CmpLT64U,
+ mkexpr( index_dword_lo[j] ),
+ mkU64( 64 ) ) ) );
+ assign( pb_dword_hi[j],
+ binop( Iop_And64,
+ binop( Iop_Shr64,
+ unop( Iop_V128HIto64,
+ mkexpr( vA ) ),
+ unop( Iop_64to8,
+ binop( Iop_Sub64,
+ mkU64( 63 ),
+ mkexpr( index_dword_hi[j] )
+ ) ) ),
+ mkU64( 0x1 ) ) );
+
+ assign( pb_dword_lo[j],
+ binop( Iop_And64,
+ binop( Iop_Shr64,
+ unop( Iop_V128to64,
+ mkexpr( vA ) ),
+ unop( Iop_64to8,
+ binop( Iop_Sub64,
+ mkU64( 63 ),
+ mkexpr( index_dword_lo[j] )
+ ) ) ),
+ mkU64( 0x1 ) ) );
+
+ assign( tmp_hi[j+1],
+ binop( Iop_Or64,
+ binop( Iop_And64,
+ mkexpr( index_dword_hi_valid[j] ),
+ binop( Iop_Shl64,
+ mkexpr( pb_dword_hi[j] ),
+ mkU8( 7 - j ) ) ),
+ mkexpr( tmp_hi[j] ) ) );
+
+ assign( tmp_lo[j+1],
+ binop( Iop_Or64,
+ binop( Iop_And64,
+ mkexpr( index_dword_lo_valid[j] ),
+ binop( Iop_Shl64,
+ mkexpr( pb_dword_lo[j] ),
+ mkU8( 7 - j ) ) ),
+ mkexpr( tmp_lo[j] ) ) );
+ }
+
+ putVReg( vRT_addr,
+ binop( Iop_64HLtoV128,
+ mkexpr( tmp_hi[8] ),
+ mkexpr( tmp_lo[8] ) ) );
+ }
+ break;
+
default:
vex_printf("dis_av_count_bitTranspose(ppc)(opc2)\n");
return False;
@@ -16352,6 +17100,140 @@
break;
}
+ case 0x10D: // lxvl
+ {
+ DIP("lxvl %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+
+ IRTemp byte[16];
+ UInt i;
+ UInt ea_off = 0;
+ IRExpr* irx_addr;
+ IRTemp tmp_low[9];
+ IRTemp tmp_hi[9];
+ IRTemp shift = newTemp( Ity_I8 );
+ IRTemp nb_gt16 = newTemp( Ity_I8 );
+ IRTemp ld_result = newTemp( Ity_V128 );
+ IRTemp nb_not_zero = newTemp( Ity_I64 );
+
+ IRTemp base_addr = newTemp( ty );
+
+ tmp_low[0] = newTemp( Ity_I64 );
+ tmp_hi[0] = newTemp( Ity_I64 );
+
+ assign( base_addr, ea_rAor0( rA_addr ) );
+ assign( tmp_low[0], mkU64( 0 ) );
+ assign( tmp_hi[0], mkU64( 0 ) );
+
+ /* shift is 15 - nb, where nb = rB[0:7], used to zero out upper bytes */
+ assign( nb_not_zero, unop( Iop_1Sto64,
+ binop( Iop_CmpNE64,
+ mkU64( 0 ),
+ binop( Iop_Shr64,
+ getIReg( rB_addr ),
+ mkU8( 56 ) ) ) ) );
+
+ assign( nb_gt16, unop( Iop_1Sto8,
+ binop( Iop_CmpLT64U,
+ binop( Iop_Shr64,
+ getIReg( rB_addr ),
+ mkU8( 60 ) ),
+ mkU64( 1 ) ) ) );
+
+ /* Set the shift to 0, by ANDing with nb_gt16. nb_gt16 will be all
+ * zeros if nb > 16. This will result in quad word load being stored.
+ */
+ assign( shift,
+ binop( Iop_And8,
+ unop( Iop_64to8,
+ binop( Iop_Mul64,
+ binop( Iop_Sub64,
+ mkU64 ( 16 ),
+ binop( Iop_Shr64,
+ getIReg( rB_addr ),
+ mkU8( 56 ) ) ),
+ mkU64( 8 ) ) ),
+ mkexpr( nb_gt16 ) ) );
+
+
+ /* fetch all 16 bytes, we will remove what we don't want later */
+ for ( i = 0; i < 8; i++ ) {
+ byte[i] = newTemp( Ity_I64 );
+ tmp_low[i+1] = newTemp( Ity_I64 );
+
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 1;
+
+ if ( host_endness == VexEndnessBE )
+ assign( byte[i], binop( Iop_Shl64,
+ unop( Iop_8Uto64,
+ load( Ity_I8, irx_addr ) ),
+ mkU8( 8 * ( 7 - i ) ) ) );
+
+ else
+ /* Reverse byte order */
+ assign( byte[i], binop( Iop_Shl64,
+ unop( Iop_8Uto64,
+ load( Ity_I8, irx_addr ) ),
+ mkU8( 8 * i ) ) );
+
+ assign( tmp_low[i+1],
+ binop( Iop_Or64,
+ mkexpr( byte[i] ), mkexpr( tmp_low[i] ) ) );
+ }
+
+ for ( i = 0; i < 8; i++ ) {
+ byte[i + 8] = newTemp( Ity_I64 );
+ tmp_hi[i+1] = newTemp( Ity_I64 );
+
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+ ea_off += 1;
+
+ if ( host_endness == VexEndnessBE )
+ assign( byte[i+8], binop( Iop_Shl64,
+ unop( Iop_8Uto64,
+ load( Ity_I8, irx_addr ) ),
+ mkU8( 8 * ( 7 - i ) ) ) );
+
+ else
+ /* Reverse byte order */
+ assign( byte[i+8], binop( Iop_Shl64,
+ unop( Iop_8Uto64,
+ load( Ity_I8, irx_addr ) ),
+ mkU8( 8 * i ) ) );
+
+ assign( tmp_hi[i+1], binop( Iop_Or64,
+ mkexpr( byte[i+8] ),
+ mkexpr( tmp_hi[i] ) ) );
+ }
+
+ if ( host_endness == VexEndnessBE )
+ assign( ld_result, binop( Iop_ShrV128,
+ binop( Iop_64HLtoV128,
+ mkexpr( tmp_hi[8] ),
+ mkexpr( tmp_low[8] ) ),
+ mkexpr( shift ) ) );
+ else
+ assign( ld_result, binop( Iop_ShrV128,
+ binop( Iop_ShlV128,
+ binop( Iop_64HLtoV128,
+ mkexpr( tmp_hi[8] ),
+ mkexpr( tmp_low[8] ) ),
+ mkexpr( shift ) ),
+ mkexpr( shift ) ) );
+
+ /* If nb = 0, make out the calculated load result so the stored
+ * value is zero.
+ */
+ putVSReg( XT, binop( Iop_AndV128,
+ mkexpr( ld_result ),
+ binop( Iop_64HLtoV128,
+ mkexpr( nb_not_zero ),
+ mkexpr( nb_not_zero ) ) ) );
+ break;
+ }
+
case 0x16C: // lxvwsx
{
IRTemp data = newTemp( Ity_I64 );
@@ -16408,6 +17290,36 @@
putVSReg( XT, binop( Iop_64HLtoV128, exp, exp ) );
break;
}
+
+ case 0x30D: // lxsibzx
+ {
+ IRExpr *byte;
+
+ DIP("lxsibzx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+
+ byte = load( Ity_I64, mkexpr( EA ) );
+ putVSReg( XT, binop( Iop_64HLtoV128,
+ binop( Iop_And64,
+ byte,
+ mkU64( 0xFF ) ),
+ mkU64( 0 ) ) );
+ break;
+ }
+
+ case 0x32D: // lxsihzx
+ {
+ IRExpr *byte;
+
+ DIP("lxsihzx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+
+ byte = load( Ity_I64, mkexpr( EA ) );
+ putVSReg( XT, binop( Iop_64HLtoV128,
+ binop( Iop_And64,
+ byte,
+ mkU64( 0xFFFF ) ),
+ mkU64( 0 ) ) );
+ break;
+ }
case 0x34C: // lxvd2x
{
IROp addOp = ty == Ity_I64 ? Iop_Add64 : Iop_Add32;
@@ -16769,6 +17681,181 @@
break;
}
+ case 0x18D: // stxvl Store VSX Vector Indexed
+ {
+ UInt ea_off = 0;
+ IRExpr* irx_addr;
+ IRTemp word0 = newTemp( Ity_I64 );
+ IRTemp word1 = newTemp( Ity_I64 );
+ IRTemp word2 = newTemp( Ity_I64 );
+ IRTemp word3 = newTemp( Ity_I64 );
+ IRTemp shift = newTemp( Ity_I8 );
+ IRTemp nb_gt16 = newTemp( Ity_I8 );
+ IRTemp nb_zero = newTemp( Ity_V128 );
+ IRTemp nb = newTemp( Ity_I8 );
+ IRTemp nb_field = newTemp( Ity_I64 );
+ IRTemp n_bytes = newTemp( Ity_I8 );
+ IRTemp base_addr = newTemp( ty );
+ IRTemp current_mem = newTemp( Ity_V128 );
+ IRTemp store_val = newTemp( Ity_V128 );
+ IRTemp nb_mask = newTemp( Ity_V128 );
+
+ DIP("stxvl %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr);
+
+ assign( nb_field, binop( Iop_Shr64,
+ getIReg(rB_addr),
+ mkU8( 56 ) ) );
+
+ assign( nb, unop( Iop_64to8, mkexpr( nb_field ) ) );
+
+ /* nb_gt16 will be all zeros if nb > 16 */
+ assign( nb_gt16, unop( Iop_1Sto8,
+ binop( Iop_CmpLT64U,
+ binop( Iop_Shr64,
+ mkexpr( nb_field ),
+ mkU8( 4 ) ),
+ mkU64( 1 ) ) ) );
+
+ /* nb_zero is 0xFF..FF if the nb_field = 0 */
+ assign( nb_zero, binop( Iop_64HLtoV128,
+ unop( Iop_1Sto64,
+ binop( Iop_CmpEQ64,
+ mkexpr( nb_field ),
+ mkU64( 0 ) ) ),
+ unop( Iop_1Sto64,
+ binop( Iop_CmpEQ64,
+ mkexpr( nb_field ),
+ mkU64( 0 ) ) ) ) );
+
+ /* set n_bytes to 0 if nb >= 16. Otherwise, set to nb. */
+ assign( n_bytes, binop( Iop_And8, mkexpr( nb ), mkexpr( nb_gt16 ) ) );
+ assign( shift, unop( Iop_64to8,
+ binop( Iop_Mul64,
+ binop( Iop_Sub64,
+ mkU64( 16 ),
+ unop( Iop_8Uto64,
+ mkexpr( n_bytes ) ) ),
+ mkU64( 8 ) ) ) );
+
+ /* We only have a 32-bit store function. So, need to fetch the
+ * contents of memory merge with the store value and do two
+ * 32-byte stores so we preserve the contents of memory not
+ * addressed by nb.
+ */
+ assign( base_addr, ea_rAor0( rA_addr ) );
+
+ assign( current_mem,
+ binop( Iop_64HLtoV128,
+ load( Ity_I64, mkexpr( base_addr ) ),
+ load( Ity_I64,
+ binop( mkSzOp( ty, Iop_Add8 ),
+ mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( 8 ) : mkU32( 8 )
+ ) ) ) );
+
+ /* Set the nb_mask to all zeros if nb = 0 so the current contents
+ * of memory get written back without modifications.
+ *
+ * The store_val is a combination of the current memory value
+ * and the bytes you want to store. The nb_mask selects the
+ * bytes you want stored from Vs.
+ */
+ if (host_endness == VexEndnessBE) {
+ assign( nb_mask,
+ binop( Iop_OrV128,
+ binop( Iop_AndV128,
+ binop( Iop_ShlV128,
+ mkV128( 0xFFFF ),
+ mkexpr( shift ) ),
+ unop( Iop_NotV128, mkexpr( nb_zero ) ) ),
+ binop( Iop_AndV128,
+ mkexpr( nb_zero ),
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( 0x0 ) ) ) ) );
+ assign( store_val,
+ binop( Iop_OrV128,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ mkexpr( vS ),
+ mkexpr( shift ) ),
+ mkexpr( nb_mask ) ),
+ binop( Iop_AndV128,
+ unop( Iop_Not64, mkexpr( nb_mask ) ),
+ mkexpr( current_mem) ) ) );
+
+ } else {
+ assign( nb_mask,
+ binop( Iop_OrV128,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ binop( Iop_ShlV128,
+ mkV128( 0xFFFF ),
+ mkexpr( shift ) ),
+ mkexpr( shift ) ),
+ unop( Iop_NotV128, mkexpr( nb_zero ) ) ),
+ binop( Iop_AndV128,
+ mkexpr( nb_zero ),
+ binop( Iop_64HLtoV128,
+ mkU64( 0x0 ),
+ mkU64( 0x0 ) ) ) ) );
+
+ assign( store_val,
+ binop( Iop_OrV128,
+ binop( Iop_AndV128,
+ binop( Iop_ShrV128,
+ binop( Iop_ShlV128,
+ mkexpr( vS ),
+ mkexpr( shift ) ),
+ mkexpr( shift ) ),
+ mkexpr( nb_mask ) ),
+ binop( Iop_AndV128,
+ unop( Iop_NotV128, mkexpr( nb_mask ) ),
+ mkexpr( current_mem) ) ) );
+ }
+
+ /* Store the value in 32-byte chunks */
+ assign( word0, binop( Iop_Shr64,
+ unop( Iop_V128HIto64, mkexpr( store_val ) ),
+ mkU8( 32 ) ) );
+
+ assign( word1, binop( Iop_And64,
+ unop( Iop_V128HIto64, mkexpr( store_val ) ),
+ mkU64( 0xFFFFFFFF ) ) );
+
+ assign( word2, binop( Iop_Shr64,
+ unop( Iop_V128to64, mkexpr( store_val ) ),
+ mkU8( 32 ) ) );
+
+ assign( word3, binop( Iop_And64,
+ unop( Iop_V128to64, mkexpr( store_val ) ),
+ mkU64( 0xFFFFFFFF ) ) );
+
+ ea_off = 0;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32, mkexpr( word3 ) ) );
+
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32, mkexpr( word2 ) ) );
+
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32, mkexpr( word1 ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( base_addr ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+
+ store( irx_addr, unop( Iop_64to32, mkexpr( word0 ) ) );
+ break;
+ }
+
case 0x28C:
{
IRTemp high64 = newTemp(Ity_F64);
@@ -16790,6 +17877,55 @@
store( mkexpr( EA ), high64 );
break;
}
+
+ case 0x38D: // stxsibx
+ {
+ IRExpr *stored_word;
+ IRTemp byte_to_store = newTemp( Ity_I64 );
+
+ DIP("stxsibx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr);
+
+ /* Can't store just a byte, need to fetch the word at EA merge data
+ * and store.
+ */
+ stored_word = load( Ity_I64, mkexpr( EA ) );
+ assign( byte_to_store, binop( Iop_And64,
+ unop( Iop_V128HIto64,
+ mkexpr( vS ) ),
+ mkU64( 0xFF ) ) );
+
+ store( mkexpr( EA ), binop( Iop_Or64,
+ binop( Iop_And64,
+ stored_word,
+ mkU64( 0xFFFFFFFFFFFFFF00 ) ),
+ mkexpr( byte_to_store ) ) );
+ break;
+ }
+
+ case 0x3AD: // stxsihx
+ {
+ IRExpr *stored_word;
+ IRTemp byte_to_store = newTemp( Ity_I64 );
+
+ DIP("stxsihx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr);
+
+ /* Can't store just a halfword, need to fetch the word at EA merge data
+ * and store.
+ */
+ stored_word = load( Ity_I64, mkexpr( EA ) );
+ assign( byte_to_store, binop( Iop_And64,
+ unop( Iop_V128HIto64,
+ mkexpr( vS ) ),
+ mkU64( 0xFFFF ) ) );
+
+ store( mkexpr( EA ), binop( Iop_Or64,
+ binop( Iop_And64,
+ stored_word,
+ mkU64( 0xFFFFFFFFFFFF0000 ) ),
+ mkexpr( byte_to_store ) ) );
+ break;
+ }
+
case 0x3CC:
{
IRExpr * high64, *low64;
@@ -18120,18 +19256,110 @@
assign( vD, binop(Iop_CmpEQ8x16, mkexpr(vA), mkexpr(vB)) );
break;
+ case 0x007: // vcmpneb (Compare Not Equal byte)
+ DIP("vcmpneb%s v%d,v%d,v%d\n", (flag_rC ? ".":""),
+ vD_addr, vA_addr, vB_addr);
+ assign( vD, unop( Iop_NotV128,
+ binop( Iop_CmpEQ8x16, mkexpr( vA ), mkexpr( vB ) ) ) );
+ break;
+
case 0x046: // vcmpequh (Compare Equal-to Unsigned HW, AV p161)
DIP("vcmpequh%s v%d,v%d,v%d\n", (flag_rC ? ".":""),
vD_addr, vA_addr, vB_addr);
assign( vD, binop(Iop_CmpEQ16x8, mkexpr(vA), mkexpr(vB)) );
break;
+ case 0x047: // vcmpneh (Compare Not Equal-to Halfword)
+ DIP("vcmpneh%s v%d,v%d,v%d\n", (flag_rC ? ".":""),
+ vD_addr, vA_addr, vB_addr);
+ assign( vD, unop( Iop_NotV128,
+ binop( Iop_CmpEQ16x8, mkexpr( vA ), mkexpr( vB ) ) ) );
+ break;
+
case 0x086: // vcmpequw (Compare Equal-to Unsigned W, AV p162)
DIP("vcmpequw%s v%d,v%d,v%d\n", (flag_rC ? ".":""),
vD_addr, vA_addr, vB_addr);
assign( vD, binop(Iop_CmpEQ32x4, mkexpr(vA), mkexpr(vB)) );
break;
+ case 0x087: // vcmpnew (Compare Not Equal-to Word)
+ DIP("vcmpnew%s v%d,v%d,v%d\n", (flag_rC ? ".":""),
+ vD_addr, vA_addr, vB_addr);
+ assign( vD, unop( Iop_NotV128,
+ binop( Iop_CmpEQ32x4, mkexpr( vA ), mkexpr( vB ) ) ) );
+ break;
+
+ case 0x107: // vcmpnezb (Compare Not Equal or Zero byte)
+ {
+ IRTemp vAeqvB = newTemp( Ity_V128 );
+ IRTemp vAeq0 = newTemp( Ity_V128 );
+ IRTemp vBeq0 = newTemp( Ity_V128 );
+ IRTemp zero = newTemp( Ity_V128 );
+
+ DIP("vcmpnezb%s v%d,v%d,v%d\n", (flag_rC ? ".":""),
+ vD_addr, vA_addr, vB_addr);
+
+ assign( zero, binop( Iop_64HLtoV128, mkU64( 0 ), mkU64( 0 ) ) );
+ assign( vAeq0, binop( Iop_CmpEQ8x16, mkexpr( vA ), mkexpr( zero ) ) );
+ assign( vBeq0, binop( Iop_CmpEQ8x16, mkexpr( vB ), mkexpr( zero ) ) );
+ assign( vAeqvB, unop( Iop_NotV128,
+ binop( Iop_CmpEQ8x16, mkexpr( vA ),
+ mkexpr( vB ) ) ) );
+
+ assign( vD, mkOr3_V128( vAeqvB, vAeq0, vBeq0 ) );
+ }
+ break;
+
+ case 0x147: // vcmpnezh (Compare Not Equal or Zero Halfword)
+ {
+ IRTemp vAeqvB = newTemp( Ity_V128 );
+ IRTemp vAeq0 = newTemp( Ity_V128 );
+ IRTemp vBeq0 = newTemp( Ity_V128 );
+ IRTemp zero = newTemp( Ity_V128 );
+
+ DIP("vcmpnezh%s v%d,v%d,v%d\n", (flag_rC ? ".":""),
+ vD_addr, vA_addr, vB_addr);
+
+ assign( zero, binop( Iop_64HLtoV128, mkU64( 0 ), mkU64( 0 ) ) );
+ assign( vAeq0, binop( Iop_CmpEQ16x8, mkexpr( vA ), mkexpr( zero ) ) );
+ assign( vBeq0, binop( Iop_CmpEQ16x8, mkexpr( vB ), mkexpr( zero ) ) );
+ assign( vAeqvB, unop( Iop_NotV128,
+ binop(Iop_CmpEQ16x8, mkexpr( vA ),
+ mkexpr( vB ) ) ) );
+
+ assign( vD, binop( Iop_OrV128,
+ binop( Iop_OrV128,
+ mkexpr( vAeq0 ),
+ mkexpr( vBeq0 ) ),
+ mkexpr( vAeqvB ) ) );
+ }
+ break;
+
+ case 0x187: // vcmpnezw (Compare Not Equal or Zero Word)
+ {
+ IRTemp vAeqvB = newTemp( Ity_V128 );
+ IRTemp vAeq0 = newTemp( Ity_V128 );
+ IRTemp vBeq0 = newTemp( Ity_V128 );
+ IRTemp zero = newTemp( Ity_V128 );
+
+ DIP("vcmpnezw%s v%d,v%d,v%d\n", (flag_rC ? ".":""),
+ vD_addr, vA_addr, vB_addr);
+
+ assign( zero, binop( Iop_64HLtoV128, mkU64( 0 ), mkU64( 0 ) ) );
+ assign( vAeq0, binop( Iop_CmpEQ32x4, mkexpr( vA ), mkexpr( zero ) ) );
+ assign( vBeq0, binop( Iop_CmpEQ32x4, mkexpr( vB ), mkexpr( zero ) ) );
+ assign( vAeqvB, unop( Iop_NotV128,
+ binop(Iop_CmpEQ32x4, mkexpr( vA ),
+ mkexpr( vB ) ) ) );
+
+ assign( vD, binop( Iop_OrV128,
+ binop( Iop_OrV128,
+ mkexpr( vAeq0 ),
+ mkexpr( vBeq0 ) ),
+ mkexpr( vAeqvB ) ) );
+ }
+ break;
+
case 0x0C7: // vcmpequd (Compare Equal-to Unsigned Doubleword)
DIP("vcmpequd%s v%d,v%d,v%d\n", (flag_rC ? ".":""),
vD_addr, vA_addr, vB_addr);
@@ -20865,6 +22093,7 @@
Bool allow_VX = False; // Equates to "supports Power ISA 2.06
Bool allow_DFP = False;
Bool allow_isa_2_07 = False;
+ Bool allow_isa_3_0 = False;
UInt hwcaps = archinfo->hwcaps;
Long delta;
@@ -20877,6 +22106,7 @@
allow_VX = (0 != (hwcaps & VEX_HWCAPS_PPC64_VX));
allow_DFP = (0 != (hwcaps & VEX_HWCAPS_PPC64_DFP));
allow_isa_2_07 = (0 != (hwcaps & VEX_HWCAPS_PPC64_ISA2_07));
+ allow_isa_3_0 = (0 != (hwcaps & VEX_HWCAPS_PPC64_ISA3_0));
} else {
allow_F = (0 != (hwcaps & VEX_HWCAPS_PPC32_F));
allow_V = (0 != (hwcaps & VEX_HWCAPS_PPC32_V));
@@ -20885,6 +22115,7 @@
allow_VX = (0 != (hwcaps & VEX_HWCAPS_PPC32_VX));
allow_DFP = (0 != (hwcaps & VEX_HWCAPS_PPC32_DFP));
allow_isa_2_07 = (0 != (hwcaps & VEX_HWCAPS_PPC32_ISA2_07));
+ allow_isa_3_0 = (0 != (hwcaps & VEX_HWCAPS_PPC32_ISA3_0));
}
/* The running delta */
@@ -21917,10 +23148,13 @@
case 0x00C: // lxsiwzx
case 0x04C: // lxsiwax
case 0x10C: // lxvx
+ case 0x10D: // lxvl
case 0x16C: // lxvwsx
case 0x20C: // lxsspx
case 0x24C: // lxsdx
case 0x32C: // lxvh8x
+ case 0x30D: // lxsibzx
+ case 0x32D: // lxsihzx
case 0x34C: // lxvd2x
case 0x36C: // lxvb16x
case 0x14C: // lxvdsx
@@ -21935,10 +23169,13 @@
/* VSX Store */
case 0x08C: // stxsiwx
case 0x18C: // stxvx
+ case 0x18D: // stxvl
case 0x28C: // stxsspx
case 0x2CC: // stxsdx
- case 0x3CC: // stxvd2x
case 0x38C: // stxvw4x
+ case 0x3CC: // stxvd2x
+ case 0x38D: // stxsibx
+ case 0x3AD: // stxsihx
case 0x3AC: // stxvh8x
case 0x3EC: // stxvb16x
// All of these VSX store instructions use some VMX facilities, so
@@ -22137,12 +23374,27 @@
if (dis_av_logic( theInstr )) goto decode_success;
goto decode_failure;
+ /* AV Rotate */
+ case 0x085: case 0x185: // vrlwmi, vrlwnm
+ case 0x0C5: case 0x1C5: // vrldmi, vrldnm
+ if (!allow_V) goto decode_noV;
+ if (dis_av_rotate( theInstr )) goto decode_success;
+ goto decode_failure;
+
/* AV Processor Control */
case 0x604: case 0x644: // mfvscr, mtvscr
if (!allow_V) goto decode_noV;
if (dis_av_procctl( theInstr )) goto decode_success;
goto decode_failure;
+ /* AV Vector Extract Element instructions */
+ case 0x60D: case 0x64D: case 0x68D: // vextublx, vextuhlx, vextuwlx
+ case 0x70D: case 0x74D: case 0x78D: // vextubrx, vextuhrx, vextuwrx
+ if (!allow_V) goto decode_noV;
+ if (dis_av_extract_element( theInstr )) goto decode_success;
+ goto decode_failure;
+
+
/* AV Floating Point Arithmetic */
case 0x00A: case 0x04A: // vaddfp, vsubfp
case 0x10A: case 0x14A: case 0x18A: // vrefp, vrsqrtefp, vexptefp
@@ -22209,6 +23461,20 @@
if (dis_av_cipher( theInstr )) goto decode_success;
goto decode_failure;
+ /* AV Vector Extend Sign Instructions and
+ * Vector Count Leading/Trailing zero Least-Significant bits Byte.
+ * Vector Integer Negate Instructions
+ */
+ case 0x602: // vextsb2w, vextsh2w, vextsb2d, vextsh2d, vextsw2d
+ // vclzlsbb and vctzlsbb
+ // vnegw, vnegd
+ // vprtybw, vprtybd, vprtybq
+ // vctzb, vctzh, vctzw, vctzd
+ if (!allow_V) goto decode_noV;
+ if (dis_av_extend_sign_count_zero( theInstr, allow_isa_3_0 ))
+ goto decode_success;
+ goto decode_failure;
+
case 0x6C2: case 0x682: // vshasigmaw, vshasigmad
if (!allow_isa_2_07) goto decode_noP8;
if (dis_av_hash( theInstr )) goto decode_success;
@@ -22227,6 +23493,7 @@
goto decode_failure;
case 0x50c: // vgbbd
+ case 0x5cc: // vbpermd
if (!allow_isa_2_07) goto decode_noP8;
if (dis_av_count_bitTranspose( theInstr, opc2 )) goto decode_success;
goto decode_failure;
@@ -22246,7 +23513,9 @@
switch (opc2) {
/* AV Compare */
- case 0x006: case 0x046: case 0x086: // vcmpequb, vcmpequh, vcmpequw
+ case 0x006: case 0x007: case 0x107: // vcmpequb, vcmpneb, vcmpnezb
+ case 0x046: case 0x047: case 0x147: // vcmpequh, vcmpneh, vcmpnezh
+ case 0x086: case 0x087: case 0x187: // vcmpequw, vcmpnew, vcmpnezw
case 0x206: case 0x246: case 0x286: // vcmpgtub, vcmpgtuh, vcmpgtuw
case 0x306: case 0x346: case 0x386: // vcmpgtsb, vcmpgtsh, vcmpgtsw
if (!allow_V) goto decode_noV;
|