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From: Philippe W. <phi...@sk...> - 2016-02-22 22:38:23
|
On Mon, 2016-02-22 at 14:52 +0530, Anuta Mukherjee wrote:
Hello Anuta,
> When I try to run it, this is the error I'm getting:
>
>
> valgrind: m_redir.c:627 (vgPlain_redir_notify_new_DebugInfo): Assertion 'is_plausible_guest_addr(sym_avmas.main)' failed.
> Segmentation fault (core dumped)
>
One possible reason for the above is if the wrapping code is linked to
the tool,
rather than being in the tool preload file.
So, what you could do is (assuming you are on amd64, and that your
install is in the directory Inst):
nm Inst/lib/valgrind/vgpreload_helgrind-amd64-linux.so|grep -i pthreadZucreate
and the same command for your tool:
nm Inst/lib/valgrind/vgpreload_tracker-amd64-linux.so|grep -i pthreadZucreate
Both commands should output a line such as:
000000000000c0bc T _vgw00000ZZ_libpthreadZdsoZd0_pthreadZucreateZAZa
If the above is ok, then run with -v -v -v -d -d -d
The tracing should show something like:
--2338:2: initimg preload_string:
following by a line containing a.o. the aboslute path name of the
tracker preload .so.
If all the above is correct, then I have no idea.
Maybe compare a run of your tool and helgrind
with the options
-v -v -v -d -d -d --trace-redir=yes
The traces/differences might explain the problem.
Philippe
|
|
From: <sv...@va...> - 2016-02-22 16:29:50
|
Author: petarj
Date: Mon Feb 22 16:29:40 2016
New Revision: 15801
Log:
mips32: add tests for mfhc1 and mthc1 instructions
Add tests for mfhc1 and mthc1 instructions and (two) new exp files.
Also, minor formatting changes throughout the test file.
This is related to VEX change r3211.
Added:
trunk/none/tests/mips32/MoveIns.stdout.exp-mips32r2-BE
trunk/none/tests/mips32/MoveIns.stdout.exp-mips32r2-LE
Modified:
trunk/none/tests/mips32/MoveIns.c
Modified: trunk/none/tests/mips32/MoveIns.c
==============================================================================
--- trunk/none/tests/mips32/MoveIns.c (original)
+++ trunk/none/tests/mips32/MoveIns.c Mon Feb 22 16:29:40 2016
@@ -1,3 +1,4 @@
+#include <stdint.h>
#include <stdio.h>
const float fs_f[] = {
@@ -9,6 +10,17 @@
-347856.475, 356047.56, -1.0, 23.04
};
+unsigned long long data[] = {
+ 0x1234567887654321ull, 0x66785bd668466667ull,
+ 0xBFF550ff07788000ull, 0x0004789236500000ull,
+ 0x3FF0001256789600ull, 0x0012365478000000ull,
+ 0x252a2e2b252a2e2bull, 0x26852147962d2d2aull,
+ 0x1234567887654321ull, 0x66785bd668466667ull,
+ 0x789651ff07788055ull, 0x00ff23f4f1f5f6f8ull,
+ 0x3FF0001256789600ull, 0xaabbcdfeefcd1256ull,
+ 0xa1b2b2a1a3a5a6aaull, 0x2569874123654786ull
+};
+
unsigned int mem[] = {
0x4095A266, 0x66666666,
0xBFF00000, 0x00000000,
@@ -22,259 +34,236 @@
};
// mfc1 rt, fs
-#define TESTINSNMOVE(instruction, offset, FS, RT) \
-{ \
- float out; \
- int out1; \
- __asm__ volatile( \
- "move $t0, %2\n\t" \
- "lwc1 $" #FS ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.s %0, $" #FS"\n\t" \
- "move %1, $" #RT "\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (mem) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: fs %f, rt 0x%x\n", \
- instruction, out, out1); \
+#define TESTINSNMOVE(instruction, offset, FS, RT) \
+{ \
+ float out; \
+ int out1; \
+ __asm__ volatile( \
+ ".set push \n\t" \
+ ".set oddspreg \n\t" \
+ "move $t0, %2\n\t" \
+ "lwc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FS"\n\t" \
+ "move %1, $" #RT "\n\t" \
+ ".set pop \n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (mem) \
+ : #RT, "memory" \
+ ); \
+ printf("%s :: fs %f, rt 0x%x\n", \
+ instruction, out, out1); \
}
// mfhc1 rt, fs
-#define TESTINSNMOVEd(instruction, offset, FS, RT) \
-{ \
- double out; \
- int out1; \
- __asm__ volatile( \
- "move $t0, %2\n\t" \
- "ldc1 $" #FS ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #FS"\n\t" \
- "move %1, $" #RT "\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (mem) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: fs %lf, rt 0x%x\n", \
- instruction, out, out1); \
+#define TESTINSNMOVEd(instruction, offset, FS, RT) \
+{ \
+ unsigned int out; \
+ __asm__ volatile( \
+ "move $t0, %1\n\t" \
+ "ldc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "move %0, $" #RT "\n\t" \
+ :"=&r" (out) \
+ : "r" (data) \
+ : #RT, "memory" \
+ ); \
+ printf("%s :: rt 0x%x\n", \
+ instruction, out); \
}
// mtc1 rt, fs
-#define TESTINSNMOVEt(instruction, offset, FS, RT) \
-{ \
- float out; \
- int out1; \
- __asm__ volatile( \
- "move $t0, %2\n\t" \
- "lw $" #RT ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.s %0, $" #FS"\n\t" \
- "move %1, $" #RT "\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (mem) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: fs %f, rt 0x%x\n", \
- instruction, out, out1); \
+#define TESTINSNMOVEt(instruction, offset, FS, RT) \
+{ \
+ float out; \
+ int out1; \
+ __asm__ volatile( \
+ ".set push \n\t" \
+ ".set oddspreg \n\t" \
+ "move $t0, %2\n\t" \
+ "lw $" #RT ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FS"\n\t" \
+ "move %1, $" #RT "\n\t" \
+ ".set pop \n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (mem) \
+ : #RT, "memory" \
+ ); \
+ printf("%s :: fs %f, rt 0x%x\n", \
+ instruction, out, out1); \
}
// mthc1 rt, fs
-#define TESTINSNMOVEtd(instruction, offset, FS, RT) \
-{ \
- double out; \
- int out1; \
- __asm__ volatile( \
- "move $t0, %2\n\t" \
- "lw $" #RT ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #FS"\n\t" \
- "move %1, $" #RT "\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (mem) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: fs %lf, rt 0x%x\n", \
- instruction, out, out1); \
+#define TESTINSNMOVEtd(instruction, offset, offset2, FS, RT) \
+{ \
+ unsigned long long out = 0; \
+ __asm__ volatile ( \
+ "move $t0, %2 \n\t" \
+ "move $t1, %1 \n\t" \
+ "ldc1 $"#FS"," #offset2"($t0)" "\n\t" \
+ "lw $"#RT"," #offset"($t1) \n\t" \
+ instruction "\n\t" \
+ "move $"#RT", %0 \n\t" \
+ "sdc1 $"#FS ", 0($"#RT")" "\n\t" \
+ : :"r" (&out), "r" (mem), "r" (data) \
+ : #RT, "memory" \
+ ); \
+ printf("%s :: out: %llx\n", instruction, out); \
}
// mov.s fd, fs
-#define TESTINSNMOVE1s(instruction, offset, FD, FS) \
-{ \
- float out; \
- int out1; \
- __asm__ volatile( \
- "move $t0, %2\n\t" \
- "lwc1 $" #FS ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.s %0, $" #FD"\n\t" \
- "mfc1 %1, $" #FD"\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (fs_f) \
- : "cc", "memory" \
- ); \
- printf("%s :: fs %f, rt 0x%x\n", \
- instruction, out, out1); \
+#define TESTINSNMOVE1s(instruction, offset, FD, FS) \
+{ \
+ float out; \
+ int out1; \
+ __asm__ volatile( \
+ ".set push \n\t" \
+ ".set oddspreg \n\t" \
+ "move $t0, %2\n\t" \
+ "lwc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FD"\n\t" \
+ "mfc1 %1, $" #FD"\n\t" \
+ ".set pop \n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (fs_f) \
+ : "memory" \
+ ); \
+ printf("%s :: fs %f, rt 0x%x\n", \
+ instruction, out, out1); \
}
// mov.d fd, fs
-#define TESTINSNMOVE1d(instruction, offset, FD, FS) \
-{ \
- double out; \
- int out1; \
- __asm__ volatile( \
- "move $t0, %2\n\t" \
- "ldc1 $" #FS ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #FD"\n\t" \
- "mfc1 %1, $" #FD"\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (fs_f) \
- : "cc", "memory" \
- ); \
- printf("%s ::fs %f, rt 0x%x\n", \
- instruction, out, out1); \
+#define TESTINSNMOVE1d(instruction, offset, FD, FS) \
+{ \
+ double out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $t0, %2\n\t" \
+ "ldc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #FD"\n\t" \
+ "mfc1 %1, $" #FD"\n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (fs_f) \
+ : "memory" \
+ ); \
+ printf("%s ::fs %f, rt 0x%x\n", \
+ instruction, out, out1); \
}
// movf rd, rs
-#define TESTINSNMOVE2(instruction, RDval, RSval, RD, RS, cc) \
-{ \
- int out; \
- __asm__ volatile( \
- "li $t0, 1\n\t" \
- "move $t1, %3\n\t" \
- "mtc1 $t0, $f0\n\t" \
- "mtc1 $t1, $f2\n\t" \
- "c.eq.s $f0, $f2\n\t" \
- "move $" #RS ", %1\n\t" \
- "move $" #RD ", %2\n\t" \
- instruction "\n\t" \
- "move %0, $" #RD "\n\t" \
- : "=&r" (out) \
- : "r" (RSval), "r" (RDval), "r" (cc) \
- : "t0", "t1", #RD, #RS, "cc", "memory" \
- ); \
- printf("%s :: out: 0x%x, RDval: 0x%x, RSval: 0x%x, cc: %d\n", \
- instruction, out, RDval, RSval, cc); \
+#define TESTINSNMOVE2(instruction, RDval, RSval, RD, RS, cc) \
+{ \
+ int out; \
+ __asm__ volatile( \
+ "li $t0, 1\n\t" \
+ "move $t1, %3\n\t" \
+ "mtc1 $t0, $f0\n\t" \
+ "mtc1 $t1, $f2\n\t" \
+ "c.eq.s $f0, $f2\n\t" \
+ "move $" #RS ", %1\n\t" \
+ "move $" #RD ", %2\n\t" \
+ instruction "\n\t" \
+ "move %0, $" #RD "\n\t" \
+ : "=&r" (out) \
+ : "r" (RSval), "r" (RDval), "r" (cc) \
+ : "t0", "t1", #RD, #RS, "memory" \
+ ); \
+ printf("%s :: out: 0x%x, RDval: 0x%x, RSval: 0x%x, cc: %d\n",\
+ instruction, out, RDval, RSval, cc); \
}
// movf.s fd, fs
-#define TESTINSNMOVE2s(instruction, FD, FS, cc, offset) \
-{ \
- float out; \
- __asm__ volatile( \
- "li $t0, 1\n\t" \
- "move $t1, %1\n\t" \
- "mtc1 $t0, $f0\n\t" \
- "mtc1 $t1, $f2\n\t" \
- "c.eq.s $f0, $f2\n\t" \
- "move $t0, %2\n\t" \
- "lwc1 $" #FD ", 4($t0)\n\t" \
- "lwc1 $" #FS ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.s %0, $" #FD"\n\t" \
- : "=&f" (out) \
- : "r" (cc), "r" (fs_f) \
- : "t0", "t1", "cc", "memory" \
- ); \
- printf("%s :: out: %f, cc: %d\n", \
- instruction, out, cc); \
+#define TESTINSNMOVE2s(instruction, FD, FS, cc, offset) \
+{ \
+ float out; \
+ __asm__ volatile( \
+ "li $t0, 1\n\t" \
+ "move $t1, %1\n\t" \
+ "mtc1 $t0, $f0\n\t" \
+ "mtc1 $t1, $f2\n\t" \
+ "c.eq.s $f0, $f2\n\t" \
+ "move $t0, %2\n\t" \
+ "lwc1 $" #FD ", 4($t0)\n\t" \
+ "lwc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FD"\n\t" \
+ : "=&f" (out) \
+ : "r" (cc), "r" (fs_f) \
+ : "t0", "t1", "memory" \
+ ); \
+ printf("%s :: out: %f, cc: %d\n", \
+ instruction, out, cc); \
}
// movf.d fd, fs
-#if (__mips_fpr==64)
-#define TESTINSNMOVE2d(instruction, FD, FS, cc, offset) \
-{ \
- double out; \
- int out1; \
- int out2; \
- __asm__ volatile( \
- "li $t0, 1\n\t" \
- "mtc1 $t0, $f0\n\t" \
- "mtc1 %3, $f2\n\t" \
- "move $t0, %4\n\t" \
- "ldc1 $f4, 8($t0)\n\t" \
- "c.eq.s $f0, $f2\n\t" \
- "ldc1 $" #FS ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #FD"\n\t" \
- "mfc1 %1, $f4\n\t" \
- "mfhc1 %2, $f4\n\t" \
- : "=&f" (out), "=&r" (out1), "=&r" (out2) \
- : "r" (cc), "r" (mem) \
- : "t0", "t1", "cc", "memory" \
- ); \
- printf("%s :: out: 0x%x 0x%x, cc: %d\n", \
- instruction, out1, out2, cc); \
-}
-#else
-#define TESTINSNMOVE2d(instruction, FD, FS, cc, offset) \
-{ \
- double out; \
- int out1; \
- int out2; \
- __asm__ volatile( \
- "li $t0, 1\n\t" \
- "move $t1, %3\n\t" \
- "mtc1 $t0, $f0\n\t" \
- "mtc1 $t1, $f2\n\t" \
- "move $t0, %4\n\t" \
- "ldc1 $f4, 8($t0)\n\t" \
- "c.eq.s $f0, $f2\n\t" \
- "ldc1 $" #FS ", "#offset"($t0)\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #FD"\n\t" \
- "mfc1 %1, $f4\n\t" \
- "mfc1 %2, $f5\n\t" \
- : "=&f" (out), "=&r" (out1), "=&r" (out2) \
- : "r" (cc), "r" (mem) \
- : "t0", "t1", "cc", "memory" \
- ); \
- printf("%s :: out: 0x%x 0x%x, cc: %d\n", \
- instruction, out1, out2, cc); \
+#define TESTINSNMOVE2d(instruction, FD, FS, cc, offset) \
+{ \
+ double out; \
+ uint64_t outl; \
+ __asm__ volatile( \
+ "li $t0, 1 \n\t" \
+ "move $t1, %1 \n\t" \
+ "mtc1 $t0, $f0 \n\t" \
+ "mtc1 $t1, $f2 \n\t" \
+ "move $t0, %2 \n\t" \
+ "ldc1 $f4, 8($t0) \n\t" \
+ "c.eq.s $f0, $f2\n\t" \
+ "ldc1 $" #FS ", "#offset"($t0)\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #FD"\n\t" \
+ "sdc1 $f4, 0(%3)" \
+ : "=f" (out) \
+ :"r" (cc), "r" (mem), "r" (&outl) \
+ : "t0", "t1", "memory" \
+ ); \
+ printf("%s :: out: 0x%x 0x%x, cc: %d\n", \
+ instruction, (uint32_t)outl, (uint32_t)(outl >> 32), cc); \
}
-#endif
// movn.s fd, fs, rt
-#define TESTINSNMOVEN1s(instruction, offset, RTval, FD, FS, RT) \
-{ \
- float out; \
- int out1; \
- __asm__ volatile( \
- "move $" #RT ", %3\n\t" \
- "move $t0, %2\n\t" \
- "lwc1 $" #FS ", "#offset"($t0)\n\t" \
- "mtc1 $0, $" #FD "\n\t" \
- instruction "\n\t" \
- "mov.s %0, $" #FD"\n\t" \
- "mfc1 %1, $" #FD"\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (fs_f), "r" (RTval) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: fs rt 0x%x\n", \
- instruction, out1); \
+#define TESTINSNMOVEN1s(instruction, offset, RTval, FD, FS, RT) \
+{ \
+ float out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $" #RT ", %3\n\t" \
+ "move $t0, %2\n\t" \
+ "lwc1 $" #FS ", "#offset"($t0)\n\t" \
+ "mtc1 $0, $" #FD "\n\t" \
+ instruction "\n\t" \
+ "mov.s %0, $" #FD"\n\t" \
+ "mfc1 %1, $" #FD"\n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (fs_f), "r" (RTval) \
+ : #RT, "memory" \
+ ); \
+ printf("%s :: fs rt 0x%x\n", \
+ instruction, out1); \
}
// movn.d fd, fs, rt
-#define TESTINSNMOVEN1d(instruction, offset, RTval, FD, FS, RT) \
-{ \
- double out; \
- int out1; \
- __asm__ volatile( \
- "move $" #RT ", %3\n\t" \
- "move $t0, %2\n\t" \
- "ldc1 $" #FS ", "#offset"($t0)\n\t" \
- "mtc1 $0, $" #FD "\n\t" \
- "mtc1 $0, $" #FD + 1"\n\t" \
- instruction "\n\t" \
- "mov.d %0, $" #FD"\n\t" \
- "mfc1 %1, $" #FD"\n\t" \
- : "=&f" (out), "=&r" (out1) \
- : "r" (fs_f), "r" (RTval) \
- : #RT, "cc", "memory" \
- ); \
- printf("%s :: fs %lf, rt 0x%x\n", \
- instruction, out, out1); \
+#define TESTINSNMOVEN1d(instruction, offset, RTval, FD, FS, RT) \
+{ \
+ double out; \
+ int out1; \
+ __asm__ volatile( \
+ "move $" #RT ", %3\n\t" \
+ "move $t0, %2\n\t" \
+ "ldc1 $" #FS ", "#offset"($t0)\n\t" \
+ "mtc1 $0, $" #FD "\n\t" \
+ "mtc1 $0, $" #FD + 1"\n\t" \
+ instruction "\n\t" \
+ "mov.d %0, $" #FD"\n\t" \
+ "mfc1 %1, $" #FD"\n\t" \
+ : "=&f" (out), "=&r" (out1) \
+ : "r" (fs_f), "r" (RTval) \
+ : #RT, "memory" \
+ ); \
+ printf("%s :: fs %lf, rt 0x%x\n", \
+ instruction, out, out1); \
}
int main()
@@ -337,6 +326,44 @@
TESTINSNMOVEt("mtc1 $t1, $f25", 34, f25, t1);
TESTINSNMOVEt("mtc1 $t2, $f26", 38, f26, t2);
+#if defined(__mips__) && ((defined(__mips_isa_rev) && __mips_isa_rev >= 2))
+ printf("MFHC1\n");
+ TESTINSNMOVEd("mfhc1 $t1, $f0", 0, f0, t1);
+ TESTINSNMOVEd("mfhc1 $t2, $f2", 8, f2, t2);
+ TESTINSNMOVEd("mfhc1 $t3, $f4", 16, f4, t3);
+ TESTINSNMOVEd("mfhc1 $v0, $f6", 24, f6, v0);
+ TESTINSNMOVEd("mfhc1 $v1, $f8", 32, f8, v1);
+ TESTINSNMOVEd("mfhc1 $a0, $f10", 40, f10, a0);
+ TESTINSNMOVEd("mfhc1 $a1, $f12", 48, f12, a1);
+ TESTINSNMOVEd("mfhc1 $a2, $f14", 56, f14, a2);
+ TESTINSNMOVEd("mfhc1 $a3, $f16", 64, f16, a3);
+ TESTINSNMOVEd("mfhc1 $s0, $f18", 72, f18, s0);
+ TESTINSNMOVEd("mfhc1 $s1, $f20", 80, f20, s1);
+ TESTINSNMOVEd("mfhc1 $s2, $f22", 88, f22, s2);
+ TESTINSNMOVEd("mfhc1 $s3, $f24", 96, f24, s3);
+ TESTINSNMOVEd("mfhc1 $s4, $f26", 104, f26, s4);
+ TESTINSNMOVEd("mfhc1 $s5, $f28", 112, f28, s5);
+ TESTINSNMOVEd("mfhc1 $s6, $f30", 120, f30, s6);
+
+ printf("MTHC1\n");
+ TESTINSNMOVEtd("mthc1 $t2, $f0", 0, 0, f0, t2);
+ TESTINSNMOVEtd("mthc1 $t3, $f2", 4, 8, f2, t3);
+ TESTINSNMOVEtd("mthc1 $v0, $f4", 8, 16, f4, v0);
+ TESTINSNMOVEtd("mthc1 $v1, $f6", 12, 24, f6, v1);
+ TESTINSNMOVEtd("mthc1 $a0, $f8", 16, 32, f8, a0);
+ TESTINSNMOVEtd("mthc1 $a1, $f10", 20, 40, f10, a1);
+ TESTINSNMOVEtd("mthc1 $a2, $f12", 24, 48, f12, a1);
+ TESTINSNMOVEtd("mthc1 $a3, $f14", 28, 56, f14, a3);
+ TESTINSNMOVEtd("mthc1 $s0, $f16", 32, 64, f16, s0);
+ TESTINSNMOVEtd("mthc1 $s1, $f18", 36, 72, f18, s1);
+ TESTINSNMOVEtd("mthc1 $s2, $f20", 40, 80, f20, s2);
+ TESTINSNMOVEtd("mthc1 $s3, $f22", 44, 88, f22, s3);
+ TESTINSNMOVEtd("mthc1 $s4, $f24", 48, 96, f24, s4);
+ TESTINSNMOVEtd("mthc1 $s5, $f26", 52, 104, f26, s5);
+ TESTINSNMOVEtd("mthc1 $s6, $f28", 56, 112, f28, s6);
+ TESTINSNMOVEtd("mthc1 $s7, $f30", 60, 120, f30, s7);
+#endif
+
printf("MOV.S\n");
TESTINSNMOVE1s("mov.s $f0, $f0", 0, f0, f0);
TESTINSNMOVE1s("mov.s $f0, $f1", 4, f0, f1);
@@ -631,5 +658,6 @@
TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 52, 0xffffffff, f0, f2, t3);
TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 56, 0x80000000, f0, f2, t3);
TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 60, 0x7fffffff, f0, f2, t3);
+
return 0;
}
Added: trunk/none/tests/mips32/MoveIns.stdout.exp-mips32r2-BE
==============================================================================
--- trunk/none/tests/mips32/MoveIns.stdout.exp-mips32r2-BE (added)
+++ trunk/none/tests/mips32/MoveIns.stdout.exp-mips32r2-BE Mon Feb 22 16:29:40 2016
@@ -0,0 +1,373 @@
+MFC1
+mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
+mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
+mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
+mfc1 $t4, $f3 :: fs 0.000000, rt 0x0
+mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
+mfc1 $t6, $f5 :: fs 0.000000, rt 0x0
+mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
+mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
+mfc1 $v1, $f8 :: fs nan, rt 0xffffffff
+mfc1 $s0, $f9 :: fs nan, rt 0xffffffff
+mfc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
+mfc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
+mfc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
+mfc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
+mfc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
+mfc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
+mfc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
+mfc1 $a0, $f17 :: fs 4.676074, rt 0x4095a266
+mfc1 $a1, $f18 :: fs 272008302207532160516096.000000, rt 0x66666666
+mfc1 $a2, $f19 :: fs -1.875000, rt 0xbff00000
+mfc1 $a3, $f20 :: fs 0.000000, rt 0x0
+mfc1 $v0, $f21 :: fs 1.875000, rt 0x3ff00000
+mfc1 $v1, $f22 :: fs 0.000000, rt 0x0
+mfc1 $t8, $f23 :: fs 0.000000, rt 0x252a2e2b
+mfc1 $t9, $f24 :: fs 0.000000, rt 0x262d2d2a
+mfc1 $t1, $f25 :: fs nan, rt 0xffffffff
+mfc1 $t2, $f26 :: fs nan, rt 0xffffffff
+MTC1
+mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
+mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
+mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
+mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
+mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
+mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
+mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
+mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
+mtc1 $v1, $f8 :: fs nan, rt 0xffffffff
+mtc1 $s0, $f9 :: fs nan, rt 0xffffffff
+mtc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
+mtc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
+mtc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
+mtc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
+mtc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
+mtc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
+mtc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
+mtc1 $a0, $f17 :: fs -0.000000, rt 0xa2666666
+mtc1 $a1, $f18 :: fs 272421228250166506553344.000000, rt 0x6666bff0
+mtc1 $a2, $f19 :: fs 0.000000, rt 0x0
+mtc1 $a3, $f20 :: fs 0.000000, rt 0x3ff0
+mtc1 $v0, $f21 :: fs 0.000000, rt 0x0
+mtc1 $v1, $f22 :: fs 0.000000, rt 0x252a
+mtc1 $t8, $f23 :: fs 0.000000, rt 0x2e2b262d
+mtc1 $t9, $f24 :: fs 0.000000, rt 0x2d2affff
+mtc1 $t1, $f25 :: fs nan, rt 0xffffffff
+mtc1 $t2, $f26 :: fs nan, rt 0xffff41d2
+MFHC1
+mfhc1 $t1, $f0 :: rt 0x12345678
+mfhc1 $t2, $f2 :: rt 0x66785bd6
+mfhc1 $t3, $f4 :: rt 0xbff550ff
+mfhc1 $v0, $f6 :: rt 0x47892
+mfhc1 $v1, $f8 :: rt 0x3ff00012
+mfhc1 $a0, $f10 :: rt 0x123654
+mfhc1 $a1, $f12 :: rt 0x252a2e2b
+mfhc1 $a2, $f14 :: rt 0x26852147
+mfhc1 $a3, $f16 :: rt 0x12345678
+mfhc1 $s0, $f18 :: rt 0x66785bd6
+mfhc1 $s1, $f20 :: rt 0x789651ff
+mfhc1 $s2, $f22 :: rt 0xff23f4
+mfhc1 $s3, $f24 :: rt 0x3ff00012
+mfhc1 $s4, $f26 :: rt 0xaabbcdfe
+mfhc1 $s5, $f28 :: rt 0xa1b2b2a1
+mfhc1 $s6, $f30 :: rt 0x25698741
+MTHC1
+mthc1 $t2, $f0 :: out: 4095a26687654321
+mthc1 $t3, $f2 :: out: 6666666668466667
+mthc1 $v0, $f4 :: out: bff0000007788000
+mthc1 $v1, $f6 :: out: 36500000
+mthc1 $a0, $f8 :: out: 3ff0000056789600
+mthc1 $a1, $f10 :: out: 78000000
+mthc1 $a2, $f12 :: out: 1252a2e2b
+mthc1 $a3, $f14 :: out: 262d2d2a962d2d2a
+mthc1 $s0, $f16 :: out: ffffffff87654321
+mthc1 $s1, $f18 :: out: ffffffff68466667
+mthc1 $s2, $f20 :: out: 41d2658007788055
+mthc1 $s3, $f22 :: out: b487e5c9f1f5f6f8
+mthc1 $s4, $f24 :: out: 4202658056789600
+mthc1 $s5, $f26 :: out: b750e388efcd1256
+mthc1 $s6, $f28 :: out: 3e45798ea3a5a6aa
+mthc1 $s7, $f30 :: out: e2308c3a23654786
+MOV.S
+mov.s $f0, $f0 :: fs 0.000000, rt 0x0
+mov.s $f0, $f1 :: fs 456.248962, rt 0x43e41fde
+mov.s $f1, $f2 :: fs 3.000000, rt 0x40400000
+mov.s $f2, $f3 :: fs -1.000000, rt 0xbf800000
+mov.s $f3, $f4 :: fs 1384.599976, rt 0x44ad1333
+mov.s $f4, $f5 :: fs -7.294568, rt 0xc0e96d19
+mov.s $f5, $f6 :: fs 1000000000.000000, rt 0x4e6e6b28
+mov.s $f6, $f7 :: fs -5786.470215, rt 0xc5b4d3c3
+mov.s $f7, $f8 :: fs 1752.000000, rt 0x44db0000
+mov.s $f8, $f9 :: fs 0.002457, rt 0x3b210e02
+mov.s $f9, $f10 :: fs 0.000000, rt 0x322bcc77
+mov.s $f10, $f11 :: fs -248562.765625, rt 0xc872bcb1
+mov.s $f11, $f12 :: fs -45786.476562, rt 0xc732da7a
+mov.s $f12, $f13 :: fs 456.248962, rt 0x43e41fde
+mov.s $f13, $f14 :: fs 34.000462, rt 0x42080079
+mov.s $f14, $f15 :: fs 45786.476562, rt 0x4732da7a
+mov.s $f15, $f16 :: fs 1752065.000000, rt 0x49d5e008
+mov.s $f16, $f17 :: fs 0.000000, rt 0x0
+mov.s $f17, $f18 :: fs 456.248962, rt 0x43e41fde
+mov.s $f18, $f19 :: fs 3.000000, rt 0x40400000
+mov.s $f19, $f20 :: fs -1.000000, rt 0xbf800000
+mov.s $f20, $f21 :: fs 1384.599976, rt 0x44ad1333
+mov.s $f21, $f22 :: fs -7.294568, rt 0xc0e96d19
+mov.s $f22, $f23 :: fs 1000000000.000000, rt 0x4e6e6b28
+mov.s $f23, $f24 :: fs -5786.470215, rt 0xc5b4d3c3
+mov.s $f24, $f25 :: fs 1752.000000, rt 0x44db0000
+mov.s $f25, $f26 :: fs 0.002457, rt 0x3b210e02
+MOV.D
+mov.d $f0, $f0 ::fs 0.000000, rt 0x43e41fde
+mov.d $f0, $f0 ::fs 32.000023, rt 0xbf800000
+mov.d $f0, $f2 ::fs 68651422688883217793024.000000, rt 0xc0e96d19
+mov.d $f2, $f4 ::fs 6560668703763947508025308754622564314214011401697745896073690307624960.000000, rt 0xc5b4d3c3
+mov.d $f2, $f4 ::fs 510015646723392374046720.000000, rt 0x3b210e02
+mov.d $f4, $f6 ::fs 0.000000, rt 0xc872bcb1
+mov.d $f4, $f6 ::fs -97892595594330935155564225983676416.000000, rt 0x43e41fde
+mov.d $f6, $f8 ::fs 12885895398.356678, rt 0x4732da7a
+mov.d $f6, $f8 ::fs 499539571012599806217935122808662584365932347392.000000, rt 0x42d60000
+mov.d $f8, $f10 ::fs 0.000000, rt 0x43e41fde
+mov.d $f8, $f10 ::fs 32.000023, rt 0xbf800000
+mov.d $f10, $f12 ::fs 68651422688883217793024.000000, rt 0xc0e96d19
+mov.d $f10, $f12 ::fs 6560668703763947508025308754622564314214011401697745896073690307624960.000000, rt 0xc5b4d3c3
+mov.d $f12, $f14 ::fs 510015646723392374046720.000000, rt 0x3b210e02
+mov.d $f12, $f14 ::fs 0.000000, rt 0xc872bcb1
+mov.d $f14, $f16 ::fs -97892595594330935155564225983676416.000000, rt 0x43e41fde
+mov.d $f14, $f16 ::fs 12885895398.356678, rt 0x4732da7a
+mov.d $f16, $f18 ::fs 499539571012599806217935122808662584365932347392.000000, rt 0x42d60000
+mov.d $f16, $f18 ::fs 0.000000, rt 0x43e41fde
+mov.d $f18, $f20 ::fs 32.000023, rt 0xbf800000
+mov.d $f18, $f20 ::fs 68651422688883217793024.000000, rt 0xc0e96d19
+mov.d $f20, $f22 ::fs 6560668703763947508025308754622564314214011401697745896073690307624960.000000, rt 0xc5b4d3c3
+mov.d $f20, $f22 ::fs 510015646723392374046720.000000, rt 0x3b210e02
+mov.d $f22, $f24 ::fs 0.000000, rt 0xc872bcb1
+mov.d $f22, $f24 ::fs -97892595594330935155564225983676416.000000, rt 0x43e41fde
+mov.d $f24, $f26 ::fs 12885895398.356678, rt 0x4732da7a
+mov.d $f24, $f26 ::fs 499539571012599806217935122808662584365932347392.000000, rt 0x42d60000
+MOVF
+movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
+MOVF.S
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 3.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -1.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1384.599976, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -7.294568, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1000000000.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -5786.470215, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1752.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 0.002457, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -248562.765625, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+MOVF.D
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xb750e388 0x42026580, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xe2308c3a 0x3e45798e, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3746f65f 0x3fbf9add, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x66666666 0x4095a266, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0x3ff00000, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x262d2d2a 0x252a2e2b, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xb750e388 0x42026580, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xe2308c3a 0x3e45798e, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3746f65f 0x3fbf9add, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x66666666 0x4095a266, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x0 0x3ff00000, cc: 0
+MOVN.S
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.s $f0, $f2, $t3 :: fs rt 0x40400000
+movn.s $f0, $f2, $t3 :: fs rt 0xbf800000
+movn.s $f0, $f2, $t3 :: fs rt 0x44ad1333
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
+movn.s $f0, $f2, $t3 :: fs rt 0x44db0000
+movn.s $f0, $f2, $t3 :: fs rt 0x3b210e02
+movn.s $f0, $f2, $t3 :: fs rt 0x322bcc77
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.s $f0, $f2, $t3 :: fs rt 0x42080079
+movn.s $f0, $f2, $t3 :: fs rt 0x4732da7a
+MOVN.D
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.d $f0, $f2, $t3 :: fs rt 0x40400000
+movn.d $f0, $f2, $t3 :: fs rt 0xbf800000
+movn.d $f0, $f2, $t3 :: fs rt 0x44ad1333
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
+movn.d $f0, $f2, $t3 :: fs rt 0x44db0000
+movn.d $f0, $f2, $t3 :: fs rt 0x3b210e02
+movn.d $f0, $f2, $t3 :: fs rt 0x322bcc77
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.d $f0, $f2, $t3 :: fs rt 0x42080079
+movn.d $f0, $f2, $t3 :: fs rt 0x4732da7a
+MOVT
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
+MOVT.S
+movt.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 3.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -1.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1384.599976, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -7.294568, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1000000000.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -5786.470215, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1752.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 0.002457, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -248562.765625, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+MOVT.D
+movt.d $f4, $f6, $fcc0 :: out: 0x66666666 0x4095a266, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0x3ff00000, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x262d2d2a 0x252a2e2b, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xb750e388 0x42026580, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xe2308c3a 0x3e45798e, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3746f65f 0x3fbf9add, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x66666666 0x4095a266, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0x3ff00000, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x262d2d2a 0x252a2e2b, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xb487e5c9 0x41d26580, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0x0 0xbff00000, cc: 0
+MOVZ.S
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0xc0e96d19
+movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0xc872bcb1
+movz.s $f0, $f2, $t3 :: fs rt 0xc732da7a
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+MOVZ.D
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0xc0e96d19
+movz.d $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0xc872bcb1
+movz.d $f0, $f2, $t3 :: fs rt 0xc732da7a
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
Added: trunk/none/tests/mips32/MoveIns.stdout.exp-mips32r2-LE
==============================================================================
--- trunk/none/tests/mips32/MoveIns.stdout.exp-mips32r2-LE (added)
+++ trunk/none/tests/mips32/MoveIns.stdout.exp-mips32r2-LE Mon Feb 22 16:29:40 2016
@@ -0,0 +1,373 @@
+MFC1
+mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
+mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
+mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
+mfc1 $t4, $f3 :: fs 0.000000, rt 0x0
+mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
+mfc1 $t6, $f5 :: fs 0.000000, rt 0x0
+mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
+mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
+mfc1 $v1, $f8 :: fs nan, rt 0xffffffff
+mfc1 $s0, $f9 :: fs nan, rt 0xffffffff
+mfc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
+mfc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
+mfc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
+mfc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
+mfc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
+mfc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
+mfc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
+mfc1 $a0, $f17 :: fs 4.676074, rt 0x4095a266
+mfc1 $a1, $f18 :: fs 272008302207532160516096.000000, rt 0x66666666
+mfc1 $a2, $f19 :: fs -1.875000, rt 0xbff00000
+mfc1 $a3, $f20 :: fs 0.000000, rt 0x0
+mfc1 $v0, $f21 :: fs 1.875000, rt 0x3ff00000
+mfc1 $v1, $f22 :: fs 0.000000, rt 0x0
+mfc1 $t8, $f23 :: fs 0.000000, rt 0x252a2e2b
+mfc1 $t9, $f24 :: fs 0.000000, rt 0x262d2d2a
+mfc1 $t1, $f25 :: fs nan, rt 0xffffffff
+mfc1 $t2, $f26 :: fs nan, rt 0xffffffff
+MTC1
+mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
+mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
+mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
+mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
+mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
+mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
+mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
+mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
+mtc1 $v1, $f8 :: fs nan, rt 0xffffffff
+mtc1 $s0, $f9 :: fs nan, rt 0xffffffff
+mtc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
+mtc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
+mtc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
+mtc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
+mtc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
+mtc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
+mtc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
+mtc1 $a0, $f17 :: fs 271833904815561865428992.000000, rt 0x66664095
+mtc1 $a1, $f18 :: fs 0.000000, rt 0x6666
+mtc1 $a2, $f19 :: fs 0.000000, rt 0xbff0
+mtc1 $a3, $f20 :: fs 0.000000, rt 0x0
+mtc1 $v0, $f21 :: fs 0.000000, rt 0x3ff0
+mtc1 $v1, $f22 :: fs 0.000000, rt 0x2e2b0000
+mtc1 $t8, $f23 :: fs 0.000000, rt 0x2d2a252a
+mtc1 $t9, $f24 :: fs nan, rt 0xffff262d
+mtc1 $t1, $f25 :: fs nan, rt 0xffffffff
+mtc1 $t2, $f26 :: fs 76148150529073774329856.000000, rt 0x6580ffff
+MFHC1
+mfhc1 $t1, $f0 :: rt 0x12345678
+mfhc1 $t2, $f2 :: rt 0x66785bd6
+mfhc1 $t3, $f4 :: rt 0xbff550ff
+mfhc1 $v0, $f6 :: rt 0x47892
+mfhc1 $v1, $f8 :: rt 0x3ff00012
+mfhc1 $a0, $f10 :: rt 0x123654
+mfhc1 $a1, $f12 :: rt 0x252a2e2b
+mfhc1 $a2, $f14 :: rt 0x26852147
+mfhc1 $a3, $f16 :: rt 0x12345678
+mfhc1 $s0, $f18 :: rt 0x66785bd6
+mfhc1 $s1, $f20 :: rt 0x789651ff
+mfhc1 $s2, $f22 :: rt 0xff23f4
+mfhc1 $s3, $f24 :: rt 0x3ff00012
+mfhc1 $s4, $f26 :: rt 0xaabbcdfe
+mfhc1 $s5, $f28 :: rt 0xa1b2b2a1
+mfhc1 $s6, $f30 :: rt 0x25698741
+MTHC1
+mthc1 $t2, $f0 :: out: 4095a26687654321
+mthc1 $t3, $f2 :: out: 6666666668466667
+mthc1 $v0, $f4 :: out: bff0000007788000
+mthc1 $v1, $f6 :: out: 36500000
+mthc1 $a0, $f8 :: out: 3ff0000056789600
+mthc1 $a1, $f10 :: out: 78000000
+mthc1 $a2, $f12 :: out: 1252a2e2b
+mthc1 $a3, $f14 :: out: 262d2d2a962d2d2a
+mthc1 $s0, $f16 :: out: ffffffff87654321
+mthc1 $s1, $f18 :: out: ffffffff68466667
+mthc1 $s2, $f20 :: out: 41d2658007788055
+mthc1 $s3, $f22 :: out: b487e5c9f1f5f6f8
+mthc1 $s4, $f24 :: out: 4202658056789600
+mthc1 $s5, $f26 :: out: b750e388efcd1256
+mthc1 $s6, $f28 :: out: 3e45798ea3a5a6aa
+mthc1 $s7, $f30 :: out: e2308c3a23654786
+MOV.S
+mov.s $f0, $f0 :: fs 0.000000, rt 0x0
+mov.s $f0, $f1 :: fs 456.248962, rt 0x43e41fde
+mov.s $f1, $f2 :: fs 3.000000, rt 0x40400000
+mov.s $f2, $f3 :: fs -1.000000, rt 0xbf800000
+mov.s $f3, $f4 :: fs 1384.599976, rt 0x44ad1333
+mov.s $f4, $f5 :: fs -7.294568, rt 0xc0e96d19
+mov.s $f5, $f6 :: fs 1000000000.000000, rt 0x4e6e6b28
+mov.s $f6, $f7 :: fs -5786.470215, rt 0xc5b4d3c3
+mov.s $f7, $f8 :: fs 1752.000000, rt 0x44db0000
+mov.s $f8, $f9 :: fs 0.002457, rt 0x3b210e02
+mov.s $f9, $f10 :: fs 0.000000, rt 0x322bcc77
+mov.s $f10, $f11 :: fs -248562.765625, rt 0xc872bcb1
+mov.s $f11, $f12 :: fs -45786.476562, rt 0xc732da7a
+mov.s $f12, $f13 :: fs 456.248962, rt 0x43e41fde
+mov.s $f13, $f14 :: fs 34.000462, rt 0x42080079
+mov.s $f14, $f15 :: fs 45786.476562, rt 0x4732da7a
+mov.s $f15, $f16 :: fs 1752065.000000, rt 0x49d5e008
+mov.s $f16, $f17 :: fs 0.000000, rt 0x0
+mov.s $f17, $f18 :: fs 456.248962, rt 0x43e41fde
+mov.s $f18, $f19 :: fs 3.000000, rt 0x40400000
+mov.s $f19, $f20 :: fs -1.000000, rt 0xbf800000
+mov.s $f20, $f21 :: fs 1384.599976, rt 0x44ad1333
+mov.s $f21, $f22 :: fs -7.294568, rt 0xc0e96d19
+mov.s $f22, $f23 :: fs 1000000000.000000, rt 0x4e6e6b28
+mov.s $f23, $f24 :: fs -5786.470215, rt 0xc5b4d3c3
+mov.s $f24, $f25 :: fs 1752.000000, rt 0x44db0000
+mov.s $f25, $f26 :: fs 0.002457, rt 0x3b210e02
+MOV.D
+mov.d $f0, $f0 ::fs 11600973572943642624.000000, rt 0x0
+mov.d $f0, $f0 ::fs -0.007813, rt 0x40400000
+mov.d $f0, $f2 ::fs -52072.789633, rt 0x44ad1333
+mov.d $f2, $f4 ::fs -6445705852632282607665545216.000000, rt 0x4e6e6b28
+mov.d $f2, $f4 ::fs 0.000000, rt 0x44db0000
+mov.d $f4, $f6 ::fs -102014360350703794652958156923702465265664.000000, rt 0x322bcc77
+mov.d $f4, $f6 ::fs 11600980417357008896.000000, rt 0xc732da7a
+mov.d $f6, $f8 ::fs 97892595018733988536880335157198848.000000, rt 0x42080079
+mov.d $f6, $f8 ::fs 96757042599808.125000, rt 0x49d5e008
+mov.d $f8, $f10 ::fs 11600973572943642624.000000, rt 0x0
+mov.d $f8, $f10 ::fs -0.007813, rt 0x40400000
+mov.d $f10, $f12 ::fs -52072.789633, rt 0x44ad1333
+mov.d $f10, $f12 ::fs -6445705852632282607665545216.000000, rt 0x4e6e6b28
+mov.d $f12, $f14 ::fs 0.000000, rt 0x44db0000
+mov.d $f12, $f14 ::fs -102014360350703794652958156923702465265664.000000, rt 0x322bcc77
+mov.d $f14, $f16 ::fs 11600980417357008896.000000, rt 0xc732da7a
+mov.d $f14, $f16 ::fs 97892595018733988536880335157198848.000000, rt 0x42080079
+mov.d $f16, $f18 ::fs 96757042599808.125000, rt 0x49d5e008
+mov.d $f16, $f18 ::fs 11600973572943642624.000000, rt 0x0
+mov.d $f18, $f20 ::fs -0.007813, rt 0x40400000
+mov.d $f18, $f20 ::fs -52072.789633, rt 0x44ad1333
+mov.d $f20, $f22 ::fs -6445705852632282607665545216.000000, rt 0x4e6e6b28
+mov.d $f20, $f22 ::fs 0.000000, rt 0x44db0000
+mov.d $f22, $f24 ::fs -102014360350703794652958156923702465265664.000000, rt 0x322bcc77
+mov.d $f22, $f24 ::fs 11600980417357008896.000000, rt 0xc732da7a
+mov.d $f24, $f26 ::fs 97892595018733988536880335157198848.000000, rt 0x42080079
+mov.d $f24, $f26 ::fs 96757042599808.125000, rt 0x49d5e008
+MOVF
+movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movf $t0, $t1, $fcc4 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movf $t0, $t1, $fcc4 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
+MOVF.S
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movf.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 3.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -1.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1384.599976, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -7.294568, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1000000000.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -5786.470215, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 1752.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 0.002457, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -248562.765625, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movf.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 0
+MOVF.D
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movf.d $f4, $f6, $fcc0 :: out: 0x42026580 0xb750e388, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3e45798e 0xe2308c3a, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3fbf9add 0x3746f65f, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x4095a266 0x66666666, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3ff00000 0x0, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x252a2e2b 0x262d2d2a, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x42026580 0xb750e388, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3e45798e 0xe2308c3a, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3fbf9add 0x3746f65f, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x4095a266 0x66666666, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movf.d $f4, $f6, $fcc0 :: out: 0x3ff00000 0x0, cc: 0
+MOVN.S
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.s $f0, $f2, $t3 :: fs rt 0x40400000
+movn.s $f0, $f2, $t3 :: fs rt 0xbf800000
+movn.s $f0, $f2, $t3 :: fs rt 0x44ad1333
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
+movn.s $f0, $f2, $t3 :: fs rt 0x44db0000
+movn.s $f0, $f2, $t3 :: fs rt 0x3b210e02
+movn.s $f0, $f2, $t3 :: fs rt 0x322bcc77
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x0
+movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.s $f0, $f2, $t3 :: fs rt 0x42080079
+movn.s $f0, $f2, $t3 :: fs rt 0x4732da7a
+MOVN.D
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.d $f0, $f2, $t3 :: fs rt 0x40400000
+movn.d $f0, $f2, $t3 :: fs rt 0xbf800000
+movn.d $f0, $f2, $t3 :: fs rt 0x44ad1333
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
+movn.d $f0, $f2, $t3 :: fs rt 0x44db0000
+movn.d $f0, $f2, $t3 :: fs rt 0x3b210e02
+movn.d $f0, $f2, $t3 :: fs rt 0x322bcc77
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x0
+movn.d $f0, $f2, $t3 :: fs rt 0x43e41fde
+movn.d $f0, $f2, $t3 :: fs rt 0x42080079
+movn.d $f0, $f2, $t3 :: fs rt 0x4732da7a
+MOVT
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movt $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x19, cc: 0
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
+movt $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x42, cc: 0
+MOVT.S
+movt.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 3.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -1.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1384.599976, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -7.294568, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1000000000.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -5786.470215, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 1752.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 0.002457, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 0.000000, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -248562.765625, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: -45786.476562, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 34.000462, cc: 1
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+movt.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 0
+MOVT.D
+movt.d $f4, $f6, $fcc0 :: out: 0x4095a266 0x66666666, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3ff00000 0x0, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x252a2e2b 0x262d2d2a, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x42026580 0xb750e388, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3e45798e 0xe2308c3a, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3fbf9add 0x3746f65f, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x4095a266 0x66666666, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x3ff00000 0x0, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x252a2e2b 0x262d2d2a, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xffffffff 0xffffffff, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0x41d26580 0xb487e5c9, cc: 1
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+movt.d $f4, $f6, $fcc0 :: out: 0xbff00000 0x0, cc: 0
+MOVZ.S
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0xc0e96d19
+movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0xc872bcb1
+movz.s $f0, $f2, $t3 :: fs rt 0xc732da7a
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+movz.s $f0, $f2, $t3 :: fs rt 0x0
+MOVZ.D
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0xc0e96d19
+movz.d $f0, $f2, $t3 :: fs rt 0x4e6e6b28
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $t3 :: fs rt 0x0
+movz.d $f0, $f2, $...
[truncated message content] |
|
From: <sv...@va...> - 2016-02-22 16:17:07
|
Author: petarj
Date: Mon Feb 22 16:16:59 2016
New Revision: 3211
Log:
mips: allow execution of mfhc1 and mthc1 for fp32 mode
MTHC1 and MFHC1 should be allowed for any MIPS32R2 compatible core, not only
for cores with FPU unit in fp64 mode.
Modified:
trunk/priv/guest_mips_toIR.c
Modified: trunk/priv/guest_mips_toIR.c
==============================================================================
--- trunk/priv/guest_mips_toIR.c (original)
+++ trunk/priv/guest_mips_toIR.c Mon Feb 22 16:16:59 2016
@@ -12228,28 +12228,39 @@
case 0x11: { /* COP1 */
if (fmt == 0x3 && fd == 0 && function == 0) { /* MFHC1 */
DIP("mfhc1 r%u, f%u", rt, fs);
- if (fp_mode64) {
- t0 = newTemp(Ity_I64);
- t1 = newTemp(Ity_I32);
- assign(t0, unop(Iop_ReinterpF64asI64, getDReg(fs)));
- assign(t1, unop(Iop_64HIto32, mkexpr(t0)));
- putIReg(rt, mkWidenFrom32(ty, mkexpr(t1), True));
- } else {
- ILLEGAL_INSTRUCTON;
+ if (VEX_MIPS_CPU_HAS_MIPS32R2(archinfo->hwcaps)) {
+ if (fp_mode64) {
+ t0 = newTemp(Ity_I64);
+ t1 = newTemp(Ity_I32);
+ assign(t0, unop(Iop_ReinterpF64asI64, getDReg(fs)));
+ assign(t1, unop(Iop_64HIto32, mkexpr(t0)));
+ putIReg(rt, mkWidenFrom32(ty, mkexpr(t1), True));
+ break;
+ } else if ((fs & 1) == 0) {
+ putIReg(rt, mkWidenFrom32(ty, unop(Iop_ReinterpF32asI32,
+ getFReg(fs | 1)), True));
+ break;
+ }
}
+ ILLEGAL_INSTRUCTON;
break;
} else if (fmt == 0x7 && fd == 0 && function == 0) { /* MTHC1 */
DIP("mthc1 r%u, f%u", rt, fs);
- if (fp_mode64) {
- t0 = newTemp(Ity_I64);
- assign(t0, binop(Iop_32HLto64, getIReg(rt),
- unop(Iop_ReinterpF32asI32,
- getLoFromF64(Ity_F64 /* 32FPR mode. */,
- getDReg(fs)))));
- putDReg(fs, unop(Iop_ReinterpI64asF64, mkexpr(t0)));
- } else {
- ILLEGAL_INSTRUCTON;
+ if (VEX_MIPS_CPU_HAS_MIPS32R2(archinfo->hwcaps)) {
+ if (fp_mode64) {
+ t0 = newTemp(Ity_I64);
+ assign(t0, binop(Iop_32HLto64, mkNarrowTo32(ty, getIReg(rt)),
+ unop(Iop_ReinterpF32asI32,
+ getLoFromF64(Ity_F64, getDReg(fs)))));
+ putDReg(fs, unop(Iop_ReinterpI64asF64, mkexpr(t0)));
+ break;
+ } else if ((fs & 1) == 0) {
+ putFReg(fs | 1, unop(Iop_ReinterpI32asF32,
+ mkNarrowTo32(ty, getIReg(rt))));
+ break;
+ }
}
+ ILLEGAL_INSTRUCTON;
break;
} else if (fmt == 0x8) { /* BC */
/* FcConditionalCode(bc1_cc) */
|
|
From: Anuta M. <man...@gm...> - 2016-02-22 09:22:35
|
To elaborate more on my implementation, I have written the wrapper inside a file called tr_wrapper.c and added this my Makefile: (as is seen in Helgrind's makefile) My tool is called tracker. *#----------------------------------------------------------------------------# vgpreload_tracker-<platform>.so#----------------------------------------------------------------------------noinst_PROGRAMS += vgpreload_tracker-@VGCONF_ARCH_PRI@-@VGCONF_OS@.soif VGCONF_HAVE_PLATFORM_SECnoinst_PROGRAMS += vgpreload_tracker-@VGCONF_ARCH_SEC@-@VGCONF_OS@.soendifif VGCONF_OS_IS_DARWINnoinst_DSYMS = $(noinst_PROGRAMS)endifVGPRELOAD_TRACKER_SOURCES_COMMON = tr_intercepts.cvgpreload_tracker_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES = \ $(VGPRELOAD_TRACKER_SOURCES_COMMON)vgpreload_tracker_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)vgpreload_tracker_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CFLAGS = \ $(AM_CFLAGS_PSO_@VGCONF_PLATFORM_PRI_CAPS@)vgpreload_tracker_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \ $(LIBREPLACEMALLOC_@VGCONF_PLATFORM_PRI_CAPS@)vgpreload_tracker_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)if VGCONF_HAVE_PLATFORM_SECvgpreload_tracker_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES = \ $(VGPRELOAD_TRACKER_SOURCES_COMMON)vgpreload_tracker_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS = \ $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)vgpreload_tracker_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CFLAGS = \ $(AM_CFLAGS_PSO_@VGCONF_PLATFORM_SEC_CAPS@)vgpreload_tracker_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_DEPENDENCIES = \ $(LIBREPLACEMALLOC_@VGCONF_PLATFORM_SEC_CAPS@)vgpreload_tracker_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_LDFLAGS = \ $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \ $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)endif* On Mon, Feb 22, 2016 at 1:07 PM, Anuta Mukherjee <man...@gm...> wrote: > Hi Philippe, > > Thank you for taking the time to respond to a newbie like me! > > The tool I am trying to create is to perform race detection on sequential > tests that call various API's of C libraries. Once I can pinpoint the data > races in the libraries I will use the existing sequential tests to write > multithreaded tests that when run on a dynamic race detector will expose > the data races in the C libraries. > > I have read all the documentation you mentioned. I've created a simple > tool that tracks thread creation using the VG_(track_pre_thread_ll_create) > function. > > My next objective is to track mutex locks and unlocks. As far as I can > see, Helgrind does this using some wrapper functions it defines inside > hg_intercepts.c > > I have been trying to write my own wrapper functions to track pthread > events (I have read this > <http://valgrind.org/docs/manual/manual-core-adv.html#manual-core-adv.wrapping> > to get a basic idea), but I am getting stuck and have some questions. > > To wrap the pthread_create() function, this is the wrapper I wrote: > > *int I_WRAP_SONAME_FNNAME_ZZ(**libpthreadZdsoZd0,* > > > > > > *pthreadZucreateZAZa)(pthread_t *thread,const pthread_attr_t *attr,void* > (*start),void *arg){ int ret; OrigFn fn; VALGRIND_GET_ORIG_FN(fn); > CALL_FN_W_WWWW(ret,fn,thread,* > > > > > *attr,start,arg); printf("\nPthread create just happened\n"); return > ret;}* > > > When I try to run it, this is the error I'm getting: > > > valgrind: m_redir.c:627 (vgPlain_redir_notify_new_DebugInfo): Assertion > 'is_plausible_guest_addr(sym_avmas.main)' failed. > Segmentation fault (core dumped) > > What am I missing? > > > > On Thu, Feb 18, 2016 at 3:26 AM, Philippe Waroquiers < > phi...@sk...> wrote: > >> On Tue, 2016-02-16 at 14:57 +0530, Anuta Mukherjee wrote: >> > Hi, >> > I am very new to Valgrind and am trying to write a tool where I need >> > to track: >> > - Variable declarations (global and local variables) >> > - Reads/writes to these variables >> > - Locks and unlocks of mutexes >> > How do I track reads/writes to variables declared by my test program? >> > How do I track pthread_mutex_{lock,unlock}? >> > >> It would be good to indicate what documentation and/or code >> you have already read and explain more in details what you have >> tried/not understood/... >> >> But ok, let's assume you have not read much :). >> >> If you want to write a tool, you must have a good idea of >> how valgrind works. >> >> So, read the 'introduction' papers/doc such as: >> http://www.valgrind.org/docs/valgrind2007.pdf >> and >> http://www.valgrind.org/docs/manual/tech-docs.html >> Look at the code of an easy tool (typically, lackey). >> >> Maybe others valgrind developers might give additional relevant pointers >> if I missed some interesting introductory documentation ? >> >> >> After that, the best is to read the source. >> E.g. scan the interfaces that valgrind provides to tools >> (these are include/pub_tool_*.h). >> >> Read the implementation of a tool that does somewhat >> similar things to what you want to do. >> For your objective above, helgrind is a good example: >> * it intercepts (a.o.) lock/unlocks >> * and it tracks read/write to the memory. >> >> >> That being said, valgrind tools are working on binary code : tools do >> not track variable declarations and/or read/write to variables. >> They (can) track read/write to memory, or stack pointer modifications >> (e.g. the sp changes that are done at entry of a function). >> >> There is no 'high level interface' to track variables declaration or rw. >> valgrind provides some support to translate an address >> into e.g. global and/or stack variables. >> See e.g. pub_tool_addrinfo.h >> >> It would be interesting also to describe the kind of tool you >> want to write. >> >> After that, once you have read doc and code, if you have more >> specific questions, do not hesitate to ask, but you must first >> read and understand the bulk by yourself, otherwise you will >> have to send hundreds of mails with questions :). >> >> Hoping this helps ... >> >> Philippe >> >> >> >> > > > -- > Anuta Mukherjee, > Dept of Computer Science Engg, > CEG, Anna University > -- Anuta Mukherjee, Dept of Computer Science Engg, CEG, Anna University |
|
From: Anuta M. <man...@gm...> - 2016-02-22 07:37:24
|
Hi Philippe, Thank you for taking the time to respond to a newbie like me! The tool I am trying to create is to perform race detection on sequential tests that call various API's of C libraries. Once I can pinpoint the data races in the libraries I will use the existing sequential tests to write multithreaded tests that when run on a dynamic race detector will expose the data races in the C libraries. I have read all the documentation you mentioned. I've created a simple tool that tracks thread creation using the VG_(track_pre_thread_ll_create) function. My next objective is to track mutex locks and unlocks. As far as I can see, Helgrind does this using some wrapper functions it defines inside hg_intercepts.c I have been trying to write my own wrapper functions to track pthread events (I have read this <http://valgrind.org/docs/manual/manual-core-adv.html#manual-core-adv.wrapping> to get a basic idea), but I am getting stuck and have some questions. To wrap the pthread_create() function, this is the wrapper I wrote: *int I_WRAP_SONAME_FNNAME_ZZ(**libpthreadZdsoZd0,* *pthreadZucreateZAZa)(pthread_t *thread,const pthread_attr_t *attr,void* (*start),void *arg){ int ret; OrigFn fn; VALGRIND_GET_ORIG_FN(fn); CALL_FN_W_WWWW(ret,fn,thread,* *attr,start,arg); printf("\nPthread create just happened\n"); return ret;}* When I try to run it, this is the error I'm getting: valgrind: m_redir.c:627 (vgPlain_redir_notify_new_DebugInfo): Assertion 'is_plausible_guest_addr(sym_avmas.main)' failed. Segmentation fault (core dumped) What am I missing? On Thu, Feb 18, 2016 at 3:26 AM, Philippe Waroquiers < phi...@sk...> wrote: > On Tue, 2016-02-16 at 14:57 +0530, Anuta Mukherjee wrote: > > Hi, > > I am very new to Valgrind and am trying to write a tool where I need > > to track: > > - Variable declarations (global and local variables) > > - Reads/writes to these variables > > - Locks and unlocks of mutexes > > How do I track reads/writes to variables declared by my test program? > > How do I track pthread_mutex_{lock,unlock}? > > > It would be good to indicate what documentation and/or code > you have already read and explain more in details what you have > tried/not understood/... > > But ok, let's assume you have not read much :). > > If you want to write a tool, you must have a good idea of > how valgrind works. > > So, read the 'introduction' papers/doc such as: > http://www.valgrind.org/docs/valgrind2007.pdf > and > http://www.valgrind.org/docs/manual/tech-docs.html > Look at the code of an easy tool (typically, lackey). > > Maybe others valgrind developers might give additional relevant pointers > if I missed some interesting introductory documentation ? > > > After that, the best is to read the source. > E.g. scan the interfaces that valgrind provides to tools > (these are include/pub_tool_*.h). > > Read the implementation of a tool that does somewhat > similar things to what you want to do. > For your objective above, helgrind is a good example: > * it intercepts (a.o.) lock/unlocks > * and it tracks read/write to the memory. > > > That being said, valgrind tools are working on binary code : tools do > not track variable declarations and/or read/write to variables. > They (can) track read/write to memory, or stack pointer modifications > (e.g. the sp changes that are done at entry of a function). > > There is no 'high level interface' to track variables declaration or rw. > valgrind provides some support to translate an address > into e.g. global and/or stack variables. > See e.g. pub_tool_addrinfo.h > > It would be interesting also to describe the kind of tool you > want to write. > > After that, once you have read doc and code, if you have more > specific questions, do not hesitate to ask, but you must first > read and understand the bulk by yourself, otherwise you will > have to send hundreds of mails with questions :). > > Hoping this helps ... > > Philippe > > > > -- Anuta Mukherjee, Dept of Computer Science Engg, CEG, Anna University |