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From: <sv...@va...> - 2015-08-03 21:21:49
|
Author: florian
Date: Mon Aug 3 22:21:42 2015
New Revision: 15480
Log:
Fix printf format inconsistencies as pointed out by gcc -Wformat-signedness.
Modified:
trunk/helgrind/hg_basics.c
trunk/helgrind/hg_basics.h
trunk/helgrind/hg_errors.c
trunk/helgrind/hg_main.c
trunk/helgrind/libhb_core.c
Modified: trunk/helgrind/hg_basics.c
==============================================================================
--- trunk/helgrind/hg_basics.c (original)
+++ trunk/helgrind/hg_basics.c Mon Aug 3 22:21:42 2015
@@ -77,7 +77,7 @@
UWord HG_(clo_conflict_cache_size) = 2000000;
-Word HG_(clo_sanity_flags) = 0;
+UWord HG_(clo_sanity_flags) = 0;
Bool HG_(clo_free_is_write) = False;
Modified: trunk/helgrind/hg_basics.h
==============================================================================
--- trunk/helgrind/hg_basics.h (original)
+++ trunk/helgrind/hg_basics.h Mon Aug 3 22:21:42 2015
@@ -101,7 +101,7 @@
/* Sanity check level. This is an or-ing of
SCE_{THREADS,LOCKS,BIGRANGE,ACCESS,LAOG}. */
-extern Word HG_(clo_sanity_flags);
+extern UWord HG_(clo_sanity_flags);
/* Treat heap frees as if the memory was written immediately prior to
the free. This shakes out races in which memory is referenced by
Modified: trunk/helgrind/hg_errors.c
==============================================================================
--- trunk/helgrind/hg_errors.c (original)
+++ trunk/helgrind/hg_errors.c Mon Aug 3 22:21:42 2015
@@ -1296,7 +1296,7 @@
if (threadp->coretid == VG_INVALID_THREADID)
VG_(printf)(" tid (exited)\n");
else
- VG_(printf)(" tid %d\n", threadp->coretid);
+ VG_(printf)(" tid %u\n", threadp->coretid);
{
Lock** locksHeldW_P;
locksHeldW_P = enumerate_WordSet_into_LockP_vector(
Modified: trunk/helgrind/hg_main.c
==============================================================================
--- trunk/helgrind/hg_main.c (original)
+++ trunk/helgrind/hg_main.c Mon Aug 3 22:21:42 2015
@@ -520,7 +520,7 @@
if (thr->coretid == VG_INVALID_THREADID)
VG_(printf)("tid (exited) ");
else
- VG_(printf)("tid %d ", thr->coretid);
+ VG_(printf)("tid %u ", thr->coretid);
}
}
@@ -1037,7 +1037,7 @@
static void shadow_mem_make_NoAccess_NoFX ( Thread* thr, Addr aIN, SizeT len )
{
if (0 && len > 500)
- VG_(printf)("make NoAccess_NoFX ( %#lx, %ld )\n", aIN, len );
+ VG_(printf)("make NoAccess_NoFX ( %#lx, %lu )\n", aIN, len );
// has no effect (NoFX)
libhb_srange_noaccess_NoFX( thr->hbthr, aIN, len );
}
@@ -1045,7 +1045,7 @@
static void shadow_mem_make_NoAccess_AHAE ( Thread* thr, Addr aIN, SizeT len )
{
if (0 && len > 500)
- VG_(printf)("make NoAccess_AHAE ( %#lx, %ld )\n", aIN, len );
+ VG_(printf)("make NoAccess_AHAE ( %#lx, %lu )\n", aIN, len );
// Actually Has An Effect (AHAE)
libhb_srange_noaccess_AHAE( thr->hbthr, aIN, len );
}
@@ -1053,7 +1053,7 @@
static void shadow_mem_make_Untracked ( Thread* thr, Addr aIN, SizeT len )
{
if (0 && len > 500)
- VG_(printf)("make Untracked ( %#lx, %ld )\n", aIN, len );
+ VG_(printf)("make Untracked ( %#lx, %lu )\n", aIN, len );
libhb_srange_untrack( thr->hbthr, aIN, len );
}
@@ -5021,7 +5021,7 @@
/* --- --- User-visible client requests --- --- */
case VG_USERREQ__HG_CLEAN_MEMORY:
- if (0) VG_(printf)("VG_USERREQ__HG_CLEAN_MEMORY(%#lx,%ld)\n",
+ if (0) VG_(printf)("VG_USERREQ__HG_CLEAN_MEMORY(%#lx,%lu)\n",
args[1], args[2]);
/* Call die_mem to (expensively) tidy up properly, if there
are any held locks etc in the area. Calling evh__die_mem
@@ -5053,7 +5053,7 @@
}
case _VG_USERREQ__HG_ARANGE_MAKE_UNTRACKED:
- if (0) VG_(printf)("HG_ARANGE_MAKE_UNTRACKED(%#lx,%ld)\n",
+ if (0) VG_(printf)("HG_ARANGE_MAKE_UNTRACKED(%#lx,%lu)\n",
args[1], args[2]);
if (args[2] > 0) { /* length */
evh__untrack_mem(args[1], args[2]);
@@ -5061,7 +5061,7 @@
break;
case _VG_USERREQ__HG_ARANGE_MAKE_TRACKED:
- if (0) VG_(printf)("HG_ARANGE_MAKE_TRACKED(%#lx,%ld)\n",
+ if (0) VG_(printf)("HG_ARANGE_MAKE_TRACKED(%#lx,%lu)\n",
args[1], args[2]);
if (args[2] > 0) { /* length */
evh__new_mem(args[1], args[2]);
@@ -5069,7 +5069,7 @@
break;
case _VG_USERREQ__HG_GET_ABITS:
- if (0) VG_(printf)("HG_GET_ABITS(%#lx,%#lx,%ld)\n",
+ if (0) VG_(printf)("HG_GET_ABITS(%#lx,%#lx,%lu)\n",
args[1], args[2], args[3]);
UChar *zzabit = (UChar *) args[2];
if (zzabit == NULL
Modified: trunk/helgrind/libhb_core.c
==============================================================================
--- trunk/helgrind/libhb_core.c (original)
+++ trunk/helgrind/libhb_core.c Mon Aug 3 22:21:42 2015
@@ -1503,7 +1503,7 @@
sequentialise_CacheLine( csvals, &csvalsUsed,
N_LINE_ARANGE, cl );
tl_assert(csvalsUsed >= 1 && csvalsUsed <= N_LINE_ARANGE);
- if (0) VG_(printf)("%lu ", csvalsUsed);
+ if (0) VG_(printf)("%ld ", csvalsUsed);
lineZ->dict[0] = lineZ->dict[1]
= lineZ->dict[2] = lineZ->dict[3] = SVal_INVALID;
@@ -2625,7 +2625,7 @@
n = vts->usedTS;
for (i = 0; i < n; i++) {
const ScalarTS *st = &vts->ts[i];
- VG_(printf)(i < n-1 ? "%u:%llu " : "%u:%llu", st->thrid, (ULong)st->tym);
+ VG_(printf)(i < n-1 ? "%d:%llu " : "%d:%llu", st->thrid, (ULong)st->tym);
}
VG_(printf)("]");
}
@@ -5050,7 +5050,7 @@
(XACmpFn_t)cmp__ULong_n_EC__by_ULong
);
if (0) VG_(printf)("record_race_info %u %u %u confThr %p "
- "confTym %llu found %d (%lu,%lu)\n",
+ "confTym %llu found %d (%ld,%ld)\n",
Cfailed, Kfailed, Cw,
confThr, confTym, found, firstIx, lastIx);
/* We can't indefinitely collect stack traces at VTS
@@ -5779,7 +5779,7 @@
stats__cache_make_New_arange += (ULong)len;
if (0 && len > 500)
- VG_(printf)("make New ( %#lx, %ld )\n", a, len );
+ VG_(printf)("make New ( %#lx, %lu )\n", a, len );
if (0) {
static UWord n_New_in_cache = 0;
@@ -6445,8 +6445,8 @@
live++;
hgthread = hgthread->admin;
}
- VG_(printf)(" libhb: threads live: %d exit_and_joinedwith %d"
- " exit %d joinedwith %d\n",
+ VG_(printf)(" libhb: threads live: %u exit_and_joinedwith %u"
+ " exit %u joinedwith %u\n",
live, llexit_and_joinedwith_done,
llexit_done, joinedwith_done);
VG_(printf)(" libhb: %d verydead_threads, "
@@ -6505,7 +6505,7 @@
/ (Double)(non0chain ? non0chain : 1));
for (i = 0; i <= MAXCHAIN; i++) {
if (chains[i] != 0)
- VG_(printf)( "[%d%s]=%d ",
+ VG_(printf)( "[%u%s]=%u ",
i, i == MAXCHAIN ? "+" : "",
chains[i]);
}
@@ -6860,9 +6860,9 @@
PlenCONSUME(APC, ARE, 1, APClen);
if (0)
- VG_(printf) ("addr %p[%ld] ARE %p"
- " BPC %p[%ld] BFC %p[%ld] FSM %p[%ld]"
- " AFC %p[%ld] APC %p[%ld]\n",
+ VG_(printf) ("addr %p[%lu] ARE %p"
+ " BPC %p[%lu] BFC %p[%lu] FSM %p[%lu]"
+ " AFC %p[%lu] APC %p[%lu]\n",
(void*)addr, len, (void*)ARE,
(void*)BPC, BPClen, (void*)BFC, BFClen, (void*)FSM, FSMlen,
(void*)AFC, AFClen, (void*)APC, APClen);
|
|
From: <sv...@va...> - 2015-08-03 21:05:32
|
Author: florian
Date: Mon Aug 3 22:05:20 2015
New Revision: 15479
Log:
Fix printf format inconsistencies as pointed out by gcc -Wformat-signedness.
Modified:
trunk/exp-bbv/bbv_main.c
trunk/exp-dhat/dh_main.c
trunk/exp-sgcheck/pc_common.c
trunk/exp-sgcheck/sg_main.c
trunk/massif/ms_main.c
Modified: trunk/exp-bbv/bbv_main.c
==============================================================================
--- trunk/exp-bbv/bbv_main.c (original)
+++ trunk/exp-bbv/bbv_main.c Mon Aug 3 22:05:20 2015
@@ -116,8 +116,8 @@
/* and function name for each basic block */
VG_(OSetGen_ResetIter)(instr_info_table);
while ( (bb_elem = VG_(OSetGen_Next)(instr_info_table)) ) {
- VG_(fprintf)( fp, "F:%d:%x:%s\n", bb_elem->block_num,
- (Int)bb_elem->BB_addr, bb_elem->fn_name);
+ VG_(fprintf)( fp, "F:%d:%lx:%s\n", bb_elem->block_num,
+ bb_elem->BB_addr, bb_elem->fn_name);
}
VG_(fclose)(fp);
@@ -565,10 +565,10 @@
VG_(sprintf)(buf,"\n\n"
"# Thread %d\n"
"# Total intervals: %d (Interval Size %d)\n"
- "# Total instructions: %lld\n"
- "# Total reps: %lld\n"
- "# Unique reps: %lld\n"
- "# Total fldcw instructions: %lld\n\n",
+ "# Total instructions: %llu\n"
+ "# Total reps: %llu\n"
+ "# Unique reps: %llu\n"
+ "# Total fldcw instructions: %llu\n\n",
i,
(Int)(bbv_thread[i].total_instr/(ULong)interval_size),
interval_size,
Modified: trunk/exp-dhat/dh_main.c
==============================================================================
--- trunk/exp-dhat/dh_main.c (original)
+++ trunk/exp-dhat/dh_main.c Mon Aug 3 22:05:20 2015
@@ -494,7 +494,7 @@
intro_Block(bk);
- if (0) VG_(printf)("ALLOC %ld -> %p\n", req_szB, p);
+ if (0) VG_(printf)("ALLOC %lu -> %p\n", req_szB, p);
return p;
}
@@ -537,7 +537,7 @@
static
void* renew_block ( ThreadId tid, void* p_old, SizeT new_req_szB )
{
- if (0) VG_(printf)("REALL %p %ld\n", p_old, new_req_szB);
+ if (0) VG_(printf)("REALL %p %lu\n", p_old, new_req_szB);
void* p_new = NULL;
tl_assert(new_req_szB > 0); // map 0 to 1
Modified: trunk/exp-sgcheck/pc_common.c
==============================================================================
--- trunk/exp-sgcheck/pc_common.c (original)
+++ trunk/exp-sgcheck/pc_common.c Mon Aug 3 22:05:20 2015
@@ -564,8 +564,8 @@
what, s );
VG_(pp_ExeContext)( VG_(get_error_where)(err) );
- emit( " <auxwhat>Address %#lx is %ld bytes inside a "
- "%ld-byte block free'd</auxwhat>\n",
+ emit( " <auxwhat>Address %#lx is %lu bytes inside a "
+ "%lu-byte block free'd</auxwhat>\n",
lo, lo-Seg__addr(seglo), Seg__size(seglo) );
VG_(pp_ExeContext)(Seg__where(seglo));
@@ -575,8 +575,8 @@
what, s );
VG_(pp_ExeContext)( VG_(get_error_where)(err) );
- emit( " Address %#lx is %ld bytes inside a "
- "%ld-byte block free'd\n",
+ emit( " Address %#lx is %lu bytes inside a "
+ "%lu-byte block free'd\n",
lo, lo-Seg__addr(seglo), Seg__size(seglo) );
VG_(pp_ExeContext)(Seg__where(seglo));
@@ -595,8 +595,8 @@
emit( " <auxwhat>First byte is "
"not inside a known block</auxwhat>\n" );
} else {
- emit( " <auxwhat>First byte (%#lx) is %ld bytes inside a "
- "%ld-byte block alloc'd</auxwhat>\n",
+ emit( " <auxwhat>First byte (%#lx) is %lu bytes inside a "
+ "%lu-byte block alloc'd</auxwhat>\n",
lo, lo-Seg__addr(seglo), Seg__size(seglo) );
VG_(pp_ExeContext)(Seg__where(seglo));
}
@@ -605,8 +605,8 @@
emit( " <auxwhat>Last byte is "
"not inside a known block</auxwhat>\n" );
} else {
- emit( " <auxwhat>Last byte (%#lx) is %ld bytes inside a "
- "%ld-byte block alloc'd</auxwhat>\n",
+ emit( " <auxwhat>Last byte (%#lx) is %lu bytes inside a "
+ "%lu-byte block alloc'd</auxwhat>\n",
hi, hi-Seg__addr(seghi), Seg__size(seghi) );
VG_(pp_ExeContext)(Seg__where(seghi));
}
@@ -620,8 +620,8 @@
if (UNKNOWN == seglo) {
emit( " First byte is not inside a known block\n" );
} else {
- emit( " First byte (%#lx) is %ld bytes inside a "
- "%ld-byte block alloc'd\n",
+ emit( " First byte (%#lx) is %lu bytes inside a "
+ "%lu-byte block alloc'd\n",
lo, lo-Seg__addr(seglo), Seg__size(seglo) );
VG_(pp_ExeContext)(Seg__where(seglo));
}
@@ -629,8 +629,8 @@
if (UNKNOWN == seghi) {
emit( " Last byte is not inside a known block\n" );
} else {
- emit( " Last byte (%#lx) is %ld bytes inside a "
- "%ld-byte block alloc'd\n",
+ emit( " Last byte (%#lx) is %lu bytes inside a "
+ "%lu-byte block alloc'd\n",
hi, hi-Seg__addr(seghi), Seg__size(seghi) );
VG_(pp_ExeContext)(Seg__where(seghi));
}
Modified: trunk/exp-sgcheck/sg_main.c
==============================================================================
--- trunk/exp-sgcheck/sg_main.c (original)
+++ trunk/exp-sgcheck/sg_main.c Mon Aug 3 22:05:20 2015
@@ -631,7 +631,7 @@
static void GlobalTreeNode__pp ( GlobalTreeNode* nd ) {
tl_assert(nd->descr);
- VG_(printf)("GTNode [%#lx,+%ld) %s",
+ VG_(printf)("GTNode [%#lx,+%lu) %s",
nd->addr, nd->szB, nd->descr->name);
}
@@ -1648,7 +1648,7 @@
sKey.szB = szB;
gKey.addr = ea;
gKey.szB = szB;
- if (0) VG_(printf)("Tree sizes %ld %ld\n",
+ if (0) VG_(printf)("Tree sizes %lu %lu\n",
VG_(sizeFM)(siTrees[tid]), VG_(sizeFM)(giTree));
sOK = VG_(findBoundsFM)( siTrees[tid],
(UWord*)&sLB, NULL/*unused*/,
@@ -1896,7 +1896,7 @@
if (0 && (sb || gb))
VG_(message)(Vg_DebugMsg,
"exp-sgcheck: new max tree sizes: "
- "StackTree %ld, GlobalTree %ld\n",
+ "StackTree %lu, GlobalTree %lu\n",
stats__max_sitree_size, stats__max_gitree_size );
}
} else {
Modified: trunk/massif/ms_main.c
==============================================================================
--- trunk/massif/ms_main.c (original)
+++ trunk/massif/ms_main.c Mon Aug 3 22:05:20 2015
@@ -1115,7 +1115,7 @@
default:
tl_assert2(0, "VERB_snapshot: unknown snapshot kind: %d", snapshot->kind);
}
- VERB(verbosity, "%s S%s%3d (t:%lld, hp:%ld, ex:%ld, st:%ld)\n",
+ VERB(verbosity, "%s S%s%3d (t:%lld, hp:%lu, ex:%lu, st:%lu)\n",
prefix, suffix, i,
snapshot->time,
snapshot->heap_szB,
@@ -1722,7 +1722,8 @@
}
VERB(3, ">>> (%ld, %ld)\n",
- new_req_szB - old_req_szB, new_slop_szB - old_slop_szB);
+ (SSizeT)(new_req_szB - old_req_szB),
+ (SSizeT)(new_slop_szB - old_slop_szB));
}
return p_new;
@@ -1902,7 +1903,7 @@
static INLINE void new_mem_stack_2(SizeT len, const HChar* what)
{
if (have_started_executing_code) {
- VERB(3, "<<< new_mem_stack (%ld)\n", len);
+ VERB(3, "<<< new_mem_stack (%lu)\n", len);
n_stack_allocs++;
update_stack_stats(len);
maybe_take_snapshot(Normal, what);
@@ -1913,7 +1914,7 @@
static INLINE void die_mem_stack_2(SizeT len, const HChar* what)
{
if (have_started_executing_code) {
- VERB(3, "<<< die_mem_stack (%ld)\n", -len);
+ VERB(3, "<<< die_mem_stack (-%lu)\n", len);
n_stack_frees++;
maybe_take_snapshot(Peak, "stkPEAK");
update_stack_stats(-len);
@@ -2149,7 +2150,7 @@
}
// Do the non-ip_desc part first...
- FP("%sn%d: %lu ", depth_str, sxpt->Sig.n_children, sxpt->szB);
+ FP("%sn%u: %lu ", depth_str, sxpt->Sig.n_children, sxpt->szB);
// For ip_descs beginning with "0xABCD...:" addresses, we first
// measure the length of the "0xabcd: " address at the start of the
@@ -2407,7 +2408,7 @@
STATS("stack allocs: %u\n", n_stack_allocs);
STATS("stack frees: %u\n", n_stack_frees);
STATS("XPts: %u\n", n_xpts);
- STATS("top-XPts: %u (%d%%)\n",
+ STATS("top-XPts: %u (%u%%)\n",
alloc_xpt->n_children,
( n_xpts ? alloc_xpt->n_children * 100 / n_xpts : 0));
STATS("XPt init expansions: %u\n", n_xpt_init_expansions);
|
|
From: <sv...@va...> - 2015-08-03 20:03:48
|
Author: florian
Date: Mon Aug 3 21:03:41 2015
New Revision: 15478
Log:
Improve the script to also show failures in the post-regtest checks
in the regtest log.
Modified:
trunk/nightly/bin/nightly
Modified: trunk/nightly/bin/nightly
==============================================================================
--- trunk/nightly/bin/nightly (original)
+++ trunk/nightly/bin/nightly Mon Aug 3 21:03:41 2015
@@ -175,6 +175,9 @@
"Running regression tests " \
"cd valgrind-$logfile && ${ABT_RUN_REGTEST}"
+ # Stash away the return code of the regression run
+ regrun_rc=$?
+
# Grab some indicative text for the short log file -- if the regtests
# succeeded, show their results. If we didn't make it that far, show the
# last 20 lines.
@@ -183,6 +186,14 @@
echo "Regression test results follow" >> $logfile.short
echo >> $logfile.short
awk '/^== [0-9]+ tests/, /^$/ { print }' $logfile.verbose >> $logfile.short
+ # Check the return code of the regression run; we might have successfully
+ # run all tests but still failed in the post-regtest checks.
+ if [ $regrun_rc != "0" ]; then
+ echo >> $logfile.short
+ echo "Last 20 lines of verbose log follow" >> $logfile.short \
+ echo >> $logfile.short
+ tail -20 $logfile.verbose >> $logfile.short
+ fi
) || (
echo >> $logfile.short
echo "Last 20 lines of verbose log follow" >> $logfile.short \
|
|
From: <sv...@va...> - 2015-08-03 16:03:29
|
Author: florian
Date: Mon Aug 3 17:03:13 2015
New Revision: 3167
Log:
Fix printf format inconsistencies as pointed out by GCC's
-Wformat-signedness.
Modified:
trunk/priv/guest_amd64_toIR.c
trunk/priv/guest_arm64_toIR.c
trunk/priv/guest_arm_toIR.c
trunk/priv/guest_mips_toIR.c
trunk/priv/guest_ppc_toIR.c
trunk/priv/guest_tilegx_toIR.c
trunk/priv/guest_x86_toIR.c
trunk/priv/host_amd64_defs.c
trunk/priv/host_arm_defs.c
trunk/priv/host_mips_defs.c
trunk/priv/host_ppc_defs.c
trunk/priv/host_ppc_isel.c
trunk/priv/host_s390_defs.c
trunk/priv/host_s390_isel.c
trunk/priv/host_tilegx_defs.c
trunk/priv/host_tilegx_isel.c
trunk/priv/host_x86_defs.c
trunk/priv/ir_defs.c
Modified: trunk/priv/guest_amd64_toIR.c
==============================================================================
--- trunk/priv/guest_amd64_toIR.c (original)
+++ trunk/priv/guest_amd64_toIR.c Mon Aug 3 17:03:13 2015
@@ -5420,7 +5420,8 @@
break;
default:
- vex_printf("unhandled opc_aux = 0x%2x\n", gregLO3ofRM(modrm));
+ vex_printf("unhandled opc_aux = 0x%2x\n",
+ (UInt)gregLO3ofRM(modrm));
vex_printf("first_opcode == 0xD8\n");
goto decode_fail;
}
@@ -5439,7 +5440,7 @@
/* Dunno if this is right */
case 0xD0 ... 0xD7: /* FCOM %st(?),%st(0) */
r_dst = (UInt)modrm - 0xD0;
- DIP("fcom %%st(0),%%st(%d)\n", r_dst);
+ DIP("fcom %%st(0),%%st(%u)\n", r_dst);
/* This forces C1 to zero, which isn't right. */
put_C3210(
unop(Iop_32Uto64,
@@ -5454,7 +5455,7 @@
/* Dunno if this is right */
case 0xD8 ... 0xDF: /* FCOMP %st(?),%st(0) */
r_dst = (UInt)modrm - 0xD8;
- DIP("fcomp %%st(0),%%st(%d)\n", r_dst);
+ DIP("fcomp %%st(0),%%st(%u)\n", r_dst);
/* This forces C1 to zero, which isn't right. */
put_C3210(
unop(Iop_32Uto64,
@@ -5679,7 +5680,8 @@
break;
default:
- vex_printf("unhandled opc_aux = 0x%2x\n", gregLO3ofRM(modrm));
+ vex_printf("unhandled opc_aux = 0x%2x\n",
+ (UInt)gregLO3ofRM(modrm));
vex_printf("first_opcode == 0xD9\n");
goto decode_fail;
}
@@ -6078,7 +6080,8 @@
break;
default:
- vex_printf("unhandled opc_aux = 0x%2x\n", gregLO3ofRM(modrm));
+ vex_printf("unhandled opc_aux = 0x%2x\n",
+ (UInt)gregLO3ofRM(modrm));
vex_printf("first_opcode == 0xDA\n");
goto decode_fail;
}
@@ -6242,7 +6245,8 @@
}
default:
- vex_printf("unhandled opc_aux = 0x%2x\n", gregLO3ofRM(modrm));
+ vex_printf("unhandled opc_aux = 0x%2x\n",
+ (UInt)gregLO3ofRM(modrm));
vex_printf("first_opcode == 0xDB\n");
goto decode_fail;
}
@@ -6425,7 +6429,8 @@
break;
default:
- vex_printf("unhandled opc_aux = 0x%2x\n", gregLO3ofRM(modrm));
+ vex_printf("unhandled opc_aux = 0x%2x\n",
+ (UInt)gregLO3ofRM(modrm));
vex_printf("first_opcode == 0xDC\n");
goto decode_fail;
}
@@ -6660,7 +6665,8 @@
}
default:
- vex_printf("unhandled opc_aux = 0x%2x\n", gregLO3ofRM(modrm));
+ vex_printf("unhandled opc_aux = 0x%2x\n",
+ (UInt)gregLO3ofRM(modrm));
vex_printf("first_opcode == 0xDD\n");
goto decode_fail;
}
@@ -6793,7 +6799,8 @@
break;
default:
- vex_printf("unhandled opc_aux = 0x%2x\n", gregLO3ofRM(modrm));
+ vex_printf("unhandled opc_aux = 0x%2x\n",
+ (UInt)gregLO3ofRM(modrm));
vex_printf("first_opcode == 0xDE\n");
goto decode_fail;
}
@@ -6909,7 +6916,8 @@
break;
default:
- vex_printf("unhandled opc_aux = 0x%2x\n", gregLO3ofRM(modrm));
+ vex_printf("unhandled opc_aux = 0x%2x\n",
+ (UInt)gregLO3ofRM(modrm));
vex_printf("first_opcode == 0xDF\n");
goto decode_fail;
}
@@ -7125,7 +7133,7 @@
case 0xFB: op = Iop_Sub64; break;
default:
- vex_printf("\n0x%x\n", (Int)opc);
+ vex_printf("\n0x%x\n", (UInt)opc);
vpanic("dis_MMXop_regmem_to_reg");
}
@@ -9200,8 +9208,8 @@
assign( plain, binop(op, getXMMReg(gregOfRexRM(pfx,rm)),
getXMMReg(eregOfRexRM(pfx,rm))) );
delta += 2;
- DIP("%s $%d,%s,%s\n", opname,
- (Int)imm8,
+ DIP("%s $%u,%s,%s\n", opname,
+ imm8,
nameXMMReg(eregOfRexRM(pfx,rm)),
nameXMMReg(gregOfRexRM(pfx,rm)) );
} else {
@@ -9224,8 +9232,8 @@
)
);
delta += alen+1;
- DIP("%s $%d,%s,%s\n", opname,
- (Int)imm8,
+ DIP("%s $%u,%s,%s\n", opname,
+ imm8,
dis_buf,
nameXMMReg(gregOfRexRM(pfx,rm)) );
}
@@ -11396,8 +11404,8 @@
assign(sV, getXMMReg(rE));
imm8 = getUChar(delta+1) & 7;
delta += 1+1;
- DIP("%spextrw $%d,%s,%s\n", isAvx ? "v" : "",
- (Int)imm8, nameXMMReg(rE), nameIReg32(rG));
+ DIP("%spextrw $%u,%s,%s\n", isAvx ? "v" : "",
+ imm8, nameXMMReg(rE), nameIReg32(rG));
} else {
/* The memory case is disallowed, apparently. */
return deltaIN; /* FAIL */
@@ -13842,7 +13850,7 @@
assign(t4, getIReg16(eregOfRexRM(pfx,modrm)));
delta += 1+1;
lane = getUChar(delta-1);
- DIP("pinsrw $%d,%s,%s\n", (Int)lane,
+ DIP("pinsrw $%d,%s,%s\n", lane,
nameIReg16(eregOfRexRM(pfx,modrm)),
nameMMXReg(gregLO3ofRM(modrm)));
} else {
@@ -13850,7 +13858,7 @@
delta += 1+alen;
lane = getUChar(delta-1);
assign(t4, loadLE(Ity_I16, mkexpr(addr)));
- DIP("pinsrw $%d,%s,%s\n", (Int)lane,
+ DIP("pinsrw $%d,%s,%s\n", lane,
dis_buf,
nameMMXReg(gregLO3ofRM(modrm)));
}
@@ -13879,7 +13887,7 @@
delta += 1+1;
lane = getUChar(delta-1);
DIP("pinsrw $%d,%s,%s\n",
- (Int)lane, nameIReg16(rE), nameXMMReg(rG));
+ lane, nameIReg16(rE), nameXMMReg(rG));
} else {
addr = disAMode ( &alen, vbi, pfx, delta, dis_buf,
1/*byte after the amode*/ );
@@ -13887,7 +13895,7 @@
lane = getUChar(delta-1);
assign(t4, loadLE(Ity_I16, mkexpr(addr)));
DIP("pinsrw $%d,%s,%s\n",
- (Int)lane, dis_buf, nameXMMReg(rG));
+ lane, dis_buf, nameXMMReg(rG));
}
IRTemp src_vec = newTemp(Ity_V128);
assign(src_vec, getXMMReg(rG));
@@ -15895,7 +15903,7 @@
assign( sV, getXMMReg(eregOfRexRM(pfx,modrm)) );
d64 = (Long)getUChar(delta+1);
delta += 1+1;
- DIP("palignr $%d,%s,%s\n", (Int)d64,
+ DIP("palignr $%lld,%s,%s\n", d64,
nameXMMReg(eregOfRexRM(pfx,modrm)),
nameXMMReg(gregOfRexRM(pfx,modrm)));
} else {
@@ -15904,7 +15912,7 @@
assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
d64 = (Long)getUChar(delta+alen);
delta += alen+1;
- DIP("palignr $%d,%s,%s\n", (Int)d64,
+ DIP("palignr $%lld,%s,%s\n", d64,
dis_buf,
nameXMMReg(gregOfRexRM(pfx,modrm)));
}
@@ -15927,7 +15935,7 @@
assign( sV, getMMXReg(eregLO3ofRM(modrm)) );
d64 = (Long)getUChar(delta+1);
delta += 1+1;
- DIP("palignr $%d,%s,%s\n", (Int)d64,
+ DIP("palignr $%lld,%s,%s\n", d64,
nameMMXReg(eregLO3ofRM(modrm)),
nameMMXReg(gregLO3ofRM(modrm)));
} else {
@@ -15935,7 +15943,7 @@
assign( sV, loadLE(Ity_I64, mkexpr(addr)) );
d64 = (Long)getUChar(delta+alen);
delta += alen+1;
- DIP("palignr $%d%s,%s\n", (Int)d64,
+ DIP("palignr $%lld%s,%s\n", d64,
dis_buf,
nameMMXReg(gregLO3ofRM(modrm)));
}
@@ -19846,7 +19854,8 @@
guest_RIP_bbstart+delta, d64 );
vassert(dres->whatNext == Dis_StopHere);
}
- DIP("j%s-8 0x%llx %s\n", name_AMD64Condcode(opc - 0x70), d64, comment);
+ DIP("j%s-8 0x%llx %s\n", name_AMD64Condcode(opc - 0x70), (ULong)d64,
+ comment);
return delta;
}
@@ -20258,7 +20267,7 @@
assign( addr, handleAddrOverrides(vbi, pfx, mkU64(d64)) );
putIRegRAX(sz, loadLE( ty, mkexpr(addr) ));
DIP("mov%c %s0x%llx, %s\n", nameISize(sz),
- segRegTxt(pfx), d64,
+ segRegTxt(pfx), (ULong)d64,
nameIRegRAX(sz));
return delta;
@@ -20276,7 +20285,7 @@
assign( addr, handleAddrOverrides(vbi, pfx, mkU64(d64)) );
storeLE( mkexpr(addr), getIRegRAX(sz) );
DIP("mov%c %s, %s0x%llx\n", nameISize(sz), nameIRegRAX(sz),
- segRegTxt(pfx), d64);
+ segRegTxt(pfx), (ULong)d64);
return delta;
case 0xA4:
@@ -20750,7 +20759,7 @@
}
stmt( IRStmt_Exit(cond, Ijk_Boring, IRConst_U64(d64), OFFB_RIP) );
- DIP("loop%s%s 0x%llx\n", xtra, haveASO(pfx) ? "l" : "", d64);
+ DIP("loop%s%s 0x%llx\n", xtra, haveASO(pfx) ? "l" : "", (ULong)d64);
return delta;
}
@@ -20768,7 +20777,7 @@
IRConst_U64(d64),
OFFB_RIP
));
- DIP("jecxz 0x%llx\n", d64);
+ DIP("jecxz 0x%llx\n", (ULong)d64);
} else {
/* 64-bit */
stmt( IRStmt_Exit( binop(Iop_CmpEQ64,
@@ -20778,7 +20787,7 @@
IRConst_U64(d64),
OFFB_RIP
));
- DIP("jrcxz 0x%llx\n", d64);
+ DIP("jrcxz 0x%llx\n", (ULong)d64);
}
return delta;
@@ -20899,7 +20908,7 @@
jmp_lit(dres, Ijk_Call, d64);
vassert(dres->whatNext == Dis_StopHere);
}
- DIP("call 0x%llx\n",d64);
+ DIP("call 0x%llx\n", (ULong)d64);
return delta;
case 0xE9: /* Jv (jump, 16/32 offset) */
@@ -20916,7 +20925,7 @@
jmp_lit(dres, Ijk_Boring, d64);
vassert(dres->whatNext == Dis_StopHere);
}
- DIP("jmp 0x%llx\n", d64);
+ DIP("jmp 0x%llx\n", (ULong)d64);
return delta;
case 0xEB: /* Jb (jump, byte offset) */
@@ -20933,7 +20942,7 @@
jmp_lit(dres, Ijk_Boring, d64);
vassert(dres->whatNext == Dis_StopHere);
}
- DIP("jmp-8 0x%llx\n", d64);
+ DIP("jmp-8 0x%llx\n", (ULong)d64);
return delta;
case 0xF5: /* CMC */
@@ -21408,7 +21417,8 @@
guest_RIP_bbstart+delta, d64 );
vassert(dres->whatNext == Dis_StopHere);
}
- DIP("j%s-32 0x%llx %s\n", name_AMD64Condcode(opc - 0x80), d64, comment);
+ DIP("j%s-32 0x%llx %s\n", name_AMD64Condcode(opc - 0x80), (ULong)d64,
+ comment);
return delta;
}
@@ -22915,8 +22925,8 @@
UInt rE = eregOfRexRM(pfx,rm);
assign(argR, getXMMReg(rE));
delta += 1+1;
- DIP("%s $%d,%s,%s,%s\n",
- opname, (Int)imm8,
+ DIP("%s $%u,%s,%s,%s\n",
+ opname, imm8,
nameXMMReg(rE), nameXMMReg(rV), nameXMMReg(rG));
} else {
addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
@@ -22928,8 +22938,8 @@
: sz == 8 ? unop( Iop_64UtoV128, loadLE(Ity_I64, mkexpr(addr)))
: /*sz==4*/ unop( Iop_32UtoV128, loadLE(Ity_I32, mkexpr(addr))));
delta += alen+1;
- DIP("%s $%d,%s,%s,%s\n",
- opname, (Int)imm8, dis_buf, nameXMMReg(rV), nameXMMReg(rG));
+ DIP("%s $%u,%s,%s,%s\n",
+ opname, imm8, dis_buf, nameXMMReg(rV), nameXMMReg(rG));
}
assign(plain, preSwap ? binop(op, mkexpr(argR), mkexpr(argL))
@@ -23030,8 +23040,8 @@
UInt rE = eregOfRexRM(pfx,rm);
assign(argR, getYMMReg(rE));
delta += 1+1;
- DIP("%s $%d,%s,%s,%s\n",
- opname, (Int)imm8,
+ DIP("%s $%u,%s,%s,%s\n",
+ opname, imm8,
nameYMMReg(rE), nameYMMReg(rV), nameYMMReg(rG));
} else {
addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 1 );
@@ -23041,8 +23051,8 @@
if (!ok) return deltaIN; /* FAIL */
assign(argR, loadLE(Ity_V256, mkexpr(addr)) );
delta += alen+1;
- DIP("%s $%d,%s,%s,%s\n",
- opname, (Int)imm8, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
+ DIP("%s $%u,%s,%s,%s\n",
+ opname, imm8, dis_buf, nameYMMReg(rV), nameYMMReg(rG));
}
breakupV256toV128s( preSwap ? argR : argL, &argLhi, &argLlo );
@@ -30511,14 +30521,14 @@
assign( sV, getXMMReg(rE) );
imm8 = getUChar(delta+1);
delta += 1+1;
- DIP("vpalignr $%d,%s,%s,%s\n", imm8, nameXMMReg(rE),
+ DIP("vpalignr $%u,%s,%s,%s\n", imm8, nameXMMReg(rE),
nameXMMReg(rV), nameXMMReg(rG));
} else {
addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
assign( sV, loadLE(Ity_V128, mkexpr(addr)) );
imm8 = getUChar(delta+alen);
delta += alen+1;
- DIP("vpalignr $%d,%s,%s,%s\n", imm8, dis_buf,
+ DIP("vpalignr $%u,%s,%s,%s\n", imm8, dis_buf,
nameXMMReg(rV), nameXMMReg(rG));
}
@@ -30546,14 +30556,14 @@
assign( sV, getYMMReg(rE) );
imm8 = getUChar(delta+1);
delta += 1+1;
- DIP("vpalignr $%d,%s,%s,%s\n", imm8, nameYMMReg(rE),
+ DIP("vpalignr $%u,%s,%s,%s\n", imm8, nameYMMReg(rE),
nameYMMReg(rV), nameYMMReg(rG));
} else {
addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
assign( sV, loadLE(Ity_V256, mkexpr(addr)) );
imm8 = getUChar(delta+alen);
delta += alen+1;
- DIP("vpalignr $%d,%s,%s,%s\n", imm8, dis_buf,
+ DIP("vpalignr $%u,%s,%s,%s\n", imm8, dis_buf,
nameYMMReg(rV), nameYMMReg(rG));
}
@@ -31867,14 +31877,14 @@
if (sigill_diag) {
vex_printf("vex amd64->IR: unhandled instruction bytes: "
"0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
- (Int)getUChar(delta_start+0),
- (Int)getUChar(delta_start+1),
- (Int)getUChar(delta_start+2),
- (Int)getUChar(delta_start+3),
- (Int)getUChar(delta_start+4),
- (Int)getUChar(delta_start+5),
- (Int)getUChar(delta_start+6),
- (Int)getUChar(delta_start+7) );
+ getUChar(delta_start+0),
+ getUChar(delta_start+1),
+ getUChar(delta_start+2),
+ getUChar(delta_start+3),
+ getUChar(delta_start+4),
+ getUChar(delta_start+5),
+ getUChar(delta_start+6),
+ getUChar(delta_start+7) );
vex_printf("vex amd64->IR: REX=%d REX.W=%d REX.R=%d REX.X=%d REX.B=%d\n",
haveREX(pfx) ? 1 : 0, getRexW(pfx), getRexR(pfx),
getRexX(pfx), getRexB(pfx));
Modified: trunk/priv/guest_arm64_toIR.c
==============================================================================
--- trunk/priv/guest_arm64_toIR.c (original)
+++ trunk/priv/guest_arm64_toIR.c Mon Aug 3 17:03:13 2015
@@ -5141,7 +5141,7 @@
vassert(0);
}
putIReg64orSP(nn, mkexpr(tEA));
- DIP(atRN ? "ldrs%c %s, [%s], #%lld\n" : "ldrs%c %s, [%s, #%lld]!",
+ DIP(atRN ? "ldrs%c %s, [%s], #%llu\n" : "ldrs%c %s, [%s, #%llu]!",
ch, nameIRegOrZR(is64, tt), nameIReg64orSP(nn), simm9);
return True;
}
@@ -5216,7 +5216,7 @@
vassert(0);
}
DIP("ldurs%c %s, [%s, #%lld]",
- ch, nameIRegOrZR(is64, tt), nameIReg64orSP(nn), simm9);
+ ch, nameIRegOrZR(is64, tt), nameIReg64orSP(nn), (Long)simm9);
return True;
}
/* else fall through */
@@ -5575,7 +5575,7 @@
putIReg64orSP(nn, mkexpr(tEA));
DIP(atRN ? "%s %s, [%s], #%lld\n" : "%s %s, [%s, #%lld]!\n",
isLD ? "ldr" : "str",
- nameQRegLO(tt, ty), nameIReg64orSP(nn), simm9);
+ nameQRegLO(tt, ty), nameIReg64orSP(nn), (Long)simm9);
return True;
}
@@ -8275,7 +8275,7 @@
putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, res));
const HChar* Ta = bitQ ==1 ? "16b" : "8b";
const HChar* nm = isTBX ? "tbx" : "tbl";
- DIP("%s %s.%s, {v%d.16b .. v%d.16b}, %s.%s\n",
+ DIP("%s %s.%s, {v%u.16b .. v%u.16b}, %s.%s\n",
nm, nameQReg128(dd), Ta, nn, (nn + len) % 32, nameQReg128(mm), Ta);
return True;
}
@@ -9495,7 +9495,7 @@
: (ks == 1 ? "sqdmlal" : "sqdmlsl");
const HChar arrNarrow = "bhsd"[size];
const HChar arrWide = "bhsd"[size+1];
- DIP("%s %c%d, %c%d, %c%d\n",
+ DIP("%s %c%u, %c%u, %c%u\n",
nm, arrWide, dd, arrNarrow, nn, arrNarrow, mm);
return True;
}
@@ -9705,7 +9705,7 @@
math_ZERO_ALL_EXCEPT_LOWEST_LANE(size, mkexpr(sat1n)));
const HChar arr = "bhsd"[size];
const HChar* nm = isR ? "sqrdmulh" : "sqdmulh";
- DIP("%s %c%d, %c%d, %c%d\n", nm, arr, dd, arr, nn, arr, mm);
+ DIP("%s %c%u, %c%u, %c%u\n", nm, arr, dd, arr, nn, arr, mm);
return True;
}
@@ -10267,7 +10267,7 @@
: (ks == 1 ? "sqdmlal" : "sqdmlsl");
const HChar arrNarrow = "bhsd"[size];
const HChar arrWide = "bhsd"[size+1];
- DIP("%s %c%d, %c%d, v%d.%c[%u]\n",
+ DIP("%s %c%u, %c%u, v%u.%c[%u]\n",
nm, arrWide, dd, arrNarrow, nn, dd, arrNarrow, ix);
return True;
}
@@ -10302,7 +10302,7 @@
updateQCFLAGwithDifferenceZHI(sat1q, sat1n, opZHI);
const HChar* nm = isR ? "sqrdmulh" : "sqdmulh";
HChar ch = size == X01 ? 'h' : 's';
- DIP("%s %c%d, %c%d, v%d.%c[%u]\n", nm, ch, dd, ch, nn, ch, dd, ix);
+ DIP("%s %c%u, %c%u, v%d.%c[%u]\n", nm, ch, dd, ch, nn, ch, (Int)dd, ix);
return True;
}
@@ -10698,7 +10698,7 @@
/* */
if (res) {
putQReg128(dd, res);
- DIP("%cshll%s %s.%s, %s.%s, #%d\n",
+ DIP("%cshll%s %s.%s, %s.%s, #%u\n",
isU ? 'u' : 's', isQ ? "2" : "",
nameQReg128(dd), ta, nameQReg128(nn), tb, sh);
return True;
@@ -12168,7 +12168,7 @@
putQReg128(dd, mkexpr(res));
const HChar* arrNarrow = nameArr_Q_SZ(bitQ, size);
const HChar* arrWide = nameArr_Q_SZ(1, size+1);
- DIP("shll%s %s.%s, %s.%s, #%u\n", is2 ? "2" : "",
+ DIP("shll%s %s.%s, %s.%s, #%d\n", is2 ? "2" : "",
nameQReg128(dd), arrWide, nameQReg128(nn), arrNarrow, 8 << size);
return True;
}
Modified: trunk/priv/guest_arm_toIR.c
==============================================================================
--- trunk/priv/guest_arm_toIR.c (original)
+++ trunk/priv/guest_arm_toIR.c Mon Aug 3 17:03:13 2015
@@ -2870,7 +2870,7 @@
putDRegI64(dreg, triop(Iop_Slice64, /*hiI64*/getDRegI64(mreg),
/*loI64*/getDRegI64(nreg), mkU8(imm4)), condT);
}
- DIP("vext.8 %c%d, %c%d, %c%d, #%d\n", reg_t, dreg, reg_t, nreg,
+ DIP("vext.8 %c%u, %c%u, %c%u, #%u\n", reg_t, dreg, reg_t, nreg,
reg_t, mreg, imm4);
return True;
}
@@ -3030,7 +3030,7 @@
} else {
putDRegI64(dreg, mkexpr(res), condT);
}
- DIP("vdup.%d %c%d, d%d[%d]\n", size, Q ? 'q' : 'd', dreg, mreg, index);
+ DIP("vdup.%u %c%u, d%u[%u]\n", size, Q ? 'q' : 'd', dreg, mreg, index);
return True;
}
@@ -3137,7 +3137,7 @@
binop(andOp, mkexpr(arg_m), imm_val),
binop(andOp, mkexpr(arg_n), imm_val)),
mkU8(1))));
- DIP("vhadd.%c%d %c%d, %c%d, %c%d\n",
+ DIP("vhadd.%c%d %c%u, %c%u, %c%u\n",
U ? 'u' : 's', 8 << size, regType,
dreg, regType, nreg, regType, mreg);
} else {
@@ -3196,7 +3196,7 @@
assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
assign(tmp, binop(op2, mkexpr(arg_n), mkexpr(arg_m)));
setFlag_QC(mkexpr(res), mkexpr(tmp), Q, condT);
- DIP("vqadd.%c%d %c%d, %c%d, %c%d\n",
+ DIP("vqadd.%c%d %c%u %c%u, %c%u\n",
U ? 'u' : 's',
8 << size, reg_t, dreg, reg_t, nreg, reg_t, mreg);
}
@@ -3307,7 +3307,7 @@
mkU8(1))),
mkexpr(cc)));
}
- DIP("vrhadd.%c%d %c%d, %c%d, %c%d\n",
+ DIP("vrhadd.%c%d %c%u, %c%u, %c%u\n",
U ? 'u' : 's',
8 << size, reg_t, dreg, reg_t, nreg, reg_t, mreg);
} else {
@@ -3323,7 +3323,7 @@
assign(res, binop(Iop_And64, mkexpr(arg_n),
mkexpr(arg_m)));
}
- DIP("vand %c%d, %c%d, %c%d\n",
+ DIP("vand %c%u, %c%u, %c%u\n",
reg_t, dreg, reg_t, nreg, reg_t, mreg);
break;
}
@@ -3337,7 +3337,7 @@
assign(res, binop(Iop_And64, mkexpr(arg_n),
unop(Iop_Not64, mkexpr(arg_m))));
}
- DIP("vbic %c%d, %c%d, %c%d\n",
+ DIP("vbic %c%u, %c%u, %c%u\n",
reg_t, dreg, reg_t, nreg, reg_t, mreg);
break;
}
@@ -3352,13 +3352,13 @@
assign(res, binop(Iop_Or64, mkexpr(arg_n),
mkexpr(arg_m)));
}
- DIP("vorr %c%d, %c%d, %c%d\n",
+ DIP("vorr %c%u, %c%u, %c%u\n",
reg_t, dreg, reg_t, nreg, reg_t, mreg);
} else {
/* VMOV */
HChar reg_t = Q ? 'q' : 'd';
assign(res, mkexpr(arg_m));
- DIP("vmov %c%d, %c%d\n", reg_t, dreg, reg_t, mreg);
+ DIP("vmov %c%u, %c%u\n", reg_t, dreg, reg_t, mreg);
}
break;
case 3:{
@@ -3371,7 +3371,7 @@
assign(res, binop(Iop_Or64, mkexpr(arg_n),
unop(Iop_Not64, mkexpr(arg_m))));
}
- DIP("vorn %c%d, %c%d, %c%d\n",
+ DIP("vorn %c%u, %c%u, %c%u\n",
reg_t, dreg, reg_t, nreg, reg_t, mreg);
break;
}
@@ -3548,7 +3548,7 @@
unop(notOp, mkexpr(arg_n)),
mkexpr(arg_m)),
imm_val)));
- DIP("vhsub.%c%u %c%u, %c%u, %c%u\n",
+ DIP("vhsub.%c%d %c%u, %c%u, %c%u\n",
U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
mreg);
@@ -3606,7 +3606,7 @@
assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
assign(tmp, binop(op2, mkexpr(arg_n), mkexpr(arg_m)));
setFlag_QC(mkexpr(res), mkexpr(tmp), Q, condT);
- DIP("vqsub.%c%u %c%u, %c%u, %c%u\n",
+ DIP("vqsub.%c%d %c%u, %c%u, %c%u\n",
U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
mreg);
@@ -3634,7 +3634,7 @@
if (B == 0) {
/* VCGT */
assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
- DIP("vcgt.%c%u %c%u, %c%u, %c%u\n",
+ DIP("vcgt.%c%d %c%u, %c%u, %c%u\n",
U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
mreg);
@@ -3647,7 +3647,7 @@
assign(res,
unop(Q ? Iop_NotV128 : Iop_Not64,
binop(op, mkexpr(arg_m), mkexpr(arg_n))));
- DIP("vcge.%c%u %c%u, %c%u, %c%u\n",
+ DIP("vcge.%c%d %c%u, %c%u, %c%u\n",
U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
mreg);
@@ -3709,7 +3709,7 @@
else
assign(res, binop(op, mkexpr(arg_m), mkexpr(tmp)));
}
- DIP("vshl.%c%u %c%u, %c%u, %c%u\n",
+ DIP("vshl.%c%d %c%u, %c%u, %c%u\n",
U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, Q ? 'q' : 'd',
nreg);
@@ -3833,7 +3833,7 @@
binop(Q ? Iop_AndV128 : Iop_And64,
mkexpr(arg_m), mkexpr(mask)),
Q, condT);
- DIP("vqshl.%c%u %c%u, %c%u, %c%u\n",
+ DIP("vqshl.%c%d %c%u, %c%u, %c%u\n",
U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, Q ? 'q' : 'd',
nreg);
@@ -3973,7 +3973,7 @@
binop(op, mkexpr(arg_m), mkexpr(arg_n)),
mkexpr(round)));
}
- DIP("vrshl.%c%u %c%u, %c%u, %c%u\n",
+ DIP("vrshl.%c%d %c%u, %c%u, %c%u\n",
U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, Q ? 'q' : 'd',
nreg);
@@ -4130,7 +4130,7 @@
binop(Q ? Iop_AndV128 : Iop_And64,
mkexpr(arg_m), mkexpr(mask)),
Q, condT);
- DIP("vqrshl.%c%u %c%u, %c%u, %c%u\n",
+ DIP("vqrshl.%c%d %c%u, %c%u, %c%u\n",
U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, Q ? 'q' : 'd',
nreg);
@@ -4159,7 +4159,7 @@
}
}
assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
- DIP("vmax.%c%u %c%u, %c%u, %c%u\n",
+ DIP("vmax.%c%d %c%u, %c%u, %c%u\n",
U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
mreg);
@@ -4184,7 +4184,7 @@
}
}
assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
- DIP("vmin.%c%u %c%u, %c%u, %c%u\n",
+ DIP("vmin.%c%d %c%u, %c%u, %c%u\n",
U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
mreg);
@@ -4253,7 +4253,7 @@
mkexpr(arg_n)),
unop(Q ? Iop_NotV128 : Iop_Not64,
mkexpr(cond)))));
- DIP("vabd.%c%u %c%u, %c%u, %c%u\n",
+ DIP("vabd.%c%d %c%u, %c%u, %c%u\n",
U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
mreg);
@@ -4332,7 +4332,7 @@
unop(Q ? Iop_NotV128 : Iop_Not64,
mkexpr(cond)))));
assign(res, binop(op_add, mkexpr(acc), mkexpr(tmp)));
- DIP("vaba.%c%u %c%u, %c%u, %c%u\n",
+ DIP("vaba.%c%d %c%u, %c%u, %c%u\n",
U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
mreg);
@@ -4350,7 +4350,7 @@
case 3: op = Q ? Iop_Add64x2 : Iop_Add64; break;
default: vassert(0);
}
- DIP("vadd.i%u %c%u, %c%u, %c%u\n",
+ DIP("vadd.i%d %c%u, %c%u, %c%u\n",
8 << size, Q ? 'q' : 'd',
dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
} else {
@@ -4362,7 +4362,7 @@
case 3: op = Q ? Iop_Sub64x2 : Iop_Sub64; break;
default: vassert(0);
}
- DIP("vsub.i%u %c%u, %c%u, %c%u\n",
+ DIP("vsub.i%d %c%u, %c%u, %c%u\n",
8 << size, Q ? 'q' : 'd',
dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
}
@@ -4381,7 +4381,7 @@
assign(res, unop(op, binop(Q ? Iop_AndV128 : Iop_And64,
mkexpr(arg_n),
mkexpr(arg_m))));
- DIP("vtst.%u %c%u, %c%u, %c%u\n",
+ DIP("vtst.%d %c%u, %c%u, %c%u\n",
8 << size, Q ? 'q' : 'd',
dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
} else {
@@ -4391,7 +4391,7 @@
binop(Q ? Iop_XorV128 : Iop_Xor64,
mkexpr(arg_n),
mkexpr(arg_m)))));
- DIP("vceq.i%u %c%u, %c%u, %c%u\n",
+ DIP("vceq.i%d %c%u, %c%u, %c%u\n",
8 << size, Q ? 'q' : 'd',
dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
}
@@ -4444,7 +4444,7 @@
assign(res, binop(op2,
Q ? getQReg(dreg) : getDRegI64(dreg),
binop(op, mkexpr(arg_n), mkexpr(arg_m))));
- DIP("vml%c.i%u %c%u, %c%u, %c%u\n",
+ DIP("vml%c.i%d %c%u, %c%u, %c%u\n",
P ? 's' : 'a', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
mreg);
@@ -4470,7 +4470,7 @@
}
}
assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
- DIP("vmul.%c%u %c%u, %c%u, %c%u\n",
+ DIP("vmul.%c%d %c%u, %c%u, %c%u\n",
P ? 'p' : 'i', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
mreg);
@@ -4500,7 +4500,7 @@
}
}
assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
- DIP("vp%s.%c%u %c%u, %c%u, %c%u\n",
+ DIP("vp%s.%c%d %c%u, %c%u, %c%u\n",
P ? "min" : "max", U ? 'u' : 's',
8 << size, Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg,
Q ? 'q' : 'd', mreg);
@@ -4539,7 +4539,7 @@
Q ? mkU128(imm) : mkU64(imm))),
Q ? mkU128(0) : mkU64(0),
Q, condT);
- DIP("vqdmulh.s%u %c%u, %c%u, %c%u\n",
+ DIP("vqdmulh.s%d %c%u, %c%u, %c%u\n",
8 << size, Q ? 'q' : 'd',
dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
} else {
@@ -4573,7 +4573,7 @@
Q ? mkU128(imm) : mkU64(imm))),
Q ? mkU128(0) : mkU64(0),
Q, condT);
- DIP("vqrdmulh.s%u %c%u, %c%u, %c%u\n",
+ DIP("vqrdmulh.s%d %c%u, %c%u, %c%u\n",
8 << size, Q ? 'q' : 'd',
dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
}
@@ -4874,7 +4874,7 @@
assign(arg_m, unop(cvt, getDRegI64(mreg)));
putQReg(dreg, binop(op, mkexpr(arg_n), mkexpr(arg_m)),
condT);
- DIP("v%s%c.%c%u q%u, %c%u, d%u\n", (A & 2) ? "sub" : "add",
+ DIP("v%s%c.%c%d q%u, %c%u, d%u\n", (A & 2) ? "sub" : "add",
(A & 1) ? 'w' : 'l', U ? 'u' : 's', 8 << size, dreg,
(A & 1) ? 'q' : 'd', nreg, mreg);
return True;
@@ -4926,7 +4926,7 @@
}
putDRegI64(dreg, unop(cvt, binop(sh, mkexpr(res), mkU8(8 << size))),
condT);
- DIP("v%saddhn.i%u d%u, q%u, q%u\n", U ? "r" : "", 16 << size, dreg,
+ DIP("v%saddhn.i%d d%u, q%u, q%u\n", U ? "r" : "", 16 << size, dreg,
nreg, mreg);
return True;
case 5:
@@ -4982,7 +4982,7 @@
unop(Iop_NotV128, mkexpr(cond)))),
getQReg(dreg)));
putQReg(dreg, mkexpr(res), condT);
- DIP("vabal.%c%u q%u, d%u, d%u\n", U ? 'u' : 's', 8 << size, dreg,
+ DIP("vabal.%c%d q%u, d%u, d%u\n", U ? 'u' : 's', 8 << size, dreg,
nreg, mreg);
return True;
case 6:
@@ -5036,7 +5036,7 @@
}
putDRegI64(dreg, unop(cvt, binop(sh, mkexpr(res), mkU8(8 << size))),
condT);
- DIP("v%ssubhn.i%u d%u, q%u, q%u\n", U ? "r" : "", 16 << size, dreg,
+ DIP("v%ssubhn.i%d d%u, q%u, q%u\n", U ? "r" : "", 16 << size, dreg,
nreg, mreg);
return True;
case 7:
@@ -5087,7 +5087,7 @@
binop(op, mkexpr(arg_m), mkexpr(arg_n)),
unop(Iop_NotV128, mkexpr(cond)))));
putQReg(dreg, mkexpr(res), condT);
- DIP("vabdl.%c%u q%u, d%u, d%u\n", U ? 'u' : 's', 8 << size, dreg,
+ DIP("vabdl.%c%d q%u, d%u, d%u\n", U ? 'u' : 's', 8 << size, dreg,
nreg, mreg);
return True;
case 8:
@@ -5118,7 +5118,7 @@
res = newTemp(Ity_V128);
assign(res, binop(op, getDRegI64(nreg),getDRegI64(mreg)));
putQReg(dreg, binop(op2, getQReg(dreg), mkexpr(res)), condT);
- DIP("vml%cl.%c%u q%u, d%u, d%u\n", P ? 's' : 'a', U ? 'u' : 's',
+ DIP("vml%cl.%c%d q%u, d%u, d%u\n", P ? 's' : 'a', U ? 'u' : 's',
8 << size, dreg, nreg, mreg);
return True;
case 9:
@@ -5165,7 +5165,7 @@
mkU64(0),
False, condT);
putQReg(dreg, binop(add, getQReg(dreg), mkexpr(res)), condT);
- DIP("vqdml%cl.s%u q%u, d%u, d%u\n", P ? 's' : 'a', 8 << size, dreg,
+ DIP("vqdml%cl.s%d q%u, d%u, d%u\n", P ? 's' : 'a', 8 << size, dreg,
nreg, mreg);
return True;
case 12:
@@ -5192,7 +5192,7 @@
}
putQReg(dreg, binop(op, getDRegI64(nreg),
getDRegI64(mreg)), condT);
- DIP("vmull.%c%u q%u, d%u, d%u\n", P ? 'p' : (U ? 'u' : 's'),
+ DIP("vmull.%c%d q%u, d%u, d%u\n", P ? 'p' : (U ? 'u' : 's'),
8 << size, dreg, nreg, mreg);
return True;
case 13:
@@ -5230,7 +5230,7 @@
binop(op2, getDRegI64(mreg), mkU64(imm))),
mkU64(0),
False, condT);
- DIP("vqdmull.s%u q%u, d%u, d%u\n", 8 << size, dreg, nreg, mreg);
+ DIP("vqdmull.s%d q%u, d%u, d%u\n", 8 << size, dreg, nreg, mreg);
return True;
default:
return False;
@@ -5355,7 +5355,7 @@
else
putDRegI64(dreg, binop(op2, getDRegI64(dreg), mkexpr(res)),
condT);
- DIP("vml%c.%c%u %c%u, %c%u, d%u[%u]\n", INSN(10,10) ? 's' : 'a',
+ DIP("vml%c.%c%d %c%u, %c%u, d%u[%u]\n", INSN(10,10) ? 's' : 'a',
INSN(8,8) ? 'f' : 'i', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, mreg, index);
return True;
@@ -5412,7 +5412,7 @@
op2 = INSN(10,10) ? sub : add;
assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
putQReg(dreg, binop(op2, getQReg(dreg), mkexpr(res)), condT);
- DIP("vml%cl.%c%u q%u, d%u, d%u[%u]\n",
+ DIP("vml%cl.%c%d q%u, d%u, d%u[%u]\n",
INSN(10,10) ? 's' : 'a', U ? 'u' : 's',
8 << size, dreg, nreg, mreg, index);
return True;
@@ -5487,7 +5487,7 @@
setFlag_QC(mkexpr(tmp), binop(add, getQReg(dreg), mkexpr(res)),
True, condT);
putQReg(dreg, binop(add, getQReg(dreg), mkexpr(res)), condT);
- DIP("vqdml%cl.s%u q%u, d%u, d%u[%u]\n", P ? 's' : 'a', 8 << size,
+ DIP("vqdml%cl.s%d q%u, d%u, d%u[%u]\n", P ? 's' : 'a', 8 << size,
dreg, nreg, mreg, index);
return True;
}
@@ -5583,7 +5583,7 @@
putQReg(dreg, mkexpr(res), condT);
else
putDRegI64(dreg, mkexpr(res), condT);
- DIP("vmul.%c%u %c%u, %c%u, d%u[%u]\n", INSN(8,8) ? 'f' : 'i',
+ DIP("vmul.%c%d %c%u, %c%u, d%u[%u]\n", INSN(8,8) ? 'f' : 'i',
8 << size, Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', nreg, mreg, index);
return True;
@@ -5628,7 +5628,7 @@
}
assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
putQReg(dreg, mkexpr(res), condT);
- DIP("vmull.%c%u q%u, d%u, d%u[%u]\n", U ? 'u' : 's', 8 << size, dreg,
+ DIP("vmull.%c%d q%u, d%u, d%u[%u]\n", U ? 'u' : 's', 8 << size, dreg,
nreg, mreg, index);
return True;
}
@@ -5691,7 +5691,7 @@
binop(op2, mkexpr(arg_m), mkU64(imm))),
mkU64(0),
False, condT);
- DIP("vqdmull.s%u q%u, d%u, d%u[%u]\n", 8 << size, dreg, nreg, mreg,
+ DIP("vqdmull.s%d q%u, d%u, d%u[%u]\n", 8 << size, dreg, nreg, mreg,
index);
return True;
}
@@ -5788,7 +5788,7 @@
putQReg(dreg, mkexpr(res), condT);
else
putDRegI64(dreg, mkexpr(res), condT);
- DIP("vqdmulh.s%u %c%u, %c%u, d%u[%u]\n",
+ DIP("vqdmulh.s%d %c%u, %c%u, d%u[%u]\n",
8 << size, Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', nreg, mreg, index);
return True;
@@ -5886,7 +5886,7 @@
putQReg(dreg, mkexpr(res), condT);
else
putDRegI64(dreg, mkexpr(res), condT);
- DIP("vqrdmulh.s%u %c%u, %c%u, d%u[%u]\n",
+ DIP("vqrdmulh.s%d %c%u, %c%u, d%u[%u]\n",
8 << size, Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', nreg, mreg, index);
return True;
@@ -6036,7 +6036,7 @@
putDRegI64(dreg, binop(add, mkexpr(res), getDRegI64(dreg)),
condT);
}
- DIP("vrsra.%c%u %c%u, %c%u, #%u\n",
+ DIP("vrsra.%c%d %c%u, %c%u, #%u\n",
U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm);
} else {
@@ -6045,7 +6045,7 @@
} else {
putDRegI64(dreg, mkexpr(res), condT);
}
- DIP("vrshr.%c%u %c%u, %c%u, #%u\n", U ? 'u' : 's', 8 << size,
+ DIP("vrshr.%c%d %c%u, %c%u, #%u\n", U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm);
}
return True;
@@ -6113,7 +6113,7 @@
putDRegI64(dreg, binop(add, mkexpr(res), getDRegI64(dreg)),
condT);
}
- DIP("vsra.%c%u %c%u, %c%u, #%u\n", U ? 'u' : 's', 8 << size,
+ DIP("vsra.%c%d %c%u, %c%u, #%u\n", U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm);
} else {
if (Q) {
@@ -6121,7 +6121,7 @@
} else {
putDRegI64(dreg, mkexpr(res), condT);
}
- DIP("vshr.%c%u %c%u, %c%u, #%u\n", U ? 'u' : 's', 8 << size,
+ DIP("vshr.%c%d %c%u, %c%u, #%u\n", U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm);
}
return True;
@@ -6170,7 +6170,7 @@
mkU8(shift_imm))));
putDRegI64(dreg, mkexpr(res), condT);
}
- DIP("vsri.%u %c%u, %c%u, #%u\n",
+ DIP("vsri.%d %c%u, %c%u, #%u\n",
8 << size, Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', mreg, shift_imm);
return True;
@@ -6219,7 +6219,7 @@
mkU8(shift_imm))));
putDRegI64(dreg, mkexpr(res), condT);
}
- DIP("vsli.%u %c%u, %c%u, #%u\n",
+ DIP("vsli.%d %c%u, %c%u, #%u\n",
8 << size, Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', mreg, shift_imm);
return True;
@@ -6245,7 +6245,7 @@
} else {
putDRegI64(dreg, mkexpr(res), condT);
}
- DIP("vshl.i%u %c%u, %c%u, #%u\n",
+ DIP("vshl.i%d %c%u, %c%u, #%u\n",
8 << size, Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', mreg, shift_imm);
return True;
@@ -6277,7 +6277,7 @@
default:
vassert(0);
}
- DIP("vqshl.u%u %c%u, %c%u, #%u\n",
+ DIP("vqshl.u%d %c%u, %c%u, #%u\n",
8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm);
} else {
@@ -6301,7 +6301,7 @@
default:
vassert(0);
}
- DIP("vqshlu.s%u %c%u, %c%u, #%u\n",
+ DIP("vqshlu.s%d %c%u, %c%u, #%u\n",
8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm);
}
@@ -6328,7 +6328,7 @@
default:
vassert(0);
}
- DIP("vqshl.s%u %c%u, %c%u, #%u\n",
+ DIP("vqshl.s%d %c%u, %c%u, #%u\n",
8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm);
}
@@ -6388,7 +6388,7 @@
mkexpr(reg_m),
mkU8(shift_imm))));
putDRegI64(dreg, mkexpr(res), condT);
- DIP("vshrn.i%u d%u, q%u, #%u\n", 8 << size, dreg, mreg,
+ DIP("vshrn.i%d d%u, q%u, #%u\n", 8 << size, dreg, mreg,
shift_imm);
return True;
} else {
@@ -6438,10 +6438,10 @@
imm_val))));
putDRegI64(dreg, mkexpr(res), condT);
if (shift_imm == 0) {
- DIP("vmov%u d%u, q%u, #%u\n", 8 << size, dreg, mreg,
+ DIP("vmov%d d%u, q%u, #%u\n", 8 << size, dreg, mreg,
shift_imm);
} else {
- DIP("vrshrn.i%u d%u, q%u, #%u\n", 8 << size, dreg, mreg,
+ DIP("vrshrn.i%d d%u, q%u, #%u\n", 8 << size, dreg, mreg,
shift_imm);
}
return True;
@@ -6476,7 +6476,7 @@
default:
vassert(0);
}
- DIP("vq%sshrn.%c%u d%u, q%u, #%u\n", B ? "r" : "",
+ DIP("vq%sshrn.%c%d d%u, q%u, #%u\n", B ? "r" : "",
U ? 'u' : 's', 8 << size, dreg, mreg, shift_imm);
} else {
vassert(U);
@@ -6499,7 +6499,7 @@
default:
vassert(0);
}
- DIP("vq%sshrun.s%u d%u, q%u, #%u\n", B ? "r" : "",
+ DIP("vq%sshrun.s%d d%u, q%u, #%u\n", B ? "r" : "",
8 << size, dreg, mreg, shift_imm);
}
if (B) {
@@ -6570,10 +6570,10 @@
assign(res, binop(op, unop(cvt, getDRegI64(mreg)), mkU8(shift_imm)));
putQReg(dreg, mkexpr(res), condT);
if (shift_imm == 0) {
- DIP("vmovl.%c%u q%u, d%u\n", U ? 'u' : 's', 8 << size,
+ DIP("vmovl.%c%d q%u, d%u\n", U ? 'u' : 's', 8 << size,
dreg, mreg);
} else {
- DIP("vshll.%c%u q%u, d%u, #%u\n", U ? 'u' : 's', 8 << size,
+ DIP("vshll.%c%d q%u, d%u, #%u\n", U ? 'u' : 's', 8 << size,
dreg, mreg, shift_imm);
}
return True;
@@ -6662,7 +6662,7 @@
vassert(0);
}
assign(res, unop(op, mkexpr(arg_m)));
- DIP("vrev64.%u %c%u, %c%u\n", 8 << size,
+ DIP("vrev64.%d %c%u, %c%u\n", 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
break;
}
@@ -6683,7 +6683,7 @@
vassert(0);
}
assign(res, unop(op, mkexpr(arg_m)));
- DIP("vrev32.%u %c%u, %c%u\n", 8 << size,
+ DIP("vrev32.%d %c%u, %c%u\n", 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
break;
}
@@ -6702,7 +6702,7 @@
vassert(0);
}
assign(res, unop(op, mkexpr(arg_m)));
- DIP("vrev16.%u %c%u, %c%u\n", 8 << size,
+ DIP("vrev16.%d %c%u, %c%u\n", 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
break;
}
@@ -6731,7 +6731,7 @@
}
}
assign(res, unop(op, mkexpr(arg_m)));
- DIP("vpaddl.%c%u %c%u, %c%u\n", U ? 'u' : 's', 8 << size,
+ DIP("vpaddl.%c%d %c%u, %c%u\n", U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
break;
}
@@ -6749,7 +6749,7 @@
default: vassert(0);
}
assign(res, unop(op, mkexpr(arg_m)));
- DIP("vcls.s%u %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg,
+ DIP("vcls.s%d %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', mreg);
break;
}
@@ -6764,7 +6764,7 @@
default: vassert(0);
}
assign(res, unop(op, mkexpr(arg_m)));
- DIP("vclz.i%u %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg,
+ DIP("vclz.i%d %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', mreg);
break;
}
@@ -6836,7 +6836,7 @@
}
assign(res, binop(add_op, unop(op, mkexpr(arg_m)),
mkexpr(arg_d)));
- DIP("vpadal.%c%u %c%u, %c%u\n", U ? 'u' : 's', 8 << size,
+ DIP("vpadal.%c%d %c%u, %c%u\n", U ? 'u' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
break;
}
@@ -6898,7 +6898,7 @@
mkexpr(mask)),
neg2)));
setFlag_QC(mkexpr(res), mkexpr(tmp), Q, condT);
- DIP("vqabs.s%u %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg,
+ DIP("vqabs.s%d %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', mreg);
break;
}
@@ -6932,7 +6932,7 @@
assign(res, binop(op, zero, mkexpr(arg_m)));
setFlag_QC(mkexpr(res), binop(op2, zero, mkexpr(arg_m)),
Q, condT);
- DIP("vqneg.s%u %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg,
+ DIP("vqneg.s%d %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', mreg);
break;
}
@@ -6981,7 +6981,7 @@
}
}
assign(res, binop(op, mkexpr(arg_m), zero));
- DIP("vcgt.%c%u %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size,
+ DIP("vcgt.%c%d %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
break;
}
@@ -7012,7 +7012,7 @@
assign(res, unop(Q ? Iop_NotV128 : Iop_Not64,
binop(op, zero, mkexpr(arg_m))));
}
- DIP("vcge.%c%u %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size,
+ DIP("vcge.%c%d %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
break;
}
@@ -7043,7 +7043,7 @@
assign(res, unop(Q ? Iop_NotV128 : Iop_Not64,
unop(op, mkexpr(arg_m))));
}
- DIP("vceq.%c%u %c%u, %c%u, #0\n", F ? 'f' : 'i', 8 << size,
+ DIP("vceq.%c%d %c%u, %c%u, #0\n", F ? 'f' : 'i', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
break;
}
@@ -7074,7 +7074,7 @@
assign(res, unop(Q ? Iop_NotV128 : Iop_Not64,
binop(op, mkexpr(arg_m), zero)));
}
- DIP("vcle.%c%u %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size,
+ DIP("vcle.%c%d %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
break;
}
@@ -7104,7 +7104,7 @@
}
assign(res, binop(op, zero, mkexpr(arg_m)));
}
- DIP("vclt.%c%u %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size,
+ DIP("vclt.%c%d %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size,
Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
break;
}
@@ -7126,7 +7126,7 @@
assign(res, unop(Q ? Iop_Abs32Fx4 : Iop_Abs32Fx2,
mkexpr(arg_m)));
}
- DIP("vabs.%c%u %c%u, %c%u\n",
+ DIP("vabs.%c%d %c%u, %c%u\n",
F ? 'f' : 's', 8 << size, Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', mreg);
break;
@@ -7157,7 +7157,7 @@
}
assign(res, binop(op, zero, mkexpr(arg_m)));
}
- DIP("vneg.%c%u %c%u, %c%u\n",
+ DIP("vneg.%c%d %c%u, %c%u\n",
F ? 'f' : 's', 8 << size, Q ? 'q' : 'd', dreg,
Q ? 'q' : 'd', mreg);
break;
@@ -7255,7 +7255,7 @@
putDRegI64(dreg, mkexpr(new_d), condT);
putDRegI64(mreg, mkexpr(new_m), condT);
}
- DIP("vtrn.%u %c%u, %c%u\n",
+ DIP("vtrn.%d %c%u, %c%u\n",
8 << size, Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
return True;
} else if ((B >> 1) == 2) {
@@ -7306,7 +7306,7 @@
putDRegI64(dreg, mkexpr(new_d), condT);
putDRegI64(mreg, mkexpr(new_m), condT);
}
- DIP("vuzp.%u %c%u, %c%u\n",
+ DIP("vuzp.%d %c%u, %c%u\n",
8 << size, Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
return True;
} else if ((B >> 1) == 3) {
@@ -7357,7 +7357,7 @@
putDRegI64(dreg, mkexpr(new_d), condT);
putDRegI64(mreg, mkexpr(new_m), condT);
}
- DIP("vzip.%u %c%u, %c%u\n",
+ DIP("vzip.%d %c%u, %c%u\n",
8 << size, Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
return True;
} else if (B == 8) {
@@ -7372,7 +7372,7 @@
default: vassert(0);
}
putDRegI64(dreg, unop(op, getQReg(mreg)), condT);
- DIP("vmovn.i%u d%u, q%u\n", 16 << size, dreg, mreg);
+ DIP("vmovn.i%d d%u, q%u\n", 16 << size, dreg, mreg);
return True;
} else if (B == 9 || (B >> 1) == 5) {
/* VQMOVN, VQMOVUN */
@@ -7401,7 +7401,7 @@
case 3: return False;
default: vassert(0);
}
- DIP("vqmovun.s%u d%u, q%u\n", 16 << size, dreg, mreg);
+ DIP("vqmovun.s%d d%u, q%u\n", 16 << size, dreg, mreg);
break;
case 2:
switch (size) {
@@ -7411,7 +7411,7 @@
case 3: return False;
default: vassert(0);
}
- DIP("vqmovn.s%u d%u, q%u\n", 16 << size, dreg, mreg);
+ DIP("vqmovn.s%d d%u, q%u\n", 16 << size, dreg, mreg);
break;
case 3:
switch (size) {
@@ -7421,7 +7421,7 @@
case 3: return False;
default: vassert(0);
}
- DIP("vqmovn.u%u d%u, q%u\n", 16 << size, dreg, mreg);
+ DIP("vqmovn.u%d d%u, q%u\n", 16 << size, dreg, mreg);
break;
default:
vassert(0);
@@ -7454,7 +7454,7 @@
assign(res, binop(op, unop(cvt, getDRegI64(mreg)),
mkU8(shift_imm)));
putQReg(dreg, mkexpr(res), condT);
- DIP("vshll.i%u q%u, d%u, #%u\n", 8 << size, dreg, mreg, 8 << size);
+ DIP("vshll.i%d q%u, d%u, #%d\n", 8 << size, dreg, mreg, 8 << size);
return True;
} else if ((B >> 3) == 3 && (B & 3) == 0) {
/* VCVT (half<->single) */
@@ -8387,7 +8387,7 @@
mk_neon_elem_load_to_one_lane(rD, inc, i, N, size, addr);
else
mk_neon_elem_store_from_one_lane(rD, inc, i, N, size, addr);
- DIP("v%s%u.%u {", bL ? "ld" : "st", N + 1, 8 << size);
+ DIP("v%s%u.%d {", bL ? "ld" : "st", N + 1, 8 << size);
for (j = 0; j <= N; j++) {
if (j)
DIP(", ");
@@ -8482,7 +8482,7 @@
}
}
}
- DIP("vld%u.%u {", N + 1, 8 << size);
+ DIP("vld%u.%d {", N + 1, 8 << size);
for (r = 0; r < regs; r++) {
for (i = 0; i <= N; i++) {
if (i || r)
@@ -8783,7 +8783,7 @@
putIRegA(rN, e, IRTemp_INVALID, Ijk_Boring);
}
- DIP("v%s%u.%u {", bL ? "ld" : "st", N + 1, 8 << INSN(7,6));
+ DIP("v%s%u.%d {", bL ? "ld" : "st", N + 1, 8 << INSN(7,6));
if ((inc == 1 && regs * (N + 1) > 1)
|| (inc == 2 && regs > 1 && N > 0)) {
DIP("d%u-d%u", rD, rD + regs * (N + 1) - 1);
@@ -12674,9 +12674,9 @@
transfer last for a load and first for a store. Requires
reordering xOff/xReg. */
if (0) {
- vex_printf("\nREG_LIST_PRE: (rN=%d)\n", rN);
+ vex_printf("\nREG_LIST_PRE: (rN=%u)\n", rN);
for (i = 0; i < nX; i++)
- vex_printf("reg %d off %d\n", xReg[i], xOff[i]);
+ vex_printf("reg %u off %u\n", xReg[i], xOff[i]);
vex_printf("\n");
}
@@ -12715,7 +12715,7 @@
if (0) {
vex_printf("REG_LIST_POST:\n");
for (i = 0; i < nX; i++)
- vex_printf("reg %d off %d\n", xReg[i], xOff[i]);
+ vex_printf("reg %u off %u\n", xReg[i], xOff[i]);
vex_printf("\n");
}
}
@@ -13398,7 +13398,7 @@
default:
vassert(0);
}
- DIP("vdup.%u q%u, r%u\n", 32 / (1<<size), rD, rT);
+ DIP("vdup.%d q%u, r%u\n", 32 / (1<<size), rD, rT);
} else {
switch (size) {
case 0:
@@ -13415,7 +13415,7 @@
default:
vassert(0);
}
- DIP("vdup.%u d%u, r%u\n", 32 / (1<<size), rD, rT);
+ DIP("vdup.%d d%u, r%u\n", 32 / (1<<size), rD, rT);
}
goto decode_success_vfp;
}
@@ -16303,7 +16303,7 @@
vassert(0); // guarded by "if" above
}
putIRegA(rD, mkexpr(dstT), condT, Ijk_Boring);
- DIP("%s%s r%u, r%u, ROR #%u\n", nm, nCC(INSN_COND), rD, rM, rot);
+ DIP("%s%s r%u, r%u, ROR #%d\n", nm, nCC(INSN_COND), rD, rM, rot);
goto decode_success;
}
/* fall through */
@@ -17305,9 +17305,9 @@
if (sigill_diag) {
vex_printf("disInstr(arm): unhandled instruction: "
"0x%x\n", insn);
- vex_printf(" cond=%d(0x%x) 27:20=%u(0x%02x) "
+ vex_printf(" cond=%d(0x%x) 27:20=%d(0x%02x) "
"4:4=%d "
- "3:0=%u(0x%x)\n",
+ "3:0=%d(0x%x)\n",
(Int)INSN_COND, (UInt)INSN_COND,
(Int)INSN(27,20), (UInt)INSN(27,20),
(Int)INSN(4,4),
@@ -21549,7 +21549,7 @@
UInt bW = INSN0(5,5);
UInt imm2 = INSN1(5,4);
if (!isBadRegT(rM)) {
- DIP("pld%s [r%u, r%u, lsl %d]\n", bW ? "w" : "", rN, rM, imm2);
+ DIP("pld%s [r%u, r%u, lsl %u]\n", bW ? "w" : "", rN, rM, imm2);
goto decode_success;
}
/* fall through */
Modified: trunk/priv/guest_mips_toIR.c
==============================================================================
--- trunk/priv/guest_mips_toIR.c (original)
+++ trunk/priv/guest_mips_toIR.c Mon Aug 3 17:03:13 2015
@@ -1554,13 +1554,13 @@
case 0x3A:
if ((regRs & 0x01) == 0) {
/* Doubleword Shift Right Logical - DSRL; MIPS64 */
- DIP("dsrl r%u, r%u, %d", regRd, regRt, (Int)sImmsa);
+ DIP("dsrl r%u, r%u, %lld", regRd, regRt, sImmsa);
assign(tmpRd, binop(Iop_Shr64, mkexpr(tmpRt), mkU8(uImmsa)));
putIReg(regRd, mkexpr(tmpRd));
} else if ((regRs & 0x01) == 1) {
/* Doubleword Rotate Right - DROTR; MIPS64r2 */
vassert(mode64);
- DIP("drotr r%u, r%u, %d", regRd, regRt, (Int)sImmsa);
+ DIP("drotr r%u, r%u, %lld", regRd, regRt, sImmsa);
IRTemp tmpL = newTemp(ty);
IRTemp tmpR = newTemp(ty);
assign(tmpR, binop(Iop_Shr64, mkexpr(tmpRt), mkU8(uImmsa)));
@@ -1575,12 +1575,12 @@
case 0x3E:
if ((regRs & 0x01) == 0) {
/* Doubleword Shift Right Logical Plus 32 - DSRL32; MIPS64 */
- DIP("dsrl32 r%u, r%u, %d", regRd, regRt, (Int)(sImmsa + 32));
+ DIP("dsrl32 r%u, r%u, %lld", regRd, regRt, sImmsa + 32);
assign(tmpRd, binop(Iop_Shr64, mkexpr(tmpRt), mkU8(uImmsa + 32)));
putIReg(regRd, mkexpr(tmpRd));
} else if ((regRs & 0x01) == 1) {
/* Doubleword Rotate Right Plus 32 - DROTR32; MIPS64r2 */
- DIP("drotr32 r%u, r%u, %d", regRd, regRt, (Int)sImmsa);
+ DIP("drotr32 r%u, r%u, %lld", regRd, regRt, sImmsa);
vassert(mode64);
IRTemp tmpL = newTemp(ty);
IRTemp tmpR = newTemp(ty);
@@ -1634,14 +1634,14 @@
break;
case 0x38: /* Doubleword Shift Left Logical - DSLL; MIPS64 */
- DIP("dsll r%u, r%u, %d", regRd, regRt, (Int)sImmsa);
+ DIP("dsll r%u, r%u, %lld", regRd, regRt, sImmsa);
vassert(mode64);
assign(tmpRd, binop(Iop_Shl64, mkexpr(tmpRt), mkU8(uImmsa)));
putIReg(regRd, mkexpr(tmpRd));
break;
case 0x3C: /* Doubleword Shift Left Logical Plus 32 - DSLL32; MIPS64 */
- DIP("dsll32 r%u, r%u, %d", regRd, regRt, (Int)sImmsa);
+ DIP("dsll32 r%u, r%u, %lld", regRd, regRt, sImmsa);
assign(tmpRd, binop(Iop_Shl64, mkexpr(tmpRt), mkU8(uImmsa + 32)));
...
[truncated message content] |
|
From: <sv...@va...> - 2015-08-03 10:48:26
|
Author: iraisr
Date: Mon Aug 3 11:48:16 2015
New Revision: 15477
Log:
Fix a typo in README.solaris.
Spotted by Florian Krohm <fl...@ei...>.
Modified:
trunk/README.solaris
Modified: trunk/README.solaris
==============================================================================
--- trunk/README.solaris (original)
+++ trunk/README.solaris Mon Aug 3 11:48:16 2015
@@ -74,11 +74,11 @@
itself it is not possible to reverse map the intended pathname.
Examples are fexecve(3C) and isaexec(3C).
- Program headers PT_SUNW_SYSSTAT and PT_SUNW_SYSSTAT_ZONE are not supported.
- That is, programs linked with mapfile directive RESERVE_SEGMENT and atribute
+ That is, programs linked with mapfile directive RESERVE_SEGMENT and attribute
TYPE equal to SYSSTAT or SYSSTAT_ZONE will cause Valgrind exit. It is not
possible for Valgrind to arrange mapping of a kernel shared page at the
address specified in the mapfile for the guest application. There is currently
- no such mechanism in Solaris.
+ no such mechanism in Solaris. Hacky workarounds are possible, though.
- When a thread has no stack then all system calls will result in Valgrind
crash, even though such system calls use just parameters passed in registers.
This should happen only in pathological situations when a thread is created
|
|
From: Florian K. <fl...@ei...> - 2015-08-03 09:33:49
|
You ought to run "make regtest" when making changes that have the potential to break stuff. There are zillions of messages like this one: none/tests/tilegx/Makefile.am:1: error: insn_test_ldnt4u_add_X1.stderr.exp is in EXTRA_DIST but doesn't exist none/tests/tilegx/Makefile.am:1: error: insn_test_ldnt4u_add_X1.vgtest is in EXTRA_DIST but doesn't exist none/tests/tilegx/Makefile.am:1: error: insn_test_ldnt_add_X1.stdout.exp is in EXTRA_DIST but doesn't exist Also make sure that "make dist BUILD_ALL_DOCS=no" runs successfully to completion. Florian On 01.08.2015 05:52, sv...@va... wrote: > Author: zliu > Date: Sat Aug 1 04:52:03 2015 > New Revision: 15466 > > Log: > Merge tilegx instruction test patch "valgrind-tilegx-instruction-test.patch" > in Bug 345921 - Add TileGX instruction set test in none/tests/tilegx > Submitted by Liming Sun, ls...@ez... > > > Added: > trunk/none/tests/tilegx/filter_stderr > trunk/none/tests/tilegx/gen_insn_test.c > trunk/none/tests/tilegx/gen_test.sh > Modified: > trunk/none/tests/tilegx/Makefile.am > > Modified: trunk/none/tests/tilegx/Makefile.am > ============================================================================== > --- trunk/none/tests/tilegx/Makefile.am (original) > +++ trunk/none/tests/tilegx/Makefile.am Sat Aug 1 04:52:03 2015 > @@ -1,13 +1,1614 @@ > > include $(top_srcdir)/Makefile.tool-tests.am > > -EXTRA_DIST = > +dist_noinst_SCRIPTS = \ > + filter_stderr > + > +EXTRA_DIST = \ > + insn_test_move_X0.stdout.exp insn_test_move_X0.stderr.exp \ > + insn_test_move_X0.vgtest \ > + insn_test_move_X1.stdout.exp insn_test_move_X1.stderr.exp \ > + insn_test_move_X1.vgtest \ > + insn_test_move_Y0.stdout.exp insn_test_move_Y0.stderr.exp \ > + insn_test_move_Y0.vgtest \ > + insn_test_move_Y1.stdout.exp insn_test_move_Y1.stderr.exp \ > + insn_test_move_Y1.vgtest \ > + insn_test_movei_X0.stdout.exp insn_test_movei_X0.stderr.exp \ > + insn_test_movei_X0.vgtest \ > + insn_test_movei_X1.stdout.exp insn_test_movei_X1.stderr.exp \ > + insn_test_movei_X1.vgtest \ > + insn_test_movei_Y0.stdout.exp insn_test_movei_Y0.stderr.exp \ > + insn_test_movei_Y0.vgtest \ > + insn_test_movei_Y1.stdout.exp insn_test_movei_Y1.stderr.exp \ > + insn_test_movei_Y1.vgtest \ > + insn_test_moveli_X0.stdout.exp insn_test_moveli_X0.stderr.exp \ > + insn_test_moveli_X0.vgtest \ > + insn_test_moveli_X1.stdout.exp insn_test_moveli_X1.stderr.exp \ > + insn_test_moveli_X1.vgtest \ > + insn_test_prefetch_X1.stdout.exp insn_test_prefetch_X1.stderr.exp \ > + insn_test_prefetch_X1.vgtest \ > + insn_test_prefetch_Y2.stdout.exp insn_test_prefetch_Y2.stderr.exp \ > + insn_test_prefetch_Y2.vgtest \ > + insn_test_prefetch_l1_X1.stdout.exp \ > + insn_test_prefetch_l1_X1.stderr.exp \ > + insn_test_prefetch_l1_X1.vgtest \ > + insn_test_prefetch_l1_Y2.stdout.exp \ > + insn_test_prefetch_l1_Y2.stderr.exp \ > + insn_test_prefetch_l1_Y2.vgtest \ > + insn_test_prefetch_l2_X1.stdout.exp \ > + insn_test_prefetch_l2_X1.stderr.exp \ > + insn_test_prefetch_l2_X1.vgtest \ > + insn_test_prefetch_l2_Y2.stdout.exp \ > + insn_test_prefetch_l2_Y2.stderr.exp \ > + insn_test_prefetch_l2_Y2.vgtest \ > + insn_test_prefetch_l3_X1.stdout.exp \ > + insn_test_prefetch_l3_X1.stderr.exp \ > + insn_test_prefetch_l3_X1.vgtest \ > + insn_test_prefetch_l3_Y2.stdout.exp \ > + insn_test_prefetch_l3_Y2.stderr.exp \ > + insn_test_prefetch_l3_Y2.vgtest \ > + insn_test_add_X0.stdout.exp insn_test_add_X0.stderr.exp \ > + insn_test_add_X0.vgtest \ > + insn_test_add_X1.stdout.exp insn_test_add_X1.stderr.exp \ > + insn_test_add_X1.vgtest \ > + insn_test_add_Y0.stdout.exp insn_test_add_Y0.stderr.exp \ > + insn_test_add_Y0.vgtest \ > + insn_test_add_Y1.stdout.exp insn_test_add_Y1.stderr.exp \ > + insn_test_add_Y1.vgtest \ > + insn_test_addi_X0.stdout.exp insn_test_addi_X0.stderr.exp \ > + insn_test_addi_X0.vgtest \ > + insn_test_addi_X1.stdout.exp insn_test_addi_X1.stderr.exp \ > + insn_test_addi_X1.vgtest \ > + insn_test_addi_Y0.stdout.exp insn_test_addi_Y0.stderr.exp \ > + insn_test_addi_Y0.vgtest \ > + insn_test_addi_Y1.stdout.exp insn_test_addi_Y1.stderr.exp \ > + insn_test_addi_Y1.vgtest \ > + insn_test_addli_X0.stdout.exp insn_test_addli_X0.stderr.exp \ > + insn_test_addli_X0.vgtest \ > + insn_test_addli_X1.stdout.exp insn_test_addli_X1.stderr.exp \ > + insn_test_addli_X1.vgtest \ > + insn_test_addx_X0.stdout.exp insn_test_addx_X0.stderr.exp \ > + insn_test_addx_X0.vgtest \ > + insn_test_addx_X1.stdout.exp insn_test_addx_X1.stderr.exp \ > + insn_test_addx_X1.vgtest \ > + insn_test_addx_Y0.stdout.exp insn_test_addx_Y0.stderr.exp \ > + insn_test_addx_Y0.vgtest \ > + insn_test_addx_Y1.stdout.exp insn_test_addx_Y1.stderr.exp \ > + insn_test_addx_Y1.vgtest \ > + insn_test_addxi_X0.stdout.exp insn_test_addxi_X0.stderr.exp \ > + insn_test_addxi_X0.vgtest \ > + insn_test_addxi_X1.stdout.exp insn_test_addxi_X1.stderr.exp \ > + insn_test_addxi_X1.vgtest \ > + insn_test_addxi_Y0.stdout.exp insn_test_addxi_Y0.stderr.exp \ > + insn_test_addxi_Y0.vgtest \ > + insn_test_addxi_Y1.stdout.exp insn_test_addxi_Y1.stderr.exp \ > + insn_test_addxi_Y1.vgtest \ > + insn_test_addxli_X0.stdout.exp insn_test_addxli_X0.stderr.exp \ > + insn_test_addxli_X0.vgtest \ > + insn_test_addxli_X1.stdout.exp insn_test_addxli_X1.stderr.exp \ > + insn_test_addxli_X1.vgtest \ > + insn_test_addxsc_X0.stdout.exp insn_test_addxsc_X0.stderr.exp \ > + insn_test_addxsc_X0.vgtest \ > + insn_test_addxsc_X1.stdout.exp insn_test_addxsc_X1.stderr.exp \ > + insn_test_addxsc_X1.vgtest \ > + insn_test_and_X0.stdout.exp insn_test_and_X0.stderr.exp \ > + insn_test_and_X0.vgtest \ > + insn_test_and_X1.stdout.exp insn_test_and_X1.stderr.exp \ > + insn_test_and_X1.vgtest \ > + insn_test_and_Y0.stdout.exp insn_test_and_Y0.stderr.exp \ > + insn_test_and_Y0.vgtest \ > + insn_test_and_Y1.stdout.exp insn_test_and_Y1.stderr.exp \ > + insn_test_and_Y1.vgtest \ > + insn_test_andi_X0.stdout.exp insn_test_andi_X0.stderr.exp \ > + insn_test_andi_X0.vgtest \ > + insn_test_andi_X1.stdout.exp insn_test_andi_X1.stderr.exp \ > + insn_test_andi_X1.vgtest \ > + insn_test_andi_Y0.stdout.exp insn_test_andi_Y0.stderr.exp \ > + insn_test_andi_Y0.vgtest \ > + insn_test_andi_Y1.stdout.exp insn_test_andi_Y1.stderr.exp \ > + insn_test_andi_Y1.vgtest \ > + insn_test_beqz_X1.stdout.exp insn_test_beqz_X1.stderr.exp \ > + insn_test_beqz_X1.vgtest \ > + insn_test_beqzt_X1.stdout.exp insn_test_beqzt_X1.stderr.exp \ > + insn_test_beqzt_X1.vgtest \ > + insn_test_bfexts_X0.stdout.exp insn_test_bfexts_X0.stderr.exp \ > + insn_test_bfexts_X0.vgtest \ > + insn_test_bfextu_X0.stdout.exp insn_test_bfextu_X0.stderr.exp \ > + insn_test_bfextu_X0.vgtest \ > + insn_test_bfins_X0.stdout.exp insn_test_bfins_X0.stderr.exp \ > + insn_test_bfins_X0.vgtest \ > + insn_test_bgez_X1.stdout.exp insn_test_bgez_X1.stderr.exp \ > + insn_test_bgez_X1.vgtest \ > + insn_test_bgezt_X1.stdout.exp insn_test_bgezt_X1.stderr.exp \ > + insn_test_bgezt_X1.vgtest \ > + insn_test_bgtz_X1.stdout.exp insn_test_bgtz_X1.stderr.exp \ > + insn_test_bgtz_X1.vgtest \ > + insn_test_bgtzt_X1.stdout.exp insn_test_bgtzt_X1.stderr.exp \ > + insn_test_bgtzt_X1.vgtest \ > + insn_test_blbc_X1.stdout.exp insn_test_blbc_X1.stderr.exp \ > + insn_test_blbc_X1.vgtest \ > + insn_test_blbct_X1.stdout.exp insn_test_blbct_X1.stderr.exp \ > + insn_test_blbct_X1.vgtest \ > + insn_test_blbs_X1.stdout.exp insn_test_blbs_X1.stderr.exp \ > + insn_test_blbs_X1.vgtest \ > + insn_test_blbst_X1.stdout.exp insn_test_blbst_X1.stderr.exp \ > + insn_test_blbst_X1.vgtest \ > + insn_test_blez_X1.stdout.exp insn_test_blez_X1.stderr.exp \ > + insn_test_blez_X1.vgtest \ > + insn_test_blezt_X1.stdout.exp insn_test_blezt_X1.stderr.exp \ > + insn_test_blezt_X1.vgtest \ > + insn_test_bltz_X1.stdout.exp insn_test_bltz_X1.stderr.exp \ > + insn_test_bltz_X1.vgtest \ > + insn_test_bltzt_X1.stdout.exp insn_test_bltzt_X1.stderr.exp \ > + insn_test_bltzt_X1.vgtest \ > + insn_test_bnez_X1.stdout.exp insn_test_bnez_X1.stderr.exp \ > + insn_test_bnez_X1.vgtest \ > + insn_test_bnezt_X1.stdout.exp insn_test_bnezt_X1.stderr.exp \ > + insn_test_bnezt_X1.vgtest \ > + insn_test_clz_X0.stdout.exp insn_test_clz_X0.stderr.exp \ > + insn_test_clz_X0.vgtest \ > + insn_test_clz_Y0.stdout.exp insn_test_clz_Y0.stderr.exp \ > + insn_test_clz_Y0.vgtest \ > + insn_test_cmoveqz_X0.stdout.exp insn_test_cmoveqz_X0.stderr.exp \ > + insn_test_cmoveqz_X0.vgtest \ > + insn_test_cmoveqz_Y0.stdout.exp insn_test_cmoveqz_Y0.stderr.exp \ > + insn_test_cmoveqz_Y0.vgtest \ > + insn_test_cmovnez_X0.stdout.exp insn_test_cmovnez_X0.stderr.exp \ > + insn_test_cmovnez_X0.vgtest \ > + insn_test_cmovnez_Y0.stdout.exp insn_test_cmovnez_Y0.stderr.exp \ > + insn_test_cmovnez_Y0.vgtest \ > + insn_test_cmpeq_X0.stdout.exp insn_test_cmpeq_X0.stderr.exp \ > + insn_test_cmpeq_X0.vgtest \ > + insn_test_cmpeq_X1.stdout.exp insn_test_cmpeq_X1.stderr.exp \ > + insn_test_cmpeq_X1.vgtest \ > + insn_test_cmpeq_Y0.stdout.exp insn_test_cmpeq_Y0.stderr.exp \ > + insn_test_cmpeq_Y0.vgtest \ > + insn_test_cmpeq_Y1.stdout.exp insn_test_cmpeq_Y1.stderr.exp \ > + insn_test_cmpeq_Y1.vgtest \ > + insn_test_cmpeqi_X0.stdout.exp insn_test_cmpeqi_X0.stderr.exp \ > + insn_test_cmpeqi_X0.vgtest \ > + insn_test_cmpeqi_X1.stdout.exp insn_test_cmpeqi_X1.stderr.exp \ > + insn_test_cmpeqi_X1.vgtest \ > + insn_test_cmpeqi_Y0.stdout.exp insn_test_cmpeqi_Y0.stderr.exp \ > + insn_test_cmpeqi_Y0.vgtest \ > + insn_test_cmpeqi_Y1.stdout.exp insn_test_cmpeqi_Y1.stderr.exp \ > + insn_test_cmpeqi_Y1.vgtest \ > + insn_test_cmples_X0.stdout.exp insn_test_cmples_X0.stderr.exp \ > + insn_test_cmples_X0.vgtest \ > + insn_test_cmples_X1.stdout.exp insn_test_cmples_X1.stderr.exp \ > + insn_test_cmples_X1.vgtest \ > + insn_test_cmples_Y0.stdout.exp insn_test_cmples_Y0.stderr.exp \ > + insn_test_cmples_Y0.vgtest \ > + insn_test_cmples_Y1.stdout.exp insn_test_cmples_Y1.stderr.exp \ > + insn_test_cmples_Y1.vgtest \ > + insn_test_cmpleu_X0.stdout.exp insn_test_cmpleu_X0.stderr.exp \ > + insn_test_cmpleu_X0.vgtest \ > + insn_test_cmpleu_X1.stdout.exp insn_test_cmpleu_X1.stderr.exp \ > + insn_test_cmpleu_X1.vgtest \ > + insn_test_cmpleu_Y0.stdout.exp insn_test_cmpleu_Y0.stderr.exp \ > + insn_test_cmpleu_Y0.vgtest \ > + insn_test_cmpleu_Y1.stdout.exp insn_test_cmpleu_Y1.stderr.exp \ > + insn_test_cmpleu_Y1.vgtest \ > + insn_test_cmplts_X0.stdout.exp insn_test_cmplts_X0.stderr.exp \ > + insn_test_cmplts_X0.vgtest \ > + insn_test_cmplts_X1.stdout.exp insn_test_cmplts_X1.stderr.exp \ > + insn_test_cmplts_X1.vgtest \ > + insn_test_cmplts_Y0.stdout.exp insn_test_cmplts_Y0.stderr.exp \ > + insn_test_cmplts_Y0.vgtest \ > + insn_test_cmplts_Y1.stdout.exp insn_test_cmplts_Y1.stderr.exp \ > + insn_test_cmplts_Y1.vgtest \ > + insn_test_cmpltsi_X0.stdout.exp insn_test_cmpltsi_X0.stderr.exp \ > + insn_test_cmpltsi_X0.vgtest \ > + insn_test_cmpltsi_X1.stdout.exp insn_test_cmpltsi_X1.stderr.exp \ > + insn_test_cmpltsi_X1.vgtest \ > + insn_test_cmpltsi_Y0.stdout.exp insn_test_cmpltsi_Y0.stderr.exp \ > + insn_test_cmpltsi_Y0.vgtest \ > + insn_test_cmpltsi_Y1.stdout.exp insn_test_cmpltsi_Y1.stderr.exp \ > + insn_test_cmpltsi_Y1.vgtest \ > + insn_test_cmpltu_X0.stdout.exp insn_test_cmpltu_X0.stderr.exp \ > + insn_test_cmpltu_X0.vgtest \ > + insn_test_cmpltu_X1.stdout.exp insn_test_cmpltu_X1.stderr.exp \ > + insn_test_cmpltu_X1.vgtest \ > + insn_test_cmpltu_Y0.stdout.exp insn_test_cmpltu_Y0.stderr.exp \ > + insn_test_cmpltu_Y0.vgtest \ > + insn_test_cmpltu_Y1.stdout.exp insn_test_cmpltu_Y1.stderr.exp \ > + insn_test_cmpltu_Y1.vgtest \ > + insn_test_cmpltui_X0.stdout.exp insn_test_cmpltui_X0.stderr.exp \ > + insn_test_cmpltui_X0.vgtest \ > + insn_test_cmpltui_X1.stdout.exp insn_test_cmpltui_X1.stderr.exp \ > + insn_test_cmpltui_X1.vgtest \ > + insn_test_cmpne_X0.stdout.exp insn_test_cmpne_X0.stderr.exp \ > + insn_test_cmpne_X0.vgtest \ > + insn_test_cmpne_X1.stdout.exp insn_test_cmpne_X1.stderr.exp \ > + insn_test_cmpne_X1.vgtest \ > + insn_test_cmpne_Y0.stdout.exp insn_test_cmpne_Y0.stderr.exp \ > + insn_test_cmpne_Y0.vgtest \ > + insn_test_cmpne_Y1.stdout.exp insn_test_cmpne_Y1.stderr.exp \ > + insn_test_cmpne_Y1.vgtest \ > + insn_test_cmul_X0.stdout.exp insn_test_cmul_X0.stderr.exp \ > + insn_test_cmul_X0.vgtest \ > + insn_test_cmula_X0.stdout.exp insn_test_cmula_X0.stderr.exp \ > + insn_test_cmula_X0.vgtest \ > + insn_test_cmulaf_X0.stdout.exp insn_test_cmulaf_X0.stderr.exp \ > + insn_test_cmulaf_X0.vgtest \ > + insn_test_cmulf_X0.stdout.exp insn_test_cmulf_X0.stderr.exp \ > + insn_test_cmulf_X0.vgtest \ > + insn_test_cmulfr_X0.stdout.exp insn_test_cmulfr_X0.stderr.exp \ > + insn_test_cmulfr_X0.vgtest \ > + insn_test_cmulh_X0.stdout.exp insn_test_cmulh_X0.stderr.exp \ > + insn_test_cmulh_X0.vgtest \ > + insn_test_cmulhr_X0.stdout.exp insn_test_cmulhr_X0.stderr.exp \ > + insn_test_cmulhr_X0.vgtest \ > + insn_test_crc32_32_X0.stdout.exp insn_test_crc32_32_X0.stderr.exp \ > + insn_test_crc32_32_X0.vgtest \ > + insn_test_crc32_8_X0.stdout.exp insn_test_crc32_8_X0.stderr.exp \ > + insn_test_crc32_8_X0.vgtest \ > + insn_test_ctz_X0.stdout.exp insn_test_ctz_X0.stderr.exp \ > + insn_test_ctz_X0.vgtest \ > + insn_test_ctz_Y0.stdout.exp insn_test_ctz_Y0.stderr.exp \ > + insn_test_ctz_Y0.vgtest \ > + insn_test_dblalign_X0.stdout.exp insn_test_dblalign_X0.stderr.exp \ > + insn_test_dblalign_X0.vgtest \ > + insn_test_dblalign2_X0.stdout.exp insn_test_dblalign2_X0.stderr.exp \ > + insn_test_dblalign2_X0.vgtest \ > + insn_test_dblalign2_X1.stdout.exp insn_test_dblalign2_X1.stderr.exp \ > + insn_test_dblalign2_X1.vgtest \ > + insn_test_dblalign4_X0.stdout.exp insn_test_dblalign4_X0.stderr.exp \ > + insn_test_dblalign4_X0.vgtest \ > + insn_test_dblalign4_X1.stdout.exp insn_test_dblalign4_X1.stderr.exp \ > + insn_test_dblalign4_X1.vgtest \ > + insn_test_dblalign6_X0.stdout.exp insn_test_dblalign6_X0.stderr.exp \ > + insn_test_dblalign6_X0.vgtest \ > + insn_test_dblalign6_X1.stdout.exp insn_test_dblalign6_X1.stderr.exp \ > + insn_test_dblalign6_X1.vgtest \ > + insn_test_dtlbpr_X1.stdout.exp insn_test_dtlbpr_X1.stderr.exp \ > + insn_test_dtlbpr_X1.vgtest \ > + insn_test_fdouble_add_flags_X0.stdout.exp \ > + insn_test_fdouble_add_flags_X0.stderr.exp \ > + insn_test_fdouble_add_flags_X0.vgtest \ > + insn_test_fdouble_addsub_X0.stdout.exp \ > + insn_test_fdouble_addsub_X0.stderr.exp \ > + insn_test_fdouble_addsub_X0.vgtest \ > + insn_test_fdouble_mul_flags_X0.stdout.exp \ > + insn_test_fdouble_mul_flags_X0.stderr.exp \ > + insn_test_fdouble_mul_flags_X0.vgtest \ > + insn_test_fdouble_pack1_X0.stdout.exp \ > + insn_test_fdouble_pack1_X0.stderr.exp \ > + insn_test_fdouble_pack1_X0.vgtest \ > + insn_test_fdouble_pack2_X0.stdout.exp \ > + insn_test_fdouble_pack2_X0.stderr.exp \ > + insn_test_fdouble_pack2_X0.vgtest \ > + insn_test_fdouble_sub_flags_X0.stdout.exp \ > + insn_test_fdouble_sub_flags_X0.stderr.exp \ > + insn_test_fdouble_sub_flags_X0.vgtest \ > + insn_test_fdouble_unpack_max_X0.stdout.exp \ > + insn_test_fdouble_unpack_max_X0.stderr.exp \ > + insn_test_fdouble_unpack_max_X0.vgtest \ > + insn_test_fdouble_unpack_min_X0.stdout.exp \ > + insn_test_fdouble_unpack_min_X0.stderr.exp \ > + insn_test_fdouble_unpack_min_X0.vgtest \ > + insn_test_flushwb_X1.stdout.exp insn_test_flushwb_X1.stderr.exp \ > + insn_test_flushwb_X1.vgtest \ > + insn_test_fnop_X0.stdout.exp insn_test_fnop_X0.stderr.exp \ > + insn_test_fnop_X0.vgtest \ > + insn_test_fnop_X1.stdout.exp insn_test_fnop_X1.stderr.exp \ > + insn_test_fnop_X1.vgtest \ > + insn_test_fnop_Y0.stdout.exp insn_test_fnop_Y0.stderr.exp \ > + insn_test_fnop_Y0.vgtest \ > + insn_test_fnop_Y1.stdout.exp insn_test_fnop_Y1.stderr.exp \ > + insn_test_fnop_Y1.vgtest \ > + insn_test_fsingle_add1_X0.stdout.exp \ > + insn_test_fsingle_add1_X0.stderr.exp \ > + insn_test_fsingle_add1_X0.vgtest \ > + insn_test_fsingle_addsub2_X0.stdout.exp \ > + insn_test_fsingle_addsub2_X0.stderr.exp \ > + insn_test_fsingle_addsub2_X0.vgtest \ > + insn_test_fsingle_mul1_X0.stdout.exp \ > + insn_test_fsingle_mul1_X0.stderr.exp \ > + insn_test_fsingle_mul1_X0.vgtest \ > + insn_test_fsingle_mul2_X0.stdout.exp \ > + insn_test_fsingle_mul2_X0.stderr.exp \ > + insn_test_fsingle_mul2_X0.vgtest \ > + insn_test_fsingle_pack1_X0.stdout.exp \ > + insn_test_fsingle_pack1_X0.stderr.exp \ > + insn_test_fsingle_pack1_X0.vgtest \ > + insn_test_fsingle_pack1_Y0.stdout.exp \ > + insn_test_fsingle_pack1_Y0.stderr.exp \ > + insn_test_fsingle_pack1_Y0.vgtest \ > + insn_test_fsingle_pack2_X0.stdout.exp \ > + insn_test_fsingle_pack2_X0.stderr.exp \ > + insn_test_fsingle_pack2_X0.vgtest \ > + insn_test_fsingle_sub1_X0.stdout.exp \ > + insn_test_fsingle_sub1_X0.stderr.exp \ > + insn_test_fsingle_sub1_X0.vgtest \ > + insn_test_icoh_X1.stdout.exp insn_test_icoh_X1.stderr.exp \ > + insn_test_icoh_X1.vgtest \ > + insn_test_j_X1.stdout.exp insn_test_j_X1.stderr.exp \ > + insn_test_j_X1.vgtest \ > + insn_test_jal_X1.stdout.exp insn_test_jal_X1.stderr.exp \ > + insn_test_jal_X1.vgtest \ > + insn_test_jalr_X1.stdout.exp insn_test_jalr_X1.stderr.exp \ > + insn_test_jalr_X1.vgtest \ > + insn_test_jalr_Y1.stdout.exp insn_test_jalr_Y1.stderr.exp \ > + insn_test_jalr_Y1.vgtest \ > + insn_test_jalrp_X1.stdout.exp insn_test_jalrp_X1.stderr.exp \ > + insn_test_jalrp_X1.vgtest \ > + insn_test_jalrp_Y1.stdout.exp insn_test_jalrp_Y1.stderr.exp \ > + insn_test_jalrp_Y1.vgtest \ > + insn_test_jr_X1.stdout.exp insn_test_jr_X1.stderr.exp \ > + insn_test_jr_X1.vgtest \ > + insn_test_jr_Y1.stdout.exp insn_test_jr_Y1.stderr.exp \ > + insn_test_jr_Y1.vgtest \ > + insn_test_jrp_X1.stdout.exp insn_test_jrp_X1.stderr.exp \ > + insn_test_jrp_X1.vgtest \ > + insn_test_jrp_Y1.stdout.exp insn_test_jrp_Y1.stderr.exp \ > + insn_test_jrp_Y1.vgtest \ > + insn_test_ld_X1.stdout.exp insn_test_ld_X1.stderr.exp \ > + insn_test_ld_X1.vgtest \ > + insn_test_ld_Y2.stdout.exp insn_test_ld_Y2.stderr.exp \ > + insn_test_ld_Y2.vgtest \ > + insn_test_ld1s_X1.stdout.exp insn_test_ld1s_X1.stderr.exp \ > + insn_test_ld1s_X1.vgtest \ > + insn_test_ld1s_Y2.stdout.exp insn_test_ld1s_Y2.stderr.exp \ > + insn_test_ld1s_Y2.vgtest \ > + insn_test_ld1s_add_X1.stdout.exp insn_test_ld1s_add_X1.stderr.exp \ > + insn_test_ld1s_add_X1.vgtest \ > + insn_test_ld1u_X1.stdout.exp insn_test_ld1u_X1.stderr.exp \ > + insn_test_ld1u_X1.vgtest \ > + insn_test_ld1u_Y2.stdout.exp insn_test_ld1u_Y2.stderr.exp \ > + insn_test_ld1u_Y2.vgtest \ > + insn_test_ld1u_add_X1.stdout.exp insn_test_ld1u_add_X1.stderr.exp \ > + insn_test_ld1u_add_X1.vgtest \ > + insn_test_ld2s_X1.stdout.exp insn_test_ld2s_X1.stderr.exp \ > + insn_test_ld2s_X1.vgtest \ > + insn_test_ld2s_Y2.stdout.exp insn_test_ld2s_Y2.stderr.exp \ > + insn_test_ld2s_Y2.vgtest \ > + insn_test_ld2u_X1.stdout.exp insn_test_ld2u_X1.stderr.exp \ > + insn_test_ld2u_X1.vgtest \ > + insn_test_ld2u_Y2.stdout.exp insn_test_ld2u_Y2.stderr.exp \ > + insn_test_ld2u_Y2.vgtest \ > + insn_test_ld4s_X1.stdout.exp insn_test_ld4s_X1.stderr.exp \ > + insn_test_ld4s_X1.vgtest \ > + insn_test_ld4s_add_X1.stdout.exp insn_test_ld4s_add_X1.stderr.exp \ > + insn_test_ld4s_add_X1.vgtest \ > + insn_test_ld4u_X1.stdout.exp insn_test_ld4u_X1.stderr.exp \ > + insn_test_ld4u_X1.vgtest \ > + insn_test_ld4u_Y2.stdout.exp insn_test_ld4u_Y2.stderr.exp \ > + insn_test_ld4u_Y2.vgtest \ > + insn_test_ld4u_add_X1.stdout.exp insn_test_ld4u_add_X1.stderr.exp \ > + insn_test_ld4u_add_X1.vgtest \ > + insn_test_ld_add_X1.stdout.exp insn_test_ld_add_X1.stderr.exp \ > + insn_test_ld_add_X1.vgtest \ > + insn_test_ldna_X1.stdout.exp insn_test_ldna_X1.stderr.exp \ > + insn_test_ldna_X1.vgtest \ > + insn_test_ldna_add_X1.stdout.exp insn_test_ldna_add_X1.stderr.exp \ > + insn_test_ldna_add_X1.vgtest \ > + insn_test_ldnt_X1.stdout.exp insn_test_ldnt_X1.stderr.exp \ > + insn_test_ldnt_X1.vgtest \ > + insn_test_ldnt1s_X1.stdout.exp insn_test_ldnt1s_X1.stderr.exp \ > + insn_test_ldnt1s_X1.vgtest \ > + insn_test_ldnt1s_add_X1.stdout.exp insn_test_ldnt1s_add_X1.stderr.exp \ > + insn_test_ldnt1s_add_X1.vgtest \ > + insn_test_ldnt1u_X1.stdout.exp insn_test_ldnt1u_X1.stderr.exp \ > + insn_test_ldnt1u_X1.vgtest \ > + insn_test_ldnt1u_add_X1.stdout.exp insn_test_ldnt1u_add_X1.stderr.exp \ > + insn_test_ldnt1u_add_X1.vgtest \ > + insn_test_ldnt2s_X1.stdout.exp insn_test_ldnt2s_X1.stderr.exp \ > + insn_test_ldnt2s_X1.vgtest \ > + insn_test_ldnt2s_add_X1.stdout.exp insn_test_ldnt2s_add_X1.stderr.exp \ > + insn_test_ldnt2s_add_X1.vgtest \ > + insn_test_ldnt2u_add_X1.stdout.exp insn_test_ldnt2u_add_X1.stderr.exp \ > + insn_test_ldnt2u_add_X1.vgtest \ > + insn_test_ldnt4s_X1.stdout.exp insn_test_ldnt4s_X1.stderr.exp \ > + insn_test_ldnt4s_X1.vgtest \ > + insn_test_ldnt4s_add_X1.stdout.exp insn_test_ldnt4s_add_X1.stderr.exp \ > + insn_test_ldnt4s_add_X1.vgtest \ > + insn_test_ldnt4u_X1.stdout.exp insn_test_ldnt4u_X1.stderr.exp \ > + insn_test_ldnt4u_X1.vgtest \ > + insn_test_ldnt4u_add_X1.stdout.exp insn_test_ldnt4u_add_X1.stderr.exp \ > + insn_test_ldnt4u_add_X1.vgtest \ > + insn_test_ldnt_add_X1.stdout.exp insn_test_ldnt_add_X1.stderr.exp \ > + insn_test_ldnt_add_X1.vgtest \ > + insn_test_lnk_X1.stdout.exp insn_test_lnk_X1.stderr.exp \ > + insn_test_lnk_X1.vgtest \ > + insn_test_lnk_Y1.stdout.exp insn_test_lnk_Y1.stderr.exp \ > + insn_test_lnk_Y1.vgtest \ > + insn_test_mf_X1.stdout.exp insn_test_mf_X1.stderr.exp \ > + insn_test_mf_X1.vgtest \ > + insn_test_mm_X0.stdout.exp insn_test_mm_X0.stderr.exp \ > + insn_test_mm_X0.vgtest \ > + insn_test_mnz_X0.stdout.exp insn_test_mnz_X0.stderr.exp \ > + insn_test_mnz_X0.vgtest \ > + insn_test_mnz_X1.stdout.exp insn_test_mnz_X1.stderr.exp \ > + insn_test_mnz_X1.vgtest \ > + insn_test_mnz_Y0.stdout.exp insn_test_mnz_Y0.stderr.exp \ > + insn_test_mnz_Y0.vgtest \ > + insn_test_mnz_Y1.stdout.exp insn_test_mnz_Y1.stderr.exp \ > + insn_test_mnz_Y1.vgtest \ > + insn_test_mul_hs_hs_X0.stdout.exp insn_test_mul_hs_hs_X0.stderr.exp \ > + insn_test_mul_hs_hs_X0.vgtest \ > + insn_test_mul_hs_hs_Y0.stdout.exp insn_test_mul_hs_hs_Y0.stderr.exp \ > + insn_test_mul_hs_hs_Y0.vgtest \ > + insn_test_mul_hs_hu_X0.stdout.exp insn_test_mul_hs_hu_X0.stderr.exp \ > + insn_test_mul_hs_hu_X0.vgtest \ > + insn_test_mul_hs_ls_X0.stdout.exp insn_test_mul_hs_ls_X0.stderr.exp \ > + insn_test_mul_hs_ls_X0.vgtest \ > + insn_test_mul_hs_lu_X0.stdout.exp insn_test_mul_hs_lu_X0.stderr.exp \ > + insn_test_mul_hs_lu_X0.vgtest \ > + insn_test_mul_hu_hu_X0.stdout.exp insn_test_mul_hu_hu_X0.stderr.exp \ > + insn_test_mul_hu_hu_X0.vgtest \ > + insn_test_mul_hu_hu_Y0.stdout.exp insn_test_mul_hu_hu_Y0.stderr.exp \ > + insn_test_mul_hu_hu_Y0.vgtest \ > + insn_test_mul_hu_lu_X0.stdout.exp insn_test_mul_hu_lu_X0.stderr.exp \ > + insn_test_mul_hu_lu_X0.vgtest \ > + insn_test_mul_ls_ls_X0.stdout.exp insn_test_mul_ls_ls_X0.stderr.exp \ > + insn_test_mul_ls_ls_X0.vgtest \ > + insn_test_mul_ls_ls_Y0.stdout.exp insn_test_mul_ls_ls_Y0.stderr.exp \ > + insn_test_mul_ls_ls_Y0.vgtest \ > + insn_test_mul_ls_lu_X0.stdout.exp insn_test_mul_ls_lu_X0.stderr.exp \ > + insn_test_mul_ls_lu_X0.vgtest \ > + insn_test_mul_lu_lu_X0.stdout.exp insn_test_mul_lu_lu_X0.stderr.exp \ > + insn_test_mul_lu_lu_X0.vgtest \ > + insn_test_mul_lu_lu_Y0.stdout.exp insn_test_mul_lu_lu_Y0.stderr.exp \ > + insn_test_mul_lu_lu_Y0.vgtest \ > + insn_test_mula_hs_hs_X0.stdout.exp insn_test_mula_hs_hs_X0.stderr.exp \ > + insn_test_mula_hs_hs_X0.vgtest \ > + insn_test_mula_hs_hs_Y0.stdout.exp insn_test_mula_hs_hs_Y0.stderr.exp \ > + insn_test_mula_hs_hs_Y0.vgtest \ > + insn_test_mula_hs_hu_X0.stdout.exp insn_test_mula_hs_hu_X0.stderr.exp \ > + insn_test_mula_hs_hu_X0.vgtest \ > + insn_test_mula_hs_ls_X0.stdout.exp insn_test_mula_hs_ls_X0.stderr.exp \ > + insn_test_mula_hs_ls_X0.vgtest \ > + insn_test_mula_hs_lu_X0.stdout.exp insn_test_mula_hs_lu_X0.stderr.exp \ > + insn_test_mula_hs_lu_X0.vgtest \ > + insn_test_mula_hu_hu_X0.stdout.exp insn_test_mula_hu_hu_X0.stderr.exp \ > + insn_test_mula_hu_hu_X0.vgtest \ > + insn_test_mula_hu_hu_Y0.stdout.exp insn_test_mula_hu_hu_Y0.stderr.exp \ > + insn_test_mula_hu_hu_Y0.vgtest \ > + insn_test_mula_hu_ls_X0.stdout.exp insn_test_mula_hu_ls_X0.stderr.exp \ > + insn_test_mula_hu_ls_X0.vgtest \ > + insn_test_mula_hu_lu_X0.stdout.exp insn_test_mula_hu_lu_X0.stderr.exp \ > + insn_test_mula_hu_lu_X0.vgtest \ > + insn_test_mula_ls_ls_X0.stdout.exp insn_test_mula_ls_ls_X0.stderr.exp \ > + insn_test_mula_ls_ls_X0.vgtest \ > + insn_test_mula_ls_ls_Y0.stdout.exp insn_test_mula_ls_ls_Y0.stderr.exp \ > + insn_test_mula_ls_ls_Y0.vgtest \ > + insn_test_mula_ls_lu_X0.stdout.exp insn_test_mula_ls_lu_X0.stderr.exp \ > + insn_test_mula_ls_lu_X0.vgtest \ > + insn_test_mula_lu_lu_X0.stdout.exp insn_test_mula_lu_lu_X0.stderr.exp \ > + insn_test_mula_lu_lu_X0.vgtest \ > + insn_test_mula_lu_lu_Y0.stdout.exp insn_test_mula_lu_lu_Y0.stderr.exp \ > + insn_test_mula_lu_lu_Y0.vgtest \ > + insn_test_mulax_X0.stdout.exp insn_test_mulax_X0.stderr.exp \ > + insn_test_mulax_X0.vgtest \ > + insn_test_mulax_Y0.stdout.exp insn_test_mulax_Y0.stderr.exp \ > + insn_test_mulax_Y0.vgtest \ > + insn_test_mulx_X0.stdout.exp insn_test_mulx_X0.stderr.exp \ > + insn_test_mulx_X0.vgtest \ > + insn_test_mulx_Y0.stdout.exp insn_test_mulx_Y0.stderr.exp \ > + insn_test_mulx_Y0.vgtest \ > + insn_test_mz_X0.stdout.exp insn_test_mz_X0.stderr.exp \ > + insn_test_mz_X0.vgtest \ > + insn_test_mz_X1.stdout.exp insn_test_mz_X1.stderr.exp \ > + insn_test_mz_X1.vgtest \ > + insn_test_mz_Y0.stdout.exp insn_test_mz_Y0.stderr.exp \ > + insn_test_mz_Y0.vgtest \ > + insn_test_mz_Y1.stdout.exp insn_test_mz_Y1.stderr.exp \ > + insn_test_mz_Y1.vgtest \ > + insn_test_nop_X0.stdout.exp insn_test_nop_X0.stderr.exp \ > + insn_test_nop_X0.vgtest \ > + insn_test_nop_X1.stdout.exp insn_test_nop_X1.stderr.exp \ > + insn_test_nop_X1.vgtest \ > + insn_test_nop_Y0.stdout.exp insn_test_nop_Y0.stderr.exp \ > + insn_test_nop_Y0.vgtest \ > + insn_test_nop_Y1.stdout.exp insn_test_nop_Y1.stderr.exp \ > + insn_test_nop_Y1.vgtest \ > + insn_test_nor_X0.stdout.exp insn_test_nor_X0.stderr.exp \ > + insn_test_nor_X0.vgtest \ > + insn_test_nor_X1.stdout.exp insn_test_nor_X1.stderr.exp \ > + insn_test_nor_X1.vgtest \ > + insn_test_nor_Y0.stdout.exp insn_test_nor_Y0.stderr.exp \ > + insn_test_nor_Y0.vgtest \ > + insn_test_nor_Y1.stdout.exp insn_test_nor_Y1.stderr.exp \ > + insn_test_nor_Y1.vgtest \ > + insn_test_or_X0.stdout.exp insn_test_or_X0.stderr.exp \ > + insn_test_or_X0.vgtest \ > + insn_test_or_X1.stdout.exp insn_test_or_X1.stderr.exp \ > + insn_test_or_X1.vgtest \ > + insn_test_or_Y0.stdout.exp insn_test_or_Y0.stderr.exp \ > + insn_test_or_Y0.vgtest \ > + insn_test_or_Y1.stdout.exp insn_test_or_Y1.stderr.exp \ > + insn_test_or_Y1.vgtest \ > + insn_test_ori_X0.stdout.exp insn_test_ori_X0.stderr.exp \ > + insn_test_ori_X0.vgtest \ > + insn_test_ori_X1.stdout.exp insn_test_ori_X1.stderr.exp \ > + insn_test_ori_X1.vgtest \ > + insn_test_pcnt_X0.stdout.exp insn_test_pcnt_X0.stderr.exp \ > + insn_test_pcnt_X0.vgtest \ > + insn_test_pcnt_Y0.stdout.exp insn_test_pcnt_Y0.stderr.exp \ > + insn_test_pcnt_Y0.vgtest \ > + insn_test_revbits_X0.stdout.exp insn_test_revbits_X0.stderr.exp \ > + insn_test_revbits_X0.vgtest \ > + insn_test_revbits_Y0.stdout.exp insn_test_revbits_Y0.stderr.exp \ > + insn_test_revbits_Y0.vgtest \ > + insn_test_revbytes_X0.stdout.exp insn_test_revbytes_X0.stderr.exp \ > + insn_test_revbytes_X0.vgtest \ > + insn_test_revbytes_Y0.stdout.exp insn_test_revbytes_Y0.stderr.exp \ > + insn_test_revbytes_Y0.vgtest \ > + insn_test_rotl_X0.stdout.exp insn_test_rotl_X0.stderr.exp \ > + insn_test_rotl_X0.vgtest \ > + insn_test_rotl_X1.stdout.exp insn_test_rotl_X1.stderr.exp \ > + insn_test_rotl_X1.vgtest \ > + insn_test_rotl_Y0.stdout.exp insn_test_rotl_Y0.stderr.exp \ > + insn_test_rotl_Y0.vgtest \ > + insn_test_rotl_Y1.stdout.exp insn_test_rotl_Y1.stderr.exp \ > + insn_test_rotl_Y1.vgtest \ > + insn_test_rotli_X0.stdout.exp insn_test_rotli_X0.stderr.exp \ > + insn_test_rotli_X0.vgtest \ > + insn_test_rotli_X1.stdout.exp insn_test_rotli_X1.stderr.exp \ > + insn_test_rotli_X1.vgtest \ > + insn_test_rotli_Y0.stdout.exp insn_test_rotli_Y0.stderr.exp \ > + insn_test_rotli_Y0.vgtest \ > + insn_test_rotli_Y1.stdout.exp insn_test_rotli_Y1.stderr.exp \ > + insn_test_rotli_Y1.vgtest \ > + insn_test_shl_X0.stdout.exp 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insn_test_shl1addx_X0.stdout.exp insn_test_shl1addx_X0.stderr.exp \ > + insn_test_shl1addx_X0.vgtest \ > + insn_test_shl1addx_X1.stdout.exp insn_test_shl1addx_X1.stderr.exp \ > + insn_test_shl1addx_X1.vgtest \ > + insn_test_shl1addx_Y0.stdout.exp insn_test_shl1addx_Y0.stderr.exp \ > + insn_test_shl1addx_Y0.vgtest \ > + insn_test_shl1addx_Y1.stdout.exp insn_test_shl1addx_Y1.stderr.exp \ > + insn_test_shl1addx_Y1.vgtest \ > + insn_test_shl2add_X0.stdout.exp insn_test_shl2add_X0.stderr.exp \ > + insn_test_shl2add_X0.vgtest \ > + insn_test_shl2add_X1.stdout.exp insn_test_shl2add_X1.stderr.exp \ > + insn_test_shl2add_X1.vgtest \ > + insn_test_shl2add_Y0.stdout.exp insn_test_shl2add_Y0.stderr.exp \ > + insn_test_shl2add_Y0.vgtest \ > + insn_test_shl2add_Y1.stdout.exp insn_test_shl2add_Y1.stderr.exp \ > + insn_test_shl2add_Y1.vgtest \ > + insn_test_shl2addx_X0.stdout.exp insn_test_shl2addx_X0.stderr.exp \ > + insn_test_shl2addx_X0.vgtest \ > + insn_test_shl2addx_X1.stdout.exp insn_test_shl2addx_X1.stderr.exp \ > + insn_test_shl2addx_X1.vgtest \ > + insn_test_shl2addx_Y0.stdout.exp insn_test_shl2addx_Y0.stderr.exp \ > + insn_test_shl2addx_Y0.vgtest \ > + insn_test_shl2addx_Y1.stdout.exp insn_test_shl2addx_Y1.stderr.exp \ > + insn_test_shl2addx_Y1.vgtest \ > + insn_test_shl3add_X0.stdout.exp insn_test_shl3add_X0.stderr.exp \ > + insn_test_shl3add_X0.vgtest \ > + insn_test_shl3add_X1.stdout.exp insn_test_shl3add_X1.stderr.exp \ > + insn_test_shl3add_X1.vgtest \ > + insn_test_shl3add_Y0.stdout.exp insn_test_shl3add_Y0.stderr.exp \ > + insn_test_shl3add_Y0.vgtest \ > + insn_test_shl3add_Y1.stdout.exp insn_test_shl3add_Y1.stderr.exp \ > + insn_test_shl3add_Y1.vgtest \ > + insn_test_shl3addx_X0.stdout.exp insn_test_shl3addx_X0.stderr.exp \ > + insn_test_shl3addx_X0.vgtest \ > + insn_test_shl3addx_X1.stdout.exp insn_test_shl3addx_X1.stderr.exp \ > + insn_test_shl3addx_X1.vgtest \ > + insn_test_shl3addx_Y0.stdout.exp insn_test_shl3addx_Y0.stderr.exp \ > + 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+ insn_test_shrs_X1.stdout.exp insn_test_shrs_X1.stderr.exp \ > + insn_test_shrs_X1.vgtest \ > + insn_test_shrs_Y0.stdout.exp insn_test_shrs_Y0.stderr.exp \ > + insn_test_shrs_Y0.vgtest \ > + insn_test_shrs_Y1.stdout.exp insn_test_shrs_Y1.stderr.exp \ > + insn_test_shrs_Y1.vgtest \ > + insn_test_shrsi_X0.stdout.exp insn_test_shrsi_X0.stderr.exp \ > + insn_test_shrsi_X0.vgtest \ > + insn_test_shrsi_X1.stdout.exp insn_test_shrsi_X1.stderr.exp \ > + insn_test_shrsi_X1.vgtest \ > + insn_test_shrsi_Y0.stdout.exp insn_test_shrsi_Y0.stderr.exp \ > + insn_test_shrsi_Y0.vgtest \ > + insn_test_shrsi_Y1.stdout.exp insn_test_shrsi_Y1.stderr.exp \ > + insn_test_shrsi_Y1.vgtest \ > + insn_test_shru_X0.stdout.exp insn_test_shru_X0.stderr.exp \ > + insn_test_shru_X0.vgtest \ > + insn_test_shru_X1.stdout.exp insn_test_shru_X1.stderr.exp \ > + insn_test_shru_X1.vgtest \ > + insn_test_shru_Y0.stdout.exp insn_test_shru_Y0.stderr.exp \ > + insn_test_shru_Y0.vgtest \ > + insn_test_shru_Y1.stdout.exp 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> + insn_test_v1cmpeq_X1.stdout.exp insn_test_v1cmpeq_X1.stderr.exp \ > + insn_test_v1cmpeq_X1.vgtest \ > + insn_test_v1cmpeqi_X0.stdout.exp insn_test_v1cmpeqi_X0.stderr.exp \ > + insn_test_v1cmpeqi_X0.vgtest \ > + insn_test_v1cmpeqi_X1.stdout.exp insn_test_v1cmpeqi_X1.stderr.exp \ > + insn_test_v1cmpeqi_X1.vgtest \ > + insn_test_v1cmples_X0.stdout.exp insn_test_v1cmples_X0.stderr.exp \ > + insn_test_v1cmples_X0.vgtest \ > + insn_test_v1cmples_X1.stdout.exp insn_test_v1cmples_X1.stderr.exp \ > + insn_test_v1cmples_X1.vgtest \ > + insn_test_v1cmpleu_X0.stdout.exp insn_test_v1cmpleu_X0.stderr.exp \ > + insn_test_v1cmpleu_X0.vgtest \ > + insn_test_v1cmpleu_X1.stdout.exp insn_test_v1cmpleu_X1.stderr.exp \ > + insn_test_v1cmpleu_X1.vgtest \ > + insn_test_v1cmplts_X0.stdout.exp insn_test_v1cmplts_X0.stderr.exp \ > + insn_test_v1cmplts_X0.vgtest \ > + insn_test_v1cmplts_X1.stdout.exp insn_test_v1cmplts_X1.stderr.exp \ > + insn_test_v1cmplts_X1.vgtest \ > + insn_test_v1cmpltu_X0.stdout.exp insn_test_v1cmpltu_X0.stderr.exp \ > + insn_test_v1cmpltu_X0.vgtest \ > + insn_test_v1cmpltu_X1.stdout.exp insn_test_v1cmpltu_X1.stderr.exp \ > + insn_test_v1cmpltu_X1.vgtest \ > + insn_test_v1cmpne_X0.stdout.exp insn_test_v1cmpne_X0.stderr.exp \ > + insn_test_v1cmpne_X0.vgtest \ > + insn_test_v1cmpne_X1.stdout.exp insn_test_v1cmpne_X1.stderr.exp \ > + insn_test_v1cmpne_X1.vgtest \ > + insn_test_v1ddotpu_X0.stdout.exp insn_test_v1ddotpu_X0.stderr.exp \ > + insn_test_v1ddotpu_X0.vgtest \ > + insn_test_v1ddotpua_X0.stdout.exp insn_test_v1ddotpua_X0.stderr.exp \ > + insn_test_v1ddotpua_X0.vgtest \ > + insn_test_v1ddotpus_X0.stdout.exp insn_test_v1ddotpus_X0.stderr.exp \ > + insn_test_v1ddotpus_X0.vgtest \ > + insn_test_v1ddotpusa_X0.stdout.exp insn_test_v1ddotpusa_X0.stderr.exp \ > + insn_test_v1ddotpusa_X0.vgtest \ > + insn_test_v1dotp_X0.stdout.exp insn_test_v1dotp_X0.stderr.exp \ > + insn_test_v1dotp_X0.vgtest \ > + insn_test_v1dotpa_X0.stdout.exp insn_test_v1dotpa_X0.stderr.exp \ > + insn_test_v1dotpa_X0.vgtest \ > + insn_test_v1dotpu_X0.stdout.exp insn_test_v1dotpu_X0.stderr.exp \ > + insn_test_v1dotpu_X0.vgtest \ > + insn_test_v1dotpua_X0.stdout.exp insn_test_v1dotpua_X0.stderr.exp \ > + insn_test_v1dotpua_X0.vgtest \ > + insn_test_v1dotpus_X0.stdout.exp insn_test_v1dotpus_X0.stderr.exp \ > + insn_test_v1dotpus_X0.vgtest \ > + insn_test_v1dotpusa_X0.stdout.exp insn_test_v1dotpusa_X0.stderr.exp \ > + insn_test_v1dotpusa_X0.vgtest \ > + insn_test_v1int_h_X0.stdout.exp insn_test_v1int_h_X0.stderr.exp \ > + insn_test_v1int_h_X0.vgtest \ > + insn_test_v1int_h_X1.stdout.exp insn_test_v1int_h_X1.stderr.exp \ > + insn_test_v1int_h_X1.vgtest \ > + insn_test_v1int_l_X0.stdout.exp insn_test_v1int_l_X0.stderr.exp \ > + insn_test_v1int_l_X0.vgtest \ > + insn_test_v1int_l_X1.stdout.exp insn_test_v1int_l_X1.stderr.exp \ > + insn_test_v1int_l_X1.vgtest \ > + insn_test_v1maxu_X0.stdout.exp insn_test_v1maxu_X0.stderr.exp \ > + insn_test_v1maxu_X0.vgtest \ > + insn_test_v1maxu_X1.stdout.exp insn_test_v1maxu_X1.stderr.exp \ > + insn_test_v1maxu_X1.vgtest \ > + insn_test_v1minu_X0.stdout.exp insn_test_v1minu_X0.stderr.exp \ > + insn_test_v1minu_X0.vgtest \ > + insn_test_v1minu_X1.stdout.exp insn_test_v1minu_X1.stderr.exp \ > + insn_test_v1minu_X1.vgtest \ > + insn_test_v1mnz_X0.stdout.exp insn_test_v1mnz_X0.stderr.exp \ > + insn_test_v1mnz_X0.vgtest \ > + insn_test_v1mnz_X1.stdout.exp insn_test_v1mnz_X1.stderr.exp \ > + insn_test_v1mnz_X1.vgtest \ > + insn_test_v1multu_X0.stdout.exp insn_test_v1multu_X0.stderr.exp \ > + insn_test_v1multu_X0.vgtest \ > + insn_test_v1mulu_X0.stdout.exp insn_test_v1mulu_X0.stderr.exp \ > + insn_test_v1mulu_X0.vgtest \ > + insn_test_v1mulus_X0.stdout.exp insn_test_v1mulus_X0.stderr.exp \ > + insn_test_v1mulus_X0.vgtest \ > + insn_test_v1mz_X0.stdout.exp insn_test_v1mz_X0.stderr.exp \ > + insn_test_v1mz_X0.vgtest \ > + insn_test_v1mz_X1.stdout.exp insn_test_v1mz_X1.stderr.exp \ > + insn_test_v1mz_X1.vgtest \ > + insn_test_v1sadau_X0.stdout.exp insn_test_v1sadau_X0.stderr.exp \ > + insn_test_v1sadau_X0.vgtest \ > + insn_test_v1sadu_X0.stdout.exp insn_test_v1sadu_X0.stderr.exp \ > + insn_test_v1sadu_X0.vgtest \ > + insn_test_v1shl_X0.stdout.exp insn_test_v1shl_X0.stderr.exp \ > + insn_test_v1shl_X0.vgtest \ > + insn_test_v1shl_X1.stdout.exp insn_test_v1shl_X1.stderr.exp \ > + insn_test_v1shl_X1.vgtest \ > + insn_test_v1shli_X0.stdout.exp insn_test_v1shli_X0.stderr.exp \ > + insn_test_v1shli_X0.vgtest \ > + insn_test_v1shli_X1.stdout.exp insn_test_v1shli_X1.stderr.exp \ > + insn_test_v1shli_X1.vgtest \ > + insn_test_v1shrs_X0.stdout.exp insn_test_v1shrs_X0.stderr.exp \ > + insn_test_v1shrs_X0.vgtest \ > + insn_test_v1shrs_X1.stdout.exp insn_test_v1shrs_X1.stderr.exp \ > + insn_test_v1shrs_X1.vgtest \ > + insn_test_v1shrsi_X0.stdout.exp insn_test_v1shrsi_X0.stderr.exp \ > + insn_test_v1shrsi_X0.vgtest \ > + insn_test_v1shrsi_X1.stdout.exp insn_test_v1shrsi_X1.stderr.exp \ > + insn_test_v1shrsi_X1.vgtest \ > + insn_test_v1shru_X0.stdout.exp insn_test_v1shru_X0.stderr.exp \ > + insn_test_v1shru_X0.vgtest \ > + insn_test_v1shru_X1.stdout.exp insn_test_v1shru_X1.stderr.exp \ > + insn_test_v1shru_X1.vgtest \ > + insn_test_v1shrui_X0.stdout.exp insn_test_v1shrui_X0.stderr.exp \ > + insn_test_v1shrui_X0.vgtest \ > + insn_test_v1shrui_X1.stdout.exp insn_test_v1shrui_X1.stderr.exp \ > + insn_test_v1shrui_X1.vgtest \ > + insn_test_v1sub_X0.stdout.exp insn_test_v1sub_X0.stderr.exp \ > + insn_test_v1sub_X0.vgtest \ > + insn_test_v1sub_X1.stdout.exp insn_test_v1sub_X1.stderr.exp \ > + insn_test_v1sub_X1.vgtest \ > + insn_test_v1subuc_X0.stdout.exp insn_test_v1subuc_X0.stderr.exp \ > + insn_test_v1subuc_X0.vgtest \ > + insn_test_v1subuc_X1.stdout.exp insn_test_v1subuc_X1.stderr.exp \ > + insn_test_v1subuc_X1.vgtest \ > + insn_test_v2add_X0.stdout.exp insn_test_v2add_X0.stderr.exp \ > + insn_test_v2add_X0.vgtest \ > + insn_test_v2add_X1.stdout.exp insn_test_v2add_X1.stderr.exp \ > + insn_test_v2add_X1.vgtest \ > + insn_test_v2addsc_X0.stdout.exp insn_test_v2addsc_X0.stderr.exp \ > + insn_test_v2addsc_X0.vgtest \ > + insn_test_v2addsc_X1.stdout.exp insn_test_v2addsc_X1.stderr.exp \ > + insn_test_v2addsc_X1.vgtest \ > + insn_test_v2adiffs_X0.stdout.exp insn_test_v2adiffs_X0.stderr.exp \ > + insn_test_v2adiffs_X0.vgtest \ > + insn_test_v2avgs_X0.stdout.exp insn_test_v2avgs_X0.stderr.exp \ > + insn_test_v2avgs_X0.vgtest \ > + insn_test_v2cmpeq_X0.stdout.exp insn_test_v2cmpeq_X0.stderr.exp \ > + insn_test_v2cmpeq_X0.vgtest \ > + insn_test_v2cmpeq_X1.stdout.exp insn_test_v2cmpeq_X1.stderr.exp \ > + insn_test_v2cmpeq_X1.vgtest \ > + insn_test_v2cmpeqi_X0.stdout.exp insn_test_v2cmpeqi_X0.stderr.exp \ > + insn_test_v2cmpeqi_X0.vgtest \ > + insn_test_v2cmpeqi_X1.stdout.exp insn_test_v2cmpeqi_X1.stderr.exp \ > + insn_test_v2cmpeqi_X1.vgtest \ > + insn_test_v2cmples_X0.stdout.exp insn_test_v2cmples_X0.stderr.exp \ > + insn_test_v2cmples_X0.vgtest \ > + insn_test_v2cmples_X1.stdout.exp insn_test_v2cmples_X1.stderr.exp \ > + insn_test_v2cmples_X1.vgtest \ > + insn_test_v2cmpleu_X0.stdout.exp insn_test_v2cmpleu_X0.stderr.exp \ > + insn_test_v2cmpleu_X0.vgtest \ > + insn_test_v2cmpleu_X1.stdout.exp insn_test_v2cmpleu_X1.stderr.exp \ > + insn_test_v2cmpleu_X1.vgtest \ > + insn_test_v2cmplts_X0.stdout.exp insn_test_v2cmplts_X0.stderr.exp \ > + insn_test_v2cmplts_X0.vgtest \ > + insn_test_v2cmplts_X1.stdout.exp insn_test_v2cmplts_X1.stderr.exp \ > + insn_test_v2cmplts_X1.vgtest \ > + insn_test_v2cmpltsi_X0.stdout.exp insn_test_v2cmpltsi_X0.stderr.exp \ > + insn_test_v2cmpltsi_X0.vgtest \ > + insn_test_v2cmpltsi_X1.stdout.exp insn_test_v2cmpltsi_X1.stderr.exp \ > + insn_test_v2cmpltsi_X1.vgtest \ > + insn_test_v2cmpltu_X0.stdout.exp insn_test_v2cmpltu_X0.stderr.exp \ > + insn_test_v2cmpltu_X0.vgtest \ > + insn_test_v2cmpltu_X1.stdout.exp insn_test_v2cmpltu_X1.stderr.exp \ > + insn_test_v2cmpltu_X1.vgtest \ > + insn_test_v2cmpltui_X0.stdout.exp insn_test_v2cmpltui_X0.stderr.exp \ > + insn_test_v2cmpltui_X0.vgtest \ > + insn_test_v2cmpltui_X1.stdout.exp insn_test_v2cmpltui_X1.stderr.exp \ > + insn_test_v2cmpltui_X1.vgtest \ > + insn_test_v2cmpne_X0.stdout.exp insn_test_v2cmpne_X0.stderr.exp \ > + insn_test_v2cmpne_X0.vgtest \ > + insn_test_v2cmpne_X1.stdout.exp insn_test_v2cmpne_X1.stderr.exp \ > + insn_test_v2cmpne_X1.vgtest \ > + insn_test_v2dotp_X0.stdout.exp insn_test_v2dotp_X0.stderr.exp \ > + insn_test_v2dotp_X0.vgtest \ > + insn_test_v2dotpa_X0.stdout.exp insn_test_v2dotpa_X0.stderr.exp \ > + insn_test_v2dotpa_X0.vgtest \ > + insn_test_v2int_h_X0.stdout.exp insn_test_v2int_h_X0.stderr.exp \ > + insn_test_v2int_h_X0.vgtest \ > + insn_test_v2int_h_X1.stdout.exp insn_test_v2int_h_X1.stderr.exp \ > + insn_test_v2int_h_X1.vgtest \ > + insn_test_v2int_l_X0.stdout.exp insn_test_v2int_l_X0.stderr.exp \ > + insn_test_v2int_l_X0.vgtest \ > + insn_test_v2int_l_X1.stdout.exp insn_test_v2int_l_X1.stderr.exp \ > + insn_test_v2int_l_X1.vgtest \ > + insn_test_v2maxs_X0.stdout.exp insn_test_v2maxs_X0.stderr.exp \ > + insn_test_v2maxs_X0.vgtest \ > + insn_test_v2maxs_X1.stdout.exp insn_test_v2maxs_X1.stderr.exp \ > + insn_test_v2maxs_X1.vgtest \ > + insn_test_v2mins_X0.stdout.exp insn_test_v2mins_X0.stderr.exp \ > + insn_test_v2mins_X0.vgtest \ > + insn_test_v2mins_X1.stdout.exp insn_test_v2mins_X1.stderr.exp \ > + insn_test_v2mins_X1.vgtest \ > + insn_test_v2mnz_X0.stdout.exp insn_test_v2mnz_X0.stderr.exp \ > + insn_test_v2mnz_X0.vgtest \ > + insn_test_v2mnz_X1.stdout.exp insn_test_v2mnz_X1.stderr.exp \ > + insn_test_v2mnz_X1.vgtest \ > + insn_test_v2mulfsc_X0.stdout.exp insn_test_v2mulfsc_X0.stderr.exp \ > + insn_test_v2mulfsc_X0.vgtest \ > + insn_test_v2muls_X0.stdout.exp insn_test_v2muls_X0.stderr.exp \ > + insn_test_v2muls_X0.vgtest \ > + insn_test_v2mults_X0.stdout.exp insn_test_v2mults_X0.stderr.exp \ > + insn_test_v2mults_X0.vgtest \ > + insn_test_v2mz_X0.stdout.exp insn_test_v2mz_X0.stderr.exp \ > + insn_test_v2mz_X0.vgtest \ > + insn_test_v2mz_X1.stdout.exp insn_test_v2mz_X1.stderr.exp \ > + insn_test_v2mz_X1.vgtest \ > + insn_test_v2packh_X0.stdout.exp insn_test_v2packh_X0.stderr.exp \ > + insn_test_v2packh_X0.vgtest \ > + insn_test_v2packh_X1.stdout.exp insn_test_v2packh_X1.stderr.exp \ > + insn_test_v2packh_X1.vgtest \ > + insn_test_v2packl_X0.stdout.exp insn_test_v2packl_X0.stderr.exp \ > + insn_test_v2packl_X0.vgtest \ > + insn_test_v2packl_X1.stdout.exp insn_test_v2packl_X1.stderr.exp \ > + insn_test_v2packl_X1.vgtest \ > + insn_test_v2packuc_X0.stdout.exp insn_test_v2packuc_X0.stderr.exp \ > + insn_test_v2packuc_X0.vgtest \ > + insn_test_v2packuc_X1.stdout.exp insn_test_v2packuc_X1.stderr.exp \ > + insn_test_v2packuc_X1.vgtest \ > + insn_test_v2sadas_X0.stdout.exp insn_test_v2sadas_X0.stderr.exp \ > + insn_test_v2sadas_X0.vgtest \ > + insn_test_v2sadau_X0.stdout.exp insn_test_v2sadau_X0.stderr.exp \ > + insn_test_v2sadau_X0.vgtest \ > + insn_test_v2sads_X0.stdout.exp insn_test_v2sads_X0.stderr.exp \ > + insn_test_v2sads_X0.vgtest \ > + insn_test_v2sadu_X0.stdout.exp insn_test_v2sadu_X0.stderr.exp \ > + insn_test_v2sadu_X0.vgtest \ > + insn_test_v2shl_X0.stdout.exp insn_test_v2shl_X0.stderr.exp \ > + insn_test_v2shl_X0.vgtest \ > + insn_test_v2shl_X1.stdout.exp insn_test_v2shl_X1.stderr.exp \ > + insn_test_v2shl_X1.vgtest \ > + insn_test_v2shli_X0.stdout.exp insn_test_v2shli_X0.stderr.exp \ > + insn_test_v2shli_X0.vgtest \ > + insn_test_v2shli_X1.stdout.exp insn_test_v2shli_X1.stderr.exp \ > + insn_test_v2shli_X1.vgtest \ > + insn_test_v2shlsc_X0.stdout.exp insn_test_v2shlsc_X0.stderr.exp \ > + insn_test_v2shlsc_X0.vgtest \ > + insn_test_v2shlsc_X1.stdout.exp insn_test_v2shlsc_X1.stderr.exp \ > + insn_test_v2shlsc_X1.vgtest \ > + insn_test_v2shrs_X0.stdout.exp insn_test_v2shrs_X0.stderr.exp \ > + insn_test_v2shrs_X0.vgtest \ > + insn_test_v2shrs_X1.stdout.exp insn_test_v2shrs_X1.stderr.exp \ > + insn_test_v2shrs_X1.vgtest \ > + insn_test_v2shrsi_X0.stdout.exp insn_test_v2shrsi_X0.stderr.exp \ > + insn_test_v2shrsi_X0.vgtest \ > + insn_test_v2shrsi_X1.stdout.exp insn_test_v2shrsi_X1.stderr.exp \ > + insn_test_v2shrsi_X1.vgtest \ > + insn_test_v2shru_X0.stdout.exp insn_test_v2shru_X0.stderr.exp \ > + insn_test_v2shru_X0.vgtest \ > + insn_test_v2shru_X1.stdout.exp insn_test_v2shru_X1.stderr.exp \ > + insn_test_v2shru_X1.vgtest \ > + insn_test_v2shrui_X0.stdout.exp insn_test_v2shrui_X0.stderr.exp \ > + insn_test_v2shrui_X0.vgtest \ > + insn_test_v2shrui_X1.stdout.exp insn_test_v2shrui_X1.stderr.exp \ > + insn_test_v2shrui_X1.vgtest \ > + insn_test_v2sub_X0.stdout.exp insn_test_v2sub_X0.stderr.exp \ > + insn_test_v2sub_X0.vgtest \ > + insn_test_v2sub_X1.stdout.exp insn_test_v2sub_X1.stderr.exp \ > + insn_test_v2sub_X1.vgtest \ > + insn_test_v2subsc_X0.stdout.exp insn_test_v2subsc_X0.stderr.exp \ > + insn_test_v2subsc_X0.vgtest \ > + insn_test_v2subsc_X1.stdout.exp insn_test_v2subsc_X1.stderr.exp \ > + insn_test_v2subsc_X1.vgtest \ > + insn_test_v4add_X0.stdout.exp insn_test_v4add_X0.stderr.exp \ > + insn_test_v4add_X0.vgtest \ > + insn_test_v4add_X1.stdout.exp insn_test_v4add_X1.stderr.exp \ > + insn_test_v4add_X1.vgtest \ > + insn_test_v4addsc_X0.stdout.exp insn_test_v4addsc_X0.stderr.exp \ > + insn_test_v4addsc_X0.vgtest \ > + insn_test_v4addsc_X1.stdout.exp insn_test_v4addsc_X1.stderr.exp \ > + insn_test_v4addsc_X1.vgtest \ > + insn_test_v4int_h_X0.stdout.exp insn_test_v4int_h_X0.stderr.exp \ > + insn_test_v4int_h_X0.vgtest \ > + insn_test_v4int_h_X1.stdout.exp insn_test_v4int_h_X1.stderr.exp \ > + insn_test_v4int_h_X1.vgtest \ > + insn_test_v4int_l_X0.stdout.exp insn_test_v4int_l_X0.stderr.exp \ > + insn_test_v4int_l_X0.vgtest \ > + insn_test_v4int_l_X1.stdout.exp insn_test_v4int_l_X1.stderr.exp \ > + insn_test_v4int_l_X1.vgtest \ > + insn_test_v4packsc_X0.stdout.exp insn_test_v4packsc_X0.stderr.exp \ > + insn_test_v4packsc_X0.vgtest \ > + insn_test_v4packsc_X1.stdout.exp insn_test_v4packsc_X1.stderr.exp \ > + insn_test_v4packsc_X1.vgtest \ > + insn_test_v4shl_X0.stdout.exp insn_test_v4shl_X0.stderr.exp \ > + insn_test_v4shl_X0.vgtest \ > + insn_test_v4shl_X1.stdout.exp insn_test_v4shl_X1.stderr.exp \ > + insn_test_v4shl_X1.vgtest \ > + insn_test_v4shlsc_X0.stdout.exp insn_test_v4shlsc_X0.stderr.exp \ > + insn_test_v4shlsc_X0.vgtest \ > + insn_test_v4shlsc_X1.stdout.exp insn_test_v4shlsc_X1.stderr.exp \ > + insn_test_v4shlsc_X1.vgtest \ > + insn_test_v4shrs_X0.stdout.exp insn_test_v4shrs_X0.stderr.exp \ > + insn_test_v4shrs_X0.vgtest \ > + insn_test_v4shrs_X1.stdout.exp insn_test_v4shrs_X1.stderr.exp \ > + insn_test_v4shrs_X1.vgtest \ > + insn_test_v4shru_X0.stdout.exp insn_test_v4shru_X0.stderr.exp \ > + insn_test_v4shru_X0.vgtest \ > + insn_test_v4shru_X1.stdout.exp insn_test_v4shru_X1.stderr.exp \ > + insn_test_v4shru_X1.vgtest \ > + insn_test_v4sub_X0.stdout.exp insn_test_v4sub_X0.stderr.exp \ > + insn_test_v4sub_X0.vgtest \ > + insn_test_v4sub_X1.stdout.exp insn_test_v4sub_X1.stderr.exp \ > + insn_test_v4sub_X1.vgtest \ > + insn_test_v4subsc_X0.stdout.exp insn_test_v4subsc_X0.stderr.exp \ > + insn_test_v4subsc_X0.vgtest \ > + insn_test_v4subsc_X1.stdout.exp insn_test_v4subsc_X1.stderr.exp \ > + insn_test_v4subsc_X1.vgtest \ > + insn_test_wh64_X1.stdout.exp insn_test_wh64_X1.stderr.exp \ > + insn_test_wh64_X1.vgtest \ > + insn_test_xor_X0.stdout.exp insn_test_xor_X0.stderr.exp \ > + insn_test_xor_X0.vgtest \ > + insn_test_xor_X1.stdout.exp insn_test_xor_X1.stderr.exp \ > + insn_test_xor_X1.vgtest \ > + insn_test_xor_Y0.stdout.exp insn_test_xor_Y0.stderr.exp \ > + insn_test_xor_Y0.vgtest \ > + insn_test_xor_Y1.stdout.exp insn_test_xor_Y1.stderr.exp \ > + insn_test_xor_Y1.vgtest \ > + insn_test_xori_X0.stdout.exp insn_test_xori_X0.stderr.exp \ > + insn_test_xori_X0.vgtest \ > + insn_test_xori_X1.stdout.exp insn_test_xori_X1.stderr.exp \ > + insn_test_xori_X1.vgtest > + > +bin_PROGRAMS = gen_insn_test > + > +insn_tests = \ > + insn_test_move_X0 \ > + insn_test_move_X1 \ > + insn_test_move_Y0 \ > + insn_test_move_Y1 \ > + insn_test_movei_X0 \ > + insn_test_movei_X1 \ > + insn_test_movei_Y0 \ > + insn_test_movei_Y1 \ > + insn_test_moveli_X0 \ > + insn_test_moveli_X1 \ > + insn_test_prefetch_X1 \ > + insn_test_prefetch_Y2 \ > + insn_test_prefetch_l1_X1 \ > + insn_test_prefetch_l1_Y2 \ > + insn_test_prefetch_l2_X1 \ > + insn_test_prefetch_l2_Y2 \ > + insn_test_prefetch_l3_X1 \ > + insn_test_prefetch_l3_Y2 \ > + insn_test_add_X0 \ > + insn_test_add_X1 \ > + insn_test_add_Y0 \ > + insn_test_add_Y1 \ > + insn_test_addi_X0 \ > + insn_test_addi_X1 \ > + insn_test_addi_Y0 \ > + insn_test_addi_Y1 \ > + insn_test_addli_X0 \ > + insn_test_addli_X1 \ > + insn_test_addx_X0 \ > + insn_test_addx_X1 \ > + insn_test_addx_Y0 \ > + insn_test_addx_Y1 \ > + insn_test_addxi_X0 \ > + insn_test_addxi_X1 \ > + insn_test_addxi_Y0 \ > + insn_test_addxi_Y1 \ > + insn_test_addxli_X0 \ > + insn_test_addxli_X1 \ > + insn_test_addxsc_X0 \ > + insn_test_addxsc_X1 \ > + insn_test_and_X0 \ > + insn_test_and_X1 \ > + insn_test_and_Y0 \ > + insn_test_and_Y1 \ > + insn_test_andi_X0 \ > + insn_test_andi_X1 \ > + insn_test_andi_Y0 \ > + insn_test_andi_Y1 \ > + insn_test_beqz_X1 \ > + insn_test_beqzt_X1 \ > + insn_test_bfexts_X0 \ > + insn_test_bfextu_X0 \ > + insn_test_bfins_X0 \ > + insn_test_bgez_X1 \ > + insn_test_bgezt_X1 \ > + insn_test_bgtz_X1 \ > + insn_test_bgtzt_X1 \ > + insn_test_blbc_X1 \ > + insn_test_blbct_X1 \ > + insn_test_blbs_X1 \ > + insn_test_blbst_X1 \ > + insn_test_blez_X1 \ > + insn_test_blezt_X1 \ > + insn_test_bltz_X1 \ > + insn_test_bltzt_X1 \ > + insn_test_bnez_X1 \ > + insn_test_bnezt_X1 \ > + insn_test_clz_X0 \ > + insn_test_clz_Y0 \ > + insn_test_cmoveqz_X0 \ > + insn_test_cmoveqz_Y0 \ > + insn_test_cmovnez_X0 \ > + insn_test_cmovnez_Y0 \ > + insn_test_cmpeq_X0 \ > + insn_test_cmpeq_X1 \ > + insn_test_cmpeq_Y0 \ > + insn_test_cmpeq_Y1 \ > + insn_test_cmpeqi_X0 \ > + insn_test_cmpeqi_X1 \ > + insn_test_cmpeqi_Y0 \ > + insn_test_cmpeqi_Y1 \ > + insn_test_cmples_X0 \ > + insn_test_cmples_X1 \ > + insn_test_cmples_Y0 \ > + insn_test_cmples_Y1 \ > + insn_test_cmpleu_X0 \ > + insn_test_cmpleu_X1 \ > + insn_test_cmpleu_Y0 \ > + insn_test_cmpleu_Y1 \ > + insn_test_cmplts_X0 \ > + insn_test_cmplts_X1 \ > + insn_test_cmplts_Y0 \ > + insn_test_cmplts_Y1 \ > + insn_test_cmpltsi_X0 \ > + insn_test_cmpltsi_X1 \ > + insn_test_cmpltsi_Y0 \ > + insn_test_cmpltsi_Y1 \ > + insn_test_cmpltu_X0 \ > + insn_test_cmpltu_X1 \ > + insn_test_cmpltu_Y0 \ > + insn_test_cmpltu_Y1 \ > + insn_test_cmpltui_X0 \ > + insn_test_cmpltui_X1 \ > + insn_test_cmpne_X0 \ > + insn_test_cmpne_X1 \ > + insn_test_cmpne_Y0 \ > + insn_test_cmpne_Y1 \ > + insn_test_cmul_X0 \ > + insn_test_cmula_X0 \ > + insn_test_cmulaf_X0 \ > + insn_test_cmulf_X0 \ > + insn_test_cmulfr_X0 \ > + insn_test_cmulh_X0 \ > + insn_test_cmulhr_X0 \ > + insn_test_crc32_32_X0 \ > + insn_test_crc32_8_X0 \ > + insn_test_ctz_X0 \ > + insn_test_ctz_Y0 \ > + insn_test_dblalign_X0 \ > + insn_test_dblalign2_X0 \ > + insn_test_dblalign2_X1 \ > + insn_test_dblalign4_X0 \ > + insn_test_dblalign4_X1 \ > + insn_test_dblalign6_X0 \ > + insn_test_dblalign6_X1 \ > + insn_test_dtlbpr_X1 \ > + insn_test_fdouble_add_flags_X0 \ > + insn_test_fdouble_addsub_X0 \ > + insn_test_fdouble_mul_flags_X0 \ > + insn_test_fdouble_pack1_X0 \ > + insn_test_fdouble_pack2_X0 \ > + insn_test_fdouble_sub_flags_X0 \ > + insn_test_fdouble_unpack_max_X0 \ > + insn_test_fdouble_unpack_min_X0 \ > + insn_test_flushwb_X1 \ > + insn_test_fnop_X0 \ > + insn_test_fnop_X1 \ > + insn_test_fnop_Y0 \ > + insn_test_fnop_Y1 \ > + insn_test_fsingle_add1_X0 \ > + insn_test_fsingle_addsub2_X0 \ > + insn_test_fsingle_mul1_X0 \ > + insn_test_fsingle_mul2_X0 \ > + insn_test_fsingle_pack1_X0 \ > + insn_test_fsingle_pack1_Y0 \ > + insn_test_fsingle_pack2_X0 \ > + insn_test_fsingle_sub1_X0 \ > + insn_test_icoh_X1 \ > + insn_test_j_X1 \ > + insn_test_jal_X1 \ > + insn_test_jalr_X1 \ > + insn_test_jalr_Y1 \ > + insn_test_jalrp_X1 \ > + insn_test_jalrp_Y1 \ > + insn_test_jr_X1 \ > + insn_test_jr_Y1 \ > + insn_test_jrp_X1 \ > + insn_test_jrp_Y1 \ > + insn_test_ld_X1 \ > + insn_test_ld_Y2 \ > + insn_test_ld1s_X1 \ > + insn_test_ld1s_Y2 \ > + insn_test_ld1s_add_X1 \ > + insn_test_ld1u_X1 \ > + insn_test_ld1u_Y2 \ > + insn_test_ld1u_add_X1 \ > + insn_test_ld2s_X1 \ > + insn_test_ld2s_Y2 \ > + insn_test_ld2u_X1 \ > + insn_test_ld2u_Y2 \ > + insn_test_ld4s_X1 \ > + insn_test_ld4s_add_X1 \ > + insn_test_ld4u_X1 \ > + insn_test_ld4u_Y2 \ > + insn_test_ld4u_add_X1 \ > + insn_test_ld_add_X1 \ > + insn_test_ldna_X1 \ > + insn_test_ldna_add_X1 \ > + insn_test_ldnt_X1 \ > + insn_test_ldnt1s_X1 \ > + insn_test_ldnt1s_add_X1 \ > + insn_test_ldnt1u_X1 \ > + insn_test_ldnt1u_add_X1 \ > + insn_test_ldnt2s_X1 \ > + insn_test_ldnt2s_add_X1 \ > + insn_test_ldnt2u_add_X1 \ > + insn_test_ldnt4s_X1 \ > + insn_test_ldnt4s_add_X1 \ > + insn_test_ldnt4u_X1 \ > + insn_test_ldnt4u_add_X1 \ > + insn_test_ldnt_add_X1 \ > + insn_test_lnk_X1 \ > + insn_test_lnk_Y1 \ > + insn_test_mf_X1 \ > + insn_test_mm_X0 \ > + insn_test_mnz_X0 \ > + insn_test_mnz_X1 \ > + insn_test_mnz_Y0 \ > + insn_test_mnz_Y1 \ > + insn_test_mul_hs_hs_X0 \ > + insn_test_mul_hs_hs_Y0 \ > + insn_test_mul_hs_hu_X0 \ > + insn_test_mul_hs_ls_X0 \ > + insn_test_mul_hs_lu_X0 \ > + insn_test_mul_hu_hu_X0 \ > + insn_test_mul_hu_hu_Y0 \ > + insn_test_mul_hu_lu_X0 \ > + insn_test_mul_ls_ls_X0 \ > + insn_test_mul_ls_ls_Y0 \ > + insn_test_mul_ls_lu_X0 \ > + insn_test_mul_lu_lu_X0 \ > + insn_test_mul_lu_lu_Y0 \ > + insn_test_mula_hs_hs_X0 \ > + insn_test_mula_hs_hs_Y0 \ > + insn_test_mula_hs_hu_X0 \ > + insn_test_mula_hs_ls_X0 \ > + insn_test_mula_hs_lu_X0 \ > + insn_test_mula_hu_hu_X0 \ > + insn_test_mula_hu_hu_Y0 \ > + insn_test_mula_hu_ls_X0 \ > + insn_test_mula_hu_lu_X0 \ > + insn_test_mula_ls_ls_X0 \ > + insn_test_mula_ls_ls_Y0 \ > + insn_test_mula_ls_lu_X0 ... [truncated message content] |
|
From: <sv...@va...> - 2015-08-03 06:17:20
|
Author: rhyskidd
Date: Mon Aug 3 07:17:13 2015
New Revision: 15476
Log:
Resolve suppressions that changed in OS X 10.11 (DP5). n-i-bz
Modified:
trunk/darwin15.supp
Modified: trunk/darwin15.supp
==============================================================================
--- trunk/darwin15.supp (original)
+++ trunk/darwin15.supp Mon Aug 3 07:17:13 2015
@@ -35,15 +35,14 @@
...
}
-#{
-# OSX1011:4-Leak
-# Memcheck:Leak
-# match-leak-kinds: reachable
-# fun:malloc_zone_?alloc
-# ...
-# fun:dyld_register_image_state_change_handler
-# ...
-#}
+{
+ OSX1011:4-Leak
+ Memcheck:Leak
+ fun:malloc_zone_?alloc
+ ...
+ fun:dyld_register_image_state_change_handler
+ ...
+}
{
OSX1011:5-Leak
@@ -62,7 +61,7 @@
fun:malloc_zone_?alloc
...
fun:map_images_nolock
- fun:map_hax_images
+ fun:map_2_images
...
}
@@ -73,7 +72,7 @@
fun:malloc_zone_?alloc
...
fun:map_images_nolock
- fun:map_hax_images
+ fun:map_2_images
...
}
@@ -500,13 +499,15 @@
obj:/usr/lib/libz.*dylib
}
-#{
-# OSX1011:32bit:_libxpc_initializer
-# Memcheck:Cond
-# fun:_libxpc_initializer
-# fun:libSystem_initializer
-# fun:*ImageLoaderMachO*doModInitFunctions*
-#}
+{
+ OSX1011:32bit:_libxpc_initializer
+ Memcheck:Cond
+ obj:/usr/lib/system/libsystem_c.dylib
+ obj:/usr/lib/system/libsystem_c.dylib
+ fun:_libxpc_initializer
+ obj:/usr/lib/libSystem.B.dylib
+ fun:*ImageLoaderMachO*doModInitFunctions*
+}
{
OSX1011:dyld-1
|
|
From: <sv...@va...> - 2015-08-03 02:14:26
|
Author: rhyskidd
Date: Mon Aug 3 03:14:17 2015
New Revision: 15475
Log:
OS X: Suppress newly introduced system library errors in OS X 10.11 (DP5). n-i-bz
Modified:
trunk/darwin15.supp
Modified: trunk/darwin15.supp
==============================================================================
--- trunk/darwin15.supp (original)
+++ trunk/darwin15.supp Mon Aug 3 03:14:17 2015
@@ -13,14 +13,14 @@
fun:_read_images
}
-#{
-# OSX1011:2-Leak
-# Memcheck:Leak
-# match-leak-kinds: definite
-# fun:?alloc
-# ...
-# fun:_ZN4dyld24initializeMainExecutableEv
-#}
+{
+ OSX1011:2-Leak
+ Memcheck:Leak
+ match-leak-kinds: definite
+ fun:malloc_zone_?alloc
+ ...
+ fun:_read_images
+}
{
OSX1011:3-Leak
@@ -202,6 +202,16 @@
...
}
+{
+ OSX1011:21-Leak
+ Memcheck:Leak
+ match-leak-kinds: definite
+ fun:malloc_zone_memalign
+ ...
+ fun:_ZN4dyld24initializeMainExecutableEv
+ ...
+}
+
############################################
## Non-leak errors
|
|
From: <sv...@va...> - 2015-08-03 00:44:08
|
Author: rhyskidd
Date: Mon Aug 3 01:44:01 2015
New Revision: 15474
Log:
Guard two hanging tests on OS X 10.11, which otherwise prevent regression test suite from running in automated manner. n-i-bz
Modified:
trunk/none/tests/res_search.vgtest
trunk/none/tests/resolv.vgtest
Modified: trunk/none/tests/res_search.vgtest
==============================================================================
--- trunk/none/tests/res_search.vgtest (original)
+++ trunk/none/tests/res_search.vgtest Mon Aug 3 01:44:01 2015
@@ -1,4 +1,4 @@
-prereq: which host >/dev/null 2>/dev/null && host www.yahoo.com > /dev/null
+prereq: which host >/dev/null 2>/dev/null && host www.yahoo.com > /dev/null && ! ../../tests/os_test darwin
prog: res_search
args: www.yahoo.com
vgopts: -q
Modified: trunk/none/tests/resolv.vgtest
==============================================================================
--- trunk/none/tests/resolv.vgtest (original)
+++ trunk/none/tests/resolv.vgtest Mon Aug 3 01:44:01 2015
@@ -1,4 +1,4 @@
# Disabled on Solaris because different approach needs to be taken.
# There is none/tests/solaris/resolv for that purpose.
-prereq: (! ../../tests/os_test solaris)
+prereq: ! ../../tests/os_test solaris && ! ../../tests/os_test darwin
prog: resolv
|