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From: Matthias S. <zz...@ge...> - 2015-08-12 19:15:00
|
Add test that calls abort with xml output.
It solved bug 191069
---
coregrind/m_signals.c | 53 +++++++++++++++++++--------
docs/internals/xml-output-protocol4.txt | 47 ++++++++++++++++++++++++
memcheck/tests/Makefile.am | 3 +-
memcheck/tests/gone_abrt_xml.stderr.exp | 63 +++++++++++++++++++++++++++++++++
memcheck/tests/gone_abrt_xml.vgtest | 5 +++
5 files changed, 155 insertions(+), 16 deletions(-)
create mode 100644 memcheck/tests/gone_abrt_xml.stderr.exp
create mode 100644 memcheck/tests/gone_abrt_xml.vgtest
diff --git a/coregrind/m_signals.c b/coregrind/m_signals.c
index f59bff7..b166845 100644
--- a/coregrind/m_signals.c
+++ b/coregrind/m_signals.c
@@ -1740,14 +1740,25 @@ static void default_action(const vki_siginfo_t *info, ThreadId tid)
core = False;
}
- if ( (VG_(clo_verbosity) >= 1 ||
- (could_core && is_signal_from_kernel(tid, sigNo, info->si_code))
- ) &&
- !VG_(clo_xml) ) {
- VG_(umsg)(
- "\n"
- "Process terminating with default action of signal %d (%s)%s\n",
- sigNo, VG_(signame)(sigNo), core ? ": dumping core" : "");
+ if ( VG_(clo_verbosity) >= 1 ||
+ (could_core && is_signal_from_kernel(tid, sigNo, info->si_code)) ||
+ VG_(clo_xml) ) {
+ if (VG_(clo_xml)) {
+ VG_(printf_xml)("<fatal_signal>\n");
+ VG_(printf_xml)(" <tid>%d</tid>\n", tid);
+ ThreadState* tst = VG_(get_ThreadState)(tid);
+ if (tst->thread_name) {
+ VG_(printf_xml)(" <threadname>%s</threadname>\n", tst->thread_name);
+ }
+ VG_(printf_xml)(" <signo>%d</signo>\n", sigNo);
+ VG_(printf_xml)(" <signame>%s</signame>\n", VG_(signame)(sigNo));
+ VG_(printf_xml)(" <sicode>%d</sicode>\n", info->si_code);
+ } else {
+ VG_(umsg)(
+ "\n"
+ "Process terminating with default action of signal %d (%s)%s\n",
+ sigNo, VG_(signame)(sigNo), core ? ": dumping core" : "");
+ }
/* Be helpful - decode some more details about this fault */
if (is_signal_from_kernel(tid, sigNo, info->si_code)) {
@@ -1820,13 +1831,20 @@ static void default_action(const vki_siginfo_t *info, ThreadId tid)
break;
} /* switch (sigNo) */
- if (event != NULL) {
- if (haveaddr)
- VG_(umsg)(" %s at address %p\n",
- event, info->VKI_SIGINFO_si_addr);
- else
- VG_(umsg)(" %s\n", event);
- }
+ if (VG_(clo_xml)) {
+ if (event != NULL)
+ VG_(printf_xml)(" <event>%s</event>\n", event);
+ if (haveaddr)
+ VG_(printf_xml)(" <siaddr>%p</siaddr>\n", info->VKI_SIGINFO_si_addr);
+ } else {
+ if (event != NULL) {
+ if (haveaddr)
+ VG_(umsg)(" %s at address %p\n",
+ event, info->VKI_SIGINFO_si_addr);
+ else
+ VG_(umsg)(" %s\n", event);
+ }
+ }
}
/* Print a stack trace. Be cautious if the thread's SP is in an
obviously stupid place (not mapped readable) that would
@@ -1889,6 +1907,11 @@ static void default_action(const vki_siginfo_t *info, ThreadId tid)
VG_(threads)[1].client_stack_szB);
}
}
+ if (VG_(clo_xml)) {
+ /* postamble */
+ VG_(printf_xml)("</fatal_signal>\n");
+ VG_(printf_xml)("\n");
+ }
}
if (VG_(clo_vgdb) != Vg_VgdbNo
diff --git a/docs/internals/xml-output-protocol4.txt b/docs/internals/xml-output-protocol4.txt
index ccb22b4..e20b9dd 100644
--- a/docs/internals/xml-output-protocol4.txt
+++ b/docs/internals/xml-output-protocol4.txt
@@ -743,3 +743,50 @@ OR
* STACK is only present in case of VALGRIND_PRINTF_BACKTRACE. See above
for a definition of STACK.
+
+====================================================================
+
+FATAL_SIGNAL
+
+FATAL_SIGNAL defines a message that was caused by a signal that killed them
+process.
+
+Definition:
+
+ <fatal_signal>
+ <tid>INT</tid>
+ <threadname>NAME</threadname> if set
+
+ <signo>INT</signo>
+ <signame>NAME</signame>
+
+ <sicode>0</sicode>
+ <event>NAME</event>
+ <siaddr>ADDR</siaddr>
+
+ STACK
+
+ </fatal_signal>
+
+* The <tid> tag indicates the Valgrind thread number. This value
+ is arbitrary but may be used to determine which threads produced
+ which errors (at least, the first instance of each error).
+
+* The <threadname> tag identifies the name of the thread if it was
+ set by the client application. If no name was set, the tag is
+ omitted.
+
+* The <signo> tag indicates signo value from struct siginfo.
+
+* In <signame> tag there is the decoded name of signo.
+
+* The <sicode> tag contains the sicode from struct siginfo.
+
+* The <event> tag indicates the decoded name of the sicode.
+
+* The <siaddr> tag indicates the address that is the reason
+ why the signal was triggered. This can be an unaligned pointer value or
+ just the address of not mapped memory that is accessed Nevertheless.
+
+* STACK is defined above and shows where the thread was when it catched the signal.
+ When sending the signal to itself using raise, then raise is visible in this stack.
diff --git a/memcheck/tests/Makefile.am b/memcheck/tests/Makefile.am
index 0a850a2..f084198 100644
--- a/memcheck/tests/Makefile.am
+++ b/memcheck/tests/Makefile.am
@@ -293,7 +293,8 @@ EXTRA_DIST = \
writev1.stderr.exp writev1.stderr.exp-solaris writev1.vgtest \
xml1.stderr.exp xml1.stdout.exp xml1.vgtest xml1.stderr.exp-s390x-mvc \
threadname.vgtest threadname.stderr.exp \
- threadname_xml.vgtest threadname_xml.stderr.exp
+ threadname_xml.vgtest threadname_xml.stderr.exp \
+ gone_abrt_xml.vgtest gone_abrt_xml.stderr.exp
check_PROGRAMS = \
accounting \
diff --git a/memcheck/tests/gone_abrt_xml.stderr.exp b/memcheck/tests/gone_abrt_xml.stderr.exp
new file mode 100644
index 0000000..b0faf73
--- /dev/null
+++ b/memcheck/tests/gone_abrt_xml.stderr.exp
@@ -0,0 +1,63 @@
+<?xml version="1.0"?>
+
+<valgrindoutput>
+
+<protocolversion>4</protocolversion>
+<protocoltool>memcheck</protocoltool>
+
+<preamble>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+ <line>...</line>
+</preamble>
+
+<pid>...</pid>
+<ppid>...</ppid>
+<tool>memcheck</tool>
+
+<args>
+ <vargv>...</vargv>
+ <argv>
+ <exe>./../../gdbserver_tests/gone</exe>
+ <arg>abort</arg>
+ </argv>
+</args>
+
+<status>
+ <state>RUNNING</state>
+ <time>...</time>
+</status>
+
+starting ...
+aborting ...
+<fatal_signal>
+ <tid>...</tid>
+ <signo>6</signo>
+ <signame>SIGABRT</signame>
+ <sicode>0</sicode>
+ <stack>
+ <frame>
+ <ip>0x........</ip>
+ <obj>...</obj>
+ <fn>main</fn>
+ <dir>...</dir>
+ <file>gone.c</file>
+ <line>...</line>
+ </frame>
+ </stack>
+</fatal_signal>
+
+
+<status>
+ <state>FINISHED</state>
+ <time>...</time>
+</status>
+
+<errorcounts>
+</errorcounts>
+
+<suppcounts>...</suppcounts>
+
+</valgrindoutput>
+
diff --git a/memcheck/tests/gone_abrt_xml.vgtest b/memcheck/tests/gone_abrt_xml.vgtest
new file mode 100644
index 0000000..dc18192
--- /dev/null
+++ b/memcheck/tests/gone_abrt_xml.vgtest
@@ -0,0 +1,5 @@
+prog: ../../gdbserver_tests/gone
+args: abort
+vgopts: --xml=yes --xml-fd=2 --log-file=/dev/null
+stderr_filter: filter_xml
+cleanup: rm -f vgcore.*
--
2.5.0
|
|
From: <sv...@va...> - 2015-08-12 16:03:25
|
Author: iraisr
Date: Wed Aug 12 17:03:16 2015
New Revision: 15530
Log:
Fix the regression from r15518 which broke builds
on older Solaris releases.
Modified:
trunk/coregrind/m_syswrap/syswrap-solaris.c
Modified: trunk/coregrind/m_syswrap/syswrap-solaris.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-solaris.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-solaris.c Wed Aug 12 17:03:16 2015
@@ -7820,6 +7820,7 @@
"entity_name->rpr_answertype)", r->rpr_answertype);
}
break;
+ #if (SOLARIS_REPCACHE_PROTOCOL_VERSION >= 25)
case VKI_REP_PROTOCOL_ENTITY_GET_ROOT:
{
struct vki_rep_protocol_entity_root *r =
@@ -7830,6 +7831,7 @@
"entity_root->rpr_outid)", r->rpr_outid);
}
break;
+ #endif /* SOLARIS_REPCACHE_PROTOCOL_VERSION >= 25 */
case VKI_REP_PROTOCOL_ENTITY_GET:
{
struct vki_rep_protocol_entity_get *r =
|
|
From: Matthias S. <zz...@ge...> - 2015-08-12 15:19:55
|
Am 12.08.2015 um 10:56 schrieb Tom Hughes: > On 12/08/15 07:09, Tom Hughes wrote: >> On 12/08/15 03:25, Bart Van Assche wrote: >> >>> Ah, right, your purpose is that the Valgrind macros do not emit any >>> client requests on x32. Unless this is very clearly documented that >>> might be a confusing outcome for x32 users ... Maybe these users expect >>> that if they build a program for x32 and analyze it with Valgrind that >>> these macros just work ? >> >> Well how would they analyse such a program with valgrind? The launcher >> would reject an x32 binary on the grounds that it isn't supported... > > On closer inspection it looks like the laucher won't actually refuse but > I don't think it will work either. > > Basically select_platform will fail, because EI_CLASS will be ELFCLASS32 > but e_machine will be EM_X86_64 which is not a combination we recognise. > So we will fallback to using amd64-linux as the default platform. > > But that will of course use a 64 bit address space, so it's unlikely > that an x32 binary will get very far. > > In fact I think once the tool tries to load the ELF readelf() in > m_ume/elf.c will just abort because the class will be wrong. > Hi! you seem to be right: It cannot detect the platform, chooses amd64-linux and that complains about wrong ELF class. This is the output when calling valgrind on an x32 binary: # valgrind -d ./bin/bash --3928:1:debuglog DebugLog system started by Stage 1, level 1 logging requested --3928:1:launcher no tool requested, defaulting to 'memcheck' --3928:1:launcher no platform detected, defaulting platform to 'amd64-linux' --3928:1:launcher launching /usr/local/lib/valgrind/memcheck-amd64-linux --3928:1:debuglog DebugLog system started by Stage 2 (main), level 1 logging requested --3928:1: main Welcome to Valgrind version 3.11.0.SVN debug logging --3928:1: main Checking current stack is plausible --3928:1: main Checking initial stack was noted --3928:1: main Starting the address space managerselect_platform --3928:1: main Address space manager is running --3928:1: main Starting the dynamic memory manager --3928:1:mallocfr newSuperblock at 0x802001000 (pszB 4194272) owner VALGRIND/core --3928:1:mallocfr deferred_reclaimSuperblock at 0x802001000 (pszB 4194272) (prev 0x0) owner VALGRIND/core --3928:1: main Dynamic memory manager is running --3928:1: main Initialise m_debuginfo --3928:1: main VG_(libdir) = /usr/local/lib/valgrind --3928:1: main Getting launcher's name ... --3928:1: main ... /usr/local/bin/valgrind --3928:1: main Get hardware capabilities ... --3928:1: cache warning: Unknown Intel cache config value (0x63), ignoring --3928:1: cache Autodetected cache info is sensible --3928:1: cache Cache info: [...deleted cache info...] --3928:1: main ... arch = AMD64, hwcaps = amd64-cx16-lzcnt-rdtscp-sse3-avx-avx2-bmi --3928:1: main Getting the working directory at startup --3928:1: main ... /data/x32 --3928:1: main Split up command line --3928:1: main (early_) Process Valgrind's command line options --3928:1: main Create initial image --3928:1: initimg Loading client valgrind: wrong ELF executable class (eg. 32-bit instead of 64-bit) valgrind: ./bin/bash: cannot execute binary file Regards Matthias |
|
From: <sv...@va...> - 2015-08-12 14:47:33
|
Author: sewardj
Date: Wed Aug 12 15:47:26 2015
New Revision: 15529
Log:
Update.
Modified:
trunk/NEWS
trunk/docs/internals/3_10_BUGSTATUS.txt
Modified: trunk/NEWS
==============================================================================
--- trunk/NEWS (original)
+++ trunk/NEWS Wed Aug 12 15:47:26 2015
@@ -340,6 +340,12 @@
340856 disInstr(arm64): unhandled instruction 0x1E634C45 (fcsel)
340922 arm64: unhandled getgroups/setgroups syscalls
350251 Fix typo in VEX utility program (test_main.c).
+350407 arm64: unhandled instruction ucvtf (vector, integer)
+350809 none/tests/async-sigs breaks when run under cron on Solaris
+350811 update README.solaris after r15445
+350813 Use handwritten memcheck assembly helpers on x86/Solaris [..]
+350854 strange code in VG_(load_ELF)()
+351140 arm64 syscalls setuid (146) and setresgid (149) not implemented
n-i-bz DRD and Helgrind: Handle Imbe_CancelReservation (clrex on ARM)
n-i-bz Add missing ]] to terminate CDATA.
n-i-bz Glibc versions prior to 2.5 do not define PTRACE_GETSIGINFO
Modified: trunk/docs/internals/3_10_BUGSTATUS.txt
==============================================================================
--- trunk/docs/internals/3_10_BUGSTATUS.txt (original)
+++ trunk/docs/internals/3_10_BUGSTATUS.txt Wed Aug 12 15:47:26 2015
@@ -40,6 +40,8 @@
349304 vex amd64->IR: 0xF 0x33 0x89 0x45 0xFC 0x89 0x55 0xF8
rdpmc?
+350593 AMD64 VEX does not support all SIMD compare variants.
+
=== VEX/arm ============================================================
335618 mov.w rN, pc/sp (ARM32)
@@ -98,6 +100,8 @@
349891 vex x86->IR: unhandled instruction bytes: 0xF3 0xF 0xB8 0xC9
+350062 3.11 SVN cannot start application (x86 ROUNDSD ?)
+
=== VEX/mips ===========================================================
340777 Illegal instruction on mips (ar71xx)
@@ -120,6 +124,8 @@
=== VEX/s390x ==========================================================
+350290 s390x unsupported instruction fixbra
+
=== VEX general ========================================================
339778 Linux/TileGx platform support to Valgrind
@@ -166,6 +172,10 @@
349952 Valgrind terminates process upon a call to remap_file_pages
+350228 Unhandled ioctl 0x6458 (i965/mesa)
+
+351029 factor our m_sigframe functions
+
=== Debuginfo reader ===================================================
327427 ifunc crash when symbols are discarded
@@ -218,6 +228,13 @@
349879 [PATCH] memcheck: add handwritten assembly for helperc_LOADV*
+350405 Support for Intel DPDK custom allocator rte_malloc
+ Seems dubious
+
+350928 mc_malloc_wrappers.c:244 (in_block_list):
+ Assertion 'found_mc == mc' failed
+ Has patch, needs looking at
+
=== Tools/DRD ==========================================================
=== Tools/Helgrind =====================================================
@@ -240,6 +257,8 @@
342353 Allow dumping full massif output while valgrind is still running
Has patch
+350934 massif VALGRIND INTERNAL ERROR: Valgrind received a signal 7 (SIGBUS)
+
=== Tools/Cachegrind ===================================================
=== Tools/Lackey =======================================================
@@ -269,6 +288,9 @@
347686 Patch set to cleanup PPC64 regtests
+350496 unhandled instruction: 0xE8040000 for powerpc e6500
+ e500 ?
+
=== other/arm ==========================================================
348252 ARM: test vcvt_fixed_float_VFP causes compiler errors
@@ -345,6 +367,8 @@
349804 wine/osx: mmap-FIXED(0x1000, 1073741824) failed in UME (load_segment2)
+350359 memcheck/tests/x86/fxsave hangs indefinetely on OS X
+
=== other/Win32 =======================================================
211529 valgrind doesn't show proper call stacks for programs compiled
@@ -361,6 +385,8 @@
348358 describe should show info about main stack guard page
+350202 Add limited param to 'monitor block_list'
+
=== Output =============================================================
339405 Adds ability to invoke a script in order to determine a
@@ -370,6 +396,8 @@
342423 Log files should have the history 'execve' calls in them
Wishlist
+351043 Invalid XML output when tracing into forked child processes
+
=== MPI ================================================================
330147 libmpiwrap PMPI_Get_count (should take; simple fix)
@@ -397,6 +425,12 @@
349790 Clean up of the hardware capability checking utilities.
+350321 3 (gdbserver) stdoutB failures, 8 stderr failures during `make regtest`
+ Very likely INVALID
+
+350491 Handling of nested scripts
+ Bizarre
+
=== Uncategorised/build=================================================
339215 Valgrind 3.10.0 contain 2013 in copyrights notice
@@ -439,4 +473,4 @@
Check: missing copyright notices in include/vki/*xen*.h
Check: update copyright dates in source files
-Tue 7 Jul 15:27:23 CEST 2015
+Wed 12 Aug 15:52:27 CEST 2015
|
|
From: Rhys K. <rhy...@gm...> - 2015-08-12 14:23:25
|
As of r15528, no new regressions on OS X and the test suite runs through successfully on my hardware. Regards, Rhys On 12 August 2015 at 21:26, Julian Seward <js...@ac...> wrote: > > In revs 3169, 15522, 15523, I finally implemented the XSAVE and > XRSTOR instructions which are associated with the AVX instruction > set. These provide saving and restoring for the new state introduced > by AVX -- that is, the YMM high half registers. They also generalise > the existing FXSAVE/FXRSTOR instructions (for SSE+X87) and FSAVE/FRSTOR > instructions (X87 only). > > As part of this I added a new CPUID implementation that reflects AVX2 > capable processors. > > As a result of this it should be possible to run code that requires > XSAVE/XRSTOR, in particular AVX and AVX2 code generated by the Intel > compiler. > > These instructions are a nightmare of complexity. I think I didn't > break anything, but there is a risk of fallout, particularly for the > OSX and Solaris ports. So it would be good to watch out for that. > > J > |
|
From: <sv...@va...> - 2015-08-12 14:19:17
|
Author: rhyskidd
Date: Wed Aug 12 15:19:09 2015
New Revision: 15528
Log:
Properly guard memcheck/tests/amd64/xsave-avx. This test relies on memalign(), which is not present on OS X. Along with a few other avx tests needs refactoring to use posix_memalign() down the track. n-i-bz.
Modified:
trunk/memcheck/tests/amd64/Makefile.am
trunk/memcheck/tests/amd64/xsave-avx.vgtest
Modified: trunk/memcheck/tests/amd64/Makefile.am
==============================================================================
--- trunk/memcheck/tests/amd64/Makefile.am (original)
+++ trunk/memcheck/tests/amd64/Makefile.am Wed Aug 12 15:19:09 2015
@@ -46,7 +46,10 @@
sse_memory \
xor-undef-amd64
if BUILD_AVX_TESTS
- check_PROGRAMS += sh-mem-vec256 xsave-avx
+ check_PROGRAMS += sh-mem-vec256
+if !VGCONF_OS_IS_DARWIN
+ check_PROGRAMS += xsave-avx
+endif
endif
if HAVE_ASM_CONSTRAINT_P
check_PROGRAMS += insn-pcmpistri
Modified: trunk/memcheck/tests/amd64/xsave-avx.vgtest
==============================================================================
--- trunk/memcheck/tests/amd64/xsave-avx.vgtest (original)
+++ trunk/memcheck/tests/amd64/xsave-avx.vgtest Wed Aug 12 15:19:09 2015
@@ -1,4 +1,4 @@
prog: xsave-avx
-prereq: ../../../tests/x86_amd64_features amd64-avx
+prereq: test -x xsave-avx && ../../../tests/x86_amd64_features amd64-avx
vgopts: -q
args: x
|
|
From: Bart V. A. <bva...@ac...> - 2015-08-12 14:08:43
|
On 08/10/15 11:52, Matthias Schwarzott wrote: > Hi! > > I have seen that valgrind.h will missdetect x32 as amd64. > > So I wonder if this can cause any bad effects. > > If so, the header needs to be protected so it does not emit client > requests on x32. > It could be done like this, because the x32 ABI says that __ILP32__ must > be defined (and it is not defined on amd64). > See abi.pdf in https://sites.google.com/site/x32abi/documents > > Regards > Matthias > > > --- a/include/valgrind.h > +++ b/include/valgrind.h > @@ -140,7 +140,7 @@ > # define PLAT_amd64_win64 1 > #elif defined(__linux__) && defined(__i386__) > # define PLAT_x86_linux 1 > -#elif defined(__linux__) && defined(__x86_64__) > +#elif defined(__linux__) && defined(__x86_64__) && !defined(__ILP32__) > # define PLAT_amd64_linux 1 > #elif defined(__linux__) && defined(__powerpc__) && !defined(__powerpc64__) > # define PLAT_ppc32_linux 1 Applied as r15526 on the trunk. Thanks for the patch. Bart. |
|
From: <sv...@va...> - 2015-08-12 13:42:49
|
Author: rhyskidd
Date: Wed Aug 12 14:42:42 2015
New Revision: 15527
Log:
Fix svn propset for memcheck/tests/amd64/xsave-avx since r15524. n-i-bz.
Modified:
trunk/memcheck/tests/amd64/ (props changed)
|
|
From: <sv...@va...> - 2015-08-12 13:29:17
|
Author: bart
Date: Wed Aug 12 14:29:10 2015
New Revision: 15526
Log:
valgrind.h: Suppress client request code generation on x32
Ensure that no code is generated for client requests on x32.
From: Matthias Schwarzott <zz...@ge...>
Modified:
trunk/include/valgrind.h
Modified: trunk/include/valgrind.h
==============================================================================
--- trunk/include/valgrind.h (original)
+++ trunk/include/valgrind.h Wed Aug 12 14:29:10 2015
@@ -140,7 +140,7 @@
# define PLAT_amd64_win64 1
#elif defined(__linux__) && defined(__i386__)
# define PLAT_x86_linux 1
-#elif defined(__linux__) && defined(__x86_64__)
+#elif defined(__linux__) && defined(__x86_64__) && !defined(__ILP32__)
# define PLAT_amd64_linux 1
#elif defined(__linux__) && defined(__powerpc__) && !defined(__powerpc64__)
# define PLAT_ppc32_linux 1
|
|
From: <sv...@va...> - 2015-08-12 13:24:44
|
Author: florian
Date: Wed Aug 12 14:24:33 2015
New Revision: 15525
Log:
Fix clobber.
Modified:
trunk/memcheck/tests/amd64/xsave-avx.c
Modified: trunk/memcheck/tests/amd64/xsave-avx.c
==============================================================================
--- trunk/memcheck/tests/amd64/xsave-avx.c (original)
+++ trunk/memcheck/tests/amd64/xsave-avx.c Wed Aug 12 14:24:33 2015
@@ -96,8 +96,8 @@
__asm__ __volatile__("fld %st(3)");
__asm__ __volatile__("fld %st(3)");
__asm__ __volatile__("fld1");
- __asm__ __volatile__("vmovups (%0), %%ymm0" : : "r"(&vec0[0]) : "ymm0" );
- __asm__ __volatile__("vmovups (%0), %%ymm1" : : "r"(&vec1[0]) : "ymm1" );
+ __asm__ __volatile__("vmovups (%0), %%ymm0" : : "r"(&vec0[0]) : "xmm0" );
+ __asm__ __volatile__("vmovups (%0), %%ymm1" : : "r"(&vec1[0]) : "xmm1" );
__asm__ __volatile__("vxorps %ymm2, %ymm2, %ymm2");
__asm__ __volatile__("vmovaps %ymm0, %ymm3");
__asm__ __volatile__("vmovaps %ymm1, %ymm4");
|
|
From: Rich C. <rc...@wi...> - 2015-08-12 11:52:43
|
On Wed, 12 Aug 2015 07:10:57 +0100 Tom Hughes <to...@co...> wrote: > On 12/08/15 04:01, Rich Coe wrote: > > > This looks like it is opensuse specific, but gcc-5 -dumpversion returns > > a single digit (5) for gcc 5.1.1. > > > > $ gcc-5 --version > > gcc-5 (SUSE Linux) 5.1.1 20150713 [gcc-5-branch revision 225736] > > > > $ gcc-5 -dumpversion > > 5 > > Shouldn't you be betting opensuse to fix this? It doesn't do that on Fedora: > > bericote [~] % gcc -dumpversion > 5.1.1 > > Sounds like it is just a bug in the opensuse build... Sounds good to me. I wasn't sure it was distribution change or a gcc change. I wrote BZ#941428 https://bugzilla.novell.com/show_bug.cgi?id=941428 to track it. Rich -- Rich Coe rc...@wi... |
|
From: Florian K. <fl...@ei...> - 2015-08-12 11:52:33
|
On 12.08.2015 13:26, Julian Seward wrote:
>
> In revs 3169, 15522, 15523, I finally implemented the XSAVE and
> XRSTOR instructions which are associated with the AVX instruction
> set. These provide saving and restoring for the new state introduced
> by AVX -- that is, the YMM high half registers. They also generalise
> the existing FXSAVE/FXRSTOR instructions (for SSE+X87) and FSAVE/FRSTOR
> instructions (X87 only).
>
> As part of this I added a new CPUID implementation that reflects AVX2
> capable processors.
>
> As a result of this it should be possible to run code that requires
> XSAVE/XRSTOR, in particular AVX and AVX2 code generated by the Intel
> compiler.
>
> These instructions are a nightmare of complexity. I think I didn't
> break anything, but there is a risk of fallout, particularly for the
> OSX and Solaris ports. So it would be good to watch out for that.
I see this:
Making check in memcheck
Making check in .
Making check in tests
Making check in .
Making check in x86
Making check in amd64
xsave-avx.c: In function 'do_setup_then_xsave':
xsave-avx.c:99:4: error: unknown register name 'ymm0' in 'asm'
__asm__ __volatile__("vmovups (%0), %%ymm0" : : "r"(&vec0[0]) :
"ymm0" );
^
xsave-avx.c:100:4: error: unknown register name 'ymm1' in 'asm'
__asm__ __volatile__("vmovups (%0), %%ymm1" : : "r"(&vec1[0]) :
"ymm1" );
^
cpuinfo:
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 42
model name : Intel(R) Core(TM) i7-2670QM CPU @ 2.20GHz
stepping : 7
microcode : 0x18
cpu MHz : 800.000
cache size : 6144 KB
physical id : 0
siblings : 8
core id : 0
cpu cores : 4
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 13
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx
rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology
nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx
est tm2 ssse3 cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic popcnt
tsc_deadline_timer xsave avx lahf_lm ida arat epb xsaveopt pln pts
dtherm tpr_shadow vnmi flexpriority ept vpid
bogomips : 4390.03
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
Florian
|
|
From: <sv...@va...> - 2015-08-12 11:35:42
|
Author: sewardj
Date: Wed Aug 12 12:35:27 2015
New Revision: 15524
Log:
Add test cases for AVX XSAVE and XRSTOR instructions.
Added:
trunk/memcheck/tests/amd64/xsave-avx.c
trunk/memcheck/tests/amd64/xsave-avx.stderr.exp
trunk/memcheck/tests/amd64/xsave-avx.stdout.exp
trunk/memcheck/tests/amd64/xsave-avx.vgtest
Modified:
trunk/memcheck/tests/amd64/Makefile.am
Modified: trunk/memcheck/tests/amd64/Makefile.am
==============================================================================
--- trunk/memcheck/tests/amd64/Makefile.am (original)
+++ trunk/memcheck/tests/amd64/Makefile.am Wed Aug 12 12:35:27 2015
@@ -32,7 +32,8 @@
sh-mem-vec256-plo-yes.stdout.exp \
sse_memory.stderr.exp sse_memory.stdout.exp sse_memory.vgtest \
xor-undef-amd64.stderr.exp xor-undef-amd64.stdout.exp \
- xor-undef-amd64.vgtest
+ xor-undef-amd64.vgtest \
+ xsave-avx.vgtest xsave-avx.stdout.exp xsave-avx.stderr.exp
check_PROGRAMS = \
bt_everything \
@@ -45,7 +46,7 @@
sse_memory \
xor-undef-amd64
if BUILD_AVX_TESTS
- check_PROGRAMS += sh-mem-vec256
+ check_PROGRAMS += sh-mem-vec256 xsave-avx
endif
if HAVE_ASM_CONSTRAINT_P
check_PROGRAMS += insn-pcmpistri
Added: trunk/memcheck/tests/amd64/xsave-avx.c
==============================================================================
--- trunk/memcheck/tests/amd64/xsave-avx.c (added)
+++ trunk/memcheck/tests/amd64/xsave-avx.c Wed Aug 12 12:35:27 2015
@@ -0,0 +1,337 @@
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+#include "tests/asm.h"
+#include "tests/malloc.h"
+#include <string.h>
+
+#define XSAVE_AREA_SIZE 832
+
+typedef unsigned char UChar;
+typedef unsigned int UInt;
+typedef unsigned long long int ULong;
+
+typedef unsigned long int UWord;
+
+typedef unsigned char Bool;
+#define True ((Bool)1)
+#define False ((Bool)0)
+
+const unsigned int vec0[8]
+ = { 0x12345678, 0x11223344, 0x55667788, 0x87654321,
+ 0x15263748, 0x91929394, 0x19293949, 0x48372615 };
+
+const unsigned int vec1[8]
+ = { 0xABCDEF01, 0xAABBCCDD, 0xEEFF0011, 0x10FEDCBA,
+ 0xBADCFE10, 0xFFEE9988, 0x11667722, 0x01EFCDAB };
+
+const unsigned int vecZ[8]
+ = { 0, 0, 0, 0, 0, 0, 0, 0 };
+
+/* A version of memset that doesn't use XMM or YMM registers. */
+static __attribute__((noinline))
+void* my_memset(void* s, int c, size_t n)
+{
+ size_t i;
+ for (i = 0; i < n; i++) {
+ ((unsigned char*)s)[i] = (unsigned char)(unsigned int)c;
+ /* Defeat any attempt at autovectorisation */
+ __asm__ __volatile__("" ::: "cc","memory");
+ }
+ return s;
+}
+
+/* Ditto for memcpy */
+static __attribute__((noinline))
+void* my_memcpy(void *dest, const void *src, size_t n)
+{
+ size_t i;
+ for (i = 0; i < n; i++) {
+ ((unsigned char*)dest)[i] = ((unsigned char*)src)[i];
+ __asm__ __volatile__("" ::: "cc","memory");
+ }
+ return dest;
+}
+
+static void* memalign_zeroed(size_t alignment, size_t size)
+{
+ char* p = memalign(alignment, size);
+ if (p && size > 0) {
+ my_memset(p, 0, size);
+ }
+ return p;
+}
+
+__attribute__((noinline))
+static void do_xsave ( void* p, UInt rfbm )
+{
+ assert(rfbm <= 7);
+ __asm__ __volatile__(
+ "movq %0, %%rax; xorq %%rdx, %%rdx; xsave (%1)"
+ : /*OUT*/ : /*IN*/ "r"((ULong)rfbm), "r"(p)
+ : /*TRASH*/ "memory", "rax", "rdx"
+ );
+}
+
+__attribute__((noinline))
+static void do_xrstor ( void* p, UInt rfbm )
+{
+ assert(rfbm <= 7);
+ __asm__ __volatile__(
+ "movq %0, %%rax; xorq %%rdx, %%rdx; xrstor (%1)"
+ : /*OUT*/ : /*IN*/ "r"((ULong)rfbm), "r"(p)
+ : /*TRASH*/ "rax", "rdx" /* FIXME plus all X87,SSE,AVX regs */
+ );
+}
+
+/* set up the FP, SSE and AVX state, and then dump it. */
+static void do_setup_then_xsave ( void* p, UInt rfbm )
+{
+ __asm__ __volatile__("finit");
+ __asm__ __volatile__("fldpi");
+ __asm__ __volatile__("fld1");
+ __asm__ __volatile__("fldln2");
+ __asm__ __volatile__("fldlg2");
+ __asm__ __volatile__("fld %st(3)");
+ __asm__ __volatile__("fld %st(3)");
+ __asm__ __volatile__("fld1");
+ __asm__ __volatile__("vmovups (%0), %%ymm0" : : "r"(&vec0[0]) : "ymm0" );
+ __asm__ __volatile__("vmovups (%0), %%ymm1" : : "r"(&vec1[0]) : "ymm1" );
+ __asm__ __volatile__("vxorps %ymm2, %ymm2, %ymm2");
+ __asm__ __volatile__("vmovaps %ymm0, %ymm3");
+ __asm__ __volatile__("vmovaps %ymm1, %ymm4");
+ __asm__ __volatile__("vmovaps %ymm2, %ymm5");
+ __asm__ __volatile__("vmovaps %ymm0, %ymm6");
+ __asm__ __volatile__("vmovaps %ymm1, %ymm7");
+ __asm__ __volatile__("vmovaps %ymm1, %ymm8");
+ __asm__ __volatile__("vmovaps %ymm2, %ymm9");
+ __asm__ __volatile__("vmovaps %ymm0, %ymm10");
+ __asm__ __volatile__("vmovaps %ymm1, %ymm11");
+ __asm__ __volatile__("vmovaps %ymm1, %ymm12");
+ __asm__ __volatile__("vmovaps %ymm2, %ymm13");
+ __asm__ __volatile__("vmovaps %ymm0, %ymm14");
+ __asm__ __volatile__("vmovaps %ymm1, %ymm15");
+ do_xsave(p, rfbm);
+}
+
+static int isFPLsbs ( int i )
+{
+ int q;
+ q = 32; if (i == q || i == q+1) return 1;
+ q = 48; if (i == q || i == q+1) return 1;
+ q = 64; if (i == q || i == q+1) return 1;
+ q = 80; if (i == q || i == q+1) return 1;
+ q = 96; if (i == q || i == q+1) return 1;
+ q = 112; if (i == q || i == q+1) return 1;
+ q = 128; if (i == q || i == q+1) return 1;
+ q = 144; if (i == q || i == q+1) return 1;
+ return 0;
+}
+
+static void show ( unsigned char* buf, Bool hideBits64to79 )
+{
+ int i;
+ for (i = 0; i < XSAVE_AREA_SIZE; i++) {
+ if ((i % 16) == 0)
+ fprintf(stderr, "%3d ", i);
+ if (hideBits64to79 && isFPLsbs(i))
+ fprintf(stderr, "xx ");
+ else
+ fprintf(stderr, "%02x ", buf[i]);
+ if (i > 0 && ((i % 16) == 15))
+ fprintf(stderr, "\n");
+ }
+}
+
+static void cpuid ( UInt* eax, UInt* ebx, UInt* ecx, UInt* edx,
+ UInt index, UInt ecx_in )
+{
+ UInt a,b,c,d;
+ asm volatile ("cpuid"
+ : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
+ : "0" (index), "2"(ecx_in) );
+ *eax = a; *ebx = b; *ecx = c; *edx = d;
+ //fprintf(stderr, "%08x %08x -> %08x %08x %08x %08x\n",
+ // index,ecx_in, a,b,c,d );
+}
+
+static void xgetbv ( UInt* eax, UInt* edx, UInt ecx_in )
+{
+ UInt a,d;
+ asm volatile ("xgetbv"
+ : "=a" (a), "=d" (d) \
+ : "c"(ecx_in) );
+ *eax = a; *edx = d;
+}
+
+static void check_for_xsave ( void )
+{
+ UInt eax, ebx, ecx, edx;
+ Bool ok = True;
+
+ eax = ebx = ecx = edx = 0;
+ cpuid(&eax, &ebx, &ecx, &edx, 1,0);
+ //fprintf(stderr, "cpuid(1).ecx[26=xsave] = %u\n", (ecx >> 26) & 1);
+ ok = ok && (((ecx >> 26) & 1) == 1);
+
+ eax = ebx = ecx = edx = 0;
+ cpuid(&eax, &ebx, &ecx, &edx, 1,0);
+ //fprintf(stderr, "cpuid(1).ecx[27=osxsave] = %u\n", (ecx >> 27) & 1);
+ ok = ok && (((ecx >> 27) & 1) == 1);
+
+ eax = ebx = ecx = edx = 0;
+ xgetbv(&eax, &edx, 0);
+ //fprintf(stderr, "xgetbv(0) = %u:%u\n", edx, eax);
+ ok = ok && (edx == 0) && (eax == 7);
+
+ if (ok) return;
+
+ fprintf(stderr,
+ "This program must be run on a CPU that supports AVX and XSAVE.\n");
+ exit(1);
+}
+
+
+void test_xsave ( Bool hideBits64to79 )
+{
+ /* Testing XSAVE:
+
+ For RBFM in 0 .. 7 (that is, all combinations): set the x87, SSE
+ and AVX registers with some values, do XSAVE to dump it, and
+ print the resulting buffer. */
+
+ UInt rfbm;
+ for (rfbm = 0; rfbm <= 7; rfbm++) {
+ UChar* saved_img = memalign_zeroed(64, XSAVE_AREA_SIZE);
+
+ my_memset(saved_img, 0xAA, XSAVE_AREA_SIZE);
+ saved_img[512] = 0;
+ do_setup_then_xsave(saved_img, rfbm);
+
+ fprintf(stderr,
+ "------------------ XSAVE, rfbm = %u ------------------\n", rfbm);
+ show(saved_img, hideBits64to79);
+ fprintf(stderr, "\n");
+
+ free(saved_img);
+ }
+}
+
+
+void test_xrstor ( Bool hideBits64to79 )
+{
+ /* Testing XRSTOR is more complex than testing XSAVE, because the
+ loaded value(s) depend not only on what bits are requested (by
+ RBFM) but also on what bits are actually present in the image
+ (defined by XSTATE_BV). So we have to test all 64 (8 x 8)
+ combinations.
+
+ The approach is to fill a memory buffer with data, do XRSTOR
+ from the buffer, them dump all components with XSAVE in a new
+ buffer, and print the result. This is complicated by the fact
+ that we need to be able to see which parts of the state (in
+ registers) are neither overwritten nor zeroed by the restore.
+ Hence the registers must be pre-filled with values which are
+ neither zero nor the data to be loaded. We choose to use 0x55
+ where possible. */
+
+ UChar* fives = memalign_zeroed(64, XSAVE_AREA_SIZE);
+ my_memset(fives, 0x55, XSAVE_AREA_SIZE);
+ /* Set MXCSR so that the insn doesn't fault */
+ fives[24] = 0x80;
+ fives[25] = 0x1f;
+ fives[26] = 0;
+ fives[27] = 0;
+ /* Ditto for the XSAVE header area. Also set XSTATE_BV. */
+ fives[512] = 7;
+ UInt i;
+ for (i = 1; i <= 23; i++) fives[512+i] = 0;
+ /* Fill the x87 register values with something that VEX's
+ 80-vs-64-bit kludging won't mess up -- an 80 bit number which is
+ representable also as 64 bit: 123456789.0123 */
+ for (i = 0; i <= 7; i++) {
+ UChar* p = &fives[32 + 16 * i];
+ p[0]=0x00; p[1]=0xf8; p[2]=0xc2; p[3]=0x64; p[4]=0xa0;
+ p[5]=0xa2; p[6]=0x79; p[7]=0xeb; p[8]=0x19; p[9]=0x40;
+ }
+ /* And mark the tags for all 8 dumped regs as "valid". */
+ fives[4/*FTW*/] = 0xFF;
+
+ /* (1) (see comment in loop below) */
+ UChar* standard_test_data = memalign_zeroed(64, XSAVE_AREA_SIZE);
+ do_setup_then_xsave(standard_test_data, 7);
+
+ UInt xstate_bv, rfbm;
+ for (xstate_bv = 0; xstate_bv <= 7; xstate_bv++) {
+ for (rfbm = 0; rfbm <= 7; rfbm++) {
+ //{ xstate_bv = 7;
+ // { rfbm = 6;
+ /* 1. Copy the "standard test data" into registers, and dump
+ it with XSAVE. This gives us an image we can try
+ restoring from.
+
+ 2. Set the register state to all-0x55s (as far as is
+ possible), so we can see which parts get overwritten
+ and which parts get zeroed on the test restore.
+
+ 3. Do the restore from the image prepared in (1).
+
+ 4. Dump the state with XSAVE and print it.
+ */
+
+ /* (3a). We can't use |standard_test_data| directly, since we
+ need to put in the required |xstate_bv| value. So make a
+ copy and modify that instead. */
+ UChar* img_to_restore_from = memalign_zeroed(64, XSAVE_AREA_SIZE);
+ my_memcpy(img_to_restore_from, standard_test_data, XSAVE_AREA_SIZE);
+ img_to_restore_from[512] = xstate_bv;
+
+ /* (4a) */
+ UChar* saved_img = memalign_zeroed(64, XSAVE_AREA_SIZE);
+ my_memset(saved_img, 0xAA, XSAVE_AREA_SIZE);
+ saved_img[512] = 0;
+
+ /* (2) */
+ do_xrstor(fives, 7);
+
+ // X87, SSE, AVX state LIVE
+
+ /* (3b) */
+ /* and this is what we're actually trying to test */
+ do_xrstor(img_to_restore_from, rfbm);
+
+ // X87, SSE, AVX state LIVE
+
+ /* (4b) */
+ do_xsave(saved_img, 7);
+
+ fprintf(stderr,
+ "---------- XRSTOR, xstate_bv = %u, rfbm = %u ---------\n",
+ xstate_bv, rfbm);
+ show(saved_img, hideBits64to79);
+ fprintf(stderr, "\n");
+
+ free(saved_img);
+ free(img_to_restore_from);
+ }
+ }
+}
+
+
+int main ( int argc, char** argv )
+{
+ Bool hideBits64to79 = argc > 1;
+ fprintf(stderr, "Re-run with any arg to suppress least-significant\n"
+ " 16 bits of 80-bit FP numbers\n");
+
+ check_for_xsave();
+
+ if (1)
+ test_xsave(hideBits64to79);
+
+ if (1)
+ test_xrstor(hideBits64to79);
+
+ return 0;
+}
Added: trunk/memcheck/tests/amd64/xsave-avx.stderr.exp
==============================================================================
--- trunk/memcheck/tests/amd64/xsave-avx.stderr.exp (added)
+++ trunk/memcheck/tests/amd64/xsave-avx.stderr.exp Wed Aug 12 12:35:27 2015
@@ -0,0 +1,3890 @@
+Re-run with any arg to suppress least-significant
+ 16 bits of 80-bit FP numbers
+------------------ XSAVE, rfbm = 0 ------------------
+ 0 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 16 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 32 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 48 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 64 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 80 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 96 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+112 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+128 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+144 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+160 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+176 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+192 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+208 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+224 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+240 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+256 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+272 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+288 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+304 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+320 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+336 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+352 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+368 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+384 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+400 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+416 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+432 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+448 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+464 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+480 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+496 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+512 00 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+528 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+544 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+560 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+576 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+592 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+608 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+624 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+640 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+656 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+672 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+688 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+704 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+720 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+736 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+752 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+768 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+784 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+800 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+816 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+
+------------------ XSAVE, rfbm = 1 ------------------
+ 0 7f 03 00 08 fe 00 00 00 00 00 00 00 00 00 00 00
+ 16 00 00 00 00 00 00 00 00 aa aa aa aa aa aa aa aa
+ 32 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
+ 48 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
+ 64 xx xx 68 21 a2 da 0f c9 00 40 00 00 00 00 00 00
+ 80 xx xx cf fb 84 9a 20 9a fd 3f 00 00 00 00 00 00
+ 96 xx xx cf d1 f7 17 72 b1 fe 3f 00 00 00 00 00 00
+112 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
+128 xx xx 68 21 a2 da 0f c9 00 40 00 00 00 00 00 00
+144 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+160 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+176 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+192 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+208 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+224 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+240 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+256 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+272 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+288 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+304 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+320 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+336 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+352 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+368 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+384 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+400 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+416 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+432 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+448 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+464 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+480 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+496 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+512 01 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+528 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+544 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+560 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+576 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+592 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+608 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+624 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+640 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+656 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+672 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+688 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+704 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+720 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+736 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+752 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+768 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+784 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+800 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+816 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+
+------------------ XSAVE, rfbm = 2 ------------------
+ 0 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 16 aa aa aa aa aa aa aa aa 80 1f 00 00 ff ff 00 00
+ 32 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 48 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 64 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 80 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 96 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+112 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+128 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+144 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+160 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+176 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+192 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+208 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+224 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+240 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+256 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+272 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+288 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+304 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+320 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+336 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+352 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+368 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+384 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+400 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+416 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+432 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+448 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+464 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+480 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+496 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+512 02 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+528 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+544 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+560 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+576 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+592 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+608 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+624 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+640 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+656 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+672 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+688 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+704 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+720 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+736 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+752 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+768 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+784 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+800 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+816 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+
+------------------ XSAVE, rfbm = 3 ------------------
+ 0 7f 03 00 08 fe 00 00 00 00 00 00 00 00 00 00 00
+ 16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
+ 32 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
+ 48 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
+ 64 xx xx 68 21 a2 da 0f c9 00 40 00 00 00 00 00 00
+ 80 xx xx cf fb 84 9a 20 9a fd 3f 00 00 00 00 00 00
+ 96 xx xx cf d1 f7 17 72 b1 fe 3f 00 00 00 00 00 00
+112 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
+128 xx xx 68 21 a2 da 0f c9 00 40 00 00 00 00 00 00
+144 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+160 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+176 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+192 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+208 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+224 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+240 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+256 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+272 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+288 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+304 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+320 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+336 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+352 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+368 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+384 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+400 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+416 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+432 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+448 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+464 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+480 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+496 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+512 03 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+528 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+544 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+560 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+576 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+592 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+608 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+624 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+640 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+656 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+672 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+688 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+704 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+720 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+736 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+752 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+768 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+784 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+800 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+816 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+
+------------------ XSAVE, rfbm = 4 ------------------
+ 0 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 16 aa aa aa aa aa aa aa aa 80 1f 00 00 ff ff 00 00
+ 32 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 48 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 64 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 80 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 96 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+112 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+128 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+144 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+160 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+176 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+192 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+208 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+224 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+240 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+256 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+272 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+288 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+304 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+320 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+336 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+352 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+368 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+384 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+400 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+416 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+432 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+448 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+464 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+480 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+496 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+512 04 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+528 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+544 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+560 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+576 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+592 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+608 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+624 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+640 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+656 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+672 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+688 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+704 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+720 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+736 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+752 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+768 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+784 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+800 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+816 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+
+------------------ XSAVE, rfbm = 5 ------------------
+ 0 7f 03 00 08 fe 00 00 00 00 00 00 00 00 00 00 00
+ 16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
+ 32 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
+ 48 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
+ 64 xx xx 68 21 a2 da 0f c9 00 40 00 00 00 00 00 00
+ 80 xx xx cf fb 84 9a 20 9a fd 3f 00 00 00 00 00 00
+ 96 xx xx cf d1 f7 17 72 b1 fe 3f 00 00 00 00 00 00
+112 xx xx 00 00 00 00 00 80 ff 3f 00 00 00 00 00 00
+128 xx xx 68 21 a2 da 0f c9 00 40 00 00 00 00 00 00
+144 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+160 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+176 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+192 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+208 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+224 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+240 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+256 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+272 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+288 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+304 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+320 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+336 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+352 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+368 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+384 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+400 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+416 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+432 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+448 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+464 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+480 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+496 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+512 05 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+528 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+544 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+560 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+576 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+592 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+608 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+624 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+640 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+656 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+672 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+688 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+704 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+720 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+736 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+752 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+768 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+784 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+800 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+816 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+
+------------------ XSAVE, rfbm = 6 ------------------
+ 0 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 16 aa aa aa aa aa aa aa aa 80 1f 00 00 ff ff 00 00
+ 32 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 48 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 64 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 80 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+ 96 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+112 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+128 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+144 xx xx aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+160 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+176 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+192 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+208 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+224 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+240 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+256 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+272 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+288 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+304 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+320 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+336 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+352 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+368 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+384 78 56 34 12 44 33 22 11 88 77 66 55 21 43 65 87
+400 01 ef cd ab dd cc bb aa 11 00 ff ee ba dc fe 10
+416 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+432 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+448 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+464 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+480 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+496 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+512 06 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+528 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+544 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+560 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+576 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+592 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+608 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+624 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+640 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+656 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+672 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+688 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+704 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
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+800 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+816 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+
+------------------ XSAVE, rfbm = 7 ------------------
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+800 48 37 26 15 94 93 92 91 49 39 29 19 15 26 37 48
+816 10 fe dc ba 88 99 ee ff 22 77 66 11 ab cd ef 01
+
+---------- XRSTOR, xstate_bv = 0, rfbm = 0 ---------
+ 0 7f 07 00 55 ff 00 00 00 00 00 00 00 00 00 00 00
+ 16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
+ 32 xx xx c2 64 a0 a2 79 eb 19 40 00 00 00 00 00 00
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+800 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
+816 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
+
+---------- XRSTOR, xstate_bv = 0, rfbm = 1 ---------
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+ 16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
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+800 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
+816 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
+
+---------- XRSTOR, xstate_bv = 0, rfbm = 2 ---------
+ 0 7f 07 00 55 ff 00 00 00 00 00 00 00 00 00 00 00
+ 16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
+ 32 xx xx c2 64 a0 a2 79 eb 19 40 00 00 00 00 00 00
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+800 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
+816 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
+
+---------- XRSTOR, xstate_bv = 0, rfbm = 3 ---------
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+800 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
+816 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
+
+---------- XRSTOR, xstate_bv = 0, rfbm = 4 ---------
+ 0 7f 07 00 55 ff 00 00 00 00 00 00 00 00 00 00 00
+ 16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
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+800 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+
+---------- XRSTOR, xstate_bv = 0, rfbm = 5 ---------
+ 0 7f 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
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+800 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+816 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+---------- XRSTOR, xstate_bv = 0, rfbm = 6 ---------
+ 0 7f 07 00 55 ff 00 00 00 00 00 00 00 00 00 00 00
+ 16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
+ 32 xx xx c2 64 a0 a2 79 eb 19 40 00 00 00 00 00 00
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+256 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+272 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+288 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+304 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+320 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+336 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+352 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+368 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+384 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+400 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+416 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+432 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+448 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+464 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+480 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+496 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+512 07 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+528 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+544 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+560 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+576 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+592 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+608 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+624 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+640 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+656 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+672 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+688 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+704 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+720 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+736 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+752 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+768 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+784 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+800 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+816 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+---------- XRSTOR, xstate_bv = 0, rfbm = 7 ---------
+ 0 7f 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
+ 32 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 48 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 64 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 80 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 96 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+112 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+128 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+144 xx xx 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+160 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+176 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+192 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+208 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+224 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+240 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+256 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+272 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+288 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+304 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+320 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+336 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+352 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+368 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+384 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+400 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+416 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+432 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+448 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+464 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+480 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+496 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+512 07 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+528 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+544 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+560 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
+576 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+592 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+608 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+624 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+640 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+656 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+672 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+688 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+704 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+720 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+736 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+752 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+768 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+784 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+800 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+816 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+---------- XRSTOR, xstate_bv = 1, rfbm = 0 ---------
+ 0 7f 07 00 55 ff 00 00 00 00 00 00 00 00 00 00 00
+ 16 00 00 00 00 00 00 00 00 80 1f 00 00 ff ff 00 00
+ 32 xx xx c2 64 a0 a2 79 eb 19 40 00 00 00 00 00 00
+ 48 xx xx c2 64 a0 a2 79 eb 19 40 00 00 00 00 00 00
+ 64 xx xx c2 64 a0 a2 79 eb 19 40 00 00 00 00 00 00
+ 80 xx xx c2 64 a0 a2 79 eb 19 40 00 00 00 00 00 00
+ 96 xx xx c2 64 a0 a2 79 eb 19 40 00 00 00 00 00 00
+112 xx xx c2 64 a0 a2 79 eb 19 40 00 00 00 00 00 00
+128 xx xx c2 64 a0 a2 79 eb 19 40 00 00 00 00 00 00
+144 xx xx c2 64 a0 a2 79 eb 19 40 00 00 00 00 00 00
+160 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
+176 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
+192 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55
+208 55 55 55 55 55 5...
[truncated message content] |
|
From: Julian S. <js...@ac...> - 2015-08-12 11:26:25
|
In revs 3169, 15522, 15523, I finally implemented the XSAVE and XRSTOR instructions which are associated with the AVX instruction set. These provide saving and restoring for the new state introduced by AVX -- that is, the YMM high half registers. They also generalise the existing FXSAVE/FXRSTOR instructions (for SSE+X87) and FSAVE/FRSTOR instructions (X87 only). As part of this I added a new CPUID implementation that reflects AVX2 capable processors. As a result of this it should be possible to run code that requires XSAVE/XRSTOR, in particular AVX and AVX2 code generated by the Intel compiler. These instructions are a nightmare of complexity. I think I didn't break anything, but there is a risk of fallout, particularly for the OSX and Solaris ports. So it would be good to watch out for that. J |
|
From: <sv...@va...> - 2015-08-12 11:16:54
|
Author: sewardj
Date: Wed Aug 12 12:16:47 2015
New Revision: 15523
Log:
Enhance VG_(machine_get_hwcaps) to check enough stuff to ensure
that VEX's XSAVE/XRSTOR implementation will work correctly.
Modified:
trunk/coregrind/m_machine.c
Modified: trunk/coregrind/m_machine.c
==============================================================================
--- trunk/coregrind/m_machine.c (original)
+++ trunk/coregrind/m_machine.c Wed Aug 12 12:16:47 2015
@@ -878,6 +878,7 @@
Bool have_lzcnt, have_avx, have_bmi, have_avx2;
Bool have_rdtscp;
UInt eax, ebx, ecx, edx, max_basic, max_extended;
+ ULong xgetbv_0 = 0;
HChar vstr[13];
vstr[0] = 0;
@@ -910,26 +911,41 @@
// sse41 is ecx:19
// sse42 is ecx:20
+ // xsave is ecx:26
// osxsave is ecx:27
// avx is ecx:28
// fma is ecx:12
have_avx = False;
/* have_fma = False; */
- if ( (ecx & ((1<<27)|(1<<28))) == ((1<<27)|(1<<28)) ) {
- /* processor supports AVX instructions and XGETBV is enabled
- by OS */
+ if ( (ecx & ((1<<28)|(1<<27)|(1<<26))) == ((1<<28)|(1<<27)|(1<<26)) ) {
+ /* Processor supports AVX instructions and XGETBV is enabled
+ by OS and AVX instructions are enabled by the OS. */
ULong w;
__asm__ __volatile__("movq $0,%%rcx ; "
".byte 0x0F,0x01,0xD0 ; " /* xgetbv */
"movq %%rax,%0"
:/*OUT*/"=r"(w) :/*IN*/
- :/*TRASH*/"rdx","rcx");
- if ((w & 6) == 6) {
- /* OS has enabled both XMM and YMM state support */
- have_avx = True;
+ :/*TRASH*/"rdx","rcx","rax");
+ xgetbv_0 = w;
+ if ((xgetbv_0 & 7) == 7) {
+ /* Only say we have AVX if the XSAVE-allowable
+ bitfield-mask allows x87, SSE and AVX state. We could
+ actually run with a more restrictive XGETBV(0) value,
+ but VEX's implementation of XSAVE and XRSTOR assumes
+ that all 3 bits are enabled.
+
+ Also, the VEX implementation of XSAVE/XRSTOR assumes that
+ state component [2] (the YMM high halves) are located in
+ the XSAVE image at offsets 576 .. 831. So we have to
+ check that here before declaring AVX to be supported. */
+ UInt eax2, ebx2, ecx2, edx2;
+ VG_(cpuid)(0xD, 2, &eax2, &ebx2, &ecx2, &edx2);
+ if (ebx2 == 576 && eax2 == 256) {
+ have_avx = True;
+ }
/* have_fma = (ecx & (1<<12)) != 0; */
/* have_fma: Probably correct, but gcc complains due to
- unusedness. &*/
+ unusedness. */
}
}
@@ -957,12 +973,12 @@
have_rdtscp = (edx & (1<<27)) != 0; /* True => have RDTSVCP */
}
- /* Check for BMI1 and AVX2. If we have AVX1 (plus OS support). */
- have_bmi = False;
+ /* Check for BMI1 and AVX2. If we have AVX1 (plus OS support). */
+ have_bmi = False;
have_avx2 = False;
if (have_avx && max_basic >= 7) {
VG_(cpuid)(7, 0, &eax, &ebx, &ecx, &edx);
- have_bmi = (ebx & (1<<3)) != 0; /* True => have BMI1 */
+ have_bmi = (ebx & (1<<3)) != 0; /* True => have BMI1 */
have_avx2 = (ebx & (1<<5)) != 0; /* True => have AVX2 */
}
|
|
From: <sv...@va...> - 2015-08-12 11:16:30
|
Author: sewardj
Date: Wed Aug 12 12:16:23 2015
New Revision: 15522
Log:
Handle new ILGop_IdentV128 introduced by vex r3169.
Modified:
trunk/memcheck/mc_translate.c
Modified: trunk/memcheck/mc_translate.c
==============================================================================
--- trunk/memcheck/mc_translate.c (original)
+++ trunk/memcheck/mc_translate.c Wed Aug 12 12:16:23 2015
@@ -6073,12 +6073,13 @@
IROp vwiden = Iop_INVALID;
IRType loadedTy = Ity_INVALID;
switch (lg->cvt) {
- case ILGop_Ident64: loadedTy = Ity_I64; vwiden = Iop_INVALID; break;
- case ILGop_Ident32: loadedTy = Ity_I32; vwiden = Iop_INVALID; break;
- case ILGop_16Uto32: loadedTy = Ity_I16; vwiden = Iop_16Uto32; break;
- case ILGop_16Sto32: loadedTy = Ity_I16; vwiden = Iop_16Sto32; break;
- case ILGop_8Uto32: loadedTy = Ity_I8; vwiden = Iop_8Uto32; break;
- case ILGop_8Sto32: loadedTy = Ity_I8; vwiden = Iop_8Sto32; break;
+ case ILGop_IdentV128: loadedTy = Ity_V128; vwiden = Iop_INVALID; break;
+ case ILGop_Ident64: loadedTy = Ity_I64; vwiden = Iop_INVALID; break;
+ case ILGop_Ident32: loadedTy = Ity_I32; vwiden = Iop_INVALID; break;
+ case ILGop_16Uto32: loadedTy = Ity_I16; vwiden = Iop_16Uto32; break;
+ case ILGop_16Sto32: loadedTy = Ity_I16; vwiden = Iop_16Sto32; break;
+ case ILGop_8Uto32: loadedTy = Ity_I8; vwiden = Iop_8Uto32; break;
+ case ILGop_8Sto32: loadedTy = Ity_I8; vwiden = Iop_8Sto32; break;
default: VG_(tool_panic)("do_shadow_LoadG");
}
@@ -7309,12 +7310,13 @@
{
IRType loadedTy = Ity_INVALID;
switch (lg->cvt) {
- case ILGop_Ident64: loadedTy = Ity_I64; break;
- case ILGop_Ident32: loadedTy = Ity_I32; break;
- case ILGop_16Uto32: loadedTy = Ity_I16; break;
- case ILGop_16Sto32: loadedTy = Ity_I16; break;
- case ILGop_8Uto32: loadedTy = Ity_I8; break;
- case ILGop_8Sto32: loadedTy = Ity_I8; break;
+ case ILGop_IdentV128: loadedTy = Ity_V128; break;
+ case ILGop_Ident64: loadedTy = Ity_I64; break;
+ case ILGop_Ident32: loadedTy = Ity_I32; break;
+ case ILGop_16Uto32: loadedTy = Ity_I16; break;
+ case ILGop_16Sto32: loadedTy = Ity_I16; break;
+ case ILGop_8Uto32: loadedTy = Ity_I8; break;
+ case ILGop_8Sto32: loadedTy = Ity_I8; break;
default: VG_(tool_panic)("schemeS.IRLoadG");
}
IRAtom* ori_alt
|
Author: sewardj
Date: Wed Aug 12 12:15:53 2015
New Revision: 3169
Log:
Implement XSAVE/XRSTOR for AVX (state components 0, 1 and 2)
Refactor existing FXSAVE / FXRSTOR implementation so as to use
the new code, since these are sub-cases of the general XSAVE/XRSTOR
functionality.
Add a new CPUID level to indicate CPUs which are AVX2 compatible,
and enable it by default on AVX2 compatible hosts.
For both the AVX and AVX2 simulated CPUIDs, claim that XSAVEOPT is not
supported, in an attempt to avoid having to implement it.
Remove CPUID kludgery to do with OSX 10.10 (Yosemite) in order to
persuade it not to use XSAVE/XRSTOR.
libvex_ir.h: add new guarded load conversion "ILGop_IdentV128"
as required by XSAVE/XRSTOR support.
Modified:
trunk/priv/guest_amd64_defs.h
trunk/priv/guest_amd64_helpers.c
trunk/priv/guest_amd64_toIR.c
trunk/priv/host_amd64_defs.c
trunk/priv/host_amd64_defs.h
trunk/priv/host_amd64_isel.c
trunk/priv/ir_defs.c
trunk/priv/ir_opt.c
trunk/pub/libvex_ir.h
Modified: trunk/priv/guest_amd64_defs.h
==============================================================================
--- trunk/priv/guest_amd64_defs.h (original)
+++ trunk/priv/guest_amd64_defs.h Wed Aug 12 12:15:53 2015
@@ -168,13 +168,19 @@
extern void amd64g_dirtyhelper_CPUID_sse3_and_cx16 ( VexGuestAMD64State* st );
extern void amd64g_dirtyhelper_CPUID_sse42_and_cx16 ( VexGuestAMD64State* st );
extern void amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st );
+extern void amd64g_dirtyhelper_CPUID_avx2 ( VexGuestAMD64State* st );
extern void amd64g_dirtyhelper_FINIT ( VexGuestAMD64State* );
-extern void amd64g_dirtyhelper_FXSAVE_ALL_EXCEPT_XMM
- ( VexGuestAMD64State*, HWord );
-extern VexEmNote amd64g_dirtyhelper_FXRSTOR_ALL_EXCEPT_XMM
- ( VexGuestAMD64State*, HWord );
+extern void amd64g_dirtyhelper_XSAVE_COMPONENT_0
+ ( VexGuestAMD64State* gst, HWord addr );
+extern void amd64g_dirtyhelper_XSAVE_COMPONENT_1_EXCLUDING_XMMREGS
+ ( VexGuestAMD64State* gst, HWord addr );
+
+extern VexEmNote amd64g_dirtyhelper_XRSTOR_COMPONENT_0
+ ( VexGuestAMD64State* gst, HWord addr );
+extern VexEmNote amd64g_dirtyhelper_XRSTOR_COMPONENT_1_EXCLUDING_XMMREGS
+ ( VexGuestAMD64State* gst, HWord addr );
extern ULong amd64g_dirtyhelper_RDTSC ( void );
extern void amd64g_dirtyhelper_RDTSCP ( VexGuestAMD64State* st );
Modified: trunk/priv/guest_amd64_helpers.c
==============================================================================
--- trunk/priv/guest_amd64_helpers.c (original)
+++ trunk/priv/guest_amd64_helpers.c Wed Aug 12 12:15:53 2015
@@ -1943,8 +1943,15 @@
}
-static
-void do_fxsave ( VexGuestAMD64State* gst, HWord addr, Bool save_xmm_regs )
+/*---------------------------------------------------------------*/
+/*--- Supporting functions for XSAVE/FXSAVE. ---*/
+/*---------------------------------------------------------------*/
+
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (reads guest state, writes guest mem) */
+/* XSAVE component 0 is the x87 FPU state. */
+void amd64g_dirtyhelper_XSAVE_COMPONENT_0
+ ( VexGuestAMD64State* gst, HWord addr )
{
/* Derived from values obtained from
vendor_id : AuthenticAMD
@@ -1959,17 +1966,15 @@
Fpu_State tmp;
UShort* addrS = (UShort*)addr;
UChar* addrC = (UChar*)addr;
- UInt mxcsr;
UShort fp_tags;
UInt summary_tags;
Int r, stno;
UShort *srcS, *dstS;
do_get_x87( gst, (UChar*)&tmp );
- mxcsr = amd64g_create_mxcsr( gst->guest_SSEROUND );
- /* Now build the proper fxsave image from the x87 image we just
- made. */
+ /* Now build the proper fxsave x87 image from the fsave x87 image
+ we just made. */
addrS[0] = tmp.env[FP_ENV_CTRL]; /* FCW: fpu control word */
addrS[1] = tmp.env[FP_ENV_STAT]; /* FCW: fpu status word */
@@ -2002,11 +2007,8 @@
addrS[10] = 0; /* BOGUS */
addrS[11] = 0; /* BOGUS */
- addrS[12] = toUShort(mxcsr); /* MXCSR */
- addrS[13] = toUShort(mxcsr >> 16);
-
- addrS[14] = 0xFFFF; /* MXCSR mask (lo16) */
- addrS[15] = 0x0000; /* MXCSR mask (hi16) */
+ /* addrS[13,12] are MXCSR -- not written */
+ /* addrS[15,14] are MXCSR_MASK -- not written */
/* Copy in the FP registers, in ST order. */
for (stno = 0; stno < 8; stno++) {
@@ -2021,94 +2023,95 @@
dstS[6] = 0;
dstS[7] = 0;
}
+}
+
+
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (reads guest state, writes guest mem) */
+/* XSAVE component 1 is the SSE state. */
+void amd64g_dirtyhelper_XSAVE_COMPONENT_1_EXCLUDING_XMMREGS
+ ( VexGuestAMD64State* gst, HWord addr )
+{
+ UShort* addrS = (UShort*)addr;
+ UInt mxcsr;
+
+ /* The only non-register parts of the SSE state are MXCSR and
+ MXCSR_MASK. */
+ mxcsr = amd64g_create_mxcsr( gst->guest_SSEROUND );
+
+ addrS[12] = toUShort(mxcsr); /* MXCSR */
+ addrS[13] = toUShort(mxcsr >> 16);
+
+ addrS[14] = 0xFFFF; /* MXCSR mask (lo16) */
+ addrS[15] = 0x0000; /* MXCSR mask (hi16) */
+}
+
+
+/* VISIBLE TO LIBVEX CLIENT */
+/* Do FXSAVE from the supplied VexGuestAMD64State structure and store
+ the result at the given address which represents a buffer of at
+ least 416 bytes.
+
+ This function is not called from generated code. FXSAVE is dealt
+ with by the amd64 front end by calling the XSAVE_COMPONENT_{0,1}
+ functions above plus some in-line IR. This function is merely a
+ convenience function for VEX's users.
+*/
+void LibVEX_GuestAMD64_fxsave ( /*IN*/VexGuestAMD64State* gst,
+ /*OUT*/HWord fp_state )
+{
+ /* Do the x87 part */
+ amd64g_dirtyhelper_XSAVE_COMPONENT_0(gst, fp_state);
+
+ /* And now the SSE part, except for the registers themselves. */
+ amd64g_dirtyhelper_XSAVE_COMPONENT_1_EXCLUDING_XMMREGS(gst, fp_state);
/* That's the first 160 bytes of the image done. */
- if (save_xmm_regs == True) {
- /* Now only %xmm0 .. %xmm15 remain to be copied. If the host is
- big-endian, these need to be byte-swapped. */
- U128 *xmm = (U128 *)(addr + 160);
-
- vassert(host_is_little_endian());
-
-# define COPY_U128(_dst,_src) \
- do { _dst[0] = _src[0]; _dst[1] = _src[1]; \
- _dst[2] = _src[2]; _dst[3] = _src[3]; } \
- while (0)
-
- COPY_U128( xmm[0], gst->guest_YMM0 );
- COPY_U128( xmm[1], gst->guest_YMM1 );
- COPY_U128( xmm[2], gst->guest_YMM2 );
- COPY_U128( xmm[3], gst->guest_YMM3 );
- COPY_U128( xmm[4], gst->guest_YMM4 );
- COPY_U128( xmm[5], gst->guest_YMM5 );
- COPY_U128( xmm[6], gst->guest_YMM6 );
- COPY_U128( xmm[7], gst->guest_YMM7 );
- COPY_U128( xmm[8], gst->guest_YMM8 );
- COPY_U128( xmm[9], gst->guest_YMM9 );
- COPY_U128( xmm[10], gst->guest_YMM10 );
- COPY_U128( xmm[11], gst->guest_YMM11 );
- COPY_U128( xmm[12], gst->guest_YMM12 );
- COPY_U128( xmm[13], gst->guest_YMM13 );
- COPY_U128( xmm[14], gst->guest_YMM14 );
- COPY_U128( xmm[15], gst->guest_YMM15 );
+ /* Now only %xmm0 .. %xmm15 remain to be copied. If the host is
+ big-endian, these need to be byte-swapped. */
+ U128 *xmm = (U128 *)(fp_state + 160);
+ vassert(host_is_little_endian());
+
+# define COPY_U128(_dst,_src) \
+ do { _dst[0] = _src[0]; _dst[1] = _src[1]; \
+ _dst[2] = _src[2]; _dst[3] = _src[3]; } \
+ while (0)
+
+ COPY_U128( xmm[0], gst->guest_YMM0 );
+ COPY_U128( xmm[1], gst->guest_YMM1 );
+ COPY_U128( xmm[2], gst->guest_YMM2 );
+ COPY_U128( xmm[3], gst->guest_YMM3 );
+ COPY_U128( xmm[4], gst->guest_YMM4 );
+ COPY_U128( xmm[5], gst->guest_YMM5 );
+ COPY_U128( xmm[6], gst->guest_YMM6 );
+ COPY_U128( xmm[7], gst->guest_YMM7 );
+ COPY_U128( xmm[8], gst->guest_YMM8 );
+ COPY_U128( xmm[9], gst->guest_YMM9 );
+ COPY_U128( xmm[10], gst->guest_YMM10 );
+ COPY_U128( xmm[11], gst->guest_YMM11 );
+ COPY_U128( xmm[12], gst->guest_YMM12 );
+ COPY_U128( xmm[13], gst->guest_YMM13 );
+ COPY_U128( xmm[14], gst->guest_YMM14 );
+ COPY_U128( xmm[15], gst->guest_YMM15 );
# undef COPY_U128
- } else {
- /* We let the generated IR to copy remaining %xmm0 .. %xmm15, so as to
- make Memcheck's definedness flow for the non-XMM parts independent from
- that of the all the other control and status words in the structure.
- This avoids the false positives shown in #291310. */
- }
}
-static
-VexEmNote do_fxrstor ( VexGuestAMD64State* gst, HWord addr,
- Bool rstor_xmm_regs )
+/*---------------------------------------------------------------*/
+/*--- Supporting functions for XRSTOR/FXRSTOR. ---*/
+/*---------------------------------------------------------------*/
+
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (writes guest state, reads guest mem) */
+VexEmNote amd64g_dirtyhelper_XRSTOR_COMPONENT_0
+ ( VexGuestAMD64State* gst, HWord addr )
{
Fpu_State tmp;
- VexEmNote warnX87 = EmNote_NONE;
- VexEmNote warnXMM = EmNote_NONE;
UShort* addrS = (UShort*)addr;
UChar* addrC = (UChar*)addr;
UShort fp_tags;
Int r, stno, i;
- if (rstor_xmm_regs == True) {
- /* Restore %xmm0 .. %xmm15. If the host is big-endian, these need
- to be byte-swapped. */
- U128 *xmm = (U128 *)(addr + 160);
-
- vassert(host_is_little_endian());
-
-# define COPY_U128(_dst,_src) \
- do { _dst[0] = _src[0]; _dst[1] = _src[1]; \
- _dst[2] = _src[2]; _dst[3] = _src[3]; } \
- while (0)
-
- COPY_U128( gst->guest_YMM0, xmm[0] );
- COPY_U128( gst->guest_YMM1, xmm[1] );
- COPY_U128( gst->guest_YMM2, xmm[2] );
- COPY_U128( gst->guest_YMM3, xmm[3] );
- COPY_U128( gst->guest_YMM4, xmm[4] );
- COPY_U128( gst->guest_YMM5, xmm[5] );
- COPY_U128( gst->guest_YMM6, xmm[6] );
- COPY_U128( gst->guest_YMM7, xmm[7] );
- COPY_U128( gst->guest_YMM8, xmm[8] );
- COPY_U128( gst->guest_YMM9, xmm[9] );
- COPY_U128( gst->guest_YMM10, xmm[10] );
- COPY_U128( gst->guest_YMM11, xmm[11] );
- COPY_U128( gst->guest_YMM12, xmm[12] );
- COPY_U128( gst->guest_YMM13, xmm[13] );
- COPY_U128( gst->guest_YMM14, xmm[14] );
- COPY_U128( gst->guest_YMM15, xmm[15] );
-
-# undef COPY_U128
- } else {
- /* Don't restore %xmm0 .. %xmm15, for the same reasons that
- do_fxsave(save_xmm_regs = False) doesn't save them. See
- comment in that function for details. */
- }
-
/* Copy the x87 registers out of the image, into a temporary
Fpu_State struct. */
for (i = 0; i < 14; i++) tmp.env[i] = 0;
@@ -2137,16 +2140,75 @@
tmp.env[FP_ENV_TAG] = fp_tags;
/* Now write 'tmp' into the guest state. */
- warnX87 = do_put_x87( True/*moveRegs*/, (UChar*)&tmp, gst );
+ VexEmNote warnX87 = do_put_x87( True/*moveRegs*/, (UChar*)&tmp, gst );
- { UInt w32 = (((UInt)addrS[12]) & 0xFFFF)
- | ((((UInt)addrS[13]) & 0xFFFF) << 16);
- ULong w64 = amd64g_check_ldmxcsr( (ULong)w32 );
+ return warnX87;
+}
- warnXMM = (VexEmNote)(w64 >> 32);
- gst->guest_SSEROUND = w64 & 0xFFFFFFFFULL;
- }
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (writes guest state, reads guest mem) */
+VexEmNote amd64g_dirtyhelper_XRSTOR_COMPONENT_1_EXCLUDING_XMMREGS
+ ( VexGuestAMD64State* gst, HWord addr )
+{
+ UShort* addrS = (UShort*)addr;
+ UInt w32 = (((UInt)addrS[12]) & 0xFFFF)
+ | ((((UInt)addrS[13]) & 0xFFFF) << 16);
+ ULong w64 = amd64g_check_ldmxcsr( (ULong)w32 );
+
+ VexEmNote warnXMM = (VexEmNote)(w64 >> 32);
+
+ gst->guest_SSEROUND = w64 & 0xFFFFFFFFULL;
+ return warnXMM;
+}
+
+
+/* VISIBLE TO LIBVEX CLIENT */
+/* Do FXRSTOR from the supplied address and store read values to the given
+ VexGuestAMD64State structure.
+
+ This function is not called from generated code. FXRSTOR is dealt
+ with by the amd64 front end by calling the XRSTOR_COMPONENT_{0,1}
+ functions above plus some in-line IR. This function is merely a
+ convenience function for VEX's users.
+*/
+VexEmNote LibVEX_GuestAMD64_fxrstor ( /*IN*/HWord fp_state,
+ /*MOD*/VexGuestAMD64State* gst )
+{
+ /* Restore %xmm0 .. %xmm15. If the host is big-endian, these need
+ to be byte-swapped. */
+ U128 *xmm = (U128 *)(fp_state + 160);
+
+ vassert(host_is_little_endian());
+
+# define COPY_U128(_dst,_src) \
+ do { _dst[0] = _src[0]; _dst[1] = _src[1]; \
+ _dst[2] = _src[2]; _dst[3] = _src[3]; } \
+ while (0)
+
+ COPY_U128( gst->guest_YMM0, xmm[0] );
+ COPY_U128( gst->guest_YMM1, xmm[1] );
+ COPY_U128( gst->guest_YMM2, xmm[2] );
+ COPY_U128( gst->guest_YMM3, xmm[3] );
+ COPY_U128( gst->guest_YMM4, xmm[4] );
+ COPY_U128( gst->guest_YMM5, xmm[5] );
+ COPY_U128( gst->guest_YMM6, xmm[6] );
+ COPY_U128( gst->guest_YMM7, xmm[7] );
+ COPY_U128( gst->guest_YMM8, xmm[8] );
+ COPY_U128( gst->guest_YMM9, xmm[9] );
+ COPY_U128( gst->guest_YMM10, xmm[10] );
+ COPY_U128( gst->guest_YMM11, xmm[11] );
+ COPY_U128( gst->guest_YMM12, xmm[12] );
+ COPY_U128( gst->guest_YMM13, xmm[13] );
+ COPY_U128( gst->guest_YMM14, xmm[14] );
+ COPY_U128( gst->guest_YMM15, xmm[15] );
+
+# undef COPY_U128
+
+ VexEmNote warnXMM
+ = amd64g_dirtyhelper_XRSTOR_COMPONENT_1_EXCLUDING_XMMREGS(gst, fp_state);
+ VexEmNote warnX87
+ = amd64g_dirtyhelper_XRSTOR_COMPONENT_0(gst, fp_state);
/* Prefer an X87 emwarn over an XMM one, if both exist. */
if (warnX87 != EmNote_NONE)
@@ -2156,24 +2218,9 @@
}
-/* CALLED FROM GENERATED CODE */
-/* DIRTY HELPER (reads guest state, writes guest mem) */
-/* NOTE: only handles 32-bit format (no REX.W on the insn) */
-/* NOTE: does not save XMM registers - see do_fxsave() for details */
-void amd64g_dirtyhelper_FXSAVE_ALL_EXCEPT_XMM ( VexGuestAMD64State* gst,
- HWord addr )
-{
- do_fxsave( gst, addr, False );
-}
-
-/* CALLED FROM GENERATED CODE */
-/* DIRTY HELPER (writes guest state, reads guest mem) */
-VexEmNote amd64g_dirtyhelper_FXRSTOR_ALL_EXCEPT_XMM ( VexGuestAMD64State* gst,
- HWord addr )
-{
- return do_fxrstor( gst, addr, False );
-}
-
+/*---------------------------------------------------------------*/
+/*--- Supporting functions for FSAVE/FRSTOR ---*/
+/*---------------------------------------------------------------*/
/* DIRTY HELPER (writes guest state) */
/* Initialise the x87 FPU state as per 'finit'. */
@@ -2465,28 +2512,9 @@
return ew;
}
-/* VISIBLE TO LIBVEX CLIENT */
-/* Do FXSAVE from the supplied VexGuestAMD64tate structure and store the
- result at the given address which represents a buffer of at least 416
- bytes. Saves also XMM registers. */
-void LibVEX_GuestAMD64_fxsave ( /*IN*/VexGuestAMD64State* gst,
- /*OUT*/HWord fp_state )
-{
- do_fxsave( gst, fp_state, True );
-}
-
-/* VISIBLE TO LIBVEX CLIENT */
-/* Do FXRSTOR from the supplied address and store read values to the given
- VexGuestAMD64State structure. Restores also XMM registers. */
-VexEmNote LibVEX_GuestAMD64_fxrstor ( /*IN*/HWord fp_state,
- /*MOD*/VexGuestAMD64State* gst )
-{
- return do_fxrstor( gst, fp_state, True );
-}
-
/*---------------------------------------------------------------*/
-/*--- Misc integer helpers, including rotates and CPUID. ---*/
+/*--- CPUID helpers. ---*/
/*---------------------------------------------------------------*/
/* Claim to be the following CPU, which is probably representative of
@@ -2845,6 +2873,14 @@
/* Claim to be the following CPU (4 x ...), which is AVX and cx16
capable. Plus (kludge!) it "supports" HTM.
+ Also with the following change: claim that XSaveOpt is not
+ available, by cpuid(eax=0xD,ecx=1).eax[0] returns 0, compared to 1
+ on the real CPU. Consequently, programs that correctly observe
+ these CPUID values should only try to use 3 of the 8 XSave-family
+ instructions: XGETBV, XSAVE and XRSTOR. In particular this avoids
+ having to implement the compacted or optimised save/restore
+ variants.
+
vendor_id : GenuineIntel
cpu family : 6
model : 42
@@ -2955,7 +2991,7 @@
switch (old_ecx) {
case 0x00000000: SET_ABCD(0x00000007, 0x00000340,
0x00000340, 0x00000000); break;
- case 0x00000001: SET_ABCD(0x00000001, 0x00000000,
+ case 0x00000001: SET_ABCD(0x00000000, 0x00000000,
0x00000000, 0x00000000); break;
case 0x00000002: SET_ABCD(0x00000100, 0x00000240,
0x00000000, 0x00000000); break;
@@ -3004,6 +3040,176 @@
}
+/* Claim to be the following CPU (4 x ...), which is AVX2 capable.
+
+ With the following change: claim that XSaveOpt is not available, by
+ cpuid(eax=0xD,ecx=1).eax[0] returns 0, compared to 1 on the real
+ CPU. Consequently, programs that correctly observe these CPUID
+ values should only try to use 3 of the 8 XSave-family instructions:
+ XGETBV, XSAVE and XRSTOR. In particular this avoids having to
+ implement the compacted or optimised save/restore variants.
+
+ vendor_id : GenuineIntel
+ cpu family : 6
+ model : 60
+ model name : Intel(R) Core(TM) i7-4910MQ CPU @ 2.90GHz
+ stepping : 3
+ microcode : 0x1c
+ cpu MHz : 919.957
+ cache size : 8192 KB
+ physical id : 0
+ siblings : 4
+ core id : 3
+ cpu cores : 4
+ apicid : 6
+ initial apicid : 6
+ fpu : yes
+ fpu_exception : yes
+ cpuid level : 13
+ wp : yes
+ flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
+ cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht
+ tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc
+ arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc
+ aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl
+ vmx smx est tm2 ssse3 fma cx16 xtpr pdcm pcid sse4_1
+ sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave
+ avx f16c rdrand lahf_lm abm ida arat epb pln pts dtherm
+ tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust
+ bmi1 avx2 smep bmi2 erms invpcid xsaveopt
+ bugs :
+ bogomips : 5786.68
+ clflush size : 64
+ cache_alignment : 64
+ address sizes : 39 bits physical, 48 bits virtual
+ power management:
+*/
+void amd64g_dirtyhelper_CPUID_avx2 ( VexGuestAMD64State* st )
+{
+# define SET_ABCD(_a,_b,_c,_d) \
+ do { st->guest_RAX = (ULong)(_a); \
+ st->guest_RBX = (ULong)(_b); \
+ st->guest_RCX = (ULong)(_c); \
+ st->guest_RDX = (ULong)(_d); \
+ } while (0)
+
+ UInt old_eax = (UInt)st->guest_RAX;
+ UInt old_ecx = (UInt)st->guest_RCX;
+
+ switch (old_eax) {
+ case 0x00000000:
+ SET_ABCD(0x0000000d, 0x756e6547, 0x6c65746e, 0x49656e69);
+ break;
+ case 0x00000001:
+ SET_ABCD(0x000306c3, 0x02100800, 0x7ffafbff, 0xbfebfbff);
+ break;
+ case 0x00000002:
+ SET_ABCD(0x76036301, 0x00f0b6ff, 0x00000000, 0x00c10000);
+ break;
+ case 0x00000003:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x00000004:
+ switch (old_ecx) {
+ case 0x00000000: SET_ABCD(0x1c004121, 0x01c0003f,
+ 0x0000003f, 0x00000000); break;
+ case 0x00000001: SET_ABCD(0x1c004122, 0x01c0003f,
+ 0x0000003f, 0x00000000); break;
+ case 0x00000002: SET_ABCD(0x1c004143, 0x01c0003f,
+ 0x000001ff, 0x00000000); break;
+ case 0x00000003: SET_ABCD(0x1c03c163, 0x03c0003f,
+ 0x00001fff, 0x00000006); break;
+ default: SET_ABCD(0x00000000, 0x00000000,
+ 0x00000000, 0x00000000); break;
+ }
+ break;
+ case 0x00000005:
+ SET_ABCD(0x00000040, 0x00000040, 0x00000003, 0x00042120);
+ break;
+ case 0x00000006:
+ SET_ABCD(0x00000077, 0x00000002, 0x00000009, 0x00000000);
+ break;
+ case 0x00000007:
+ switch (old_ecx) {
+ case 0x00000000: SET_ABCD(0x00000000, 0x000027ab,
+ 0x00000000, 0x00000000); break;
+ default: SET_ABCD(0x00000000, 0x00000000,
+ 0x00000000, 0x00000000); break;
+ }
+ break;
+ case 0x00000008:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x00000009:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x0000000a:
+ SET_ABCD(0x07300803, 0x00000000, 0x00000000, 0x00000603);
+ break;
+ case 0x0000000b:
+ switch (old_ecx) {
+ case 0x00000000: SET_ABCD(0x00000001, 0x00000002,
+ 0x00000100, 0x00000002); break;
+ case 0x00000001: SET_ABCD(0x00000004, 0x00000008,
+ 0x00000201, 0x00000002); break;
+ default: SET_ABCD(0x00000000, 0x00000000,
+ old_ecx, 0x00000002); break;
+ }
+ break;
+ case 0x0000000c:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x0000000d:
+ switch (old_ecx) {
+ case 0x00000000: SET_ABCD(0x00000007, 0x00000340,
+ 0x00000340, 0x00000000); break;
+ case 0x00000001: SET_ABCD(0x00000000, 0x00000000,
+ 0x00000000, 0x00000000); break;
+ case 0x00000002: SET_ABCD(0x00000100, 0x00000240,
+ 0x00000000, 0x00000000); break;
+ default: SET_ABCD(0x00000000, 0x00000000,
+ 0x00000000, 0x00000000); break;
+ }
+ break;
+ case 0x80000000:
+ SET_ABCD(0x80000008, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x80000001:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000021, 0x2c100800);
+ break;
+ case 0x80000002:
+ SET_ABCD(0x65746e49, 0x2952286c, 0x726f4320, 0x4d542865);
+ break;
+ case 0x80000003:
+ SET_ABCD(0x37692029, 0x3139342d, 0x20514d30, 0x20555043);
+ break;
+ case 0x80000004:
+ SET_ABCD(0x2e322040, 0x48473039, 0x0000007a, 0x00000000);
+ break;
+ case 0x80000005:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ case 0x80000006:
+ SET_ABCD(0x00000000, 0x00000000, 0x01006040, 0x00000000);
+ break;
+ case 0x80000007:
+ SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000100);
+ break;
+ case 0x80000008:
+ SET_ABCD(0x00003027, 0x00000000, 0x00000000, 0x00000000);
+ break;
+ default:
+ SET_ABCD(0x00000007, 0x00000340, 0x00000340, 0x00000000);
+ break;
+ }
+# undef SET_ABCD
+}
+
+
+/*---------------------------------------------------------------*/
+/*--- Misc integer helpers, including rotates and crypto. ---*/
+/*---------------------------------------------------------------*/
+
ULong amd64g_calculate_RCR ( ULong arg,
ULong rot_amt,
ULong rflags_in,
Modified: trunk/priv/guest_amd64_toIR.c
==============================================================================
--- trunk/priv/guest_amd64_toIR.c (original)
+++ trunk/priv/guest_amd64_toIR.c Wed Aug 12 12:15:53 2015
@@ -349,6 +349,13 @@
vpanic("doScalarWidening(amd64)");
}
+static
+void putGuarded ( Int gstOffB, IRExpr* guard, IRExpr* value )
+{
+ IRType ty = typeOfIRExpr(irsb->tyenv, value);
+ stmt( IRStmt_Put(gstOffB,
+ IRExpr_ITE(guard, value, IRExpr_Get(gstOffB, ty))) );
+}
/*------------------------------------------------------------*/
@@ -5195,6 +5202,52 @@
}
+/* Generate a dirty helper call that initialises the x87 state a la
+ FINIT. If |guard| is NULL, it is done unconditionally. Otherwise
+ |guard| is used as a guarding condition.
+*/
+static void gen_FINIT_SEQUENCE ( IRExpr* guard )
+{
+ /* Uses dirty helper:
+ void amd64g_do_FINIT ( VexGuestAMD64State* ) */
+ IRDirty* d = unsafeIRDirty_0_N (
+ 0/*regparms*/,
+ "amd64g_dirtyhelper_FINIT",
+ &amd64g_dirtyhelper_FINIT,
+ mkIRExprVec_1( IRExpr_BBPTR() )
+ );
+
+ /* declare we're writing guest state */
+ d->nFxState = 5;
+ vex_bzero(&d->fxState, sizeof(d->fxState));
+
+ d->fxState[0].fx = Ifx_Write;
+ d->fxState[0].offset = OFFB_FTOP;
+ d->fxState[0].size = sizeof(UInt);
+
+ d->fxState[1].fx = Ifx_Write;
+ d->fxState[1].offset = OFFB_FPREGS;
+ d->fxState[1].size = 8 * sizeof(ULong);
+
+ d->fxState[2].fx = Ifx_Write;
+ d->fxState[2].offset = OFFB_FPTAGS;
+ d->fxState[2].size = 8 * sizeof(UChar);
+
+ d->fxState[3].fx = Ifx_Write;
+ d->fxState[3].offset = OFFB_FPROUND;
+ d->fxState[3].size = sizeof(ULong);
+
+ d->fxState[4].fx = Ifx_Write;
+ d->fxState[4].offset = OFFB_FC3210;
+ d->fxState[4].size = sizeof(ULong);
+
+ if (guard)
+ d->guard = guard;
+
+ stmt( IRStmt_Dirty(d) );
+}
+
+
/* ------------------------------------------------------- */
/* Given all that stack-mangling junk, we can now go ahead
and describe FP instructions.
@@ -6309,41 +6362,7 @@
break;
case 0xE3: {
- /* Uses dirty helper:
- void amd64g_do_FINIT ( VexGuestAMD64State* ) */
- IRDirty* d = unsafeIRDirty_0_N (
- 0/*regparms*/,
- "amd64g_dirtyhelper_FINIT",
- &amd64g_dirtyhelper_FINIT,
- mkIRExprVec_1( IRExpr_BBPTR() )
- );
-
- /* declare we're writing guest state */
- d->nFxState = 5;
- vex_bzero(&d->fxState, sizeof(d->fxState));
-
- d->fxState[0].fx = Ifx_Write;
- d->fxState[0].offset = OFFB_FTOP;
- d->fxState[0].size = sizeof(UInt);
-
- d->fxState[1].fx = Ifx_Write;
- d->fxState[1].offset = OFFB_FPREGS;
- d->fxState[1].size = 8 * sizeof(ULong);
-
- d->fxState[2].fx = Ifx_Write;
- d->fxState[2].offset = OFFB_FPTAGS;
- d->fxState[2].size = 8 * sizeof(UChar);
-
- d->fxState[3].fx = Ifx_Write;
- d->fxState[3].offset = OFFB_FPROUND;
- d->fxState[3].size = sizeof(ULong);
-
- d->fxState[4].fx = Ifx_Write;
- d->fxState[4].offset = OFFB_FC3210;
- d->fxState[4].size = sizeof(ULong);
-
- stmt( IRStmt_Dirty(d) );
-
+ gen_FINIT_SEQUENCE(NULL/*no guarding condition*/);
DIP("fninit\n");
break;
}
@@ -9875,6 +9894,10 @@
gen_SEGV_if_not_XX_aligned(effective_addr, 32-1);
}
+static void gen_SEGV_if_not_64_aligned ( IRTemp effective_addr ) {
+ gen_SEGV_if_not_XX_aligned(effective_addr, 64-1);
+}
+
/* Helper for deciding whether a given insn (starting at the opcode
byte) may validly be used with a LOCK prefix. The following insns
may be used with LOCK when their destination operand is in memory.
@@ -11550,6 +11573,495 @@
}
+static void gen_XSAVE_SEQUENCE ( IRTemp addr, IRTemp rfbm )
+{
+ /* ------ rfbm[0] gates the x87 state ------ */
+
+ /* Uses dirty helper:
+ void amd64g_do_XSAVE_COMPONENT_0 ( VexGuestAMD64State*, ULong )
+ */
+ IRDirty* d0 = unsafeIRDirty_0_N (
+ 0/*regparms*/,
+ "amd64g_dirtyhelper_XSAVE_COMPONENT_0",
+ &amd64g_dirtyhelper_XSAVE_COMPONENT_0,
+ mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ );
+ d0->guard = binop(Iop_CmpEQ64, binop(Iop_And64, mkexpr(rfbm), mkU64(1)),
+ mkU64(1));
+
+ /* Declare we're writing memory. Really, bytes 24 through 31
+ (MXCSR and MXCSR_MASK) aren't written, but we can't express more
+ than 1 memory area here, so just mark the whole thing as
+ written. */
+ d0->mFx = Ifx_Write;
+ d0->mAddr = mkexpr(addr);
+ d0->mSize = 160;
+
+ /* declare we're reading guest state */
+ d0->nFxState = 5;
+ vex_bzero(&d0->fxState, sizeof(d0->fxState));
+
+ d0->fxState[0].fx = Ifx_Read;
+ d0->fxState[0].offset = OFFB_FTOP;
+ d0->fxState[0].size = sizeof(UInt);
+
+ d0->fxState[1].fx = Ifx_Read;
+ d0->fxState[1].offset = OFFB_FPREGS;
+ d0->fxState[1].size = 8 * sizeof(ULong);
+
+ d0->fxState[2].fx = Ifx_Read;
+ d0->fxState[2].offset = OFFB_FPTAGS;
+ d0->fxState[2].size = 8 * sizeof(UChar);
+
+ d0->fxState[3].fx = Ifx_Read;
+ d0->fxState[3].offset = OFFB_FPROUND;
+ d0->fxState[3].size = sizeof(ULong);
+
+ d0->fxState[4].fx = Ifx_Read;
+ d0->fxState[4].offset = OFFB_FC3210;
+ d0->fxState[4].size = sizeof(ULong);
+
+ stmt( IRStmt_Dirty(d0) );
+
+ /* ------ rfbm[1] gates the SSE state ------ */
+
+ IRTemp rfbm_1 = newTemp(Ity_I64);
+ IRTemp rfbm_1or2 = newTemp(Ity_I64);
+ assign(rfbm_1, binop(Iop_And64, mkexpr(rfbm), mkU64(2)));
+ assign(rfbm_1or2, binop(Iop_And64, mkexpr(rfbm), mkU64(6)));
+
+ IRExpr* guard_1 = binop(Iop_CmpEQ64, mkexpr(rfbm_1), mkU64(2));
+ IRExpr* guard_1or2 = binop(Iop_CmpNE64, mkexpr(rfbm_1or2), mkU64(0));
+
+ /* Uses dirty helper:
+ void amd64g_do_XSAVE_COMPONENT_1_EXCLUDING_XMMREGS
+ ( VexGuestAMD64State*, ULong )
+ This creates only MXCSR and MXCSR_MASK. We need to do this if
+ either components 1 (SSE) or 2 (AVX) are requested. Hence the
+ guard condition is a bit more complex.
+ */
+ IRDirty* d1 = unsafeIRDirty_0_N (
+ 0/*regparms*/,
+ "amd64g_dirtyhelper_XSAVE_COMPONENT_1_EXCLUDING_XMMREGS",
+ &amd64g_dirtyhelper_XSAVE_COMPONENT_1_EXCLUDING_XMMREGS,
+ mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ );
+ d1->guard = guard_1or2;
+
+ /* Declare we're writing memory: MXCSR and MXCSR_MASK. Note that
+ the code for rbfm[0] just above claims a write of 0 .. 159, so
+ this duplicates it. But at least correctly connects 24 .. 31 to
+ the MXCSR guest state representation (SSEROUND field). */
+ d1->mFx = Ifx_Write;
+ d1->mAddr = binop(Iop_Add64, mkexpr(addr), mkU64(24));
+ d1->mSize = 8;
+
+ /* declare we're reading guest state */
+ d1->nFxState = 1;
+ vex_bzero(&d1->fxState, sizeof(d1->fxState));
+
+ d1->fxState[0].fx = Ifx_Read;
+ d1->fxState[0].offset = OFFB_SSEROUND;
+ d1->fxState[0].size = sizeof(ULong);
+
+ /* Call the helper. This creates MXCSR and MXCSR_MASK but nothing
+ else. We do the actual register array, XMM[0..15], separately,
+ in order that any undefinedness in the XMM registers is tracked
+ separately by Memcheck and does not "infect" the in-memory
+ shadow for the other parts of the image. */
+ stmt( IRStmt_Dirty(d1) );
+
+ /* And now the XMMs themselves. */
+ UInt reg;
+ for (reg = 0; reg < 16; reg++) {
+ stmt( IRStmt_StoreG(
+ Iend_LE,
+ binop(Iop_Add64, mkexpr(addr), mkU64(160 + reg * 16)),
+ getXMMReg(reg),
+ guard_1
+ ));
+ }
+
+ /* ------ rfbm[2] gates the AVX state ------ */
+ /* Component 2 is just a bunch of register saves, so we'll do it
+ inline, just to be simple and to be Memcheck friendly. */
+
+ IRTemp rfbm_2 = newTemp(Ity_I64);
+ assign(rfbm_2, binop(Iop_And64, mkexpr(rfbm), mkU64(4)));
+
+ IRExpr* guard_2 = binop(Iop_CmpEQ64, mkexpr(rfbm_2), mkU64(4));
+
+ for (reg = 0; reg < 16; reg++) {
+ stmt( IRStmt_StoreG(
+ Iend_LE,
+ binop(Iop_Add64, mkexpr(addr), mkU64(576 + reg * 16)),
+ getYMMRegLane128(reg,1),
+ guard_2
+ ));
+ }
+}
+
+
+static Long dis_XSAVE ( const VexAbiInfo* vbi,
+ Prefix pfx, Long delta, Int sz )
+{
+ /* Note that the presence or absence of REX.W (indicated here by
+ |sz|) slightly affects the written format: whether the saved FPU
+ IP and DP pointers are 64 or 32 bits. But the helper function
+ we call simply writes zero bits in the relevant fields, which
+ are 64 bits regardless of what REX.W is, and so it's good enough
+ (iow, equally broken) in both cases. */
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ vassert(!epartIsReg(modrm)); /* ensured by caller */
+ vassert(sz == 4 || sz == 8); /* ditto */
+
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ gen_SEGV_if_not_64_aligned(addr);
+
+ DIP("%sxsave %s\n", sz==8 ? "rex64/" : "", dis_buf);
+
+ /* VEX's caller is assumed to have checked this. */
+ const ULong aSSUMED_XCR0_VALUE = 7;
+
+ IRTemp rfbm = newTemp(Ity_I64);
+ assign(rfbm,
+ binop(Iop_And64,
+ binop(Iop_Or64,
+ binop(Iop_Shl64,
+ unop(Iop_32Uto64, getIRegRDX(4)), mkU8(32)),
+ unop(Iop_32Uto64, getIRegRAX(4))),
+ mkU64(aSSUMED_XCR0_VALUE)));
+
+ gen_XSAVE_SEQUENCE(addr, rfbm);
+
+ /* Finally, we need to update XSTATE_BV in the XSAVE header area, by
+ OR-ing the RFBM value into it. */
+ IRTemp addr_plus_512 = newTemp(Ity_I64);
+ assign(addr_plus_512, binop(Iop_Add64, mkexpr(addr), mkU64(512)));
+ storeLE( mkexpr(addr_plus_512),
+ binop(Iop_Or8,
+ unop(Iop_64to8, mkexpr(rfbm)),
+ loadLE(Ity_I8, mkexpr(addr_plus_512))) );
+
+ return delta;
+}
+
+
+static Long dis_FXSAVE ( const VexAbiInfo* vbi,
+ Prefix pfx, Long delta, Int sz )
+{
+ /* See comment in dis_XSAVE about the significance of REX.W. */
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ vassert(!epartIsReg(modrm)); /* ensured by caller */
+ vassert(sz == 4 || sz == 8); /* ditto */
+
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ gen_SEGV_if_not_16_aligned(addr);
+
+ DIP("%sfxsave %s\n", sz==8 ? "rex64/" : "", dis_buf);
+
+ /* FXSAVE is just XSAVE with components 0 and 1 selected. Set rfbm
+ to 0b011, generate the XSAVE sequence accordingly, and let iropt
+ fold out the unused (AVX) parts accordingly. */
+ IRTemp rfbm = newTemp(Ity_I64);
+ assign(rfbm, mkU64(3));
+ gen_XSAVE_SEQUENCE(addr, rfbm);
+
+ return delta;
+}
+
+
+static void gen_XRSTOR_SEQUENCE ( IRTemp addr, IRTemp xstate_bv, IRTemp rfbm )
+{
+ /* ------ rfbm[0] gates the x87 state ------ */
+
+ /* If rfbm[0] == 1, we have to write the x87 state. If
+ xstate_bv[0] == 1, we will read it from the memory image, else
+ we'll set it to initial values. Doing this with a helper
+ function and getting the definedness flow annotations correct is
+ too difficult, so generate stupid but simple code: first set the
+ registers to initial values, regardless of xstate_bv[0]. Then,
+ conditionally restore from the memory image. */
+
+ IRTemp rfbm_0 = newTemp(Ity_I64);
+ IRTemp xstate_bv_0 = newTemp(Ity_I64);
+ IRTemp restore_0 = newTemp(Ity_I64);
+ assign(rfbm_0, binop(Iop_And64, mkexpr(rfbm), mkU64(1)));
+ assign(xstate_bv_0, binop(Iop_And64, mkexpr(xstate_bv), mkU64(1)));
+ assign(restore_0, binop(Iop_And64, mkexpr(rfbm_0), mkexpr(xstate_bv_0)));
+
+ gen_FINIT_SEQUENCE( binop(Iop_CmpNE64, mkexpr(rfbm_0), mkU64(0)) );
+
+ /* Uses dirty helper:
+ void amd64g_do_XRSTOR_COMPONENT_0 ( VexGuestAMD64State*, ULong )
+ */
+ IRDirty* d0 = unsafeIRDirty_0_N (
+ 0/*regparms*/,
+ "amd64g_dirtyhelper_XRSTOR_COMPONENT_0",
+ &amd64g_dirtyhelper_XRSTOR_COMPONENT_0,
+ mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ );
+ d0->guard = binop(Iop_CmpNE64, mkexpr(restore_0), mkU64(0));
+
+ /* Declare we're reading memory. Really, bytes 24 through 31
+ (MXCSR and MXCSR_MASK) aren't read, but we can't express more
+ than 1 memory area here, so just mark the whole thing as
+ read. */
+ d0->mFx = Ifx_Read;
+ d0->mAddr = mkexpr(addr);
+ d0->mSize = 160;
+
+ /* declare we're writing guest state */
+ d0->nFxState = 5;
+ vex_bzero(&d0->fxState, sizeof(d0->fxState));
+
+ d0->fxState[0].fx = Ifx_Write;
+ d0->fxState[0].offset = OFFB_FTOP;
+ d0->fxState[0].size = sizeof(UInt);
+
+ d0->fxState[1].fx = Ifx_Write;
+ d0->fxState[1].offset = OFFB_FPREGS;
+ d0->fxState[1].size = 8 * sizeof(ULong);
+
+ d0->fxState[2].fx = Ifx_Write;
+ d0->fxState[2].offset = OFFB_FPTAGS;
+ d0->fxState[2].size = 8 * sizeof(UChar);
+
+ d0->fxState[3].fx = Ifx_Write;
+ d0->fxState[3].offset = OFFB_FPROUND;
+ d0->fxState[3].size = sizeof(ULong);
+
+ d0->fxState[4].fx = Ifx_Write;
+ d0->fxState[4].offset = OFFB_FC3210;
+ d0->fxState[4].size = sizeof(ULong);
+
+ stmt( IRStmt_Dirty(d0) );
+
+ /* ------ rfbm[1] gates the SSE state ------ */
+
+ /* Same scheme as component 0: first zero it out, and then possibly
+ restore from the memory area. */
+ IRTemp rfbm_1 = newTemp(Ity_I64);
+ IRTemp xstate_bv_1 = newTemp(Ity_I64);
+ IRTemp restore_1 = newTemp(Ity_I64);
+ assign(rfbm_1, binop(Iop_And64, mkexpr(rfbm), mkU64(2)));
+ assign(xstate_bv_1, binop(Iop_And64, mkexpr(xstate_bv), mkU64(2)));
+ assign(restore_1, binop(Iop_And64, mkexpr(rfbm_1), mkexpr(xstate_bv_1)));
+ IRExpr* rfbm_1e = binop(Iop_CmpNE64, mkexpr(rfbm_1), mkU64(0));
+ IRExpr* restore_1e = binop(Iop_CmpNE64, mkexpr(restore_1), mkU64(0));
+
+ IRTemp rfbm_1or2 = newTemp(Ity_I64);
+ IRTemp xstate_bv_1or2 = newTemp(Ity_I64);
+ IRTemp restore_1or2 = newTemp(Ity_I64);
+ assign(rfbm_1or2, binop(Iop_And64, mkexpr(rfbm), mkU64(6)));
+ assign(xstate_bv_1or2, binop(Iop_And64, mkexpr(xstate_bv), mkU64(6)));
+ assign(restore_1or2, binop(Iop_And64, mkexpr(rfbm_1or2),
+ mkexpr(xstate_bv_1or2)));
+ IRExpr* rfbm_1or2e = binop(Iop_CmpNE64, mkexpr(rfbm_1or2), mkU64(0));
+ IRExpr* restore_1or2e = binop(Iop_CmpNE64, mkexpr(restore_1or2), mkU64(0));
+
+ /* The areas in question are: SSEROUND, and the XMM register array. */
+ putGuarded(OFFB_SSEROUND, rfbm_1or2e, mkU64(Irrm_NEAREST));
+
+ UInt reg;
+ for (reg = 0; reg < 16; reg++) {
+ putGuarded(xmmGuestRegOffset(reg), rfbm_1e, mkV128(0));
+ }
+
+ /* And now possibly restore from MXCSR/MXCSR_MASK */
+ /* Uses dirty helper:
+ void amd64g_do_XRSTOR_COMPONENT_1_EXCLUDING_XMMREGS
+ ( VexGuestAMD64State*, ULong )
+ This restores from only MXCSR and MXCSR_MASK. We need to do
+ this if either components 1 (SSE) or 2 (AVX) are requested.
+ Hence the guard condition is a bit more complex.
+ */
+ IRDirty* d1 = unsafeIRDirty_0_N (
+ 0/*regparms*/,
+ "amd64g_dirtyhelper_XRSTOR_COMPONENT_1_EXCLUDING_XMMREGS",
+ &amd64g_dirtyhelper_XRSTOR_COMPONENT_1_EXCLUDING_XMMREGS,
+ mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
+ ) ;
+ d1->guard = restore_1or2e;
+
+ /* Declare we're reading memory: MXCSR and MXCSR_MASK. Note that
+ the code for rbfm[0] just above claims a read of 0 .. 159, so
+ this duplicates it. But at least correctly connects 24 .. 31 to
+ the MXCSR guest state representation (SSEROUND field). */
+ d1->mFx = Ifx_Read;
+ d1->mAddr = binop(Iop_Add64, mkexpr(addr), mkU64(24));
+ d1->mSize = 8;
+
+ /* declare we're writing guest state */
+ d1->nFxState = 1;
+ vex_bzero(&d1->fxState, sizeof(d1->fxState));
+
+ d1->fxState[0].fx = Ifx_Write;
+ d1->fxState[0].offset = OFFB_SSEROUND;
+ d1->fxState[0].size = sizeof(ULong);
+
+ /* Call the helper. This creates SSEROUND but nothing
+ else. We do the actual register array, XMM[0..15], separately,
+ in order that any undefinedness in the XMM registers is tracked
+ separately by Memcheck and is not "infected" by the in-memory
+ shadow for the other parts of the image. */
+ stmt( IRStmt_Dirty(d1) );
+
+ /* And now the XMMs themselves. For each register, we PUT either
+ its old value, or the value loaded from memory. One convenient
+ way to do that is with a conditional load that has its the
+ default value, the old value of the register. */
+ for (reg = 0; reg < 16; reg++) {
+ IRExpr* ea = binop(Iop_Add64, mkexpr(addr), mkU64(160 + reg * 16));
+ IRExpr* alt = getXMMReg(reg);
+ IRTemp loadedValue = newTemp(Ity_V128);
+ stmt( IRStmt_LoadG(Iend_LE,
+ ILGop_IdentV128,
+ loadedValue, ea, alt, restore_1e) );
+ putXMMReg(reg, mkexpr(loadedValue));
+ }
+
+ /* ------ rfbm[2] gates the AVX state ------ */
+ /* Component 2 is just a bunch of register loads, so we'll do it
+ inline, just to be simple and to be Memcheck friendly. */
+
+ /* Same scheme as component 0: first zero it out, and then possibly
+ restore from the memory area. */
+ IRTemp rfbm_2 = newTemp(Ity_I64);
+ IRTemp xstate_bv_2 = newTemp(Ity_I64);
+ IRTemp restore_2 = newTemp(Ity_I64);
+ assign(rfbm_2, binop(Iop_And64, mkexpr(rfbm), mkU64(4)));
+ assign(xstate_bv_2, binop(Iop_And64, mkexpr(xstate_bv), mkU64(4)));
+ assign(restore_2, binop(Iop_And64, mkexpr(rfbm_2), mkexpr(xstate_bv_2)));
+
+ IRExpr* rfbm_2e = binop(Iop_CmpNE64, mkexpr(rfbm_2), mkU64(0));
+ IRExpr* restore_2e = binop(Iop_CmpNE64, mkexpr(restore_2), mkU64(0));
+
+ for (reg = 0; reg < 16; reg++) {
+ putGuarded(ymmGuestRegLane128offset(reg, 1), rfbm_2e, mkV128(0));
+ }
+
+ for (reg = 0; reg < 16; reg++) {
+ IRExpr* ea = binop(Iop_Add64, mkexpr(addr), mkU64(576 + reg * 16));
+ IRExpr* alt = getYMMRegLane128(reg, 1);
+ IRTemp loadedValue = newTemp(Ity_V128);
+ stmt( IRStmt_LoadG(Iend_LE,
+ ILGop_IdentV128,
+ loadedValue, ea, alt, restore_2e) );
+ putYMMRegLane128(reg, 1, mkexpr(loadedValue));
+ }
+}
+
+
+static Long dis_XRSTOR ( const VexAbiInfo* vbi,
+ Prefix pfx, Long delta, Int sz )
+{
+ /* As with XRSTOR above we ignore the value of REX.W since we're
+ not bothering with the FPU DP and IP fields. */
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ vassert(!epartIsReg(modrm)); /* ensured by caller */
+ vassert(sz == 4 || sz == 8); /* ditto */
+
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ gen_SEGV_if_not_64_aligned(addr);
+
+ DIP("%sxrstor %s\n", sz==8 ? "rex64/" : "", dis_buf);
+
+ /* VEX's caller is assumed to have checked this. */
+ const ULong aSSUMED_XCR0_VALUE = 7;
+
+ IRTemp rfbm = newTemp(Ity_I64);
+ assign(rfbm,
+ binop(Iop_And64,
+ binop(Iop_Or64,
+ binop(Iop_Shl64,
+ unop(Iop_32Uto64, getIRegRDX(4)), mkU8(32)),
+ unop(Iop_32Uto64, getIRegRAX(4))),
+ mkU64(aSSUMED_XCR0_VALUE)));
+
+ IRTemp xstate_bv = newTemp(Ity_I64);
+ assign(xstate_bv, loadLE(Ity_I64,
+ binop(Iop_Add64, mkexpr(addr), mkU64(512+0))));
+
+ IRTemp xcomp_bv = newTemp(Ity_I64);
+ assign(xcomp_bv, loadLE(Ity_I64,
+ binop(Iop_Add64, mkexpr(addr), mkU64(512+8))));
+
+ IRTemp xsavehdr_23_16 = newTemp(Ity_I64);
+ assign( xsavehdr_23_16,
+ loadLE(Ity_I64,
+ binop(Iop_Add64, mkexpr(addr), mkU64(512+16))));
+
+ /* We must fault if
+ * xcomp_bv[63] == 1, since this simulated CPU does not support
+ the compaction extension.
+ * xstate_bv sets a bit outside of XCR0 (which we assume to be 7).
+ * any of the xsave header bytes 23 .. 8 are nonzero. This seems to
+ imply that xcomp_bv must be zero.
+ xcomp_bv is header bytes 15 .. 8 and xstate_bv is header bytes 7 .. 0
+ */
+ IRTemp fault_if_nonzero = newTemp(Ity_I64);
+ assign(fault_if_nonzero,
+ binop(Iop_Or64,
+ binop(Iop_And64, mkexpr(xstate_bv), mkU64(~aSSUMED_XCR0_VALUE)),
+ binop(Iop_Or64, mkexpr(xcomp_bv), mkexpr(xsavehdr_23_16))));
+ stmt( IRStmt_Exit(binop(Iop_CmpNE64, mkexpr(fault_if_nonzero), mkU64(0)),
+ Ijk_SigSEGV,
+ IRConst_U64(guest_RIP_curr_instr),
+ OFFB_RIP
+ ));
+
+ /* We are guaranteed now that both xstate_bv and rfbm are in the
+ range 0 .. 7. Generate the restore sequence proper. */
+ gen_XRSTOR_SEQUENCE(addr, xstate_bv, rfbm);
+
+ return delta;
+}
+
+
+static Long dis_FXRSTOR ( const VexAbiInfo* vbi,
+ Prefix pfx, Long delta, Int sz )
+{
+ /* As with FXSAVE above we ignore the value of REX.W since we're
+ not bothering with the FPU DP and IP fields. */
+ IRTemp addr = IRTemp_INVALID;
+ Int alen = 0;
+ HChar dis_buf[50];
+ UChar modrm = getUChar(delta);
+ vassert(!epartIsReg(modrm)); /* ensured by caller */
+ vassert(sz == 4 || sz == 8); /* ditto */
+
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
+ gen_SEGV_if_not_16_aligned(addr);
+
+ DIP("%sfxrstor %s\n", sz==8 ? "rex64/" : "", dis_buf);
+
+ /* FXRSTOR is just XRSTOR with components 0 and 1 selected and also
+ as if components 0 and 1 are set as present in XSTATE_BV in the
+ XSAVE header. Set both rfbm and xstate_bv to 0b011 therefore,
+ generate the XRSTOR sequence accordingly, and let iropt fold out
+ the unused (AVX) parts accordingly. */
+ IRTemp three = newTemp(Ity_I64);
+ assign(three, mkU64(3));
+ gen_XRSTOR_SEQUENCE(addr, three/*xstate_bv*/, three/*rfbm*/);
+
+ return delta;
+}
+
+
static IRTemp math_PINSRW_128 ( IRTemp v128, IRTemp u16, UInt imm8 )
{
vassert(imm8 >= 0 && imm8 <= 7);
@@ -11794,6 +12306,7 @@
__attribute__((noinline))
static
Long dis_ESC_0F__SSE2 ( Bool* decode_OK,
+ const VexArchInfo* archinfo,
const VexAbiInfo* vbi,
Prefix pfx, Int sz, Long deltaIN,
DisResult* dres )
@@ -13620,166 +14133,34 @@
delta = dis_LDMXCSR(vbi, pfx, delta, False/*!isAvx*/);
goto decode_success;
}
- /* 0F AE /0 = FXSAVE m512 -- write x87 and SSE state to memory.
- Note that the presence or absence of REX.W slightly affects the
- written format: whether the saved FPU IP and DP pointers are 64
- or 32 bits. But the helper function we call simply writes zero
- bits in the relevant fields (which are 64 bits regardless of
- what REX.W is) and so it's good enough (iow, equally broken) in
- both cases. */
+ /* 0F AE /0 = FXSAVE m512 -- write x87 and SSE state to memory */
if (haveNo66noF2noF3(pfx) && (sz == 4 || sz == 8)
&& !epartIsReg(getUChar(delta))
&& gregOfRexRM(pfx,getUChar(delta)) == 0) {
- IRDirty* d;
- modrm = getUChar(delta);
- vassert(!epartIsReg(modrm));
-
- addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- delta += alen;
- gen_SEGV_if_not_16_aligned(addr);
-
- DIP("%sfxsave %s\n", sz==8 ? "rex64/" : "", dis_buf);
-
- /* Uses dirty helper:
- void amd64g_do_FXSAVE_ALL_EXCEPT_XMM ( VexGuestAMD64State*,
- ULong ) */
- d = unsafeIRDirty_0_N (
- 0/*regparms*/,
- "amd64g_dirtyhelper_FXSAVE_ALL_EXCEPT_XMM",
- &amd64g_dirtyhelper_FXSAVE_ALL_EXCEPT_XMM,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
- );
-
- /* declare we're writing memory */
- d->mFx = Ifx_Write;
- d->mAddr = mkexpr(addr);
- d->mSize = 464; /* according to recent Intel docs */
-
- /* declare we're reading guest state */
- d->nFxState = 6;
- vex_bzero(&d->fxState, sizeof(d->fxState));
-
- d->fxState[0].fx = Ifx_Read;
- d->fxState[0].offset = OFFB_FTOP;
- d->fxState[0].size = sizeof(UInt);
-
- d->fxState[1].fx = Ifx_Read;
- d->fxState[1].offset = OFFB_FPREGS;
- d->fxState[1].size = 8 * sizeof(ULong);
-
- d->fxState[2].fx = Ifx_Read;
- d->fxState[2].offset = OFFB_FPTAGS;
- d->fxState[2].size = 8 * sizeof(UChar);
-
- d->fxState[3].fx = Ifx_Read;
- d->fxState[3].offset = OFFB_FPROUND;
- d->fxState[3].size = sizeof(ULong);
-
- d->fxState[4].fx = Ifx_Read;
- d->fxState[4].offset = OFFB_FC3210;
- d->fxState[4].size = sizeof(ULong);
-
- d->fxState[5].fx = Ifx_Read;
- d->fxState[5].offset = OFFB_SSEROUND;
- d->fxState[5].size = sizeof(ULong);
-
- /* Call the helper. This creates all parts of the in-memory
- image except for the XMM[0..15] array, which we do
- separately, in order that any undefinedness in the XMM
- registers is tracked separately by Memcheck and does not
- "infect" the in-memory shadow for the other parts of the
- image (FPTOP, FPREGS, FPTAGS, FPROUND, FC3210,
- SSEROUND). */
- stmt( IRStmt_Dirty(d) );
-
- /* And now the XMMs themselves. */
- UInt xmm;
- for (xmm = 0; xmm < 16; xmm++) {
- storeLE( binop(Iop_Add64, mkexpr(addr), mkU64(160 + xmm * 16)),
- getXMMReg(xmm) );
- }
-
+ delta = dis_FXSAVE(vbi, pfx, delta, sz);
goto decode_success;
}
- /* 0F AE /1 = FXRSTOR m512 -- read x87 and SSE state from memory.
- As with FXSAVE above we ignore the value of REX.W since we're
- not bothering with the FPU DP and IP fields. */
+ /* 0F AE /1 = FXRSTOR m512 -- read x87 and SSE state from memory */
if (haveNo66noF2noF3(pfx) && (sz == 4 || sz == 8)
&& !epartIsReg(getUChar(delta))
&& gregOfRexRM(pfx,getUChar(delta)) == 1) {
- IRDirty* d;
- modrm = getUChar(delta);
- vassert(!epartIsReg(modrm));
-
- addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- delta += alen;
- gen_SEGV_if_not_16_aligned(addr);
-
- DIP("%sfxrstor %s\n", sz==8 ? "rex64/" : "", dis_buf);
-
- /* Uses dirty helper:
- VexEmNote amd64g_do_FXRSTOR_ALL_EXCEPT_XMM ( VexGuestAMD64State*,
- ULong )
- NOTE:
- the VexEmNote value is simply ignored
- */
- d = unsafeIRDirty_0_N (
- 0/*regparms*/,
- "amd64g_dirtyhelper_FXRSTOR_ALL_EXCEPT_XMM",
- &amd64g_dirtyhelper_FXRSTOR_ALL_EXCEPT_XMM,
- mkIRExprVec_2( IRExpr_BBPTR(), mkexpr(addr) )
- );
-
- /* declare we're reading memory */
- d->mFx = Ifx_Read;
- d->mAddr = mkexpr(addr);
- d->mSize = 464; /* according to recent Intel docs */
-
- /* declare we're writing guest state */
- d->nFxState = 6;
- vex_bzero(&d->fxState, sizeof(d->fxState));
-
- d->fxState[0].fx = Ifx_Write;
- d->fxState[0].offset = OFFB_FTOP;
- d->fxState[0].size = sizeof(UInt);
-
- d->fxState[1].fx = Ifx_Write;
- d->fxState[1].offset = OFFB_FPREGS;
- d->fxState[1].size = 8 * sizeof(ULong);
-
- d->fxState[2].fx = Ifx_Write;
- d->fxState[2].offset = OFFB_FPTAGS;
- d->fxState[2].size = 8 * sizeof(UChar);
-
- d->fxState[3].fx = Ifx_Write;
- d->fxState[3].offset = OFFB_FPROUND;
- d->fxState[3].size = sizeof(ULong);
-
- d->fxState[4].fx = Ifx_Write;
- d->fxState[4].offset = OFFB_FC3210;
- d->fxState[4].size = sizeof(ULong);
-
- d->fxState[5].fx = Ifx_Write;
- d->fxState[5].offset = OFFB_SSEROUND;
- d->fxState[5].size = sizeof(ULong);
-
- /* Call the helper. This reads all parts of the in-memory
- image except for the XMM[0..15] array, which we do
- separately, in order that any undefinedness in the XMM
- registers is tracked separately by Memcheck and does not
- "infect" the in-guest-state shadow for the other parts of the
- image (FPTOP, FPREGS, FPTAGS, FPROUND, FC3210,
- SSEROUND). */
- stmt( IRStmt_Dirty(d) );
-
- /* And now the XMMs themselves. */
- UInt xmm;
- for (xmm = 0; xmm < 16; xmm++) {
- putXMMReg(xmm, loadLE(Ity_V128,
- binop(Iop_Add64, mkexpr(addr),
- mkU64(160 + xmm * 16))));
- }
-
+ delta = dis_FXRSTOR(vbi, pfx, delta, sz);
+ goto decode_success;
+ }
+ /* 0F AE /4 = XSAVE mem -- write x87, SSE, AVX state to memory */
+ if (haveNo66noF2noF3(pfx) && (sz == 4 || sz == 8)
+ && !epartIsReg(getUChar(delta))
+ && gregOfRexRM(pfx,getUChar(delta)) == 4
+ && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) {
+ delta = dis_XSAVE(vbi, pfx, delta, sz);
+ goto decode_success;
+ }
+ /* 0F AE /5 = XRSTOR mem -- read x87, SSE, AVX state from memory */
+ if (haveNo66noF2noF3(pfx) && (sz == 4 || sz == 8)
+ && !epartIsReg(getUChar(delta))
+ && gregOfRexRM(pfx,getUChar(delta)) == 5
+ && (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) {
+ delta = dis_XRSTOR(vbi, pfx, delta, sz);
goto decode_success;
}
break;
@@ -21524,31 +21905,20 @@
const HChar* fName = NULL;
void* fAddr = NULL;
- /* JRS 2014-11-11: this a really horrible temp kludge to work
- around the fact that the Yosemite (OSX 10.10)
- /usr/lib/system/libdyld.dylib expects XSAVE/XRSTOR to be
- implemented, because amd64g_dirtyhelper_CPUID_avx_and_cx16
- claims they are supported, but so far they aren't. So cause
- it to fall back to a simpler CPU. The cleaner approach of
- setting CPUID(eax=1).OSXSAVE=0 and .XSAVE=0 isn't desirable
- since it will (per the official Intel guidelines) lead to
- software concluding that AVX isn't supported.
-
- This is also a kludge in that putting these ifdefs here checks
- the build (host) architecture, when really we're checking the
- guest architecture. */
- Bool this_is_yosemite = False;
-# if defined(VGP_amd64_darwin) && DARWIN_VERS == DARWIN_10_10
- this_is_yosemite = True;
-# endif
-
if (haveF2orF3(pfx)) goto decode_failure;
+
/* This isn't entirely correct, CPUID should depend on the VEX
capabilities, not on the underlying CPU. See bug #324882. */
- if (!this_is_yosemite &&
- (archinfo->hwcaps & VEX_HWCAPS_AMD64_SSE3) &&
+ if ((archinfo->hwcaps & VEX_HWCAPS_AMD64_SSE3) &&
(archinfo->hwcaps & VEX_HWCAPS_AMD64_CX16) &&
- (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) {
+ (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX2)) {
+ fName = "amd64g_dirtyhelper_CPUID_avx2";
+ fAddr = &amd64g_dirtyhelper_CPUID_avx2;
+ /* This is a Core-i7-4910-like machine */
+ }
+ else if ((archinfo->hwcaps & VEX_HWCAPS_AMD64_SSE3) &&
+ (archinfo->hwcaps & VEX_HWCAPS_AMD64_CX16) &&
+ (archinfo->hwcaps & VEX_HWCAPS_AMD64_AVX)) {
fName = "amd64g_dirtyhelper_CPUID_avx_and_cx16";
fAddr = &amd64g_dirtyhelper_CPUID_avx_and_cx16;
/* This is a Core-i5-2300-like machine */
@@ -22050,7 +22420,8 @@
facility in 64 bit mode. */
{
Bool decode_OK = False;
- delta = dis_ESC_0F__SSE2 ( &decode_OK, vbi, pfx, sz, deltaIN, dres );
+ delta = dis_ESC_0F__SSE2 ( &decode_OK,
+ archinfo, vbi, pfx, sz, deltaIN, dres );
if (decode_OK)
return delta;
}
Modified: trunk/priv/host_amd64_defs.c
==============================================================================
--- trunk/priv/host_amd64_defs.c (original)
+++ trunk/priv/host_amd64_defs.c Wed Aug 12 12:15:53 2015
@@ -910,6 +910,28 @@
vassert(sz == 4 || sz == 8 || sz == 16);
return i;
}
+AMD64Instr* AMD64Instr_SseCStore ( AMD64CondCode cond,
+ HReg src, AMD64AMode* addr )
+{
+ AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
+ i->tag = Ain_SseCStore;
+ i->Ain.SseCStore.cond = cond;
+ i->Ain.SseCStore.src = src;
+ i->Ain.SseCStore.addr = addr;
+ vassert(cond != Acc_ALWAYS);
+ return i;
+}
+AMD64Instr* AMD64Instr_SseCLoad ( AMD64CondCode cond,
+ AMD64AMode* addr, HReg dst )
+{
+ AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
+ i->tag = Ain_SseCLoad;
+ i->Ain.SseCLoad.cond = cond;
+ i->Ain.SseCLoad.addr = addr;
+ i->Ain.SseCLoad.dst = dst;
+ vassert(cond != Acc_ALWAYS);
+ return i;
+}
AMD64Instr* AMD64Instr_SseLdzLO ( Int sz, HReg reg, AMD64AMode* addr )
{
AMD64Instr* i = LibVEX_Alloc_inline(sizeof(AMD64Instr));
@@ -1268,6 +1290,24 @@
ppAMD64AMode(i->Ain.SseLdSt.addr);
}
return;
+ case Ain_SseCStore:
+ vex_printf("if (%%rflags.%s) { ",
+ showAMD64CondCode(i->Ain.SseCStore.cond));
+ vex_printf("movups ");
+ ppHRegAMD64(i->Ain.SseCStore.src);
+ vex_printf(", ");
+ ppAMD64AMode(i->Ain.SseCStore.addr);
+ vex_printf(" }");
+ return;
+ case Ain_SseCLoad:
+ vex_printf("if (%%rflags.%s) { ",
+ showAMD64CondCode(i->Ain.SseCLoad.cond));
+ vex_printf("movups ");
+ ppAMD64AMode(i->Ain.SseCLoad.addr);
+ vex_printf(", ");
+ ppHRegAMD64(i->Ain.SseCLoad.dst);
+ vex_printf(" }");
+ return;
case Ain_SseLdzLO:
vex_printf("movs%s ", i->Ain.SseLdzLO.sz==4 ? "s" : "d");
ppAMD64AMode(i->Ain.SseLdzLO.addr);
@@ -1566,6 +1606,14 @@
addHRegUse(u, i->Ain.SseLdSt.isLoad ? HRmWrite : HRmRead,
i->Ain.SseLdSt.reg);
return;
+ case Ain_SseCStore:
+ addRegUsage_AMD64AMode(u, i->Ain.SseCStore.addr);
+ addHRegUse(u, HRmRead, i->Ain.SseCStore.src);
+ return;
+ case Ain_SseCLoad:
+ addRegUsage_AMD64AMode(u, i->Ain.SseCLoad.addr);
+ addHRegUse(u, HRmModify, i->Ain.SseCLoad.dst);
+ return;
case Ain_SseLdzLO:
addRegUsage_AMD64AMode(u, i->Ain.SseLdzLO.addr);
addHRegUse(u, HRmWrite...
[truncated message content] |
|
From: <sv...@va...> - 2015-08-12 11:00:00
|
Author: sewardj
Date: Wed Aug 12 11:59:52 2015
New Revision: 15521
Log:
Remove extraneous "-x" which I suspect is debugging support that got
acidentally left in by r15291.
Modified:
trunk/auxprogs/gsl16test
Modified: trunk/auxprogs/gsl16test
==============================================================================
--- trunk/auxprogs/gsl16test (original)
+++ trunk/auxprogs/gsl16test Wed Aug 12 11:59:52 2015
@@ -1,4 +1,4 @@
-#!/bin/sh -x
+#!/bin/sh
# Do an automated test which involves building and regtesting version
# 1.6 of the GNU Scientific Library (gsl). This has proven to be a
|
|
From: Tom H. <to...@co...> - 2015-08-12 08:56:37
|
On 12/08/15 07:09, Tom Hughes wrote: > On 12/08/15 03:25, Bart Van Assche wrote: > >> Ah, right, your purpose is that the Valgrind macros do not emit any >> client requests on x32. Unless this is very clearly documented that >> might be a confusing outcome for x32 users ... Maybe these users expect >> that if they build a program for x32 and analyze it with Valgrind that >> these macros just work ? > > Well how would they analyse such a program with valgrind? The launcher > would reject an x32 binary on the grounds that it isn't supported... On closer inspection it looks like the laucher won't actually refuse but I don't think it will work either. Basically select_platform will fail, because EI_CLASS will be ELFCLASS32 but e_machine will be EM_X86_64 which is not a combination we recognise. So we will fallback to using amd64-linux as the default platform. But that will of course use a 64 bit address space, so it's unlikely that an x32 binary will get very far. In fact I think once the tool tries to load the ELF readelf() in m_ume/elf.c will just abort because the class will be wrong. Tom -- Tom Hughes (to...@co...) http://compton.nu/ |
|
From: Tom H. <to...@co...> - 2015-08-12 06:11:10
|
On 12/08/15 04:01, Rich Coe wrote: > This looks like it is opensuse specific, but gcc-5 -dumpversion returns > a single digit (5) for gcc 5.1.1. > > $ gcc-5 --version > gcc-5 (SUSE Linux) 5.1.1 20150713 [gcc-5-branch revision 225736] > > $ gcc-5 -dumpversion > 5 Shouldn't you be betting opensuse to fix this? It doesn't do that on Fedora: bericote [~] % gcc -dumpversion 5.1.1 Sounds like it is just a bug in the opensuse build... Tom -- Tom Hughes (to...@co...) http://compton.nu/ |
|
From: Tom H. <to...@co...> - 2015-08-12 06:09:45
|
On 12/08/15 03:25, Bart Van Assche wrote: > Ah, right, your purpose is that the Valgrind macros do not emit any > client requests on x32. Unless this is very clearly documented that > might be a confusing outcome for x32 users ... Maybe these users expect > that if they build a program for x32 and analyze it with Valgrind that > these macros just work ? Well how would they analyse such a program with valgrind? The launcher would reject an x32 binary on the grounds that it isn't supported... Tom -- Tom Hughes (to...@co...) http://compton.nu/ |
|
From: Rich C. <rc...@wi...> - 2015-08-12 03:01:23
|
This looks like it is opensuse specific, but gcc-5 -dumpversion returns
a single digit (5) for gcc 5.1.1.
$ gcc-5 --version
gcc-5 (SUSE Linux) 5.1.1 20150713 [gcc-5-branch revision 225736]
$ gcc-5 -dumpversion
5
This patch adds support for a single digit version for gcc.
I found a reference to this problem here
https://github.com/joyent/node/pull/25671
I've reverted the 'default' gcc to gcc-4.8, as there doesn't seem to be
a way to override the gcc version in the nightly conf file (nor do I think
there should be at the moment).
Rich
diff --git a/configure.ac b/configure.ac
index d5111f7..c24b857 100644
--- a/configure.ac
+++ b/configure.ac
@@ -160,7 +160,7 @@ case "${is_clang}-${gcc_version}" in
icc-1[[3-9]].*)
AC_MSG_RESULT([ok (ICC version ${gcc_version})])
;;
- notclang-[[3-9]].*|notclang-[[1-9][0-9]]*)
+ notclang-[[3-9]].*|notclang-[[1-9][0-9]]*|notclang-[[5-9]])
AC_MSG_RESULT([ok (${gcc_version})])
;;
clang-2.9|clang-[[3-9]].*|clang-[[1-9][0-9]]*)
--
Rich Coe rc...@wi...
|
|
From: Bart V. A. <bva...@ac...> - 2015-08-12 02:25:35
|
On 08/11/15 11:10, Matthias Schwarzott wrote: > Am 11.08.2015 um 04:07 schrieb Bart Van Assche: >> On 08/10/15 11:52, Matthias Schwarzott wrote: >>> Hi! >>> >>> I have seen that valgrind.h will missdetect x32 as amd64. >>> >>> So I wonder if this can cause any bad effects. >>> >>> If so, the header needs to be protected so it does not emit client >>> requests on x32. >>> It could be done like this, because the x32 ABI says that __ILP32__ must >>> be defined (and it is not defined on amd64). >>> See abi.pdf in https://sites.google.com/site/x32abi/documents >>> >>> Regards >>> Matthias >>> >>> >>> --- a/include/valgrind.h >>> +++ b/include/valgrind.h >>> @@ -140,7 +140,7 @@ >>> # define PLAT_amd64_win64 1 >>> #elif defined(__linux__) && defined(__i386__) >>> # define PLAT_x86_linux 1 >>> -#elif defined(__linux__) && defined(__x86_64__) >>> +#elif defined(__linux__) && defined(__x86_64__) && !defined(__ILP32__) >>> # define PLAT_amd64_linux 1 >>> #elif defined(__linux__) && defined(__powerpc__) && >>> !defined(__powerpc64__) >>> # define PLAT_ppc32_linux 1 >> >> Hello Matthias, >> >> Has this patch been tested ? I think if you want the above to work >> correctly that you need to swap the x86 and amd64 detection code. >> >> Bart. >> > Hello Bart, > > yes, I did a compile check with a very simple c file calling > VALGRIND_PRINTF. > Then I compiled this with -m32, -m64 and -mx32. > > With my modified valgrind.h and using -mx32 the VALGRIND_PRINTF did not > leave traces in the executabe. > > Why should it be necessary to swap amd64 and x86 - it worked already > before I touched it and stays like this. > And x32 does not define __i386__. > > But I still don't know if it is necessary to exclude x32 or if it just > does not matter. Ah, right, your purpose is that the Valgrind macros do not emit any client requests on x32. Unless this is very clearly documented that might be a confusing outcome for x32 users ... Maybe these users expect that if they build a program for x32 and analyze it with Valgrind that these macros just work ? Bart. |