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From: <sv...@va...> - 2015-04-07 20:44:03
|
Author: florian Date: Tue Apr 7 21:43:55 2015 New Revision: 15075 Log: Certain kernels on s390 provide extra read permissions on executable segments. See discussion here: https://bugs.kde.org/show_bug.cgi?id=345824#c4 Making sure that rx and x compare equal. Modified: trunk/coregrind/m_aspacemgr/aspacemgr-linux.c Modified: trunk/coregrind/m_aspacemgr/aspacemgr-linux.c ============================================================================== --- trunk/coregrind/m_aspacemgr/aspacemgr-linux.c (original) +++ trunk/coregrind/m_aspacemgr/aspacemgr-linux.c Tue Apr 7 21:43:55 2015 @@ -770,7 +770,7 @@ const HChar* filename ) { Int iLo, iHi, i; - Bool sloppyXcheck; + Bool sloppyXcheck, sloppyRcheck; /* If a problem has already been detected, don't continue comparing segments, so as to avoid flooding the output with error @@ -814,6 +814,14 @@ sloppyXcheck = False; # endif + /* Some kernels on s390 provide 'r' permission even when it was not + explicitly requested. It seems that 'x' permission implies 'r'. */ +# if defined(VGA_s390x) + sloppyRcheck = True; +# else + sloppyRcheck = False; +# endif + /* NSegments iLo .. iHi inclusive should agree with the presented data. */ for (i = iLo; i <= iHi; i++) { @@ -868,6 +876,11 @@ seg_prot |= VKI_PROT_EXEC; } + if (sloppyRcheck && (prot & (VKI_PROT_EXEC | VKI_PROT_READ)) == + (VKI_PROT_EXEC | VKI_PROT_READ)) { + seg_prot |= VKI_PROT_READ; + } + same = same && seg_prot == prot && (cmp_devino |
|
From: Julian S. <js...@ac...> - 2015-04-07 14:44:35
|
Hi Torbjörn, Once again in Valgrind land we are having problems due to lack of nightly test machines for some architectures, especially mips32/64 and arm32/64. In the context of the conversation below, I seem to remember you said something to the effect that you use QEMU to solve this problem for GMP. Do I remember correctly? If so, do you have any information that you can share, regarding configurations of QEMU and Linux distros for these targets? I am wondering if we can set up QEMU VMs for at least some of them, so I am writing to ask if you know which QEMU+distro combinations work well enough to actually be useful. Thanks, J -------- Forwarded Message -------- Subject: Re: [Gcc-cfarm-users] Is there a mips(64)el box? Date: Fri, 10 Oct 2014 11:28:39 +0200 From: Julian Seward <js...@ac...> Reply-To: js...@ac... To: Torbjörn Granlund <tg...@gm...> CC: Sergio Durigan Junior <ser...@re...>, gcc...@gn..., Philippe Waroquiers <phi...@sk...> On 10/10/2014 09:38 AM, Torbjörn Granlund wrote: > The only machines which are actually alive which are useful TO ME are > the two power7 machines. They allowed me to improve the performance of > my code for the chips, and let me do regular testing for ppc64 and AIX. The Power7 machine is also useful for Valgrind support. Without it it would be more difficult to maintain the ppc64 Valgrind port. There are (or were, at one time) a lot of machines in the farm, but most of them were x86 variants, which IMO are the least valuable because that hardware is most widely available. What the farm is really useful for is the more obscure stuff, viz, MIPS, PPC, ARM, which are harder to get hold of. For sure if there were fast, solid MIPS32/64 and AArch32/64 machines, they would be useful for Valgrind testing and development. My impression is that it would be preferable to have fewer machines in the farm, but concentrate on providing at least one reliable, fast implementation of each of MIPS, PPC and ARM (32 and 64 bit in all cases). That is, to try and emphasise quality (breadth and reliability of supported targets) over quantity (numbers of machines). J |
|
From: <sv...@va...> - 2015-04-07 09:36:42
|
Author: sewardj
Date: Tue Apr 7 10:36:35 2015
New Revision: 3122
Log:
x86 front and back ends: track vex r3120, which changed the type of
Iop_Sqrt64Fx2 and Iop_Sqrt32Fx4.
Modified:
trunk/priv/guest_x86_toIR.c
trunk/priv/host_x86_isel.c
Modified: trunk/priv/guest_x86_toIR.c
==============================================================================
--- trunk/priv/guest_x86_toIR.c (original)
+++ trunk/priv/guest_x86_toIR.c Tue Apr 7 10:36:35 2015
@@ -7134,17 +7134,26 @@
Int alen;
IRTemp addr;
UChar rm = getIByte(delta);
+ // Sqrt32Fx4 and Sqrt64Fx2 take a rounding mode, which is faked
+ // up in the usual way.
+ Bool needsIRRM = op == Iop_Sqrt32Fx4 || op == Iop_Sqrt64Fx2;
if (epartIsReg(rm)) {
- putXMMReg( gregOfRM(rm),
- unop(op, getXMMReg(eregOfRM(rm))) );
+ IRExpr* src = getXMMReg(eregOfRM(rm));
+ /* XXXROUNDINGFIXME */
+ IRExpr* res = needsIRRM ? binop(op, get_FAKE_roundingmode(), src)
+ : unop(op, src);
+ putXMMReg( gregOfRM(rm), res );
DIP("%s %s,%s\n", opname,
nameXMMReg(eregOfRM(rm)),
nameXMMReg(gregOfRM(rm)) );
return delta+1;
} else {
addr = disAMode ( &alen, sorb, delta, dis_buf );
- putXMMReg( gregOfRM(rm),
- unop(op, loadLE(Ity_V128, mkexpr(addr))) );
+ IRExpr* src = loadLE(Ity_V128, mkexpr(addr));
+ /* XXXROUNDINGFIXME */
+ IRExpr* res = needsIRRM ? binop(op, get_FAKE_roundingmode(), src)
+ : unop(op, src);
+ putXMMReg( gregOfRM(rm), res );
DIP("%s %s,%s\n", opname,
dis_buf,
nameXMMReg(gregOfRM(rm)) );
Modified: trunk/priv/host_x86_isel.c
==============================================================================
--- trunk/priv/host_x86_isel.c (original)
+++ trunk/priv/host_x86_isel.c Tue Apr 7 10:36:35 2015
@@ -3415,7 +3415,6 @@
case Iop_RecipEst32Fx4: op = Xsse_RCPF; goto do_32Fx4_unary;
case Iop_RSqrtEst32Fx4: op = Xsse_RSQRTF; goto do_32Fx4_unary;
- case Iop_Sqrt32Fx4: op = Xsse_SQRTF; goto do_32Fx4_unary;
do_32Fx4_unary:
{
HReg arg = iselVecExpr(env, e->Iex.Unop.arg);
@@ -3424,16 +3423,6 @@
return dst;
}
- case Iop_Sqrt64Fx2: op = Xsse_SQRTF; goto do_64Fx2_unary;
- do_64Fx2_unary:
- {
- HReg arg = iselVecExpr(env, e->Iex.Unop.arg);
- HReg dst = newVRegV(env);
- REQUIRE_SSE2;
- addInstr(env, X86Instr_Sse64Fx2(op, arg, dst));
- return dst;
- }
-
case Iop_RecipEst32F0x4: op = Xsse_RCPF; goto do_32F0x4_unary;
case Iop_RSqrtEst32F0x4: op = Xsse_RSQRTF; goto do_32F0x4_unary;
case Iop_Sqrt32F0x4: op = Xsse_SQRTF; goto do_32F0x4_unary;
@@ -3499,6 +3488,21 @@
if (e->tag == Iex_Binop) {
switch (e->Iex.Binop.op) {
+ case Iop_Sqrt64Fx2:
+ REQUIRE_SSE2;
+ /* fallthrough */
+ case Iop_Sqrt32Fx4: {
+ /* :: (rmode, vec) -> vec */
+ HReg arg = iselVecExpr(env, e->Iex.Binop.arg2);
+ HReg dst = newVRegV(env);
+ /* XXXROUNDINGFIXME */
+ /* set roundingmode here */
+ addInstr(env, (e->Iex.Binop.op == Iop_Sqrt64Fx2
+ ? X86Instr_Sse64Fx2 : X86Instr_Sse32Fx4)
+ (Xsse_SQRTF, arg, dst));
+ return dst;
+ }
+
case Iop_SetV128lo32: {
HReg dst = newVRegV(env);
HReg srcV = iselVecExpr(env, e->Iex.Binop.arg1);
|
|
From: <sv...@va...> - 2015-04-07 09:08:54
|
Author: sewardj
Date: Tue Apr 7 10:08:42 2015
New Revision: 15074
Log:
Track vex r3120, that changed the type of Iop_Sqrt64x2 and Iop_Sqrt32x4.
Modified:
trunk/memcheck/mc_translate.c
Modified: trunk/memcheck/mc_translate.c
==============================================================================
--- trunk/memcheck/mc_translate.c (original)
+++ trunk/memcheck/mc_translate.c Tue Apr 7 10:08:42 2015
@@ -2391,6 +2391,35 @@
return t1;
}
+/* --- 64Fx2 unary FP ops, with rounding mode --- */
+
+static
+IRAtom* unary64Fx2_w_rm ( MCEnv* mce, IRAtom* vRM, IRAtom* vatomX )
+{
+ /* Same scheme as binary64Fx2_w_rm. */
+ // "do" the vector arg
+ IRAtom* t1 = unary64Fx2(mce, vatomX);
+ // PCast the RM, and widen it to 128 bits
+ IRAtom* t2 = mkPCastTo(mce, Ity_V128, vRM);
+ // Roll it into the result
+ t1 = mkUifUV128(mce, t1, t2);
+ return t1;
+}
+
+/* --- ... and ... 32Fx4 versions of the same --- */
+
+static
+IRAtom* unary32Fx4_w_rm ( MCEnv* mce, IRAtom* vRM, IRAtom* vatomX )
+{
+ /* Same scheme as unary32Fx4_w_rm. */
+ IRAtom* t1 = unary32Fx4(mce, vatomX);
+ // PCast the RM, and widen it to 128 bits
+ IRAtom* t2 = mkPCastTo(mce, Ity_V128, vRM);
+ // Roll it into the result
+ t1 = mkUifUV128(mce, t1, t2);
+ return t1;
+}
+
/* --- --- Vector saturated narrowing --- --- */
@@ -3175,6 +3204,11 @@
/* V128-bit SIMD */
+ case Iop_Sqrt32Fx4:
+ return unary32Fx4_w_rm(mce, vatom1, vatom2);
+ case Iop_Sqrt64Fx2:
+ return unary64Fx2_w_rm(mce, vatom1, vatom2);
+
case Iop_ShrN8x16:
case Iop_ShrN16x8:
case Iop_ShrN32x4:
@@ -4251,7 +4285,6 @@
tl_assert(isOriginalAtom(mce,atom));
switch (op) {
- case Iop_Sqrt64Fx2:
case Iop_Abs64Fx2:
case Iop_Neg64Fx2:
case Iop_RSqrtEst64Fx2:
@@ -4269,7 +4302,6 @@
case Iop_Sqrt64Fx4:
return unary64Fx4(mce, vatom);
- case Iop_Sqrt32Fx4:
case Iop_RecipEst32Fx4:
case Iop_I32UtoFx4:
case Iop_I32StoFx4:
|
|
From: <sv...@va...> - 2015-04-07 09:08:04
|
Author: sewardj
Date: Tue Apr 7 10:07:51 2015
New Revision: 3121
Log:
amd64 front and back ends: track the change of type of Iop_Sqrt32Fx4
and Iop_Sqrt64Fx2 as introduced in r3120, in which they acquired a
rounding-mode argument.
Modified:
trunk/priv/guest_amd64_toIR.c
trunk/priv/host_amd64_isel.c
Modified: trunk/priv/guest_amd64_toIR.c
==============================================================================
--- trunk/priv/guest_amd64_toIR.c (original)
+++ trunk/priv/guest_amd64_toIR.c Tue Apr 7 10:07:51 2015
@@ -8850,17 +8850,26 @@
Int alen;
IRTemp addr;
UChar rm = getUChar(delta);
+ // Sqrt32Fx4 and Sqrt64Fx2 take a rounding mode, which is faked
+ // up in the usual way.
+ Bool needsIRRM = op == Iop_Sqrt32Fx4 || op == Iop_Sqrt64Fx2;
if (epartIsReg(rm)) {
- putXMMReg( gregOfRexRM(pfx,rm),
- unop(op, getXMMReg(eregOfRexRM(pfx,rm))) );
+ IRExpr* src = getXMMReg(eregOfRexRM(pfx,rm));
+ /* XXXROUNDINGFIXME */
+ IRExpr* res = needsIRRM ? binop(op, get_FAKE_roundingmode(), src)
+ : unop(op, src);
+ putXMMReg( gregOfRexRM(pfx,rm), res );
DIP("%s %s,%s\n", opname,
nameXMMReg(eregOfRexRM(pfx,rm)),
nameXMMReg(gregOfRexRM(pfx,rm)) );
return delta+1;
} else {
addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- putXMMReg( gregOfRexRM(pfx,rm),
- unop(op, loadLE(Ity_V128, mkexpr(addr))) );
+ IRExpr* src = loadLE(Ity_V128, mkexpr(addr));
+ /* XXXROUNDINGFIXME */
+ IRExpr* res = needsIRRM ? binop(op, get_FAKE_roundingmode(), src)
+ : unop(op, src);
+ putXMMReg( gregOfRexRM(pfx,rm), res );
DIP("%s %s,%s\n", opname,
dis_buf,
nameXMMReg(gregOfRexRM(pfx,rm)) );
@@ -23046,7 +23055,13 @@
delta += alen;
DIP("%s %s,%s\n", opname, dis_buf, nameXMMReg(rG));
}
- putYMMRegLoAndZU( rG, unop(op, mkexpr(arg)) );
+ // Sqrt32Fx4 and Sqrt64Fx2 take a rounding mode, which is faked
+ // up in the usual way.
+ Bool needsIRRM = op == Iop_Sqrt32Fx4 || op == Iop_Sqrt64Fx2;
+ /* XXXROUNDINGFIXME */
+ IRExpr* res = needsIRRM ? binop(op, get_FAKE_roundingmode(), mkexpr(arg))
+ : unop(op, mkexpr(arg));
+ putYMMRegLoAndZU( rG, res );
*uses_vvvv = False;
return delta;
}
Modified: trunk/priv/host_amd64_isel.c
==============================================================================
--- trunk/priv/host_amd64_isel.c (original)
+++ trunk/priv/host_amd64_isel.c Tue Apr 7 10:07:51 2015
@@ -3227,7 +3227,6 @@
case Iop_RecipEst32Fx4: op = Asse_RCPF; goto do_32Fx4_unary;
case Iop_RSqrtEst32Fx4: op = Asse_RSQRTF; goto do_32Fx4_unary;
- case Iop_Sqrt32Fx4: op = Asse_SQRTF; goto do_32Fx4_unary;
do_32Fx4_unary:
{
HReg arg = iselVecExpr(env, e->Iex.Unop.arg);
@@ -3236,15 +3235,6 @@
return dst;
}
- case Iop_Sqrt64Fx2: op = Asse_SQRTF; goto do_64Fx2_unary;
- do_64Fx2_unary:
- {
- HReg arg = iselVecExpr(env, e->Iex.Unop.arg);
- HReg dst = newVRegV(env);
- addInstr(env, AMD64Instr_Sse64Fx2(op, arg, dst));
- return dst;
- }
-
case Iop_RecipEst32F0x4: op = Asse_RCPF; goto do_32F0x4_unary;
case Iop_RSqrtEst32F0x4: op = Asse_RSQRTF; goto do_32F0x4_unary;
case Iop_Sqrt32F0x4: op = Asse_SQRTF; goto do_32F0x4_unary;
@@ -3313,6 +3303,19 @@
if (e->tag == Iex_Binop) {
switch (e->Iex.Binop.op) {
+ case Iop_Sqrt64Fx2:
+ case Iop_Sqrt32Fx4: {
+ /* :: (rmode, vec) -> vec */
+ HReg arg = iselVecExpr(env, e->Iex.Binop.arg2);
+ HReg dst = newVRegV(env);
+ /* XXXROUNDINGFIXME */
+ /* set roundingmode here */
+ addInstr(env, (e->Iex.Binop.op == Iop_Sqrt64Fx2
+ ? AMD64Instr_Sse64Fx2 : AMD64Instr_Sse32Fx4)
+ (Asse_SQRTF, arg, dst));
+ return dst;
+ }
+
/* FIXME: could we generate MOVQ here? */
case Iop_SetV128lo64: {
HReg dst = newVRegV(env);
|