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From: <sv...@va...> - 2015-04-17 23:43:43
|
Author: carll
Date: Sat Apr 18 00:43:36 2015
New Revision: 15106
Log:
Add support for the lbarx, lharx, stbcx and sthcs instructions.
The instructions are part of the ISA 2.06 but were not implemented
in all versions of hardware. The four instructions are all supported
in ISA 2.07. The instructions were put under the ISA 2.07 category
of supported instructions in this patch.
The VEX commit for this fix is r3137.
The bugzilla for this issue is 346324.
Modified:
trunk/memcheck/tests/ppc32/Makefile.am
trunk/memcheck/tests/ppc64/Makefile.am
trunk/none/tests/ppc32/Makefile.am
trunk/none/tests/ppc32/jm_int_isa_2_07.stdout.exp
trunk/none/tests/ppc64/Makefile.am
trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp
trunk/none/tests/ppc64/test_isa_2_07_part1.c
Modified: trunk/memcheck/tests/ppc32/Makefile.am
==============================================================================
--- trunk/memcheck/tests/ppc32/Makefile.am (original)
+++ trunk/memcheck/tests/ppc32/Makefile.am Sat Apr 18 00:43:36 2015
@@ -5,10 +5,23 @@
EXTRA_DIST = $(noinst_SCRIPTS) \
power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest \
- power_ISA2_05.stdout.exp_Without_FPPO
+ power_ISA2_05.stdout.exp_Without_FPPO \
+ power_ISA2_07.stdout.exp power_ISA2_07.stdout.exp-LE \
+ power_ISA2_07.stderr.exp power_ISA2_07.vgtest
check_PROGRAMS = \
- power_ISA2_05
+ power_ISA2_05 power_ISA2_07
power_ISA2_05_CFLAGS = $(AM_CFLAGS) $(WERROR) -Winline -Wall -Wshadow -g \
-I$(top_srcdir)/include @FLAG_M32@
+
+if HAS_ISA_2_07
+ BUILD_FLAGS_ISA_2_07 = -mhtm -mcpu=power8
+ ISA_2_07_FLAG = -DHAS_ISA_2_07
+else
+ BUILD_FLAGS_ISA_2_07 =
+ ISA_2_07_FLAG =
+endif
+
+power_ISA2_07_CFLAGS = $(AM_CFLAGS) $(WERROR) -Winline -Wall -Wshadow -g \
+ $(ISA_2_07_FLAG) -I$(top_srcdir)/include @FLAG_M32@
Modified: trunk/memcheck/tests/ppc64/Makefile.am
==============================================================================
--- trunk/memcheck/tests/ppc64/Makefile.am (original)
+++ trunk/memcheck/tests/ppc64/Makefile.am Sat Apr 18 00:43:36 2015
@@ -5,10 +5,24 @@
EXTRA_DIST = $(noinst_SCRIPTS) \
power_ISA2_05.stderr.exp power_ISA2_05.stdout.exp power_ISA2_05.vgtest \
- power_ISA2_05.stdout.exp_Without_FPPO
+ power_ISA2_05.stdout.exp_Without_FPPO \
+ power_ISA2_07.stdout.exp power_ISA2_07.stdout.exp-LE \
+ power_ISA2_07.stderr.exp power_ISA2_07.vgtest
+
check_PROGRAMS = \
- power_ISA2_05
+ power_ISA2_05 power_ISA2_07
power_ISA2_05_CFLAGS = $(AM_CFLAGS) $(WERROR) -Winline -Wall -Wshadow -g \
-I$(top_srcdir)/include @FLAG_M64@
+
+if HAS_ISA_2_07
+ BUILD_FLAGS_ISA_2_07 = -mhtm -mcpu=power8
+ ISA_2_07_FLAG = -DHAS_ISA_2_07
+else
+ BUILD_FLAGS_ISA_2_07 =
+ ISA_2_07_FLAG =
+endif
+
+power_ISA2_07_CFLAGS = $(AM_CFLAGS) $(WERROR) -Winline -Wall -Wshadow -g \
+ $(ISA_2_07_FLAG) -I$(top_srcdir)/include @FLAG_M64@
Modified: trunk/none/tests/ppc32/Makefile.am
==============================================================================
--- trunk/none/tests/ppc32/Makefile.am (original)
+++ trunk/none/tests/ppc32/Makefile.am Sat Apr 18 00:43:36 2015
@@ -40,7 +40,8 @@
test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest \
jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.vgtest \
jm_fp_isa_2_07.stderr.exp jm_fp_isa_2_07.stdout.exp jm_fp_isa_2_07.vgtest \
- jm_int_isa_2_07.stderr.exp jm_int_isa_2_07.stdout.exp jm_int_isa_2_07.vgtest \
+ jm_int_isa_2_07.stdout.exp jm_int_isa_2_07.stdout.exp-LE \
+ jm_int_isa_2_07.stderr.exp jm_int_isa_2_07.vgtest \
test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest \
test_tm.stderr.exp test_tm.stdout.exp test_tm.vgtest \
test_touch_tm.stderr.exp test_touch_tm.stdout.exp test_touch_tm.vgtest \
Modified: trunk/none/tests/ppc32/jm_int_isa_2_07.stdout.exp
==============================================================================
--- trunk/none/tests/ppc32/jm_int_isa_2_07.stdout.exp (original)
+++ trunk/none/tests/ppc32/jm_int_isa_2_07.stdout.exp Sat Apr 18 00:43:36 2015
@@ -2,8 +2,16 @@
lq (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 11335577,23456789)
+lbarx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0x000000aa, 0x00000000)
+
+lharx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0x0000aacc, 0x00000000)
+
lqarx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0x11335577, 0x23456789)
+stbcx. 45236789,44226688, => 8900000000000000,0000000000000001; CR=20000000
+
+sthcx. 45236789,44226688, => 6789000000000000,0000000000000001; CR=20000000
+
stqcx. 45236789,44226688, => 0000000045236789,0000000044226688; CR=20000000
-All done. Tested 4 different instructions
+All done. Tested 8 different instructions
Modified: trunk/none/tests/ppc64/Makefile.am
==============================================================================
--- trunk/none/tests/ppc64/Makefile.am (original)
+++ trunk/none/tests/ppc64/Makefile.am Sat Apr 18 00:43:36 2015
@@ -28,7 +28,8 @@
test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest \
jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.vgtest \
jm_fp_isa_2_07.stderr.exp jm_fp_isa_2_07.stdout.exp jm_fp_isa_2_07.vgtest \
- jm_int_isa_2_07.stderr.exp jm_int_isa_2_07.stdout.exp jm_int_isa_2_07.vgtest \
+ jm_int_isa_2_07.stderr.exp jm_int_isa_2_07.vgtest \
+ jm_int_isa_2_07.stdout.exp jm_int_isa_2_07.stdout.exp-LE \
test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest \
test_tm.stderr.exp test_tm.stdout.exp test_tm.vgtest \
test_touch_tm.stderr.exp test_touch_tm.stdout.exp test_touch_tm.vgtest \
Modified: trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp
==============================================================================
--- trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp (original)
+++ trunk/none/tests/ppc64/jm_int_isa_2_07.stdout.exp Sat Apr 18 00:43:36 2015
@@ -2,8 +2,16 @@
lq (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0xaaccee0011335577, 0xabcdef0123456789)
+lbarx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0x00000000000000aa, 0x0000000000000000)
+
+lharx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0x000000000000aacc, 0x0000000000000000)
+
lqarx (0xaaccee0011335577, 0xabcdef0123456789) => (reg_pair = 0xaaccee0011335577, 0xabcdef0123456789)
+stbcx. abefcd0145236789,1155337744226688 => 8900000000000000,0000000000000001; CR=20000000
+
+sthcx. abefcd0145236789,1155337744226688 => 6789000000000000,0000000000000001; CR=20000000
+
stqcx. abefcd0145236789,1155337744226688 => abefcd0145236789,1155337744226688; CR=20000000
-All done. Tested 4 different instructions
+All done. Tested 8 different instructions
Modified: trunk/none/tests/ppc64/test_isa_2_07_part1.c
==============================================================================
--- trunk/none/tests/ppc64/test_isa_2_07_part1.c (original)
+++ trunk/none/tests/ppc64/test_isa_2_07_part1.c Sat Apr 18 00:43:36 2015
@@ -301,8 +301,31 @@
{ NULL, NULL, },
};
-
+#ifdef HAS_ISA_2_07
Word_t * mem_resv;
+static void test_stbcx(void)
+{
+ /* Have to do the lbarx to the memory address to create the reservation
+ * or the store will not occur.
+ */
+ __asm__ __volatile__ ("lbarx %0, %1, %2" : :"r" (r14), "r" (r16),"r" (r17));
+ r14 = (HWord_t) 0xABEFCD0145236789ULL;
+ r15 = (HWord_t) 0x1155337744226688ULL;
+ __asm__ __volatile__ ("stbcx. %0, %1, %2" : :"r" (r14), "r" (r16),"r" (r17));
+}
+
+static void test_sthcx(void)
+{
+ /* Have to do the lharx to the memory address to create the reservation
+ * or the store will not occur.
+ */
+ __asm__ __volatile__ ("lharx %0, %1, %2" : :"r" (r14), "r" (r16),"r" (r17));
+ r14 = (HWord_t) 0xABEFCD0145236789ULL;
+ r15 = (HWord_t) 0x1155337744226688ULL;
+ __asm__ __volatile__ ("sthcx. %0, %1, %2" : :"r" (r14), "r" (r16),"r" (r17));
+}
+#endif
+
static void test_stqcx(void)
{
/* Have to do the lqarx to the memory address to create the reservation
@@ -315,16 +338,34 @@
}
static test_t tests_stq_ops_three[] = {
+#ifdef HAS_ISA_2_07
+ { &test_stbcx , "stbcx.", },
+ { &test_sthcx , "sthcx.", },
+#endif
{ &test_stqcx , "stqcx.", },
{ NULL, NULL, },
};
+#ifdef HAS_ISA_2_07
+static void test_lbarx(void)
+{
+ __asm__ __volatile__ ("lbarx %0, %1, %2, 0" : :"r" (r14), "r" (r16),"r" (r17));
+}
+static void test_lharx(void)
+{
+ __asm__ __volatile__ ("lharx %0, %1, %2, 0" : :"r" (r14), "r" (r16),"r" (r17));
+}
+#endif
static void test_lqarx(void)
{
__asm__ __volatile__ ("lqarx %0, %1, %2, 0" : :"r" (r14), "r" (r16),"r" (r17));
}
static test_t tests_ldq_ops_three[] = {
+#ifdef HAS_ISA_2_07
+ { &test_lbarx , "lbarx", },
+ { &test_lharx , "lharx", },
+#endif
{ &test_lqarx , "lqarx", },
{ NULL, NULL, },
};
|
|
From: <sv...@va...> - 2015-04-17 23:42:48
|
Author: carll
Date: Sat Apr 18 00:42:40 2015
New Revision: 3137
Log:
Add support for the lbarx, lharx, stbcx and sthcs instructions.
The instructions are part of the ISA 2.06 but were not implemented
in all versions of hardware. The four instructions are all supported
in ISA 2.07. The instructions were put under the ISA 2.07 category
of supported instructions in this patch.
The bugzilla for this issue is 346324.
Modified:
trunk/priv/guest_ppc_toIR.c
trunk/priv/host_ppc_defs.c
trunk/priv/host_ppc_isel.c
Modified: trunk/priv/guest_ppc_toIR.c
==============================================================================
--- trunk/priv/guest_ppc_toIR.c (original)
+++ trunk/priv/guest_ppc_toIR.c Sat Apr 18 00:42:40 2015
@@ -1729,7 +1729,7 @@
restart of the current insn. */
static void gen_SIGBUS_if_misaligned ( IRTemp addr, UChar align )
{
- vassert(align == 4 || align == 8 || align == 16);
+ vassert(align == 2 || align == 4 || align == 8 || align == 16);
if (mode64) {
vassert(typeOfIRTemp(irsb->tyenv, addr) == Ity_I64);
stmt(
@@ -6292,6 +6292,41 @@
break;
}
+ case 0x034: { // lbarx (Load Word and Reserve Indexed)
+ IRTemp res;
+ /* According to the PowerPC ISA version 2.05, b0 (called EH
+ in the documentation) is merely a hint bit to the
+ hardware, I think as to whether or not contention is
+ likely. So we can just ignore it. */
+ DIP("lbarx r%u,r%u,r%u,EH=%u\n", rD_addr, rA_addr, rB_addr, (UInt)b0);
+
+ // and actually do the load
+ res = newTemp(Ity_I8);
+ stmt( stmt_load(res, mkexpr(EA), NULL/*this is a load*/) );
+
+ putIReg( rD_addr, mkWidenFrom8(ty, mkexpr(res), False) );
+ break;
+ }
+
+ case 0x074: { // lharx (Load Word and Reserve Indexed)
+ IRTemp res;
+ /* According to the PowerPC ISA version 2.05, b0 (called EH
+ in the documentation) is merely a hint bit to the
+ hardware, I think as to whether or not contention is
+ likely. So we can just ignore it. */
+ DIP("lharx r%u,r%u,r%u,EH=%u\n", rD_addr, rA_addr, rB_addr, (UInt)b0);
+
+ // trap if misaligned
+ gen_SIGBUS_if_misaligned( EA, 2 );
+
+ // and actually do the load
+ res = newTemp(Ity_I16);
+ stmt( stmt_load(res, mkexpr(EA), NULL/*this is a load*/) );
+
+ putIReg( rD_addr, mkWidenFrom16(ty, mkexpr(res), False) );
+ break;
+ }
+
case 0x096: {
// stwcx. (Store Word Conditional Indexed, PPC32 p532)
// Note this has to handle stwcx. in both 32- and 64-bit modes,
@@ -6326,6 +6361,71 @@
break;
}
+ case 0x2B6: {
+ // stbcx. (Store Byte Conditional Indexed)
+ // Note this has to handle stbcx. in both 32- and 64-bit modes,
+ // so isn't quite as straightforward as it might otherwise be.
+ IRTemp rS = newTemp(Ity_I8);
+ IRTemp resSC;
+ if (b0 != 1) {
+ vex_printf("dis_memsync(ppc)(stbcx.,b0)\n");
+ return False;
+ }
+ DIP("stbcx. r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+
+ // Get the data to be stored, and narrow to 32 bits if necessary
+ assign( rS, mkNarrowTo8(ty, getIReg(rS_addr)) );
+
+ // Do the store, and get success/failure bit into resSC
+ resSC = newTemp(Ity_I1);
+ stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS)) );
+
+ // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure
+ // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success
+ putCR321(0, binop(Iop_Shl8, unop(Iop_1Uto8, mkexpr(resSC)), mkU8(1)));
+ putCR0(0, getXER_SO());
+
+ /* Note:
+ If resaddr != lbarx_resaddr, CR0[EQ] is undefined, and
+ whether rS is stored is dependent on that value. */
+ /* So I guess we can just ignore this case? */
+ break;
+ }
+
+ case 0x2D6: {
+ // sthcx. (Store Word Conditional Indexed, PPC32 p532)
+ // Note this has to handle sthcx. in both 32- and 64-bit modes,
+ // so isn't quite as straightforward as it might otherwise be.
+ IRTemp rS = newTemp(Ity_I16);
+ IRTemp resSC;
+ if (b0 != 1) {
+ vex_printf("dis_memsync(ppc)(stwcx.,b0)\n");
+ return False;
+ }
+ DIP("sthcx. r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+
+ // trap if misaligned
+ gen_SIGBUS_if_misaligned( EA, 2 );
+
+ // Get the data to be stored, and narrow to 16 bits if necessary
+ assign( rS, mkNarrowTo16(ty, getIReg(rS_addr)) );
+
+ // Do the store, and get success/failure bit into resSC
+ resSC = newTemp(Ity_I1);
+ stmt( stmt_load( resSC, mkexpr(EA), mkexpr(rS)) );
+
+ // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure
+ // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success
+ putCR321(0, binop(Iop_Shl8, unop(Iop_1Uto8, mkexpr(resSC)), mkU8(1)));
+ putCR0(0, getXER_SO());
+
+ /* Note:
+ If resaddr != lharx_resaddr, CR0[EQ] is undefined, and
+ whether rS is stored is dependent on that value. */
+ /* So I guess we can just ignore this case? */
+ break;
+ }
+
case 0x256: // sync (Synchronize, PPC32 p543),
// also lwsync (L==1), ptesync (L==2)
/* http://sources.redhat.com/ml/binutils/2000-12/msg00311.html
@@ -19668,6 +19768,12 @@
}
/* Memory Synchronization Instructions */
+ case 0x034: case 0x074: // lbarx, lharx
+ case 0x2B6: case 0x2D6: // stbcx, sthcx
+ if (!allow_isa_2_07) goto decode_noP8;
+ if (dis_memsync( theInstr )) goto decode_success;
+ goto decode_failure;
+
case 0x356: case 0x014: case 0x096: // eieio, lwarx, stwcx.
case 0x256: // sync
if (dis_memsync( theInstr )) goto decode_success;
Modified: trunk/priv/host_ppc_defs.c
==============================================================================
--- trunk/priv/host_ppc_defs.c (original)
+++ trunk/priv/host_ppc_defs.c Sat Apr 18 00:42:40 2015
@@ -861,7 +861,7 @@
i->Pin.LoadL.sz = sz;
i->Pin.LoadL.src = src;
i->Pin.LoadL.dst = dst;
- vassert(sz == 4 || sz == 8);
+ vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8);
if (sz == 8) vassert(mode64);
return i;
}
@@ -882,7 +882,7 @@
i->Pin.StoreC.sz = sz;
i->Pin.StoreC.src = src;
i->Pin.StoreC.dst = dst;
- vassert(sz == 4 || sz == 8);
+ vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8);
if (sz == 8) vassert(mode64);
return i;
}
@@ -1644,12 +1644,15 @@
ppPPCAMode(i->Pin.Load.src);
return;
}
- case Pin_LoadL:
- vex_printf("l%carx ", i->Pin.LoadL.sz==4 ? 'w' : 'd');
+ case Pin_LoadL: {
+ UChar sz = i->Pin.LoadL.sz;
+ HChar c_sz = sz==1 ? 'b' : sz==2 ? 'h' : sz==4 ? 'w' : 'd';
+ vex_printf("l%carx ", c_sz);
ppHRegPPC(i->Pin.LoadL.dst);
vex_printf(",%%r0,");
ppHRegPPC(i->Pin.LoadL.src);
return;
+ }
case Pin_Store: {
UChar sz = i->Pin.Store.sz;
Bool idxd = toBool(i->Pin.Store.dst->tag == Pam_RR);
@@ -1660,12 +1663,15 @@
ppPPCAMode(i->Pin.Store.dst);
return;
}
- case Pin_StoreC:
- vex_printf("st%ccx. ", i->Pin.StoreC.sz==4 ? 'w' : 'd');
+ case Pin_StoreC: {
+ UChar sz = i->Pin.StoreC.sz;
+ HChar c_sz = sz==1 ? 'b' : sz==2 ? 'h' : sz==4 ? 'w' : 'd';
+ vex_printf("st%ccx. ", c_sz);
ppHRegPPC(i->Pin.StoreC.src);
vex_printf(",%%r0,");
ppHRegPPC(i->Pin.StoreC.dst);
return;
+ }
case Pin_Set: {
PPCCondCode cc = i->Pin.Set.cond;
vex_printf("set (%s),", showPPCCondCode(cc));
@@ -4399,6 +4405,16 @@
}
case Pin_LoadL: {
+ if (i->Pin.LoadL.sz == 1) {
+ p = mkFormX(p, 31, iregEnc(i->Pin.LoadL.dst, mode64),
+ 0, iregEnc(i->Pin.LoadL.src, mode64), 52, 0, endness_host);
+ goto done;
+ }
+ if (i->Pin.LoadL.sz == 2) {
+ p = mkFormX(p, 31, iregEnc(i->Pin.LoadL.dst, mode64),
+ 0, iregEnc(i->Pin.LoadL.src, mode64), 116, 0, endness_host);
+ goto done;
+ }
if (i->Pin.LoadL.sz == 4) {
p = mkFormX(p, 31, iregEnc(i->Pin.LoadL.dst, mode64),
0, iregEnc(i->Pin.LoadL.src, mode64), 20, 0, endness_host);
@@ -4495,6 +4511,17 @@
}
case Pin_StoreC: {
+ if (i->Pin.StoreC.sz == 1) {
+ p = mkFormX(p, 31, iregEnc(i->Pin.StoreC.src, mode64),
+ 0, iregEnc(i->Pin.StoreC.dst, mode64), 694, 1, endness_host);
+ goto done;
+ }
+ if (i->Pin.StoreC.sz == 2) {
+ p = mkFormX(p, 31, iregEnc(i->Pin.StoreC.src, mode64),
+ 0, iregEnc(i->Pin.StoreC.dst, mode64), 726, 1, endness_host);
+ goto done;
+ }
+
if (i->Pin.StoreC.sz == 4) {
p = mkFormX(p, 31, iregEnc(i->Pin.StoreC.src, mode64),
0, iregEnc(i->Pin.StoreC.dst, mode64), 150, 1, endness_host);
Modified: trunk/priv/host_ppc_isel.c
==============================================================================
--- trunk/priv/host_ppc_isel.c (original)
+++ trunk/priv/host_ppc_isel.c Sat Apr 18 00:42:40 2015
@@ -5754,6 +5754,14 @@
/* LL */
HReg r_addr = iselWordExpr_R( env, stmt->Ist.LLSC.addr, IEndianess );
HReg r_dst = lookupIRTemp(env, res);
+ if (tyRes == Ity_I8) {
+ addInstr(env, PPCInstr_LoadL( 1, r_dst, r_addr, mode64 ));
+ return;
+ }
+ if (tyRes == Ity_I16) {
+ addInstr(env, PPCInstr_LoadL( 2, r_dst, r_addr, mode64 ));
+ return;
+ }
if (tyRes == Ity_I32) {
addInstr(env, PPCInstr_LoadL( 4, r_dst, r_addr, mode64 ));
return;
@@ -5773,8 +5781,20 @@
IRType tyData = typeOfIRExpr(env->type_env,
stmt->Ist.LLSC.storedata);
vassert(tyRes == Ity_I1);
- if (tyData == Ity_I32 || (tyData == Ity_I64 && mode64)) {
- addInstr(env, PPCInstr_StoreC( tyData==Ity_I32 ? 4 : 8,
+ if (tyData == Ity_I8 || tyData == Ity_I16 || tyData == Ity_I32 ||
+ (tyData == Ity_I64 && mode64)) {
+ int size = 0;
+
+ if (tyData == Ity_I64)
+ size = 8;
+ else if (tyData == Ity_I32)
+ size = 4;
+ else if (tyData == Ity_I16)
+ size = 2;
+ else if (tyData == Ity_I8)
+ size = 1;
+
+ addInstr(env, PPCInstr_StoreC( size,
r_a, r_src, mode64 ));
addInstr(env, PPCInstr_MfCR( r_tmp ));
addInstr(env, PPCInstr_Shft(
|
|
From: <sv...@va...> - 2015-04-17 21:19:53
|
Author: philippe
Date: Fri Apr 17 22:19:43 2015
New Revision: 15105
Log:
Fix statistics about ctxt_rcec :
* the nr of discards was always 0
* the cur nr of values was shown as max
Modified:
trunk/helgrind/libhb_core.c
Modified: trunk/helgrind/libhb_core.c
==============================================================================
--- trunk/helgrind/libhb_core.c (original)
+++ trunk/helgrind/libhb_core.c Fri Apr 17 22:19:43 2015
@@ -4738,6 +4738,7 @@
free_RCEC(p);
p = *pp;
tl_assert(stats__ctxt_tab_curr > 0);
+ stats__ctxt_rcdec_discards++;
stats__ctxt_tab_curr--;
} else {
pp = &p->next;
@@ -6293,9 +6294,10 @@
stats__ctxt_rcdec3 );
VG_(printf)( " libhb: ctxt__rcdec: calls %lu, discards %lu\n",
stats__ctxt_rcdec_calls, stats__ctxt_rcdec_discards);
- VG_(printf)( " libhb: contextTab: %lu slots, %lu max ents\n",
+ VG_(printf)( " libhb: contextTab: %lu slots, %lu cur ents,"
+ " %lu max ents\n",
(UWord)N_RCEC_TAB,
- stats__ctxt_tab_curr );
+ stats__ctxt_tab_curr, stats__ctxt_tab_max );
VG_(printf)( " libhb: contextTab: %lu queries, %lu cmps\n",
stats__ctxt_tab_qs,
stats__ctxt_tab_cmps );
|
|
From: Patrick J. L. <lop...@gm...> - 2015-04-17 15:57:24
|
On Thu, Apr 16, 2015 at 11:31 AM, Carl E. Love <ce...@us...> wrote: > > > There is nothing that can be done at the source code level to eliminate the notice from the compiler. Really? Glancing through the GCC source, it looks like: #pragma GCC diagnostic ignored "-Wpsabi" ...should do the trick. Or just pass "-Wno-psabi" on the command line. (Or am I missing something?) Probably should be conditional on GCC version, of course. - Pat |
|
From: Julian S. <js...@ac...> - 2015-04-17 10:57:16
|
On 17/04/15 12:47, Florian Krohm wrote: > Now, looking at the linux side of things: > > VG_TRACK( new_mem_stack_signal, addr - VG_STACK_REDZONE_SZB, > size + VG_STACK_REDZONE_SZB, tid ); > > With your above argument (which is platform neutral), this does not look > right either. I agree. It might be one of those things which has always been wrong, but which nobody really noticed until now. If you're amenable to it, I'd suggest to use simply |size| in the new merged-up version. If we get it wrong somehow, the worst that can happen is that we'll get flooded with false positive errors in signal handlers and we'll soon know something isn't right. So it's a low-risk change IMO. J |
|
From: Florian K. <fl...@ei...> - 2015-04-17 10:47:47
|
>>> incarnations of that function for Darwin are subtly different.
>>> The difference is:
>>>
>>> x86-darwin:
>>>
>>> VG_TRACK( new_mem_stack_signal,
>>> addr - VG_STACK_REDZONE_SZB, size, tid );
>>>
>>> amd64-darwin:
>>>
>>> VG_TRACK( new_mem_stack_signal, addr - VG_STACK_REDZONE_SZB,
>>> size + VG_STACK_REDZONE_SZB, tid );
>
>
> On the whole I'd guess that the first version is actually correct.
>
> Imagine, on amd64-linux, where the redzone size is 128 (bytes). That is,
> the area up to 128 below %rsp is accessible. If we now want to allocate a
> new block on the stack for delivering signals, with size |size|, the area
> that we want to mark as "new" is new_rsp-128 .. old_rsp-128. So I'd say
> that we don't want to extend the marked area by 128 (as in the second
> version) since that will paint the pre-signal-delivery redzone as
> addressible but uninitialised. And so if, after the signal frame is
> cleared, the thread pulls a value out of the redzone and uses it, it
> will be incorrectly marked as uninitialised.
>
That makes sense to me.
> This is just me guessing on the meaning of |size| here.
|size| is either sizeof(struct sigframe) or sizeof(struct rt_sigframe).
You guess was excellent! :)
Now, looking at the linux side of things:
VG_TRACK( new_mem_stack_signal, addr - VG_STACK_REDZONE_SZB,
size + VG_STACK_REDZONE_SZB, tid );
With your above argument (which is platform neutral), this does not look
right either.
Florian
|
|
From: Julian S. <js...@ac...> - 2015-04-17 10:19:19
|
>> In coregrind/m_sigframe we currently have for the linux platform 9
>> versions of a function called 'extend' which extends the stack segment
>> -- all alike (modulo white space).
>> I'm factoring that out
Excellent.
>> incarnations of that function for Darwin are subtly different.
>> The difference is:
>>
>> x86-darwin:
>>
>> VG_TRACK( new_mem_stack_signal,
>> addr - VG_STACK_REDZONE_SZB, size, tid );
>>
>> amd64-darwin:
>>
>> VG_TRACK( new_mem_stack_signal, addr - VG_STACK_REDZONE_SZB,
>> size + VG_STACK_REDZONE_SZB, tid );
My 2 euro-cents worth: on x86-darwin (and x86-linux), VG_STACK_REDZONE_SZB
is zero, so
VG_TRACK( new_mem_stack_signal,
addr - VG_STACK_REDZONE_SZB,
size, tid );
and
VG_TRACK( new_mem_stack_signal,
addr - VG_STACK_REDZONE_SZB,
size + VG_STACK_REDZONE_SZB, tid );
are equivalent.
On the whole I'd guess that the first version is actually correct.
Imagine, on amd64-linux, where the redzone size is 128 (bytes). That is,
the area up to 128 below %rsp is accessible. If we now want to allocate a
new block on the stack for delivering signals, with size |size|, the area
that we want to mark as "new" is new_rsp-128 .. old_rsp-128. So I'd say
that we don't want to extend the marked area by 128 (as in the second
version) since that will paint the pre-signal-delivery redzone as
addressible but uninitialised. And so if, after the signal frame is
cleared, the thread pulls a value out of the redzone and uses it, it
will be incorrectly marked as uninitialised.
This is just me guessing on the meaning of |size| here.
Commoning up the extend functions is great .. it means there's only one
place we have to prove correct :)
J
|
|
From: Tom H. <to...@co...> - 2015-04-17 09:49:57
|
On 17/04/15 10:32, Florian Krohm wrote: > In coregrind/m_sigframe we currently have for the linux platform 9 > versions of a function called 'extend' which extends the stack segment > -- all alike (modulo white space). > I'm factoring that out and while doing so I noticed that the 2 > incarnations of that function for Darwin are subtly different. > The difference is: > > x86-darwin: > > VG_TRACK( new_mem_stack_signal, > addr - VG_STACK_REDZONE_SZB, size, tid ); > > amd64-darwin: > > VG_TRACK( new_mem_stack_signal, addr - VG_STACK_REDZONE_SZB, > size + VG_STACK_REDZONE_SZB, tid ); > > It used to be that the amd64-darwin version of 'extend' was identical to > the x86-darwin version. In r13320 Bart changed the amd64-darwin version > to what it is today. The rationale is not the strongest one: > Darwin: Make stack growth tracking consistent with other architectures > > I'm curious...... Why was x86-darwin not changed the same way? > Or the other way round: Was r13320 perhaps not the right thing to do? Well if Darwin is like other platforms then amd64 has a redzone and x86 doesn't - maybe that is the reason for the difference? Tom -- Tom Hughes (to...@co...) http://compton.nu/ |
|
From: Florian K. <fl...@ei...> - 2015-04-17 09:32:21
|
In coregrind/m_sigframe we currently have for the linux platform 9
versions of a function called 'extend' which extends the stack segment
-- all alike (modulo white space).
I'm factoring that out and while doing so I noticed that the 2
incarnations of that function for Darwin are subtly different.
The difference is:
x86-darwin:
VG_TRACK( new_mem_stack_signal,
addr - VG_STACK_REDZONE_SZB, size, tid );
amd64-darwin:
VG_TRACK( new_mem_stack_signal, addr - VG_STACK_REDZONE_SZB,
size + VG_STACK_REDZONE_SZB, tid );
It used to be that the amd64-darwin version of 'extend' was identical to
the x86-darwin version. In r13320 Bart changed the amd64-darwin version
to what it is today. The rationale is not the strongest one:
Darwin: Make stack growth tracking consistent with other architectures
I'm curious...... Why was x86-darwin not changed the same way?
Or the other way round: Was r13320 perhaps not the right thing to do?
Florian
|
|
From: Florian K. <fl...@ei...> - 2015-04-17 09:09:34
|
On 16.04.2015 20:31, Carl E. Love wrote: > The warning went into the gcc 4.9 compiler for the PPC64 > platform. There will be an ABI change made in the gcc 5.0 with regards to the alignment of 128-bit > arguments to a function. As I understand it, this will only be an issue for code when linking code > that was compiled with different gcc versions. If some of the code was compiled with a pre gcc 5.0 > compiler and it is linked with functions with 128-bit arguments that were compiled with a gcc 5.0 > or newer compiler,there will be a problem of the arguments not aligning properly. > OK. Thanks for the clarification. > There is nothing that can be done at the source code level to eliminate the notice from the compiler. > Sigh. Florian |
|
From: <sv...@va...> - 2015-04-17 08:56:19
|
Author: florian
Date: Fri Apr 17 09:56:11 2015
New Revision: 15104
Log:
Followup to r15101. Remove pointless cast. The castee already
has that type.
Modified:
trunk/coregrind/m_coredump/coredump-elf.c
Modified: trunk/coregrind/m_coredump/coredump-elf.c
==============================================================================
--- trunk/coregrind/m_coredump/coredump-elf.c (original)
+++ trunk/coregrind/m_coredump/coredump-elf.c Fri Apr 17 09:56:11 2015
@@ -358,8 +358,8 @@
regs->orig_gpr3 = arch->vex.guest_GPR3;
regs->ctr = arch->vex.guest_CTR;
regs->link = arch->vex.guest_LR;
- regs->xer = LibVEX_GuestPPC64_get_XER( (const VexGuestPPC64State*) &(arch->vex) );
- regs->ccr = LibVEX_GuestPPC64_get_CR( (const VexGuestPPC64State*) &(arch->vex) );
+ regs->xer = LibVEX_GuestPPC64_get_XER( &(arch->vex) );
+ regs->ccr = LibVEX_GuestPPC64_get_CR( &(arch->vex) );
/* regs->mq = 0; */
regs->trap = 0;
regs->dar = 0; /* should be fault address? */
|
|
From: Julian S. <js...@ac...> - 2015-04-17 07:35:35
|
> On 17/04/15 06:50, Matthias Schwarzott wrote:
>
>>> + /* NCode [r0] = "LOADV32le_on_32" [a0] s0 {
>>> + hot:
>>> + 0 tst.w a0, #3 high?
>>
>> I guess here it should say "unaligned".
>
> So .. actually .. no.
Hmm ok, I shouldn't write email with so little coffee in the system.
Yes you are right. Should be "unaligned".
J
|
|
From: Julian S. <js...@ac...> - 2015-04-17 07:28:49
|
On 17/04/15 06:50, Matthias Schwarzott wrote:
>> + /* NCode [r0] = "LOADV32le_on_32" [a0] s0 {
>> + hot:
>> + 0 tst.w a0, #3 high?
>
> I guess here it should say "unaligned".
Wow, I didn't think anybody was reading these in so much detail.
So .. actually .. no. On 32 bit targets, the primary_map covers
the entire address space in 64k chunks, so we only need to check the
address for misalignment; it can't be "high". And this is for a
32-bit target -- hence the "_on_32" suffix.
You can see the equivalent test for a 64 bit target is against
0xFFFF FFF0 0000 0003, since if any of the top 28 bits of the
address are set, then it can't be indexed via the primary_map.
J
|
|
From: Matthias S. <zz...@ge...> - 2015-04-17 04:50:16
|
On 14.04.2015 21:23, sv...@va... wrote:
>
> +static NCodeTemplate* mk_tmpl__LOADV32le_on_32 ( NAlloc na )
> +{
> + NInstr** hot = na((11+1) * sizeof(NInstr*));
> + NInstr** cold = na((6+1) * sizeof(NInstr*));
> +
> + NReg rINVALID = mkNRegINVALID();
> +
> + NReg r0 = mkNReg(Nrr_Result, 0);
> + NReg a0 = mkNReg(Nrr_Argument, 0);
> + NReg s0 = mkNReg(Nrr_Scratch, 0);
> +
> + /* NCode [r0] = "LOADV32le_on_32" [a0] s0 {
> + hot:
> + 0 tst.w a0, #3 high?
I guess here it should say "unaligned".
Regards
Matthias
|