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From: <sv...@va...> - 2015-04-15 21:46:05
|
Author: florian
Date: Wed Apr 15 22:45:57 2015
New Revision: 15100
Log:
Fix function call: 1st argument is the thread id.
Modified:
trunk/coregrind/m_sigframe/sigframe-tilegx-linux.c
Modified: trunk/coregrind/m_sigframe/sigframe-tilegx-linux.c
==============================================================================
--- trunk/coregrind/m_sigframe/sigframe-tilegx-linux.c (original)
+++ trunk/coregrind/m_sigframe/sigframe-tilegx-linux.c Wed Apr 15 22:45:57 2015
@@ -76,7 +76,7 @@
ThreadId tid = tst->tid;
NSegment const* stackseg = NULL;
- if (VG_(extend_stack)(addr, addr))
+ if (VG_(extend_stack)(tid, addr))
stackseg = VG_(am_find_nsegment)(addr);
if (stackseg == NULL || !stackseg->hasR || !stackseg->hasW)
|
|
From: <sv...@va...> - 2015-04-15 20:31:00
|
Author: philippe
Date: Wed Apr 15 21:30:52 2015
New Revision: 15099
Log:
Following fix done in tilegx host in vex: r3130, reenable tilegx as host
in libvexmultiarch_test
Modified:
trunk/none/tests/libvex_test.c
Modified: trunk/none/tests/libvex_test.c
==============================================================================
--- trunk/none/tests/libvex_test.c (original)
+++ trunk/none/tests/libvex_test.c Wed Apr 15 21:30:52 2015
@@ -241,14 +241,6 @@
show_vta("skipped (word size differs)", &vta);
continue;
}
- // Special condition for VexArchTILEGX that is not yet ready
- // to run in multiarch as an host for different guest.
- if (va == VexArchTILEGX
- && guest_arch != VexArchTILEGX
- && multiarch != va) {
- show_vta("skipped (TILEGX host and guest != TILEGX)", &vta);
- continue;
- }
if (multiarch > VexArch_INVALID
&& multiarch != va) {
show_vta("skipped (!= specific requested arch)", &vta);
|
|
From: <sv...@va...> - 2015-04-15 18:35:59
|
Author: florian
Date: Wed Apr 15 19:35:52 2015
New Revision: 15098
Log:
Update list of ignored files.
Modified:
trunk/none/tests/ (props changed)
|
|
From: Zhu, Y. <Yan...@vi...> - 2015-04-15 18:12:50
|
Leonard,
I finally got valgrind compiled correctly. And I just run valgrind without attaching to any command in MIPS64 OCTEON target, I got the following error. Looks like some of the shared libraries are missing:
# uname -a
Linux ViaSat 3.10.20-rt14-Cavium-Octeon #1 SMP Wed Apr 15 09:30:37 EDT 2015 mips64 GNU/Linux
# which valgrind
/usr/bin/valgrind
# valgrind
valgrind: failed to start tool 'memcheck' for platform 'mips64-linux': No such file or directory
# strace valgrind
execve("/usr/bin/valgrind", ["valgrind"], [/* 20 vars */]) = 0
brk(0) = 0x100cb0f4
mmap(NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) = 0x77dad000
uname({sys="Linux", node="ViaSat", ...}) = 0
access("/etc/ld.so.preload", R_OK) = -1 ENOENT (No such file or directory)
open("/lib32-fp/tls/octeon3/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat("/lib32-fp/tls/octeon3", 0x7fad6050) = -1 ENOENT (No such file or directory)
open("/lib32-fp/tls/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat("/lib32-fp/tls", 0x7fad6050) = -1 ENOENT (No such file or directory)
open("/lib32-fp/octeon3/libc.so.6", O_RDONLY|O_CLOEXEC) = -1 ENOENT (No such file or directory)
stat("/lib32-fp/octeon3", 0x7fad6050) = -1 ENOENT (No such file or directory)
Attached is my own makefile to build valgrind, maybe something is not right in that make file?
Thanks,
Yanwen
From: Crestez Dan Leonard [mailto:cdl...@gm...]
Sent: Tuesday, April 14, 2015 6:02 PM
To: Zhu, Yanwen; Valgrind Developers
Subject: Re: Valgrind 13854: Cross compiling for Cavium MIPS64, N32 ABI
Hello,
You seem to be building for mips32, this is wrong. Instead of _mips32_ those object files should all contain "_mips64n32_".
You need to make sure your configure target is some form of mips64*, not mips32. What this patch does is add support for the N32 ABI as a secondary arch of mips64. What used to only build valgrind for mips64 will now build a second set of binaries for the N32 ABI. The main valgrind launcher will pick the correct mips64/mips64n32 version of the tool based on flags in the elf header.
You also need to avoid including -mabi inside any explicit CFLAGS. Apparently gcc gets confused by multiple -mabi=* flags instead of just using the last option.
Maybe you show how you are running the configure script? Also make sure you reran autogen.sh after patching and cleaned any stale binaries.
I included the valgrind-developers list because this mail thread should be public in case anyone has similar issues.
Regards,
Leonard
On Wed, Apr 15, 2015 at 12:31 AM, Zhu, Yanwen <Yan...@vi...<mailto:Yan...@vi...>> wrote:
Leonard,
Thanks for your reply, I just fixed some errors during the patch. You’re right, not too bad, just 3 files that I had to manually port the changes.
I am building valgrind for MIPS64 with -mabi=n32 using the OCTEOM cross compiler and I am seeing the following error in the linking phase:
../coregrind/link_tool_exe_linux 0x38000000 /home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/tools/ext/bin/mips64-octeon-linux-gnu-gcc --sysroot=/home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/tools -Os -pipe -Os -mtune=mips64 -mabi=n32 -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 -Wl,-melf32btsmipn32 -march=octeon3 -I/home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/toolchain/linux/include -Wno-long-long -Os -pipe -Os -mtune=mips64 -mabi=n32 -D_LARGEFILE_SOURCE -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64 -Wl,-melf32btsmipn32 -march=octeon3 -fno-stack-protector -mabi=n32 -Wl,-melf32btsmipn32 -march=octeon3 -L/home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/tools/lib -L/home/yzhu/workspace/buildroot/buildroot/output/kg255x.v2_pp_devel/tools/usr/lib -o memcheck-mips32-linux -O2 -g -Wall -Wmissing-prototypes -Wshadow -Wpointer-arith -Wstrict-prototypes -Wmissing-declarations -Wno-format-zero-length -fno-strict-aliasing -fno-builtin -O2 -static -nodefaultlibs -nostartfiles -u __start memcheck_mips32_linux-mc_leakcheck.o memcheck_mips32_linux-mc_malloc_wrappers.o memcheck_mips32_linux-mc_main.o memcheck_mips32_linux-mc_translate.o memcheck_mips32_linux-mc_machine.o memcheck_mips32_linux-mc_errors.o ../coregrind/libcoregrind-mips32-linux.a ../VEX/libvex-mips32-linux.a -lgcc
../coregrind/libcoregrind-mips32-linux.a(libcoregrind_mips32_linux_a-m_main.o): In function `__start':
m_main.c:(.text+0xc): undefined reference to `_gp_disp'
m_main.c:(.text+0x10): undefined reference to `_gp_disp'
collect2: error: ld returned 1 exit status
make[4]: *** [memcheck-mips32-linux] Error 1
I don’t know what’s going on here, any suggestions?
Thanks,
Yanwen
From: Crestez Dan Leonard [mailto:cdl...@gm...<mailto:cdl...@gm...>]
Sent: Tuesday, April 14, 2015 3:08 PM
To: Zhu, Yanwen
Subject: Re: Valgrind 13854: Cross compiling for Cavium MIPS64, N32 ABI
Hello,
The patches are against SVN trunk at around the time the patches were posted (it differs between V1 and V2). Backporting them to 3.10.1 should not be terribly difficult. They won't apply cleanly but I expect the issues to be minor and easily solvable. Since the tilegx port was integrated a few days ago I expect they won't apply cleanly on svn trunk either, at least not until I rebase and post the next version.
You can also try to compile directly from the git repos mentioned in the tracker item. That should "just work".
If you have problems compiling you should mention the actual build errors as well as compiler/target details. Support for N32 should be generic but I'm only actually targeting octeon chips using the cavium gcc-4.7 toolchain.
Regards,
Leonard
On Tue, Apr 14, 2015 at 7:16 PM, <Yan...@vi...<mailto:Yan...@vi...>> wrote:
Hi Leonard,
I'm trying to apply your patches for mips64n32 on valgrind 3.10.1 and there some some errors, I manually fixed the patching errors, however, I have some problem compiling it. Looks to me that your patches were not made based on 3.10.1. What version of valgrind were your patches made from? Do you have patches for 3.10.1?
|
|
From: lin z. <man...@gm...> - 2015-04-15 10:05:50
|
Hi,
Here my current patch to libVEX. And not It can translate most arm
code, exception vfp ones. Please tell me if they are useful.
Comparing to libhoudini, my implementation is not as good when float
point instr met. But other integer part works well.
---
lin zuojian
|
|
From: Florian K. <fl...@ei...> - 2015-04-15 07:40:41
|
On 15.04.2015 05:11, sv...@va... wrote: > > Add Iop_Add8, Iop_Add16 and other 8 or 16 bit ALU Iop > in the host_tilegx_isel.c > > They were removed during the code review. But without > them, the memcheck's vbit-test failed. So, simply add > them back. > The change is OK but the reason is not. You could as well have chosen to set .tilegx = 0 in irops.c for the respective IRops. Which would perhaps have been more natural for your architecture. Florian |
|
From: <sv...@va...> - 2015-04-15 03:26:45
|
Author: zliu
Date: Wed Apr 15 04:26:38 2015
New Revision: 15097
Log:
To address memcheck/tests/leak-segv-jmp test failure for TILEGX
By: Zhi-Gang Liu zh...@gm...
Modified:
trunk/memcheck/tests/leak-segv-jmp.c
Modified: trunk/memcheck/tests/leak-segv-jmp.c
==============================================================================
--- trunk/memcheck/tests/leak-segv-jmp.c (original)
+++ trunk/memcheck/tests/leak-segv-jmp.c Wed Apr 15 04:26:38 2015
@@ -168,13 +168,13 @@
{
UWord out;
__asm__ __volatile__ (
- "move r10, r0\n\t"
- "move r0, r1\n\t"
- "move r1, r2\n\t"
- "move r2, r3\n\t"
- "move r3, r4\n\t"
- "move r4, r5\n\t"
- "move r5, r6\n\t"
+ "move r10, %1\n\t"
+ "move r0, %2\n\t"
+ "move r1, %3\n\t"
+ "move r2, %4\n\t"
+ "move r3, %5\n\t"
+ "move r4, %6\n\t"
+ "move r5, %7\n\t"
"swint1 \n\t"
"move %0, r0\n\t"
: /*out*/ "=r" (out)
|
|
From: <sv...@va...> - 2015-04-15 03:22:24
|
Author: zliu
Date: Wed Apr 15 04:22:17 2015
New Revision: 15096
Log:
Add TILEGX arch. specific syscall #245, __NR_cacheflush
By:Zhi-Gang Liu
Modified:
trunk/coregrind/m_syswrap/syswrap-tilegx-linux.c
trunk/include/vki/vki-scnums-tilegx-linux.h
Modified: trunk/coregrind/m_syswrap/syswrap-tilegx-linux.c
==============================================================================
--- trunk/coregrind/m_syswrap/syswrap-tilegx-linux.c (original)
+++ trunk/coregrind/m_syswrap/syswrap-tilegx-linux.c Wed Apr 15 04:22:17 2015
@@ -474,43 +474,44 @@
aren't visible outside this file, but that requires even more macro
magic. */
-DECL_TEMPLATE(tilegx_linux, sys_clone);
-DECL_TEMPLATE(tilegx_linux, sys_rt_sigreturn);
-DECL_TEMPLATE(tilegx_linux, sys_socket);
-DECL_TEMPLATE(tilegx_linux, sys_setsockopt);
-DECL_TEMPLATE(tilegx_linux, sys_getsockopt);
-DECL_TEMPLATE(tilegx_linux, sys_connect);
-DECL_TEMPLATE(tilegx_linux, sys_accept);
-DECL_TEMPLATE(tilegx_linux, sys_accept4);
-DECL_TEMPLATE(tilegx_linux, sys_sendto);
-DECL_TEMPLATE(tilegx_linux, sys_recvfrom);
-DECL_TEMPLATE(tilegx_linux, sys_sendmsg);
-DECL_TEMPLATE(tilegx_linux, sys_recvmsg);
-DECL_TEMPLATE(tilegx_linux, sys_shutdown);
-DECL_TEMPLATE(tilegx_linux, sys_bind);
-DECL_TEMPLATE(tilegx_linux, sys_listen);
-DECL_TEMPLATE(tilegx_linux, sys_getsockname);
-DECL_TEMPLATE(tilegx_linux, sys_getpeername);
-DECL_TEMPLATE(tilegx_linux, sys_socketpair);
-DECL_TEMPLATE(tilegx_linux, sys_semget);
-DECL_TEMPLATE(tilegx_linux, sys_semop);
-DECL_TEMPLATE(tilegx_linux, sys_semtimedop);
-DECL_TEMPLATE(tilegx_linux, sys_semctl);
-DECL_TEMPLATE(tilegx_linux, sys_msgget);
-DECL_TEMPLATE(tilegx_linux, sys_msgrcv);
-DECL_TEMPLATE(tilegx_linux, sys_msgsnd);
-DECL_TEMPLATE(tilegx_linux, sys_msgctl);
-DECL_TEMPLATE(tilegx_linux, sys_shmget);
-DECL_TEMPLATE(tilegx_linux, wrap_sys_shmat);
-DECL_TEMPLATE(tilegx_linux, sys_shmdt);
-DECL_TEMPLATE(tilegx_linux, sys_shmdt);
-DECL_TEMPLATE(tilegx_linux, sys_shmctl);
-DECL_TEMPLATE(tilegx_linux, sys_arch_prctl);
-DECL_TEMPLATE(tilegx_linux, sys_ptrace);
-DECL_TEMPLATE(tilegx_linux, sys_fadvise64);
-DECL_TEMPLATE(tilegx_linux, sys_mmap);
-DECL_TEMPLATE(tilegx_linux, sys_syscall184);
-DECL_TEMPLATE(tilegx_linux, sys_set_dataplane);
+DECL_TEMPLATE (tilegx_linux, sys_clone);
+DECL_TEMPLATE (tilegx_linux, sys_rt_sigreturn);
+DECL_TEMPLATE (tilegx_linux, sys_socket);
+DECL_TEMPLATE (tilegx_linux, sys_setsockopt);
+DECL_TEMPLATE (tilegx_linux, sys_getsockopt);
+DECL_TEMPLATE (tilegx_linux, sys_connect);
+DECL_TEMPLATE (tilegx_linux, sys_accept);
+DECL_TEMPLATE (tilegx_linux, sys_accept4);
+DECL_TEMPLATE (tilegx_linux, sys_sendto);
+DECL_TEMPLATE (tilegx_linux, sys_recvfrom);
+DECL_TEMPLATE (tilegx_linux, sys_sendmsg);
+DECL_TEMPLATE (tilegx_linux, sys_recvmsg);
+DECL_TEMPLATE (tilegx_linux, sys_shutdown);
+DECL_TEMPLATE (tilegx_linux, sys_bind);
+DECL_TEMPLATE (tilegx_linux, sys_listen);
+DECL_TEMPLATE (tilegx_linux, sys_getsockname);
+DECL_TEMPLATE (tilegx_linux, sys_getpeername);
+DECL_TEMPLATE (tilegx_linux, sys_socketpair);
+DECL_TEMPLATE (tilegx_linux, sys_semget);
+DECL_TEMPLATE (tilegx_linux, sys_semop);
+DECL_TEMPLATE (tilegx_linux, sys_semtimedop);
+DECL_TEMPLATE (tilegx_linux, sys_semctl);
+DECL_TEMPLATE (tilegx_linux, sys_msgget);
+DECL_TEMPLATE (tilegx_linux, sys_msgrcv);
+DECL_TEMPLATE (tilegx_linux, sys_msgsnd);
+DECL_TEMPLATE (tilegx_linux, sys_msgctl);
+DECL_TEMPLATE (tilegx_linux, sys_shmget);
+DECL_TEMPLATE (tilegx_linux, wrap_sys_shmat);
+DECL_TEMPLATE (tilegx_linux, sys_shmdt);
+DECL_TEMPLATE (tilegx_linux, sys_shmdt);
+DECL_TEMPLATE (tilegx_linux, sys_shmctl);
+DECL_TEMPLATE (tilegx_linux, sys_arch_prctl);
+DECL_TEMPLATE (tilegx_linux, sys_ptrace);
+DECL_TEMPLATE (tilegx_linux, sys_fadvise64);
+DECL_TEMPLATE (tilegx_linux, sys_mmap);
+DECL_TEMPLATE (tilegx_linux, sys_syscall184);
+DECL_TEMPLATE (tilegx_linux, sys_cacheflush);
+DECL_TEMPLATE (tilegx_linux, sys_set_dataplane);
PRE(sys_clone)
{
@@ -1106,6 +1107,15 @@
/* ---------------------------------------------------------------
PRE/POST wrappers for TILEGX/Linux-variant specific syscalls
------------------------------------------------------------ */
+PRE(sys_cacheflush)
+{
+ PRINT("cacheflush (%lx, %lx, %lx)", ARG1, ARG2, ARG3);
+ PRE_REG_READ3(long, "cacheflush", unsigned long, addr,
+ int, nbytes, int, cache);
+ VG_ (discard_translations) ((Addr)ARG1, (ULong) ARG2,
+ "PRE(sys_cacheflush)");
+ SET_STATUS_Success(0);
+}
PRE(sys_set_dataplane)
{
@@ -1368,6 +1378,7 @@
PLAXY(__NR_accept4, sys_accept4), // 242
+ PLAX_(__NR_cacheflush, sys_cacheflush), // 245
PLAX_(__NR_set_dataplane, sys_set_dataplane), // 246
GENXY(__NR_wait4, sys_wait4), // 260
Modified: trunk/include/vki/vki-scnums-tilegx-linux.h
==============================================================================
--- trunk/include/vki/vki-scnums-tilegx-linux.h (original)
+++ trunk/include/vki/vki-scnums-tilegx-linux.h Wed Apr 15 04:22:17 2015
@@ -406,7 +406,8 @@
* starting with this value.
*/
#define __NR_arch_specific_syscall 244
-#define __NR_set_dataplane 246
+#define __NR_cacheflush 245
+#define __NR_set_dataplane 246
#define __NR_wait4 260
#define __NR_prlimit64 261
#define __NR_fanotify_init 262
|
|
From: <sv...@va...> - 2015-04-15 03:11:44
|
Author: zliu
Date: Wed Apr 15 04:11:38 2015
New Revision: 3133
Log:
Add Iop_Add8, Iop_Add16 and other 8 or 16 bit ALU Iop
in the host_tilegx_isel.c
They were removed during the code review. But without
them, the memcheck's vbit-test failed. So, simply add
them back.
-This line, and those below, will be ignored--
M host_tilegx_isel.c
Modified:
trunk/priv/host_tilegx_isel.c
Modified: trunk/priv/host_tilegx_isel.c
==============================================================================
--- trunk/priv/host_tilegx_isel.c (original)
+++ trunk/priv/host_tilegx_isel.c Wed Apr 15 04:11:38 2015
@@ -480,26 +480,36 @@
switch (e->Iex.Binop.op) {
+ case Iop_Add8:
+ case Iop_Add16:
case Iop_Add32:
case Iop_Add64:
aluOp = GXalu_ADD;
break;
+ case Iop_Sub8:
+ case Iop_Sub16:
case Iop_Sub32:
case Iop_Sub64:
aluOp = GXalu_SUB;
break;
+ case Iop_And8:
+ case Iop_And16:
case Iop_And32:
case Iop_And64:
aluOp = GXalu_AND;
break;
+ case Iop_Or8:
+ case Iop_Or16:
case Iop_Or32:
case Iop_Or64:
aluOp = GXalu_OR;
break;
+ case Iop_Xor8:
+ case Iop_Xor16:
case Iop_Xor32:
case Iop_Xor64:
aluOp = GXalu_XOR;
|
|
From: <sv...@va...> - 2015-04-15 02:56:28
|
Author: zliu
Date: Wed Apr 15 03:56:20 2015
New Revision: 15095
Log:
Fix the bigcode test failure for TILEGX
By: Zhi-Gang Liu
Modified:
trunk/perf/bigcode.c
Modified: trunk/perf/bigcode.c
==============================================================================
--- trunk/perf/bigcode.c (original)
+++ trunk/perf/bigcode.c Wed Apr 15 03:56:20 2015
@@ -15,10 +15,12 @@
#if defined(__mips__)
#include <asm/cachectl.h>
#include <sys/syscall.h>
+#elif defined(__tilegx__)
+#include <asm/cachectl.h>
#endif
#include "tests/sys_mman.h"
-#define FN_SIZE 996 // Must be big enough to hold the compiled f()
+#define FN_SIZE 1024 // Must be big enough to hold the compiled f()
#define N_LOOPS 20000 // Should be divisible by four
#define RATIO 4 // Ratio of code sizes between the two modes
@@ -71,6 +73,8 @@
#if defined(__mips__)
syscall(__NR_cacheflush, a, FN_SIZE * n_fns, ICACHE);
+#elif defined(__tilegx__)
+ cacheflush(a, FN_SIZE * n_fns, ICACHE);
#endif
for (h = 0; h < n_reps; h += 1) {
|
|
From: <sv...@va...> - 2015-04-15 02:33:16
|
Author: zliu
Date: Wed Apr 15 03:33:09 2015
New Revision: 15094
Log:
Address minor issues in Julian's last review.
For TILEGX only.
By: Zhi-Gang Liu
Modified:
trunk/coregrind/m_debuglog.c
trunk/coregrind/m_libcassert.c
Modified: trunk/coregrind/m_debuglog.c
==============================================================================
--- trunk/coregrind/m_debuglog.c (original)
+++ trunk/coregrind/m_debuglog.c Wed Apr 15 03:33:09 2015
@@ -508,13 +508,15 @@
: "$2" );
return (UInt)(__res);
}
+
#elif defined(VGP_tilegx_linux)
+
static UInt local_sys_write_stderr ( const HChar* buf, Int n )
{
volatile Long block[2];
block[0] = (Long)buf;
block[1] = n;
- ULong __res = 0;
+ Long __res = 0;
__asm__ volatile (
"movei r0, 2 \n\t" /* stderr */
"move r1, %1 \n\t" /* buf */
Modified: trunk/coregrind/m_libcassert.c
==============================================================================
--- trunk/coregrind/m_libcassert.c (original)
+++ trunk/coregrind/m_libcassert.c Wed Apr 15 03:33:09 2015
@@ -227,7 +227,7 @@
}
#elif defined(VGP_tilegx_linux)
# define GET_STARTREGS(srP) \
- { UInt pc, sp, fp, ra; \
+ { ULong pc, sp, fp, ra; \
__asm__ __volatile__( \
"move r8, lr \n" \
"jal 0f \n" \
|
|
From: <sv...@va...> - 2015-04-15 02:16:44
|
Author: zliu
Date: Wed Apr 15 03:16:37 2015
New Revision: 3132
Log:
Removed "extern"
Delete extern in front of function TILEGXInstr *TILEGXInstr_Acas(.)
in host_tilegx_defs.c.
By: Zhi-Gang Liu
Modified:
trunk/priv/host_tilegx_defs.c
Modified: trunk/priv/host_tilegx_defs.c
==============================================================================
--- trunk/priv/host_tilegx_defs.c (original)
+++ trunk/priv/host_tilegx_defs.c Wed Apr 15 03:16:37 2015
@@ -765,8 +765,8 @@
return i;
}
-extern TILEGXInstr *TILEGXInstr_Acas ( TILEGXAcasOp op, HReg old,
- HReg addr, HReg exp, HReg new, UInt sz )
+TILEGXInstr *TILEGXInstr_Acas ( TILEGXAcasOp op, HReg old,
+ HReg addr, HReg exp, HReg new, UInt sz )
{
TILEGXInstr *i = LibVEX_Alloc(sizeof(TILEGXInstr));
i->tag = GXin_Acas;
|
|
From: <sv...@va...> - 2015-04-15 02:05:09
|
Author: zliu
Date: Wed Apr 15 03:05:01 2015
New Revision: 3131
Log:
Removed #if __tilegx__ ... #endif in guest_tilegx_toIR.c
Also eliminated several gcc warning message for this file.
By: Zhi-Gang Liu
zh...@gm...
Modified:
trunk/priv/guest_tilegx_toIR.c
Modified: trunk/priv/guest_tilegx_toIR.c
==============================================================================
--- trunk/priv/guest_tilegx_toIR.c (original)
+++ trunk/priv/guest_tilegx_toIR.c Wed Apr 15 03:05:01 2015
@@ -42,7 +42,6 @@
#include "guest_tilegx_defs.h"
#include "tilegx_disasm.h"
-#if __tilegx__
/*------------------------------------------------------------*/
/*--- Globals ---*/
/*------------------------------------------------------------*/
@@ -237,7 +236,7 @@
((_n == 32) ? \
unop(Iop_32Sto64, _e) : \
((_n == 16) ? \
- (Iop_16Sto64, _e) : \
+ unop(Iop_16Sto64, _e) : \
(binop(Iop_Sar64, binop(Iop_Shl64, _e, mkU8(63 - (_n))), mkU8(63 - (_n))))))
static IRStmt* dis_branch ( IRExpr* guard, ULong imm )
@@ -276,7 +275,7 @@
{
struct tilegx_decoded_instruction
decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
- ULong cins, opcode, rd, ra, rb, imm;
+ ULong cins, opcode = -1, rd, ra, rb, imm = 0;
ULong opd[4];
ULong opd_src_map, opd_dst_map, opd_imm_map;
Int use_dirty_helper;
@@ -286,9 +285,8 @@
ULong rd_wb_reg[6];
/* Tilegx is a VLIW processor, we have to commit register write after read.*/
Int rd_wb_index;
- Int n, nr_insn;
+ Int n = 0, nr_insn;
DisResult dres;
- Int stmts_used;
/* The running delta */
Long delta = delta64;
@@ -311,7 +309,7 @@
dres.jk_StopHere = Ijk_INVALID;
/* Verify the code addr is 8-byte aligned. */
- vassert((((ULong)code) & 7) == 0);
+ vassert((((Addr)code) & 7) == 0);
/* Get the instruction bundle. */
cins = *((ULong *)(Addr) code);
@@ -393,20 +391,17 @@
/* To decode the given instruction bundle. */
nr_insn = parse_insn_tilegx((tilegx_bundle_bits)cins,
- (ULong)code,
+ (ULong)(Addr)code,
decoded);
if (vex_traceflags & VEX_TRACE_FE)
- decode_and_display(&cins, 1, (ULong)code);
+ decode_and_display(&cins, 1, (ULong)(Addr)code);
/* Init. rb_wb_index */
rd_wb_index = 0;
steering_pc = -1ULL;
- // Save the current stmts_used in case we need rollback.
- stmts_used = irsb->stmts_used;
-
for (n = 0; n < nr_insn; n++) {
opcode = decoded[n].opcode->mnemonic;
Int opi;
@@ -1392,13 +1387,17 @@
use_dirty_helper = 1;
break;
case 151: /* "mfspr" */
- if (imm == 0x2780) // Get Cmpexch value
- MARK_REG_WB(rd, getIReg(70));
- else if (imm == 0x2580) // Get EX_CONTEXT_0_0
- MARK_REG_WB(rd, getIReg(576/8));
- else if (imm == 0x2581) // Get EX_CONTEXT_0_1
- MARK_REG_WB(rd, getIReg(584/8));
- else
+ t2 = newTemp(Ity_I64);
+ if (imm == 0x2780) { // Get Cmpexch value
+ assign(t2, getIReg(70));
+ MARK_REG_WB(rd, t2);
+ } else if (imm == 0x2580) { // Get EX_CONTEXT_0_0
+ assign(t2, getIReg(576 / 8));
+ MARK_REG_WB(rd, t2);
+ } else if (imm == 0x2581) { // Get EX_CONTEXT_0_1
+ assign(t2, getIReg(584 / 8));
+ MARK_REG_WB(rd, t2);
+ } else
use_dirty_helper = 1;
break;
case 152: /* "mm" */
@@ -2469,7 +2468,6 @@
return dres;
}
-#endif
/*------------------------------------------------------------*/
/*--- Top-level fn ---*/
@@ -2494,7 +2492,6 @@
{
DisResult dres;
-#if __tilegx__
/* Set globals (see top of this file) */
vassert(guest_arch == VexArchTILEGX);
@@ -2507,9 +2504,7 @@
dres = disInstr_TILEGX_WRK(resteerOkFn, resteerCisOk,
callback_opaque,
delta, archinfo, abiinfo, sigill_diag_IN);
-#else
- dres.whatNext = Dis_StopHere;
-#endif
+
return dres;
}
|
|
From: <sv...@va...> - 2015-04-15 01:15:38
|
Author: zliu
Date: Wed Apr 15 02:15:31 2015
New Revision: 3130
Log:
Fix the evCheck assertion for TileGX
Quote from Philippe's original email.
"When guest = amd64 and host = TILEGX, the
libvexmultiarch_test asserts in TILEGX code:
vex: priv/host_tilegx_defs.c:2361 (emit_TILEGXInstr):
Assertion `evCheckSzB_TILEGX() ==
(UChar*)p - (UChar*)p0' failed."
This patch make sure that evCheck always emits
exact 80 bytes instruction stream.
By: Zhi-Gang Liu
zh...@gm...
Modified:
trunk/priv/host_tilegx_defs.c
Modified: trunk/priv/host_tilegx_defs.c
==============================================================================
--- trunk/priv/host_tilegx_defs.c (original)
+++ trunk/priv/host_tilegx_defs.c Wed Apr 15 02:15:31 2015
@@ -1348,11 +1348,10 @@
static UChar *doAMode_IR ( UChar * p, UInt opc1, UInt rSD, TILEGXAMode * am )
{
- UInt rA; //, idx;
+ UInt rA;
vassert(am->tag == GXam_IR);
rA = iregNo(am->GXam.IR.base);
- //idx = am->GXam.IR.index;
if (opc1 == TILEGX_OPC_ST1 || opc1 == TILEGX_OPC_ST2 ||
opc1 == TILEGX_OPC_ST4 || opc1 == TILEGX_OPC_ST) {
@@ -1381,19 +1380,29 @@
return p;
}
-/* Generate a machine-word sized load or store. Simplified version of
- the GXin_Load and GXin_Store cases below. */
+/* Generate a machine-word sized load or store using exact 2 bundles.
+ Simplified version of the GXin_Load and GXin_Store cases below. */
static UChar* do_load_or_store_machine_word ( UChar* p, Bool isLoad, UInt reg,
TILEGXAMode* am )
{
+ UInt rA = iregNo(am->GXam.IR.base);
+
if (am->tag != GXam_IR)
vpanic(__func__);
- if (isLoad) /* load */
- p = doAMode_IR(p, TILEGX_OPC_LD, reg, am);
- else /* store */
- p = doAMode_IR(p, TILEGX_OPC_ST, reg, am);
-
+ if (isLoad) /* load */ {
+ /* r51 is reserved scratch registers. */
+ p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
+ 51, rA, am->GXam.IR.index));
+ /* load from address in r51 to rSD. */
+ p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_LD, 2, reg, 51));
+ } else /* store */ {
+ /* r51 is reserved scratch registers. */
+ p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ADDLI, 3,
+ 51, rA, am->GXam.IR.index));
+ /* store rSD to address in r51 */
+ p = mkInsnBin(p, mkTileGxInsn(TILEGX_OPC_ST, 2, 51, reg));
+ }
return p;
}
|
|
From: <sv...@va...> - 2015-04-15 00:56:48
|
Author: zliu
Date: Wed Apr 15 01:56:40 2015
New Revision: 15093
Log:
Add 'allexec.c' in "none/tests/tilegx"
The symbolic link 'allexec.c' -> ../allecec.c
By: Zhi-Gang Liu
zh...@gm...
Added:
trunk/none/tests/tilegx/allexec.c (with props)
Added: trunk/none/tests/tilegx/allexec.c
==============================================================================
--- trunk/none/tests/tilegx/allexec.c (added)
+++ trunk/none/tests/tilegx/allexec.c Wed Apr 15 01:56:40 2015
@@ -0,0 +1 @@
+link ../allexec.c
\ No newline at end of file
|
|
From: <sv...@va...> - 2015-04-15 00:48:41
|
Author: zliu
Date: Wed Apr 15 01:48:34 2015
New Revision: 15092
Log:
Remove allecec.c from none/tests/tilegx
Will add a symbolic link for that file next.
Zhi-Gang Liu
Removed:
trunk/none/tests/tilegx/allexec.c
Removed: trunk/none/tests/tilegx/allexec.c
==============================================================================
--- trunk/none/tests/tilegx/allexec.c (original)
+++ trunk/none/tests/tilegx/allexec.c (removed)
@@ -1 +0,0 @@
-link ../allexec.c
\ No newline at end of file
|