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From: Philippe W. <phi...@sk...> - 2015-04-10 23:38:29
|
I see that valgrind-low-tilegx.c references the files tilegx-linux-valgrind.xml and tilegx-linux.xml (see target_xml function) but these files are not present in coregrind/m_gdbserver directory and are not in the GDBSERVER_XML_FILES in coregrind/Makefile.am I guess these files were missing in the patch ? Philippe |
|
From: Rich C. <rc...@wi...> - 2015-04-10 23:16:19
|
On Fri, 10 Apr 2015 10:41:10 -0500 Rich Coe <rc...@wi...> wrote: > On Wed, 8 Apr 2015 08:35:09 -0500 > Rich Coe <rc...@wi...> wrote: > > For mips or ppc, without JeOS, there should be a way to mount a distribution > > dvd of linux and install another platform. I'd have to look into it. > > I worked on creating a mips and a ppc qemu installation. I started with ppc > because I know that platform better. I created a qemu installation for mips from wget http://ftp.de.debian.org/debian/dists/wheezy/main/installer-mipsel/current/images/malta/netboot/vmlinux-3.2.0-4-4kc-malta wget http://ftp.de.debian.org/debian/dists/wheezy/main/installer-mipsel/current/images/malta/netboot/initrd.gz by running: qemu-system-mipsel -m 256 -hda deb-mips.qcow2 -kernel vmlinux-3.2.0-4-4kc-malta -initrd initrd.gz -append "root=/dev/ram console=ttyS0" -nographic I installed: gcc g++ make automake autoconf subversion I built valgrind with the following config parameters: Maximum build arch: mips32 Primary build arch: mips32 Secondary build arch: Build OS: linux Primary build target: MIPS32_LINUX Secondary build target: Platform variant: vanilla Primary -DVGPV string: -DVGPV_mips32_linux_vanilla=1 Default supp files: exp-sgcheck.supp xfree-3.supp xfree-4.supp glibc-2.X-drd.supp glibc-2.34567-NPTL-helgrind.supp glibc-2.X.supp V builds ok. When I try to build the tests, it fails building MIPS32int.c with many errors (with duplicates removed) like /tmp/ccpgn2sW.s:3257: Error: opcode not supported on this processor: mips2 (mips2) `clo $t0,$t1' /tmp/ccpgn2sW.s:3345: Error: opcode not supported on this processor: mips2 (mips2) `clz $t0,$t1' /tmp/ccpgn2sW.s:8311: Error: opcode not supported on this processor: mips2 (mips2) `madd $t0,$t1' I did a bit research on 'clo' (clear ones). It looks like it should be supported. I think I'm missing the correct arch specification to gcc. Rich |
|
From: Philippe W. <phi...@sk...> - 2015-04-10 23:11:39
|
On Sat, 2015-04-11 at 01:02 +0200, Philippe Waroquiers wrote: > Julian, > do you agree that the offB_HOST_* offsets are depending on the host > architecture, and not on the guest architecture ? Moving the offB_HOST_* to the arch_host switch makes guest amd64/host tilegx work ok. It looks to me that this is the good thing to do Note: in any case, moving these initialisations from 'guest switch' to 'host switch' can only change the values when guest != host. Philippe |
|
From: Philippe W. <phi...@sk...> - 2015-04-10 23:01:29
|
On Fri, 2015-04-10 at 22:19 +0000, Zhigang Liu wrote:
> Philippe
>
> I can look this carefully for you tonight.
>
> A quick look: the doAMode_IR( ... ) has an optimized case when the am->GXam.IR.index = 0.
>
> In this condition, the load or store will be mapped as 1 bundle, instead of 2 normally. That could be the reason.
That is a good hint.
When looking in main_main.c:594, we see:
switch (vta->arch_guest) {
and then depending on the guest architecture,
offB_HOST_EvC_COUNTER and offB_HOST_EvC_FAILADDR are initialised.
It sounds somewhat suspicious to initialise offB_HOST_* variables
using the guest architecture.
When we have a guest amd64, the host_EvC_FAILADDR is at offset 0
(while for TILEGX, the offset of FAILADDR is 592.
And so, the TILEGX instruction changes, due to the offset 0 being
handled specially.
We in fact use the guest offsets while we should in fact use
host offset for that.
And so, the initialisations of all offB_HOST_EvC_COUNTER and
offB_HOST_EvC_FAILADDR should in fact rather be done in
the switch at main_main.c:407
switch (vta->arch_host) {
Julian,
do you agree that the offB_HOST_* offsets are depending on the host
architecture, and not on the guest architecture ?
Philippe
|
|
From: John R. <jr...@bi...> - 2015-04-10 22:37:29
|
> Parsing /proc/cpuinfo is a bad idea. That might be true, but please say why you believe it. > Julian again mentioned the correct > method and that is to query the AT_HWCAP and AT_HWCAP2 flags in the AUXV. > > [bergner@makalu ~]$ LD_SHOW_AUXV=1 /bin/true | grep AT_HWCAP > AT_HWCAP: vsx arch_2_06 dfp ic_snoop smt mmu fpu altivec ppc64 ppc32 > AT_HWCAP2: tar isel ebb dscr htm arch_2_07 > > That shows all the instruction categories that are supported in the > cpu you're running on. In my experience, relying on AT_HWCAP* (and especially its decoded representation) is a bad idea. /proc/cpuinfo is *much* better. Here are three current examples: On x86_64: $ LD_SHOW_AUXV=1 /bin/true | grep AT_HWCAP AT_HWCAP: bfebfbf ### meaning ?? $ cat /proc/cpuinfo ### abbreviated :) processor : 3 vendor_id : GenuineIntel cpu family : 6 model : 42 model name : Intel(R) Core(TM) i5-2500K CPU @ 3.30GHz flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm pcid sse4_1 sse4_2 popcnt tsc_deadline_timer aes xsave avx lahf_lm ida arat epb xsaveopt pln pts dtherm tpr_shadow vnmi flexpriority ept vpid On ARM (raspberry pi2): $ LD_SHOW_AUXV=1 /bin/true | grep AT_HWCAP AT_HWCAP: half thumb fastmult vfp edsp neon vfpv3 ### armv6 or armv7 ?? etc. $ cat /proc/cpuinfo ### abbreviated :) model name : ARMv7 Processor rev 5 (v7l) Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x0 CPU part : 0xc07 CPU revision : 5 On MIPS (ASUS RT-N16): $ LD_SHOW_AUXV=1 /bin/true | grep AT_HWCAP ### empty output from grep: no AT_HWCAP at all $ cat /proc/cpuinfo ### abbreviated :) system type : Broadcom BCM4716 chip rev 1 cpu model : MIPS 74K V4.0 ASEs implemented : mips16 dsp In those 3 cases /proc/cpuinfo is vastly superior to AT_HWCAP*. Given that the vendor of e500v2 is stingy with expected software, I expect that /proc/cpuinfo contains more and better information. |
|
From: Zhigang L. <zl...@ez...> - 2015-04-10 22:19:15
|
Philippe I can look this carefully for you tonight. A quick look: the doAMode_IR( ... ) has an optimized case when the am->GXam.IR.index = 0. In this condition, the load or store will be mapped as 1 bundle, instead of 2 normally. That could be the reason. ---Zhigang -----Original Message----- From: Philippe Waroquiers [mailto:phi...@sk...] Sent: Friday, April 10, 2015 5:25 PM To: Valgrind Developers Subject: [Valgrind-developers] I need access to a TILEGX :) : libvexmultiarch_test failing with TILEGX host Hello, I am busy preparing a test that ensures that libVEX (somewhat) works when guest != host. I was going to soon commit the test, but now that TILEGX has been committed, the test fails miserably :(. Find attached the patch that adds the new tests and a few changes/fixes in VEX needed for this guest != host setup. When guest = amd64 and host = TILEGX, the libvexmultiarch_test asserts in TILEGX code: vex: priv/host_tilegx_defs.c:2361 (emit_TILEGXInstr): Assertion `evCheckSzB_TILEGX() == (UChar*)p - (UChar*)p0' failed. I have added some traces to see how the 'p' pointer advances. evCheckSzB_TILEGX is 80 bytes, but the 'p' pointer is only advanced by 72 bytes: ------------------------ Assembly ------------------------ EvCheck (evCheck) ld r11, 8(r50); addli r11, r11, -1; st r11, 8(r50); bgez r11, nofail; jalr *(r50); nofail: A 16 0x7fff53188880 0x7fff53188890 B 24 0x7fff53188880 0x7fff53188898 C 40 0x7fff53188880 0x7fff531888a8 D 48 0x7fff53188880 0x7fff531888b0 p1 0x7fff531888a8 E 56 0x7fff53188880 0x7fff531888b8 p1 0x7fff531888a8 F 56 0x7fff53188880 0x7fff531888b8 p1 0x7fff531888a8 p2 0x7fff531888b0 G 64 0x7fff53188880 0x7fff531888c0 H 72 0x7fff53188880 0x7fff531888c8 vex: priv/host_tilegx_defs.c:2361 (emit_TILEGXInstr): Assertion `evCheckSzB_TILEGX() == (UChar*)p - (UChar*)p0' failed. //// failure exit called by libVEX It looks like the evcheck can have a variable nr of instruction, and there is some code aiming at coping with that. But at least on guest amd64/host tilegx, that gives a problem. To reproduce, once V has been build with the patch: cd none/tests ./libvexmultiarch_test 1 0 0 Any idea what is going wrong ? Thanks Philippe NB: Having access to a TILEGX system would have allowed me to investigate the normal expected behaviour of TILEGX evcheck. But I guess at short term, we will have to debug via mail :). |
|
From: Peter B. <be...@vn...> - 2015-04-10 21:39:22
|
On Fri, 2015-04-10 at 06:53 -0700, John Reiser wrote:
> Traditionally the hardware manufacturer publishes such software, which uses
> a combination of software-readable configuration registers and deliberate
> SIGILL faults (for unimplemented instructions) to determine the actual CPU.
PowerPC doesn't have a software readable config register and Julian
showed that relying on SIGILL (or lack thereof) to determine whether
a instruction is supported or not won't work for e500, since the
same opcode is used for different instructions on different cpus.
> On Linux much of the information is encoded in the /proc/cpuinfo pseudo file.
> So parse(read(open("/proc/cpuinfo", O_RDONLY))).
Parsing /proc/cpuinfo is a bad idea. Julian again mentioned the correct
method and that is to query the AT_HWCAP and AT_HWCAP2 flags in the AUXV.
[bergner@makalu ~]$ LD_SHOW_AUXV=1 /bin/true | grep AT_HWCAP
AT_HWCAP: vsx arch_2_06 dfp ic_snoop smt mmu fpu altivec ppc64 ppc32
AT_HWCAP2: tar isel ebb dscr htm arch_2_07
That shows all the instruction categories that are supported in the
cpu you're running on. I thought we (IBM) had added some support for
querying the AT_HWCAP (AT_PLATFORM?) values...or maybe I'm just
remembering us (IBM) talking about it. Carl, what is the status of
using the AT_HWCAP values to enable/disable instruction categories?
> In practice the software would be distributed by Application Support
> Engineers from the _marketing_ department of the chip manufacturer.
> So ask the hardware vendor, ...
This is the real problem, since it seems this specific hardware vendor
doesn't engage with the community that often and their support for their
cpus suffer. The same goes for gcc, glibc, binutils and gdb too.
Peter
|
|
From: Philippe W. <phi...@sk...> - 2015-04-10 21:24:32
|
Hello, I am busy preparing a test that ensures that libVEX (somewhat) works when guest != host. I was going to soon commit the test, but now that TILEGX has been committed, the test fails miserably :(. Find attached the patch that adds the new tests and a few changes/fixes in VEX needed for this guest != host setup. When guest = amd64 and host = TILEGX, the libvexmultiarch_test asserts in TILEGX code: vex: priv/host_tilegx_defs.c:2361 (emit_TILEGXInstr): Assertion `evCheckSzB_TILEGX() == (UChar*)p - (UChar*)p0' failed. I have added some traces to see how the 'p' pointer advances. evCheckSzB_TILEGX is 80 bytes, but the 'p' pointer is only advanced by 72 bytes: ------------------------ Assembly ------------------------ EvCheck (evCheck) ld r11, 8(r50); addli r11, r11, -1; st r11, 8(r50); bgez r11, nofail; jalr *(r50); nofail: A 16 0x7fff53188880 0x7fff53188890 B 24 0x7fff53188880 0x7fff53188898 C 40 0x7fff53188880 0x7fff531888a8 D 48 0x7fff53188880 0x7fff531888b0 p1 0x7fff531888a8 E 56 0x7fff53188880 0x7fff531888b8 p1 0x7fff531888a8 F 56 0x7fff53188880 0x7fff531888b8 p1 0x7fff531888a8 p2 0x7fff531888b0 G 64 0x7fff53188880 0x7fff531888c0 H 72 0x7fff53188880 0x7fff531888c8 vex: priv/host_tilegx_defs.c:2361 (emit_TILEGXInstr): Assertion `evCheckSzB_TILEGX() == (UChar*)p - (UChar*)p0' failed. //// failure exit called by libVEX It looks like the evcheck can have a variable nr of instruction, and there is some code aiming at coping with that. But at least on guest amd64/host tilegx, that gives a problem. To reproduce, once V has been build with the patch: cd none/tests ./libvexmultiarch_test 1 0 0 Any idea what is going wrong ? Thanks Philippe NB: Having access to a TILEGX system would have allowed me to investigate the normal expected behaviour of TILEGX evcheck. But I guess at short term, we will have to debug via mail :). |
|
From: <sv...@va...> - 2015-04-10 19:34:22
|
Author: philippe
Date: Fri Apr 10 20:34:14 2015
New Revision: 15082
Log:
Have the event map GC use the same approach as the other GC
done from libhb_maybe_GC, i.e. check the condition in
libhb_maybe_GC, and call the (non inlined) GC only if
a GC is needed.
Modified:
trunk/helgrind/libhb_core.c
Modified: trunk/helgrind/libhb_core.c
==============================================================================
--- trunk/helgrind/libhb_core.c (original)
+++ trunk/helgrind/libhb_core.c Fri Apr 10 20:34:14 2015
@@ -4491,7 +4491,7 @@
}
__attribute__((noinline))
-static void event_map_maybe_GC ( void )
+static void event_map_GC ( void )
{
OldRef* oldref;
UWord keyW, valW, retained, maxGen;
@@ -4502,9 +4502,6 @@
UWord genMap_min = 0;
UWord genMap_size = 0;
- if (LIKELY(oldrefTreeN < HG_(clo_conflict_cache_size)))
- return;
-
if (0)
VG_(printf)("libhb: event_map GC at size %lu\n", oldrefTreeN);
@@ -6585,7 +6582,9 @@
void libhb_maybe_GC ( void )
{
- event_map_maybe_GC();
+ if (UNLIKELY(oldrefTreeN >= HG_(clo_conflict_cache_size)))
+ event_map_GC();
+
/* If there are still freelist entries available, no need for a
GC. */
if (vts_tab_freelist != VtsID_INVALID)
|
|
From: <sv...@va...> - 2015-04-10 19:08:24
|
Author: philippe
Date: Fri Apr 10 20:08:17 2015
New Revision: 15081
Log:
Update expected result for leak-segv-jmp, following TileGX addition of
a few lines in leak-segv-jmp.c
Modified:
trunk/memcheck/tests/leak-segv-jmp.stderr.exp
Modified: trunk/memcheck/tests/leak-segv-jmp.stderr.exp
==============================================================================
--- trunk/memcheck/tests/leak-segv-jmp.stderr.exp (original)
+++ trunk/memcheck/tests/leak-segv-jmp.stderr.exp Fri Apr 10 20:08:17 2015
@@ -14,8 +14,8 @@
expecting a leak
1,000 bytes in 1 blocks are definitely lost in loss record ... of ...
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: f (leak-segv-jmp.c:199)
- by 0x........: main (leak-segv-jmp.c:262)
+ by 0x........: f (leak-segv-jmp.c:223)
+ by 0x........: main (leak-segv-jmp.c:286)
LEAK SUMMARY:
definitely lost: 1,000 bytes in 1 blocks
@@ -30,8 +30,8 @@
expecting a leak again
1,000 bytes in 1 blocks are definitely lost in loss record ... of ...
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: f (leak-segv-jmp.c:199)
- by 0x........: main (leak-segv-jmp.c:262)
+ by 0x........: f (leak-segv-jmp.c:223)
+ by 0x........: main (leak-segv-jmp.c:286)
LEAK SUMMARY:
definitely lost: 1,000 bytes in 1 blocks
@@ -46,8 +46,8 @@
expecting a leak again after full mprotect
1,000 bytes in 1 blocks are definitely lost in loss record ... of ...
at 0x........: malloc (vg_replace_malloc.c:...)
- by 0x........: f (leak-segv-jmp.c:199)
- by 0x........: main (leak-segv-jmp.c:262)
+ by 0x........: f (leak-segv-jmp.c:223)
+ by 0x........: main (leak-segv-jmp.c:286)
LEAK SUMMARY:
definitely lost: 1,000 bytes in 1 blocks
|
|
From: Philippe W. <phi...@sk...> - 2015-04-10 19:01:16
|
On Fri, 2015-04-10 at 02:30 +0000, Zhigang Liu wrote: > [Zhigang] The regress test shows 20+ failures as post in my previous email today. > Most of them are due to the mismatch source file line # given by stack trace. > The mismatched line number are very close to expected within +/-3. > Apparently, we need improve the stack back trace later. You might compare the stacktraces produced by Valgrind and the stacktraces produced by gdb (using V gdbserver). This might indicate if the problem lies in the Valgrind unwinder or just in the way the compiler generates unwind info. > Regarding the maintaining: we can periodically(say once a week) pull the trunk and > run on TileGX linux machine and post the results on this mail-list. There is a standard script that is used by all nightly builds to build, compare and send the results to the valdev result mailing lists. The idea is to run that nightly (so as to detect problems/regressions) asap. If your company can donate a machine to gcc compile farm, the nightly build can be setup there. Otherwise, a cronjob starting the build in a quiet period is the best thing to do. Philippe |
|
From: Philippe W. <phi...@sk...> - 2015-04-10 18:55:52
|
On Fri, 2015-04-10 at 06:47 +0200, Matthias Schwarzott wrote: > The check "if (fp_min + 256 >= fp_max)" in coregrind/m_stacktrace.c:501 > is triggered here. > > By changing it to "if (fp_min + 128 >= fp_max)" it can be fixed. > > I think amd64 is having problems here because some functions do not need > additional local variables but can use the redzone, so the stackframes > are small. Thanks for this analysis. Some days ago, I looked at the history of this check. I saw that the value was already decreased in the past for amd64. This check is also disabled for Darwin. For x86/ppc32/ppc64/arm/arm64, the value is still 512. s390x/mips32/mips64/tilegx have no such condition. It is not clear to me what is the purpose of this check. I did not find an explanation in the svn history. I am wondering if that had not as objective to avoid SEGV for bogus stack pointers. There was some recent work done to avoid SEGV (e.g. by obtaining better stack limits for unwinding). So, I am not sure that these checks are still useful. Rather, they might only harm in case we have small but valid stack frames. Philippe |
|
From: Philippe W. <phi...@sk...> - 2015-04-10 18:41:19
|
On Fri, 2015-04-10 at 02:34 +0000, Zhigang Liu wrote: [about donate a machine to gcc compile farm] > > I will check if we did that already. Probably not :) Would be nice to have such a machine donated. That will for sure help to keep the TileGX Valgrind port in a good state, and also other free software (gcc, gdb, ...) Philippe |
|
From: Rich C. <rc...@wi...> - 2015-04-10 15:41:23
|
On Wed, 8 Apr 2015 08:35:09 -0500
Rich Coe <rc...@wi...> wrote:
> For mips or ppc, without JeOS, there should be a way to mount a distribution
> dvd of linux and install another platform. I'd have to look into it.
I worked on creating a mips and a ppc qemu installation. I started with ppc
because I know that platform better.
I created a qemu installation for ppc from
openSUSE-13.2-DVD-ppc64-Build0023-Media.iso.
I removed all the xorg etc. packages and made a rootfs directory from the
files in created qemu partition. I copied /usr/bin/qemu-ppc64 and
/usr/bin/qemu-ppc64-binfmt to rootfs/usr/bin.
I installed: gcc gcc-c++ make SDL-devel automake autoconf subversion
I built valgrind with the following config parameters:
Maximum build arch: ppc64be
Primary build arch: ppc64be
Secondary build arch:
Build OS: linux
Primary build target: PPC64BE_LINUX
Secondary build target:
Platform variant: vanilla
Primary -DVGPV string: -DVGPV_ppc64be_linux_vanilla=1
Default supp files: exp-sgcheck.supp xfree-3.supp xfree-4.supp glibc-2.X-drd.supp glibc-2.34567-NPTL-helgrind.supp glibc-2.X.supp
When I try to run the tests, I get an invalid data memory access as shown below
and always from IP 0000000803762300.
Since it always happens, I suspect that something in the V framework is
consistently failing in the same place. I'll have to get into the V internals
more to understand where it's failing.
Here's the traceback from one of the core files:
#0 0x0000000803762780 in ?? ()
#1 0x63de619403724c50 in ?? ()
#2 0x00000000380d5054 in run_thread_for_a_while (two_words=two_words@entry=0x803724e00,
dispatchCtrP=dispatchCtrP@entry=0x803724e14, tid=tid@entry=1, alt_host_addr=98818,
alt_host_addr@entry=18446744073709551615, use_alt_host_addr=use_alt_host_addr@entry=255 '\377')
at m_scheduler/scheduler.c:929
#3 0x00000000380d75a4 in vgPlain_scheduler (tid=<optimized out>) at m_scheduler/scheduler.c:1318
#4 0x00000000380f0e30 in thread_wrapper (tidW=1) at m_syswrap/syswrap-linux.c:103
#5 run_a_thread_NORETURN (tidW=1) at m_syswrap/syswrap-linux.c:156
#6 0x0000000000000000 in ?? ()
(gdb) x/i $pc-4
0x380d5050 <run_thread_for_a_while+560>: bl 0x380c5ea8 <.vgPlain_disp_run_translations>
Here's the output from running the tool:
/usr/local/src/vg/.in_place/memcheck-ppc64be-linux --command-line-only=yes --memcheck:leak-check=no --tool=memcheck ./fwrite
Invalid instruction
NIP 00000000380766c0 LR 00000000380766b0 CTR 0000000000000000 XER 0000000000000000
MSR 8000000002806000 HID0 0000000000000000 HF 0000000002806000 idx 0
TB 00000000 00000000
GPR00 0000000038076330 000000003939bae0 0000000038262010 0000000000000000
GPR04 0000000028000022 000000003939b9f0 0000000000000008 0000000000000000
GPR08 0000000000000000 0000000000000001 0000000000000000 0000000000000000
GPR12 0000000000000008 0000000000000000 0000000000000003 00000040008000e8
GPR16 0000004000800512 000000003939bc90 00000000381e41d0 00000000381e7788
GPR20 00000000381e7748 00000000381e7760 0000000038225b90 0000000000000000
GPR24 00000000381e77c0 00000000381e77a0 00000000381e7770 00000000381e7750
GPR28 000000003824baa8 0000000000000001 0000000038a6a900 000000007ffffffb
CR 28000022 [ E L - - - - E E ] RES ffffffffffffffff
FPR00 7ff0000000000000 0000000000000000 0000000000000000 0000000000000000
FPR04 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR08 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR12 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR24 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR28 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPSCR ffffffff84002000
setup_frame: not implemented
==8095== Memcheck, a memory error detector
==8095== Copyright (C) 2002-2013, and GNU GPL'd, by Julian Seward et al.
==8095== Using Valgrind-3.11.0.SVN and LibVEX; rerun with -h for copyright info
==8095== Command: ./fwrite
==8095==
==8095== Use of uninitialised value of size 8
==8095== at 0x401D620: _dl_sysdep_start (in /lib64/ld-2.19.so)
==8095== by 0x4004047: _dl_start_final (in /lib64/ld-2.19.so)
==8095== by 0x4007FEF: _dl_start (in /lib64/ld-2.19.so)
==8095== by 0x4003CCF: _start (in /lib64/ld-2.19.so)
==8095==
==8095== Use of uninitialised value of size 8
==8095== at 0x401D630: _dl_sysdep_start (in /lib64/ld-2.19.so)
==8095== by 0x4004047: _dl_start_final (in /lib64/ld-2.19.so)
==8095== by 0x4007FEF: _dl_start (in /lib64/ld-2.19.so)
==8095== by 0x4003CCF: _start (in /lib64/ld-2.19.so)
==8095==
==8095== Use of uninitialised value of size 8
==8095== at 0x401D6F4: _dl_sysdep_start (in /lib64/ld-2.19.so)
==8095== by 0x4004047: _dl_start_final (in /lib64/ld-2.19.so)
==8095== by 0x4007FEF: _dl_start (in /lib64/ld-2.19.so)
==8095== by 0x4003CCF: _start (in /lib64/ld-2.19.so)
==8095==
==8095== Use of uninitialised value of size 8
==8095== at 0x401E024: _dl_next_ld_env_entry (in /lib64/ld-2.19.so)
==8095== by 0x40048B3: dl_main (in /lib64/ld-2.19.so)
==8095== by 0x4004047: _dl_start_final (in /lib64/ld-2.19.so)
==8095== by 0x4007FEF: _dl_start (in /lib64/ld-2.19.so)
==8095== by 0x4003CCF: _start (in /lib64/ld-2.19.so)
==8095==
==8095== Use of uninitialised value of size 8
==8095== at 0x401E03C: _dl_next_ld_env_entry (in /lib64/ld-2.19.so)
==8095== by 0x40048B3: dl_main (in /lib64/ld-2.19.so)
==8095== by 0x4004047: _dl_start_final (in /lib64/ld-2.19.so)
==8095== by 0x4007FEF: _dl_start (in /lib64/ld-2.19.so)
==8095== by 0x4003CCF: _start (in /lib64/ld-2.19.so)
==8095==
==8095== Use of uninitialised value of size 8
==8095== at 0x400491C: dl_main (in /lib64/ld-2.19.so)
==8095== by 0x401D873: _dl_sysdep_start (in /lib64/ld-2.19.so)
==8095== by 0x4004047: _dl_start_final (in /lib64/ld-2.19.so)
==8095== by 0x4007FEF: _dl_start (in /lib64/ld-2.19.so)
==8095== by 0x4003CCF: _start (in /lib64/ld-2.19.so)
==8095==
Invalid data memory access: 0x0000000ffeffee80
NIP 0000000803762300 LR 0000000803762300 CTR 0000000038036c40 XER 0000000000000000
MSR 8000000002806000 HID0 0000000000000000 HF 0000000002806000 idx 0
TB 00000000 00000000
GPR00 00000008037622cc 0000000803724a10 0000000038262010 0000000ffeffee80
GPR04 000000003825a2c8 0000000000000000 00000000382622c8 0000000000003ba0
GPR08 0000000000005555 ffffffffffffaaaa 0000000802ba0000 0000000000000000
GPR12 0000000024000048 0000000000000000 0000000000000000 0000000ffeffee80
GPR16 0000000ffefff300 0000000000000000 0000000000000000 0000000ffefff300
GPR20 0000000000000002 0000000ffefff310 0000000000000000 0000000000000000
GPR24 ffffffffffffffbf ffffffffffffffff fffffffffffffffd 0000000038dc4158
GPR28 0000000038a72945 0000000038dc4158 000000000001820c 00000008031835c0
CR 24000082 [ E G - - - - L E ] RES ffffffffffffffff
FPR00 7ff0000000000000 0000000000000000 0000000000000000 0000000000000000
FPR04 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR08 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR12 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR24 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR28 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPSCR ffffffff00000000
Invalid segfault errno (42000000)
NIP 0000000803762300 LR 0000000803762300 CTR 0000000038036c40 XER 0000000000000000
MSR 8000000002806000 HID0 0000000000000000 HF 0000000002806000 idx 0
TB 00000000 00000000
GPR00 00000008037622cc 0000000803724a10 0000000038262010 0000000ffeffee80
GPR04 000000003825a2c8 0000000000000000 00000000382622c8 0000000000003ba0
GPR08 0000000000005555 ffffffffffffaaaa 0000000802ba0000 0000000000000000
GPR12 0000000024000048 0000000000000000 0000000000000000 0000000ffeffee80
GPR16 0000000ffefff300 0000000000000000 0000000000000000 0000000ffefff300
GPR20 0000000000000002 0000000ffefff310 0000000000000000 0000000000000000
GPR24 ffffffffffffffbf ffffffffffffffff fffffffffffffffd 0000000038dc4158
GPR28 0000000038a72945 0000000038dc4158 000000000001820c 00000008031835c0
CR 24000082 [ E G - - - - L E ] RES ffffffffffffffff
FPR00 7ff0000000000000 0000000000000000 0000000000000000 0000000000000000
FPR04 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR08 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR12 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR24 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR28 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPSCR ffffffff00000000
qemu: uncaught target signal 11 (Segmentation fault) - core dumped
|
|
From: Josef W. <Jos...@gm...> - 2015-04-10 15:13:52
|
Can we keep this discussion on the mailing list, so others can add to it? Am 10.04.2015 um 16:35 schrieb Alex: > This tool evaluates the spatial locality for client application (the > length of contiguous data access). I need to test spatial behavior of > various client apps and debug it on single server or cluster to > prevent performance degradation. So it will be better for my analysis > if VG simulated CPU will be closer to my real CPU. I don't understand. Are you worried about doing a wrong analysis when comparing executions within VG vs. native environment? What has this to do with CPU features? As Julian said, VG tries to keep the functional behavior the same, but does not worry about non-functional behavior as you would expect from a simulation (simulated time, simulated energy consumption and so on). Josef This is the only > thing that confuses me. In other respects V is perfect for my > purposes. > > 2015-04-10 16:02 GMT+03:00 Josef Weidendorfer <Jos...@gm...>: >> Am 10.04.2015 um 10:44 schrieb Alex: >>> Can someone provide a quick explanation what are the characteristics >>> of VG simulated CPU (cache, cores, core speed, threads)? >> >> Cachegrind/Callgrind simulate one 2-level cache hierarchy with separate >> L1 data and L1 instuction caches, and unified L2. L1 and L2 are inclusive >> (not strict inclusive) with write-allocate and LRU replacement. >> Cache parameters (associativity/sizes) are taken per default from the CPU >> you run VG on. For newer Intel CPUs with L3, the real L3 parameters are >> used for the L2 in the cache model. >> >> As events, you get number of instructions executed (= fetched from L1), >> data read and written from/to L1, L1D/L1I and L2 misses. >> >> Valgrind serializes threads with a timeslice of 100000 superblocks (which >> may be around a million guest instructions), and all threads make use of the >> same cache hierarchy. So it would compare to a single-core with >> corresponding >> timeslicing. >> >> Any time estimation has to be derived from the collected event counters, >> and you can use your own assumed core speed here. It allows a >> 1 clock/instruction core performance plus some penalties for L1/L2 misses. >> >> The counters do not provide information about whether an evicted cache >> line was dirty or clean; thus, the cache model not even makes a distinction >> between write-through/write-back L1 or L2, as it does not matter. >> >> However, in Callgrind, optionally you can switch on tracking of >> dirty/clean in L2 (--simulate-wb=yes), resulting on more event types. >> Further, "-simulate-hwpref=yes" enables simulation of a page-based >> L2 stream hardware prefetcher (which makes every prefetched line into >> an L2 hit). >> >>> I need >>> benchmark client code for different hardware with my VG tool plugin. >> >> What does your tool provide? >> >> Josef >> >>> >>> Alex. >>> >> >> ------------------------------------------------------------------------------ >> BPM Camp - Free Virtual Workshop May 6th at 10am PDT/1PM EDT >> Develop your own process in accordance with the BPMN 2 standard >> Learn Process modeling best practices with Bonita BPM through live exercises >> http://www.bonitasoft.com/be-part-of-it/events/bpm-camp-virtual- event?utm_ >> source=Sourceforge_BPM_Camp_5_6_15&utm_medium=email&utm_campaign=VA_SF >> _______________________________________________ >> Valgrind-developers mailing list >> Val...@li... >> https://lists.sourceforge.net/lists/listinfo/valgrind-developers > |
|
From: John R. <jr...@bi...> - 2015-04-10 13:53:17
|
On 04/09/2015 04:09 AM, Julian Seward wrote:
> On 08/04/15 12:23, santosh wrote:
>>>> I still get the error: disInstr(ppc): unhandled instruction: 0x10E40301
>>>> I thought Valgrind 3.10.1 has support for CPU: e500v2? NO?
>
> A general comment about e500 support. We've had people asking about this
> for several years now, and I think there are even some patches drifting
> around. From my point of view, the reason these haven't been committed
> is that they require proper integration with the existing POWER/PowerPC
> front end (guest_ppc_toIR.c).
>
> In particular, e500 has some instruction encodings which are interpreted
> as Altivec instructions in the "standard" POWER/PowerPC world. That means
> we can't simply commit e500 support as-is because it will completely break
> the existing POWER/PowerPC targets. Instead, the front end needs to know
> whether it is decoding for e500 or not.
>
> If someone could create a patch which has proper e500 hwcaps detection and
> uses that detection in the front end, and can verify that the patch really
> doesn't break existing POWER/PowerPC targets, then I'd be much more inclined
> to take it. That, as far as I am concerned, is really the limiting factor.
Traditionally the hardware manufacturer publishes such software, which uses
a combination of software-readable configuration registers and deliberate
SIGILL faults (for unimplemented instructions) to determine the actual CPU.
In practice the software would be distributed by Application Support
Engineers from the _marketing_ department of the chip manufacturer.
So ask the hardware vendor, who stands to get more money (or sooner)
by making it easier to use the CPU chips.
On Linux much of the information is encoded in the /proc/cpuinfo pseudo file.
So parse(read(open("/proc/cpuinfo", O_RDONLY))).
Valgrind could contribute a "last resort" option by implementing optional
command-line arguments similar to the -march= or -mcpu= parameters of gcc.
The motivated end user of valgrind should write a patch which implements
the /proc/cpuinfo or -mcpu= strategies. [Let this be a warning
to use hardware that is better supported than e500! such as MIPS, ARM, x86*]
|
|
From: Josef W. <Jos...@gm...> - 2015-04-10 13:02:40
|
Am 10.04.2015 um 10:44 schrieb Alex: > Can someone provide a quick explanation what are the characteristics > of VG simulated CPU (cache, cores, core speed, threads)? Cachegrind/Callgrind simulate one 2-level cache hierarchy with separate L1 data and L1 instuction caches, and unified L2. L1 and L2 are inclusive (not strict inclusive) with write-allocate and LRU replacement. Cache parameters (associativity/sizes) are taken per default from the CPU you run VG on. For newer Intel CPUs with L3, the real L3 parameters are used for the L2 in the cache model. As events, you get number of instructions executed (= fetched from L1), data read and written from/to L1, L1D/L1I and L2 misses. Valgrind serializes threads with a timeslice of 100000 superblocks (which may be around a million guest instructions), and all threads make use of the same cache hierarchy. So it would compare to a single-core with corresponding timeslicing. Any time estimation has to be derived from the collected event counters, and you can use your own assumed core speed here. It allows a 1 clock/instruction core performance plus some penalties for L1/L2 misses. The counters do not provide information about whether an evicted cache line was dirty or clean; thus, the cache model not even makes a distinction between write-through/write-back L1 or L2, as it does not matter. However, in Callgrind, optionally you can switch on tracking of dirty/clean in L2 (--simulate-wb=yes), resulting on more event types. Further, "-simulate-hwpref=yes" enables simulation of a page-based L2 stream hardware prefetcher (which makes every prefetched line into an L2 hit). > I need > benchmark client code for different hardware with my VG tool plugin. What does your tool provide? Josef > > Alex. > |
Author: sewardj
Date: Fri Apr 10 13:30:09 2015
New Revision: 15080
Log:
Add a port to Linux/TileGx. Zhi-Gang Liu (zl...@ti...)
Valgrind aspects, to match vex r3124.
See bug 339778 - Linux/TileGx platform support to Valgrind
Added:
trunk/coregrind/m_dispatch/dispatch-tilegx-linux.S
trunk/coregrind/m_gdbserver/valgrind-low-tilegx.c
trunk/coregrind/m_sigframe/sigframe-tilegx-linux.c
trunk/coregrind/m_syswrap/syscall-tilegx-linux.S
trunk/coregrind/m_syswrap/syswrap-tilegx-linux.c
trunk/include/vki/vki-posixtypes-tilegx-linux.h
trunk/include/vki/vki-scnums-tilegx-linux.h
trunk/include/vki/vki-tilegx-linux.h
trunk/memcheck/tests/origin5-bz2.stderr.exp-glibc212-tilegx
trunk/memcheck/tests/origin6-fp.stderr.exp-glibc212-tilegx
trunk/none/tests/tilegx/
trunk/none/tests/tilegx/Makefile.am
trunk/none/tests/tilegx/allexec.c
Modified:
trunk/Makefile.all.am
trunk/Makefile.tool.am
trunk/Makefile.vex.am
trunk/cachegrind/cg_arch.c
trunk/cachegrind/cg_branchpred.c
trunk/configure.ac
trunk/coregrind/Makefile.am
trunk/coregrind/launcher-linux.c
trunk/coregrind/m_aspacemgr/aspacemgr-common.c
trunk/coregrind/m_cache.c
trunk/coregrind/m_coredump/coredump-elf.c
trunk/coregrind/m_debugger.c
trunk/coregrind/m_debuginfo/d3basics.c
trunk/coregrind/m_debuginfo/debuginfo.c
trunk/coregrind/m_debuginfo/priv_storage.h
trunk/coregrind/m_debuginfo/readdwarf.c
trunk/coregrind/m_debuginfo/readelf.c
trunk/coregrind/m_debuginfo/storage.c
trunk/coregrind/m_debuglog.c
trunk/coregrind/m_gdbserver/target.c
trunk/coregrind/m_gdbserver/valgrind_low.h
trunk/coregrind/m_initimg/initimg-linux.c
trunk/coregrind/m_libcassert.c
trunk/coregrind/m_libcfile.c
trunk/coregrind/m_libcproc.c
trunk/coregrind/m_machine.c
trunk/coregrind/m_main.c
trunk/coregrind/m_redir.c
trunk/coregrind/m_scheduler/scheduler.c
trunk/coregrind/m_signals.c
trunk/coregrind/m_stacktrace.c
trunk/coregrind/m_syscall.c
trunk/coregrind/m_syswrap/priv_types_n_macros.h
trunk/coregrind/m_syswrap/syswrap-linux.c
trunk/coregrind/m_syswrap/syswrap-main.c
trunk/coregrind/m_trampoline.S
trunk/coregrind/m_translate.c
trunk/coregrind/pub_core_aspacemgr.h
trunk/coregrind/pub_core_basics.h
trunk/coregrind/pub_core_debuginfo.h
trunk/coregrind/pub_core_machine.h
trunk/coregrind/pub_core_mallocfree.h
trunk/coregrind/pub_core_syscall.h
trunk/coregrind/pub_core_trampoline.h
trunk/coregrind/pub_core_transtab_asm.h
trunk/coregrind/vgdb-invoker-ptrace.c
trunk/docs/internals/register-uses.txt
trunk/drd/drd_bitmap.h
trunk/drd/drd_clientreq.c
trunk/drd/drd_load_store.c
trunk/exp-sgcheck/pc_main.c
trunk/exp-sgcheck/tests/is_arch_supported
trunk/gdbserver_tests/mcblocklistsearch.vgtest
trunk/gdbserver_tests/nlcontrolc.vgtest
trunk/gdbserver_tests/nlgone_return.vgtest
trunk/helgrind/tests/annotate_hbefore.c
trunk/helgrind/tests/tc07_hbl1.c
trunk/helgrind/tests/tc08_hbl2.c
trunk/helgrind/tests/tc11_XCHG.c
trunk/include/pub_tool_basics.h
trunk/include/pub_tool_guest.h
trunk/include/pub_tool_machine.h
trunk/include/pub_tool_vkiscnums_asm.h
trunk/include/valgrind.h
trunk/include/vki/vki-linux.h
trunk/massif/tests/Makefile.am
trunk/memcheck/mc_machine.c
trunk/memcheck/tests/Makefile.am
trunk/memcheck/tests/atomic_incs.c
trunk/memcheck/tests/leak-segv-jmp.c
trunk/memcheck/tests/vbit-test/irops.c
trunk/memcheck/tests/vbit-test/vtest.h
trunk/none/tests/Makefile.am
trunk/none/tests/allexec_prepare_prereq
trunk/tests/arch_test.c
Modified: trunk/Makefile.all.am
==============================================================================
--- trunk/Makefile.all.am (original)
+++ trunk/Makefile.all.am Fri Apr 10 13:30:09 2015
@@ -234,6 +234,9 @@
$(AM_CFLAGS_PSO_BASE)
AM_CCASFLAGS_MIPS64_LINUX = @FLAG_M64@ -g @FLAG_MIPS64@
+AM_CFLAGS_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CFLAGS_PSO_TILEGX_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE) $(AM_CFLAGS_PSO_BASE)
+
# Flags for the primary target. These must be used to build the
# regtests and performance tests. In fact, these must be used to
# build anything which is built only once on a dual-arch build.
@@ -274,4 +277,5 @@
PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_TILEGX_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
Modified: trunk/Makefile.tool.am
==============================================================================
--- trunk/Makefile.tool.am (original)
+++ trunk/Makefile.tool.am Fri Apr 10 13:30:09 2015
@@ -76,6 +76,9 @@
-static -nodefaultlibs -nostartfiles -u __start @FLAG_NO_BUILD_ID@ \
@FLAG_M64@
+TOOL_LDFLAGS_TILEGX_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
# On Android we must ask for non-executable stack, not sure why.
if VGCONF_PLATFORMS_INCLUDE_ARM_LINUX
if VGCONF_PLATVARIANT_IS_ANDROID
@@ -132,6 +135,9 @@
LIBREPLACEMALLOC_MIPS64_LINUX = \
$(top_builddir)/coregrind/libreplacemalloc_toolpreload-mips64-linux.a
+LIBREPLACEMALLOC_TILEGX_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-tilegx-linux.a
+
LIBREPLACEMALLOC_LDFLAGS_X86_LINUX = \
-Wl,--whole-archive \
$(LIBREPLACEMALLOC_X86_LINUX) \
@@ -188,6 +194,11 @@
$(LIBREPLACEMALLOC_MIPS64_LINUX) \
-Wl,--no-whole-archive
+LIBREPLACEMALLOC_LDFLAGS_TILEGX_LINUX = \
+ -Wl,--whole-archive \
+ $(LIBREPLACEMALLOC_TILEGX_LINUX) \
+ -Wl,--no-whole-archive
+
#----------------------------------------------------------------------------
# General stuff
#----------------------------------------------------------------------------
Modified: trunk/Makefile.vex.am
==============================================================================
--- trunk/Makefile.vex.am (original)
+++ trunk/Makefile.vex.am Fri Apr 10 13:30:09 2015
@@ -26,6 +26,7 @@
pub/libvex_guest_s390x.h \
pub/libvex_guest_mips32.h \
pub/libvex_guest_mips64.h \
+ pub/libvex_guest_tilegx.h \
pub/libvex_s390x_common.h \
pub/libvex_ir.h \
pub/libvex_trc_values.h
@@ -44,6 +45,7 @@
priv/guest_arm64_defs.h \
priv/guest_s390_defs.h \
priv/guest_mips_defs.h \
+ priv/guest_tilegx_defs.h \
priv/host_generic_regs.h \
priv/host_generic_simd64.h \
priv/host_generic_simd128.h \
@@ -57,7 +59,8 @@
priv/host_s390_defs.h \
priv/s390_disasm.h \
priv/s390_defs.h \
- priv/host_mips_defs.h
+ priv/host_mips_defs.h \
+ priv/tilegx_disasm.h
BUILT_SOURCES = pub/libvex_guest_offsets.h
CLEANFILES = pub/libvex_guest_offsets.h
@@ -82,7 +85,8 @@
pub/libvex_guest_arm64.h \
pub/libvex_guest_s390x.h \
pub/libvex_guest_mips32.h \
- pub/libvex_guest_mips64.h
+ pub/libvex_guest_mips64.h \
+ pub/libvex_guest_tilegx.h
rm -f auxprogs/genoffsets.s
$(mkdir_p) auxprogs pub
$(CC) $(CFLAGS_FOR_GENOFFSETS) \
@@ -137,6 +141,8 @@
priv/guest_s390_toIR.c \
priv/guest_mips_helpers.c \
priv/guest_mips_toIR.c \
+ priv/guest_tilegx_helpers.c \
+ priv/guest_tilegx_toIR.c \
priv/host_generic_regs.c \
priv/host_generic_simd64.c \
priv/host_generic_simd128.c \
@@ -157,7 +163,10 @@
priv/host_s390_isel.c \
priv/s390_disasm.c \
priv/host_mips_defs.c \
- priv/host_mips_isel.c
+ priv/host_mips_isel.c \
+ priv/host_tilegx_defs.c \
+ priv/host_tilegx_isel.c \
+ priv/tilegx_disasm.c
LIBVEXMULTIARCH_SOURCES = priv/multiarch_main_main.c
Modified: trunk/cachegrind/cg_arch.c
==============================================================================
--- trunk/cachegrind/cg_arch.c (original)
+++ trunk/cachegrind/cg_arch.c Fri Apr 10 13:30:09 2015
@@ -477,6 +477,13 @@
*D1c = (cache_t) { 65536, 2, 64 };
*LLc = (cache_t) { 262144, 8, 64 };
+#elif defined(VGA_tilegx)
+
+ // Set caches to default for Tilegx.
+ *I1c = (cache_t) { 0x8000, 2, 64 };
+ *D1c = (cache_t) { 0x8000, 2, 64 };
+ *LLc = (cache_t) { 0x40000, 8, 64 };
+
#else
#error "Unknown arch"
Modified: trunk/cachegrind/cg_branchpred.c
==============================================================================
--- trunk/cachegrind/cg_branchpred.c (original)
+++ trunk/cachegrind/cg_branchpred.c Fri Apr 10 13:30:09 2015
@@ -51,6 +51,8 @@
# define N_IADDR_LO_ZERO_BITS 0
#elif defined(VGA_s390x) || defined(VGA_arm)
# define N_IADDR_LO_ZERO_BITS 1
+#elif defined(VGA_tilegx)
+# define N_IADDR_LO_ZERO_BITS 3
#else
# error "Unsupported architecture"
#endif
Modified: trunk/configure.ac
==============================================================================
--- trunk/configure.ac (original)
+++ trunk/configure.ac Fri Apr 10 13:30:09 2015
@@ -268,6 +268,12 @@
AC_MSG_RESULT([ok (${host_cpu})])
ARCH_MAX="mips64"
;;
+
+ tilegx)
+ AC_MSG_RESULT([ok (${host_cpu})])
+ ARCH_MAX="tilegx"
+ ;;
+
*)
AC_MSG_RESULT([no (${host_cpu})])
AC_MSG_ERROR([Unsupported host architecture. Sorry])
@@ -690,6 +696,17 @@
valt_load_address_sec_inner="0xUNSET"
AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
;;
+ tilegx-linux)
+ VGCONF_ARCH_PRI="tilegx"
+ VGCONF_ARCH_SEC=""
+ VGCONF_PLATFORM_PRI_CAPS="TILEGX_LINUX"
+ VGCONF_PLATFORM_SEC_CAPS=""
+ valt_load_address_pri_norml="0x38000000"
+ valt_load_address_pri_inner="0x28000000"
+ valt_load_address_sec_norml="0xUNSET"
+ valt_load_address_sec_inner="0xUNSET"
+ AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
+ ;;
*)
VGCONF_ARCH_PRI="unknown"
VGCONF_ARCH_SEC="unknown"
@@ -733,6 +750,8 @@
test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS32_LINUX )
AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_MIPS64,
test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX )
+AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_TILEGX,
+ test x$VGCONF_PLATFORM_PRI_CAPS = xTILEGX_LINUX )
# Set up VGCONF_PLATFORMS_INCLUDE_<platform>. Either one or two of these
# become defined.
@@ -760,6 +779,8 @@
test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS32_LINUX)
AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_MIPS64_LINUX,
test x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX)
+AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_TILEGX_LINUX,
+ test x$VGCONF_PLATFORM_PRI_CAPS = xTILEGX_LINUX)
AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_X86_DARWIN,
test x$VGCONF_PLATFORM_PRI_CAPS = xX86_DARWIN \
-o x$VGCONF_PLATFORM_SEC_CAPS = xX86_DARWIN)
@@ -780,7 +801,8 @@
-o x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX \
-o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \
-o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS32_LINUX \
- -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX)
+ -o x$VGCONF_PLATFORM_PRI_CAPS = xMIPS64_LINUX \
+ -o x$VGCONF_PLATFORM_PRI_CAPS = xTILEGX_LINUX)
AM_CONDITIONAL(VGCONF_OS_IS_DARWIN,
test x$VGCONF_PLATFORM_PRI_CAPS = xX86_DARWIN \
-o x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_DARWIN)
@@ -3008,6 +3030,7 @@
none/tests/s390x/Makefile
none/tests/mips32/Makefile
none/tests/mips64/Makefile
+ none/tests/tilegx/Makefile
none/tests/linux/Makefile
none/tests/darwin/Makefile
none/tests/x86-linux/Makefile
Modified: trunk/coregrind/Makefile.am
==============================================================================
--- trunk/coregrind/Makefile.am (original)
+++ trunk/coregrind/Makefile.am Fri Apr 10 13:30:09 2015
@@ -343,6 +343,7 @@
m_dispatch/dispatch-s390x-linux.S \
m_dispatch/dispatch-mips32-linux.S \
m_dispatch/dispatch-mips64-linux.S \
+ m_dispatch/dispatch-tilegx-linux.S \
m_dispatch/dispatch-x86-darwin.S \
m_dispatch/dispatch-amd64-darwin.S \
m_gdbserver/inferiors.c \
@@ -362,6 +363,7 @@
m_gdbserver/valgrind-low-s390x.c \
m_gdbserver/valgrind-low-mips32.c \
m_gdbserver/valgrind-low-mips64.c \
+ m_gdbserver/valgrind-low-tilegx.c \
m_gdbserver/version.c \
m_initimg/initimg-linux.c \
m_initimg/initimg-darwin.c \
@@ -384,6 +386,7 @@
m_sigframe/sigframe-s390x-linux.c \
m_sigframe/sigframe-mips32-linux.c \
m_sigframe/sigframe-mips64-linux.c \
+ m_sigframe/sigframe-tilegx-linux.c \
m_sigframe/sigframe-x86-darwin.c \
m_sigframe/sigframe-amd64-darwin.c \
m_syswrap/syscall-x86-linux.S \
@@ -396,6 +399,7 @@
m_syswrap/syscall-s390x-linux.S \
m_syswrap/syscall-mips32-linux.S \
m_syswrap/syscall-mips64-linux.S \
+ m_syswrap/syscall-tilegx-linux.S \
m_syswrap/syscall-x86-darwin.S \
m_syswrap/syscall-amd64-darwin.S \
m_syswrap/syswrap-main.c \
@@ -412,6 +416,7 @@
m_syswrap/syswrap-s390x-linux.c \
m_syswrap/syswrap-mips32-linux.c \
m_syswrap/syswrap-mips64-linux.c \
+ m_syswrap/syswrap-tilegx-linux.c \
m_syswrap/syswrap-x86-darwin.c \
m_syswrap/syswrap-amd64-darwin.c \
m_syswrap/syswrap-xen.c \
Modified: trunk/coregrind/launcher-linux.c
==============================================================================
--- trunk/coregrind/launcher-linux.c (original)
+++ trunk/coregrind/launcher-linux.c Fri Apr 10 13:30:09 2015
@@ -65,6 +65,10 @@
#define EM_PPC64 21 // ditto
#endif
+#ifndef EM_TILEGX
+#define EM_TILEGX 191
+#endif
+
/* Report fatal errors */
__attribute__((noreturn))
static void barf ( const char *format, ... )
@@ -243,6 +247,10 @@
(ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
platform = "mips64-linux";
+ } else if (ehdr->e_machine == EM_TILEGX &&
+ (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ platform = "tilegx-linux";
} else if (ehdr->e_machine == EM_AARCH64 &&
(ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
@@ -349,6 +357,7 @@
(0==strcmp(VG_PLATFORM,"arm-linux")) ||
(0==strcmp(VG_PLATFORM,"arm64-linux")) ||
(0==strcmp(VG_PLATFORM,"s390x-linux")) ||
+ (0==strcmp(VG_PLATFORM,"tilegx-linux")) ||
(0==strcmp(VG_PLATFORM,"mips32-linux")) ||
(0==strcmp(VG_PLATFORM,"mips64-linux")))
default_platform = VG_PLATFORM;
Modified: trunk/coregrind/m_aspacemgr/aspacemgr-common.c
==============================================================================
--- trunk/coregrind/m_aspacemgr/aspacemgr-common.c (original)
+++ trunk/coregrind/m_aspacemgr/aspacemgr-common.c Fri Apr 10 13:30:09 2015
@@ -158,7 +158,8 @@
# elif defined(VGP_amd64_linux) \
|| defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
|| defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \
- || defined(VGP_mips64_linux) || defined(VGP_arm64_linux)
+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux) \
+ || defined(VGP_tilegx_linux)
res = VG_(do_syscall6)(__NR_mmap, (UWord)start, length,
prot, flags, fd, offset);
# elif defined(VGP_x86_darwin)
@@ -245,6 +246,9 @@
/* ARM64 wants to use __NR_openat rather than __NR_open. */
SysRes res = VG_(do_syscall4)(__NR_openat,
VKI_AT_FDCWD, (UWord)pathname, flags, mode);
+# elif defined(VGP_tilegx_linux)
+ SysRes res = VG_(do_syscall4)(__NR_openat, AT_FDCWD, (UWord)pathname,
+ flags, mode);
# else
SysRes res = VG_(do_syscall3)(__NR_open, (UWord)pathname, flags, mode);
# endif
@@ -268,6 +272,9 @@
# if defined(VGP_arm64_linux)
res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD,
(UWord)path, (UWord)buf, bufsiz);
+# elif defined(VGP_tilegx_linux)
+ res = VG_(do_syscall4)(__NR_readlinkat, AT_FDCWD, (UWord)path, (UWord)buf,
+ bufsiz);
# else
res = VG_(do_syscall3)(__NR_readlink, (UWord)path, (UWord)buf, bufsiz);
# endif
Modified: trunk/coregrind/m_cache.c
==============================================================================
--- trunk/coregrind/m_cache.c (original)
+++ trunk/coregrind/m_cache.c Fri Apr 10 13:30:09 2015
@@ -540,8 +540,8 @@
#elif defined(VGA_arm) || defined(VGA_ppc32) || \
defined(VGA_ppc64be) || defined(VGA_ppc64le) || \
- defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64)
-
+ defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64) || \
+ defined(VGA_tilegx)
static Bool
get_cache_info(VexArchInfo *vai)
{
Modified: trunk/coregrind/m_coredump/coredump-elf.c
==============================================================================
--- trunk/coregrind/m_coredump/coredump-elf.c (original)
+++ trunk/coregrind/m_coredump/coredump-elf.c Fri Apr 10 13:30:09 2015
@@ -419,7 +419,17 @@
# undef DO
regs->MIPS_hi = arch->vex.guest_HI;
regs->MIPS_lo = arch->vex.guest_LO;
-
+#elif defined(VGP_tilegx_linux)
+# define DO(n) regs->regs[n] = arch->vex.guest_r##n
+ DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
+ DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
+ DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23);
+ DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
+ DO(32); DO(33); DO(34); DO(35); DO(36); DO(37); DO(38); DO(39);
+ DO(40); DO(41); DO(42); DO(43); DO(44); DO(45); DO(46); DO(47);
+ DO(48); DO(49); DO(50); DO(51); DO(52); DO(53); DO(54); DO(55);
+ regs->pc = arch->vex.guest_pc;
+ regs->orig_r0 = arch->vex.guest_r0;
#else
# error Unknown ELF platform
#endif
@@ -492,7 +502,7 @@
DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
# undef DO
-#elif defined(VGP_arm_linux)
+#elif defined(VGP_arm_linux) || defined(VGP_tilegx_linux)
// umm ...
#elif defined(VGP_arm64_linux)
Modified: trunk/coregrind/m_debugger.c
==============================================================================
--- trunk/coregrind/m_debugger.c (original)
+++ trunk/coregrind/m_debugger.c Fri Apr 10 13:30:09 2015
@@ -386,6 +386,69 @@
regs.MIPS_r31 = vex->guest_r31;
return VG_(ptrace)(VKI_PTRACE_SETREGS, pid, NULL, ®s);
+#elif defined(VGP_tilegx_linux)
+ struct vki_user_regs_struct regs;
+ VG_(memset)(®s, 0, sizeof(regs));
+ regs.TILEGX_r0 = vex->guest_r0;
+ regs.TILEGX_r1 = vex->guest_r1;
+ regs.TILEGX_r2 = vex->guest_r2;
+ regs.TILEGX_r3 = vex->guest_r3;
+ regs.TILEGX_r4 = vex->guest_r4;
+ regs.TILEGX_r5 = vex->guest_r5;
+ regs.TILEGX_r6 = vex->guest_r6;
+ regs.TILEGX_r7 = vex->guest_r7;
+ regs.TILEGX_r8 = vex->guest_r8;
+ regs.TILEGX_r9 = vex->guest_r9;
+ regs.TILEGX_r10 = vex->guest_r10;
+ regs.TILEGX_r11 = vex->guest_r11;
+ regs.TILEGX_r12 = vex->guest_r12;
+ regs.TILEGX_r13 = vex->guest_r13;
+ regs.TILEGX_r14 = vex->guest_r14;
+ regs.TILEGX_r15 = vex->guest_r15;
+ regs.TILEGX_r16 = vex->guest_r16;
+ regs.TILEGX_r17 = vex->guest_r17;
+ regs.TILEGX_r18 = vex->guest_r18;
+ regs.TILEGX_r19 = vex->guest_r19;
+ regs.TILEGX_r20 = vex->guest_r20;
+ regs.TILEGX_r21 = vex->guest_r21;
+ regs.TILEGX_r22 = vex->guest_r22;
+ regs.TILEGX_r23 = vex->guest_r23;
+ regs.TILEGX_r24 = vex->guest_r24;
+ regs.TILEGX_r25 = vex->guest_r25;
+ regs.TILEGX_r26 = vex->guest_r26;
+ regs.TILEGX_r27 = vex->guest_r27;
+ regs.TILEGX_r28 = vex->guest_r28;
+ regs.TILEGX_r29 = vex->guest_r29;
+ regs.TILEGX_r30 = vex->guest_r30;
+ regs.TILEGX_r31 = vex->guest_r31;
+ regs.TILEGX_r32 = vex->guest_r32;
+ regs.TILEGX_r33 = vex->guest_r33;
+ regs.TILEGX_r34 = vex->guest_r34;
+ regs.TILEGX_r35 = vex->guest_r35;
+ regs.TILEGX_r36 = vex->guest_r36;
+ regs.TILEGX_r37 = vex->guest_r37;
+ regs.TILEGX_r38 = vex->guest_r38;
+ regs.TILEGX_r39 = vex->guest_r39;
+ regs.TILEGX_r40 = vex->guest_r40;
+ regs.TILEGX_r41 = vex->guest_r41;
+ regs.TILEGX_r42 = vex->guest_r42;
+ regs.TILEGX_r43 = vex->guest_r43;
+ regs.TILEGX_r44 = vex->guest_r44;
+ regs.TILEGX_r45 = vex->guest_r45;
+ regs.TILEGX_r46 = vex->guest_r46;
+ regs.TILEGX_r47 = vex->guest_r47;
+ regs.TILEGX_r48 = vex->guest_r48;
+ regs.TILEGX_r49 = vex->guest_r49;
+ regs.TILEGX_r50 = vex->guest_r50;
+ regs.TILEGX_r51 = vex->guest_r51;
+ regs.TILEGX_r52 = vex->guest_r52;
+ regs.TILEGX_r53 = vex->guest_r53;
+ regs.TILEGX_r54 = vex->guest_r54;
+ regs.TILEGX_r55 = vex->guest_r55;
+ regs.TILEGX_pc = vex->guest_pc;
+
+ return VG_(ptrace)(VKI_PTRACE_SETREGS, pid, NULL, ®s);
+
#else
# error Unknown arch
#endif
Modified: trunk/coregrind/m_debuginfo/d3basics.c
==============================================================================
--- trunk/coregrind/m_debuginfo/d3basics.c (original)
+++ trunk/coregrind/m_debuginfo/d3basics.c Fri Apr 10 13:30:09 2015
@@ -424,6 +424,9 @@
if (regno == 30) { *a = regs->fp; return True; }
# elif defined(VGP_arm64_linux)
if (regno == 31) { *a = regs->sp; return True; }
+# elif defined(VGP_tilegx_linux)
+ if (regno == 52) { *a = regs->fp; return True; }
+ if (regno == 54) { *a = regs->sp; return True; }
# else
# error "Unknown platform"
# endif
Modified: trunk/coregrind/m_debuginfo/debuginfo.c
==============================================================================
--- trunk/coregrind/m_debuginfo/debuginfo.c (original)
+++ trunk/coregrind/m_debuginfo/debuginfo.c Fri Apr 10 13:30:09 2015
@@ -955,6 +955,9 @@
# elif defined(VGP_s390x_linux)
is_rx_map = seg->hasR && seg->hasX && !seg->hasW;
is_rw_map = seg->hasR && seg->hasW;
+# elif defined(VGA_tilegx)
+ is_rx_map = seg->hasR && seg->hasX; // && !seg->hasW;
+ is_rw_map = seg->hasR && seg->hasW; // && !seg->hasX;
# else
# error "Unknown platform"
# endif
@@ -2488,6 +2491,11 @@
|| defined(VGA_ppc64le)
# elif defined(VGP_arm64_linux)
case Creg_ARM64_X30: return eec->uregs->x30;
+# elif defined(VGA_tilegx)
+ case Creg_TILEGX_IP: return eec->uregs->pc;
+ case Creg_TILEGX_SP: return eec->uregs->sp;
+ case Creg_TILEGX_BP: return eec->uregs->fp;
+ case Creg_TILEGX_LR: return eec->uregs->lr;
# else
# error "Unsupported arch"
# endif
@@ -2743,6 +2751,16 @@
case CFIC_ARM64_X29REL:
cfa = cfsi_m->cfa_off + uregs->x29;
break;
+# elif defined(VGA_tilegx)
+ case CFIC_IA_SPREL:
+ cfa = cfsi_m->cfa_off + uregs->sp;
+ break;
+ case CFIR_SAME:
+ cfa = uregs->fp;
+ break;
+ case CFIC_IA_BPREL:
+ cfa = cfsi_m->cfa_off + uregs->fp;
+ break;
# else
# error "Unsupported arch"
# endif
@@ -2797,7 +2815,7 @@
return compute_cfa(&uregs,
min_accessible, max_accessible, ce->di, ce->cfsi_m);
}
-#elif defined(VGA_mips32) || defined(VGA_mips64)
+#elif defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_tilegx)
{ D3UnwindRegs uregs;
uregs.pc = ip;
uregs.sp = sp;
@@ -2846,6 +2864,8 @@
# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
# elif defined(VGP_arm64_linux)
ipHere = uregsHere->pc;
+# elif defined(VGA_tilegx)
+ ipHere = uregsHere->pc;
# else
# error "Unknown arch"
# endif
@@ -2931,6 +2951,10 @@
COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi_m->sp_how, cfsi_m->sp_off);
COMPUTE(uregsPrev.x30, uregsHere->x30, cfsi_m->x30_how, cfsi_m->x30_off);
COMPUTE(uregsPrev.x29, uregsHere->x29, cfsi_m->x29_how, cfsi_m->x29_off);
+# elif defined(VGA_tilegx)
+ COMPUTE(uregsPrev.pc, uregsHere->pc, cfsi_m->ra_how, cfsi_m->ra_off);
+ COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi_m->sp_how, cfsi_m->sp_off);
+ COMPUTE(uregsPrev.fp, uregsHere->fp, cfsi_m->fp_how, cfsi_m->fp_off);
# else
# error "Unknown arch"
# endif
Modified: trunk/coregrind/m_debuginfo/priv_storage.h
==============================================================================
--- trunk/coregrind/m_debuginfo/priv_storage.h (original)
+++ trunk/coregrind/m_debuginfo/priv_storage.h Fri Apr 10 13:30:09 2015
@@ -333,6 +333,19 @@
Int fp_off;
}
DiCfSI_m;
+#elif defined(VGA_tilegx)
+typedef
+ struct {
+ UChar cfa_how; /* a CFIC_IA value */
+ UChar ra_how; /* a CFIR_ value */
+ UChar sp_how; /* a CFIR_ value */
+ UChar fp_how; /* a CFIR_ value */
+ Int cfa_off;
+ Int ra_off;
+ Int sp_off;
+ Int fp_off;
+ }
+ DiCfSI_m;
#else
# error "Unknown arch"
#endif
@@ -386,7 +399,11 @@
Creg_S390_SP,
Creg_S390_FP,
Creg_S390_LR,
- Creg_MIPS_RA
+ Creg_MIPS_RA,
+ Creg_TILEGX_IP,
+ Creg_TILEGX_SP,
+ Creg_TILEGX_BP,
+ Creg_TILEGX_LR
}
CfiReg;
Modified: trunk/coregrind/m_debuginfo/readdwarf.c
==============================================================================
--- trunk/coregrind/m_debuginfo/readdwarf.c (original)
+++ trunk/coregrind/m_debuginfo/readdwarf.c Fri Apr 10 13:30:09 2015
@@ -1763,6 +1763,10 @@
# define FP_REG 30
# define SP_REG 29
# define RA_REG_DEFAULT 31
+#elif defined(VGP_tilegx_linux)
+# define FP_REG 52
+# define SP_REG 54
+# define RA_REG_DEFAULT 55
#else
# error "Unknown platform"
#endif
@@ -1775,7 +1779,7 @@
|| defined(VGP_ppc64le_linux) || defined(VGP_mips32_linux) \
|| defined(VGP_mips64_linux)
# define N_CFI_REGS 72
-#elif defined(VGP_arm_linux)
+#elif defined(VGP_arm_linux) || defined(VGP_tilegx_linux)
# define N_CFI_REGS 320
#elif defined(VGP_arm64_linux)
# define N_CFI_REGS 128
@@ -2083,7 +2087,8 @@
if (ctxs->cfa_is_regoff && ctxs->cfa_reg == SP_REG) {
si_m->cfa_off = ctxs->cfa_off;
# if defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x) \
- || defined(VGA_mips32) || defined(VGA_mips64)
+ || defined(VGA_mips32) || defined(VGA_mips64) \
+ || defined(VGA_tilegx)
si_m->cfa_how = CFIC_IA_SPREL;
# elif defined(VGA_arm)
si_m->cfa_how = CFIC_ARM_R13REL;
@@ -2097,7 +2102,8 @@
if (ctxs->cfa_is_regoff && ctxs->cfa_reg == FP_REG) {
si_m->cfa_off = ctxs->cfa_off;
# if defined(VGA_x86) || defined(VGA_amd64) || defined(VGA_s390x) \
- || defined(VGA_mips32) || defined(VGA_mips64)
+ || defined(VGA_mips32) || defined(VGA_mips64) \
+ || defined(VGA_tilegx)
si_m->cfa_how = CFIC_IA_BPREL;
# elif defined(VGA_arm)
si_m->cfa_how = CFIC_ARM_R12REL;
@@ -2345,9 +2351,9 @@
return True;
# elif defined(VGA_mips32) || defined(VGA_mips64)
-
+
/* --- entire tail of this fn specialised for mips --- */
-
+
SUMMARISE_HOW(si_m->ra_how, si_m->ra_off,
ctxs->reg[ctx->ra_reg] );
SUMMARISE_HOW(si_m->fp_how, si_m->fp_off,
@@ -2386,7 +2392,48 @@
*len = (UInt)(ctx->loc - loc_start);
return True;
+# elif defined(VGA_tilegx)
+
+ /* --- entire tail of this fn specialised for tilegx --- */
+
+ SUMMARISE_HOW(si_m->ra_how, si_m->ra_off,
+ ctxs->reg[ctx->ra_reg] );
+ SUMMARISE_HOW(si_m->fp_how, si_m->fp_off,
+ ctxs->reg[FP_REG] );
+ SUMMARISE_HOW(si_m->sp_how, si_m->sp_off,
+ ctxs->reg[SP_REG] );
+ si_m->sp_how = CFIR_CFAREL;
+ si_m->sp_off = 0;
+ if (si_m->fp_how == CFIR_UNKNOWN)
+ si_m->fp_how = CFIR_SAME;
+ if (si_m->cfa_how == CFIR_UNKNOWN) {
+ si_m->cfa_how = CFIC_IA_SPREL;
+ si_m->cfa_off = 160;
+ }
+ if (si_m->ra_how == CFIR_UNKNOWN) {
+ if (!debuginfo->cfsi_exprs)
+ debuginfo->cfsi_exprs = VG_(newXA)( ML_(dinfo_zalloc),
+ "di.ccCt.2a",
+ ML_(dinfo_free),
+ sizeof(CfiExpr) );
+ si_m->ra_how = CFIR_EXPR;
+ si_m->ra_off = ML_(CfiExpr_CfiReg)( debuginfo->cfsi_exprs,
+ Creg_TILEGX_LR);
+ }
+
+ if (si_m->ra_how == CFIR_SAME)
+ { why = 3; goto failed; }
+
+ if (loc_start >= ctx->loc)
+ { why = 4; goto failed; }
+ if (ctx->loc - loc_start > 10000000 /* let's say */)
+ { why = 5; goto failed; }
+
+ *base = loc_start + ctx->initloc;
+ *len = (UInt)(ctx->loc - loc_start);
+
+ return True;
# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
/* These don't use CFI based unwinding (is that really true?) */
@@ -2483,6 +2530,13 @@
I_die_here;
# elif defined(VGA_ppc32) || defined(VGA_ppc64be) \
|| defined(VGA_ppc64le)
+# elif defined(VGA_tilegx)
+ if (dwreg == SP_REG)
+ return ML_(CfiExpr_CfiReg)( dstxa, Creg_TILEGX_SP );
+ if (dwreg == FP_REG)
+ return ML_(CfiExpr_CfiReg)( dstxa, Creg_TILEGX_BP );
+ if (dwreg == srcuc->ra_reg)
+ return ML_(CfiExpr_CfiReg)( dstxa, Creg_TILEGX_IP );
# else
# error "Unknown arch"
# endif
Modified: trunk/coregrind/m_debuginfo/readelf.c
==============================================================================
--- trunk/coregrind/m_debuginfo/readelf.c (original)
+++ trunk/coregrind/m_debuginfo/readelf.c Fri Apr 10 13:30:09 2015
@@ -2161,7 +2161,7 @@
# if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \
|| defined(VGP_arm_linux) || defined (VGP_s390x_linux) \
|| defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \
- || defined(VGP_arm64_linux)
+ || defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
/* Accept .plt where mapped as rx (code) */
if (0 == VG_(strcmp)(name, ".plt")) {
if (inrx && !di->plt_present) {
Modified: trunk/coregrind/m_debuginfo/storage.c
==============================================================================
--- trunk/coregrind/m_debuginfo/storage.c (original)
+++ trunk/coregrind/m_debuginfo/storage.c Fri Apr 10 13:30:09 2015
@@ -212,6 +212,11 @@
SHOW_HOW(si_m->x30_how, si_m->x30_off);
VG_(printf)(" X29=");
SHOW_HOW(si_m->x29_how, si_m->x29_off);
+# elif defined(VGA_tilegx)
+ VG_(printf)(" SP=");
+ SHOW_HOW(si_m->sp_how, si_m->sp_off);
+ VG_(printf)(" FP=");
+ SHOW_HOW(si_m->fp_how, si_m->fp_off);
# else
# error "Unknown arch"
# endif
@@ -920,6 +925,10 @@
case Creg_S390_SP: VG_(printf)("SP"); break;
case Creg_S390_FP: VG_(printf)("FP"); break;
case Creg_S390_LR: VG_(printf)("LR"); break;
+ case Creg_TILEGX_IP: VG_(printf)("PC"); break;
+ case Creg_TILEGX_SP: VG_(printf)("SP"); break;
+ case Creg_TILEGX_BP: VG_(printf)("BP"); break;
+ case Creg_TILEGX_LR: VG_(printf)("R55"); break;
default: vg_assert(0);
}
}
Modified: trunk/coregrind/m_debuglog.c
==============================================================================
--- trunk/coregrind/m_debuglog.c (original)
+++ trunk/coregrind/m_debuglog.c Fri Apr 10 13:30:09 2015
@@ -508,6 +508,51 @@
: "$2" );
return (UInt)(__res);
}
+#elif defined(VGP_tilegx_linux)
+static UInt local_sys_write_stderr ( const HChar* buf, Int n )
+{
+ volatile Long block[2];
+ block[0] = (Long)buf;
+ block[1] = n;
+ ULong __res = 0;
+ __asm__ volatile (
+ "movei r0, 2 \n\t" /* stderr */
+ "move r1, %1 \n\t" /* buf */
+ "move r2, %2 \n\t" /* n */
+ "move r3, zero \n\t"
+ "moveli r10, %3 \n\t" /* set r10 = __NR_write */
+ "swint1 \n\t" /* write() */
+ "nop \n\t"
+ "move %0, r0 \n\t" /* save return into block[0] */
+ : "=r"(__res)
+ : "r" (block[0]), "r"(block[1]), "n" (__NR_write)
+ : "r0", "r1", "r2", "r3", "r4", "r5");
+ if (__res < 0)
+ __res = -1;
+ return (UInt)__res;
+}
+
+static UInt local_sys_getpid ( void )
+{
+ UInt __res, __err;
+ __res = 0;
+ __err = 0;
+ __asm__ volatile (
+ "moveli r10, %2\n\t" /* set r10 = __NR_getpid */
+ "swint1\n\t" /* getpid() */
+ "nop\n\t"
+ "move %0, r0\n"
+ "move %1, r1\n"
+ : "=r" (__res), "=r"(__err)
+ : "n" (__NR_getpid)
+ : "r0", "r1", "r2", "r3", "r4",
+ "r5", "r6", "r7", "r8", "r9",
+ "r10", "r11", "r12", "r13", "r14",
+ "r15", "r16", "r17", "r18", "r19",
+ "r20", "r21", "r22", "r23", "r24",
+ "r25", "r26", "r27", "r28", "r29");
+ return __res;
+}
#else
# error Unknown platform
Added: trunk/coregrind/m_dispatch/dispatch-tilegx-linux.S
==============================================================================
--- trunk/coregrind/m_dispatch/dispatch-tilegx-linux.S (added)
+++ trunk/coregrind/m_dispatch/dispatch-tilegx-linux.S Fri Apr 10 13:30:09 2015
@@ -0,0 +1,308 @@
+
+/*--------------------------------------------------------------------*/
+/*--- begin dispatch-tilegx-linux.S ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2013 Tilera Corp.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+/* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
+
+#if defined(VGP_tilegx_linux)
+#include "pub_core_basics_asm.h"
+#include "pub_core_dispatch_asm.h"
+#include "pub_core_transtab_asm.h"
+#include "libvex_guest_offsets.h" /* for OFFSET_tilegx_PC */
+
+ /*------------------------------------------------------------*/
+ /*--- ---*/
+ /*--- The dispatch loop. VG_(run_innerloop) is used to ---*/
+ /*--- run all translations except no-redir ones. ---*/
+ /*--- ---*/
+ /*------------------------------------------------------------*/
+
+ /*----------------------------------------------------*/
+ /*--- Preamble (set everything up) ---*/
+ /*----------------------------------------------------*/
+
+ /* signature:
+ void VG_(disp_run_translations)(UWord* two_words,
+ void* guest_state,
+ Addr host_addr );
+ UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling );
+ */
+
+ .text
+ .globl VG_(disp_run_translations)
+ VG_(disp_run_translations):
+
+ /* r0 holds two_words
+ r1 holds guest_state
+ r2 holds host_addr */
+
+ /* New stack frame */
+ addli sp, sp, -256
+ addi r29, sp, 8
+ /*
+ high memory of stack
+ 216 lr
+ 208 r53
+ 200 r52
+ 192 r51
+ ...
+ 48 r33
+ 40 r32
+ 32 r31
+ 24 r30
+ 16 r1 <---
+ 8 r0
+ 0 <-sp
+ */
+ st_add r29, r0, 8
+ st_add r29, r1, 8
+
+ /* ... and r30 - r53 */
+ st_add r29, r30, 8
+ st_add r29, r31, 8
+ st_add r29, r32, 8
+ st_add r29, r33, 8
+ st_add r29, r34, 8
+ st_add r29, r35, 8
+ st_add r29, r36, 8
+ st_add r29, r37, 8
+ st_add r29, r38, 8
+ st_add r29, r39, 8
+ st_add r29, r40, 8
+ st_add r29, r41, 8
+ st_add r29, r42, 8
+ st_add r29, r43, 8
+ st_add r29, r44, 8
+ st_add r29, r45, 8
+ st_add r29, r46, 8
+ st_add r29, r47, 8
+ st_add r29, r48, 8
+ st_add r29, r49, 8
+ st_add r29, r50, 8
+ st_add r29, r51, 8
+ st_add r29, r52, 8
+ st_add r29, r53, 8
+ st r29, lr
+
+ /* Load the address of guest state into guest state register r50. */
+ move r50, r1
+
+ //j postamble
+
+ /* jump to the code cache. */
+ jr r2
+ /*NOTREACHED*/
+
+
+ /*----------------------------------------------------*/
+ /*--- Postamble and exit. ---*/
+ /*----------------------------------------------------*/
+
+postamble:
+ /* At this point, r12 and r13 contain two
+ words to be returned to the caller. r12
+ holds a TRC value, and r13 optionally may
+ hold another word (for CHAIN_ME exits, the
+ address of the place to patch.) */
+
+ /* run_innerloop_exit_REALLY:
+ r50 holds VG_TRC_* value to return
+ Return to parent stack
+ addli sp, sp, 256 */
+
+ addi r29, sp, 8
+
+ /* Restore r0 from stack; holding address of twp words */
+ ld_add r0, r29, 16
+ /* store r12 in two_words[0] */
+ st_add r0, r12, 8
+ /* store r13 in two_words[1] */
+ st r0, r13
+
+ /* Restore callee-saved registers... */
+ ld_add r30, r29, 8
+ ld_add r31, r29, 8
+ ld_add r32, r29, 8
+ ld_add r33, r29, 8
+ ld_add r34, r29, 8
+ ld_add r35, r29, 8
+ ld_add r36, r29, 8
+ ld_add r37, r29, 8
+ ld_add r38, r29, 8
+ ld_add r39, r29, 8
+ ld_add r40, r29, 8
+ ld_add r41, r29, 8
+ ld_add r42, r29, 8
+ ld_add r43, r29, 8
+ ld_add r44, r29, 8
+ ld_add r45, r29, 8
+ ld_add r46, r29, 8
+ ld_add r47, r29, 8
+ ld_add r48, r29, 8
+ ld_add r49, r29, 8
+ ld_add r50, r29, 8
+ ld_add r51, r29, 8
+ ld_add r52, r29, 8
+ ld_add r53, r29, 8
+ ld lr, r29
+ addli sp, sp, 256 /* stack_size */
+ jr lr
+ nop
+
+
+ /*----------------------------------------------------*/
+ /*--- Continuation points ---*/
+ /*----------------------------------------------------*/
+
+ /* ------ Chain me to slow entry point ------ */
+ .global VG_(disp_cp_chain_me_to_slowEP)
+ VG_(disp_cp_chain_me_to_slowEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ # if (VG_TRC_CHAIN_ME_TO_SLOW_EP > 128)
+ # error ("VG_TRC_CHAIN_ME_TO_SLOW_EP is > 128");
+ # endif
+ moveli r12, VG_TRC_CHAIN_ME_TO_SLOW_EP
+ move r13, lr
+ /* 32 = mkLoadImm_EXACTLY4
+ 8 = jalr r9
+ 8 = nop */
+ addi r13, r13, -40
+ j postamble
+
+ /* ------ Chain me to slow entry point ------ */
+ .global VG_(disp_cp_chain_me_to_fastEP)
+ VG_(disp_cp_chain_me_to_fastEP):
+ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+ # if (VG_TRC_CHAIN_ME_TO_FAST_EP > 128)
+ # error ("VG_TRC_CHAIN_ME_TO_FAST_EP is > 128");
+ # endif
+ moveli r12, VG_TRC_CHAIN_ME_TO_FAST_EP
+ move r13, lr
+ /* 32 = mkLoadImm_EXACTLY4
+ 8 = jalr r9
+ 8 = nop */
+ addi r13, r13, -40
+ j postamble
+
+ /* ------ Indirect but boring jump ------ */
+ .global VG_(disp_cp_xindir)
+ VG_(disp_cp_xindir):
+ /* Where are we going? */
+ addli r11, r50, OFFSET_tilegx_pc
+ ld r11, r11
+
+ moveli r7, hw2_last(VG_(stats__n_xindirs_32))
+ shl16insli r7, r7, hw1(VG_(stats__n_xindirs_32))
+ shl16insli r7, r7, hw0(VG_(stats__n_xindirs_32))
+ ld4u r6, r7
+ addi r6, r6, 1
+ st4 r7, r6
+
+ /* try a fast lookup in the translation cache */
+ /* r14 = VG_TT_FAST_HASH(addr) * sizeof(ULong*)
+ = (t8 >> 3 & VG_TT_FAST_MASK) << 3 */
+
+ move r14, r11
+ /* Assume VG_TT_FAST_MASK < 4G */
+ moveli r12, hw1(VG_TT_FAST_MASK)
+ shl16insli r12, r12, hw0(VG_TT_FAST_MASK)
+ shrui r14, r14, 3
+ and r14, r14, r12
+ shli r14, r14, 4
+ /* Note, each tt_fast hash entry has two pointers i.e. 16 Bytes. */
+
+ /* r13 = (addr of VG_(tt_fast)) + r14 */
+ moveli r13, hw2_last(VG_(tt_fast))
+ shl16insli r13, r13, hw1(VG_(tt_fast))
+ shl16insli r13, r13, hw0(VG_(tt_fast))
+
+ add r13, r13, r14
+
+ /* r12 = VG_(tt_fast)[hash] :: ULong* */
+ ld_add r12, r13, 8
+
+ {
+ ld r25, r13
+ sub r7, r12, r11
+ }
+
+ bnez r7, fast_lookup_failed
+
+ /* Run the translation */
+ jr r25
+
+ .quad 0x0
+
+fast_lookup_failed:
+ /* %PC is up to date */
+ /* back out decrement of the dispatch counter */
+ /* hold dispatch_ctr in t0 (r8) */
+
+ moveli r7, hw2_last(VG_(stats__n_xindir_misses_32))
+ shl16insli r7, r7, hw1(VG_(stats__n_xindir_misses_32))
+ shl16insli r7, r7, hw0(VG_(stats__n_xindir_misses_32))
+ ld4u r6, r7
+ addi r6, r6, 1
+ st4 r7, r6
+ moveli r12, VG_TRC_INNER_FASTMISS
+ movei r13, 0
+ j postamble
+
+ /* ------ Assisted jump ------ */
+ .global VG_(disp_cp_xassisted)
+ VG_(disp_cp_xassisted):
+ /* guest-state-pointer contains the TRC. Put the value into the
+ return register */
+ move r12, r50
+ movei r13, 0
+ j postamble
+
+ /* ------ Event check failed ------ */
+ .global VG_(disp_cp_evcheck_fail)
+ VG_(disp_cp_evcheck_fail):
+ moveli r12, VG_TRC_INNER_COUNTERZERO
+ movei r13, 0
+ j postamble
+
+ .size VG_(disp_run_translations), .-VG_(disp_run_translations)
+
+
+ /* Let the linker know we do not need an executable stack */
+ .section .note.GNU-stack,"",@progbits
+
+#endif /* defined(VGP_tilegx_linux) */
+/*--------------------------------------------------------------------*/
+/*--- end ---*/
+/*--------------------------------------------------------------------*/
+
Modified: trunk/coregrind/m_gdbserver/target.c
==============================================================================
--- trunk/coregrind/m_gdbserver/target.c (original)
+++ trunk/coregrind/m_gdbserver/target.c Fri Apr 10 13:30:09 2015
@@ -804,6 +804,8 @@
mips32_init_architecture(&the_low_target);
#elif defined(VGA_mips64)
mips64_init_architecture(&the_low_target);
+#elif defined(VGA_tilegx)
+ tilegx_init_architecture(&the_low_target);
#else
#error "architecture missing in target.c valgrind_initialize_target"
#endif
Added: trunk/coregrind/m_gdbserver/valgrind-low-tilegx.c
==============================================================================
--- trunk/coregrind/m_gdbserver/valgrind-low-tilegx.c (added)
+++ trunk/coregrind/m_gdbserver/valgrind-low-tilegx.c Fri Apr 10 13:30:09 2015
@@ -0,0 +1,260 @@
+/* Low level interface to valgrind, for the remote server for GDB integrated
+ in valgrind.
+ Copyright (C) 2012
+ Free Software Foundation, Inc.
+
+ This file is part of VALGRIND.
+ It has been inspired from a file from gdbserver in gdb 6.6.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+#include "server.h"
+#include "target.h"
+#include "regdef.h"
+#include "regcache.h"
+
+#include "pub_core_aspacemgr.h"
+#include "pub_core_threadstate.h"
+#include "pub_core_transtab.h"
+#include "pub_core_gdbserver.h"
+
+#include "valgrind_low.h"
+
+#include "libvex_guest_tilegx.h"
+#define REG_ONE(_n) { "r"#_n, 64 * (_n), 64 }
+#define REG_ONE_NAME(_n, _name) { _name, 64 * (_n), 64 }
+
+static struct reg regs[] = {
+ REG_ONE(0),
+ REG_ONE(1),
+ REG_ONE(2),
+ REG_ONE(3),
+ REG_ONE(4),
+ REG_ONE(5),
+ REG_ONE(6),
+ REG_ONE(7),
+ REG_ONE(8),
+ REG_ONE(9),
+
+ REG_ONE(10),
+ REG_ONE(11),
+ REG_ONE(12),
+ REG_ONE(13),
+ REG_ONE(14),
+ REG_ONE(15),
+ REG_ONE(16),
+ REG_ONE(17),
+ REG_ONE(18),
+ REG_ONE(19),
+
+ REG_ONE(20),
+ REG_ONE(21),
+ REG_ONE(22),
+ REG_ONE(23),
+ REG_ONE(24),
+ REG_ONE(25),
+ REG_ONE(26),
+ REG_ONE(27),
+ REG_ONE(28),
+ REG_ONE(29),
+
+ REG_ONE(30),
+ REG_ONE(31),
+ REG_ONE(32),
+ REG_ONE(33),
+ REG_ONE(34),
+ REG_ONE(35),
+ REG_ONE(36),
+ REG_ONE(37),
+ REG_ONE(38),
+ REG_ONE(39),
+
+ REG_ONE(40),
+ REG_ONE(41),
+ REG_ONE(42),
+ REG_ONE(43),
+ REG_ONE(44),
+ REG_ONE(45),
+ REG_ONE(46),
+ REG_ONE(47),
+ REG_ONE(48),
+ REG_ONE(49),
+
+ REG_ONE(50),
+ REG_ONE(51),
+ REG_ONE(52),
+ REG_ONE(53),
+
+ REG_ONE_NAME(54, "sp"),
+ REG_ONE_NAME(55, "lr"),
+ REG_ONE(56),
+ REG_ONE(57),
+ REG_ONE(58),
+ REG_ONE(59),
+
+ REG_ONE(60),
+ REG_ONE(61),
+ REG_ONE(62),
+ REG_ONE_NAME(63, "zero"),
+ REG_ONE_NAME(64, "pc"),
+};
+
+#define num_regs (sizeof (regs) / sizeof (regs[0]))
+
+static const char *expedite_regs[] = { "sp", "pc", 0 };
+
+static
+CORE_ADDR get_pc (void)
+{
+ unsigned long pc;
+
+ collect_register_by_name ("pc", &pc);
+
+ dlog(1, "stop pc is %p\n", (void *) pc);
+ return pc;
+}
+
+static
+void set_pc ( CORE_ADDR newpc )
+{
+ Bool mod;
+ supply_register_by_name ("pc", &newpc, &mod);
+ if (mod)
+ dlog(1, "set pc to %p\n", C2v (newpc));
+ else
+ dlog(1, "set pc not changed %p\n", C2v (newpc));
+}
+
+/* store registers in the guest state (gdbserver_to_valgrind)
+ or fetch register from the guest state (valgrind_to_gdbserver). */
+static
+void transfer_register ( ThreadId tid, int abs_regno, void * buf,
+ transfer_direction dir, int size, Bool *mod )
+{
+ ThreadState* tst = VG_(get_ThreadState)(tid);
+ int set = abs_regno / num_regs;
+ int regno = abs_regno % num_regs;
+ *mod = False;
+
+ VexGuestTILEGXState* tilegx = (VexGuestTILEGXState*) get_arch (set, tst);
+
+ switch (regno) {
+ case 0: VG_(transfer) (&tilegx->guest_r0, buf, dir, size, mod); break;
+ case 1: VG_(transfer) (&tilegx->guest_r1, buf, dir, size, mod); break;
+ case 2: VG_(transfer) (&tilegx->guest_r2, buf, dir, size, mod); break;
+ case 3: VG_(transfer) (&tilegx->guest_r3, buf, dir, size, mod); break;
+ case 4: VG_(transfer) (&tilegx->guest_r4, buf, dir, size, mod); break;
+ case 5: VG_(transfer) (&tilegx->guest_r5, buf, dir, size, mod); break;
+ case 6: VG_(transfer) (&tilegx->guest_r6, buf, dir, size, mod); break;
+ case 7: VG_(transfer) (&tilegx->guest_r7, buf, dir, size, mod); break;
+ case 8: VG_(transfer) (&tilegx->guest_r8, buf, dir, size, mod); break;
+ case 9: VG_(transfer) (&tilegx->guest_r9, buf, dir, size, mod); break;
+ case 10: VG_(transfer) (&tilegx->guest_r10, buf, dir, size, mod); break;
+ case 11: VG_(transfer) (&tilegx->guest_r11, buf, dir, size, mod); break;
+ case 12: VG_(transfer) (&tilegx->guest_r12, buf, dir, size, mod); break;
+ case 13: VG_(transfer) (&tilegx->guest_r13, buf, dir, size, mod); break;
+ case 14: VG_(transfer) (&tilegx->guest_r14, buf, dir, size, mod); break;
+ case 15: VG_(transfer) (&tilegx->guest_r15, buf, dir, size, mod); break;
+ case 16: VG_(transfer) (&tilegx->guest_r16, buf, dir, size, mod); break;
+ case 17: VG_(transfer) (&tilegx->guest_r17, buf, dir, size, mod); break;
+ case 18: VG_(transfer) (&tilegx->guest_r18, buf, dir, size, mod); break;
+ case 19: VG_(transfer) (&tilegx->guest_r19, buf, dir, size, mod); break;
+ case 20: VG_(transfer) (&tilegx->guest_r20, buf, dir, size, mod); break;
+ case 21: VG_(transfer) (&tilegx->guest_r21, buf, dir, size, mod); break;
+ case 22: VG_(transfer) (&tilegx->guest_r22, buf, dir, size, mod); break;
+ case 23: VG_(transfer) (&tilegx->guest_r23, buf, dir, size, mod); break;
+ case 24: VG_(transfer) (&tilegx->guest_r24, buf, dir, size, mod); break;
+ case 25: VG_(transfer) (&tilegx->guest_r25, buf, dir, size, mod); break;
+ case 26: VG_(transfer) (&tilegx->guest_r26, buf, dir, size, mod); break;
+ case 27: VG_(transfer) (&tilegx->guest_r27, buf, dir, size, mod); break;
+ case 28: VG_(transfer) (&tilegx->guest_r28, buf, dir, size, mod); break;
+ case 29: VG_(transfer) (&tilegx->guest_r29, buf, dir, size, mod); break;
+ case 30: VG_(transfer) (&tilegx->guest_r30, buf, dir, size, mod); break;
+ case 31: VG_(transfer) (&tilegx->guest_r31, buf, dir, size, mod); break;
+ case 32: VG_(transfer) (&tilegx->guest_r32, buf, dir, size, mod); break;
+ case 33: VG_(transfer) (&tilegx->guest_r33, buf, dir, size, mod); break;
+ case 34: VG_(transfer) (&tilegx->guest_r34, buf, dir, size, mod); break;
+ case 35: VG_(transfer) (&tilegx->guest_r35, buf, dir, size, mod); break;
+ case 36: VG_(transfer) (&tilegx->guest_r36, buf, dir, size, mod); break;
+ case 37: VG_(transfer) (&tilegx->guest_r37, buf, dir, size, mod); break;
+ case 38: VG_(transfer) (&tilegx->guest_r38, buf, dir, size, mod); break;
+ case 39: VG_(transfer) (&tilegx->guest_r39, buf, dir, size, mod); break;
+ case 40: VG_(transfer) (&tilegx->guest_r40, buf, dir, size, mod); break;
+ case 41: VG_(transfer) (&tilegx->guest_r41, buf, dir, size, mod); break;
+ case 42: VG_(transfer) (&tilegx->guest_r42, buf, dir, size, mod); break;
+ case 43: VG_(transfer) (&tilegx->guest_r43, buf, dir, size, mod); break;
+ case 44: VG_(transfer) (&tilegx->guest_r44, buf, dir, size, mod); break;
+ case 45: VG_(transfer) (&tilegx->guest_r45, buf, dir, size, mod); break;
+ case 46: VG_(transfer) (&tilegx->guest_r46, buf, dir, size, mod); break;
+ case 47: VG_(transfer) (&tilegx->guest_r47, buf, dir, size, mod); break;
+ case 48: VG_(transfer) (&tilegx->guest_r48, buf, dir, size, mod); break;
+ case 49: VG_(transfer) (&tilegx->guest_r49, buf, dir, size, mod); break;
+ case 50: VG_(transfer) (&tilegx->guest_r50, buf, dir, size, mod); break;
+ case 51: VG_(transfer) (&tilegx->guest_r51, buf, dir, size, mod); break;
+ case 52: VG_(transfer) (&tilegx->guest_r52, buf, dir, size, mod); break;
+ case 53: VG_(transfer) (&tilegx->guest_r53, buf, dir, size, mod); break;
+ case 54: VG_(transfer) (&tilegx->guest_r54, buf, dir, size, mod); break;
+ case 55: VG_(transfer) (&tilegx->guest_r55, buf, dir, size, mod); break;
+ case 56: VG_(transfer) (&tilegx->guest_r56, buf, dir, size, mod); break;
+ case 57: VG_(transfer) (&tilegx->guest_r57, buf, dir, size, mod); break;
+ case 58: VG_(transfer) (&tilegx->guest_r58, buf, dir, size, mod); break;
+ case 59: VG_(transfer) (&tilegx->guest_r59, buf, dir, size, mod); break;
+ case 60: VG_(transfer) (&tilegx->guest_r60, buf, dir, size, mod); break;
+ case 61: VG_(transfer) (&tilegx->guest_r61, buf, dir, size, mod); break;
+ case 62: VG_(transfer) (&tilegx->guest_r62, buf, dir, size, mod); break;
+ case 63: VG_(transfer) (&tilegx->guest_r63, buf, dir, size, mod); break;
+ case 64: VG_(transfer) (&tilegx->guest_pc, buf, dir, size, mod); break;
+
+ default: VG_(printf)("regno: %d\n", regno); vg_assert(0);
+ }
+}
+
+static
+const char* target_xml ( Bool shadow_mode )
+{
+ if (shadow_mode) {
+ return "tilegx-linux-valgrind.xml";
+ } else {
+ return "tilegx-linux.xml";
+ }
+}
+
+static CORE_ADDR** target_get_dtv (ThreadState *tst)
+{
+ VexGuestTILEGXState* tilegx = (VexGuestTILEGXState*)&tst->arch.vex;
+ // tilegx dtv location similar to mips
+ return (CORE_ADDR**)((CORE_ADDR)tilegx->guest_r53
+ - 0x7000 - sizeof(CORE_ADDR));
+}
+
+static struct valgrind_target_ops low_target = {
+ num_regs,
+ regs,
+ 54, //sp = r54, which is register offset 54 in regs
+ transfer_register,
+ get_pc,
+ set_pc,
+ "tilegx",
+ target_xml,
+ target_get_dtv
+};
+
+void tilegx_init_architecture ( struct valgrind_target_ops *target )
+{
+ *target = low_target;
+ set_register_cache (regs, num_regs);
+ gdbserver_expedite_regs = expedite_regs;
+}
Modified: trunk/coregrind/m_gdbserver/valgrind_low.h
==============================================================================
--- trunk/coregrind/m_gdbserver/valgrind_low.h (original)
+++ trunk/coregrind/m_gdbserver/valgrind_low.h Fri Apr 10 13:30:09 2015
@@ -107,5 +107,6 @@
extern void s390x_init_architecture (struct valgrind_target_ops *target);
extern void mips32_init_architecture (struct valgrind_target_ops *target);
extern void mips64_init_architecture (struct valgrind_target_ops *target);
+extern void tilegx_init_architecture (struct valgrind_target_ops *target);
#endif
Modified: trunk/coregrind/m_initimg/initimg-linux.c
==============================================================================
--- trunk/coregrind/m_initimg/initimg-linux.c (original)
+++ trunk/coregrind/m_initimg/initimg-linux.c Fri Apr 10 13:30:09 2015
@@ -1173,6 +1173,21 @@
arch->vex.guest_PC = iifii.initial_client_IP;
arch->vex.guest_r31 = iifii.initial_client_SP;
+# elif defined(VGP_tilegx_linux)
+ vg_assert(0 == sizeof(VexGuestTILEGXState) % 8);
+ vg_assert(0 == sizeof(VexGuestTILEGXState) % VexGuestTILEGXStateAlignment);
+
+ /* Zero out the initial state. */
+ LibVEX_GuestTILEGX_initialise(&arch->vex);
+
+ /* Zero out the shadow areas. */
+ VG_(memset)(&arch->vex_shadow1, 0, sizeof(VexGuestTILEGXState));
+ VG_(memset)(&arch->vex_shadow2, 0, sizeof(VexGuestTILEGXState));
+
+ /* Put essential stuff into the new state. */
+ arch->vex.guest_r54 = iifii.initial_client_SP;
+ arch->vex.guest_pc = iifii.initial_client_IP;
+
# else
# error Unknown platform
# endif
Modified: trunk/coregrind/m_libcassert.c
==============================================================================
--- trunk/coregrind/m_libcassert.c (original)
+++ trunk/coregrind/m_libcassert.c Fri Apr 10 13:30:09 2015
@@ -225,6 +225,29 @@
(srP)->misc.MIPS64.r31 = (ULong)ra; \
(srP)->misc.MIPS64.r28 = (ULong)gp; \
}
+#elif defined(VGP_tilegx_linux)
+# define GET_STARTREGS(srP) \
+ { UInt pc, sp, fp, ra; \
+ __asm__ __volatile__( \
+ "move r8, lr \n" \
+ "jal 0f \n" \
+ "0:\n" \
+ "move %0, lr \n" \
+ "move lr, r8 \n" /* put old lr back*/ \
+ "move %1, sp \n" \
+ "move %2, r52 \n" \
+ "move %3, lr \n" \
+ : "=r" (pc), \
+ "=r" (sp), \
+ "=r" (fp), \
+ "=r" (ra) \
+ : /* reads none */ \
+ : "%r8" /* trashed */ ); \
+ (srP)->r_pc = (ULong)pc - 8; \
+ (srP)->r_sp = (ULong)sp; \
+ (srP)->misc.TILEGX.r52 = (ULong)fp; \
+ (srP)->misc.TILEGX.r55 = (ULong)ra; \
+ }
#else
# error Unknown platform
#endif
Modified: trunk/coregrind/m_libcfile.c
==============================================================================
--- trunk/coregrind/m_libcfile.c (original)
+++ trunk/coregrind/m_libcfile.c Fri Apr 10 13:30:09 2015
@@ -131,8 +131,8 @@
}
SysRes VG_(mknod) ( const HChar* pathname, Int mode, UWord dev )
-{
-# if defined(VGP_arm64_linux)
+{
+# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
/* ARM64 wants to use __NR_mknodat rather than __NR_mknod. */
SysRes res = VG_(do_syscall4)(__NR_mknodat,
VKI_AT_FDCWD, (UWord)pathname, mode, dev);
@@ -147,7 +147,7 @@
SysRes VG_(open) ( const HChar* pathname, Int flags, Int mode )
{
-# if defined(VGP_arm64_linux)
+# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
/* ARM64 wants to use __NR_openat rather than __NR_open. */
SysRes res = VG_(do_syscall4)(__NR_openat,
VKI_AT_FDCWD, (UWord)pathname, flags, mode);
@@ -238,7 +238,7 @@
} else {
return -1;
}
-# elif defined(VGP_arm64_linux)
+# elif defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
SysRes res = VG_(do_syscall2)(__NR_pipe2, (UWord)fd, 0);
return sr_isError(res) ? -1 : 0;
# elif defined(VGO_linux)
@@ -328,7 +328,7 @@
# endif /* defined(__NR_stat64) */
/* This is the fallback ("vanilla version"). */
{ struct vki_stat buf;
-# if defined(VGP_arm64_linux)
+# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
res = VG_(do_syscall3)(__NR3264_fstatat, VKI_AT_FDCWD,
(UWord)file_name, (UWord)&buf);
# else
@@ -434,13 +434,18 @@
Int VG_(rename) ( const HChar* old_name, const HChar* new_name )
{
+# if defined(VGP_tilegx_linux)
+ SysRes res = VG_(do_syscall3)(__NR_renameat, AT_FDCWD,
+ (UWord)old_name, (UWord)new_name);
+# else
SysRes res = VG_(do_syscall2)(__NR_rename, (UWord)old_name, (UWord)new_name);
+# endif
return sr_isError(res) ? (-1) : 0;
}
Int VG_(unlink) ( const HChar* file_name )
{
-# if defined(VGP_arm64_linux)
+# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
SysRes res = VG_(do_syscall2)(__NR_unlinkat, VKI_AT_FDCWD,
(UWord)file_name);
# else
@@ -515,7 +520,7 @@
SysRes VG_(poll) (struct vki_pollfd *fds, Int nfds, Int timeout)
{
SysRes res;
-# if defined(VGP_arm64_linux)
+# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
/* ARM64 wants to use __NR_ppoll rather than __NR_poll. */
struct vki_timespec timeout_ts;
if (timeout >= 0) {
@@ -545,7 +550,7 @@
{
SysRes res;
/* res = readlink( path, buf, bufsiz ); */
-# if defined(VGP_arm64_linux)
+# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
res = VG_(do_syscall4)(__NR_readlinkat, VKI_AT_FDCWD,
(UWord)path, (UWord)buf, bufsiz);
# else
@@ -581,7 +586,7 @@
UWord w = (irusr ? VKI_R_OK : 0)
| (iwusr ? VKI_W_OK : 0)
| (ixusr ? VKI_X_OK : 0);
-# if defined(VGP_arm64_linux)
+# if defined(VGP_arm64_linux) || defined(VGP_tilegx_linux)
SysRes res = VG_(do_syscall3)(__NR_faccessat, VKI_AT_FDCWD, (UWord)path, w);
# else
SysRes res = VG_(do_syscall2)(__NR_access, (UWord)path, w);
@@ -721,7 +726,7 @@
# elif defined(VGP_amd64_linux) || defined(VGP_s390x_linux) \
|| defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
|| defined(VGP_mips64_linux) \
- || defined(VGP_arm64_linux)
+ || de...
[truncated message content] |
|
From: <sv...@va...> - 2015-04-10 12:27:53
|
Author: sewardj
Date: Fri Apr 10 13:27:40 2015
New Revision: 3124
Log:
Add a port to Linux/TileGx. Zhi-Gang Liu (zl...@ti...)
VEX aspects.
See bug 339778 - Linux/TileGx platform support to Valgrind
Added:
trunk/priv/guest_tilegx_defs.h
trunk/priv/guest_tilegx_helpers.c
trunk/priv/guest_tilegx_toIR.c
trunk/priv/host_tilegx_defs.c
trunk/priv/host_tilegx_defs.h
trunk/priv/host_tilegx_isel.c
trunk/priv/tilegx_disasm.c
trunk/priv/tilegx_disasm.h
trunk/pub/libvex_guest_tilegx.h
Modified:
trunk/auxprogs/genoffsets.c
trunk/priv/guest_generic_bb_to_IR.c
trunk/priv/ir_defs.c
trunk/priv/main_main.c
trunk/pub/libvex.h
trunk/pub/libvex_basictypes.h
Modified: trunk/auxprogs/genoffsets.c
==============================================================================
--- trunk/auxprogs/genoffsets.c (original)
+++ trunk/auxprogs/genoffsets.c Fri Apr 10 13:27:40 2015
@@ -55,6 +55,7 @@
#include "../pub/libvex_guest_s390x.h"
#include "../pub/libvex_guest_mips32.h"
#include "../pub/libvex_guest_mips64.h"
+#include "../pub/libvex_guest_tilegx.h"
#define VG_STRINGIFZ(__str) #__str
#define VG_STRINGIFY(__str) VG_STRINGIFZ(__str)
@@ -263,6 +264,68 @@
GENOFFSET(MIPS64,mips64,PC);
GENOFFSET(MIPS64,mips64,HI);
GENOFFSET(MIPS64,mips64,LO);
+
+ // Tilegx
+ GENOFFSET(TILEGX,tilegx,r0);
+ GENOFFSET(TILEGX,tilegx,r1);
+ GENOFFSET(TILEGX,tilegx,r2);
+ GENOFFSET(TILEGX,tilegx,r3);
+ GENOFFSET(TILEGX,tilegx,r4);
+ GENOFFSET(TILEGX,tilegx,r5);
+ GENOFFSET(TILEGX,tilegx,r6);
+ GENOFFSET(TILEGX,tilegx,r7);
+ GENOFFSET(TILEGX,tilegx,r8);
+ GENOFFSET(TILEGX,tilegx,r9);
+ GENOFFSET(TILEGX,tilegx,r10);
+ GENOFFSET(TILEGX,tilegx,r11);
+ GENOFFSET(TILEGX,tilegx,r12);
+ GENOFFSET(TILEGX,tilegx,r13);
+ GENOFFSET(TILEGX,tilegx,r14);
+ GENOFFSET(TILEGX,tilegx,r15);
+ GENOFFSET(TILEGX,tilegx,r16);
+ GENOFFSET(TILEGX,tilegx,r17);
+ GENOFFSET(TILEGX,tilegx,r18);
+ GENOFFSET(TILEGX,tilegx,r19);
+ GENOFFSET(TILEGX,tilegx,r20);
+ GENOFFSET(TILEGX,tilegx,r21);
+ GENOFFSET(TILEGX,tilegx,r22);
+ GENOFFSET(TILEGX,tilegx,r23);
+ GENOFFSET(TILEGX,tilegx,r24);
+ GENOFFSET(TILEGX,tilegx,r25);
+ GENOFFSET(TILEGX,tilegx,r26);
+ GENOFFSET(TILEGX,tilegx,r27);
+ GENOFFSET(TILEGX,tilegx,r28);
+ GENOFFSET(TILEGX,tilegx,r29);
+ GENOFFSET(TILEGX,tilegx,r30);
+ GENOFFSET(TILEGX,tilegx,r31);
+ GENOFFSET(TILEGX,tilegx,r32);
+ GENOFFSET(TILEGX,tilegx,r33);
+ GENOFFSET(TILEGX,tilegx,r34);
+ GENOFFSET(TILEGX,tilegx,r35);
+ GENOFFSET(TILEGX,tilegx,r36);
+ GENOFFSET(TILEGX,tilegx,r37);
+ GENOFFSET(TILEGX,tilegx,r38);
+ GENOFFSET(TILEGX,tilegx,r39);
+ GENOFFSET(TILEGX,tilegx,r40);
+ GENOFFSET(TILEGX,tilegx,r41);
+ GENOFFSET(TILEGX,tilegx,r42);
+ GENOFFSET(TILEGX,tilegx,r43);
+ GENOFFSET(TILEGX,tilegx,r44);
+ GENOFFSET(TILEGX,tilegx,r45);
+ GENOFFSET(TILEGX,tilegx,r46);
+ GENOFFSET(TILEGX,tilegx,r47);
+ GENOFFSET(TILEGX,tilegx,r48);
+ GENOFFSET(TILEGX,tilegx,r49);
+ GENOFFSET(TILEGX,tilegx,r50);
+ GENOFFSET(TILEGX,tilegx,r51);
+ GENOFFSET(TILEGX,tilegx,r52);
+ GENOFFSET(TILEGX,tilegx,r53);
+ GENOFFSET(TILEGX,tilegx,r54);
+ GENOFFSET(TILEGX,tilegx,r55);
+ GENOFFSET(TILEGX,tilegx,pc);
+ GENOFFSET(TILEGX,tilegx,EMNOTE);
+ GENOFFSET(TILEGX,tilegx,CMSTART);
+ GENOFFSET(TILEGX,tilegx,NRADDR);
}
/*--------------------------------------------------------------------*/
Modified: trunk/priv/guest_generic_bb_to_IR.c
==============================================================================
--- trunk/priv/guest_generic_bb_to_IR.c (original)
+++ trunk/priv/guest_generic_bb_to_IR.c Fri Apr 10 13:27:40 2015
@@ -374,7 +374,7 @@
|| dres.whatNext == Dis_ResteerU
|| dres.whatNext == Dis_ResteerC);
/* ... disassembled insn length is sane ... */
- vassert(dres.len >= 0 && dres.len <= 20);
+ vassert(dres.len >= 0 && dres.len <= 24);
/* ... continueAt is zero if no resteer requested ... */
if (dres.whatNext != Dis_ResteerU && dres.whatNext != Dis_ResteerC)
vassert(dres.continueAt == 0);
Added: trunk/priv/guest_tilegx_defs.h
==============================================================================
--- trunk/priv/guest_tilegx_defs.h (added)
+++ trunk/priv/guest_tilegx_defs.h Fri Apr 10 13:27:40 2015
@@ -0,0 +1,110 @@
+/*---------------------------------------------------------------*/
+/*--- begin guest_tilegx_defs.h ---*/
+/*---------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2013 Tilera Corp.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+ /* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
+
+#ifndef __VEX_GUEST_TILEGX_DEFS_H
+#define __VEX_GUEST_TILEGX_DEFS_H
+
+#ifdef __tilegx__
+#include "tilegx_disasm.h"
+#endif
+
+/*---------------------------------------------------------*/
+/*--- tilegx to IR conversion ---*/
+/*---------------------------------------------------------*/
+
+/* Convert one TILEGX insn to IR. See the type DisOneInstrFn in
+ bb_to_IR.h. */
+extern DisResult disInstr_TILEGX ( IRSB* irbb,
+ Bool (*resteerOkFn) ( void *, Addr ),
+ Bool resteerCisOk,
+ void* callback_opaque,
+ const UChar* guest_code,
+ Long delta,
+ Addr guest_IP,
+ VexArch guest_arch,
+ const VexArchInfo* archinfo,
+ const VexAbiInfo* abiinfo,
+ VexEndness host_endness_IN,
+ Bool sigill_diag_IN );
+
+/* Used by the optimiser to specialise calls to helpers. */
+extern IRExpr *guest_tilegx_spechelper ( const HChar * function_name,
+ IRExpr ** args,
+ IRStmt ** precedingStmts,
+ Int n_precedingStmts );
+
+/* Describes to the optimser which part of the guest state require
+ precise memory exceptions. This is logically part of the guest
+ state description. */
+extern Bool guest_tilegx_state_requires_precise_mem_exns (
+ Int, Int, VexRegisterUpdates );
+
+extern VexGuestLayout tilegxGuest_layout;
+
+/*---------------------------------------------------------*/
+/*--- tilegx guest helpers ---*/
+/*---------------------------------------------------------*/
+
+extern ULong tilegx_dirtyhelper_gen ( ULong opc,
+ ULong rd0,
+ ULong rd1,
+ ULong rd2,
+ ULong rd3 );
+
+/*---------------------------------------------------------*/
+/*--- Condition code stuff ---*/
+/*---------------------------------------------------------*/
+
+/* Defines conditions which we can ask for TILEGX */
+
+typedef enum {
+ TILEGXCondEQ = 0, /* equal : Z=1 */
+ TILEGXCondNE = 1, /* not equal : Z=0 */
+ TILEGXCondHS = 2, /* >=u (higher or same) : C=1 */
+ TILEGXCondLO = 3, /* <u (lower) : C=0 */
+ TILEGXCondMI = 4, /* minus (negative) : N=1 */
+ TILEGXCondPL = 5, /* plus (zero or +ve) : N=0 */
+ TILEGXCondVS = 6, /* overflow : V=1 */
+ TILEGXCondVC = 7, /* no overflow : V=0 */
+ TILEGXCondHI = 8, /* >u (higher) : C=1 && Z=0 */
+ TILEGXCondLS = 9, /* <=u (lower or same) : C=0 || Z=1 */
+ TILEGXCondGE = 10, /* >=s (signed greater or equal) : N=V */
+ TILEGXCondLT = 11, /* <s (signed less than) : N!=V */
+ TILEGXCondGT = 12, /* >s (signed greater) : Z=0 && N=V */
+ TILEGXCondLE = 13, /* <=s (signed less or equal) : Z=1 || N!=V */
+ TILEGXCondAL = 14, /* always (unconditional) : 1 */
+ TILEGXCondNV = 15 /* never (unconditional): : 0 */
+} TILEGXCondcode;
+
+#endif /* __VEX_GUEST_TILEGX_DEFS_H */
+
+/*---------------------------------------------------------------*/
+/*--- end guest_tilegx_defs.h ---*/
+/*---------------------------------------------------------------*/
Added: trunk/priv/guest_tilegx_helpers.c
==============================================================================
--- trunk/priv/guest_tilegx_helpers.c (added)
+++ trunk/priv/guest_tilegx_helpers.c Fri Apr 10 13:27:40 2015
@@ -0,0 +1,1112 @@
+/*---------------------------------------------------------------*/
+/*--- begin guest_tilegx_helpers.c ---*/
+/*---------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2013 Tilera Corp.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+/* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
+
+#include "libvex_basictypes.h"
+#include "libvex_emnote.h"
+#include "libvex_guest_tilegx.h"
+#include "libvex_ir.h"
+#include "libvex.h"
+
+#include "main_util.h"
+#include "guest_generic_bb_to_IR.h"
+#include "guest_tilegx_defs.h"
+
+/* This file contains helper functions for tilegx guest code. Calls to
+ these functions are generated by the back end.
+*/
+
+#define ALWAYSDEFD(field) \
+ { offsetof(VexGuestTILEGXState, field), \
+ (sizeof ((VexGuestTILEGXState*)0)->field) }
+
+/* generalised left-shifter */
+static inline UInt lshift ( UInt x, Int n )
+{
+ if (n >= 0)
+ return x << n;
+ else
+ return x >> (-n);
+}
+
+IRExpr *guest_tilegx_spechelper ( const HChar * function_name, IRExpr ** args,
+ IRStmt ** precedingStmts, Int n_precedingStmts)
+{
+ return NULL;
+}
+
+/* VISIBLE TO LIBVEX CLIENT */
+void LibVEX_GuestTILEGX_initialise ( VexGuestTILEGXState * vex_state )
+{
+ vex_state->guest_r0 = 0;
+ vex_state->guest_r1 = 0;
+ vex_state->guest_r2 = 0;
+ vex_state->guest_r3 = 0;
+ vex_state->guest_r4 = 0;
+ vex_state->guest_r5 = 0;
+ vex_state->guest_r6 = 0;
+ vex_state->guest_r7 = 0;
+ vex_state->guest_r8 = 0;
+ vex_state->guest_r9 = 0;
+ vex_state->guest_r10 = 0;
+ vex_state->guest_r11 = 0;
+ vex_state->guest_r12 = 0;
+ vex_state->guest_r13 = 0;
+ vex_state->guest_r14 = 0;
+ vex_state->guest_r15 = 0;
+ vex_state->guest_r16 = 0;
+ vex_state->guest_r17 = 0;
+ vex_state->guest_r18 = 0;
+ vex_state->guest_r19 = 0;
+ vex_state->guest_r20 = 0;
+ vex_state->guest_r21 = 0;
+ vex_state->guest_r22 = 0;
+ vex_state->guest_r23 = 0;
+ vex_state->guest_r24 = 0;
+ vex_state->guest_r25 = 0;
+ vex_state->guest_r26 = 0;
+ vex_state->guest_r27 = 0;
+ vex_state->guest_r28 = 0;
+ vex_state->guest_r29 = 0;
+ vex_state->guest_r30 = 0;
+ vex_state->guest_r31 = 0;
+ vex_state->guest_r32 = 0;
+ vex_state->guest_r33 = 0;
+ vex_state->guest_r34 = 0;
+ vex_state->guest_r35 = 0;
+ vex_state->guest_r36 = 0;
+ vex_state->guest_r37 = 0;
+ vex_state->guest_r38 = 0;
+ vex_state->guest_r39 = 0;
+ vex_state->guest_r40 = 0;
+ vex_state->guest_r41 = 0;
+ vex_state->guest_r42 = 0;
+ vex_state->guest_r43 = 0;
+ vex_state->guest_r44 = 0;
+ vex_state->guest_r45 = 0;
+ vex_state->guest_r46 = 0;
+ vex_state->guest_r47 = 0;
+ vex_state->guest_r48 = 0;
+ vex_state->guest_r49 = 0;
+ vex_state->guest_r50 = 0;
+ vex_state->guest_r51 = 0;
+ vex_state->guest_r52 = 0;
+ vex_state->guest_r53 = 0;
+ vex_state->guest_r54 = 0;
+ vex_state->guest_r55 = 0;
+
+ vex_state->guest_pc = 0; /* Program counter */
+
+ vex_state->guest_EMNOTE = 0;
+ vex_state->guest_CMSTART = 0;
+
+ /* For clflush: record start and length of area to invalidate */
+ vex_state->guest_CMSTART = 0;
+ vex_state->guest_CMLEN = 0;
+
+ /* Used to record the unredirected guest address at the start of
+ a translation whose start has been redirected. By reading
+ this pseudo-register shortly afterwards, the translation can
+ find out what the corresponding no-redirection address was.
+ Note, this is only set for wrap-style redirects, not for
+ replace-style ones. */
+ vex_state->guest_NRADDR = 0;
+}
+
+/*-----------------------------------------------------------*/
+/*--- Describing the tilegx guest state, for the benefit ---*/
+/*--- of iropt and instrumenters. ---*/
+/*-----------------------------------------------------------*/
+
+/* Figure out if any part of the guest state contained in minoff
+ .. maxoff requires precise memory exceptions. If in doubt return
+ True (but this is generates significantly slower code).
+
+ We enforce precise exns for guest SP, PC.
+*/
+Bool guest_tilegx_state_requires_precise_mem_exns (
+ Int minoff, Int maxoff,
+ VexRegisterUpdates pxControl)
+{
+ Int sp_min = offsetof(VexGuestTILEGXState, guest_r54);
+ Int sp_max = sp_min + 8 - 1;
+ Int pc_min = offsetof(VexGuestTILEGXState, guest_pc);
+ Int pc_max = pc_min + 8 - 1;
+
+ if (maxoff < sp_min || minoff > sp_max) {
+ /* no overlap with sp */
+ if (pxControl == VexRegUpdSpAtMemAccess)
+ return False; /* We only need to check stack pointer. */
+ } else {
+ return True;
+ }
+
+ if (maxoff < pc_min || minoff > pc_max) {
+ /* no overlap with pc */
+ } else {
+ return True;
+ }
+
+ /* We appear to need precise updates of R52 in order to get proper
+ stacktraces from non-optimised code. */
+ Int fp_min = offsetof(VexGuestTILEGXState, guest_r52);
+ Int fp_max = fp_min + 8 - 1;
+
+ if (maxoff < fp_min || minoff > fp_max) {
+ /* no overlap with fp */
+ } else {
+ return True;
+ }
+
+ return False;
+}
+
+VexGuestLayout tilegxGuest_layout = {
+ /* Total size of the guest state, in bytes. */
+ .total_sizeB = sizeof(VexGuestTILEGXState),
+ /* Describe the stack pointer. */
+ .offset_SP = offsetof(VexGuestTILEGXState, guest_r54),
+ .sizeof_SP = 8,
+ /* Describe the frame pointer. */
+ .offset_FP = offsetof(VexGuestTILEGXState, guest_r52),
+ .sizeof_FP = 8,
+ /* Describe the instruction pointer. */
+ .offset_IP = offsetof(VexGuestTILEGXState, guest_pc),
+ .sizeof_IP = 8,
+ /* Describe any sections to be regarded by Memcheck as
+ 'always-defined'. */
+ .n_alwaysDefd = 8,
+ /* ? :( */
+ .alwaysDefd = {
+ /* 0 */ ALWAYSDEFD(guest_r0),
+ /* 1 */ ALWAYSDEFD(guest_r1),
+ /* 2 */ ALWAYSDEFD(guest_EMNOTE),
+ /* 3 */ ALWAYSDEFD(guest_CMSTART),
+ /* 4 */ ALWAYSDEFD(guest_CMLEN),
+ /* 5 */ ALWAYSDEFD(guest_r52),
+ /* 6 */ ALWAYSDEFD(guest_r55),
+ /* 7 */ ALWAYSDEFD(guest_pc),
+ }
+};
+
+#ifdef __tilegx__
+ULong tilegx_dirtyhelper_gen ( ULong opc,
+ ULong rd0, ULong rd1,
+ ULong rd2, ULong rd3)
+{
+ switch (opc)
+ {
+ case 0:
+ {
+ /* break point */
+ switch (rd0) {
+ case 0x286a44ae90048fffULL:
+ asm (" bpt ");
+ break;
+ default:
+ vex_printf("unhandled \"bpt\": cins=%016llx\n", rd0);
+
+ vassert(0);
+ return 0;
+ }
+ }
+ break;
+ case 28:
+ {
+ return __insn_addxsc(rd1, rd2);
+ }
+ break;
+
+ case 150:
+ {
+ __insn_mf();
+ return 0;
+ }
+ break;
+
+ case 152: /* mm rd, ra, imm0, imm1 */
+ {
+ ULong mask;
+
+ if( rd2 <= rd3)
+ mask = (-1ULL << rd2) ^ ((-1ULL << rd3) << 1);
+ else
+ mask = (-1ULL << rd2) | (-1ULL >> (63 - rd3));
+
+ return (rd0 & mask) | (rd1 & (-1ULL ^ mask));
+ }
+ break;
+ case 154: /* mtspr imm, ra */
+ {
+ switch(rd0)
+ {
+ case 0x2785:
+ __insn_mtspr(0x2785, rd1);
+ break;
+ case 0x2780:
+ __insn_mtspr(0x2780, rd1);
+ break;
+ case 0x2708:
+ __insn_mtspr(0x2708, rd1);
+ break;
+ case 0x2580:
+ __insn_mtspr(0x2580, rd1);
+ break;
+ case 0x2581:
+ __insn_mtspr(0x2581, rd1);
+ break;
+ case 0x2709: // PASS
+ __insn_mtspr(0x2709, rd1);
+ break;
+ case 0x2707: // FAIL
+ __insn_mtspr(0x2707, rd1);
+ break;
+ case 0x2705: // DONE
+ __insn_mtspr(0x2705, rd1);
+ break;
+
+ case 0x2870: //
+
+ default:
+ vex_printf("opc=%d rd0=%llx rd1=%llx\n",
+ (int)opc, rd0, rd1);
+ vassert(0);
+ }
+ }
+ break;
+
+ case 151: /* mfspr rd, imm */
+ {
+ switch(rd1)
+ {
+ case 0x2785: // SIM_CTRL
+ return __insn_mfspr(0x2785);
+ break;
+
+ case 0x2708: // ICS
+ return __insn_mfspr(0x2708);
+ break;
+
+ case 0x2780: // CMPEXCH_VALUE
+ return __insn_mfspr(0x2780);
+ break;
+
+ case 0x2781: // CYCLE
+ return __insn_mfspr(0x2781);
+ break;
+
+ case 0x2709: // PASS
+ return __insn_mfspr(0x2709);
+ break;
+
+ case 0x2707: // FAIL
+ return __insn_mfspr(0x2707);
+ break;
+
+ case 0x2705: // DONE
+ return __insn_mfspr(0x2705);
+ break;
+
+ case 0x2580: // EX_CONTEXT_0
+ return __insn_mfspr(0x2580);
+ break;
+
+ case 0x2581: // EX_CONTEXT_1
+ return __insn_mfspr(0x2581);
+ break;
+
+ default:
+ vex_printf("opc=%d rd0=%llx rd1=%llx\n",
+ (int)opc, rd0, rd1);
+ vassert(0);
+ }
+ }
+ break;
+ case 183:
+ {
+ return __insn_pcnt(rd1);
+ }
+ break;
+ case 184:
+ {
+ return __insn_revbits(rd1);
+ }
+ break;
+ case 185: /* revbytes rd, ra */
+ {
+ return __insn_revbytes(rd1);
+ }
+ break;
+
+ case 102:
+ return __insn_fsingle_add1(rd1, rd2);
+ break;
+
+ case 103:
+ return __insn_fsingle_addsub2(rd0, rd1, rd2);
+ break;
+
+ case 104:
+ return __insn_fsingle_mul1(rd1, rd2);
+ break;
+
+ case 105:
+ return __insn_fsingle_mul2(rd1, rd2);
+ break;
+
+ case 106:
+ return __insn_fsingle_pack1(rd1);
+ break;
+
+ case 107:
+ return __insn_fsingle_pack2(rd1, rd2);
+ break;
+
+ case 108:
+ return __insn_fsingle_sub1(rd1, rd2);
+ break;
+
+ case 21:
+ switch (rd0) {
+ case 0x286a44ae90048fffULL:
+ asm ("{ moveli zero, 72 ; raise }");
+ break;
+ default:
+ vex_printf("unhandled \"raise\": cins=%016llx\n", rd0);
+ __insn_ill();
+ return 0;
+ }
+ break;
+
+ case 64:
+ {
+ return __insn_cmul(rd1, rd2);
+ }
+ break;
+ case 65:
+ {
+ return __insn_cmula(rd0, rd1, rd2);
+ }
+ break;
+ case 66:
+ {
+ return __insn_cmulaf(rd0, rd1, rd2);
+ }
+ break;
+ case 67:
+ {
+ return __insn_cmulf(rd1, rd2);
+ }
+ break;
+ case 68:
+ {
+ return __insn_cmulfr(rd1, rd2);
+ }
+ break;
+ case 69:
+ {
+ return __insn_cmulh(rd1, rd2);
+ }
+ break;
+ case 70:
+ {
+ return __insn_cmulhr(rd1, rd2);
+ }
+ break;
+ case 71:
+ {
+ return __insn_crc32_32(rd1, rd2);
+ }
+ break;
+ case 72:
+ {
+ return __insn_crc32_8(rd1, rd2);
+ }
+ break;
+ case 75:
+ {
+ return __insn_dblalign2(rd1, rd2);
+ }
+ break;
+ case 76:
+ {
+ return __insn_dblalign4(rd1, rd2);
+ }
+ break;
+ case 77:
+ {
+ return __insn_dblalign6(rd1, rd2);
+ }
+ break;
+ case 78:
+ {
+ __insn_drain();
+ return 0;
+ }
+ break;
+ case 79:
+ {
+ __insn_dtlbpr(rd0);
+ return 0;
+ }
+ break;
+ case 82:
+ {
+ return __insn_fdouble_add_flags(rd1, rd2);
+ }
+ break;
+ case 83:
+ {
+ return __insn_fdouble_addsub(rd0, rd1, rd2);
+ }
+ break;
+ case 84:
+ {
+ return __insn_fdouble_mul_flags(rd1, rd2);
+ }
+ break;
+ case 85:
+ {
+ return __insn_fdouble_pack1(rd1, rd2);
+ }
+ break;
+ case 86:
+ {
+ return __insn_fdouble_pack2(rd0, rd1, rd2);
+ }
+ break;
+ case 87:
+ {
+ return __insn_fdouble_sub_flags(rd1, rd2);
+ }
+ break;
+ case 88:
+ {
+ return __insn_fdouble_unpack_max(rd1, rd2);
+ }
+ break;
+ case 89:
+ {
+ return __insn_fdouble_unpack_min(rd1, rd2);
+ }
+ break;
+
+ case 98:
+ {
+ __insn_finv(rd0);
+ return 0;
+ }
+ break;
+ case 99:
+ {
+ __insn_flush(rd0);
+ return 0;
+ }
+ break;
+ case 100:
+ {
+ __insn_flushwb();
+ return 0;
+ }
+ break;
+
+ case 109:
+ {
+ __insn_icoh((ULong *)rd0);
+ return 0;
+ }
+ break;
+ case 110:
+ {
+ __insn_ill();
+ }
+ break;
+ case 111:
+ {
+ __insn_inv((ULong *)rd0);
+ return 0;
+ }
+ break;
+
+ case 169:
+ {
+ return __insn_mula_hu_hu(rd0, rd1, rd2);
+ }
+ break;
+ case 170:
+ {
+ return __insn_mula_hu_ls(rd0, rd1, rd2);
+ }
+ break;
+ case 205:
+ {
+ return __insn_shufflebytes(rd0, rd1, rd2);
+ }
+ break;
+ case 224:
+ {
+ return __insn_subxsc(rd1, rd2);
+ }
+ break;
+ case 229:
+ {
+ return __insn_tblidxb0(rd0, rd1);
+ }
+ break;
+ case 230:
+ {
+ return __insn_tblidxb1(rd0, rd1);
+ }
+ break;
+ case 231:
+ {
+ return __insn_tblidxb2(rd0, rd1);
+ }
+ break;
+ case 232:
+ {
+ return __insn_tblidxb3(rd0, rd1);
+ }
+ break;
+ case 233:
+ {
+ return __insn_v1add(rd1, rd2);
+ }
+ break;
+ case 234:
+ {
+ return __insn_v1add(rd1, rd2);
+ }
+ break;
+ case 235:
+ {
+ return __insn_v1adduc(rd1, rd2);
+ }
+ break;
+ case 236:
+ {
+ return __insn_v1adiffu(rd1, rd2);
+ }
+ break;
+ case 237:
+ {
+ return __insn_v1avgu(rd1, rd2);
+ }
+ break;
+
+ case 238:
+ {
+ return __insn_v1cmpeq(rd1, rd2);
+ }
+ break;
+ case 239:
+ {
+ return __insn_v1cmpeq(rd1, rd2);
+ }
+ break;
+ case 240:
+ {
+ return __insn_v1cmples(rd1, rd2);
+ }
+ break;
+ case 241:
+ {
+ return __insn_v1cmpleu(rd1, rd2);
+ }
+ break;
+ case 242:
+ {
+ return __insn_v1cmplts(rd1, rd2);
+ }
+ break;
+ case 243:
+ {
+ return __insn_v1cmplts(rd1, rd2);
+ }
+ break;
+ case 244:
+ {
+ return __insn_v1cmpltu(rd1, rd2);
+ }
+ break;
+ case 245:
+ {
+ return __insn_v1cmpltu(rd1, rd2);
+ }
+ break;
+ case 246:
+ {
+ return __insn_v1cmpne(rd1, rd2);
+ }
+ break;
+ case 247:
+ {
+ return __insn_v1ddotpu(rd1, rd2);
+ }
+ break;
+ case 248:
+ {
+ return __insn_v1ddotpua(rd0, rd1, rd2);
+ }
+ break;
+ case 249:
+ {
+ return __insn_v1ddotpus(rd1, rd2);
+ }
+ break;
+ case 250:
+ {
+ return __insn_v1ddotpusa(rd0, rd1, rd2);
+ }
+ break;
+ case 251:
+ {
+ return __insn_v1dotp(rd1, rd2);
+ }
+ break;
+ case 252:
+ {
+ return __insn_v1dotpa(rd0, rd1, rd2);
+ }
+ break;
+ case 253:
+ {
+ return __insn_v1dotpu(rd1, rd2);
+ }
+ break;
+ case 254:
+ {
+ return __insn_v1dotpua(rd0, rd1, rd2);
+ }
+ break;
+ case 255:
+ {
+ return __insn_v1dotpus(rd1, rd2);
+ }
+ break;
+ case 256:
+ {
+ return __insn_v1dotpusa(rd0, rd1, rd2);
+ }
+ break;
+ case 257:
+ {
+ return __insn_v1int_h(rd1, rd2);
+ }
+ break;
+ case 258:
+ {
+ return __insn_v1int_l(rd1, rd2);
+ }
+ break;
+ case 259:
+ {
+ return __insn_v1maxu(rd1, rd2);
+ }
+ break;
+ case 260:
+ {
+ return __insn_v1maxu(rd1, rd2);
+ }
+ break;
+ case 261:
+ {
+ return __insn_v1minu(rd1, rd2);
+ }
+ break;
+ case 262:
+ {
+ return __insn_v1minu(rd1, rd2);
+ }
+ break;
+ case 263:
+ {
+ return __insn_v1mnz(rd1, rd2);
+ }
+ break;
+ case 264:
+ {
+ return __insn_v1multu(rd1, rd2);
+ }
+ break;
+ case 265:
+ {
+ return __insn_v1mulu(rd1, rd2);
+ }
+ break;
+ case 266:
+ {
+ return __insn_v1mulus(rd1, rd2);
+ }
+ break;
+ case 267:
+ {
+ return __insn_v1mz(rd1, rd2);
+ }
+ break;
+ case 268:
+ {
+ return __insn_v1sadau(rd0, rd1, rd2);
+ }
+ break;
+ case 269:
+ {
+ return __insn_v1sadu(rd1, rd2);
+ }
+ break;
+ case 270:
+ {
+ return __insn_v1shl(rd1, rd2);
+ }
+ break;
+ case 271:
+ {
+ return __insn_v1shli(rd1, rd2);
+ }
+ break;
+ case 272:
+ {
+ return __insn_v1shrs(rd1, rd2);
+ }
+ break;
+ case 273:
+ {
+ return __insn_v1shrsi(rd1, rd2);
+ }
+ break;
+ case 274:
+ {
+ return __insn_v1shru(rd1, rd2);
+ }
+ break;
+ case 275:
+ {
+ return __insn_v1shrui(rd1, rd2);
+ }
+ break;
+ case 276:
+ {
+ return __insn_v1sub(rd1, rd2);
+ }
+ break;
+ case 277:
+ {
+ return __insn_v1subuc(rd1, rd2);
+ }
+ break;
+ case 278:
+ {
+ return __insn_v2add(rd1, rd2);
+ }
+ break;
+ case 279:
+ {
+ return __insn_v2add(rd1, rd2);
+ }
+ break;
+ case 280:
+ {
+ return __insn_v2addsc(rd1, rd2);
+ }
+ break;
+ case 281:
+ {
+ return __insn_v2adiffs(rd1, rd2);
+ }
+ break;
+ case 282:
+ {
+ return __insn_v2avgs(rd1, rd2);
+ }
+ break;
+ case 283:
+ {
+ return __insn_v2cmpeq(rd1, rd2);
+ }
+ break;
+ case 284:
+ {
+ return __insn_v2cmpeq(rd1, rd2);
+ }
+ break;
+ case 285:
+ {
+ return __insn_v2cmples(rd1, rd2);
+ }
+ break;
+ case 286:
+ {
+ return __insn_v2cmpleu(rd1, rd2);
+ }
+ break;
+ case 287:
+ {
+ return __insn_v2cmplts(rd1, rd2);
+ }
+ break;
+ case 288:
+ {
+ return __insn_v2cmplts(rd1, rd2);
+ }
+ break;
+ case 289:
+ {
+ return __insn_v2cmpltu(rd1, rd2);
+ }
+ break;
+ case 290:
+ {
+ return __insn_v2cmpltu(rd1, rd2);
+ }
+ break;
+ case 291:
+ {
+ return __insn_v2cmpne(rd1, rd2);
+ }
+ break;
+ case 292:
+ {
+ return __insn_v2dotp(rd1, rd2);
+ }
+ break;
+ case 293:
+ {
+ return __insn_v2dotpa(rd0, rd1, rd2);
+ }
+ break;
+ case 294:
+ {
+ return __insn_v2int_h(rd1, rd2);
+ }
+ break;
+ case 295:
+ {
+ return __insn_v2int_l(rd1, rd2);
+ }
+ break;
+ case 296:
+ {
+ return __insn_v2maxs(rd1, rd2);
+ }
+ break;
+ case 297:
+ {
+ return __insn_v2maxs(rd1, rd2);
+ }
+ break;
+ case 298:
+ {
+ return __insn_v2mins(rd1, rd2);
+ }
+ break;
+ case 299:
+ {
+ return __insn_v2mins(rd1, rd2);
+ }
+ break;
+ case 300:
+ {
+ return __insn_v2mnz(rd1, rd2);
+ }
+ break;
+ case 301:
+ {
+ return __insn_v2mulfsc(rd1, rd2);
+ }
+ break;
+ case 302:
+ {
+ return __insn_v2muls(rd1, rd2);
+ }
+ break;
+ case 303:
+ {
+ return __insn_v2mults(rd1, rd2);
+ }
+ break;
+ case 304:
+ {
+ return __insn_v2mz(rd1, rd2);
+ }
+ break;
+ case 305:
+ {
+ return __insn_v2packh(rd1, rd2);
+ }
+ break;
+ case 306:
+ {
+ return __insn_v2packl(rd1, rd2);
+ }
+ break;
+ case 307:
+ {
+ return __insn_v2packuc(rd1, rd2);
+ }
+ break;
+ case 308:
+ {
+ return __insn_v2sadas(rd0, rd1, rd2);
+ }
+ break;
+ case 309:
+ {
+ return __insn_v2sadau(rd0, rd1, rd2);
+ }
+ break;
+ case 310:
+ {
+ return __insn_v2sads(rd1, rd2);
+ }
+ break;
+ case 311:
+ {
+ return __insn_v2sadu(rd1, rd2);
+ }
+ break;
+ case 312:
+ {
+ return __insn_v2shl(rd1, rd2);
+ }
+ break;
+ case 313:
+ {
+ return __insn_v2shli(rd1, rd2);
+ }
+ break;
+ case 314:
+ {
+ return __insn_v2shlsc(rd1, rd2);
+ }
+ break;
+ case 315:
+ {
+ return __insn_v2shrs(rd1, rd2);
+ }
+ break;
+ case 316:
+ {
+ return __insn_v2shrsi(rd1, rd2);
+ }
+ break;
+ case 317:
+ {
+ return __insn_v2shru(rd1, rd2);
+ }
+ break;
+ case 318:
+ {
+ return __insn_v2shrui(rd1, rd2);
+ }
+ break;
+ case 319:
+ {
+ return __insn_v2sub(rd1, rd2);
+ }
+ break;
+ case 320:
+ {
+ return __insn_v2subsc(rd1, rd2);
+ }
+ break;
+ case 321:
+ {
+ return __insn_v4add(rd1, rd2);
+ }
+ break;
+ case 322:
+ {
+ return __insn_v4addsc(rd1, rd2);
+ }
+ break;
+ case 323:
+ {
+ return __insn_v4int_h(rd1, rd2);
+ }
+ break;
+ case 324:
+ {
+ return __insn_v4int_l(rd1, rd2);
+ }
+ break;
+ case 325:
+ {
+ return __insn_v4packsc(rd1, rd2);
+ }
+ break;
+ case 326:
+ {
+ return __insn_v4shl(rd1, rd2);
+ }
+ break;
+ case 327:
+ {
+ return __insn_v4shlsc(rd1, rd2);
+ }
+ break;
+ case 328:
+ {
+ return __insn_v4shrs(rd1, rd2);
+ }
+ break;
+ case 329:
+ {
+ return __insn_v4shru(rd1, rd2);
+ }
+ break;
+ case 330:
+ {
+ return __insn_v4sub(rd1, rd2);
+ }
+ break;
+ case 331:
+ {
+ return __insn_v4subsc(rd1, rd2);
+ }
+ break;
+
+ default:
+ vex_printf("opc=%d rd0=%llx rd1=%llx\n",
+ (int)opc, rd0, rd1);
+ vassert(0);
+ }
+}
+#else
+ULong tilegx_dirtyhelper_gen ( ULong opc,
+ ULong rd0, ULong rd1,
+ ULong rd2, ULong rd3 )
+{
+ vex_printf("NOT a TILEGX platform");
+ return 0;
+}
+#endif /* __tilegx__ */
+
+/*---------------------------------------------------------------*/
+/*--- end guest_tilegx_helpers.c ---*/
+/*---------------------------------------------------------------*/
Added: trunk/priv/guest_tilegx_toIR.c
==============================================================================
--- trunk/priv/guest_tilegx_toIR.c (added)
+++ trunk/priv/guest_tilegx_toIR.c Fri Apr 10 13:27:40 2015
@@ -0,0 +1,2518 @@
+
+/*--------------------------------------------------------------------*/
+/*--- begin guest_tilegx_toIR.c ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+ This file is part of Valgrind, a dynamic binary instrumentation
+ framework.
+
+ Copyright (C) 2010-2013 Tilera Corp.
+
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
+
+ The GNU General Public License is contained in the file COPYING.
+*/
+
+/* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */
+
+/* Translates TILEGX code to IR. */
+
+#include "libvex_basictypes.h"
+#include "libvex_ir.h"
+#include "libvex.h"
+#include "libvex_guest_tilegx.h"
+
+#include "main_util.h"
+#include "main_globals.h"
+#include "guest_generic_bb_to_IR.h"
+#include "guest_tilegx_defs.h"
+#include "tilegx_disasm.h"
+
+#if __tilegx__
+/*------------------------------------------------------------*/
+/*--- Globals ---*/
+/*------------------------------------------------------------*/
+
+/* These are set at the start of the translation of a instruction, so
+ that we don't have to pass them around endlessly. CONST means does
+ not change during translation of the instruction.
+*/
+
+/* CONST: is the host bigendian? This has to do with float vs double
+ register accesses on VFP, but it's complex and not properly thought
+ out. */
+static VexEndness host_endness;
+
+/* Pointer to the guest code area. */
+static UChar *guest_code;
+
+/* The guest address corresponding to guest_code[0]. */
+static Addr64 guest_PC_bbstart;
+
+/* CONST: The guest address for the instruction currently being
+ translated. */
+static Addr64 guest_PC_curr_instr;
+
+/* MOD: The IRSB* into which we're generating code. */
+static IRSB *irsb;
+
+/*------------------------------------------------------------*/
+/*--- Debugging output ---*/
+/*------------------------------------------------------------*/
+
+#define DIP(format, args...) \
+ if (vex_traceflags & VEX_TRACE_FE) \
+ vex_printf(format, ## args)
+
+/*------------------------------------------------------------*/
+/*--- Helper bits and pieces for deconstructing the ---*/
+/*--- tilegx insn stream. ---*/
+/*------------------------------------------------------------*/
+
+static Int integerGuestRegOffset ( UInt iregNo )
+{
+ return 8 * (iregNo);
+}
+
+/*------------------------------------------------------------*/
+/*--- Field helpers ---*/
+/*------------------------------------------------------------*/
+
+/*------------------------------------------------------------*/
+/*--- Helper bits and pieces for creating IR fragments. ---*/
+/*------------------------------------------------------------*/
+
+static IRExpr *mkU8 ( UInt i )
+{
+ return IRExpr_Const(IRConst_U8((UChar) i));
+}
+
+/* Create an expression node for a 32-bit integer constant */
+static IRExpr *mkU32 ( UInt i )
+{
+ return IRExpr_Const(IRConst_U32(i));
+}
+
+/* Create an expression node for a 64-bit integer constant */
+static IRExpr *mkU64 ( ULong i )
+{
+ return IRExpr_Const(IRConst_U64(i));
+}
+
+static IRExpr *mkexpr ( IRTemp tmp )
+{
+ return IRExpr_RdTmp(tmp);
+}
+
+static IRExpr *unop ( IROp op, IRExpr * a )
+{
+ return IRExpr_Unop(op, a);
+}
+
+static IRExpr *binop ( IROp op, IRExpr * a1, IRExpr * a2 )
+{
+ return IRExpr_Binop(op, a1, a2);
+}
+
+static IRExpr *load ( IRType ty, IRExpr * addr )
+{
+ IRExpr *load1 = NULL;
+
+ load1 = IRExpr_Load(Iend_LE, ty, addr);
+ return load1;
+}
+
+/* Add a statement to the list held by "irsb". */
+static void stmt ( IRStmt * st )
+{
+ addStmtToIRSB(irsb, st);
+}
+
+#define OFFB_PC offsetof(VexGuestTILEGXState, guest_pc)
+
+static void putPC ( IRExpr * e )
+{
+ stmt(IRStmt_Put(OFFB_PC, e));
+}
+
+static void assign ( IRTemp dst, IRExpr * e )
+{
+ stmt(IRStmt_WrTmp(dst, e));
+}
+
+static void store ( IRExpr * addr, IRExpr * data )
+{
+ stmt(IRStmt_Store(Iend_LE, addr, data));
+}
+
+/* Generate a new temporary of the given type. */
+static IRTemp newTemp ( IRType ty )
+{
+ vassert(isPlausibleIRType(ty));
+ return newIRTemp(irsb->tyenv, ty);
+}
+
+static ULong extend_s_16to64 ( UInt x )
+{
+ return (ULong) ((((Long) x) << 48) >> 48);
+}
+
+static ULong extend_s_8to64 ( UInt x )
+{
+ return (ULong) ((((Long) x) << 56) >> 56);
+}
+
+static IRExpr *getIReg ( UInt iregNo )
+{
+ IRType ty = Ity_I64;
+ if(!(iregNo < 56 || iregNo == 63 ||
+ (iregNo >= 70 && iregNo <= 73))) {
+ vex_printf("iregNo=%d\n", iregNo);
+ vassert(0);
+ }
+ return IRExpr_Get(integerGuestRegOffset(iregNo), ty);
+}
+
+static void putIReg ( UInt archreg, IRExpr * e )
+{
+ IRType ty = Ity_I64;
+ if(!(archreg < 56 || archreg == 63 || archreg == 70 ||
+ archreg == 72 || archreg == 73)) {
+ vex_printf("archreg=%d\n", archreg);
+ vassert(0);
+ }
+ vassert(typeOfIRExpr(irsb->tyenv, e) == ty);
+ if (archreg != 63)
+ stmt(IRStmt_Put(integerGuestRegOffset(archreg), e));
+}
+
+/* Narrow 8/16/32 bit int expr to 8/16/32. Clearly only some
+ of these combinations make sense. */
+static IRExpr *narrowTo ( IRType dst_ty, IRExpr * e )
+{
+ IRType src_ty = typeOfIRExpr(irsb->tyenv, e);
+ if (src_ty == dst_ty)
+ return e;
+ if (src_ty == Ity_I32 && dst_ty == Ity_I16)
+ return unop(Iop_32to16, e);
+ if (src_ty == Ity_I32 && dst_ty == Ity_I8)
+ return unop(Iop_32to8, e);
+
+ if (src_ty == Ity_I64 && dst_ty == Ity_I8) {
+ return unop(Iop_64to8, e);
+ }
+ if (src_ty == Ity_I64 && dst_ty == Ity_I16) {
+ return unop(Iop_64to16, e);
+ }
+ if (src_ty == Ity_I64 && dst_ty == Ity_I32) {
+ return unop(Iop_64to32, e);
+ }
+
+ if (vex_traceflags & VEX_TRACE_FE) {
+ vex_printf("\nsrc, dst tys are: ");
+ ppIRType(src_ty);
+ vex_printf(", ");
+ ppIRType(dst_ty);
+ vex_printf("\n");
+ }
+ vpanic("narrowTo(tilegx)");
+ return e;
+}
+
+#define signExtend(_e, _n) \
+ ((_n == 32) ? \
+ unop(Iop_32Sto64, _e) : \
+ ((_n == 16) ? \
+ (Iop_16Sto64, _e) : \
+ (binop(Iop_Sar64, binop(Iop_Shl64, _e, mkU8(63 - (_n))), mkU8(63 - (_n))))))
+
+static IRStmt* dis_branch ( IRExpr* guard, ULong imm )
+{
+ IRTemp t0;
+
+ t0 = newTemp(Ity_I1);
+ assign(t0, guard);
+ return IRStmt_Exit(mkexpr(t0), Ijk_Boring,
+ IRConst_U64(imm), OFFB_PC);
+}
+
+#define MARK_REG_WB(_rd, _td) \
+ do { \
+ vassert(rd_wb_index < 6); \
+ rd_wb_temp[rd_wb_index] = _td; \
+ rd_wb_reg[rd_wb_index] = _rd; \
+ rd_wb_index++; \
+ } while(0)
+
+/*------------------------------------------------------------*/
+/*--- Disassemble a single instruction ---*/
+/*------------------------------------------------------------*/
+
+/* Disassemble a single instruction bundle into IR. The bundle is
+ located in host memory at guest_instr, and has guest IP of
+ guest_PC_curr_instr, which will have been set before the call
+ here. */
+static DisResult disInstr_TILEGX_WRK ( Bool(*resteerOkFn) (void *, Addr),
+ Bool resteerCisOk,
+ void *callback_opaque,
+ Long delta64,
+ const VexArchInfo * archinfo,
+ const VexAbiInfo * abiinfo,
+ Bool sigill_diag )
+{
+ struct tilegx_decoded_instruction
+ decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
+ ULong cins, opcode, rd, ra, rb, imm;
+ ULong opd[4];
+ ULong opd_src_map, opd_dst_map, opd_imm_map;
+ Int use_dirty_helper;
+ IRTemp t0, t1, t2, t3, t4;
+ IRTemp tb[4];
+ IRTemp rd_wb_temp[6];
+ ULong rd_wb_reg[6];
+ /* Tilegx is a VLIW processor, we have to commit register write after read.*/
+ Int rd_wb_index;
+ Int n, nr_insn;
+ DisResult dres;
+ Int stmts_used;
+
+ /* The running delta */
+ Long delta = delta64;
+
+ /* Holds pc at the start of the insn, so that we can print
+ consistent error messages for unimplemented insns. */
+ //Long delta_start = delta;
+
+ UChar *code = (UChar *) (guest_code + delta);
+
+ IRStmt *bstmt = NULL; /* Branch statement. */
+ IRExpr *next = NULL; /* Next bundle expr. */
+ ULong jumpkind = Ijk_Boring;
+ ULong steering_pc;
+
+ /* Set result defaults. */
+ dres.whatNext = Dis_Continue;
+ dres.len = 0;
+ dres.continueAt = 0;
+ dres.jk_StopHere = Ijk_INVALID;
+
+ /* Verify the code addr is 8-byte aligned. */
+ vassert((((ULong)code) & 7) == 0);
+
+ /* Get the instruction bundle. */
+ cins = *((ULong *)(Addr) code);
+
+ /* "Special" instructions. */
+ /* Spot the 16-byte preamble: ****tilegx****
+ 0:02b3c7ff91234fff { moveli zero, 4660 ; moveli zero, 22136 }
+ 8:0091a7ff95678fff { moveli zero, 22136 ; moveli zero, 4660 }
+ */
+#define CL_W0 0x02b3c7ff91234fffULL
+#define CL_W1 0x0091a7ff95678fffULL
+
+ if (*((ULong*)(Addr)(code)) == CL_W0 &&
+ *((ULong*)(Addr)(code + 8)) == CL_W1) {
+ /* Got a "Special" instruction preamble. Which one is it? */
+ if (*((ULong*)(Addr)(code + 16)) ==
+ 0x283a69a6d1483000ULL /* or r13, r13, r13 */ ) {
+ /* r0 = client_request ( r12 ) */
+ DIP("r0 = client_request ( r12 )\n");
+
+ putPC(mkU64(guest_PC_curr_instr + 24));
+
+ dres.jk_StopHere = Ijk_ClientReq;
+ dres.whatNext = Dis_StopHere;
+ dres.len = 24;
+ goto decode_success;
+
+ } else if (*((ULong*)(Addr)(code + 16)) ==
+ 0x283a71c751483000ULL /* or r14, r14, r14 */ ) {
+ /* r11 = guest_NRADDR */
+ DIP("r11 = guest_NRADDR\n");
+ dres.len = 24;
+ putIReg(11, IRExpr_Get(offsetof(VexGuestTILEGXState, guest_NRADDR),
+ Ity_I64));
+ putPC(mkU64(guest_PC_curr_instr + 8));
+ goto decode_success;
+
+ } else if (*((ULong*)(Addr)(code + 16)) ==
+ 0x283a79e7d1483000ULL /* or r15, r15, r15 */ ) {
+ /* branch-and-link-to-noredir r12 */
+ DIP("branch-and-link-to-noredir r12\n");
+ dres.len = 24;
+ putIReg(55, mkU64(guest_PC_curr_instr + 24));
+
+ putPC(getIReg(12));
+
+ dres.jk_StopHere = Ijk_NoRedir;
+ dres.whatNext = Dis_StopHere;
+ goto decode_success;
+
+ } else if (*((ULong*)(Addr)(code + 16)) ==
+ 0x283a5965d1483000ULL /* or r11, r11, r11 */ ) {
+ /* vex-inject-ir */
+ DIP("vex-inject-ir\n");
+ dres.len = 24;
+
+ vex_inject_ir(irsb, Iend_LE);
+
+ stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_CMSTART),
+ mkU64(guest_PC_curr_instr)));
+ stmt(IRStmt_Put(offsetof(VexGuestTILEGXState, guest_CMLEN),
+ mkU64(24)));
+
+ /* 2 + 1 = 3 bundles. 24 bytes. */
+ putPC(mkU64(guest_PC_curr_instr + 24));
+
+ dres.jk_StopHere = Ijk_InvalICache;
+ dres.whatNext = Dis_StopHere;
+ goto decode_success;
+ }
+
+ /* We don't expect this. */
+ vex_printf("%s: unexpect special bundles at %lx\n",
+ __func__, (Addr)guest_PC_curr_instr);
+ delta += 16;
+ goto decode_failure;
+ /*NOTREACHED*/
+ }
+
+ /* To decode the given instruction bundle. */
+ nr_insn = parse_insn_tilegx((tilegx_bundle_bits)cins,
+ (ULong)code,
+ decoded);
+
+ if (vex_traceflags & VEX_TRACE_FE)
+ decode_and_display(&cins, 1, (ULong)code);
+
+ /* Init. rb_wb_index */
+ rd_wb_index = 0;
+
+ steering_pc = -1ULL;
+
+ // Save the current stmts_used in case we need rollback.
+ stmts_used = irsb->stmts_used;
+
+ for (n = 0; n < nr_insn; n++) {
+ opcode = decoded[n].opcode->mnemonic;
+ Int opi;
+
+ rd = ra = rb = -1;
+ opd[0] = opd[1] = opd[2] = opd[3] = -1;
+ opd_dst_map = 0;
+ opd_src_map = 0;
+ opd_imm_map = 0;
+
+ for (opi = 0; opi < decoded[n].opcode->num_operands; opi++) {
+ const struct tilegx_operand *op = decoded[n].operands[opi];
+ opd[opi] = decoded[n].operand_values[opi];
+
+ /* Set the operands. rd, ra, rb and imm. */
+ if (opi < 3) {
+ if (op->is_dest_reg) {
+ if (rd == -1)
+ rd = decoded[n].operand_values[opi];
+ else if (ra == -1)
+ ra = decoded[n].operand_values[opi];
+ } else if (op->is_src_reg) {
+ if (ra == -1) {
+ ra = decoded[n].operand_values[opi];
+ } else if(rb == -1) {
+ rb = decoded[n].operand_values[opi];
+ } else {
+ vassert(0);
+ }
+ } else {
+ imm = decoded[n].operand_values[opi];
+ }
+ }
+
+ /* Build bit maps of used dest, source registers
+ and immediate. */
+ if (op->is_dest_reg) {
+ opd_dst_map |= 1ULL << opi;
+ if(op->is_src_reg)
+ opd_src_map |= 1ULL << opi;
+ } else if(op->is_src_reg) {
+ opd_src_map |= 1ULL << opi;
+ } else {
+ opd_imm_map |= 1ULL << opi;
+ }
+ }
+
+ use_dirty_helper = 0;
+
+ switch (opcode) {
+ case 0: /* "bpt" */ /* "raise" */
+ /* "bpt" pseudo instruction is an illegal instruction */
+ opd_imm_map |= (1 << 0);
+ opd[0] = cins;
+ use_dirty_helper = 1;
+ break;
+ case 1: /* "info" */ /* Ignore this instruction. */
+ break;
+ case 2: /* "infol" */ /* Ignore this instruction. */
+ break;
+ case 3: /* "ld4s_tls" */ /* Ignore this instruction. */
+ break;
+ case 4: /* "ld_tls" */ /* Ignore this instruction. */
+ break;
+ case 5: /* "move" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, getIReg(ra));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 6: /* "movei" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, mkU64(extend_s_8to64(imm)));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 7: /* "moveli" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, mkU64(extend_s_16to64(imm)));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 8: /* "prefetch" */ /* Ignore. */
+ break;
+ case 9: /* "prefetch_add_l1" */ /* Ignore. */
+ break;
+ case 10: /* "prefetch_add_l1_fault" */ /* Ignore. */
+ break;
+ case 11: /* "prefetch_add_l2" */ /* Ignore. */
+ break;
+ case 12: /* "prefetch_add_l2_fault" */ /* Ignore. */
+ break;
+ case 13: /* "prefetch_add_l3" */ /* Ignore. */
+ break;
+ case 14: /* "prefetch_add_l3_fault" */ /* Ignore. */
+ break;
+ case 15: /* "prefetch_l1" */ /* Ignore. */
+ break;
+ case 16: /* "prefetch_l1_fault" */ /* Ignore. */
+ break;
+ case 17: /* "prefetch_l2" */ /* Ignore. */
+ break;
+ case 18: /* "prefetch_l2_fault" */ /* Ignore. */
+ break;
+ case 19: /* "prefetch_l3" */ /* Ignore. */
+ break;
+ case 20: /* "prefetch_l3_fault" */ /* Ignore. */
+ break;
+ case 21: /* "raise" */
+ /* "raise" pseudo instruction is an illegal instruction plusing
+ a "moveli zero, <sig>", so we need save whole bundle in the
+ opd[0], which will be used in the dirty helper. */
+ opd_imm_map |= (1 << 0);
+ opd[0] = cins;
+ use_dirty_helper = 1;
+ break;
+ case 22: /* "add" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, binop(Iop_Add64, getIReg(ra), getIReg(rb)));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 23: /* "addi" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, binop(Iop_Add64, getIReg(ra),
+ mkU64(extend_s_8to64(imm))));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 24: /* "addli" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, binop(Iop_Add64, getIReg(ra),
+ mkU64(extend_s_16to64(imm))));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 25: /* "addx" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, signExtend(binop(Iop_Add32,
+ narrowTo(Ity_I32, getIReg(ra)),
+ narrowTo(Ity_I32, getIReg(rb))),
+ 32));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 26: /* "addxi" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, signExtend(binop(Iop_Add32,
+ narrowTo(Ity_I32, getIReg(ra)),
+ mkU32(imm)), 32));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 27: /* "addxli" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, signExtend(binop(Iop_Add32,
+ narrowTo(Ity_I32, getIReg(ra)),
+ mkU32(imm)), 32));
+
+ MARK_REG_WB(rd, t2);
+ break;
+ case 28: /* "addxsc" */
+ use_dirty_helper = 1;
+ break;
+ case 29: /* "and" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, binop(Iop_And64, getIReg(ra), getIReg(rb)));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 30: /* "andi" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, binop(Iop_And64, getIReg(ra),
+ mkU64(extend_s_8to64(imm))));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 31: /* "beqz" */
+ /* Fall-through */
+ case 32:
+ /* "beqzt" */
+ bstmt = dis_branch(binop(Iop_CmpEQ64, getIReg(ra), mkU64(0)),
+ imm);
+ break;
+ case 33: /* "bfexts" */
+ {
+ ULong imm0 = decoded[n].operand_values[3];
+ ULong mask = ((-1ULL) ^ ((-1ULL << ((imm0 - imm) & 63)) << 1));
+ t0 = newTemp(Ity_I64);
+ t2 = newTemp(Ity_I64);
+ assign(t0, binop(Iop_Xor64,
+ binop(Iop_Sub64,
+ binop(Iop_And64,
+ binop(Iop_Shr64,
+ getIReg(ra),
+ mkU8(imm0)),
+ mkU64(1)),
+ mkU64(1)),
+ mkU64(-1ULL)));
+ assign(t2,
+ binop(Iop_Or64,
+ binop(Iop_And64,
+ binop(Iop_Or64,
+ binop(Iop_Shr64,
+ getIReg(ra),
+ mkU8(imm)),
+ binop(Iop_Shl64,
+ getIReg(ra),
+ mkU8(64 - imm))),
+ mkU64(mask)),
+ binop(Iop_And64,
+ mkexpr(t0),
+ mkU64(~mask))));
+
+ MARK_REG_WB(rd, t2);
+ }
+ break;
+ case 34: /* "bfextu" */
+ {
+ ULong imm0 = decoded[n].operand_values[3];
+ ULong mask = 0;
+ t2 = newTemp(Ity_I64);
+ mask = ((-1ULL) ^ ((-1ULL << ((imm0 - imm) & 63)) << 1));
+
+ assign(t2,
+ binop(Iop_And64,
+ binop(Iop_Or64,
+ binop(Iop_Shr64,
+ getIReg(ra),
+ mkU8(imm)),
+ binop(Iop_Shl64,
+ getIReg(ra),
+ mkU8(64 - imm))),
+ mkU64(mask)));
+ MARK_REG_WB(rd, t2);
+ }
+ break;
+ case 35: /* "bfins" */
+ {
+ ULong mask;
+ ULong imm0 = decoded[n].operand_values[3];
+ t0 = newTemp(Ity_I64);
+ t2 = newTemp(Ity_I64);
+ if (imm <= imm0)
+ {
+ mask = ((-1ULL << imm) ^ ((-1ULL << imm0) << 1));
+ }
+ else
+ {
+ mask = ((-1ULL << imm) | (-1ULL >> (63 - imm0)));
+ }
+
+ assign(t0, binop(Iop_Or64,
+ binop(Iop_Shl64,
+ getIReg(ra),
+ mkU8(imm)),
+ binop(Iop_Shr64,
+ getIReg(ra),
+ mkU8(64 - imm))));
+
+ assign(t2, binop(Iop_Or64,
+ binop(Iop_And64,
+ mkexpr(t0),
+ mkU64(mask)),
+ binop(Iop_And64,
+ getIReg(rd),
+ mkU64(~mask))));
+
+ MARK_REG_WB(rd, t2);
+ }
+ break;
+ case 36: /* "bgez" */
+ /* Fall-through */
+ case 37: /* "bgezt" */
+ bstmt = dis_branch(binop(Iop_CmpEQ64,
+ binop(Iop_And64,
+ getIReg(ra),
+ mkU64(0x8000000000000000ULL)),
+ mkU64(0x0)),
+ imm);
+ break;
+ case 38: /* "bgtz" */
+ /* Fall-through */
+ case 39:
+ /* "bgtzt" */
+ bstmt = dis_branch(unop(Iop_Not1,
+ binop(Iop_CmpLE64S,
+ getIReg(ra),
+ mkU64(0))),
+ imm);
+ break;
+ case 40: /* "blbc" */
+ /* Fall-through */
+ case 41: /* "blbct" */
+ bstmt = dis_branch(unop(Iop_64to1,
+ unop(Iop_Not64, getIReg(ra))),
+ imm);
+
+ break;
+ case 42: /* "blbs" */
+ /* Fall-through */
+ case 43:
+ /* "blbst" */
+ bstmt = dis_branch(unop(Iop_64to1,
+ getIReg(ra)),
+ imm);
+ break;
+ case 44: /* "blez" */
+ bstmt = dis_branch(binop(Iop_CmpLE64S, getIReg(ra),
+ mkU64(0)),
+ imm);
+ break;
+ case 45: /* "blezt" */
+ bstmt = dis_branch(binop(Iop_CmpLE64S, getIReg(ra),
+ mkU64(0)),
+ imm);
+ break;
+ case 46: /* "bltz" */
+ bstmt = dis_branch(binop(Iop_CmpLT64S, getIReg(ra),
+ mkU64(0)),
+ imm);
+ break;
+ case 47: /* "bltzt" */
+ bstmt = dis_branch(binop(Iop_CmpLT64S, getIReg(ra),
+ mkU64(0)),
+ imm);
+ break;
+ case 48: /* "bnez" */
+ /* Fall-through */
+ case 49:
+ /* "bnezt" */
+ bstmt = dis_branch(binop(Iop_CmpNE64, getIReg(ra),
+ mkU64(0)),
+ imm);
+ break;
+ case 50: /* "clz" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, unop(Iop_Clz64, getIReg(ra)));
+
+ MARK_REG_WB(rd, t2);
+ break;
+ case 51: /* "cmoveqz rd, ra, rb" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, IRExpr_ITE(binop(Iop_CmpEQ64, getIReg(ra), mkU64(0)),
+ getIReg(rb), getIReg(rd)));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 52: /* "cmovnez" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, IRExpr_ITE(binop(Iop_CmpEQ64, getIReg(ra), mkU64(0)),
+ getIReg(rd), getIReg(rb)));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 53: /* "cmpeq" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, unop(Iop_1Uto64, binop(Iop_CmpEQ64,
+ getIReg(ra), getIReg(rb))));
+ MARK_REG_WB(rd, t2);
+ break;
+
+ case 54: /* "cmpeqi" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, unop(Iop_1Uto64, binop(Iop_CmpEQ64,
+ getIReg(ra),
+ mkU64(extend_s_8to64(imm)))));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 55: /* "cmpexch" */
+ t1 = newTemp(Ity_I64);
+ t2 = newTemp(Ity_I64);
+
+ assign(t1, getIReg(rb));
+ stmt( IRStmt_CAS(mkIRCAS(IRTemp_INVALID, t2, Iend_LE,
+ getIReg(ra),
+ NULL, binop(Iop_Add64,
+ getIReg(70),
+ getIReg(71)),
+ NULL, mkexpr(t1))));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 56: /* "cmpexch4" */
+ t1 = newTemp(Ity_I32);
+ t2 = newTemp(Ity_I64);
+ t3 = newTemp(Ity_I32);
+
+ assign(t1, narrowTo(Ity_I32, getIReg(rb)));
+ stmt( IRStmt_CAS(mkIRCAS(IRTemp_INVALID, t3, Iend_LE,
+ getIReg(ra),
+ NULL,
+ narrowTo(Ity_I32, binop(Iop_Add64,
+ getIReg(70),
+ getIReg(71))),
+ NULL,
+ mkexpr(t1))));
+ assign(t2, unop(Iop_32Uto64, mkexpr(t3)));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 57: /* "cmples" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, unop(Iop_1Uto64,
+ binop(Iop_CmpLE64S, getIReg(ra), getIReg(rb))));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 58: /* "cmpleu" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, unop(Iop_1Uto64,
+ binop(Iop_CmpLE64U, getIReg(ra), getIReg(rb))));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 59: /* "cmplts" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, unop(Iop_1Uto64,
+ binop(Iop_CmpLT64S, getIReg(ra), getIReg(rb))));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 60: /* "cmpltsi" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, unop(Iop_1Uto64,
+ binop(Iop_CmpLT64S,
+ getIReg(ra),
+ mkU64(extend_s_8to64(imm)))));
+ MARK_REG_WB(rd, t2);
+ break;
+ case 61:
+
+ /* "cmpltu" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, unop(Iop_1Uto64,
+ binop(Iop_CmpLT64U, getIReg(ra), getIReg(rb))));
+ MARK_REG_WB(rd, t2);
+
+
+ break;
+ case 62: /* "cmpltui" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, unop(Iop_1Uto64,
+ binop(Iop_CmpLT64U,
+ getIReg(ra),
+ mkU64(imm))));
+ MARK_REG_WB(rd, t2);
+
+
+ break;
+ case 63: /* "cmpne" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, unop(Iop_1Uto64,
+ binop(Iop_CmpNE64, getIReg(ra), getIReg(rb))));
+ MARK_REG_WB(rd, t2);
+
+
+ break;
+ case 64:
+ /* Fall-through */
+ case 65:
+ /* Fall-through */
+ case 66:
+ /* Fall-through */
+ case 67:
+ /* Fall-through */
+ case 68:
+ /* Fall-through */
+ case 69:
+ /* Fall-through */
+ case 70:
+ /* Fall-through */
+ case 71:
+ /* Fall-through */
+ case 72:
+ use_dirty_helper = 1;
+ break;
+ case 73: /* "ctz" */
+ t2 = newTemp(Ity_I64);
+ assign(t2, unop(Iop_Ctz64, getIReg(ra)));
+
+ MARK_REG_WB(rd, t2);
+
+
+ break;
+ case 74: /* "dblalign" */
+ t0 = newTemp(Ity_I64);
+ t1 = newTemp(Ity_I64);
+ t2 = newTemp(Ity_I64);
+
+ /* t0 is the bit shift amount */
+ assign(t0, binop(Iop_Shl64,
+ binop(Iop_And64,
+ getIReg(rb),
+ mkU64(7)),
+ mkU8(3)));
+ assign(t1, binop(Iop_Sub64,
+ mkU64(64),
+ mkexpr(t0)));
+
+ assign(t2, binop(Iop_Or64,
+ binop(Iop_Shl64,
+ getIReg(ra),
+ unop(Iop_64to8, mkexpr(t1))),
+ binop(Iop_Shr64,
+ ...
[truncated message content] |
|
From: Julian S. <js...@ac...> - 2015-04-10 11:15:42
|
On 10/04/15 10:44, Alex wrote: > Can someone provide a quick explanation what are the characteristics > of VG simulated CPU (cache, cores, core speed, threads)? I need > benchmark client code for different hardware with my VG tool plugin. V just provides an instruction set simulator, that is, something that can compute the architecturally-visible effects of executing each instruction. There is no attempt made to simulate any microarchitural details (caches etc) -- at least in the core. The Callgrind and Cachegrind tools do simulate that kind of thing. But that's not "core" functionality. J |
|
From: Julian S. <js...@ac...> - 2015-04-10 11:11:41
|
On 09/04/15 21:11, Philippe Waroquiers wrote: >>From my point of view, I would even say addition of a brand new OS > or brand new arch implies: > * Mandatory requirement: have a nightly build setup > * Not mandatory, but close: have an accessible machine by valgrind > developers (in gcc compile farm or similarly accessible by valdev). Yes, I agree. J |
|
From: Alex <spl...@gm...> - 2015-04-10 08:44:50
|
Can someone provide a quick explanation what are the characteristics of VG simulated CPU (cache, cores, core speed, threads)? I need benchmark client code for different hardware with my VG tool plugin. Alex. |
|
From: Ivo R. <iv...@iv...> - 2015-04-10 06:06:36
|
2015-03-17 9:32 GMT+01:00 Ivo Raisr <iv...@iv...>: > [also submitted as bug report https://bugs.kde.org/show_bug.cgi?id=345248] > > Dear Valgrind developers, > we would like to ask you to integrate support for Solaris and illumos OS > in upstream Valgrind. > I would like to solicit more code review comments for this set of patches. So far Julian Seward, Rhys Kidd and Florian Krohm posted their findings; all have been addressed. Please could you review these patches (or at least functional area you are interested in). Kind regards, I. |
|
From: Matthias S. <zz...@ge...> - 2015-04-10 04:47:59
|
Hi! I analysed why the test memcheck/tests/threadname fails on amd64. See also https://bugs.kde.org/show_bug.cgi?id=345928 On amd64 it has this on stderr: ==32123== Thread 2: ==32123== Invalid write of size 1 ==32123== at 0x40083F: bad_things (threadname.c:16) ==32123== Address 0x53e71e2 is 0 bytes after a block of size 2 alloc'd ==32123== at 0x4C28BEF: malloc (vg_replace_malloc.c:299) ==32123== by 0x40082D: bad_things (threadname.c:15) ==32123== by 0x40094E: child_fn_0 (threadname.c:61) ==32123== by 0x4E3C203: start_thread (pthread_create.c:310) ==32123== I then enabled debug and added more printf-statements: The check "if (fp_min + 256 >= fp_max)" in coregrind/m_stacktrace.c:501 is triggered here. By changing it to "if (fp_min + 128 >= fp_max)" it can be fixed. I think amd64 is having problems here because some functions do not need additional local variables but can use the redzone, so the stackframes are small. Regards Matthias |
|
From: Zhigang L. <zl...@ez...> - 2015-04-10 02:34:35
|
________________________________________ From: Philippe Waroquiers <phi...@sk...> Sent: Thursday, April 9, 2015 4:06 PM To: Florian Krohm Cc: js...@ac...; Valgrind Developers; Zhigang Liu Subject: Re: [Valgrind-developers] Linux/TileGX port: last call for comments On Thu, 2015-04-09 at 22:00 +0200, Florian Krohm wrote: > > * Not mandatory, but close: have an accessible machine by valgrind > > developers (in gcc compile farm or similarly accessible by valdev). > > > > For sure would be nice but probably not realistic. In most companies > granting external access to a machine would require an act of Congress > or something like that... Yes :). A maybe more realistic approach for such companies is to donate a machine to gcc compile farm (which also avoids the company the administration effort). I will check if we did that already. Probably not :) Philippe |